Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:09:47.495392 lava-dispatcher, installed at version: 2024.01
2 01:09:47.496251 start: 0 validate
3 01:09:47.496722 Start time: 2024-10-31 01:09:47.496693+00:00 (UTC)
4 01:09:47.497251 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:09:47.497791 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:09:47.536142 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:09:47.536673 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 01:09:47.563548 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:09:47.564191 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:09:47.595772 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:09:47.596281 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:09:47.625147 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:09:47.625935 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
14 01:09:47.659198 validate duration: 0.16
16 01:09:47.660034 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:09:47.660372 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:09:47.660756 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:09:47.661357 Not decompressing ramdisk as can be used compressed.
20 01:09:47.661794 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:09:47.662066 saving as /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/ramdisk/initrd.cpio.gz
22 01:09:47.662323 total size: 5628169 (5 MB)
23 01:09:47.702191 progress 0 % (0 MB)
24 01:09:47.706430 progress 5 % (0 MB)
25 01:09:47.710729 progress 10 % (0 MB)
26 01:09:47.714502 progress 15 % (0 MB)
27 01:09:47.718748 progress 20 % (1 MB)
28 01:09:47.722523 progress 25 % (1 MB)
29 01:09:47.726723 progress 30 % (1 MB)
30 01:09:47.730977 progress 35 % (1 MB)
31 01:09:47.734798 progress 40 % (2 MB)
32 01:09:47.738920 progress 45 % (2 MB)
33 01:09:47.742709 progress 50 % (2 MB)
34 01:09:47.746910 progress 55 % (2 MB)
35 01:09:47.751123 progress 60 % (3 MB)
36 01:09:47.754900 progress 65 % (3 MB)
37 01:09:47.759104 progress 70 % (3 MB)
38 01:09:47.762872 progress 75 % (4 MB)
39 01:09:47.767151 progress 80 % (4 MB)
40 01:09:47.770860 progress 85 % (4 MB)
41 01:09:47.775023 progress 90 % (4 MB)
42 01:09:47.779264 progress 95 % (5 MB)
43 01:09:47.782662 progress 100 % (5 MB)
44 01:09:47.783329 5 MB downloaded in 0.12 s (44.37 MB/s)
45 01:09:47.783888 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:09:47.784837 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:09:47.785131 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:09:47.785399 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:09:47.785868 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig/clang-15/kernel/Image
51 01:09:47.786132 saving as /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/kernel/Image
52 01:09:47.786347 total size: 37878272 (36 MB)
53 01:09:47.786568 No compression specified
54 01:09:47.829620 progress 0 % (0 MB)
55 01:09:47.853895 progress 5 % (1 MB)
56 01:09:47.878722 progress 10 % (3 MB)
57 01:09:47.904467 progress 15 % (5 MB)
58 01:09:47.929124 progress 20 % (7 MB)
59 01:09:47.953518 progress 25 % (9 MB)
60 01:09:47.978030 progress 30 % (10 MB)
61 01:09:48.002954 progress 35 % (12 MB)
62 01:09:48.027669 progress 40 % (14 MB)
63 01:09:48.052475 progress 45 % (16 MB)
64 01:09:48.076685 progress 50 % (18 MB)
65 01:09:48.101741 progress 55 % (19 MB)
66 01:09:48.126295 progress 60 % (21 MB)
67 01:09:48.150900 progress 65 % (23 MB)
68 01:09:48.175478 progress 70 % (25 MB)
69 01:09:48.199676 progress 75 % (27 MB)
70 01:09:48.224497 progress 80 % (28 MB)
71 01:09:48.249086 progress 85 % (30 MB)
72 01:09:48.273614 progress 90 % (32 MB)
73 01:09:48.298275 progress 95 % (34 MB)
74 01:09:48.322452 progress 100 % (36 MB)
75 01:09:48.323213 36 MB downloaded in 0.54 s (67.29 MB/s)
76 01:09:48.323712 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:09:48.324562 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:09:48.324843 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:09:48.325111 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:09:48.325592 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:09:48.325875 saving as /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:09:48.326089 total size: 54703 (0 MB)
84 01:09:48.326299 No compression specified
85 01:09:48.363215 progress 59 % (0 MB)
86 01:09:48.364078 progress 100 % (0 MB)
87 01:09:48.364655 0 MB downloaded in 0.04 s (1.35 MB/s)
88 01:09:48.365149 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:09:48.365974 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:09:48.366241 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:09:48.366503 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:09:48.366961 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:09:48.367209 saving as /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/nfsrootfs/full.rootfs.tar
95 01:09:48.367415 total size: 120894716 (115 MB)
96 01:09:48.367626 Using unxz to decompress xz
97 01:09:48.400805 progress 0 % (0 MB)
98 01:09:49.187284 progress 5 % (5 MB)
99 01:09:50.018579 progress 10 % (11 MB)
100 01:09:50.806956 progress 15 % (17 MB)
101 01:09:51.537982 progress 20 % (23 MB)
102 01:09:52.127506 progress 25 % (28 MB)
103 01:09:52.946240 progress 30 % (34 MB)
104 01:09:53.737361 progress 35 % (40 MB)
105 01:09:54.083698 progress 40 % (46 MB)
106 01:09:54.473539 progress 45 % (51 MB)
107 01:09:55.188855 progress 50 % (57 MB)
108 01:09:56.075331 progress 55 % (63 MB)
109 01:09:56.865392 progress 60 % (69 MB)
110 01:09:57.622253 progress 65 % (74 MB)
111 01:09:58.402313 progress 70 % (80 MB)
112 01:09:59.247111 progress 75 % (86 MB)
113 01:10:00.035392 progress 80 % (92 MB)
114 01:10:00.797220 progress 85 % (98 MB)
115 01:10:01.651713 progress 90 % (103 MB)
116 01:10:02.431493 progress 95 % (109 MB)
117 01:10:03.271080 progress 100 % (115 MB)
118 01:10:03.283466 115 MB downloaded in 14.92 s (7.73 MB/s)
119 01:10:03.284485 end: 1.4.1 http-download (duration 00:00:15) [common]
121 01:10:03.286279 end: 1.4 download-retry (duration 00:00:15) [common]
122 01:10:03.286857 start: 1.5 download-retry (timeout 00:09:44) [common]
123 01:10:03.287422 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 01:10:03.288342 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig/clang-15/modules.tar.xz
125 01:10:03.288852 saving as /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/modules/modules.tar
126 01:10:03.289301 total size: 11755844 (11 MB)
127 01:10:03.289758 Using unxz to decompress xz
128 01:10:03.338950 progress 0 % (0 MB)
129 01:10:03.406324 progress 5 % (0 MB)
130 01:10:03.481499 progress 10 % (1 MB)
131 01:10:03.561984 progress 15 % (1 MB)
132 01:10:03.643014 progress 20 % (2 MB)
133 01:10:03.720607 progress 25 % (2 MB)
134 01:10:03.803174 progress 30 % (3 MB)
135 01:10:03.880876 progress 35 % (3 MB)
136 01:10:03.964009 progress 40 % (4 MB)
137 01:10:04.075758 progress 45 % (5 MB)
138 01:10:04.158546 progress 50 % (5 MB)
139 01:10:04.243694 progress 55 % (6 MB)
140 01:10:04.328021 progress 60 % (6 MB)
141 01:10:04.413980 progress 65 % (7 MB)
142 01:10:04.498363 progress 70 % (7 MB)
143 01:10:04.580020 progress 75 % (8 MB)
144 01:10:04.663310 progress 80 % (9 MB)
145 01:10:04.738828 progress 85 % (9 MB)
146 01:10:04.811723 progress 90 % (10 MB)
147 01:10:04.909460 progress 95 % (10 MB)
148 01:10:05.005060 progress 100 % (11 MB)
149 01:10:05.018533 11 MB downloaded in 1.73 s (6.48 MB/s)
150 01:10:05.019393 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:10:05.021089 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:10:05.021608 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 01:10:05.022124 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 01:10:21.382156 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/915252/extract-nfsrootfs-aygyv4eq
156 01:10:21.382770 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 01:10:21.383058 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 01:10:21.383768 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj
159 01:10:21.384239 makedir: /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin
160 01:10:21.384571 makedir: /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/tests
161 01:10:21.384891 makedir: /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/results
162 01:10:21.385240 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-add-keys
163 01:10:21.385768 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-add-sources
164 01:10:21.386271 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-background-process-start
165 01:10:21.386760 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-background-process-stop
166 01:10:21.387275 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-common-functions
167 01:10:21.387771 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-echo-ipv4
168 01:10:21.388311 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-install-packages
169 01:10:21.388800 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-installed-packages
170 01:10:21.389292 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-os-build
171 01:10:21.389780 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-probe-channel
172 01:10:21.390253 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-probe-ip
173 01:10:21.390720 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-target-ip
174 01:10:21.391195 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-target-mac
175 01:10:21.391666 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-target-storage
176 01:10:21.392165 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-test-case
177 01:10:21.392646 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-test-event
178 01:10:21.393141 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-test-feedback
179 01:10:21.393629 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-test-raise
180 01:10:21.394168 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-test-reference
181 01:10:21.394650 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-test-runner
182 01:10:21.395127 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-test-set
183 01:10:21.395600 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-test-shell
184 01:10:21.396097 Updating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-add-keys (debian)
185 01:10:21.396629 Updating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-add-sources (debian)
186 01:10:21.397127 Updating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-install-packages (debian)
187 01:10:21.397617 Updating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-installed-packages (debian)
188 01:10:21.398100 Updating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/bin/lava-os-build (debian)
189 01:10:21.398526 Creating /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/environment
190 01:10:21.398909 LAVA metadata
191 01:10:21.399169 - LAVA_JOB_ID=915252
192 01:10:21.399383 - LAVA_DISPATCHER_IP=192.168.6.2
193 01:10:21.399737 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 01:10:21.400735 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 01:10:21.401051 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 01:10:21.401257 skipped lava-vland-overlay
197 01:10:21.401494 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 01:10:21.401743 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 01:10:21.401959 skipped lava-multinode-overlay
200 01:10:21.402199 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 01:10:21.402446 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 01:10:21.402691 Loading test definitions
203 01:10:21.402964 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 01:10:21.403182 Using /lava-915252 at stage 0
205 01:10:21.404293 uuid=915252_1.6.2.4.1 testdef=None
206 01:10:21.404595 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 01:10:21.404856 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 01:10:21.406398 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 01:10:21.407176 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 01:10:21.409137 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 01:10:21.409956 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 01:10:21.411764 runner path: /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/0/tests/0_timesync-off test_uuid 915252_1.6.2.4.1
215 01:10:21.412324 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 01:10:21.413131 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 01:10:21.413350 Using /lava-915252 at stage 0
219 01:10:21.413698 Fetching tests from https://github.com/kernelci/test-definitions.git
220 01:10:21.413981 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/0/tests/1_kselftest-alsa'
221 01:10:24.886604 Running '/usr/bin/git checkout kernelci.org
222 01:10:25.334147 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 01:10:25.335579 uuid=915252_1.6.2.4.5 testdef=None
224 01:10:25.335919 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 01:10:25.337549 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 01:10:25.343426 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 01:10:25.345213 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 01:10:25.353068 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 01:10:25.354884 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 01:10:25.362572 runner path: /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/0/tests/1_kselftest-alsa test_uuid 915252_1.6.2.4.5
234 01:10:25.363142 BOARD='meson-g12b-a311d-libretech-cc'
235 01:10:25.363587 BRANCH='mainline'
236 01:10:25.364058 SKIPFILE='/dev/null'
237 01:10:25.364501 SKIP_INSTALL='True'
238 01:10:25.364932 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig/clang-15/kselftest.tar.xz'
239 01:10:25.365372 TST_CASENAME=''
240 01:10:25.365805 TST_CMDFILES='alsa'
241 01:10:25.366857 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 01:10:25.368569 Creating lava-test-runner.conf files
244 01:10:25.369013 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/915252/lava-overlay-_k89twvj/lava-915252/0 for stage 0
245 01:10:25.369698 - 0_timesync-off
246 01:10:25.370185 - 1_kselftest-alsa
247 01:10:25.370857 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 01:10:25.371436 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 01:10:48.556832 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 01:10:48.557281 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 01:10:48.557546 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 01:10:48.557817 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 01:10:48.558082 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 01:10:49.169377 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 01:10:49.169839 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 01:10:49.170091 extracting modules file /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/modules/modules.tar to /var/lib/lava/dispatcher/tmp/915252/extract-nfsrootfs-aygyv4eq
257 01:10:50.523095 extracting modules file /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/modules/modules.tar to /var/lib/lava/dispatcher/tmp/915252/extract-overlay-ramdisk-84uk9n9o/ramdisk
258 01:10:51.911780 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 01:10:51.912276 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
260 01:10:51.912554 [common] Applying overlay to NFS
261 01:10:51.912770 [common] Applying overlay /var/lib/lava/dispatcher/tmp/915252/compress-overlay-r9kqzw5w/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/915252/extract-nfsrootfs-aygyv4eq
262 01:10:54.679823 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 01:10:54.680327 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 01:10:54.680611 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 01:10:54.680850 Converting downloaded kernel to a uImage
266 01:10:54.681171 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/kernel/Image /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/kernel/uImage
267 01:10:55.168758 output: Image Name:
268 01:10:55.169186 output: Created: Thu Oct 31 01:10:54 2024
269 01:10:55.169398 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 01:10:55.169605 output: Data Size: 37878272 Bytes = 36990.50 KiB = 36.12 MiB
271 01:10:55.169807 output: Load Address: 01080000
272 01:10:55.170011 output: Entry Point: 01080000
273 01:10:55.170210 output:
274 01:10:55.170545 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 01:10:55.170812 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 01:10:55.171079 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 01:10:55.171334 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 01:10:55.171588 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 01:10:55.171844 Building ramdisk /var/lib/lava/dispatcher/tmp/915252/extract-overlay-ramdisk-84uk9n9o/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/915252/extract-overlay-ramdisk-84uk9n9o/ramdisk
280 01:10:57.403434 >> 173421 blocks
281 01:11:06.082362 Adding RAMdisk u-boot header.
282 01:11:06.083026 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/915252/extract-overlay-ramdisk-84uk9n9o/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/915252/extract-overlay-ramdisk-84uk9n9o/ramdisk.cpio.gz.uboot
283 01:11:06.356626 output: Image Name:
284 01:11:06.357038 output: Created: Thu Oct 31 01:11:06 2024
285 01:11:06.357250 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 01:11:06.357456 output: Data Size: 24148867 Bytes = 23582.88 KiB = 23.03 MiB
287 01:11:06.357660 output: Load Address: 00000000
288 01:11:06.357861 output: Entry Point: 00000000
289 01:11:06.358061 output:
290 01:11:06.358712 rename /var/lib/lava/dispatcher/tmp/915252/extract-overlay-ramdisk-84uk9n9o/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/ramdisk/ramdisk.cpio.gz.uboot
291 01:11:06.359135 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 01:11:06.359420 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 01:11:06.359729 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 01:11:06.360046 No LXC device requested
295 01:11:06.360634 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 01:11:06.361221 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 01:11:06.361768 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 01:11:06.362222 Checking files for TFTP limit of 4294967296 bytes.
299 01:11:06.365202 end: 1 tftp-deploy (duration 00:01:19) [common]
300 01:11:06.365857 start: 2 uboot-action (timeout 00:05:00) [common]
301 01:11:06.366434 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 01:11:06.366982 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 01:11:06.367534 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 01:11:06.368152 Using kernel file from prepare-kernel: 915252/tftp-deploy-p8cyqr0s/kernel/uImage
305 01:11:06.368864 substitutions:
306 01:11:06.369319 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 01:11:06.369765 - {DTB_ADDR}: 0x01070000
308 01:11:06.370212 - {DTB}: 915252/tftp-deploy-p8cyqr0s/dtb/meson-g12b-a311d-libretech-cc.dtb
309 01:11:06.370657 - {INITRD}: 915252/tftp-deploy-p8cyqr0s/ramdisk/ramdisk.cpio.gz.uboot
310 01:11:06.371097 - {KERNEL_ADDR}: 0x01080000
311 01:11:06.371533 - {KERNEL}: 915252/tftp-deploy-p8cyqr0s/kernel/uImage
312 01:11:06.371967 - {LAVA_MAC}: None
313 01:11:06.372487 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/915252/extract-nfsrootfs-aygyv4eq
314 01:11:06.372932 - {NFS_SERVER_IP}: 192.168.6.2
315 01:11:06.373365 - {PRESEED_CONFIG}: None
316 01:11:06.373798 - {PRESEED_LOCAL}: None
317 01:11:06.374231 - {RAMDISK_ADDR}: 0x08000000
318 01:11:06.374657 - {RAMDISK}: 915252/tftp-deploy-p8cyqr0s/ramdisk/ramdisk.cpio.gz.uboot
319 01:11:06.375086 - {ROOT_PART}: None
320 01:11:06.375517 - {ROOT}: None
321 01:11:06.375944 - {SERVER_IP}: 192.168.6.2
322 01:11:06.376402 - {TEE_ADDR}: 0x83000000
323 01:11:06.376831 - {TEE}: None
324 01:11:06.377260 Parsed boot commands:
325 01:11:06.377674 - setenv autoload no
326 01:11:06.378097 - setenv initrd_high 0xffffffff
327 01:11:06.378524 - setenv fdt_high 0xffffffff
328 01:11:06.378946 - dhcp
329 01:11:06.379369 - setenv serverip 192.168.6.2
330 01:11:06.379798 - tftpboot 0x01080000 915252/tftp-deploy-p8cyqr0s/kernel/uImage
331 01:11:06.380258 - tftpboot 0x08000000 915252/tftp-deploy-p8cyqr0s/ramdisk/ramdisk.cpio.gz.uboot
332 01:11:06.380693 - tftpboot 0x01070000 915252/tftp-deploy-p8cyqr0s/dtb/meson-g12b-a311d-libretech-cc.dtb
333 01:11:06.381126 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/915252/extract-nfsrootfs-aygyv4eq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 01:11:06.381568 - bootm 0x01080000 0x08000000 0x01070000
335 01:11:06.382141 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 01:11:06.383789 start: 2.3 connect-device (timeout 00:05:00) [common]
338 01:11:06.384332 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 01:11:06.400922 Setting prompt string to ['lava-test: # ']
340 01:11:06.402585 end: 2.3 connect-device (duration 00:00:00) [common]
341 01:11:06.403261 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 01:11:06.403877 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 01:11:06.404551 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 01:11:06.405789 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 01:11:06.456196 >> OK - accepted request
346 01:11:06.458284 Returned 0 in 0 seconds
347 01:11:06.559517 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 01:11:06.561423 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 01:11:06.562017 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 01:11:06.562574 Setting prompt string to ['Hit any key to stop autoboot']
352 01:11:06.563073 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 01:11:06.564886 Trying 192.168.56.21...
354 01:11:06.565438 Connected to conserv1.
355 01:11:06.565885 Escape character is '^]'.
356 01:11:06.566341
357 01:11:06.566799 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 01:11:06.567263
359 01:11:18.323062 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 01:11:18.323739 bl2_stage_init 0x01
361 01:11:18.324259 bl2_stage_init 0x81
362 01:11:18.328549 hw id: 0x0000 - pwm id 0x01
363 01:11:18.329055 bl2_stage_init 0xc1
364 01:11:18.329516 bl2_stage_init 0x02
365 01:11:18.329963
366 01:11:18.334112 L0:00000000
367 01:11:18.334612 L1:20000703
368 01:11:18.335070 L2:00008067
369 01:11:18.335515 L3:14000000
370 01:11:18.336998 B2:00402000
371 01:11:18.337476 B1:e0f83180
372 01:11:18.337909
373 01:11:18.338341 TE: 58124
374 01:11:18.338770
375 01:11:18.348175 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 01:11:18.348647
377 01:11:18.349079 Board ID = 1
378 01:11:18.349505 Set A53 clk to 24M
379 01:11:18.349929 Set A73 clk to 24M
380 01:11:18.353803 Set clk81 to 24M
381 01:11:18.354274 A53 clk: 1200 MHz
382 01:11:18.354704 A73 clk: 1200 MHz
383 01:11:18.359385 CLK81: 166.6M
384 01:11:18.359900 smccc: 00012a92
385 01:11:18.364998 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 01:11:18.365453 board id: 1
387 01:11:18.373571 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 01:11:18.384250 fw parse done
389 01:11:18.390209 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 01:11:18.432870 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 01:11:18.443752 PIEI prepare done
392 01:11:18.444255 fastboot data load
393 01:11:18.444659 fastboot data verify
394 01:11:18.449472 verify result: 266
395 01:11:18.455130 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 01:11:18.455633 LPDDR4 probe
397 01:11:18.456198 ddr clk to 1584MHz
398 01:11:18.463002 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 01:11:18.500287
400 01:11:18.500832 dmc_version 0001
401 01:11:18.506977 Check phy result
402 01:11:18.512901 INFO : End of CA training
403 01:11:18.513405 INFO : End of initialization
404 01:11:18.518419 INFO : Training has run successfully!
405 01:11:18.518914 Check phy result
406 01:11:18.524176 INFO : End of initialization
407 01:11:18.524676 INFO : End of read enable training
408 01:11:18.529612 INFO : End of fine write leveling
409 01:11:18.535222 INFO : End of Write leveling coarse delay
410 01:11:18.535748 INFO : Training has run successfully!
411 01:11:18.536192 Check phy result
412 01:11:18.540885 INFO : End of initialization
413 01:11:18.541375 INFO : End of read dq deskew training
414 01:11:18.546434 INFO : End of MPR read delay center optimization
415 01:11:18.552182 INFO : End of write delay center optimization
416 01:11:18.557665 INFO : End of read delay center optimization
417 01:11:18.558166 INFO : End of max read latency training
418 01:11:18.563226 INFO : Training has run successfully!
419 01:11:18.563716 1D training succeed
420 01:11:18.572347 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 01:11:18.620055 Check phy result
422 01:11:18.620673 INFO : End of initialization
423 01:11:18.641665 INFO : End of 2D read delay Voltage center optimization
424 01:11:18.661760 INFO : End of 2D read delay Voltage center optimization
425 01:11:18.713714 INFO : End of 2D write delay Voltage center optimization
426 01:11:18.762987 INFO : End of 2D write delay Voltage center optimization
427 01:11:18.768447 INFO : Training has run successfully!
428 01:11:18.768936
429 01:11:18.769339 channel==0
430 01:11:18.774154 RxClkDly_Margin_A0==88 ps 9
431 01:11:18.774642 TxDqDly_Margin_A0==98 ps 10
432 01:11:18.779665 RxClkDly_Margin_A1==88 ps 9
433 01:11:18.780204 TxDqDly_Margin_A1==98 ps 10
434 01:11:18.780609 TrainedVREFDQ_A0==74
435 01:11:18.785271 TrainedVREFDQ_A1==74
436 01:11:18.785752 VrefDac_Margin_A0==25
437 01:11:18.786149 DeviceVref_Margin_A0==40
438 01:11:18.790922 VrefDac_Margin_A1==25
439 01:11:18.791393 DeviceVref_Margin_A1==40
440 01:11:18.791787
441 01:11:18.792220
442 01:11:18.796451 channel==1
443 01:11:18.796917 RxClkDly_Margin_A0==98 ps 10
444 01:11:18.797312 TxDqDly_Margin_A0==98 ps 10
445 01:11:18.802189 RxClkDly_Margin_A1==98 ps 10
446 01:11:18.802673 TxDqDly_Margin_A1==88 ps 9
447 01:11:18.807678 TrainedVREFDQ_A0==77
448 01:11:18.808179 TrainedVREFDQ_A1==77
449 01:11:18.808579 VrefDac_Margin_A0==22
450 01:11:18.813237 DeviceVref_Margin_A0==37
451 01:11:18.813701 VrefDac_Margin_A1==22
452 01:11:18.818911 DeviceVref_Margin_A1==37
453 01:11:18.819375
454 01:11:18.819775 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 01:11:18.824455
456 01:11:18.852402 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 01:11:18.852989 2D training succeed
458 01:11:18.858198 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 01:11:18.863666 auto size-- 65535DDR cs0 size: 2048MB
460 01:11:18.864174 DDR cs1 size: 2048MB
461 01:11:18.869250 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 01:11:18.869723 cs0 DataBus test pass
463 01:11:18.874839 cs1 DataBus test pass
464 01:11:18.875307 cs0 AddrBus test pass
465 01:11:18.875704 cs1 AddrBus test pass
466 01:11:18.876134
467 01:11:18.880440 100bdlr_step_size ps== 420
468 01:11:18.880925 result report
469 01:11:18.886201 boot times 0Enable ddr reg access
470 01:11:18.891495 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 01:11:18.904955 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 01:11:19.477135 0.0;M3 CHK:0;cm4_sp_mode 0
473 01:11:19.477746 MVN_1=0x00000000
474 01:11:19.482560 MVN_2=0x00000000
475 01:11:19.488298 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 01:11:19.488767 OPS=0x10
477 01:11:19.489186 ring efuse init
478 01:11:19.489593 chipver efuse init
479 01:11:19.493870 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 01:11:19.499471 [0.018960 Inits done]
481 01:11:19.499937 secure task start!
482 01:11:19.500397 high task start!
483 01:11:19.504029 low task start!
484 01:11:19.504488 run into bl31
485 01:11:19.510667 NOTICE: BL31: v1.3(release):4fc40b1
486 01:11:19.518464 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 01:11:19.518929 NOTICE: BL31: G12A normal boot!
488 01:11:19.543779 NOTICE: BL31: BL33 decompress pass
489 01:11:19.549493 ERROR: Error initializing runtime service opteed_fast
490 01:11:20.782452
491 01:11:20.783081
492 01:11:20.790860 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 01:11:20.791335
494 01:11:20.791753 Model: Libre Computer AML-A311D-CC Alta
495 01:11:20.999426 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 01:11:21.022751 DRAM: 2 GiB (effective 3.8 GiB)
497 01:11:21.165712 Core: 408 devices, 31 uclasses, devicetree: separate
498 01:11:21.171658 WDT: Not starting watchdog@f0d0
499 01:11:21.203824 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 01:11:21.216329 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 01:11:21.221259 ** Bad device specification mmc 0 **
502 01:11:21.231555 Card did not respond to voltage select! : -110
503 01:11:21.239255 ** Bad device specification mmc 0 **
504 01:11:21.239800 Couldn't find partition mmc 0
505 01:11:21.247552 Card did not respond to voltage select! : -110
506 01:11:21.253025 ** Bad device specification mmc 0 **
507 01:11:21.253503 Couldn't find partition mmc 0
508 01:11:21.258162 Error: could not access storage.
509 01:11:22.523650 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 01:11:22.524379 bl2_stage_init 0x01
511 01:11:22.524847 bl2_stage_init 0x81
512 01:11:22.529257 hw id: 0x0000 - pwm id 0x01
513 01:11:22.529835 bl2_stage_init 0xc1
514 01:11:22.530298 bl2_stage_init 0x02
515 01:11:22.530706
516 01:11:22.534769 L0:00000000
517 01:11:22.535296 L1:20000703
518 01:11:22.535750 L2:00008067
519 01:11:22.536308 L3:14000000
520 01:11:22.540349 B2:00402000
521 01:11:22.540835 B1:e0f83180
522 01:11:22.541234
523 01:11:22.541630 TE: 58124
524 01:11:22.542022
525 01:11:22.545854 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 01:11:22.546300
527 01:11:22.546694 Board ID = 1
528 01:11:22.551477 Set A53 clk to 24M
529 01:11:22.551923 Set A73 clk to 24M
530 01:11:22.552355 Set clk81 to 24M
531 01:11:22.557166 A53 clk: 1200 MHz
532 01:11:22.557671 A73 clk: 1200 MHz
533 01:11:22.558066 CLK81: 166.6M
534 01:11:22.558456 smccc: 00012a92
535 01:11:22.562684 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 01:11:22.568428 board id: 1
537 01:11:22.574455 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 01:11:22.584811 fw parse done
539 01:11:22.590755 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 01:11:22.633373 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 01:11:22.644421 PIEI prepare done
542 01:11:22.645023 fastboot data load
543 01:11:22.645495 fastboot data verify
544 01:11:22.649977 verify result: 266
545 01:11:22.655635 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 01:11:22.656268 LPDDR4 probe
547 01:11:22.656686 ddr clk to 1584MHz
548 01:11:22.663648 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 01:11:22.700928
550 01:11:22.701547 dmc_version 0001
551 01:11:22.707569 Check phy result
552 01:11:22.713374 INFO : End of CA training
553 01:11:22.713870 INFO : End of initialization
554 01:11:22.718984 INFO : Training has run successfully!
555 01:11:22.719466 Check phy result
556 01:11:22.724522 INFO : End of initialization
557 01:11:22.725002 INFO : End of read enable training
558 01:11:22.727866 INFO : End of fine write leveling
559 01:11:22.733414 INFO : End of Write leveling coarse delay
560 01:11:22.739077 INFO : Training has run successfully!
561 01:11:22.739556 Check phy result
562 01:11:22.739954 INFO : End of initialization
563 01:11:22.744621 INFO : End of read dq deskew training
564 01:11:22.750199 INFO : End of MPR read delay center optimization
565 01:11:22.750676 INFO : End of write delay center optimization
566 01:11:22.755787 INFO : End of read delay center optimization
567 01:11:22.761409 INFO : End of max read latency training
568 01:11:22.761884 INFO : Training has run successfully!
569 01:11:22.767029 1D training succeed
570 01:11:22.774930 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 01:11:22.820587 Check phy result
572 01:11:22.821171 INFO : End of initialization
573 01:11:22.842260 INFO : End of 2D read delay Voltage center optimization
574 01:11:22.862519 INFO : End of 2D read delay Voltage center optimization
575 01:11:22.914659 INFO : End of 2D write delay Voltage center optimization
576 01:11:22.964081 INFO : End of 2D write delay Voltage center optimization
577 01:11:22.969632 INFO : Training has run successfully!
578 01:11:22.970125
579 01:11:22.970532 channel==0
580 01:11:22.975295 RxClkDly_Margin_A0==88 ps 9
581 01:11:22.975805 TxDqDly_Margin_A0==98 ps 10
582 01:11:22.978621 RxClkDly_Margin_A1==88 ps 9
583 01:11:22.979091 TxDqDly_Margin_A1==98 ps 10
584 01:11:22.984005 TrainedVREFDQ_A0==74
585 01:11:22.984480 TrainedVREFDQ_A1==74
586 01:11:22.989588 VrefDac_Margin_A0==25
587 01:11:22.990058 DeviceVref_Margin_A0==40
588 01:11:22.990453 VrefDac_Margin_A1==23
589 01:11:22.995147 DeviceVref_Margin_A1==40
590 01:11:22.995623
591 01:11:22.996076
592 01:11:22.996528 channel==1
593 01:11:22.997066 RxClkDly_Margin_A0==98 ps 10
594 01:11:22.998572 TxDqDly_Margin_A0==98 ps 10
595 01:11:23.004270 RxClkDly_Margin_A1==88 ps 9
596 01:11:23.004800 TxDqDly_Margin_A1==88 ps 9
597 01:11:23.005220 TrainedVREFDQ_A0==77
598 01:11:23.009912 TrainedVREFDQ_A1==77
599 01:11:23.010442 VrefDac_Margin_A0==22
600 01:11:23.015425 DeviceVref_Margin_A0==37
601 01:11:23.015910 VrefDac_Margin_A1==24
602 01:11:23.016344 DeviceVref_Margin_A1==37
603 01:11:23.016743
604 01:11:23.024299 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 01:11:23.024792
606 01:11:23.052465 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 01:11:23.053068 2D training succeed
608 01:11:23.063584 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 01:11:23.064162 auto size-- 65535DDR cs0 size: 2048MB
610 01:11:23.064577 DDR cs1 size: 2048MB
611 01:11:23.069146 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 01:11:23.069619 cs0 DataBus test pass
613 01:11:23.074826 cs1 DataBus test pass
614 01:11:23.075387 cs0 AddrBus test pass
615 01:11:23.080396 cs1 AddrBus test pass
616 01:11:23.081035
617 01:11:23.081263 100bdlr_step_size ps== 420
618 01:11:23.081491 result report
619 01:11:23.085997 boot times 0Enable ddr reg access
620 01:11:23.092629 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 01:11:23.105889 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 01:11:23.678932 0.0;M3 CHK:0;cm4_sp_mode 0
623 01:11:23.679581 MVN_1=0x00000000
624 01:11:23.684279 MVN_2=0x00000000
625 01:11:23.690138 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 01:11:23.690666 OPS=0x10
627 01:11:23.691135 ring efuse init
628 01:11:23.691362 chipver efuse init
629 01:11:23.695750 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 01:11:23.701434 [0.018961 Inits done]
631 01:11:23.701949 secure task start!
632 01:11:23.702389 high task start!
633 01:11:23.705880 low task start!
634 01:11:23.706394 run into bl31
635 01:11:23.712548 NOTICE: BL31: v1.3(release):4fc40b1
636 01:11:23.720289 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 01:11:23.720769 NOTICE: BL31: G12A normal boot!
638 01:11:23.745724 NOTICE: BL31: BL33 decompress pass
639 01:11:23.751313 ERROR: Error initializing runtime service opteed_fast
640 01:11:24.984250
641 01:11:24.984920
642 01:11:24.992597 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 01:11:24.993098
644 01:11:24.993533 Model: Libre Computer AML-A311D-CC Alta
645 01:11:25.201139 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 01:11:25.224389 DRAM: 2 GiB (effective 3.8 GiB)
647 01:11:25.367492 Core: 408 devices, 31 uclasses, devicetree: separate
648 01:11:25.373411 WDT: Not starting watchdog@f0d0
649 01:11:25.406155 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 01:11:25.418107 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 01:11:25.423073 ** Bad device specification mmc 0 **
652 01:11:25.433327 Card did not respond to voltage select! : -110
653 01:11:25.441070 ** Bad device specification mmc 0 **
654 01:11:25.441591 Couldn't find partition mmc 0
655 01:11:25.449307 Card did not respond to voltage select! : -110
656 01:11:25.454840 ** Bad device specification mmc 0 **
657 01:11:25.455385 Couldn't find partition mmc 0
658 01:11:25.459870 Error: could not access storage.
659 01:11:25.803371 Net: eth0: ethernet@ff3f0000
660 01:11:25.803787 starting USB...
661 01:11:26.055229 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 01:11:26.055866 Starting the controller
663 01:11:26.062140 USB XHCI 1.10
664 01:11:27.773636 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
665 01:11:27.774300 bl2_stage_init 0x81
666 01:11:27.779186 hw id: 0x0000 - pwm id 0x01
667 01:11:27.779657 bl2_stage_init 0xc1
668 01:11:27.780123 bl2_stage_init 0x02
669 01:11:27.780535
670 01:11:27.784787 L0:00000000
671 01:11:27.785239 L1:20000703
672 01:11:27.785647 L2:00008067
673 01:11:27.786054 L3:14000000
674 01:11:27.786452 B2:00402000
675 01:11:27.790382 B1:e0f83180
676 01:11:27.790831
677 01:11:27.791241 TE: 58150
678 01:11:27.791670
679 01:11:27.796045 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 01:11:27.796579
681 01:11:27.797008 Board ID = 1
682 01:11:27.801562 Set A53 clk to 24M
683 01:11:27.802074 Set A73 clk to 24M
684 01:11:27.802513 Set clk81 to 24M
685 01:11:27.807083 A53 clk: 1200 MHz
686 01:11:27.807369 A73 clk: 1200 MHz
687 01:11:27.807685 CLK81: 166.6M
688 01:11:27.808164 smccc: 00012aab
689 01:11:27.812749 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 01:11:27.818349 board id: 1
691 01:11:27.824145 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 01:11:27.834763 fw parse done
693 01:11:27.840763 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 01:11:27.883454 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 01:11:27.894357 PIEI prepare done
696 01:11:27.894897 fastboot data load
697 01:11:27.895346 fastboot data verify
698 01:11:27.900006 verify result: 266
699 01:11:27.905634 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 01:11:27.906144 LPDDR4 probe
701 01:11:27.906603 ddr clk to 1584MHz
702 01:11:27.913517 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 01:11:27.950897
704 01:11:27.951480 dmc_version 0001
705 01:11:27.957523 Check phy result
706 01:11:27.963478 INFO : End of CA training
707 01:11:27.963954 INFO : End of initialization
708 01:11:27.969027 INFO : Training has run successfully!
709 01:11:27.969509 Check phy result
710 01:11:27.974597 INFO : End of initialization
711 01:11:27.975070 INFO : End of read enable training
712 01:11:27.980235 INFO : End of fine write leveling
713 01:11:27.985778 INFO : End of Write leveling coarse delay
714 01:11:27.986233 INFO : Training has run successfully!
715 01:11:27.986633 Check phy result
716 01:11:27.991488 INFO : End of initialization
717 01:11:27.991972 INFO : End of read dq deskew training
718 01:11:27.997068 INFO : End of MPR read delay center optimization
719 01:11:28.002576 INFO : End of write delay center optimization
720 01:11:28.008271 INFO : End of read delay center optimization
721 01:11:28.008797 INFO : End of max read latency training
722 01:11:28.013764 INFO : Training has run successfully!
723 01:11:28.014271 1D training succeed
724 01:11:28.022978 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 01:11:28.070646 Check phy result
726 01:11:28.071247 INFO : End of initialization
727 01:11:28.093192 INFO : End of 2D read delay Voltage center optimization
728 01:11:28.113336 INFO : End of 2D read delay Voltage center optimization
729 01:11:28.165599 INFO : End of 2D write delay Voltage center optimization
730 01:11:28.215046 INFO : End of 2D write delay Voltage center optimization
731 01:11:28.220641 INFO : Training has run successfully!
732 01:11:28.221128
733 01:11:28.221538 channel==0
734 01:11:28.226055 RxClkDly_Margin_A0==88 ps 9
735 01:11:28.226518 TxDqDly_Margin_A0==98 ps 10
736 01:11:28.231695 RxClkDly_Margin_A1==88 ps 9
737 01:11:28.232187 TxDqDly_Margin_A1==98 ps 10
738 01:11:28.232591 TrainedVREFDQ_A0==74
739 01:11:28.237378 TrainedVREFDQ_A1==74
740 01:11:28.237841 VrefDac_Margin_A0==24
741 01:11:28.238238 DeviceVref_Margin_A0==40
742 01:11:28.242895 VrefDac_Margin_A1==24
743 01:11:28.243349 DeviceVref_Margin_A1==40
744 01:11:28.243743
745 01:11:28.244175
746 01:11:28.248637 channel==1
747 01:11:28.249094 RxClkDly_Margin_A0==98 ps 10
748 01:11:28.249493 TxDqDly_Margin_A0==98 ps 10
749 01:11:28.254094 RxClkDly_Margin_A1==98 ps 10
750 01:11:28.254550 TxDqDly_Margin_A1==88 ps 9
751 01:11:28.259611 TrainedVREFDQ_A0==77
752 01:11:28.260093 TrainedVREFDQ_A1==77
753 01:11:28.260494 VrefDac_Margin_A0==22
754 01:11:28.265177 DeviceVref_Margin_A0==37
755 01:11:28.265626 VrefDac_Margin_A1==22
756 01:11:28.270793 DeviceVref_Margin_A1==37
757 01:11:28.271249
758 01:11:28.271645 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 01:11:28.276522
760 01:11:28.304517 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
761 01:11:28.305052 2D training succeed
762 01:11:28.310000 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 01:11:28.315621 auto size-- 65535DDR cs0 size: 2048MB
764 01:11:28.316102 DDR cs1 size: 2048MB
765 01:11:28.321211 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 01:11:28.321668 cs0 DataBus test pass
767 01:11:28.326771 cs1 DataBus test pass
768 01:11:28.327214 cs0 AddrBus test pass
769 01:11:28.327607 cs1 AddrBus test pass
770 01:11:28.328035
771 01:11:28.332552 100bdlr_step_size ps== 420
772 01:11:28.333022 result report
773 01:11:28.337997 boot times 0Enable ddr reg access
774 01:11:28.343443 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 01:11:28.356909 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 01:11:28.930670 0.0;M3 CHK:0;cm4_sp_mode 0
777 01:11:28.931312 MVN_1=0x00000000
778 01:11:28.936008 MVN_2=0x00000000
779 01:11:28.941893 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 01:11:28.942407 OPS=0x10
781 01:11:28.942812 ring efuse init
782 01:11:28.943206 chipver efuse init
783 01:11:28.947330 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 01:11:28.952929 [0.018961 Inits done]
785 01:11:28.953364 secure task start!
786 01:11:28.953753 high task start!
787 01:11:28.957542 low task start!
788 01:11:28.957977 run into bl31
789 01:11:28.964130 NOTICE: BL31: v1.3(release):4fc40b1
790 01:11:28.971935 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 01:11:28.972406 NOTICE: BL31: G12A normal boot!
792 01:11:28.997359 NOTICE: BL31: BL33 decompress pass
793 01:11:29.002944 ERROR: Error initializing runtime service opteed_fast
794 01:11:30.235855
795 01:11:30.236508
796 01:11:30.244223 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 01:11:30.244695
798 01:11:30.245119 Model: Libre Computer AML-A311D-CC Alta
799 01:11:30.452707 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 01:11:30.476083 DRAM: 2 GiB (effective 3.8 GiB)
801 01:11:30.619075 Core: 408 devices, 31 uclasses, devicetree: separate
802 01:11:30.624899 WDT: Not starting watchdog@f0d0
803 01:11:30.657146 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 01:11:30.669685 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 01:11:30.675012 ** Bad device specification mmc 0 **
806 01:11:30.684909 Card did not respond to voltage select! : -110
807 01:11:30.692575 ** Bad device specification mmc 0 **
808 01:11:30.693032 Couldn't find partition mmc 0
809 01:11:30.700902 Card did not respond to voltage select! : -110
810 01:11:30.706437 ** Bad device specification mmc 0 **
811 01:11:30.706883 Couldn't find partition mmc 0
812 01:11:30.711508 Error: could not access storage.
813 01:11:31.053928 Net: eth0: ethernet@ff3f0000
814 01:11:31.054321 starting USB...
815 01:11:31.305881 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 01:11:31.306432 Starting the controller
817 01:11:31.312635 USB XHCI 1.10
818 01:11:33.473790 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
819 01:11:33.474190 bl2_stage_init 0x81
820 01:11:33.479377 hw id: 0x0000 - pwm id 0x01
821 01:11:33.479645 bl2_stage_init 0xc1
822 01:11:33.479849 bl2_stage_init 0x02
823 01:11:33.480184
824 01:11:33.484967 L0:00000000
825 01:11:33.485233 L1:20000703
826 01:11:33.485438 L2:00008067
827 01:11:33.485637 L3:14000000
828 01:11:33.485833 B2:00402000
829 01:11:33.490643 B1:e0f83180
830 01:11:33.490908
831 01:11:33.491114 TE: 58150
832 01:11:33.491315
833 01:11:33.496187 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
834 01:11:33.496463
835 01:11:33.496668 Board ID = 1
836 01:11:33.501726 Set A53 clk to 24M
837 01:11:33.502083 Set A73 clk to 24M
838 01:11:33.502396 Set clk81 to 24M
839 01:11:33.507266 A53 clk: 1200 MHz
840 01:11:33.507629 A73 clk: 1200 MHz
841 01:11:33.507940 CLK81: 166.6M
842 01:11:33.508189 smccc: 00012aab
843 01:11:33.512886 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
844 01:11:33.518556 board id: 1
845 01:11:33.524388 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
846 01:11:33.534990 fw parse done
847 01:11:33.541091 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
848 01:11:33.583425 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
849 01:11:33.594338 PIEI prepare done
850 01:11:33.594612 fastboot data load
851 01:11:33.594825 fastboot data verify
852 01:11:33.600146 verify result: 266
853 01:11:33.605624 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
854 01:11:33.605892 LPDDR4 probe
855 01:11:33.606100 ddr clk to 1584MHz
856 01:11:33.613591 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
857 01:11:33.650892
858 01:11:33.651198 dmc_version 0001
859 01:11:33.657534 Check phy result
860 01:11:33.663396 INFO : End of CA training
861 01:11:33.663661 INFO : End of initialization
862 01:11:33.669146 INFO : Training has run successfully!
863 01:11:33.669416 Check phy result
864 01:11:33.674589 INFO : End of initialization
865 01:11:33.674854 INFO : End of read enable training
866 01:11:33.680190 INFO : End of fine write leveling
867 01:11:33.685790 INFO : End of Write leveling coarse delay
868 01:11:33.686177 INFO : Training has run successfully!
869 01:11:33.686415 Check phy result
870 01:11:33.691406 INFO : End of initialization
871 01:11:33.691680 INFO : End of read dq deskew training
872 01:11:33.697250 INFO : End of MPR read delay center optimization
873 01:11:33.702647 INFO : End of write delay center optimization
874 01:11:33.708234 INFO : End of read delay center optimization
875 01:11:33.708721 INFO : End of max read latency training
876 01:11:33.713935 INFO : Training has run successfully!
877 01:11:33.714418 1D training succeed
878 01:11:33.723023 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
879 01:11:33.769637 Check phy result
880 01:11:33.770166 INFO : End of initialization
881 01:11:33.793114 INFO : End of 2D read delay Voltage center optimization
882 01:11:33.813274 INFO : End of 2D read delay Voltage center optimization
883 01:11:33.865132 INFO : End of 2D write delay Voltage center optimization
884 01:11:33.914362 INFO : End of 2D write delay Voltage center optimization
885 01:11:33.919950 INFO : Training has run successfully!
886 01:11:33.920524
887 01:11:33.920997 channel==0
888 01:11:33.925499 RxClkDly_Margin_A0==88 ps 9
889 01:11:33.926004 TxDqDly_Margin_A0==108 ps 11
890 01:11:33.931194 RxClkDly_Margin_A1==88 ps 9
891 01:11:33.931691 TxDqDly_Margin_A1==98 ps 10
892 01:11:33.932225 TrainedVREFDQ_A0==74
893 01:11:33.936729 TrainedVREFDQ_A1==74
894 01:11:33.937284 VrefDac_Margin_A0==24
895 01:11:33.942340 DeviceVref_Margin_A0==40
896 01:11:33.942891 VrefDac_Margin_A1==25
897 01:11:33.943329 DeviceVref_Margin_A1==40
898 01:11:33.943754
899 01:11:33.944227
900 01:11:33.947943 channel==1
901 01:11:33.948460 RxClkDly_Margin_A0==98 ps 10
902 01:11:33.948890 TxDqDly_Margin_A0==98 ps 10
903 01:11:33.953483 RxClkDly_Margin_A1==88 ps 9
904 01:11:33.953963 TxDqDly_Margin_A1==88 ps 9
905 01:11:33.959224 TrainedVREFDQ_A0==77
906 01:11:33.959722 TrainedVREFDQ_A1==77
907 01:11:33.960192 VrefDac_Margin_A0==22
908 01:11:33.964697 DeviceVref_Margin_A0==37
909 01:11:33.965172 VrefDac_Margin_A1==24
910 01:11:33.970287 DeviceVref_Margin_A1==37
911 01:11:33.970777
912 01:11:33.971209 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
913 01:11:33.976048
914 01:11:34.003948 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
915 01:11:34.004546 2D training succeed
916 01:11:34.009506 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
917 01:11:34.015217 auto size-- 65535DDR cs0 size: 2048MB
918 01:11:34.015731 DDR cs1 size: 2048MB
919 01:11:34.020723 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
920 01:11:34.021228 cs0 DataBus test pass
921 01:11:34.026357 cs1 DataBus test pass
922 01:11:34.026836 cs0 AddrBus test pass
923 01:11:34.027268 cs1 AddrBus test pass
924 01:11:34.027693
925 01:11:34.031950 100bdlr_step_size ps== 420
926 01:11:34.032506 result report
927 01:11:34.037517 boot times 0Enable ddr reg access
928 01:11:34.042952 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
929 01:11:34.056414 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
930 01:11:34.628456 0.0;M3 CHK:0;cm4_sp_mode 0
931 01:11:34.629096 MVN_1=0x00000000
932 01:11:34.633881 MVN_2=0x00000000
933 01:11:34.639650 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
934 01:11:34.640223 OPS=0x10
935 01:11:34.640696 ring efuse init
936 01:11:34.641150 chipver efuse init
937 01:11:34.645239 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
938 01:11:34.650836 [0.018961 Inits done]
939 01:11:34.651357 secure task start!
940 01:11:34.651821 high task start!
941 01:11:34.655447 low task start!
942 01:11:34.655941 run into bl31
943 01:11:34.662050 NOTICE: BL31: v1.3(release):4fc40b1
944 01:11:34.669812 NOTICE: BL31: Built : 15:58:17, May 22 2019
945 01:11:34.670335 NOTICE: BL31: G12A normal boot!
946 01:11:34.695342 NOTICE: BL31: BL33 decompress pass
947 01:11:34.700908 ERROR: Error initializing runtime service opteed_fast
948 01:11:35.933824
949 01:11:35.934478
950 01:11:35.942142 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
951 01:11:35.942648
952 01:11:35.943108 Model: Libre Computer AML-A311D-CC Alta
953 01:11:36.150603 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
954 01:11:36.173972 DRAM: 2 GiB (effective 3.8 GiB)
955 01:11:36.316927 Core: 408 devices, 31 uclasses, devicetree: separate
956 01:11:36.322785 WDT: Not starting watchdog@f0d0
957 01:11:36.355059 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
958 01:11:36.367541 Loading Environment from FAT... Card did not respond to voltage select! : -110
959 01:11:36.372528 ** Bad device specification mmc 0 **
960 01:11:36.382839 Card did not respond to voltage select! : -110
961 01:11:36.390550 ** Bad device specification mmc 0 **
962 01:11:36.391042 Couldn't find partition mmc 0
963 01:11:36.398808 Card did not respond to voltage select! : -110
964 01:11:36.404490 ** Bad device specification mmc 0 **
965 01:11:36.404979 Couldn't find partition mmc 0
966 01:11:36.409412 Error: could not access storage.
967 01:11:36.751892 Net: eth0: ethernet@ff3f0000
968 01:11:36.752527 starting USB...
969 01:11:37.003713 Bus usb@ff500000: Register 3000140 NbrPorts 3
970 01:11:37.004317 Starting the controller
971 01:11:37.010697 USB XHCI 1.10
972 01:11:38.873686 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
973 01:11:38.874345 bl2_stage_init 0x01
974 01:11:38.874820 bl2_stage_init 0x81
975 01:11:38.879155 hw id: 0x0000 - pwm id 0x01
976 01:11:38.879653 bl2_stage_init 0xc1
977 01:11:38.880158 bl2_stage_init 0x02
978 01:11:38.880614
979 01:11:38.884682 L0:00000000
980 01:11:38.885161 L1:20000703
981 01:11:38.885607 L2:00008067
982 01:11:38.886043 L3:14000000
983 01:11:38.890369 B2:00402000
984 01:11:38.890847 B1:e0f83180
985 01:11:38.891291
986 01:11:38.891734 TE: 58167
987 01:11:38.892216
988 01:11:38.895923 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
989 01:11:38.896440
990 01:11:38.896887 Board ID = 1
991 01:11:38.901620 Set A53 clk to 24M
992 01:11:38.902101 Set A73 clk to 24M
993 01:11:38.902542 Set clk81 to 24M
994 01:11:38.907157 A53 clk: 1200 MHz
995 01:11:38.907631 A73 clk: 1200 MHz
996 01:11:38.908109 CLK81: 166.6M
997 01:11:38.908553 smccc: 00012abd
998 01:11:38.912658 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
999 01:11:38.918368 board id: 1
1000 01:11:38.924306 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1001 01:11:38.934922 fw parse done
1002 01:11:38.940866 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1003 01:11:38.983412 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1004 01:11:38.994306 PIEI prepare done
1005 01:11:38.994816 fastboot data load
1006 01:11:38.995250 fastboot data verify
1007 01:11:39.000028 verify result: 266
1008 01:11:39.005572 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1009 01:11:39.006045 LPDDR4 probe
1010 01:11:39.006472 ddr clk to 1584MHz
1011 01:11:39.013541 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1012 01:11:39.050770
1013 01:11:39.051270 dmc_version 0001
1014 01:11:39.057490 Check phy result
1015 01:11:39.063339 INFO : End of CA training
1016 01:11:39.063806 INFO : End of initialization
1017 01:11:39.068975 INFO : Training has run successfully!
1018 01:11:39.069516 Check phy result
1019 01:11:39.074534 INFO : End of initialization
1020 01:11:39.075028 INFO : End of read enable training
1021 01:11:39.080208 INFO : End of fine write leveling
1022 01:11:39.085777 INFO : End of Write leveling coarse delay
1023 01:11:39.086267 INFO : Training has run successfully!
1024 01:11:39.086720 Check phy result
1025 01:11:39.091389 INFO : End of initialization
1026 01:11:39.091877 INFO : End of read dq deskew training
1027 01:11:39.096967 INFO : End of MPR read delay center optimization
1028 01:11:39.102583 INFO : End of write delay center optimization
1029 01:11:39.108237 INFO : End of read delay center optimization
1030 01:11:39.108744 INFO : End of max read latency training
1031 01:11:39.113831 INFO : Training has run successfully!
1032 01:11:39.114344 1D training succeed
1033 01:11:39.123108 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1034 01:11:39.170667 Check phy result
1035 01:11:39.171207 INFO : End of initialization
1036 01:11:39.192240 INFO : End of 2D read delay Voltage center optimization
1037 01:11:39.212318 INFO : End of 2D read delay Voltage center optimization
1038 01:11:39.264250 INFO : End of 2D write delay Voltage center optimization
1039 01:11:39.313524 INFO : End of 2D write delay Voltage center optimization
1040 01:11:39.319094 INFO : Training has run successfully!
1041 01:11:39.319651
1042 01:11:39.320163 channel==0
1043 01:11:39.324662 RxClkDly_Margin_A0==88 ps 9
1044 01:11:39.325205 TxDqDly_Margin_A0==98 ps 10
1045 01:11:39.330247 RxClkDly_Margin_A1==88 ps 9
1046 01:11:39.330778 TxDqDly_Margin_A1==98 ps 10
1047 01:11:39.331265 TrainedVREFDQ_A0==74
1048 01:11:39.335823 TrainedVREFDQ_A1==74
1049 01:11:39.336384 VrefDac_Margin_A0==25
1050 01:11:39.336853 DeviceVref_Margin_A0==40
1051 01:11:39.341440 VrefDac_Margin_A1==23
1052 01:11:39.341985 DeviceVref_Margin_A1==40
1053 01:11:39.342468
1054 01:11:39.342956
1055 01:11:39.347065 channel==1
1056 01:11:39.347596 RxClkDly_Margin_A0==98 ps 10
1057 01:11:39.348104 TxDqDly_Margin_A0==98 ps 10
1058 01:11:39.352722 RxClkDly_Margin_A1==98 ps 10
1059 01:11:39.353237 TxDqDly_Margin_A1==98 ps 10
1060 01:11:39.358286 TrainedVREFDQ_A0==77
1061 01:11:39.358802 TrainedVREFDQ_A1==77
1062 01:11:39.359281 VrefDac_Margin_A0==22
1063 01:11:39.363904 DeviceVref_Margin_A0==37
1064 01:11:39.364440 VrefDac_Margin_A1==24
1065 01:11:39.369454 DeviceVref_Margin_A1==37
1066 01:11:39.370001
1067 01:11:39.370476 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1068 01:11:39.375126
1069 01:11:39.403206 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1070 01:11:39.403831 2D training succeed
1071 01:11:39.408678 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1072 01:11:39.414177 auto size-- 65535DDR cs0 size: 2048MB
1073 01:11:39.414822 DDR cs1 size: 2048MB
1074 01:11:39.419754 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1075 01:11:39.420436 cs0 DataBus test pass
1076 01:11:39.425278 cs1 DataBus test pass
1077 01:11:39.425840 cs0 AddrBus test pass
1078 01:11:39.426325 cs1 AddrBus test pass
1079 01:11:39.426792
1080 01:11:39.430927 100bdlr_step_size ps== 420
1081 01:11:39.431477 result report
1082 01:11:39.436454 boot times 0Enable ddr reg access
1083 01:11:39.441984 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1084 01:11:39.455477 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1085 01:11:40.027541 0.0;M3 CHK:0;cm4_sp_mode 0
1086 01:11:40.028205 MVN_1=0x00000000
1087 01:11:40.033024 MVN_2=0x00000000
1088 01:11:40.038772 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1089 01:11:40.039262 OPS=0x10
1090 01:11:40.039720 ring efuse init
1091 01:11:40.040201 chipver efuse init
1092 01:11:40.044376 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1093 01:11:40.050078 [0.018961 Inits done]
1094 01:11:40.050555 secure task start!
1095 01:11:40.051005 high task start!
1096 01:11:40.054549 low task start!
1097 01:11:40.055026 run into bl31
1098 01:11:40.061175 NOTICE: BL31: v1.3(release):4fc40b1
1099 01:11:40.069100 NOTICE: BL31: Built : 15:58:17, May 22 2019
1100 01:11:40.069587 NOTICE: BL31: G12A normal boot!
1101 01:11:40.094331 NOTICE: BL31: BL33 decompress pass
1102 01:11:40.100109 ERROR: Error initializing runtime service opteed_fast
1103 01:11:41.332947
1104 01:11:41.333567
1105 01:11:41.341298 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1106 01:11:41.341786
1107 01:11:41.342265 Model: Libre Computer AML-A311D-CC Alta
1108 01:11:41.549731 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1109 01:11:41.573129 DRAM: 2 GiB (effective 3.8 GiB)
1110 01:11:41.716107 Core: 408 devices, 31 uclasses, devicetree: separate
1111 01:11:41.721977 WDT: Not starting watchdog@f0d0
1112 01:11:41.754252 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1113 01:11:41.766699 Loading Environment from FAT... Card did not respond to voltage select! : -110
1114 01:11:41.771675 ** Bad device specification mmc 0 **
1115 01:11:41.781994 Card did not respond to voltage select! : -110
1116 01:11:41.789663 ** Bad device specification mmc 0 **
1117 01:11:41.790137 Couldn't find partition mmc 0
1118 01:11:41.797987 Card did not respond to voltage select! : -110
1119 01:11:41.803496 ** Bad device specification mmc 0 **
1120 01:11:41.803969 Couldn't find partition mmc 0
1121 01:11:41.808579 Error: could not access storage.
1122 01:11:42.152096 Net: eth0: ethernet@ff3f0000
1123 01:11:42.152672 starting USB...
1124 01:11:42.403891 Bus usb@ff500000: Register 3000140 NbrPorts 3
1125 01:11:42.404507 Starting the controller
1126 01:11:42.410823 USB XHCI 1.10
1127 01:11:43.965043 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1128 01:11:43.973338 scanning usb for storage devices... 0 Storage Device(s) found
1130 01:11:44.025099 Hit any key to stop autoboot: 1
1131 01:11:44.025934 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1132 01:11:44.026540 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1133 01:11:44.027038 Setting prompt string to ['=>']
1134 01:11:44.027554 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1135 01:11:44.040713 0
1136 01:11:44.041606 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1137 01:11:44.042137 Sending with 10 millisecond of delay
1139 01:11:45.176989 => setenv autoload no
1140 01:11:45.187858 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1141 01:11:45.193291 setenv autoload no
1142 01:11:45.194098 Sending with 10 millisecond of delay
1144 01:11:46.991016 => setenv initrd_high 0xffffffff
1145 01:11:47.001817 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1146 01:11:47.002703 setenv initrd_high 0xffffffff
1147 01:11:47.003462 Sending with 10 millisecond of delay
1149 01:11:48.619722 => setenv fdt_high 0xffffffff
1150 01:11:48.630542 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1151 01:11:48.631414 setenv fdt_high 0xffffffff
1152 01:11:48.632170 Sending with 10 millisecond of delay
1154 01:11:48.924056 => dhcp
1155 01:11:48.934793 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1156 01:11:48.935708 dhcp
1157 01:11:48.936272 Speed: 1000, full duplex
1158 01:11:48.936761 BOOTP broadcast 1
1159 01:11:48.943116 DHCP client bound to address 192.168.6.27 (8 ms)
1160 01:11:48.943898 Sending with 10 millisecond of delay
1162 01:11:50.620599 => setenv serverip 192.168.6.2
1163 01:11:50.631443 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1164 01:11:50.632454 setenv serverip 192.168.6.2
1165 01:11:50.633221 Sending with 10 millisecond of delay
1167 01:11:54.357458 => tftpboot 0x01080000 915252/tftp-deploy-p8cyqr0s/kernel/uImage
1168 01:11:54.368297 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1169 01:11:54.369284 tftpboot 0x01080000 915252/tftp-deploy-p8cyqr0s/kernel/uImage
1170 01:11:54.369815 Speed: 1000, full duplex
1171 01:11:54.370308 Using ethernet@ff3f0000 device
1172 01:11:54.371498 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1173 01:11:54.376839 Filename '915252/tftp-deploy-p8cyqr0s/kernel/uImage'.
1174 01:11:54.380605 Load address: 0x1080000
1175 01:11:56.880335 Loading: *################################################## 36.1 MiB
1176 01:11:56.880973 14.4 MiB/s
1177 01:11:56.881432 done
1178 01:11:56.884615 Bytes transferred = 37878336 (241fa40 hex)
1179 01:11:56.885398 Sending with 10 millisecond of delay
1181 01:12:01.570605 => tftpboot 0x08000000 915252/tftp-deploy-p8cyqr0s/ramdisk/ramdisk.cpio.gz.uboot
1182 01:12:01.581370 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1183 01:12:01.582260 tftpboot 0x08000000 915252/tftp-deploy-p8cyqr0s/ramdisk/ramdisk.cpio.gz.uboot
1184 01:12:01.582708 Speed: 1000, full duplex
1185 01:12:01.583124 Using ethernet@ff3f0000 device
1186 01:12:01.584289 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1187 01:12:01.596078 Filename '915252/tftp-deploy-p8cyqr0s/ramdisk/ramdisk.cpio.gz.uboot'.
1188 01:12:01.596579 Load address: 0x8000000
1189 01:12:08.500595 Loading: *############################T ##################### UDP wrong checksum 00000005 0000ca5a
1190 01:12:13.500922 T UDP wrong checksum 00000005 0000ca5a
1191 01:12:23.504155 T T UDP wrong checksum 00000005 0000ca5a
1192 01:12:43.508344 T T T T UDP wrong checksum 00000005 0000ca5a
1193 01:12:58.512403 T T
1194 01:12:58.513058 Retry count exceeded; starting again
1196 01:12:58.514641 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1199 01:12:58.516664 end: 2.4 uboot-commands (duration 00:01:52) [common]
1201 01:12:58.518030 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1203 01:12:58.519032 end: 2 uboot-action (duration 00:01:52) [common]
1205 01:12:58.520571 Cleaning after the job
1206 01:12:58.521115 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/ramdisk
1207 01:12:58.522527 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/kernel
1208 01:12:58.561078 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/dtb
1209 01:12:58.562353 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/nfsrootfs
1210 01:12:58.728510 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915252/tftp-deploy-p8cyqr0s/modules
1211 01:12:58.749663 start: 4.1 power-off (timeout 00:00:30) [common]
1212 01:12:58.750329 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1213 01:12:58.783232 >> OK - accepted request
1214 01:12:58.785055 Returned 0 in 0 seconds
1215 01:12:58.885765 end: 4.1 power-off (duration 00:00:00) [common]
1217 01:12:58.886668 start: 4.2 read-feedback (timeout 00:10:00) [common]
1218 01:12:58.887314 Listened to connection for namespace 'common' for up to 1s
1219 01:12:59.887715 Finalising connection for namespace 'common'
1220 01:12:59.888210 Disconnecting from shell: Finalise
1221 01:12:59.888497 =>
1222 01:12:59.989162 end: 4.2 read-feedback (duration 00:00:01) [common]
1223 01:12:59.989738 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/915252
1224 01:13:03.183052 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/915252
1225 01:13:03.183667 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.