Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 00:12:05.534970 lava-dispatcher, installed at version: 2024.01
2 00:12:05.535793 start: 0 validate
3 00:12:05.536303 Start time: 2024-10-31 00:12:05.536271+00:00 (UTC)
4 00:12:05.536865 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:12:05.537432 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:12:05.577174 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:12:05.577726 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 00:12:05.608226 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:12:05.608923 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 00:12:05.646476 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:12:05.647037 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:12:05.681144 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 00:12:05.681655 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc5-63-g0fc810ae3ae11%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
14 00:12:05.722887 validate duration: 0.19
16 00:12:05.723740 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:12:05.724076 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:12:05.724382 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:12:05.724946 Not decompressing ramdisk as can be used compressed.
20 00:12:05.725397 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 00:12:05.725669 saving as /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/ramdisk/initrd.cpio.gz
22 00:12:05.725931 total size: 5628140 (5 MB)
23 00:12:05.766031 progress 0 % (0 MB)
24 00:12:05.773875 progress 5 % (0 MB)
25 00:12:05.782075 progress 10 % (0 MB)
26 00:12:05.788835 progress 15 % (0 MB)
27 00:12:05.793096 progress 20 % (1 MB)
28 00:12:05.796831 progress 25 % (1 MB)
29 00:12:05.800996 progress 30 % (1 MB)
30 00:12:05.805307 progress 35 % (1 MB)
31 00:12:05.809149 progress 40 % (2 MB)
32 00:12:05.813340 progress 45 % (2 MB)
33 00:12:05.817110 progress 50 % (2 MB)
34 00:12:05.821253 progress 55 % (2 MB)
35 00:12:05.825442 progress 60 % (3 MB)
36 00:12:05.829312 progress 65 % (3 MB)
37 00:12:05.833389 progress 70 % (3 MB)
38 00:12:05.837106 progress 75 % (4 MB)
39 00:12:05.841161 progress 80 % (4 MB)
40 00:12:05.844884 progress 85 % (4 MB)
41 00:12:05.849052 progress 90 % (4 MB)
42 00:12:05.853055 progress 95 % (5 MB)
43 00:12:05.856463 progress 100 % (5 MB)
44 00:12:05.857108 5 MB downloaded in 0.13 s (40.92 MB/s)
45 00:12:05.857651 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:12:05.858530 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:12:05.858820 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:12:05.859091 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:12:05.859547 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig/clang-15/kernel/Image
51 00:12:05.859789 saving as /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/kernel/Image
52 00:12:05.860028 total size: 37878272 (36 MB)
53 00:12:05.860244 No compression specified
54 00:12:05.899232 progress 0 % (0 MB)
55 00:12:05.922457 progress 5 % (1 MB)
56 00:12:05.945808 progress 10 % (3 MB)
57 00:12:05.969641 progress 15 % (5 MB)
58 00:12:05.992748 progress 20 % (7 MB)
59 00:12:06.015500 progress 25 % (9 MB)
60 00:12:06.038650 progress 30 % (10 MB)
61 00:12:06.061947 progress 35 % (12 MB)
62 00:12:06.085156 progress 40 % (14 MB)
63 00:12:06.108288 progress 45 % (16 MB)
64 00:12:06.130783 progress 50 % (18 MB)
65 00:12:06.153900 progress 55 % (19 MB)
66 00:12:06.176894 progress 60 % (21 MB)
67 00:12:06.200257 progress 65 % (23 MB)
68 00:12:06.223560 progress 70 % (25 MB)
69 00:12:06.246265 progress 75 % (27 MB)
70 00:12:06.269934 progress 80 % (28 MB)
71 00:12:06.293405 progress 85 % (30 MB)
72 00:12:06.316726 progress 90 % (32 MB)
73 00:12:06.340109 progress 95 % (34 MB)
74 00:12:06.363053 progress 100 % (36 MB)
75 00:12:06.363857 36 MB downloaded in 0.50 s (71.70 MB/s)
76 00:12:06.364372 end: 1.2.1 http-download (duration 00:00:01) [common]
78 00:12:06.365181 end: 1.2 download-retry (duration 00:00:01) [common]
79 00:12:06.365454 start: 1.3 download-retry (timeout 00:09:59) [common]
80 00:12:06.365721 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 00:12:06.366313 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 00:12:06.366605 saving as /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/dtb/meson-g12b-a311d-libretech-cc.dtb
83 00:12:06.366817 total size: 54703 (0 MB)
84 00:12:06.367026 No compression specified
85 00:12:06.409657 progress 59 % (0 MB)
86 00:12:06.410503 progress 100 % (0 MB)
87 00:12:06.411033 0 MB downloaded in 0.04 s (1.18 MB/s)
88 00:12:06.411489 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:12:06.412341 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:12:06.412607 start: 1.4 download-retry (timeout 00:09:59) [common]
92 00:12:06.412872 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 00:12:06.413353 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 00:12:06.413595 saving as /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/nfsrootfs/full.rootfs.tar
95 00:12:06.413798 total size: 474398908 (452 MB)
96 00:12:06.414009 Using unxz to decompress xz
97 00:12:06.454558 progress 0 % (0 MB)
98 00:12:07.549672 progress 5 % (22 MB)
99 00:12:08.981835 progress 10 % (45 MB)
100 00:12:09.433317 progress 15 % (67 MB)
101 00:12:10.203127 progress 20 % (90 MB)
102 00:12:10.727068 progress 25 % (113 MB)
103 00:12:11.087137 progress 30 % (135 MB)
104 00:12:11.691406 progress 35 % (158 MB)
105 00:12:12.555277 progress 40 % (181 MB)
106 00:12:13.460357 progress 45 % (203 MB)
107 00:12:14.208495 progress 50 % (226 MB)
108 00:12:14.838964 progress 55 % (248 MB)
109 00:12:16.038991 progress 60 % (271 MB)
110 00:12:17.484114 progress 65 % (294 MB)
111 00:12:19.051250 progress 70 % (316 MB)
112 00:12:22.109163 progress 75 % (339 MB)
113 00:12:24.529869 progress 80 % (361 MB)
114 00:12:27.417514 progress 85 % (384 MB)
115 00:12:30.592870 progress 90 % (407 MB)
116 00:12:33.771692 progress 95 % (429 MB)
117 00:12:36.900163 progress 100 % (452 MB)
118 00:12:36.913207 452 MB downloaded in 30.50 s (14.83 MB/s)
119 00:12:36.914157 end: 1.4.1 http-download (duration 00:00:31) [common]
121 00:12:36.915803 end: 1.4 download-retry (duration 00:00:31) [common]
122 00:12:36.916393 start: 1.5 download-retry (timeout 00:09:29) [common]
123 00:12:36.916925 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 00:12:36.917938 downloading http://storage.kernelci.org/mainline/master/v6.12-rc5-63-g0fc810ae3ae11/arm64/defconfig/clang-15/modules.tar.xz
125 00:12:36.918455 saving as /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/modules/modules.tar
126 00:12:36.918878 total size: 11755844 (11 MB)
127 00:12:36.919308 Using unxz to decompress xz
128 00:12:36.964394 progress 0 % (0 MB)
129 00:12:37.032670 progress 5 % (0 MB)
130 00:12:37.112178 progress 10 % (1 MB)
131 00:12:37.195296 progress 15 % (1 MB)
132 00:12:37.277867 progress 20 % (2 MB)
133 00:12:37.356725 progress 25 % (2 MB)
134 00:12:37.438466 progress 30 % (3 MB)
135 00:12:37.516236 progress 35 % (3 MB)
136 00:12:37.598781 progress 40 % (4 MB)
137 00:12:37.685313 progress 45 % (5 MB)
138 00:12:37.767774 progress 50 % (5 MB)
139 00:12:37.852054 progress 55 % (6 MB)
140 00:12:37.935175 progress 60 % (6 MB)
141 00:12:38.020039 progress 65 % (7 MB)
142 00:12:38.102903 progress 70 % (7 MB)
143 00:12:38.185256 progress 75 % (8 MB)
144 00:12:38.269585 progress 80 % (9 MB)
145 00:12:38.344812 progress 85 % (9 MB)
146 00:12:38.417541 progress 90 % (10 MB)
147 00:12:38.514826 progress 95 % (10 MB)
148 00:12:38.611329 progress 100 % (11 MB)
149 00:12:38.624837 11 MB downloaded in 1.71 s (6.57 MB/s)
150 00:12:38.625788 end: 1.5.1 http-download (duration 00:00:02) [common]
152 00:12:38.627376 end: 1.5 download-retry (duration 00:00:02) [common]
153 00:12:38.627891 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 00:12:38.628466 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 00:12:53.920574 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/915212/extract-nfsrootfs-0xcout0m
156 00:12:53.921173 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 00:12:53.921459 start: 1.6.2 lava-overlay (timeout 00:09:12) [common]
158 00:12:53.922168 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu
159 00:12:53.922608 makedir: /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin
160 00:12:53.922927 makedir: /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/tests
161 00:12:53.923237 makedir: /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/results
162 00:12:53.923561 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-add-keys
163 00:12:53.924112 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-add-sources
164 00:12:53.924650 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-background-process-start
165 00:12:53.925182 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-background-process-stop
166 00:12:53.925704 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-common-functions
167 00:12:53.926196 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-echo-ipv4
168 00:12:53.926670 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-install-packages
169 00:12:53.927149 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-installed-packages
170 00:12:53.927616 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-os-build
171 00:12:53.928112 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-probe-channel
172 00:12:53.928628 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-probe-ip
173 00:12:53.929162 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-target-ip
174 00:12:53.929643 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-target-mac
175 00:12:53.930112 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-target-storage
176 00:12:53.930582 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-test-case
177 00:12:53.931052 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-test-event
178 00:12:53.931512 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-test-feedback
179 00:12:53.932062 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-test-raise
180 00:12:53.932553 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-test-reference
181 00:12:53.933026 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-test-runner
182 00:12:53.933497 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-test-set
183 00:12:53.933958 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-test-shell
184 00:12:53.934427 Updating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-install-packages (oe)
185 00:12:53.934946 Updating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/bin/lava-installed-packages (oe)
186 00:12:53.935371 Creating /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/environment
187 00:12:53.935730 LAVA metadata
188 00:12:53.936002 - LAVA_JOB_ID=915212
189 00:12:53.936218 - LAVA_DISPATCHER_IP=192.168.6.2
190 00:12:53.936567 start: 1.6.2.1 ssh-authorize (timeout 00:09:12) [common]
191 00:12:53.937496 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 00:12:53.937800 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:12) [common]
193 00:12:53.938007 skipped lava-vland-overlay
194 00:12:53.938246 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 00:12:53.938499 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:12) [common]
196 00:12:53.938714 skipped lava-multinode-overlay
197 00:12:53.938953 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 00:12:53.939200 start: 1.6.2.4 test-definition (timeout 00:09:12) [common]
199 00:12:53.939442 Loading test definitions
200 00:12:53.939714 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:12) [common]
201 00:12:53.939929 Using /lava-915212 at stage 0
202 00:12:53.941116 uuid=915212_1.6.2.4.1 testdef=None
203 00:12:53.941414 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 00:12:53.941674 start: 1.6.2.4.2 test-overlay (timeout 00:09:12) [common]
205 00:12:53.943354 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 00:12:53.944169 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:12) [common]
208 00:12:53.946286 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 00:12:53.947107 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:12) [common]
211 00:12:53.949179 runner path: /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 915212_1.6.2.4.1
212 00:12:53.949743 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 00:12:53.950491 Creating lava-test-runner.conf files
215 00:12:53.950689 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/915212/lava-overlay-kmrgr2hu/lava-915212/0 for stage 0
216 00:12:53.951014 - 0_v4l2-decoder-conformance-vp9
217 00:12:53.951344 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 00:12:53.951614 start: 1.6.2.5 compress-overlay (timeout 00:09:12) [common]
219 00:12:53.972922 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 00:12:53.973266 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:12) [common]
221 00:12:53.973520 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 00:12:53.973780 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 00:12:53.974040 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:12) [common]
224 00:12:54.599335 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 00:12:54.599799 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 00:12:54.600085 extracting modules file /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/915212/extract-nfsrootfs-0xcout0m
227 00:12:55.948051 extracting modules file /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/915212/extract-overlay-ramdisk-dyik7t_1/ramdisk
228 00:12:57.333577 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 00:12:57.334033 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 00:12:57.334306 [common] Applying overlay to NFS
231 00:12:57.334520 [common] Applying overlay /var/lib/lava/dispatcher/tmp/915212/compress-overlay-34o5e_b2/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/915212/extract-nfsrootfs-0xcout0m
232 00:12:57.363283 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 00:12:57.363632 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 00:12:57.363901 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 00:12:57.364164 Converting downloaded kernel to a uImage
236 00:12:57.364464 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/kernel/Image /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/kernel/uImage
237 00:12:57.773302 output: Image Name:
238 00:12:57.773693 output: Created: Thu Oct 31 00:12:57 2024
239 00:12:57.773905 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 00:12:57.774107 output: Data Size: 37878272 Bytes = 36990.50 KiB = 36.12 MiB
241 00:12:57.774309 output: Load Address: 01080000
242 00:12:57.774506 output: Entry Point: 01080000
243 00:12:57.774704 output:
244 00:12:57.775036 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 00:12:57.775303 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 00:12:57.775573 start: 1.6.7 configure-preseed-file (timeout 00:09:08) [common]
247 00:12:57.775826 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 00:12:57.776127 start: 1.6.8 compress-ramdisk (timeout 00:09:08) [common]
249 00:12:57.776387 Building ramdisk /var/lib/lava/dispatcher/tmp/915212/extract-overlay-ramdisk-dyik7t_1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/915212/extract-overlay-ramdisk-dyik7t_1/ramdisk
250 00:13:00.426157 >> 173421 blocks
251 00:13:08.169637 Adding RAMdisk u-boot header.
252 00:13:08.170307 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/915212/extract-overlay-ramdisk-dyik7t_1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/915212/extract-overlay-ramdisk-dyik7t_1/ramdisk.cpio.gz.uboot
253 00:13:08.422039 output: Image Name:
254 00:13:08.422470 output: Created: Thu Oct 31 00:13:08 2024
255 00:13:08.422903 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 00:13:08.423321 output: Data Size: 24149603 Bytes = 23583.60 KiB = 23.03 MiB
257 00:13:08.423730 output: Load Address: 00000000
258 00:13:08.424376 output: Entry Point: 00000000
259 00:13:08.424860 output:
260 00:13:08.425996 rename /var/lib/lava/dispatcher/tmp/915212/extract-overlay-ramdisk-dyik7t_1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/ramdisk/ramdisk.cpio.gz.uboot
261 00:13:08.426746 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 00:13:08.427321 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 00:13:08.427879 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 00:13:08.428447 No LXC device requested
265 00:13:08.428994 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 00:13:08.429534 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 00:13:08.430054 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 00:13:08.430486 Checking files for TFTP limit of 4294967296 bytes.
269 00:13:08.433204 end: 1 tftp-deploy (duration 00:01:03) [common]
270 00:13:08.433811 start: 2 uboot-action (timeout 00:05:00) [common]
271 00:13:08.434366 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 00:13:08.434886 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 00:13:08.435407 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 00:13:08.435953 Using kernel file from prepare-kernel: 915212/tftp-deploy-bvzy0tdv/kernel/uImage
275 00:13:08.436644 substitutions:
276 00:13:08.437075 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 00:13:08.437490 - {DTB_ADDR}: 0x01070000
278 00:13:08.437895 - {DTB}: 915212/tftp-deploy-bvzy0tdv/dtb/meson-g12b-a311d-libretech-cc.dtb
279 00:13:08.438301 - {INITRD}: 915212/tftp-deploy-bvzy0tdv/ramdisk/ramdisk.cpio.gz.uboot
280 00:13:08.438701 - {KERNEL_ADDR}: 0x01080000
281 00:13:08.439099 - {KERNEL}: 915212/tftp-deploy-bvzy0tdv/kernel/uImage
282 00:13:08.439500 - {LAVA_MAC}: None
283 00:13:08.439939 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/915212/extract-nfsrootfs-0xcout0m
284 00:13:08.440387 - {NFS_SERVER_IP}: 192.168.6.2
285 00:13:08.440792 - {PRESEED_CONFIG}: None
286 00:13:08.441187 - {PRESEED_LOCAL}: None
287 00:13:08.441580 - {RAMDISK_ADDR}: 0x08000000
288 00:13:08.441971 - {RAMDISK}: 915212/tftp-deploy-bvzy0tdv/ramdisk/ramdisk.cpio.gz.uboot
289 00:13:08.442364 - {ROOT_PART}: None
290 00:13:08.442756 - {ROOT}: None
291 00:13:08.443147 - {SERVER_IP}: 192.168.6.2
292 00:13:08.443538 - {TEE_ADDR}: 0x83000000
293 00:13:08.443928 - {TEE}: None
294 00:13:08.444353 Parsed boot commands:
295 00:13:08.444742 - setenv autoload no
296 00:13:08.445135 - setenv initrd_high 0xffffffff
297 00:13:08.445523 - setenv fdt_high 0xffffffff
298 00:13:08.445913 - dhcp
299 00:13:08.446306 - setenv serverip 192.168.6.2
300 00:13:08.446697 - tftpboot 0x01080000 915212/tftp-deploy-bvzy0tdv/kernel/uImage
301 00:13:08.447088 - tftpboot 0x08000000 915212/tftp-deploy-bvzy0tdv/ramdisk/ramdisk.cpio.gz.uboot
302 00:13:08.447478 - tftpboot 0x01070000 915212/tftp-deploy-bvzy0tdv/dtb/meson-g12b-a311d-libretech-cc.dtb
303 00:13:08.447870 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/915212/extract-nfsrootfs-0xcout0m,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 00:13:08.448311 - bootm 0x01080000 0x08000000 0x01070000
305 00:13:08.448831 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 00:13:08.450355 start: 2.3 connect-device (timeout 00:05:00) [common]
308 00:13:08.450853 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 00:13:08.465755 Setting prompt string to ['lava-test: # ']
310 00:13:08.467258 end: 2.3 connect-device (duration 00:00:00) [common]
311 00:13:08.467899 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 00:13:08.468531 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 00:13:08.469101 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 00:13:08.470288 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 00:13:08.507072 >> OK - accepted request
316 00:13:08.509208 Returned 0 in 0 seconds
317 00:13:08.610332 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 00:13:08.612029 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 00:13:08.612646 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 00:13:08.613187 Setting prompt string to ['Hit any key to stop autoboot']
322 00:13:08.613667 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 00:13:08.615254 Trying 192.168.56.21...
324 00:13:08.615766 Connected to conserv1.
325 00:13:08.616233 Escape character is '^]'.
326 00:13:08.616666
327 00:13:08.617099 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 00:13:08.617533
329 00:13:20.411806 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
330 00:13:20.412484 bl2_stage_init 0x81
331 00:13:20.417292 hw id: 0x0000 - pwm id 0x01
332 00:13:20.417825 bl2_stage_init 0xc1
333 00:13:20.418286 bl2_stage_init 0x02
334 00:13:20.418716
335 00:13:20.422853 L0:00000000
336 00:13:20.423329 L1:20000703
337 00:13:20.423772 L2:00008067
338 00:13:20.424245 L3:14000000
339 00:13:20.424673 B2:00402000
340 00:13:20.425642 B1:e0f83180
341 00:13:20.426109
342 00:13:20.426541 TE: 58150
343 00:13:20.426973
344 00:13:20.436894 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
345 00:13:20.437420
346 00:13:20.437855 Board ID = 1
347 00:13:20.438306 Set A53 clk to 24M
348 00:13:20.438775 Set A73 clk to 24M
349 00:13:20.442473 Set clk81 to 24M
350 00:13:20.442987 A53 clk: 1200 MHz
351 00:13:20.443465 A73 clk: 1200 MHz
352 00:13:20.448092 CLK81: 166.6M
353 00:13:20.448598 smccc: 00012aac
354 00:13:20.453642 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
355 00:13:20.454113 board id: 1
356 00:13:20.462294 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
357 00:13:20.472886 fw parse done
358 00:13:20.478878 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
359 00:13:20.520611 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
360 00:13:20.532402 PIEI prepare done
361 00:13:20.532927 fastboot data load
362 00:13:20.533371 fastboot data verify
363 00:13:20.538134 verify result: 266
364 00:13:20.543807 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
365 00:13:20.544534 LPDDR4 probe
366 00:13:20.545020 ddr clk to 1584MHz
367 00:13:20.551709 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
368 00:13:20.588586
369 00:13:20.589105 dmc_version 0001
370 00:13:20.594610 Check phy result
371 00:13:20.601509 INFO : End of CA training
372 00:13:20.601980 INFO : End of initialization
373 00:13:20.607090 INFO : Training has run successfully!
374 00:13:20.607568 Check phy result
375 00:13:20.612729 INFO : End of initialization
376 00:13:20.613206 INFO : End of read enable training
377 00:13:20.616013 INFO : End of fine write leveling
378 00:13:20.621460 INFO : End of Write leveling coarse delay
379 00:13:20.627114 INFO : Training has run successfully!
380 00:13:20.627585 Check phy result
381 00:13:20.628045 INFO : End of initialization
382 00:13:20.632658 INFO : End of read dq deskew training
383 00:13:20.638283 INFO : End of MPR read delay center optimization
384 00:13:20.638755 INFO : End of write delay center optimization
385 00:13:20.643891 INFO : End of read delay center optimization
386 00:13:20.649471 INFO : End of max read latency training
387 00:13:20.649948 INFO : Training has run successfully!
388 00:13:20.655156 1D training succeed
389 00:13:20.661089 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 00:13:20.708760 Check phy result
391 00:13:20.709252 INFO : End of initialization
392 00:13:20.729514 INFO : End of 2D read delay Voltage center optimization
393 00:13:20.749649 INFO : End of 2D read delay Voltage center optimization
394 00:13:20.802652 INFO : End of 2D write delay Voltage center optimization
395 00:13:20.851957 INFO : End of 2D write delay Voltage center optimization
396 00:13:20.857555 INFO : Training has run successfully!
397 00:13:20.858035
398 00:13:20.858471 channel==0
399 00:13:20.863185 RxClkDly_Margin_A0==88 ps 9
400 00:13:20.863670 TxDqDly_Margin_A0==98 ps 10
401 00:13:20.868734 RxClkDly_Margin_A1==88 ps 9
402 00:13:20.869206 TxDqDly_Margin_A1==98 ps 10
403 00:13:20.869641 TrainedVREFDQ_A0==74
404 00:13:20.874358 TrainedVREFDQ_A1==74
405 00:13:20.874827 VrefDac_Margin_A0==25
406 00:13:20.875262 DeviceVref_Margin_A0==40
407 00:13:20.879946 VrefDac_Margin_A1==25
408 00:13:20.880447 DeviceVref_Margin_A1==40
409 00:13:20.880881
410 00:13:20.881316
411 00:13:20.885537 channel==1
412 00:13:20.886010 RxClkDly_Margin_A0==98 ps 10
413 00:13:20.886446 TxDqDly_Margin_A0==88 ps 9
414 00:13:20.891160 RxClkDly_Margin_A1==88 ps 9
415 00:13:20.891628 TxDqDly_Margin_A1==88 ps 9
416 00:13:20.896753 TrainedVREFDQ_A0==76
417 00:13:20.897228 TrainedVREFDQ_A1==77
418 00:13:20.897664 VrefDac_Margin_A0==22
419 00:13:20.902444 DeviceVref_Margin_A0==38
420 00:13:20.902914 VrefDac_Margin_A1==24
421 00:13:20.907952 DeviceVref_Margin_A1==37
422 00:13:20.908446
423 00:13:20.908882 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
424 00:13:20.909313
425 00:13:20.941590 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
426 00:13:20.942171 2D training succeed
427 00:13:20.947236 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
428 00:13:20.952891 auto size-- 65535DDR cs0 size: 2048MB
429 00:13:20.953402 DDR cs1 size: 2048MB
430 00:13:20.958460 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
431 00:13:20.958956 cs0 DataBus test pass
432 00:13:20.964022 cs1 DataBus test pass
433 00:13:20.964510 cs0 AddrBus test pass
434 00:13:20.964943 cs1 AddrBus test pass
435 00:13:20.965375
436 00:13:20.969608 100bdlr_step_size ps== 420
437 00:13:20.970092 result report
438 00:13:20.975211 boot times 0Enable ddr reg access
439 00:13:20.980416 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
440 00:13:20.993896 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
441 00:13:21.567067 0.0;M3 CHK:0;cm4_sp_mode 0
442 00:13:21.567489 MVN_1=0x00000000
443 00:13:21.572488 MVN_2=0x00000000
444 00:13:21.578514 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
445 00:13:21.578963 OPS=0x10
446 00:13:21.579305 ring efuse init
447 00:13:21.579547 chipver efuse init
448 00:13:21.586498 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
449 00:13:21.586830 [0.018960 Inits done]
450 00:13:21.593981 secure task start!
451 00:13:21.594310 high task start!
452 00:13:21.594530 low task start!
453 00:13:21.594741 run into bl31
454 00:13:21.600606 NOTICE: BL31: v1.3(release):4fc40b1
455 00:13:21.608507 NOTICE: BL31: Built : 15:58:17, May 22 2019
456 00:13:21.608939 NOTICE: BL31: G12A normal boot!
457 00:13:21.633802 NOTICE: BL31: BL33 decompress pass
458 00:13:21.639627 ERROR: Error initializing runtime service opteed_fast
459 00:13:22.872498
460 00:13:22.872938
461 00:13:22.880953 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
462 00:13:22.881395
463 00:13:22.881653 Model: Libre Computer AML-A311D-CC Alta
464 00:13:23.100301 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
465 00:13:23.137059 DRAM: 2 GiB (effective 3.8 GiB)
466 00:13:23.255710 Core: 408 devices, 31 uclasses, devicetree: separate
467 00:13:23.261530 WDT: Not starting watchdog@f0d0
468 00:13:23.293732 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
469 00:13:23.306250 Loading Environment from FAT... Card did not respond to voltage select! : -110
470 00:13:23.310385 ** Bad device specification mmc 0 **
471 00:13:23.321525 Card did not respond to voltage select! : -110
472 00:13:23.329165 ** Bad device specification mmc 0 **
473 00:13:23.329723 Couldn't find partition mmc 0
474 00:13:23.337427 Card did not respond to voltage select! : -110
475 00:13:23.342932 ** Bad device specification mmc 0 **
476 00:13:23.343467 Couldn't find partition mmc 0
477 00:13:23.348016 Error: could not access storage.
478 00:13:24.612071 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
479 00:13:24.612679 bl2_stage_init 0x01
480 00:13:24.613111 bl2_stage_init 0x81
481 00:13:24.617666 hw id: 0x0000 - pwm id 0x01
482 00:13:24.618170 bl2_stage_init 0xc1
483 00:13:24.618590 bl2_stage_init 0x02
484 00:13:24.618997
485 00:13:24.623279 L0:00000000
486 00:13:24.623778 L1:20000703
487 00:13:24.624233 L2:00008067
488 00:13:24.624639 L3:14000000
489 00:13:24.628951 B2:00402000
490 00:13:24.629442 B1:e0f83180
491 00:13:24.629856
492 00:13:24.630262 TE: 58124
493 00:13:24.630662
494 00:13:24.634433 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 00:13:24.634939
496 00:13:24.635374 Board ID = 1
497 00:13:24.640068 Set A53 clk to 24M
498 00:13:24.640557 Set A73 clk to 24M
499 00:13:24.640973 Set clk81 to 24M
500 00:13:24.645633 A53 clk: 1200 MHz
501 00:13:24.646115 A73 clk: 1200 MHz
502 00:13:24.646526 CLK81: 166.6M
503 00:13:24.646926 smccc: 00012a92
504 00:13:24.651227 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 00:13:24.656915 board id: 1
506 00:13:24.662681 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 00:13:24.673352 fw parse done
508 00:13:24.679326 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 00:13:24.721942 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 00:13:24.732942 PIEI prepare done
511 00:13:24.733446 fastboot data load
512 00:13:24.733866 fastboot data verify
513 00:13:24.738466 verify result: 266
514 00:13:24.744090 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 00:13:24.744568 LPDDR4 probe
516 00:13:24.744980 ddr clk to 1584MHz
517 00:13:24.752095 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 00:13:24.789320
519 00:13:24.789825 dmc_version 0001
520 00:13:24.796068 Check phy result
521 00:13:24.801922 INFO : End of CA training
522 00:13:24.802382 INFO : End of initialization
523 00:13:24.807422 INFO : Training has run successfully!
524 00:13:24.807885 Check phy result
525 00:13:24.813054 INFO : End of initialization
526 00:13:24.813521 INFO : End of read enable training
527 00:13:24.818673 INFO : End of fine write leveling
528 00:13:24.824294 INFO : End of Write leveling coarse delay
529 00:13:24.824797 INFO : Training has run successfully!
530 00:13:24.825206 Check phy result
531 00:13:24.829988 INFO : End of initialization
532 00:13:24.830487 INFO : End of read dq deskew training
533 00:13:24.835454 INFO : End of MPR read delay center optimization
534 00:13:24.841076 INFO : End of write delay center optimization
535 00:13:24.846673 INFO : End of read delay center optimization
536 00:13:24.847160 INFO : End of max read latency training
537 00:13:24.852266 INFO : Training has run successfully!
538 00:13:24.852757 1D training succeed
539 00:13:24.861393 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 00:13:24.909077 Check phy result
541 00:13:24.909590 INFO : End of initialization
542 00:13:24.931085 INFO : End of 2D read delay Voltage center optimization
543 00:13:24.950184 INFO : End of 2D read delay Voltage center optimization
544 00:13:25.002235 INFO : End of 2D write delay Voltage center optimization
545 00:13:25.051618 INFO : End of 2D write delay Voltage center optimization
546 00:13:25.057135 INFO : Training has run successfully!
547 00:13:25.057629
548 00:13:25.058047 channel==0
549 00:13:25.062701 RxClkDly_Margin_A0==88 ps 9
550 00:13:25.063173 TxDqDly_Margin_A0==98 ps 10
551 00:13:25.068318 RxClkDly_Margin_A1==88 ps 9
552 00:13:25.068811 TxDqDly_Margin_A1==98 ps 10
553 00:13:25.069233 TrainedVREFDQ_A0==74
554 00:13:25.073981 TrainedVREFDQ_A1==76
555 00:13:25.074481 VrefDac_Margin_A0==25
556 00:13:25.074897 DeviceVref_Margin_A0==40
557 00:13:25.079553 VrefDac_Margin_A1==25
558 00:13:25.080074 DeviceVref_Margin_A1==38
559 00:13:25.080487
560 00:13:25.080892
561 00:13:25.085122 channel==1
562 00:13:25.085590 RxClkDly_Margin_A0==88 ps 9
563 00:13:25.085999 TxDqDly_Margin_A0==98 ps 10
564 00:13:25.090693 RxClkDly_Margin_A1==88 ps 9
565 00:13:25.091161 TxDqDly_Margin_A1==88 ps 9
566 00:13:25.096301 TrainedVREFDQ_A0==77
567 00:13:25.096776 TrainedVREFDQ_A1==77
568 00:13:25.097187 VrefDac_Margin_A0==23
569 00:13:25.102018 DeviceVref_Margin_A0==37
570 00:13:25.102491 VrefDac_Margin_A1==24
571 00:13:25.107522 DeviceVref_Margin_A1==37
572 00:13:25.108019
573 00:13:25.108439 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 00:13:25.108836
575 00:13:25.141048 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
576 00:13:25.141616 2D training succeed
577 00:13:25.146757 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 00:13:25.152327 auto size-- 65535DDR cs0 size: 2048MB
579 00:13:25.152820 DDR cs1 size: 2048MB
580 00:13:25.157991 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 00:13:25.158492 cs0 DataBus test pass
582 00:13:25.163509 cs1 DataBus test pass
583 00:13:25.164022 cs0 AddrBus test pass
584 00:13:25.164438 cs1 AddrBus test pass
585 00:13:25.164839
586 00:13:25.169137 100bdlr_step_size ps== 420
587 00:13:25.169628 result report
588 00:13:25.174686 boot times 0Enable ddr reg access
589 00:13:25.180084 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 00:13:25.193407 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 00:13:25.767754 0.0;M3 CHK:0;cm4_sp_mode 0
592 00:13:25.768413 MVN_1=0x00000000
593 00:13:25.772680 MVN_2=0x00000000
594 00:13:25.778419 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 00:13:25.778734 OPS=0x10
596 00:13:25.778978 ring efuse init
597 00:13:25.779189 chipver efuse init
598 00:13:25.786544 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 00:13:25.786875 [0.018961 Inits done]
600 00:13:25.794114 secure task start!
601 00:13:25.794456 high task start!
602 00:13:25.794684 low task start!
603 00:13:25.794916 run into bl31
604 00:13:25.800826 NOTICE: BL31: v1.3(release):4fc40b1
605 00:13:25.808588 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 00:13:25.808925 NOTICE: BL31: G12A normal boot!
607 00:13:25.834040 NOTICE: BL31: BL33 decompress pass
608 00:13:25.839649 ERROR: Error initializing runtime service opteed_fast
609 00:13:27.072493
610 00:13:27.073164
611 00:13:27.080863 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 00:13:27.081375
613 00:13:27.081836 Model: Libre Computer AML-A311D-CC Alta
614 00:13:27.289380 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 00:13:27.311852 DRAM: 2 GiB (effective 3.8 GiB)
616 00:13:27.455617 Core: 408 devices, 31 uclasses, devicetree: separate
617 00:13:27.461481 WDT: Not starting watchdog@f0d0
618 00:13:27.493782 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 00:13:27.506286 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 00:13:27.511211 ** Bad device specification mmc 0 **
621 00:13:27.521617 Card did not respond to voltage select! : -110
622 00:13:27.529257 ** Bad device specification mmc 0 **
623 00:13:27.529590 Couldn't find partition mmc 0
624 00:13:27.537571 Card did not respond to voltage select! : -110
625 00:13:27.543132 ** Bad device specification mmc 0 **
626 00:13:27.543471 Couldn't find partition mmc 0
627 00:13:27.548194 Error: could not access storage.
628 00:13:27.890656 Net: eth0: ethernet@ff3f0000
629 00:13:27.891325 starting USB...
630 00:13:28.142526 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 00:13:28.143187 Starting the controller
632 00:13:28.149443 USB XHCI 1.10
633 00:13:29.862388 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
634 00:13:29.862820 bl2_stage_init 0x01
635 00:13:29.863036 bl2_stage_init 0x81
636 00:13:29.867876 hw id: 0x0000 - pwm id 0x01
637 00:13:29.868322 bl2_stage_init 0xc1
638 00:13:29.868651 bl2_stage_init 0x02
639 00:13:29.868969
640 00:13:29.873559 L0:00000000
641 00:13:29.873950 L1:20000703
642 00:13:29.874188 L2:00008067
643 00:13:29.874393 L3:14000000
644 00:13:29.878979 B2:00402000
645 00:13:29.879272 B1:e0f83180
646 00:13:29.879480
647 00:13:29.879684 TE: 58167
648 00:13:29.879886
649 00:13:29.884667 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 00:13:29.884969
651 00:13:29.885189 Board ID = 1
652 00:13:29.890166 Set A53 clk to 24M
653 00:13:29.890464 Set A73 clk to 24M
654 00:13:29.890676 Set clk81 to 24M
655 00:13:29.895862 A53 clk: 1200 MHz
656 00:13:29.896309 A73 clk: 1200 MHz
657 00:13:29.896769 CLK81: 166.6M
658 00:13:29.897213 smccc: 00012abe
659 00:13:29.901455 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 00:13:29.907032 board id: 1
661 00:13:29.912945 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 00:13:29.923656 fw parse done
663 00:13:29.929543 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 00:13:29.972156 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 00:13:29.983010 PIEI prepare done
666 00:13:29.983497 fastboot data load
667 00:13:29.983948 fastboot data verify
668 00:13:29.988772 verify result: 266
669 00:13:29.994289 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 00:13:29.994770 LPDDR4 probe
671 00:13:29.995215 ddr clk to 1584MHz
672 00:13:30.002264 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 00:13:30.039512
674 00:13:30.040046 dmc_version 0001
675 00:13:30.046221 Check phy result
676 00:13:30.052076 INFO : End of CA training
677 00:13:30.052565 INFO : End of initialization
678 00:13:30.057672 INFO : Training has run successfully!
679 00:13:30.058153 Check phy result
680 00:13:30.063265 INFO : End of initialization
681 00:13:30.063747 INFO : End of read enable training
682 00:13:30.066667 INFO : End of fine write leveling
683 00:13:30.072203 INFO : End of Write leveling coarse delay
684 00:13:30.077773 INFO : Training has run successfully!
685 00:13:30.078248 Check phy result
686 00:13:30.078694 INFO : End of initialization
687 00:13:30.083366 INFO : End of read dq deskew training
688 00:13:30.088961 INFO : End of MPR read delay center optimization
689 00:13:30.089458 INFO : End of write delay center optimization
690 00:13:30.094612 INFO : End of read delay center optimization
691 00:13:30.100238 INFO : End of max read latency training
692 00:13:30.100792 INFO : Training has run successfully!
693 00:13:30.105818 1D training succeed
694 00:13:30.111862 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 00:13:30.159406 Check phy result
696 00:13:30.159957 INFO : End of initialization
697 00:13:30.181083 INFO : End of 2D read delay Voltage center optimization
698 00:13:30.201393 INFO : End of 2D read delay Voltage center optimization
699 00:13:30.253454 INFO : End of 2D write delay Voltage center optimization
700 00:13:30.302815 INFO : End of 2D write delay Voltage center optimization
701 00:13:30.308333 INFO : Training has run successfully!
702 00:13:30.308846
703 00:13:30.309274 channel==0
704 00:13:30.313926 RxClkDly_Margin_A0==88 ps 9
705 00:13:30.314454 TxDqDly_Margin_A0==98 ps 10
706 00:13:30.319514 RxClkDly_Margin_A1==88 ps 9
707 00:13:30.320065 TxDqDly_Margin_A1==88 ps 9
708 00:13:30.320506 TrainedVREFDQ_A0==74
709 00:13:30.325095 TrainedVREFDQ_A1==74
710 00:13:30.325632 VrefDac_Margin_A0==24
711 00:13:30.326068 DeviceVref_Margin_A0==40
712 00:13:30.330846 VrefDac_Margin_A1==25
713 00:13:30.331372 DeviceVref_Margin_A1==40
714 00:13:30.331797
715 00:13:30.332254
716 00:13:30.332689 channel==1
717 00:13:30.336351 RxClkDly_Margin_A0==98 ps 10
718 00:13:30.336872 TxDqDly_Margin_A0==98 ps 10
719 00:13:30.341945 RxClkDly_Margin_A1==98 ps 10
720 00:13:30.342452 TxDqDly_Margin_A1==88 ps 9
721 00:13:30.347452 TrainedVREFDQ_A0==77
722 00:13:30.347968 TrainedVREFDQ_A1==77
723 00:13:30.348434 VrefDac_Margin_A0==22
724 00:13:30.353078 DeviceVref_Margin_A0==37
725 00:13:30.353585 VrefDac_Margin_A1==22
726 00:13:30.358819 DeviceVref_Margin_A1==37
727 00:13:30.359319
728 00:13:30.359740 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 00:13:30.360190
730 00:13:30.392276 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
731 00:13:30.392847 2D training succeed
732 00:13:30.397870 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 00:13:30.403390 auto size-- 65535DDR cs0 size: 2048MB
734 00:13:30.403898 DDR cs1 size: 2048MB
735 00:13:30.409013 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 00:13:30.409523 cs0 DataBus test pass
737 00:13:30.414597 cs1 DataBus test pass
738 00:13:30.415102 cs0 AddrBus test pass
739 00:13:30.415517 cs1 AddrBus test pass
740 00:13:30.415918
741 00:13:30.420232 100bdlr_step_size ps== 420
742 00:13:30.420756 result report
743 00:13:30.425805 boot times 0Enable ddr reg access
744 00:13:30.431143 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 00:13:30.444605 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 00:13:31.018121 0.0;M3 CHK:0;cm4_sp_mode 0
747 00:13:31.018538 MVN_1=0x00000000
748 00:13:31.023895 MVN_2=0x00000000
749 00:13:31.029508 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 00:13:31.029823 OPS=0x10
751 00:13:31.030042 ring efuse init
752 00:13:31.030240 chipver efuse init
753 00:13:31.035298 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 00:13:31.040701 [0.018961 Inits done]
755 00:13:31.041024 secure task start!
756 00:13:31.041233 high task start!
757 00:13:31.045242 low task start!
758 00:13:31.045554 run into bl31
759 00:13:31.051910 NOTICE: BL31: v1.3(release):4fc40b1
760 00:13:31.059725 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 00:13:31.060078 NOTICE: BL31: G12A normal boot!
762 00:13:31.085071 NOTICE: BL31: BL33 decompress pass
763 00:13:31.090768 ERROR: Error initializing runtime service opteed_fast
764 00:13:32.323689
765 00:13:32.324365
766 00:13:32.332129 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 00:13:32.332638
768 00:13:32.333064 Model: Libre Computer AML-A311D-CC Alta
769 00:13:32.540601 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 00:13:32.564020 DRAM: 2 GiB (effective 3.8 GiB)
771 00:13:32.706951 Core: 408 devices, 31 uclasses, devicetree: separate
772 00:13:32.712820 WDT: Not starting watchdog@f0d0
773 00:13:32.745119 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 00:13:32.757500 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 00:13:32.762553 ** Bad device specification mmc 0 **
776 00:13:32.772933 Card did not respond to voltage select! : -110
777 00:13:32.780548 ** Bad device specification mmc 0 **
778 00:13:32.781094 Couldn't find partition mmc 0
779 00:13:32.788946 Card did not respond to voltage select! : -110
780 00:13:32.794386 ** Bad device specification mmc 0 **
781 00:13:32.794883 Couldn't find partition mmc 0
782 00:13:32.799433 Error: could not access storage.
783 00:13:33.141842 Net: eth0: ethernet@ff3f0000
784 00:13:33.142446 starting USB...
785 00:13:33.393681 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 00:13:33.394281 Starting the controller
787 00:13:33.400654 USB XHCI 1.10
788 00:13:35.563888 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 00:13:35.564334 bl2_stage_init 0x01
790 00:13:35.564580 bl2_stage_init 0x81
791 00:13:35.569474 hw id: 0x0000 - pwm id 0x01
792 00:13:35.569898 bl2_stage_init 0xc1
793 00:13:35.570175 bl2_stage_init 0x02
794 00:13:35.570410
795 00:13:35.575052 L0:00000000
796 00:13:35.575364 L1:20000703
797 00:13:35.575603 L2:00008067
798 00:13:35.575834 L3:14000000
799 00:13:35.580626 B2:00402000
800 00:13:35.580931 B1:e0f83180
801 00:13:35.581184
802 00:13:35.581427 TE: 58124
803 00:13:35.581663
804 00:13:35.586425 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 00:13:35.586889
806 00:13:35.587282 Board ID = 1
807 00:13:35.591818 Set A53 clk to 24M
808 00:13:35.592287 Set A73 clk to 24M
809 00:13:35.592560 Set clk81 to 24M
810 00:13:35.597552 A53 clk: 1200 MHz
811 00:13:35.598008 A73 clk: 1200 MHz
812 00:13:35.598566 CLK81: 166.6M
813 00:13:35.598841 smccc: 00012a92
814 00:13:35.603067 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 00:13:35.608557 board id: 1
816 00:13:35.614425 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 00:13:35.625152 fw parse done
818 00:13:35.630134 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 00:13:35.672759 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 00:13:35.684592 PIEI prepare done
821 00:13:35.684940 fastboot data load
822 00:13:35.685184 fastboot data verify
823 00:13:35.690378 verify result: 266
824 00:13:35.695886 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 00:13:35.696389 LPDDR4 probe
826 00:13:35.696791 ddr clk to 1584MHz
827 00:13:35.702934 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 00:13:35.741131
829 00:13:35.741517 dmc_version 0001
830 00:13:35.747763 Check phy result
831 00:13:35.753786 INFO : End of CA training
832 00:13:35.754284 INFO : End of initialization
833 00:13:35.759477 INFO : Training has run successfully!
834 00:13:35.759958 Check phy result
835 00:13:35.765057 INFO : End of initialization
836 00:13:35.765535 INFO : End of read enable training
837 00:13:35.768281 INFO : End of fine write leveling
838 00:13:35.773778 INFO : End of Write leveling coarse delay
839 00:13:35.779465 INFO : Training has run successfully!
840 00:13:35.779944 Check phy result
841 00:13:35.780400 INFO : End of initialization
842 00:13:35.784994 INFO : End of read dq deskew training
843 00:13:35.790601 INFO : End of MPR read delay center optimization
844 00:13:35.791094 INFO : End of write delay center optimization
845 00:13:35.796202 INFO : End of read delay center optimization
846 00:13:35.801767 INFO : End of max read latency training
847 00:13:35.802248 INFO : Training has run successfully!
848 00:13:35.807453 1D training succeed
849 00:13:35.813331 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 00:13:35.860907 Check phy result
851 00:13:35.861442 INFO : End of initialization
852 00:13:35.882625 INFO : End of 2D read delay Voltage center optimization
853 00:13:35.901898 INFO : End of 2D read delay Voltage center optimization
854 00:13:35.955320 INFO : End of 2D write delay Voltage center optimization
855 00:13:36.004308 INFO : End of 2D write delay Voltage center optimization
856 00:13:36.009835 INFO : Training has run successfully!
857 00:13:36.010332
858 00:13:36.010756 channel==0
859 00:13:36.015506 RxClkDly_Margin_A0==88 ps 9
860 00:13:36.016032 TxDqDly_Margin_A0==98 ps 10
861 00:13:36.021005 RxClkDly_Margin_A1==88 ps 9
862 00:13:36.021498 TxDqDly_Margin_A1==98 ps 10
863 00:13:36.021928 TrainedVREFDQ_A0==74
864 00:13:36.026643 TrainedVREFDQ_A1==76
865 00:13:36.027145 VrefDac_Margin_A0==25
866 00:13:36.027555 DeviceVref_Margin_A0==40
867 00:13:36.032247 VrefDac_Margin_A1==25
868 00:13:36.032758 DeviceVref_Margin_A1==38
869 00:13:36.033155
870 00:13:36.033550
871 00:13:36.037793 channel==1
872 00:13:36.038250 RxClkDly_Margin_A0==98 ps 10
873 00:13:36.038638 TxDqDly_Margin_A0==88 ps 9
874 00:13:36.043474 RxClkDly_Margin_A1==98 ps 10
875 00:13:36.043936 TxDqDly_Margin_A1==88 ps 9
876 00:13:36.048999 TrainedVREFDQ_A0==75
877 00:13:36.049468 TrainedVREFDQ_A1==77
878 00:13:36.049860 VrefDac_Margin_A0==22
879 00:13:36.054604 DeviceVref_Margin_A0==38
880 00:13:36.055066 VrefDac_Margin_A1==22
881 00:13:36.060233 DeviceVref_Margin_A1==37
882 00:13:36.060734
883 00:13:36.061125 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 00:13:36.061510
885 00:13:36.093755 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
886 00:13:36.094313 2D training succeed
887 00:13:36.099492 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 00:13:36.104990 auto size-- 65535DDR cs0 size: 2048MB
889 00:13:36.105459 DDR cs1 size: 2048MB
890 00:13:36.110612 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 00:13:36.111067 cs0 DataBus test pass
892 00:13:36.116235 cs1 DataBus test pass
893 00:13:36.116710 cs0 AddrBus test pass
894 00:13:36.117103 cs1 AddrBus test pass
895 00:13:36.117496
896 00:13:36.121746 100bdlr_step_size ps== 420
897 00:13:36.122244 result report
898 00:13:36.127493 boot times 0Enable ddr reg access
899 00:13:36.132701 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 00:13:36.146169 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 00:13:36.719801 0.0;M3 CHK:0;cm4_sp_mode 0
902 00:13:36.720254 MVN_1=0x00000000
903 00:13:36.725287 MVN_2=0x00000000
904 00:13:36.731077 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 00:13:36.731407 OPS=0x10
906 00:13:36.731652 ring efuse init
907 00:13:36.731878 chipver efuse init
908 00:13:36.736651 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 00:13:36.742291 [0.018960 Inits done]
910 00:13:36.742608 secure task start!
911 00:13:36.742847 high task start!
912 00:13:36.746837 low task start!
913 00:13:36.747154 run into bl31
914 00:13:36.753507 NOTICE: BL31: v1.3(release):4fc40b1
915 00:13:36.761279 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 00:13:36.761787 NOTICE: BL31: G12A normal boot!
917 00:13:36.786801 NOTICE: BL31: BL33 decompress pass
918 00:13:36.792404 ERROR: Error initializing runtime service opteed_fast
919 00:13:38.025233
920 00:13:38.025860
921 00:13:38.033693 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 00:13:38.034233
923 00:13:38.034657 Model: Libre Computer AML-A311D-CC Alta
924 00:13:38.241161 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 00:13:38.265496 DRAM: 2 GiB (effective 3.8 GiB)
926 00:13:38.408501 Core: 408 devices, 31 uclasses, devicetree: separate
927 00:13:38.414346 WDT: Not starting watchdog@f0d0
928 00:13:38.446689 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 00:13:38.459067 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 00:13:38.464079 ** Bad device specification mmc 0 **
931 00:13:38.474378 Card did not respond to voltage select! : -110
932 00:13:38.481986 ** Bad device specification mmc 0 **
933 00:13:38.482528 Couldn't find partition mmc 0
934 00:13:38.490342 Card did not respond to voltage select! : -110
935 00:13:38.495876 ** Bad device specification mmc 0 **
936 00:13:38.496457 Couldn't find partition mmc 0
937 00:13:38.501015 Error: could not access storage.
938 00:13:38.843461 Net: eth0: ethernet@ff3f0000
939 00:13:38.844134 starting USB...
940 00:13:39.095204 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 00:13:39.095618 Starting the controller
942 00:13:39.102163 USB XHCI 1.10
943 00:13:40.963890 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
944 00:13:40.964332 bl2_stage_init 0x01
945 00:13:40.964559 bl2_stage_init 0x81
946 00:13:40.969437 hw id: 0x0000 - pwm id 0x01
947 00:13:40.969732 bl2_stage_init 0xc1
948 00:13:40.969950 bl2_stage_init 0x02
949 00:13:40.970157
950 00:13:40.975077 L0:00000000
951 00:13:40.975367 L1:20000703
952 00:13:40.975581 L2:00008067
953 00:13:40.975800 L3:14000000
954 00:13:40.980533 B2:00402000
955 00:13:40.980813 B1:e0f83180
956 00:13:40.981025
957 00:13:40.981242 TE: 58167
958 00:13:40.981451
959 00:13:40.986318 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
960 00:13:40.986602
961 00:13:40.986817 Board ID = 1
962 00:13:40.991825 Set A53 clk to 24M
963 00:13:40.992125 Set A73 clk to 24M
964 00:13:40.992342 Set clk81 to 24M
965 00:13:40.997501 A53 clk: 1200 MHz
966 00:13:40.997896 A73 clk: 1200 MHz
967 00:13:40.998231 CLK81: 166.6M
968 00:13:40.998554 smccc: 00012abe
969 00:13:41.003075 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
970 00:13:41.008599 board id: 1
971 00:13:41.014588 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
972 00:13:41.025031 fw parse done
973 00:13:41.030990 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
974 00:13:41.073614 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
975 00:13:41.084460 PIEI prepare done
976 00:13:41.084968 fastboot data load
977 00:13:41.085412 fastboot data verify
978 00:13:41.090031 verify result: 266
979 00:13:41.095656 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
980 00:13:41.096154 LPDDR4 probe
981 00:13:41.096553 ddr clk to 1584MHz
982 00:13:41.103610 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
983 00:13:41.140945
984 00:13:41.141480 dmc_version 0001
985 00:13:41.147606 Check phy result
986 00:13:41.153454 INFO : End of CA training
987 00:13:41.153949 INFO : End of initialization
988 00:13:41.159081 INFO : Training has run successfully!
989 00:13:41.159553 Check phy result
990 00:13:41.164756 INFO : End of initialization
991 00:13:41.165271 INFO : End of read enable training
992 00:13:41.170293 INFO : End of fine write leveling
993 00:13:41.175912 INFO : End of Write leveling coarse delay
994 00:13:41.176436 INFO : Training has run successfully!
995 00:13:41.176864 Check phy result
996 00:13:41.181488 INFO : End of initialization
997 00:13:41.182003 INFO : End of read dq deskew training
998 00:13:41.187083 INFO : End of MPR read delay center optimization
999 00:13:41.192653 INFO : End of write delay center optimization
1000 00:13:41.198241 INFO : End of read delay center optimization
1001 00:13:41.198741 INFO : End of max read latency training
1002 00:13:41.203916 INFO : Training has run successfully!
1003 00:13:41.204459 1D training succeed
1004 00:13:41.213119 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 00:13:41.260700 Check phy result
1006 00:13:41.261273 INFO : End of initialization
1007 00:13:41.282372 INFO : End of 2D read delay Voltage center optimization
1008 00:13:41.302612 INFO : End of 2D read delay Voltage center optimization
1009 00:13:41.354650 INFO : End of 2D write delay Voltage center optimization
1010 00:13:41.404071 INFO : End of 2D write delay Voltage center optimization
1011 00:13:41.409524 INFO : Training has run successfully!
1012 00:13:41.410052
1013 00:13:41.410544 channel==0
1014 00:13:41.415113 RxClkDly_Margin_A0==88 ps 9
1015 00:13:41.415662 TxDqDly_Margin_A0==98 ps 10
1016 00:13:41.420720 RxClkDly_Margin_A1==88 ps 9
1017 00:13:41.421237 TxDqDly_Margin_A1==98 ps 10
1018 00:13:41.421684 TrainedVREFDQ_A0==74
1019 00:13:41.426329 TrainedVREFDQ_A1==74
1020 00:13:41.426834 VrefDac_Margin_A0==25
1021 00:13:41.427258 DeviceVref_Margin_A0==40
1022 00:13:41.431938 VrefDac_Margin_A1==25
1023 00:13:41.432471 DeviceVref_Margin_A1==40
1024 00:13:41.432894
1025 00:13:41.433343
1026 00:13:41.437518 channel==1
1027 00:13:41.438014 RxClkDly_Margin_A0==98 ps 10
1028 00:13:41.438426 TxDqDly_Margin_A0==98 ps 10
1029 00:13:41.443121 RxClkDly_Margin_A1==88 ps 9
1030 00:13:41.443613 TxDqDly_Margin_A1==88 ps 9
1031 00:13:41.448686 TrainedVREFDQ_A0==77
1032 00:13:41.449168 TrainedVREFDQ_A1==77
1033 00:13:41.449594 VrefDac_Margin_A0==22
1034 00:13:41.454324 DeviceVref_Margin_A0==37
1035 00:13:41.454842 VrefDac_Margin_A1==24
1036 00:13:41.460008 DeviceVref_Margin_A1==37
1037 00:13:41.460355
1038 00:13:41.460588 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1039 00:13:41.460822
1040 00:13:41.493594 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1041 00:13:41.494173 2D training succeed
1042 00:13:41.499173 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1043 00:13:41.504795 auto size-- 65535DDR cs0 size: 2048MB
1044 00:13:41.505267 DDR cs1 size: 2048MB
1045 00:13:41.510362 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1046 00:13:41.510875 cs0 DataBus test pass
1047 00:13:41.516011 cs1 DataBus test pass
1048 00:13:41.516502 cs0 AddrBus test pass
1049 00:13:41.516921 cs1 AddrBus test pass
1050 00:13:41.517329
1051 00:13:41.521639 100bdlr_step_size ps== 420
1052 00:13:41.522016 result report
1053 00:13:41.527266 boot times 0Enable ddr reg access
1054 00:13:41.532504 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1055 00:13:41.546237 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1056 00:13:42.119692 0.0;M3 CHK:0;cm4_sp_mode 0
1057 00:13:42.120160 MVN_1=0x00000000
1058 00:13:42.125161 MVN_2=0x00000000
1059 00:13:42.130894 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1060 00:13:42.131245 OPS=0x10
1061 00:13:42.131473 ring efuse init
1062 00:13:42.131699 chipver efuse init
1063 00:13:42.136541 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1064 00:13:42.142213 [0.018961 Inits done]
1065 00:13:42.142736 secure task start!
1066 00:13:42.143120 high task start!
1067 00:13:42.146697 low task start!
1068 00:13:42.147205 run into bl31
1069 00:13:42.153347 NOTICE: BL31: v1.3(release):4fc40b1
1070 00:13:42.161261 NOTICE: BL31: Built : 15:58:17, May 22 2019
1071 00:13:42.161813 NOTICE: BL31: G12A normal boot!
1072 00:13:42.186592 NOTICE: BL31: BL33 decompress pass
1073 00:13:42.192253 ERROR: Error initializing runtime service opteed_fast
1074 00:13:43.425200
1075 00:13:43.425842
1076 00:13:43.433534 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1077 00:13:43.434080
1078 00:13:43.434512 Model: Libre Computer AML-A311D-CC Alta
1079 00:13:43.642030 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1080 00:13:43.665392 DRAM: 2 GiB (effective 3.8 GiB)
1081 00:13:43.808421 Core: 408 devices, 31 uclasses, devicetree: separate
1082 00:13:43.814228 WDT: Not starting watchdog@f0d0
1083 00:13:43.846476 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1084 00:13:43.858922 Loading Environment from FAT... Card did not respond to voltage select! : -110
1085 00:13:43.862997 ** Bad device specification mmc 0 **
1086 00:13:43.874279 Card did not respond to voltage select! : -110
1087 00:13:43.881896 ** Bad device specification mmc 0 **
1088 00:13:43.882402 Couldn't find partition mmc 0
1089 00:13:43.890264 Card did not respond to voltage select! : -110
1090 00:13:43.895717 ** Bad device specification mmc 0 **
1091 00:13:43.896222 Couldn't find partition mmc 0
1092 00:13:43.900798 Error: could not access storage.
1093 00:13:44.243295 Net: eth0: ethernet@ff3f0000
1094 00:13:44.243876 starting USB...
1095 00:13:44.495135 Bus usb@ff500000: Register 3000140 NbrPorts 3
1096 00:13:44.495724 Starting the controller
1097 00:13:44.502078 USB XHCI 1.10
1098 00:13:46.056267 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1099 00:13:46.064646 scanning usb for storage devices... 0 Storage Device(s) found
1101 00:13:46.116268 Hit any key to stop autoboot: 1
1102 00:13:46.117168 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1103 00:13:46.117733 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1104 00:13:46.118188 Setting prompt string to ['=>']
1105 00:13:46.118654 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1106 00:13:46.132191 0
1107 00:13:46.133082 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1108 00:13:46.133557 Sending with 10 millisecond of delay
1110 00:13:47.268627 => setenv autoload no
1111 00:13:47.279418 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1112 00:13:47.284303 setenv autoload no
1113 00:13:47.285054 Sending with 10 millisecond of delay
1115 00:13:49.082282 => setenv initrd_high 0xffffffff
1116 00:13:49.093072 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1117 00:13:49.093967 setenv initrd_high 0xffffffff
1118 00:13:49.094734 Sending with 10 millisecond of delay
1120 00:13:50.711468 => setenv fdt_high 0xffffffff
1121 00:13:50.722317 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1122 00:13:50.723195 setenv fdt_high 0xffffffff
1123 00:13:50.723903 Sending with 10 millisecond of delay
1125 00:13:51.015767 => dhcp
1126 00:13:51.026567 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1127 00:13:51.027430 dhcp
1128 00:13:51.027865 Speed: 1000, full duplex
1129 00:13:51.028320 BOOTP broadcast 1
1130 00:13:51.038021 DHCP client bound to address 192.168.6.27 (11 ms)
1131 00:13:51.038719 Sending with 10 millisecond of delay
1133 00:13:52.715185 => setenv serverip 192.168.6.2
1134 00:13:52.726062 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1135 00:13:52.727067 setenv serverip 192.168.6.2
1136 00:13:52.728131 Sending with 10 millisecond of delay
1138 00:13:56.454990 => tftpboot 0x01080000 915212/tftp-deploy-bvzy0tdv/kernel/uImage
1139 00:13:56.466023 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1140 00:13:56.466671 tftpboot 0x01080000 915212/tftp-deploy-bvzy0tdv/kernel/uImage
1141 00:13:56.466923 Speed: 1000, full duplex
1142 00:13:56.467139 Using ethernet@ff3f0000 device
1143 00:13:56.468499 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1144 00:13:56.474061 Filename '915212/tftp-deploy-bvzy0tdv/kernel/uImage'.
1145 00:13:56.477944 Load address: 0x1080000
1146 00:13:59.048649 Loading: *################################################## 36.1 MiB
1147 00:13:59.049274 14 MiB/s
1148 00:13:59.049707 done
1149 00:13:59.053037 Bytes transferred = 37878336 (241fa40 hex)
1150 00:13:59.053837 Sending with 10 millisecond of delay
1152 00:14:03.741923 => tftpboot 0x08000000 915212/tftp-deploy-bvzy0tdv/ramdisk/ramdisk.cpio.gz.uboot
1153 00:14:03.752707 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1154 00:14:03.753551 tftpboot 0x08000000 915212/tftp-deploy-bvzy0tdv/ramdisk/ramdisk.cpio.gz.uboot
1155 00:14:03.753997 Speed: 1000, full duplex
1156 00:14:03.754409 Using ethernet@ff3f0000 device
1157 00:14:03.756127 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1158 00:14:03.767514 Filename '915212/tftp-deploy-bvzy0tdv/ramdisk/ramdisk.cpio.gz.uboot'.
1159 00:14:03.768123 Load address: 0x8000000
1160 00:14:10.379120 Loading: *###############################T ################## UDP wrong checksum 00000005 00002792
1161 00:14:15.379559 T UDP wrong checksum 00000005 00002792
1162 00:14:25.383277 T T UDP wrong checksum 00000005 00002792
1163 00:14:31.618492 T UDP wrong checksum 000000ff 0000efbe
1164 00:14:31.628182 UDP wrong checksum 000000ff 000083b1
1165 00:14:32.063521 UDP wrong checksum 000000ff 000084c4
1166 00:14:32.129988 UDP wrong checksum 000000ff 00000ab7
1167 00:14:45.385073 T T UDP wrong checksum 00000005 00002792
1168 00:14:51.011480 T T UDP wrong checksum 000000ff 00009279
1169 00:14:51.051532 UDP wrong checksum 000000ff 00001e6c
1170 00:14:55.561480 T UDP wrong checksum 000000ff 0000600d
1171 00:14:55.720896 UDP wrong checksum 000000ff 0000faff
1172 00:14:56.231763 UDP wrong checksum 000000ff 000017ca
1173 00:14:56.252498 UDP wrong checksum 000000ff 0000acbc
1174 00:15:00.391442
1175 00:15:00.392131 Retry count exceeded; starting again
1177 00:15:00.393654 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1180 00:15:00.395656 end: 2.4 uboot-commands (duration 00:01:52) [common]
1182 00:15:00.397193 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1184 00:15:00.398324 end: 2 uboot-action (duration 00:01:52) [common]
1186 00:15:00.400031 Cleaning after the job
1187 00:15:00.400656 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/ramdisk
1188 00:15:00.402177 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/kernel
1189 00:15:00.409270 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/dtb
1190 00:15:00.410595 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/nfsrootfs
1191 00:15:00.479493 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/915212/tftp-deploy-bvzy0tdv/modules
1192 00:15:00.484590 start: 4.1 power-off (timeout 00:00:30) [common]
1193 00:15:00.485214 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1194 00:15:00.518529 >> OK - accepted request
1195 00:15:00.521120 Returned 0 in 0 seconds
1196 00:15:00.622065 end: 4.1 power-off (duration 00:00:00) [common]
1198 00:15:00.623081 start: 4.2 read-feedback (timeout 00:10:00) [common]
1199 00:15:00.623751 Listened to connection for namespace 'common' for up to 1s
1200 00:15:01.623871 Finalising connection for namespace 'common'
1201 00:15:01.624666 Disconnecting from shell: Finalise
1202 00:15:01.625244 =>
1203 00:15:01.726356 end: 4.2 read-feedback (duration 00:00:01) [common]
1204 00:15:01.727066 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/915212
1205 00:15:04.110598 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/915212
1206 00:15:04.111213 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.