Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 21:54:27.956727 lava-dispatcher, installed at version: 2024.01
2 21:54:27.957495 start: 0 validate
3 21:54:27.958000 Start time: 2024-11-06 21:54:27.957967+00:00 (UTC)
4 21:54:27.958544 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 21:54:27.959086 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 21:54:29.011570 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 21:54:29.012135 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 21:54:29.040413 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 21:54:29.041021 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 21:54:29.064692 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 21:54:29.065185 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 21:54:30.107366 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 21:54:30.107852 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 21:54:30.148022 validate duration: 2.19
16 21:54:30.148936 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 21:54:30.149259 start: 1.1 download-retry (timeout 00:10:00) [common]
18 21:54:30.149554 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 21:54:30.150158 Not decompressing ramdisk as can be used compressed.
20 21:54:30.150581 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 21:54:30.150859 saving as /var/lib/lava/dispatcher/tmp/949303/tftp-deploy-418_zsla/ramdisk/initrd.cpio.gz
22 21:54:30.151121 total size: 4775763 (4 MB)
23 21:54:30.179831 progress 0 % (0 MB)
24 21:54:30.186187 progress 5 % (0 MB)
25 21:54:30.189468 progress 10 % (0 MB)
26 21:54:30.192784 progress 15 % (0 MB)
27 21:54:30.196713 progress 20 % (0 MB)
28 21:54:30.200201 progress 25 % (1 MB)
29 21:54:30.203497 progress 30 % (1 MB)
30 21:54:30.207239 progress 35 % (1 MB)
31 21:54:30.210571 progress 40 % (1 MB)
32 21:54:30.213882 progress 45 % (2 MB)
33 21:54:30.217144 progress 50 % (2 MB)
34 21:54:30.220841 progress 55 % (2 MB)
35 21:54:30.224150 progress 60 % (2 MB)
36 21:54:30.227452 progress 65 % (2 MB)
37 21:54:30.231081 progress 70 % (3 MB)
38 21:54:30.235182 progress 75 % (3 MB)
39 21:54:30.238509 progress 80 % (3 MB)
40 21:54:30.241916 progress 85 % (3 MB)
41 21:54:30.245680 progress 90 % (4 MB)
42 21:54:30.248783 progress 95 % (4 MB)
43 21:54:30.251877 progress 100 % (4 MB)
44 21:54:30.252543 4 MB downloaded in 0.10 s (44.92 MB/s)
45 21:54:30.253189 end: 1.1.1 http-download (duration 00:00:00) [common]
47 21:54:30.254214 end: 1.1 download-retry (duration 00:00:00) [common]
48 21:54:30.254590 start: 1.2 download-retry (timeout 00:10:00) [common]
49 21:54:30.254924 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 21:54:30.255492 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 21:54:30.255772 saving as /var/lib/lava/dispatcher/tmp/949303/tftp-deploy-418_zsla/kernel/zImage
52 21:54:30.256065 total size: 11444736 (10 MB)
53 21:54:30.256322 No compression specified
54 21:54:30.289072 progress 0 % (0 MB)
55 21:54:30.296926 progress 5 % (0 MB)
56 21:54:30.304727 progress 10 % (1 MB)
57 21:54:30.312856 progress 15 % (1 MB)
58 21:54:30.320652 progress 20 % (2 MB)
59 21:54:30.328802 progress 25 % (2 MB)
60 21:54:30.336416 progress 30 % (3 MB)
61 21:54:30.344281 progress 35 % (3 MB)
62 21:54:30.351882 progress 40 % (4 MB)
63 21:54:30.360038 progress 45 % (4 MB)
64 21:54:30.367539 progress 50 % (5 MB)
65 21:54:30.375478 progress 55 % (6 MB)
66 21:54:30.382997 progress 60 % (6 MB)
67 21:54:30.390877 progress 65 % (7 MB)
68 21:54:30.398315 progress 70 % (7 MB)
69 21:54:30.405582 progress 75 % (8 MB)
70 21:54:30.413613 progress 80 % (8 MB)
71 21:54:30.421224 progress 85 % (9 MB)
72 21:54:30.429055 progress 90 % (9 MB)
73 21:54:30.436536 progress 95 % (10 MB)
74 21:54:30.444023 progress 100 % (10 MB)
75 21:54:30.444554 10 MB downloaded in 0.19 s (57.91 MB/s)
76 21:54:30.445090 end: 1.2.1 http-download (duration 00:00:00) [common]
78 21:54:30.445992 end: 1.2 download-retry (duration 00:00:00) [common]
79 21:54:30.446283 start: 1.3 download-retry (timeout 00:10:00) [common]
80 21:54:30.446610 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 21:54:30.447121 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 21:54:30.447480 saving as /var/lib/lava/dispatcher/tmp/949303/tftp-deploy-418_zsla/dtb/am335x-boneblack.dtb
83 21:54:30.447690 total size: 70568 (0 MB)
84 21:54:30.447935 No compression specified
85 21:54:30.478488 progress 46 % (0 MB)
86 21:54:30.479382 progress 92 % (0 MB)
87 21:54:30.480208 progress 100 % (0 MB)
88 21:54:30.480642 0 MB downloaded in 0.03 s (2.04 MB/s)
89 21:54:30.481165 end: 1.3.1 http-download (duration 00:00:00) [common]
91 21:54:30.482060 end: 1.3 download-retry (duration 00:00:00) [common]
92 21:54:30.482336 start: 1.4 download-retry (timeout 00:10:00) [common]
93 21:54:30.482649 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 21:54:30.483144 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 21:54:30.483454 saving as /var/lib/lava/dispatcher/tmp/949303/tftp-deploy-418_zsla/nfsrootfs/full.rootfs.tar
96 21:54:30.483661 total size: 117747780 (112 MB)
97 21:54:30.483869 Using unxz to decompress xz
98 21:54:30.515459 progress 0 % (0 MB)
99 21:54:31.827894 progress 5 % (5 MB)
100 21:54:32.597164 progress 10 % (11 MB)
101 21:54:33.381384 progress 15 % (16 MB)
102 21:54:34.095651 progress 20 % (22 MB)
103 21:54:34.671592 progress 25 % (28 MB)
104 21:54:35.472148 progress 30 % (33 MB)
105 21:54:36.281257 progress 35 % (39 MB)
106 21:54:36.670239 progress 40 % (44 MB)
107 21:54:37.035284 progress 45 % (50 MB)
108 21:54:37.690760 progress 50 % (56 MB)
109 21:54:38.509149 progress 55 % (61 MB)
110 21:54:39.248178 progress 60 % (67 MB)
111 21:54:39.986716 progress 65 % (73 MB)
112 21:54:40.758457 progress 70 % (78 MB)
113 21:54:41.523589 progress 75 % (84 MB)
114 21:54:42.262280 progress 80 % (89 MB)
115 21:54:42.971633 progress 85 % (95 MB)
116 21:54:43.746936 progress 90 % (101 MB)
117 21:54:44.499589 progress 95 % (106 MB)
118 21:54:45.301799 progress 100 % (112 MB)
119 21:54:45.314772 112 MB downloaded in 14.83 s (7.57 MB/s)
120 21:54:45.315702 end: 1.4.1 http-download (duration 00:00:15) [common]
122 21:54:45.317448 end: 1.4 download-retry (duration 00:00:15) [common]
123 21:54:45.318111 start: 1.5 download-retry (timeout 00:09:45) [common]
124 21:54:45.318691 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 21:54:45.319504 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 21:54:45.319988 saving as /var/lib/lava/dispatcher/tmp/949303/tftp-deploy-418_zsla/modules/modules.tar
127 21:54:45.320429 total size: 6611528 (6 MB)
128 21:54:45.320870 Using unxz to decompress xz
129 21:54:45.352867 progress 0 % (0 MB)
130 21:54:45.387255 progress 5 % (0 MB)
131 21:54:45.436277 progress 10 % (0 MB)
132 21:54:45.480554 progress 15 % (0 MB)
133 21:54:45.526273 progress 20 % (1 MB)
134 21:54:45.573850 progress 25 % (1 MB)
135 21:54:45.617497 progress 30 % (1 MB)
136 21:54:45.659493 progress 35 % (2 MB)
137 21:54:45.702728 progress 40 % (2 MB)
138 21:54:45.745610 progress 45 % (2 MB)
139 21:54:45.788881 progress 50 % (3 MB)
140 21:54:45.831301 progress 55 % (3 MB)
141 21:54:45.880652 progress 60 % (3 MB)
142 21:54:45.922659 progress 65 % (4 MB)
143 21:54:45.965663 progress 70 % (4 MB)
144 21:54:46.011590 progress 75 % (4 MB)
145 21:54:46.054077 progress 80 % (5 MB)
146 21:54:46.096509 progress 85 % (5 MB)
147 21:54:46.139392 progress 90 % (5 MB)
148 21:54:46.182284 progress 95 % (6 MB)
149 21:54:46.226204 progress 100 % (6 MB)
150 21:54:46.240076 6 MB downloaded in 0.92 s (6.86 MB/s)
151 21:54:46.240837 end: 1.5.1 http-download (duration 00:00:01) [common]
153 21:54:46.242814 end: 1.5 download-retry (duration 00:00:01) [common]
154 21:54:46.243552 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 21:54:46.244243 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 21:55:02.798818 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/949303/extract-nfsrootfs-w_ovq08x
157 21:55:02.799418 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 21:55:02.799707 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 21:55:02.800310 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k
160 21:55:02.800737 makedir: /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin
161 21:55:02.801060 makedir: /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/tests
162 21:55:02.801385 makedir: /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/results
163 21:55:02.801755 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-add-keys
164 21:55:02.802342 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-add-sources
165 21:55:02.802857 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-background-process-start
166 21:55:02.803356 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-background-process-stop
167 21:55:02.803894 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-common-functions
168 21:55:02.804488 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-echo-ipv4
169 21:55:02.805009 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-install-packages
170 21:55:02.805490 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-installed-packages
171 21:55:02.806018 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-os-build
172 21:55:02.806528 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-probe-channel
173 21:55:02.807010 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-probe-ip
174 21:55:02.807490 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-target-ip
175 21:55:02.807968 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-target-mac
176 21:55:02.808511 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-target-storage
177 21:55:02.809032 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-test-case
178 21:55:02.809522 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-test-event
179 21:55:02.810054 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-test-feedback
180 21:55:02.810562 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-test-raise
181 21:55:02.811043 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-test-reference
182 21:55:02.811524 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-test-runner
183 21:55:02.812014 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-test-set
184 21:55:02.812496 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-test-shell
185 21:55:02.813029 Updating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-add-keys (debian)
186 21:55:02.813653 Updating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-add-sources (debian)
187 21:55:02.814276 Updating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-install-packages (debian)
188 21:55:02.814864 Updating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-installed-packages (debian)
189 21:55:02.815399 Updating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/bin/lava-os-build (debian)
190 21:55:02.815842 Creating /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/environment
191 21:55:02.816221 LAVA metadata
192 21:55:02.816480 - LAVA_JOB_ID=949303
193 21:55:02.816693 - LAVA_DISPATCHER_IP=192.168.6.3
194 21:55:02.817057 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 21:55:02.818081 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 21:55:02.818407 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 21:55:02.818610 skipped lava-vland-overlay
198 21:55:02.818850 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 21:55:02.819100 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 21:55:02.819299 skipped lava-multinode-overlay
201 21:55:02.819534 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 21:55:02.819780 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 21:55:02.820026 Loading test definitions
204 21:55:02.820301 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 21:55:02.820536 Using /lava-949303 at stage 0
206 21:55:02.821628 uuid=949303_1.6.2.4.1 testdef=None
207 21:55:02.821955 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 21:55:02.822219 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 21:55:02.823785 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 21:55:02.824570 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 21:55:02.826618 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 21:55:02.827452 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 21:55:02.829264 runner path: /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/0/tests/0_timesync-off test_uuid 949303_1.6.2.4.1
216 21:55:02.829836 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 21:55:02.830653 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 21:55:02.830876 Using /lava-949303 at stage 0
220 21:55:02.831233 Fetching tests from https://github.com/kernelci/test-definitions.git
221 21:55:02.831525 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/0/tests/1_kselftest-dt'
222 21:55:06.482668 Running '/usr/bin/git checkout kernelci.org
223 21:55:06.857318 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 21:55:06.858771 uuid=949303_1.6.2.4.5 testdef=None
225 21:55:06.859121 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 21:55:06.859862 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 21:55:06.862733 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 21:55:06.863556 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 21:55:06.867273 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 21:55:06.868137 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 21:55:06.871738 runner path: /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/0/tests/1_kselftest-dt test_uuid 949303_1.6.2.4.5
235 21:55:06.872057 BOARD='beaglebone-black'
236 21:55:06.872266 BRANCH='mainline'
237 21:55:06.872464 SKIPFILE='/dev/null'
238 21:55:06.872659 SKIP_INSTALL='True'
239 21:55:06.872853 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 21:55:06.873052 TST_CASENAME=''
241 21:55:06.873246 TST_CMDFILES='dt'
242 21:55:06.873837 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 21:55:06.874638 Creating lava-test-runner.conf files
245 21:55:06.874843 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949303/lava-overlay-kl_tjd6k/lava-949303/0 for stage 0
246 21:55:06.875293 - 0_timesync-off
247 21:55:06.875556 - 1_kselftest-dt
248 21:55:06.875892 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 21:55:06.876174 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 21:55:30.542843 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 21:55:30.543284 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 21:55:30.543547 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 21:55:30.543815 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 21:55:30.544079 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 21:55:31.004236 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 21:55:31.004717 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
257 21:55:31.004973 extracting modules file /var/lib/lava/dispatcher/tmp/949303/tftp-deploy-418_zsla/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949303/extract-nfsrootfs-w_ovq08x
258 21:55:31.922663 extracting modules file /var/lib/lava/dispatcher/tmp/949303/tftp-deploy-418_zsla/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949303/extract-overlay-ramdisk-baeqen75/ramdisk
259 21:55:32.855957 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 21:55:32.856406 start: 1.6.5 apply-overlay-tftp (timeout 00:08:57) [common]
261 21:55:32.856683 [common] Applying overlay to NFS
262 21:55:32.856897 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949303/compress-overlay-ic5en51a/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949303/extract-nfsrootfs-w_ovq08x
263 21:55:35.694595 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 21:55:35.695068 start: 1.6.6 prepare-kernel (timeout 00:08:54) [common]
265 21:55:35.695342 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:54) [common]
266 21:55:35.695649 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 21:55:35.695906 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 21:55:35.696162 start: 1.6.7 configure-preseed-file (timeout 00:08:54) [common]
269 21:55:35.696410 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 21:55:35.696664 start: 1.6.8 compress-ramdisk (timeout 00:08:54) [common]
271 21:55:35.696889 Building ramdisk /var/lib/lava/dispatcher/tmp/949303/extract-overlay-ramdisk-baeqen75/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949303/extract-overlay-ramdisk-baeqen75/ramdisk
272 21:55:36.818573 >> 74900 blocks
273 21:55:41.693670 Adding RAMdisk u-boot header.
274 21:55:41.694192 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949303/extract-overlay-ramdisk-baeqen75/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949303/extract-overlay-ramdisk-baeqen75/ramdisk.cpio.gz.uboot
275 21:55:41.856753 output: Image Name:
276 21:55:41.857145 output: Created: Wed Nov 6 21:55:41 2024
277 21:55:41.857356 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 21:55:41.857559 output: Data Size: 14790864 Bytes = 14444.20 KiB = 14.11 MiB
279 21:55:41.857761 output: Load Address: 00000000
280 21:55:41.858177 output: Entry Point: 00000000
281 21:55:41.858625 output:
282 21:55:41.859886 rename /var/lib/lava/dispatcher/tmp/949303/extract-overlay-ramdisk-baeqen75/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949303/tftp-deploy-418_zsla/ramdisk/ramdisk.cpio.gz.uboot
283 21:55:41.860662 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 21:55:41.861260 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 21:55:41.861903 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
286 21:55:41.862447 No LXC device requested
287 21:55:41.863004 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 21:55:41.863564 start: 1.8 deploy-device-env (timeout 00:08:48) [common]
289 21:55:41.864106 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 21:55:41.864557 Checking files for TFTP limit of 4294967296 bytes.
291 21:55:41.867537 end: 1 tftp-deploy (duration 00:01:12) [common]
292 21:55:41.868196 start: 2 uboot-action (timeout 00:05:00) [common]
293 21:55:41.868803 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 21:55:41.869370 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 21:55:41.869937 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 21:55:41.870780 substitutions:
297 21:55:41.871245 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 21:55:41.871692 - {DTB_ADDR}: 0x88000000
299 21:55:41.872157 - {DTB}: 949303/tftp-deploy-418_zsla/dtb/am335x-boneblack.dtb
300 21:55:41.872602 - {INITRD}: 949303/tftp-deploy-418_zsla/ramdisk/ramdisk.cpio.gz.uboot
301 21:55:41.873039 - {KERNEL_ADDR}: 0x82000000
302 21:55:41.873472 - {KERNEL}: 949303/tftp-deploy-418_zsla/kernel/zImage
303 21:55:41.873937 - {LAVA_MAC}: None
304 21:55:41.874473 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/949303/extract-nfsrootfs-w_ovq08x
305 21:55:41.874943 - {NFS_SERVER_IP}: 192.168.6.3
306 21:55:41.875377 - {PRESEED_CONFIG}: None
307 21:55:41.875807 - {PRESEED_LOCAL}: None
308 21:55:41.876235 - {RAMDISK_ADDR}: 0x83000000
309 21:55:41.876661 - {RAMDISK}: 949303/tftp-deploy-418_zsla/ramdisk/ramdisk.cpio.gz.uboot
310 21:55:41.877095 - {ROOT_PART}: None
311 21:55:41.877520 - {ROOT}: None
312 21:55:41.878016 - {SERVER_IP}: 192.168.6.3
313 21:55:41.878451 - {TEE_ADDR}: 0x83000000
314 21:55:41.878879 - {TEE}: None
315 21:55:41.879308 Parsed boot commands:
316 21:55:41.879721 - setenv autoload no
317 21:55:41.880144 - setenv initrd_high 0xffffffff
318 21:55:41.880565 - setenv fdt_high 0xffffffff
319 21:55:41.880983 - dhcp
320 21:55:41.881401 - setenv serverip 192.168.6.3
321 21:55:41.881844 - tftp 0x82000000 949303/tftp-deploy-418_zsla/kernel/zImage
322 21:55:41.882280 - tftp 0x83000000 949303/tftp-deploy-418_zsla/ramdisk/ramdisk.cpio.gz.uboot
323 21:55:41.882706 - setenv initrd_size ${filesize}
324 21:55:41.883127 - tftp 0x88000000 949303/tftp-deploy-418_zsla/dtb/am335x-boneblack.dtb
325 21:55:41.883551 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/949303/extract-nfsrootfs-w_ovq08x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 21:55:41.883986 - bootz 0x82000000 0x83000000 0x88000000
327 21:55:41.884543 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 21:55:41.886197 start: 2.3 connect-device (timeout 00:05:00) [common]
330 21:55:41.886656 [common] connect-device Connecting to device using 'telnet conserv3 3003'
331 21:55:41.901681 Setting prompt string to ['lava-test: # ']
332 21:55:41.903308 end: 2.3 connect-device (duration 00:00:00) [common]
333 21:55:41.903956 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 21:55:41.904637 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 21:55:41.905294 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 21:55:41.906611 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-06'
337 21:55:41.941246 >> OK - accepted request
338 21:55:41.943203 Returned 0 in 0 seconds
339 21:55:42.044388 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 21:55:42.046225 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 21:55:42.046858 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 21:55:42.047421 Setting prompt string to ['Hit any key to stop autoboot']
344 21:55:42.047916 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 21:55:42.049600 Trying 192.168.56.22...
346 21:55:42.050171 Connected to conserv3.
347 21:55:42.050634 Escape character is '^]'.
348 21:55:42.051089
349 21:55:42.051543 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 21:55:42.051993
351 21:55:49.486829
352 21:55:49.493528 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 21:55:49.493845 Trying to boot from MMC1
354 21:55:50.084055
355 21:55:50.084452
356 21:55:50.089507 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
357 21:55:50.089775
358 21:55:50.090041 CPU : AM335X-GP rev 2.0
359 21:55:50.094917 Model: TI AM335x BeagleBone Black
360 21:55:50.095199 DRAM: 512 MiB
361 21:55:53.539997
362 21:55:53.546390 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 21:55:53.546979 Trying to boot from MMC1
364 21:55:54.136500
365 21:55:54.137142
366 21:55:54.142021 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
367 21:55:54.142569
368 21:55:54.143038 CPU : AM335X-GP rev 2.0
369 21:55:54.146060 Model: TI AM335x BeagleBone Black
370 21:55:54.146580 DRAM: 512 MiB
371 21:55:56.236608
372 21:55:56.243626 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
373 21:55:56.244181 Trying to boot from MMC1
374 21:55:56.835104
375 21:55:56.835528
376 21:55:56.840508 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
377 21:55:56.840836
378 21:55:56.841098 CPU : AM335X-GP rev 2.0
379 21:55:56.844807 Model: TI AM335x BeagleBone Black
380 21:55:56.845371 DRAM: 512 MiB
381 21:55:56.924991 Core: 160 devices, 18 uclasses, devicetree: separate
382 21:55:56.939472 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 21:55:57.340521 NAND: 0 MiB
384 21:55:57.350784 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 21:55:57.425570 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 21:55:57.446027 <ethaddr> not set. Validating first E-fuse MAC
387 21:55:57.476538 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 21:55:57.535107 Hit any key to stop autoboot: 2
390 21:55:57.536123 end: 2.4.2 bootloader-interrupt (duration 00:00:15) [common]
391 21:55:57.536807 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
392 21:55:57.537384 Setting prompt string to ['=>']
393 21:55:57.538019 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
394 21:55:57.545669 0
395 21:55:57.546753 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 21:55:57.547378 Sending with 10 millisecond of delay
398 21:55:58.682834 => setenv autoload no
399 21:55:58.695507 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
400 21:55:58.698233 setenv autoload no
401 21:55:58.698762 Sending with 10 millisecond of delay
403 21:56:00.495411 => setenv initrd_high 0xffffffff
404 21:56:00.506022 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
405 21:56:00.506596 setenv initrd_high 0xffffffff
406 21:56:00.507142 Sending with 10 millisecond of delay
408 21:56:02.123860 => setenv fdt_high 0xffffffff
409 21:56:02.134585 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
410 21:56:02.135357 setenv fdt_high 0xffffffff
411 21:56:02.136015 Sending with 10 millisecond of delay
413 21:56:02.427915 => dhcp
414 21:56:02.438748 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
415 21:56:02.439683 dhcp
416 21:56:02.441600 link up on port 0, speed 100, full duplex
417 21:56:02.442172 BOOTP broadcast 1
418 21:56:02.693757 BOOTP broadcast 2
419 21:56:03.195963 BOOTP broadcast 3
420 21:56:04.197770 BOOTP broadcast 4
421 21:56:06.199736 BOOTP broadcast 5
422 21:56:06.265028 DHCP client bound to address 192.168.6.10 (3820 ms)
423 21:56:06.265804 Sending with 10 millisecond of delay
425 21:56:07.942920 => setenv serverip 192.168.6.3
426 21:56:07.953481 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
427 21:56:07.954018 setenv serverip 192.168.6.3
428 21:56:07.954500 Sending with 10 millisecond of delay
430 21:56:11.438419 => tftp 0x82000000 949303/tftp-deploy-418_zsla/kernel/zImage
431 21:56:11.448990 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:30)
432 21:56:11.449548 tftp 0x82000000 949303/tftp-deploy-418_zsla/kernel/zImage
433 21:56:11.449793 link up on port 0, speed 100, full duplex
434 21:56:11.453897 Using ethernet@4a100000 device
435 21:56:11.459518 TFTP from server 192.168.6.3; our IP address is 192.168.6.10
436 21:56:11.459791 Filename '949303/tftp-deploy-418_zsla/kernel/zImage'.
437 21:56:11.462975 Load address: 0x82000000
438 21:56:13.549157 Loading: *################################################## 10.9 MiB
439 21:56:13.549594 5.2 MiB/s
440 21:56:13.549860 done
441 21:56:13.553368 Bytes transferred = 11444736 (aea200 hex)
442 21:56:13.553914 Sending with 10 millisecond of delay
444 21:56:18.001903 => tftp 0x83000000 949303/tftp-deploy-418_zsla/ramdisk/ramdisk.cpio.gz.uboot
445 21:56:18.012868 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
446 21:56:18.013806 tftp 0x83000000 949303/tftp-deploy-418_zsla/ramdisk/ramdisk.cpio.gz.uboot
447 21:56:18.014329 link up on port 0, speed 100, full duplex
448 21:56:18.017609 Using ethernet@4a100000 device
449 21:56:18.023149 TFTP from server 192.168.6.3; our IP address is 192.168.6.10
450 21:56:18.026645 Filename '949303/tftp-deploy-418_zsla/ramdisk/ramdisk.cpio.gz.uboot'.
451 21:56:18.031690 Load address: 0x83000000
452 21:56:20.618497 Loading: *################################################## 14.1 MiB
453 21:56:20.618898 5.5 MiB/s
454 21:56:20.619121 done
455 21:56:20.622757 Bytes transferred = 14790928 (e1b110 hex)
456 21:56:20.623415 Sending with 10 millisecond of delay
458 21:56:22.479905 => setenv initrd_size ${filesize}
459 21:56:22.490593 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
460 21:56:22.491074 setenv initrd_size ${filesize}
461 21:56:22.491539 Sending with 10 millisecond of delay
463 21:56:26.635674 => tftp 0x88000000 949303/tftp-deploy-418_zsla/dtb/am335x-boneblack.dtb
464 21:56:26.646216 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
465 21:56:26.646732 tftp 0x88000000 949303/tftp-deploy-418_zsla/dtb/am335x-boneblack.dtb
466 21:56:26.646960 link up on port 0, speed 100, full duplex
467 21:56:26.650970 Using ethernet@4a100000 device
468 21:56:26.656555 TFTP from server 192.168.6.3; our IP address is 192.168.6.10
469 21:56:26.664735 Filename '949303/tftp-deploy-418_zsla/dtb/am335x-boneblack.dtb'.
470 21:56:26.665035 Load address: 0x88000000
471 21:56:26.692071 Loading: *################################################## 68.9 KiB
472 21:56:26.692417 2.7 MiB/s
473 21:56:26.692624 done
474 21:56:26.697673 Bytes transferred = 70568 (113a8 hex)
475 21:56:26.698234 Sending with 10 millisecond of delay
477 21:56:39.875526 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/949303/extract-nfsrootfs-w_ovq08x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 21:56:39.886060 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
479 21:56:39.886549 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/949303/extract-nfsrootfs-w_ovq08x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 21:56:39.887093 Sending with 10 millisecond of delay
482 21:56:42.225916 => bootz 0x82000000 0x83000000 0x88000000
483 21:56:42.236701 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 21:56:42.237256 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
485 21:56:42.238276 bootz 0x82000000 0x83000000 0x88000000
486 21:56:42.238868 Kernel image @ 0x82000000 [ 0x000000 - 0xaea200 ]
487 21:56:42.239385 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 21:56:42.244409 Image Name:
489 21:56:42.244889 Created: 2024-11-06 21:55:41 UTC
490 21:56:42.247787 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 21:56:42.253351 Data Size: 14790864 Bytes = 14.1 MiB
492 21:56:42.261639 Load Address: 00000000
493 21:56:42.262130 Entry Point: 00000000
494 21:56:42.430114 Verifying Checksum ... OK
495 21:56:42.430632 ## Flattened Device Tree blob at 88000000
496 21:56:42.436488 Booting using the fdt blob at 0x88000000
497 21:56:42.436960 Working FDT set to 88000000
498 21:56:42.442159 Using Device Tree in place at 88000000, end 880143a7
499 21:56:42.446527 Working FDT set to 88000000
500 21:56:42.462372
501 21:56:42.462845 Starting kernel ...
502 21:56:42.463259
503 21:56:42.464127 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
504 21:56:42.464699 start: 2.4.4 auto-login-action (timeout 00:03:59) [common]
505 21:56:42.465153 Setting prompt string to ['Linux version [0-9]']
506 21:56:42.465600 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
507 21:56:42.466111 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
508 21:56:43.303509 [ 0.000000] Booting Linux on physical CPU 0x0
509 21:56:43.309521 start: 2.4.4.1 login-action (timeout 00:03:59) [common]
510 21:56:43.309885 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 21:56:43.310160 Setting prompt string to []
512 21:56:43.310424 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 21:56:43.310664 Using line separator: #'\n'#
514 21:56:43.310874 No login prompt set.
515 21:56:43.311098 Parsing kernel messages
516 21:56:43.311301 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 21:56:43.311721 [login-action] Waiting for messages, (timeout 00:03:59)
518 21:56:43.311952 Waiting using forced prompt support (timeout 00:01:59)
519 21:56:43.323696 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j365653-arm-gcc-12-multi-v7-defconfig-wknmq) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Wed Nov 6 21:36:50 UTC 2024
520 21:56:43.335007 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
521 21:56:43.340657 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
522 21:56:43.346323 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
523 21:56:43.352115 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
524 21:56:43.357897 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
525 21:56:43.364556 [ 0.000000] Memory policy: Data cache writeback
526 21:56:43.364833 [ 0.000000] efi: UEFI not found.
527 21:56:43.373335 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
528 21:56:43.379176 [ 0.000000] Zone ranges:
529 21:56:43.384793 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
530 21:56:43.385076 [ 0.000000] Normal empty
531 21:56:43.390523 [ 0.000000] HighMem empty
532 21:56:43.396258 [ 0.000000] Movable zone start for each node
533 21:56:43.396646 [ 0.000000] Early memory node ranges
534 21:56:43.407547 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
535 21:56:43.412297 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
536 21:56:43.437890 [ 0.000000] CPU: All CPU(s) started in SVC mode.
537 21:56:43.443406 [ 0.000000] AM335X ES2.0 (sgx neon)
538 21:56:43.455045 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
539 21:56:43.475204 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/949303/extract-nfsrootfs-w_ovq08x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
540 21:56:43.480993 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
541 21:56:43.492414 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
542 21:56:43.498076 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
543 21:56:43.505211 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
544 21:56:43.535608 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
545 21:56:43.541060 <6>[ 0.000000] trace event string verifier disabled
546 21:56:43.541598 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
547 21:56:43.546654 <6>[ 0.000000] rcu: RCU event tracing is enabled.
548 21:56:43.558057 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
549 21:56:43.563791 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
550 21:56:43.571083 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
551 21:56:43.586044 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
552 21:56:43.603227 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
553 21:56:43.610112 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
554 21:56:43.702433 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
555 21:56:43.713914 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
556 21:56:43.720575 <6>[ 0.008335] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
557 21:56:43.733638 <6>[ 0.019141] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
558 21:56:43.741005 <6>[ 0.033950] Console: colour dummy device 80x30
559 21:56:43.746998 Matched prompt #6: WARNING:
560 21:56:43.747370 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
561 21:56:43.752563 <3>[ 0.038849] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
562 21:56:43.758310 <3>[ 0.045919] This ensures that you still see kernel messages. Please
563 21:56:43.761554 <3>[ 0.052646] update your kernel commandline.
564 21:56:43.802279 <6>[ 0.057257] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
565 21:56:43.808174 <6>[ 0.096139] CPU: Testing write buffer coherency: ok
566 21:56:43.814081 <6>[ 0.101506] CPU0: Spectre v2: using BPIALL workaround
567 21:56:43.814599 <6>[ 0.106972] pid_max: default: 32768 minimum: 301
568 21:56:43.825466 <6>[ 0.112169] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 21:56:43.832361 <6>[ 0.119992] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
570 21:56:43.839379 <6>[ 0.129338] CPU0: thread -1, cpu 0, socket -1, mpidr 0
571 21:56:43.905005 <6>[ 0.189523] Setting up static identity map for 0x80300000 - 0x803000ac
572 21:56:43.910935 <6>[ 0.199142] rcu: Hierarchical SRCU implementation.
573 21:56:43.914536 <6>[ 0.204431] rcu: Max phase no-delay instances is 1000.
574 21:56:43.923075 <6>[ 0.215441] EFI services will not be available.
575 21:56:43.928779 <6>[ 0.220786] smp: Bringing up secondary CPUs ...
576 21:56:43.934651 <6>[ 0.225754] smp: Brought up 1 node, 1 CPU
577 21:56:43.942640 <6>[ 0.230245] SMP: Total of 1 processors activated (996.14 BogoMIPS).
578 21:56:43.948653 <6>[ 0.236962] CPU: All CPU(s) started in SVC mode.
579 21:56:43.963490 <6>[ 0.242166] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
580 21:56:43.964071 <6>[ 0.258441] devtmpfs: initialized
581 21:56:43.988786 <6>[ 0.275518] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
582 21:56:44.000268 <6>[ 0.284123] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
583 21:56:44.006319 <6>[ 0.294565] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
584 21:56:44.016994 <6>[ 0.306834] pinctrl core: initialized pinctrl subsystem
585 21:56:44.026249 <6>[ 0.317457] DMI not present or invalid.
586 21:56:44.034626 <6>[ 0.323329] NET: Registered PF_NETLINK/PF_ROUTE protocol family
587 21:56:44.044073 <6>[ 0.332302] DMA: preallocated 256 KiB pool for atomic coherent allocations
588 21:56:44.059234 <6>[ 0.343754] thermal_sys: Registered thermal governor 'step_wise'
589 21:56:44.059774 <6>[ 0.343924] cpuidle: using governor menu
590 21:56:44.086756 <6>[ 0.379495] No ATAGs?
591 21:56:44.092883 <6>[ 0.382139] hw-breakpoint: debug architecture 0x4 unsupported.
592 21:56:44.102989 <6>[ 0.393997] Serial: AMBA PL011 UART driver
593 21:56:44.132281 <6>[ 0.424855] iommu: Default domain type: Translated
594 21:56:44.141227 <6>[ 0.430200] iommu: DMA domain TLB invalidation policy: strict mode
595 21:56:44.168694 <5>[ 0.460717] SCSI subsystem initialized
596 21:56:44.174435 <6>[ 0.465604] usbcore: registered new interface driver usbfs
597 21:56:44.180227 <6>[ 0.471632] usbcore: registered new interface driver hub
598 21:56:44.187129 <6>[ 0.477414] usbcore: registered new device driver usb
599 21:56:44.192743 <6>[ 0.483916] pps_core: LinuxPPS API ver. 1 registered
600 21:56:44.204212 <6>[ 0.489302] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
601 21:56:44.211415 <6>[ 0.499027] PTP clock support registered
602 21:56:44.211917 <6>[ 0.503487] EDAC MC: Ver: 3.0.0
603 21:56:44.262326 <6>[ 0.552454] scmi_core: SCMI protocol bus registered
604 21:56:44.286784 <6>[ 0.578851] vgaarb: loaded
605 21:56:44.292456 <6>[ 0.582692] clocksource: Switched to clocksource dmtimer
606 21:56:44.317229 <6>[ 0.609663] NET: Registered PF_INET protocol family
607 21:56:44.329783 <6>[ 0.615379] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
608 21:56:44.336906 <6>[ 0.624233] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
609 21:56:44.348361 <6>[ 0.633164] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
610 21:56:44.351392 <6>[ 0.641406] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
611 21:56:44.362726 <6>[ 0.649694] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
612 21:56:44.368645 <6>[ 0.657413] TCP: Hash tables configured (established 4096 bind 4096)
613 21:56:44.374406 <6>[ 0.664330] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
614 21:56:44.380209 <6>[ 0.671342] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
615 21:56:44.389407 <6>[ 0.678954] NET: Registered PF_UNIX/PF_LOCAL protocol family
616 21:56:44.475383 <6>[ 0.762531] RPC: Registered named UNIX socket transport module.
617 21:56:44.475908 <6>[ 0.768963] RPC: Registered udp transport module.
618 21:56:44.481258 <6>[ 0.774085] RPC: Registered tcp transport module.
619 21:56:44.486939 <6>[ 0.779187] RPC: Registered tcp-with-tls transport module.
620 21:56:44.499849 <6>[ 0.785117] RPC: Registered tcp NFSv4.1 backchannel transport module.
621 21:56:44.500348 <6>[ 0.792024] PCI: CLS 0 bytes, default 64
622 21:56:44.507103 <5>[ 0.797790] Initialise system trusted keyrings
623 21:56:44.528071 <6>[ 0.817852] Trying to unpack rootfs image as initramfs...
624 21:56:44.606521 <6>[ 0.893095] workingset: timestamp_bits=30 max_order=17 bucket_order=0
625 21:56:44.611347 <6>[ 0.900611] squashfs: version 4.0 (2009/01/31) Phillip Lougher
626 21:56:44.650742 <5>[ 0.943467] NFS: Registering the id_resolver key type
627 21:56:44.656570 <5>[ 0.949080] Key type id_resolver registered
628 21:56:44.662331 <5>[ 0.953772] Key type id_legacy registered
629 21:56:44.668132 <6>[ 0.958213] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
630 21:56:44.677604 <6>[ 0.965411] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
631 21:56:44.750487 <5>[ 1.043310] Key type asymmetric registered
632 21:56:44.756385 <5>[ 1.047836] Asymmetric key parser 'x509' registered
633 21:56:44.767926 <6>[ 1.053313] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
634 21:56:44.768552 <6>[ 1.061196] io scheduler mq-deadline registered
635 21:56:44.773700 <6>[ 1.066177] io scheduler kyber registered
636 21:56:44.778510 <6>[ 1.070631] io scheduler bfq registered
637 21:56:44.884349 <6>[ 1.173410] ledtrig-cpu: registered to indicate activity on CPUs
638 21:56:45.168047 <6>[ 1.457020] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
639 21:56:45.225647 <6>[ 1.518143] msm_serial: driver initialized
640 21:56:45.231538 <6>[ 1.523082] SuperH (H)SCI(F) driver initialized
641 21:56:45.237385 <6>[ 1.528192] STMicroelectronics ASC driver initialized
642 21:56:45.242645 <6>[ 1.533834] STM32 USART driver initialized
643 21:56:45.343165 <6>[ 1.635310] brd: module loaded
644 21:56:45.376140 <6>[ 1.668351] loop: module loaded
645 21:56:45.421323 <6>[ 1.713531] CAN device driver interface
646 21:56:45.427981 <6>[ 1.718495] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
647 21:56:45.433653 <6>[ 1.725536] e1000e: Intel(R) PRO/1000 Network Driver
648 21:56:45.439538 <6>[ 1.730923] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
649 21:56:45.445281 <6>[ 1.737386] igb: Intel(R) Gigabit Ethernet Network Driver
650 21:56:45.453516 <6>[ 1.743232] igb: Copyright (c) 2007-2014 Intel Corporation.
651 21:56:45.465259 <6>[ 1.752360] pegasus: Pegasus/Pegasus II USB Ethernet driver
652 21:56:45.471128 <6>[ 1.758511] usbcore: registered new interface driver pegasus
653 21:56:45.476891 <6>[ 1.764676] usbcore: registered new interface driver asix
654 21:56:45.482675 <6>[ 1.770527] usbcore: registered new interface driver ax88179_178a
655 21:56:45.488489 <6>[ 1.777118] usbcore: registered new interface driver cdc_ether
656 21:56:45.494284 <6>[ 1.783437] usbcore: registered new interface driver smsc75xx
657 21:56:45.499994 <6>[ 1.789644] usbcore: registered new interface driver smsc95xx
658 21:56:45.505876 <6>[ 1.795887] usbcore: registered new interface driver net1080
659 21:56:45.511622 <6>[ 1.802008] usbcore: registered new interface driver cdc_subset
660 21:56:45.517412 <6>[ 1.808426] usbcore: registered new interface driver zaurus
661 21:56:45.525071 <6>[ 1.814491] usbcore: registered new interface driver cdc_ncm
662 21:56:45.534943 <6>[ 1.824084] usbcore: registered new interface driver usb-storage
663 21:56:45.544235 <6>[ 1.835159] i2c_dev: i2c /dev entries driver
664 21:56:45.568241 <5>[ 1.853274] cpuidle: enable-method property 'ti,am3352' found operations
665 21:56:45.574106 <6>[ 1.862591] sdhci: Secure Digital Host Controller Interface driver
666 21:56:45.581525 <6>[ 1.869358] sdhci: Copyright(c) Pierre Ossman
667 21:56:45.588772 <6>[ 1.875774] Synopsys Designware Multimedia Card Interface Driver
668 21:56:45.594255 <6>[ 1.883744] sdhci-pltfm: SDHCI platform and OF driver helper
669 21:56:45.608179 <6>[ 1.893563] usbcore: registered new interface driver usbhid
670 21:56:45.608752 <6>[ 1.899588] usbhid: USB HID core driver
671 21:56:45.620916 <6>[ 1.910961] NET: Registered PF_INET6 protocol family
672 21:56:46.076066 <6>[ 2.368567] Segment Routing with IPv6
673 21:56:46.081439 <6>[ 2.372813] In-situ OAM (IOAM) with IPv6
674 21:56:46.088287 <6>[ 2.377222] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
675 21:56:46.093998 <6>[ 2.384553] NET: Registered PF_PACKET protocol family
676 21:56:46.099880 <6>[ 2.390042] can: controller area network core
677 21:56:46.105703 <6>[ 2.394938] NET: Registered PF_CAN protocol family
678 21:56:46.106260 <6>[ 2.400145] can: raw protocol
679 21:56:46.111423 <6>[ 2.403495] can: broadcast manager protocol
680 21:56:46.117950 <6>[ 2.408073] can: netlink gateway - max_hops=1
681 21:56:46.124017 <5>[ 2.413580] Key type dns_resolver registered
682 21:56:46.130362 <6>[ 2.418565] ThumbEE CPU extension supported.
683 21:56:46.130844 <5>[ 2.423337] Registering SWP/SWPB emulation handler
684 21:56:46.140019 <3>[ 2.428986] omap_voltage_late_init: Voltage driver support not added
685 21:56:46.332634 <5>[ 2.623051] Loading compiled-in X.509 certificates
686 21:56:46.461909 <6>[ 2.741812] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
687 21:56:46.469119 <6>[ 2.758488] pinctrl-single 44e10800.pinmux: 142 pins, size 568
688 21:56:46.495428 <3>[ 2.782146] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
689 21:56:46.699324 <3>[ 2.986998] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
690 21:56:46.881907 <6>[ 3.173239] OMAP GPIO hardware version 0.1
691 21:56:46.902816 <6>[ 3.191844] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
692 21:56:47.005958 <4>[ 3.295665] at24 2-0054: supply vcc not found, using dummy regulator
693 21:56:47.050460 <4>[ 3.339335] at24 2-0055: supply vcc not found, using dummy regulator
694 21:56:47.089629 <4>[ 3.378449] at24 2-0056: supply vcc not found, using dummy regulator
695 21:56:47.140066 <4>[ 3.428954] at24 2-0057: supply vcc not found, using dummy regulator
696 21:56:47.179304 <6>[ 3.468980] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
697 21:56:47.249945 <3>[ 3.535574] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
698 21:56:47.274531 <6>[ 3.556456] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
699 21:56:47.298221 <4>[ 3.582548] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
700 21:56:47.304656 <4>[ 3.593486] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
701 21:56:47.454740 <6>[ 3.743613] omap_rng 48310000.rng: Random Number Generator ver. 20
702 21:56:47.477912 <5>[ 3.769669] random: crng init done
703 21:56:47.526253 <6>[ 3.813751] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
704 21:56:47.554580 <6>[ 3.845745] Freeing initrd memory: 14448K
705 21:56:47.608514 <6>[ 3.895125] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
706 21:56:47.614384 <6>[ 3.905457] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
707 21:56:47.622551 <6>[ 3.912795] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
708 21:56:47.634086 <6>[ 3.920238] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
709 21:56:47.645680 <6>[ 3.928373] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
710 21:56:47.652971 <6>[ 3.940014] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:13:2b
711 21:56:47.663902 <5>[ 3.949053] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
712 21:56:47.691644 <3>[ 3.978787] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
713 21:56:47.697441 <6>[ 3.987374] edma 49000000.dma: TI EDMA DMA engine driver
714 21:56:47.768440 <3>[ 4.054808] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
715 21:56:47.782952 <6>[ 4.069167] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
716 21:56:47.796032 <3>[ 4.086230] l3-aon-clkctrl:0000:0: failed to disable
717 21:56:47.846643 <6>[ 4.133770] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
718 21:56:47.852371 <6>[ 4.143240] printk: legacy console [ttyS0] enabled
719 21:56:47.858086 <6>[ 4.143240] printk: legacy console [ttyS0] enabled
720 21:56:47.863766 <6>[ 4.153574] printk: legacy bootconsole [omap8250] disabled
721 21:56:47.869696 <6>[ 4.153574] printk: legacy bootconsole [omap8250] disabled
722 21:56:47.907343 <4>[ 4.193462] tps65217-pmic: Failed to locate of_node [id: -1]
723 21:56:47.910968 <4>[ 4.200859] tps65217-bl: Failed to locate of_node [id: -1]
724 21:56:47.927387 <6>[ 4.220477] tps65217 0-0024: TPS65217 ID 0xe version 1.2
725 21:56:47.947704 <6>[ 4.227423] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
726 21:56:47.959376 <6>[ 4.241116] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
727 21:56:47.962169 <6>[ 4.253019] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
728 21:56:47.985242 <6>[ 4.272629] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
729 21:56:47.991144 <6>[ 4.281810] sdhci-omap 48060000.mmc: Got CD GPIO
730 21:56:47.999203 <4>[ 4.286983] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
731 21:56:48.013855 <4>[ 4.300635] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
732 21:56:48.020266 <4>[ 4.309290] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
733 21:56:48.030128 <4>[ 4.317976] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
734 21:56:48.153918 <6>[ 4.442302] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
735 21:56:48.202893 <6>[ 4.489692] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
736 21:56:48.209291 <6>[ 4.498373] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
737 21:56:48.218485 <6>[ 4.507286] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
738 21:56:48.267670 <6>[ 4.552157] mmc0: new high speed SDHC card at address 0001
739 21:56:48.268285 <6>[ 4.559561] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
740 21:56:48.275148 <6>[ 4.567996] mmcblk0: p1
741 21:56:48.298509 <6>[ 4.582238] mmc1: new high speed MMC card at address 0001
742 21:56:48.299082 <6>[ 4.589298] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
743 21:56:48.310736 <6>[ 4.597065] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
744 21:56:48.317842 <6>[ 4.609128] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
745 21:56:48.325348 <6>[ 4.616602] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
746 21:56:48.340679 <6>[ 4.629893] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
747 21:56:50.466734 <6>[ 6.753724] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
748 21:56:50.570026 <5>[ 6.782717] Sending DHCP requests ., OK
749 21:56:50.581302 <6>[ 6.867151] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.10
750 21:56:50.581795 <6>[ 6.875322] IP-Config: Complete:
751 21:56:50.592675 <6>[ 6.878861] device=eth0, hwaddr=90:59:af:5b:13:2b, ipaddr=192.168.6.10, mask=255.255.255.0, gw=192.168.6.1
752 21:56:50.598363 <6>[ 6.889378] host=192.168.6.10, domain=, nis-domain=(none)
753 21:56:50.610671 <6>[ 6.895600] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
754 21:56:50.611152 <6>[ 6.895635] nameserver0=10.255.253.1
755 21:56:50.616932 <6>[ 6.908202] clk: Disabling unused clocks
756 21:56:50.621884 <6>[ 6.912989] PM: genpd: Disabling unused power domains
757 21:56:50.642120 <6>[ 6.931618] Freeing unused kernel image (initmem) memory: 2048K
758 21:56:50.649501 <6>[ 6.941349] Run /init as init process
759 21:56:50.674611 Loading, please wait...
760 21:56:50.750352 Starting systemd-udevd version 252.22-1~deb12u1
761 21:56:53.891575 <4>[ 10.178284] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
762 21:56:54.047158 <4>[ 10.333080] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
763 21:56:54.217639 <6>[ 10.510878] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
764 21:56:54.228635 <6>[ 10.516738] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
765 21:56:54.450315 <6>[ 10.742084] hub 1-0:1.0: USB hub found
766 21:56:54.483639 <6>[ 10.775277] hub 1-0:1.0: 1 port detected
767 21:56:54.574702 <6>[ 10.866129] tda998x 0-0070: found TDA19988
768 21:56:57.721168 Begin: Loading essential drivers ... done.
769 21:56:57.727395 Begin: Running /scripts/init-premount ... done.
770 21:56:57.738708 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
771 21:56:57.741994 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
772 21:56:57.749431 Device /sys/class/net/eth0 found
773 21:56:57.749950 done.
774 21:56:57.845014 Begin: Waiting up to 180 secs for any network device to become available ... done.
775 21:56:57.912966 IP-Config: eth0 hardware address 90:59:af:5b:13:2b mtu 1500 DHCP
776 21:56:58.001282 IP-Config: eth0 guessed broadcast address 192.168.6.255
777 21:56:58.006741 IP-Config: eth0 complete (dhcp from 192.168.6.1):
778 21:56:58.012357 address: 192.168.6.10 broadcast: 192.168.6.255 netmask: 255.255.255.0
779 21:56:58.021181 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
780 21:56:58.027030 rootserver: 192.168.6.1 rootpath:
781 21:56:58.027533 filename :
782 21:56:58.122000 done.
783 21:56:58.129391 Begin: Running /scripts/nfs-bottom ... done.
784 21:56:58.194404 Begin: Running /scripts/init-bottom ... done.
785 21:56:59.581802 <30>[ 15.871184] systemd[1]: System time before build time, advancing clock.
786 21:56:59.754810 <30>[ 16.017532] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
787 21:56:59.763134 <30>[ 16.054241] systemd[1]: Detected architecture arm.
788 21:56:59.775873
789 21:56:59.776478 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
790 21:56:59.776690
791 21:56:59.802703 <30>[ 16.093080] systemd[1]: Hostname set to <debian-bookworm-armhf>.
792 21:57:01.938212 <30>[ 18.226570] systemd[1]: Queued start job for default target graphical.target.
793 21:57:01.954845 <30>[ 18.241132] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
794 21:57:01.962354 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
795 21:57:01.989702 <30>[ 18.275081] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
796 21:57:01.997089 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
797 21:57:02.022206 <30>[ 18.308931] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
798 21:57:02.034974 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
799 21:57:02.057356 <30>[ 18.344515] systemd[1]: Created slice user.slice - User and Session Slice.
800 21:57:02.064073 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
801 21:57:02.093092 <30>[ 18.374089] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
802 21:57:02.099137 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
803 21:57:02.116979 <30>[ 18.403818] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
804 21:57:02.124848 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
805 21:57:02.157850 <30>[ 18.433878] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
806 21:57:02.164307 <30>[ 18.454359] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
807 21:57:02.171881 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
808 21:57:02.195970 <30>[ 18.483203] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
809 21:57:02.204235 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
810 21:57:02.226881 <30>[ 18.513642] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
811 21:57:02.235340 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
812 21:57:02.256498 <30>[ 18.543673] systemd[1]: Reached target paths.target - Path Units.
813 21:57:02.261736 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
814 21:57:02.286227 <30>[ 18.573348] systemd[1]: Reached target remote-fs.target - Remote File Systems.
815 21:57:02.292711 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
816 21:57:02.316179 <30>[ 18.603275] systemd[1]: Reached target slices.target - Slice Units.
817 21:57:02.321633 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
818 21:57:02.346351 <30>[ 18.633494] systemd[1]: Reached target swap.target - Swaps.
819 21:57:02.349862 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
820 21:57:02.376683 <30>[ 18.663527] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
821 21:57:02.385516 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
822 21:57:02.407441 <30>[ 18.694277] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
823 21:57:02.415760 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
824 21:57:02.494719 <30>[ 18.776855] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
825 21:57:02.507509 <30>[ 18.794539] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
826 21:57:02.515963 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
827 21:57:02.539211 <30>[ 18.825351] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
828 21:57:02.546624 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
829 21:57:02.568799 <30>[ 18.855776] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
830 21:57:02.576952 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
831 21:57:02.599182 <30>[ 18.887694] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
832 21:57:02.609628 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
833 21:57:02.635796 <30>[ 18.924482] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
834 21:57:02.647318 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
835 21:57:02.675128 <30>[ 18.956081] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
836 21:57:02.695701 <30>[ 18.976505] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
837 21:57:02.735987 <30>[ 19.023887] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
838 21:57:02.751008 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
839 21:57:02.783871 <30>[ 19.071611] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
840 21:57:02.808353 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
841 21:57:02.881102 <30>[ 19.167844] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
842 21:57:02.914408 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
843 21:57:02.956656 <30>[ 19.243980] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
844 21:57:02.978666 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
845 21:57:03.038451 <30>[ 19.326193] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
846 21:57:03.065739 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
847 21:57:03.119461 <30>[ 19.407526] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
848 21:57:03.145587 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
849 21:57:03.198512 <30>[ 19.485552] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
850 21:57:03.226534 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
851 21:57:03.278051 <30>[ 19.566184] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
852 21:57:03.305031 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
853 21:57:03.355093 <30>[ 19.644067] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
854 21:57:03.384434 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
855 21:57:03.413855 <28>[ 19.694949] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
856 21:57:03.422233 <28>[ 19.709436] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
857 21:57:03.465717 <30>[ 19.754226] systemd[1]: Starting systemd-journald.service - Journal Service...
858 21:57:03.484846 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
859 21:57:03.566492 <30>[ 19.854317] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
860 21:57:03.582146 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
861 21:57:03.637970 <30>[ 19.925953] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
862 21:57:03.695317 Starting [0;1;39msystemd-network-g… units from Kernel command line...
863 21:57:03.763007 <30>[ 20.049331] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
864 21:57:03.802049 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
865 21:57:03.868577 <30>[ 20.155886] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
866 21:57:03.935210 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
867 21:57:03.988128 <30>[ 20.276237] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
868 21:57:04.028240 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
869 21:57:04.046878 <30>[ 20.334829] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
870 21:57:04.092450 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
871 21:57:04.119439 <30>[ 20.406364] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
872 21:57:04.149143 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
873 21:57:04.298823 <30>[ 20.587481] systemd[1]: modprobe@configfs.service: Deactivated successfully.
874 21:57:04.336220 <30>[ 20.624604] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
875 21:57:04.366077 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
876 21:57:04.397198 <30>[ 20.684459] systemd[1]: Started systemd-journald.service - Journal Service.
877 21:57:04.404016 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
878 21:57:04.446340 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
879 21:57:04.476125 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
880 21:57:04.507493 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
881 21:57:04.531847 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
882 21:57:04.567276 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
883 21:57:04.596292 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
884 21:57:04.618595 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
885 21:57:04.639376 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
886 21:57:04.670805 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
887 21:57:04.735606 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
888 21:57:04.780207 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
889 21:57:04.839066 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
890 21:57:04.894795 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
891 21:57:04.976084 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
892 21:57:05.126465 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
893 21:57:05.219472 <46>[ 21.507499] systemd-journald[163]: Received client request to flush runtime journal.
894 21:57:05.318485 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
895 21:57:05.358593 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
896 21:57:06.168136 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
897 21:57:06.232800 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
898 21:57:06.897736 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
899 21:57:07.018085 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
900 21:57:07.037943 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
901 21:57:07.055667 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
902 21:57:07.141035 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
903 21:57:07.188064 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
904 21:57:08.131512 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
905 21:57:08.207383 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
906 21:57:08.421521 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
907 21:57:08.497183 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
908 21:57:08.567982 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
909 21:57:10.542829 [[0m[0;31m* [0m] (1 of 5) Job systemd-update-utmp.service/start running (8s / no limit)
910 21:57:10.660948 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
911 21:57:10.975256 [K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
912 21:57:11.064673 <5>[ 27.352607] cfg80211: Loading compiled-in X.509 certificates for regulatory database
913 21:57:11.892079 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
914 21:57:12.625567 <5>[ 28.916619] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
915 21:57:12.718871 <5>[ 29.007397] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
916 21:57:12.745202 <4>[ 29.033378] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
917 21:57:12.750466 <6>[ 29.042362] cfg80211: failed to load regulatory.db
918 21:57:13.060893 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
919 21:57:13.377430 <46>[ 29.656500] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
920 21:57:13.520108 <46>[ 29.801319] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
921 21:57:13.922206 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
922 21:57:22.358659 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
923 21:57:22.392319 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
924 21:57:22.416943 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
925 21:57:22.437310 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
926 21:57:22.511529 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
927 21:57:22.575655 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
928 21:57:22.617997 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
929 21:57:22.689068 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
930 21:57:22.736076 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
931 21:57:22.761868 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
932 21:57:22.793518 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
933 21:57:22.821438 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
934 21:57:22.862537 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
935 21:57:22.892927 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
936 21:57:22.929025 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
937 21:57:22.963968 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
938 21:57:23.009936 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
939 21:57:23.042415 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
940 21:57:23.066621 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
941 21:57:23.088637 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
942 21:57:23.138212 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
943 21:57:23.154442 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
944 21:57:23.178552 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
945 21:57:23.256650 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
946 21:57:23.334990 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
947 21:57:23.434362 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
948 21:57:23.535653 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
949 21:57:23.577357 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
950 21:57:23.618418 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
951 21:57:23.628439 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
952 21:57:23.848744 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
953 21:57:23.914109 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
954 21:57:23.977234 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
955 21:57:23.996033 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
956 21:57:24.017730 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
957 21:57:24.197744 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
958 21:57:24.540242 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
959 21:57:24.596244 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
960 21:57:24.619485 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
961 21:57:24.695997 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
962 21:57:24.881048 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
963 21:57:25.028957
964 21:57:25.031669 Debian GNU/Linux 12 worm-armhf login: root (automatic login)
965 21:57:25.032236
966 21:57:25.336781 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Wed Nov 6 21:36:50 UTC 2024 armv7l
967 21:57:25.337397
968 21:57:25.342350 The programs included with the Debian GNU/Linux system are free software;
969 21:57:25.345629 the exact distribution terms for each program are described in the
970 21:57:25.351256 individual files in /usr/share/doc/*/copyright.
971 21:57:25.351815
972 21:57:25.356825 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
973 21:57:25.360526 permitted by applicable law.
974 21:57:30.009619 Unable to match end of the kernel message
976 21:57:30.011305 Setting prompt string to ['/ #']
977 21:57:30.011909 end: 2.4.4.1 login-action (duration 00:00:47) [common]
979 21:57:30.013786 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
980 21:57:30.014501 start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
981 21:57:30.015058 Setting prompt string to ['/ #']
982 21:57:30.015516 Forcing a shell prompt, looking for ['/ #']
984 21:57:30.066556 / #
985 21:57:30.067345 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
986 21:57:30.067871 Waiting using forced prompt support (timeout 00:02:30)
987 21:57:30.072540
988 21:57:30.082256 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
989 21:57:30.082903 start: 2.4.6 export-device-env (timeout 00:03:12) [common]
990 21:57:30.083442 Sending with 10 millisecond of delay
992 21:57:35.076260 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/949303/extract-nfsrootfs-w_ovq08x'
993 21:57:35.087238 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/949303/extract-nfsrootfs-w_ovq08x'
994 21:57:35.088326 Sending with 10 millisecond of delay
996 21:57:37.186734 / # export NFS_SERVER_IP='192.168.6.3'
997 21:57:37.197545 export NFS_SERVER_IP='192.168.6.3'
998 21:57:37.199029 end: 2.4.6 export-device-env (duration 00:00:07) [common]
999 21:57:37.199389 end: 2.4 uboot-commands (duration 00:01:55) [common]
1000 21:57:37.199705 end: 2 uboot-action (duration 00:01:55) [common]
1001 21:57:37.200004 start: 3 lava-test-retry (timeout 00:06:53) [common]
1002 21:57:37.200312 start: 3.1 lava-test-shell (timeout 00:06:53) [common]
1003 21:57:37.200556 Using namespace: common
1005 21:57:37.301276 / # #
1006 21:57:37.301933 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1007 21:57:37.306719 #
1008 21:57:37.312249 Using /lava-949303
1010 21:57:37.413036 / # export SHELL=/bin/bash
1011 21:57:37.417242 export SHELL=/bin/bash
1013 21:57:37.524520 / # . /lava-949303/environment
1014 21:57:37.529875 . /lava-949303/environment
1016 21:57:37.642244 / # /lava-949303/bin/lava-test-runner /lava-949303/0
1017 21:57:37.642867 Test shell timeout: 10s (minimum of the action and connection timeout)
1018 21:57:37.646815 /lava-949303/bin/lava-test-runner /lava-949303/0
1019 21:57:38.024823 + export TESTRUN_ID=0_timesync-off
1020 21:57:38.031807 + TESTRUN_ID=0_timesync-off
1021 21:57:38.032094 + cd /lava-949303/0/tests/0_timesync-off
1022 21:57:38.032320 ++ cat uuid
1023 21:57:38.048496 + UUID=949303_1.6.2.4.1
1024 21:57:38.048797 + set +x
1025 21:57:38.056110 <LAVA_SIGNAL_STARTRUN 0_timesync-off 949303_1.6.2.4.1>
1026 21:57:38.056390 + systemctl stop systemd-timesyncd
1027 21:57:38.056845 Received signal: <STARTRUN> 0_timesync-off 949303_1.6.2.4.1
1028 21:57:38.057090 Starting test lava.0_timesync-off (949303_1.6.2.4.1)
1029 21:57:38.057378 Skipping test definition patterns.
1030 21:57:38.351425 + set +x
1031 21:57:38.351825 <LAVA_SIGNAL_ENDRUN 0_timesync-off 949303_1.6.2.4.1>
1032 21:57:38.352269 Received signal: <ENDRUN> 0_timesync-off 949303_1.6.2.4.1
1033 21:57:38.352543 Ending use of test pattern.
1034 21:57:38.352755 Ending test lava.0_timesync-off (949303_1.6.2.4.1), duration 0.30
1036 21:57:38.554371 + export TESTRUN_ID=1_kselftest-dt
1037 21:57:38.561286 + TESTRUN_ID=1_kselftest-dt
1038 21:57:38.561568 + cd /lava-949303/0/tests/1_kselftest-dt
1039 21:57:38.561786 ++ cat uuid
1040 21:57:38.578071 + UUID=949303_1.6.2.4.5
1041 21:57:38.578376 + set +x
1042 21:57:38.583603 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 949303_1.6.2.4.5>
1043 21:57:38.583861 + cd ./automated/linux/kselftest/
1044 21:57:38.584286 Received signal: <STARTRUN> 1_kselftest-dt 949303_1.6.2.4.5
1045 21:57:38.584511 Starting test lava.1_kselftest-dt (949303_1.6.2.4.5)
1046 21:57:38.584768 Skipping test definition patterns.
1047 21:57:38.611821 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1048 21:57:38.719121 INFO: install_deps skipped
1049 21:57:39.367834 --2024-11-06 21:57:39-- http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1050 21:57:39.393018 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1051 21:57:39.538528 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1052 21:57:39.684567 HTTP request sent, awaiting response... 200 OK
1053 21:57:39.684958 Length: 4105936 (3.9M) [application/octet-stream]
1054 21:57:39.690099 Saving to: 'kselftest_armhf.tar.gz'
1055 21:57:39.690477
1056 21:57:41.482617
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 44.73K 158KB/s
kselftest_armhf.tar 5%[> ] 208.82K 359KB/s
kselftest_armhf.tar 20%[===> ] 806.92K 879KB/s
kselftest_armhf.tar 48%[========> ] 1.90M 1.67MB/s
kselftest_armhf.tar 59%[==========> ] 2.32M 1.71MB/s
kselftest_armhf.tar 81%[===============> ] 3.19M 2.03MB/s
kselftest_armhf.tar 97%[==================> ] 3.81M 2.15MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 2.19MB/s in 1.8s
1057 21:57:41.483762
1058 21:57:42.029968 2024-11-06 21:57:41 (2.19 MB/s) - 'kselftest_armhf.tar.gz' saved [4105936/4105936]
1059 21:57:42.030668
1060 21:57:57.592028 skiplist:
1061 21:57:57.592680 ========================================
1062 21:57:57.597755 ========================================
1063 21:57:57.697844 dt:test_unprobed_devices.sh
1064 21:57:57.731665 ============== Tests to run ===============
1065 21:57:57.740548 dt:test_unprobed_devices.sh
1066 21:57:57.744632 ===========End Tests to run ===============
1067 21:57:57.752785 shardfile-dt pass
1068 21:57:57.978881 <12>[ 74.272519] kselftest: Running tests in dt
1069 21:57:58.010396 TAP version 13
1070 21:57:58.032381 1..1
1071 21:57:58.086556 # timeout set to 45
1072 21:57:58.087080 # selftests: dt: test_unprobed_devices.sh
1073 21:57:58.946152 # TAP version 13
1074 21:58:23.924633 # 1..257
1075 21:58:24.088092 # ok 1 / # SKIP
1076 21:58:24.114475 # ok 2 /clk_mcasp0
1077 21:58:24.187640 # ok 3 /clk_mcasp0_fixed # SKIP
1078 21:58:24.253258 # ok 4 /cpus/cpu@0 # SKIP
1079 21:58:24.324914 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1080 21:58:24.345095 # ok 6 /fixedregulator0
1081 21:58:24.365782 # ok 7 /leds
1082 21:58:24.386129 # ok 8 /ocp
1083 21:58:24.410641 # ok 9 /ocp/interconnect@44c00000
1084 21:58:24.437504 # ok 10 /ocp/interconnect@44c00000/segment@0
1085 21:58:24.456581 # ok 11 /ocp/interconnect@44c00000/segment@100000
1086 21:58:24.485555 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1087 21:58:24.553345 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1088 21:58:24.576736 # ok 14 /ocp/interconnect@44c00000/segment@200000
1089 21:58:24.600738 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1090 21:58:24.706944 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1091 21:58:24.779420 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1092 21:58:24.851618 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1093 21:58:24.923451 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1094 21:58:24.991496 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1095 21:58:25.066368 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1096 21:58:25.138949 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1097 21:58:25.211919 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1098 21:58:25.283412 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1099 21:58:25.351850 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1100 21:58:25.423914 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1101 21:58:25.495954 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1102 21:58:25.567890 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1103 21:58:25.640049 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1104 21:58:25.711849 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1105 21:58:25.783047 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1106 21:58:25.854524 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1107 21:58:25.928684 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1108 21:58:25.998617 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1109 21:58:26.073576 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1110 21:58:26.144718 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1111 21:58:26.213726 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1112 21:58:26.291180 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1113 21:58:26.362678 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1114 21:58:26.433760 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1115 21:58:26.501867 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1116 21:58:26.574901 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1117 21:58:26.648489 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1118 21:58:26.723320 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1119 21:58:26.794501 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1120 21:58:26.862891 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1121 21:58:26.938977 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1122 21:58:27.010667 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1123 21:58:27.082805 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1124 21:58:27.154268 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1125 21:58:27.222475 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1126 21:58:27.296507 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1127 21:58:27.370927 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1128 21:58:27.443932 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1129 21:58:27.514292 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1130 21:58:27.581886 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1131 21:58:27.653448 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1132 21:58:27.735123 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1133 21:58:27.809876 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1134 21:58:27.882068 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1135 21:58:27.953269 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1136 21:58:28.023655 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1137 21:58:28.091850 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1138 21:58:28.164114 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1139 21:58:28.233355 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1140 21:58:28.312440 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1141 21:58:28.384675 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1142 21:58:28.452329 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1143 21:58:28.526550 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1144 21:58:28.597495 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1145 21:58:28.672142 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1146 21:58:28.747130 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1147 21:58:28.815628 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1148 21:58:28.888548 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1149 21:58:28.961069 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1150 21:58:29.032799 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1151 21:58:29.105852 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1152 21:58:29.180656 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1153 21:58:29.252451 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1154 21:58:29.324195 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1155 21:58:29.393919 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1156 21:58:29.465576 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1157 21:58:29.541510 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1158 21:58:29.613214 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1159 21:58:29.681279 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1160 21:58:29.755415 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1161 21:58:29.830596 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1162 21:58:29.903191 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1163 21:58:29.975326 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1164 21:58:30.051890 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1165 21:58:30.121374 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1166 21:58:30.195132 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1167 21:58:30.263287 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1168 21:58:30.340716 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1169 21:58:30.357188 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1170 21:58:30.380501 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1171 21:58:30.404989 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1172 21:58:30.428256 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1173 21:58:30.455454 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1174 21:58:30.480573 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1175 21:58:30.501752 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1176 21:58:30.526964 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1177 21:58:30.631809 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1178 21:58:30.656212 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1179 21:58:30.677640 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1180 21:58:30.702450 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1181 21:58:30.808325 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1182 21:58:30.882399 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1183 21:58:30.961283 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1184 21:58:31.033505 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1185 21:58:31.105077 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1186 21:58:31.173606 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1187 21:58:31.246676 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1188 21:58:31.318475 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1189 21:58:31.390760 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1190 21:58:31.463238 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1191 21:58:31.537609 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1192 21:58:31.612896 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1193 21:58:31.683592 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1194 21:58:31.760206 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1195 21:58:31.830217 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1196 21:58:31.902458 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1197 21:58:31.926182 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1198 21:58:31.993454 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1199 21:58:32.065272 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1200 21:58:32.137796 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1201 21:58:32.159327 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1202 21:58:32.231856 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1203 21:58:32.253742 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1204 21:58:32.324593 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1205 21:58:32.346585 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1206 21:58:32.371466 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1207 21:58:32.397790 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1208 21:58:32.421571 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1209 21:58:32.440040 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1210 21:58:32.464611 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1211 21:58:32.490087 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1212 21:58:32.564281 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1213 21:58:32.585994 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1214 21:58:32.608917 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1215 21:58:32.681218 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1216 21:58:32.752518 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1217 21:58:32.774277 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1218 21:58:32.876329 # not ok 144 /ocp/interconnect@47c00000
1219 21:58:32.949229 # not ok 145 /ocp/interconnect@47c00000/segment@0
1220 21:58:32.969996 # ok 146 /ocp/interconnect@48000000
1221 21:58:32.996983 # ok 147 /ocp/interconnect@48000000/segment@0
1222 21:58:33.020492 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1223 21:58:33.045381 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1224 21:58:33.068373 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1225 21:58:33.090585 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1226 21:58:33.114682 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1227 21:58:33.139103 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1228 21:58:33.160634 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1229 21:58:33.229710 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1230 21:58:33.302624 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1231 21:58:33.324423 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1232 21:58:33.348364 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1233 21:58:33.375361 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1234 21:58:33.399240 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1235 21:58:33.420687 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1236 21:58:33.441941 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1237 21:58:33.464444 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1238 21:58:33.488214 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1239 21:58:33.515262 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1240 21:58:33.539643 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1241 21:58:33.560636 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1242 21:58:33.581935 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1243 21:58:33.604667 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1244 21:58:33.628479 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1245 21:58:33.651069 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1246 21:58:33.679618 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1247 21:58:33.700516 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1248 21:58:33.722216 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1249 21:58:33.742594 # ok 175 /ocp/interconnect@48000000/segment@100000
1250 21:58:33.766306 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1251 21:58:33.795940 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1252 21:58:33.865284 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1253 21:58:33.938562 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1254 21:58:34.008791 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1255 21:58:34.082417 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1256 21:58:34.153204 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1257 21:58:34.224735 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1258 21:58:34.300933 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1259 21:58:34.374484 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1260 21:58:34.393870 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1261 21:58:34.414665 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1262 21:58:34.437938 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1263 21:58:34.465738 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1264 21:58:34.489240 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1265 21:58:34.511397 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1266 21:58:34.532713 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1267 21:58:34.561482 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1268 21:58:34.579613 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1269 21:58:34.603160 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1270 21:58:34.626075 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1271 21:58:34.650163 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1272 21:58:34.671017 # ok 198 /ocp/interconnect@48000000/segment@200000
1273 21:58:34.699265 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1274 21:58:34.771648 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1275 21:58:34.792857 # ok 201 /ocp/interconnect@48000000/segment@300000
1276 21:58:34.813870 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1277 21:58:34.840822 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1278 21:58:34.866006 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1279 21:58:34.884921 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1280 21:58:34.907973 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1281 21:58:34.930841 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1282 21:58:35.006878 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1283 21:58:35.025361 # ok 209 /ocp/interconnect@4a000000
1284 21:58:35.047694 # ok 210 /ocp/interconnect@4a000000/segment@0
1285 21:58:35.074023 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1286 21:58:35.098736 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1287 21:58:35.121895 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1288 21:58:35.142086 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1289 21:58:35.214073 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1290 21:58:35.318721 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1291 21:58:35.393856 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1292 21:58:35.494417 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1293 21:58:35.565042 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1294 21:58:35.635437 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1295 21:58:35.733919 # not ok 221 /ocp/interconnect@4b140000
1296 21:58:35.804736 # not ok 222 /ocp/interconnect@4b140000/segment@0
1297 21:58:35.876553 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1298 21:58:35.898272 # ok 224 /ocp/target-module@40300000
1299 21:58:35.925574 # ok 225 /ocp/target-module@40300000/sram@0
1300 21:58:35.998932 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1301 21:58:36.070588 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1302 21:58:36.086403 # ok 228 /ocp/target-module@47400000
1303 21:58:36.115439 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1304 21:58:36.133158 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1305 21:58:36.158933 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1306 21:58:36.177956 # ok 232 /ocp/target-module@47400000/usb@1400
1307 21:58:36.200792 # ok 233 /ocp/target-module@47400000/usb@1800
1308 21:58:36.222215 # ok 234 /ocp/target-module@47810000
1309 21:58:36.244595 # ok 235 /ocp/target-module@49000000
1310 21:58:36.268373 # ok 236 /ocp/target-module@49000000/dma@0
1311 21:58:36.289749 # ok 237 /ocp/target-module@49800000
1312 21:58:36.316672 # ok 238 /ocp/target-module@49800000/dma@0
1313 21:58:36.337751 # ok 239 /ocp/target-module@49900000
1314 21:58:36.365047 # ok 240 /ocp/target-module@49900000/dma@0
1315 21:58:36.380797 # ok 241 /ocp/target-module@49a00000
1316 21:58:36.407687 # ok 242 /ocp/target-module@49a00000/dma@0
1317 21:58:36.428128 # ok 243 /ocp/target-module@4c000000
1318 21:58:36.497907 # not ok 244 /ocp/target-module@4c000000/emif@0
1319 21:58:36.519379 # ok 245 /ocp/target-module@50000000
1320 21:58:36.541472 # ok 246 /ocp/target-module@53100000
1321 21:58:36.617286 # not ok 247 /ocp/target-module@53100000/sham@0
1322 21:58:36.637674 # ok 248 /ocp/target-module@53500000
1323 21:58:36.727015 # not ok 249 /ocp/target-module@53500000/aes@0
1324 21:58:36.750428 # ok 250 /ocp/target-module@56000000
1325 21:58:36.880589 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1326 21:58:36.952612 # ok 252 /opp-table # SKIP
1327 21:58:37.016933 # ok 253 /soc # SKIP
1328 21:58:37.042179 # ok 254 /sound
1329 21:58:37.060491 # ok 255 /target-module@4b000000
1330 21:58:37.085601 # ok 256 /target-module@4b000000/target-module@140000
1331 21:58:37.107369 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1332 21:58:37.114715 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1333 21:58:37.123655 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1334 21:58:39.568281 dt_test_unprobed_devices_sh_ skip
1335 21:58:39.569654 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1336 21:58:39.569960 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1337 21:58:39.570181 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1338 21:58:39.570389 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1339 21:58:39.570597 dt_test_unprobed_devices_sh_fixedregulator0 pass
1340 21:58:39.571118 dt_test_unprobed_devices_sh_leds pass
1341 21:58:39.571350 dt_test_unprobed_devices_sh_ocp pass
1342 21:58:39.571556 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1343 21:58:39.571761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1344 21:58:39.571962 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1345 21:58:39.572165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1346 21:58:39.572365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1347 21:58:39.572564 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1348 21:58:39.572761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1349 21:58:39.572959 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1350 21:58:39.573159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1351 21:58:39.573359 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1352 21:58:39.573560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1353 21:58:39.573760 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1354 21:58:39.573992 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1355 21:58:39.574195 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1356 21:58:39.574393 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1357 21:58:39.574592 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1358 21:58:39.574791 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1359 21:58:39.574988 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1360 21:58:39.575185 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1361 21:58:39.580619 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1362 21:58:39.590877 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1363 21:58:39.596467 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1364 21:58:39.607869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1365 21:58:39.618843 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1366 21:58:39.630120 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1367 21:58:39.635704 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1368 21:58:39.646840 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1369 21:58:39.658031 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1370 21:58:39.669204 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1371 21:58:39.680388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1372 21:58:39.691576 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1373 21:58:39.697177 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1374 21:58:39.708341 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1375 21:58:39.719573 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1376 21:58:39.730744 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1377 21:58:39.742055 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1378 21:58:39.753142 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1379 21:58:39.764315 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1380 21:58:39.775516 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1381 21:58:39.786711 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1382 21:58:39.797932 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1383 21:58:39.809171 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1384 21:58:39.820298 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1385 21:58:39.831477 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1386 21:58:39.842668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1387 21:58:39.853882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1388 21:58:39.865173 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1389 21:58:39.876254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1390 21:58:39.887470 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1391 21:58:39.898642 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1392 21:58:39.909836 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1393 21:58:39.921069 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1394 21:58:39.932332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1395 21:58:39.943611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1396 21:58:39.954714 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1397 21:58:39.965905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1398 21:58:39.977067 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1399 21:58:39.982804 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1400 21:58:39.993826 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1401 21:58:40.005044 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1402 21:58:40.016270 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1403 21:58:40.027393 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1404 21:58:40.038619 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1405 21:58:40.049757 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1406 21:58:40.060999 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1407 21:58:40.072409 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1408 21:58:40.083901 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1409 21:58:40.095580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1410 21:58:40.105999 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1411 21:58:40.117088 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1412 21:58:40.128237 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1413 21:58:40.139556 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1414 21:58:40.150749 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1415 21:58:40.161806 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1416 21:58:40.172885 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1417 21:58:40.178503 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1418 21:58:40.189652 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1419 21:58:40.200955 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1420 21:58:40.212122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1421 21:58:40.223361 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1422 21:58:40.234446 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1423 21:58:40.245718 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1424 21:58:40.256912 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1425 21:58:40.268151 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1426 21:58:40.279334 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1427 21:58:40.290594 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1428 21:58:40.301780 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1429 21:58:40.307463 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1430 21:58:40.318639 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1431 21:58:40.329776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1432 21:58:40.335390 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1433 21:58:40.346597 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1434 21:58:40.357797 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1435 21:58:40.363367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1436 21:58:40.374687 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1437 21:58:40.380188 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1438 21:58:40.391501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1439 21:58:40.402674 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1440 21:58:40.413874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1441 21:58:40.425089 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1442 21:58:40.436321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1443 21:58:40.447400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1444 21:58:40.458569 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1445 21:58:40.469881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1446 21:58:40.480941 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1447 21:58:40.492150 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1448 21:58:40.508911 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1449 21:58:40.520267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1450 21:58:40.531470 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1451 21:58:40.542496 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1452 21:58:40.553719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1453 21:58:40.570447 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1454 21:58:40.581728 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1455 21:58:40.592850 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1456 21:58:40.604060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1457 21:58:40.615334 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1458 21:58:40.626484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1459 21:58:40.632157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1460 21:58:40.643289 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1461 21:58:40.648943 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1462 21:58:40.660170 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1463 21:58:40.665746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1464 21:58:40.677015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1465 21:58:40.682529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1466 21:58:40.693737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1467 21:58:40.699209 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1468 21:58:40.710530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1469 21:58:40.716199 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1470 21:58:41.007195 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1471 21:58:41.008312 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1472 21:58:41.008820 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1473 21:58:41.009273 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1474 21:58:41.009716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1475 21:58:41.010216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1476 21:58:41.010654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1477 21:58:41.011090 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1478 21:58:41.011521 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1479 21:58:41.011950 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1480 21:58:41.012374 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1481 21:58:41.012969 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1482 21:58:41.013412 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1483 21:58:41.013866 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1484 21:58:41.014300 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1485 21:58:41.014728 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1486 21:58:41.015153 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1487 21:58:41.015576 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1488 21:58:41.015997 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1489 21:58:41.016419 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1490 21:58:41.016838 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1491 21:58:41.017261 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1492 21:58:41.017682 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1493 21:58:41.018247 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1494 21:58:41.018676 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1495 21:58:41.019101 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1496 21:58:41.019523 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1497 21:58:41.019946 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1498 21:58:41.020372 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1499 21:58:41.020791 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1500 21:58:41.021210 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1501 21:58:41.021659 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1502 21:58:41.022126 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1503 21:58:41.022548 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1504 21:58:41.022990 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1505 21:58:41.023569 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1506 21:58:41.024018 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1507 21:58:41.029572 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1508 21:58:41.041000 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1509 21:58:41.046400 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1510 21:58:41.057563 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1511 21:58:41.063204 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1512 21:58:41.074419 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1513 21:58:41.085578 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1514 21:58:41.096736 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1515 21:58:41.108026 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1516 21:58:41.119190 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1517 21:58:41.130527 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1518 21:58:41.141542 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1519 21:58:41.152721 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1520 21:58:41.158371 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1521 21:58:41.163993 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1522 21:58:41.175121 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1523 21:58:41.180871 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1524 21:58:41.191941 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1525 21:58:41.203095 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1526 21:58:41.208852 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1527 21:58:41.219874 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1528 21:58:41.225513 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1529 21:58:41.236633 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1530 21:58:41.242314 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1531 21:58:41.247873 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1532 21:58:41.259059 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1533 21:58:41.264719 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1534 21:58:41.270232 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1535 21:58:41.281497 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1536 21:58:41.286999 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1537 21:58:41.298178 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1538 21:58:41.303893 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1539 21:58:41.314991 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1540 21:58:41.320626 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1541 21:58:41.331804 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1542 21:58:41.337499 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1543 21:58:41.342986 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1544 21:58:41.348595 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1545 21:58:41.359803 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1546 21:58:41.371018 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1547 21:58:41.376665 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1548 21:58:41.387989 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1549 21:58:41.393515 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1550 21:58:41.404566 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1551 21:58:41.415863 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1552 21:58:41.427056 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1553 21:58:41.432628 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1554 21:58:41.438246 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1555 21:58:41.443850 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1556 21:58:41.455044 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1557 21:58:41.455504 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1558 21:58:41.466234 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1559 21:58:41.471871 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1560 21:58:41.477490 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1561 21:58:41.483039 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1562 21:58:41.488653 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1563 21:58:41.499943 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1564 21:58:41.505488 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1565 21:58:41.511050 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1566 21:58:41.516635 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1567 21:58:41.522230 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1568 21:58:41.527830 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1569 21:58:41.533478 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1570 21:58:41.539011 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1571 21:58:41.544993 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1572 21:58:41.550238 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1573 21:58:41.555819 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1574 21:58:41.561493 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1575 21:58:41.567029 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1576 21:58:41.572631 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1577 21:58:41.578213 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1578 21:58:41.583932 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1579 21:58:41.589513 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1580 21:58:41.595043 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1581 21:58:41.600617 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1582 21:58:41.606216 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1583 21:58:41.611833 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1584 21:58:41.617459 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1585 21:58:41.623001 dt_test_unprobed_devices_sh_opp-table skip
1586 21:58:41.623358 dt_test_unprobed_devices_sh_soc skip
1587 21:58:41.629023 dt_test_unprobed_devices_sh_sound pass
1588 21:58:41.634325 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1589 21:58:41.639919 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1590 21:58:41.645507 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1591 21:58:41.651165 dt_test_unprobed_devices_sh fail
1592 21:58:41.656790 + ../../utils/send-to-lava.sh ./output/result.txt
1593 21:58:41.657309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1594 21:58:41.658246 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1596 21:58:41.666630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1597 21:58:41.667443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1599 21:58:41.746152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1600 21:58:41.747010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1602 21:58:41.838878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1603 21:58:41.839650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1605 21:58:41.929481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1606 21:58:41.930271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1608 21:58:42.025118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1609 21:58:42.025948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1611 21:58:42.114843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1612 21:58:42.115609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1614 21:58:42.204742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1615 21:58:42.205548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1617 21:58:42.295871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1618 21:58:42.296637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1620 21:58:42.390299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1621 21:58:42.391084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1623 21:58:42.485211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1624 21:58:42.485979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1626 21:58:42.578043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1627 21:58:42.578791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1629 21:58:42.668746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1630 21:58:42.669484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1632 21:58:42.759477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1633 21:58:42.760218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1635 21:58:42.847203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1636 21:58:42.847953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1638 21:58:42.940799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1639 21:58:42.941608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1641 21:58:43.034217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1642 21:58:43.034968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1644 21:58:43.130938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1645 21:58:43.131704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1647 21:58:43.223668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1648 21:58:43.224431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1650 21:58:43.315852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1651 21:58:43.316597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1653 21:58:43.411536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1654 21:58:43.412380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1656 21:58:43.502850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1657 21:58:43.503687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1659 21:58:43.596129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1660 21:58:43.596973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1662 21:58:43.689702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1663 21:58:43.690526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1665 21:58:43.781025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1666 21:58:43.781878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1668 21:58:43.873475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1669 21:58:43.874294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1671 21:58:43.964849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1672 21:58:43.965683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1674 21:58:44.061242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1675 21:58:44.062163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1677 21:58:44.158702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1678 21:58:44.159585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1680 21:58:44.277012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1681 21:58:44.278067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1683 21:58:44.374644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1684 21:58:44.375322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1686 21:58:44.472641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1687 21:58:44.473546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1689 21:58:44.568797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1690 21:58:44.571829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1692 21:58:44.670409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1693 21:58:44.671430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1695 21:58:44.763399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1696 21:58:44.764235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1698 21:58:44.856318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1699 21:58:44.857043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1701 21:58:44.948262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1702 21:58:44.949061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1704 21:58:45.041721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1705 21:58:45.042708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1707 21:58:45.133858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1708 21:58:45.134814 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1710 21:58:45.226102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1711 21:58:45.226936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1713 21:58:45.318746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1714 21:58:45.319606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1716 21:58:45.411570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1717 21:58:45.412433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1719 21:58:45.508748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1720 21:58:45.511887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1722 21:58:45.599560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1723 21:58:45.600487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1725 21:58:45.696765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1726 21:58:45.697757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1728 21:58:45.790141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1729 21:58:45.790987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1731 21:58:45.883941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1732 21:58:45.884847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1734 21:58:45.976223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1735 21:58:45.977275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1737 21:58:46.069666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1738 21:58:46.070583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1740 21:58:46.160033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1741 21:58:46.160901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1743 21:58:46.252754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1744 21:58:46.253637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1746 21:58:46.343580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1747 21:58:46.344523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1749 21:58:46.437084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1750 21:58:46.437982 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1752 21:58:46.529460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1753 21:58:46.530386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1755 21:58:46.622961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1756 21:58:46.623888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1758 21:58:46.715612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1759 21:58:46.716522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1761 21:58:46.810259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1762 21:58:46.811122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1764 21:58:46.902746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1765 21:58:46.903606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1767 21:58:46.992068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1768 21:58:46.992881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1770 21:58:47.083839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1771 21:58:47.084740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1773 21:58:47.176111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1774 21:58:47.176990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1776 21:58:47.268084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1777 21:58:47.268926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1779 21:58:47.360139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1780 21:58:47.361017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1782 21:58:47.453078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1783 21:58:47.453918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1785 21:58:47.545555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1786 21:58:47.546433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1788 21:58:47.639991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1789 21:58:47.640635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1791 21:58:47.732902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1792 21:58:47.733595 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1794 21:58:47.826336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1795 21:58:47.827025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1797 21:58:47.918716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1798 21:58:47.919367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1800 21:58:48.010623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1801 21:58:48.011270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1803 21:58:48.103327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1804 21:58:48.103981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1806 21:58:48.197987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1807 21:58:48.198724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1809 21:58:48.291034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1810 21:58:48.291707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1812 21:58:48.382493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1813 21:58:48.383155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1815 21:58:48.474984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1816 21:58:48.475644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1818 21:58:48.567434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1819 21:58:48.568307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1821 21:58:48.659978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1822 21:58:48.660816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1824 21:58:48.760964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1825 21:58:48.761775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1827 21:58:48.861657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1828 21:58:48.862511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1830 21:58:48.962880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1831 21:58:48.963695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1833 21:58:49.064275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1834 21:58:49.065129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1836 21:58:49.155714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1837 21:58:49.156517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1839 21:58:49.249258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1840 21:58:49.250204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1842 21:58:49.340368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1843 21:58:49.341210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1845 21:58:49.432420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1846 21:58:49.433248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1848 21:58:49.529506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1849 21:58:49.530320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1851 21:58:49.622307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1852 21:58:49.623165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1854 21:58:49.715129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1855 21:58:49.716010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1857 21:58:49.816562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1858 21:58:49.817443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1860 21:58:49.911359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1861 21:58:49.912235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1863 21:58:50.003742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1864 21:58:50.004641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1866 21:58:50.092214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1867 21:58:50.093138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1869 21:58:50.187019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1870 21:58:50.187955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1872 21:58:50.280487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1873 21:58:50.281572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1875 21:58:50.375253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1876 21:58:50.376587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1878 21:58:50.464151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1879 21:58:50.465451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1881 21:58:50.558574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1882 21:58:50.559413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1884 21:58:50.651611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1885 21:58:50.652483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1887 21:58:50.743577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1888 21:58:50.744888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1890 21:58:50.836763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1891 21:58:50.838001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1893 21:58:50.929647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1894 21:58:50.930982 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1896 21:58:51.021848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1897 21:58:51.023160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1899 21:58:51.112066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1900 21:58:51.113333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1902 21:58:51.204926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1903 21:58:51.205779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1905 21:58:51.299639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1906 21:58:51.300485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1908 21:58:51.391411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1909 21:58:51.392266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1911 21:58:51.482330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1912 21:58:51.483172 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1914 21:58:51.575080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1915 21:58:51.576039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1917 21:58:51.678120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1918 21:58:51.679034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1920 21:58:51.770968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1921 21:58:51.771812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1923 21:58:51.864074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1924 21:58:51.864935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1926 21:58:51.956004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1927 21:58:51.956971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1929 21:58:52.051022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1930 21:58:52.051886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1932 21:58:52.141908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1933 21:58:52.142719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1935 21:58:52.232591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1936 21:58:52.233390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1938 21:58:52.322798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1939 21:58:52.323599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1941 21:58:52.416935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1942 21:58:52.418959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1944 21:58:52.511143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1945 21:58:52.511980 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1947 21:58:52.603534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1948 21:58:52.604403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1950 21:58:52.694648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1951 21:58:52.695560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1953 21:58:52.785933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1955 21:58:52.789034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1956 21:58:52.879375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1958 21:58:52.882523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1959 21:58:52.971489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1961 21:58:52.975157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1962 21:58:53.064518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1963 21:58:53.065317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1965 21:58:53.156861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1966 21:58:53.157539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1968 21:58:53.247219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1969 21:58:53.248073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1971 21:58:53.340068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1972 21:58:53.341022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1974 21:58:53.431668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1975 21:58:53.432649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1977 21:58:53.524026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1978 21:58:53.524871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1980 21:58:53.618470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1981 21:58:53.619471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1983 21:58:53.710681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1984 21:58:53.711527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1986 21:58:53.802718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1987 21:58:53.803897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1989 21:58:53.897019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1990 21:58:53.898000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1992 21:58:53.991848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1993 21:58:53.992959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1995 21:58:54.085377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1996 21:58:54.086300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1998 21:58:54.177459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1999 21:58:54.178443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2001 21:58:54.270622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2002 21:58:54.271483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2004 21:58:54.365099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2005 21:58:54.366000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2007 21:58:54.459833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2008 21:58:54.460701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2010 21:58:54.548961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2011 21:58:54.549801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2013 21:58:54.641621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2014 21:58:54.642576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2016 21:58:54.734649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2017 21:58:54.735482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2019 21:58:54.827082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2020 21:58:54.827954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2022 21:58:54.918100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2023 21:58:54.918969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2025 21:58:55.007528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2026 21:58:55.008344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2028 21:58:55.101590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2029 21:58:55.102453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2031 21:58:55.193215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2032 21:58:55.194031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2034 21:58:55.286232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2035 21:58:55.287094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2037 21:58:55.379646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2038 21:58:55.380730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2040 21:58:55.472889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2041 21:58:55.473747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2043 21:58:55.564932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2044 21:58:55.565797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2046 21:58:55.657738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2047 21:58:55.658762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2049 21:58:55.750608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2050 21:58:55.751476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2052 21:58:55.845596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2053 21:58:55.846979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2055 21:58:55.937525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2056 21:58:55.938393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2058 21:58:56.030039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2059 21:58:56.031297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2061 21:58:56.124372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2062 21:58:56.125258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2064 21:58:56.216459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2065 21:58:56.217335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2067 21:58:56.318572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2068 21:58:56.319520 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2070 21:58:56.412628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2071 21:58:56.413489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2073 21:58:56.506819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2074 21:58:56.507670 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2076 21:58:56.598111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2077 21:58:56.598956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2079 21:58:56.691468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2080 21:58:56.692317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2082 21:58:56.782511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2083 21:58:56.783354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2085 21:58:56.877865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2086 21:58:56.878713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2088 21:58:56.970201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2089 21:58:56.971035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2091 21:58:57.063127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2092 21:58:57.063963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2094 21:58:57.154215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2095 21:58:57.155065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2097 21:58:57.247667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2098 21:58:57.248528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2100 21:58:57.339608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2101 21:58:57.340439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2103 21:58:57.430281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2104 21:58:57.431134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2106 21:58:57.519250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2107 21:58:57.520159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2109 21:58:57.614142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2110 21:58:57.615078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2112 21:58:57.704896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2113 21:58:57.705880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2115 21:58:57.798962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2116 21:58:57.799837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2118 21:58:57.889136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2119 21:58:57.889998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2121 21:58:57.982784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2122 21:58:57.983724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2124 21:58:58.076227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2125 21:58:58.077180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2127 21:58:58.169371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2128 21:58:58.170379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2130 21:58:58.262111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2131 21:58:58.262974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2133 21:58:58.352079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2134 21:58:58.352923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2136 21:58:58.447263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2137 21:58:58.448224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2139 21:58:58.538676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2140 21:58:58.539586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2142 21:58:58.631324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2143 21:58:58.632748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2145 21:58:58.720997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2146 21:58:58.721938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2148 21:58:58.813284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2149 21:58:58.814286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2151 21:58:58.899147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2152 21:58:58.900134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2154 21:58:58.990338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2155 21:58:58.991204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2157 21:58:59.083056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2158 21:58:59.083972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2160 21:58:59.319338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2161 21:58:59.320202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2163 21:58:59.424691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2164 21:58:59.425637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2166 21:58:59.516435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2167 21:58:59.517345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2169 21:58:59.607712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2170 21:58:59.608595 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2172 21:58:59.700207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2173 21:58:59.701100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2175 21:58:59.785490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2176 21:58:59.786397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2178 21:58:59.877856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2179 21:58:59.878682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2181 21:58:59.969303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2182 21:58:59.970149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2184 21:59:00.060675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2185 21:59:00.061523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2187 21:59:00.149416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2188 21:59:00.150122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2190 21:59:00.247025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2191 21:59:00.247872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2193 21:59:00.340932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2194 21:59:00.342458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2196 21:59:00.432349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2197 21:59:00.433248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2199 21:59:00.526593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2200 21:59:00.527487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2202 21:59:00.619383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2203 21:59:00.620218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2205 21:59:00.711103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2206 21:59:00.711854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2208 21:59:00.802581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2209 21:59:00.803359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2211 21:59:00.894604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2212 21:59:00.895506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2214 21:59:00.985748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2215 21:59:00.986817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2217 21:59:01.078976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2218 21:59:01.079906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2220 21:59:01.165431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2221 21:59:01.166848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2223 21:59:01.258300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2224 21:59:01.259194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2226 21:59:01.354993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2227 21:59:01.355927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2229 21:59:01.448663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2230 21:59:01.449566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2232 21:59:01.539485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2233 21:59:01.540261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2235 21:59:01.629407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2236 21:59:01.630367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2238 21:59:01.719714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2239 21:59:01.720543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2241 21:59:01.806599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2242 21:59:01.807473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2244 21:59:01.900446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2245 21:59:01.901311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2247 21:59:01.990504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2248 21:59:01.991280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2250 21:59:02.082565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2251 21:59:02.083315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2253 21:59:02.175586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2254 21:59:02.176357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2256 21:59:02.262935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2257 21:59:02.263514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2259 21:59:02.357891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2260 21:59:02.358728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2262 21:59:02.447517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2263 21:59:02.448224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2265 21:59:02.537491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2266 21:59:02.538379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2268 21:59:02.630490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2269 21:59:02.631251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2271 21:59:02.723080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2272 21:59:02.723671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2274 21:59:02.812768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2276 21:59:02.815899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2277 21:59:02.905196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2278 21:59:02.906770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2280 21:59:02.999723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2281 21:59:03.000313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2283 21:59:03.090481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2284 21:59:03.091379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2286 21:59:03.183965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2287 21:59:03.184915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2289 21:59:03.274695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2290 21:59:03.275572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2292 21:59:03.365749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2293 21:59:03.366662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2295 21:59:03.456302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2296 21:59:03.457166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2298 21:59:03.546085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2299 21:59:03.546925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2301 21:59:03.637125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2302 21:59:03.637971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2304 21:59:03.729699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2305 21:59:03.730587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2307 21:59:03.821572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2308 21:59:03.822471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2310 21:59:03.912594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2311 21:59:03.913457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2313 21:59:04.005421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2314 21:59:04.006344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2316 21:59:04.096773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2317 21:59:04.097644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2319 21:59:04.187712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2320 21:59:04.188604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2322 21:59:04.279336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2323 21:59:04.280218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2325 21:59:04.372364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2326 21:59:04.373199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2328 21:59:04.463520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2329 21:59:04.464376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2331 21:59:04.555600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2332 21:59:04.556656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2334 21:59:04.647941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2335 21:59:04.648788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2337 21:59:04.738984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2338 21:59:04.739925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2340 21:59:04.831081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2341 21:59:04.831944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2343 21:59:04.922216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2344 21:59:04.923068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2346 21:59:05.014347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2347 21:59:05.015193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2349 21:59:05.104899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2350 21:59:05.105709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2352 21:59:05.195392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2353 21:59:05.196220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2355 21:59:05.287644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2356 21:59:05.288468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2358 21:59:05.381570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2359 21:59:05.382539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2361 21:59:05.475841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2362 21:59:05.476673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2364 21:59:05.577031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2365 21:59:05.578015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2367 21:59:05.667519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2368 21:59:05.668159 + set +x
2369 21:59:05.668854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2371 21:59:05.674209 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 949303_1.6.2.4.5>
2372 21:59:05.675516 Received signal: <ENDRUN> 1_kselftest-dt 949303_1.6.2.4.5
2373 21:59:05.676714 Ending use of test pattern.
2374 21:59:05.677211 Ending test lava.1_kselftest-dt (949303_1.6.2.4.5), duration 87.09
2376 21:59:05.680688 <LAVA_TEST_RUNNER EXIT>
2377 21:59:05.681285 ok: lava_test_shell seems to have completed
2378 21:59:05.688184 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2379 21:59:05.689331 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2380 21:59:05.689715 end: 3 lava-test-retry (duration 00:01:28) [common]
2381 21:59:05.690070 start: 4 finalize (timeout 00:05:24) [common]
2382 21:59:05.690414 start: 4.1 power-off (timeout 00:00:30) [common]
2383 21:59:05.690981 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-06'
2384 21:59:05.723942 >> OK - accepted request
2385 21:59:05.725738 Returned 0 in 0 seconds
2386 21:59:05.826732 end: 4.1 power-off (duration 00:00:00) [common]
2388 21:59:05.828567 start: 4.2 read-feedback (timeout 00:05:24) [common]
2389 21:59:05.829745 Listened to connection for namespace 'common' for up to 1s
2390 21:59:05.830526 Listened to connection for namespace 'common' for up to 1s
2391 21:59:06.829964 Finalising connection for namespace 'common'
2392 21:59:06.830693 Disconnecting from shell: Finalise
2393 21:59:06.831191 / #
2394 21:59:06.932188 end: 4.2 read-feedback (duration 00:00:01) [common]
2395 21:59:06.932993 end: 4 finalize (duration 00:00:01) [common]
2396 21:59:06.933691 Cleaning after the job
2397 21:59:06.934365 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949303/tftp-deploy-418_zsla/ramdisk
2398 21:59:06.944099 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949303/tftp-deploy-418_zsla/kernel
2399 21:59:06.946350 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949303/tftp-deploy-418_zsla/dtb
2400 21:59:06.947553 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949303/tftp-deploy-418_zsla/nfsrootfs
2401 21:59:06.992061 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949303/tftp-deploy-418_zsla/modules
2402 21:59:07.001245 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949303
2403 21:59:10.181738 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949303
2404 21:59:10.184092 Job finished correctly