Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:58:57.700337 lava-dispatcher, installed at version: 2024.01
2 22:58:57.701113 start: 0 validate
3 22:58:57.701582 Start time: 2024-11-06 22:58:57.701553+00:00 (UTC)
4 22:58:57.702109 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:58:57.702644 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 22:58:57.742980 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:58:57.743539 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 22:58:57.776958 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:58:57.777557 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 22:58:58.833536 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:58:58.834015 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
12 22:58:58.884218 validate duration: 1.18
14 22:58:58.885685 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:58:58.886283 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:58:58.886853 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:58:58.887841 Not decompressing ramdisk as can be used compressed.
18 22:58:58.888606 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 22:58:58.889111 saving as /var/lib/lava/dispatcher/tmp/949530/tftp-deploy-6x4ho9rl/ramdisk/rootfs.cpio.gz
20 22:58:58.889614 total size: 8181887 (7 MB)
21 22:58:58.932591 progress 0 % (0 MB)
22 22:58:58.943052 progress 5 % (0 MB)
23 22:58:58.953193 progress 10 % (0 MB)
24 22:58:58.963970 progress 15 % (1 MB)
25 22:58:58.973111 progress 20 % (1 MB)
26 22:58:58.978637 progress 25 % (1 MB)
27 22:58:58.983762 progress 30 % (2 MB)
28 22:58:58.989279 progress 35 % (2 MB)
29 22:58:58.994319 progress 40 % (3 MB)
30 22:58:58.999872 progress 45 % (3 MB)
31 22:58:59.004961 progress 50 % (3 MB)
32 22:58:59.010422 progress 55 % (4 MB)
33 22:58:59.015525 progress 60 % (4 MB)
34 22:58:59.020972 progress 65 % (5 MB)
35 22:58:59.026031 progress 70 % (5 MB)
36 22:58:59.031501 progress 75 % (5 MB)
37 22:58:59.036569 progress 80 % (6 MB)
38 22:58:59.041995 progress 85 % (6 MB)
39 22:58:59.047032 progress 90 % (7 MB)
40 22:58:59.052679 progress 95 % (7 MB)
41 22:58:59.057335 progress 100 % (7 MB)
42 22:58:59.057963 7 MB downloaded in 0.17 s (46.35 MB/s)
43 22:58:59.058521 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:58:59.059436 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:58:59.059742 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:58:59.060328 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:58:59.061190 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/kernel/Image
49 22:58:59.061454 saving as /var/lib/lava/dispatcher/tmp/949530/tftp-deploy-6x4ho9rl/kernel/Image
50 22:58:59.061676 total size: 37878272 (36 MB)
51 22:58:59.061899 No compression specified
52 22:58:59.102426 progress 0 % (0 MB)
53 22:58:59.126779 progress 5 % (1 MB)
54 22:58:59.151470 progress 10 % (3 MB)
55 22:58:59.176727 progress 15 % (5 MB)
56 22:58:59.201233 progress 20 % (7 MB)
57 22:58:59.225708 progress 25 % (9 MB)
58 22:58:59.250906 progress 30 % (10 MB)
59 22:58:59.275530 progress 35 % (12 MB)
60 22:58:59.299932 progress 40 % (14 MB)
61 22:58:59.324764 progress 45 % (16 MB)
62 22:58:59.349532 progress 50 % (18 MB)
63 22:58:59.374517 progress 55 % (19 MB)
64 22:58:59.399122 progress 60 % (21 MB)
65 22:58:59.423412 progress 65 % (23 MB)
66 22:58:59.448306 progress 70 % (25 MB)
67 22:58:59.472825 progress 75 % (27 MB)
68 22:58:59.497536 progress 80 % (28 MB)
69 22:58:59.521925 progress 85 % (30 MB)
70 22:58:59.546810 progress 90 % (32 MB)
71 22:58:59.571413 progress 95 % (34 MB)
72 22:58:59.595396 progress 100 % (36 MB)
73 22:58:59.596249 36 MB downloaded in 0.53 s (67.58 MB/s)
74 22:58:59.596782 end: 1.2.1 http-download (duration 00:00:01) [common]
76 22:58:59.597620 end: 1.2 download-retry (duration 00:00:01) [common]
77 22:58:59.597900 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:58:59.598170 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:58:59.598653 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 22:58:59.598973 saving as /var/lib/lava/dispatcher/tmp/949530/tftp-deploy-6x4ho9rl/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 22:58:59.599187 total size: 53209 (0 MB)
82 22:58:59.599397 No compression specified
83 22:58:59.642717 progress 61 % (0 MB)
84 22:58:59.643599 progress 100 % (0 MB)
85 22:58:59.644262 0 MB downloaded in 0.05 s (1.13 MB/s)
86 22:58:59.644858 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:58:59.645753 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:58:59.646025 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:58:59.646334 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:58:59.646886 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/modules.tar.xz
92 22:58:59.647162 saving as /var/lib/lava/dispatcher/tmp/949530/tftp-deploy-6x4ho9rl/modules/modules.tar
93 22:58:59.647368 total size: 11769360 (11 MB)
94 22:58:59.647580 Using unxz to decompress xz
95 22:58:59.681810 progress 0 % (0 MB)
96 22:58:59.749889 progress 5 % (0 MB)
97 22:58:59.828310 progress 10 % (1 MB)
98 22:58:59.929121 progress 15 % (1 MB)
99 22:59:00.028998 progress 20 % (2 MB)
100 22:59:00.109714 progress 25 % (2 MB)
101 22:59:00.188382 progress 30 % (3 MB)
102 22:59:00.270296 progress 35 % (3 MB)
103 22:59:00.351339 progress 40 % (4 MB)
104 22:59:00.429028 progress 45 % (5 MB)
105 22:59:00.515056 progress 50 % (5 MB)
106 22:59:00.598932 progress 55 % (6 MB)
107 22:59:00.685248 progress 60 % (6 MB)
108 22:59:00.768302 progress 65 % (7 MB)
109 22:59:00.851601 progress 70 % (7 MB)
110 22:59:00.935972 progress 75 % (8 MB)
111 22:59:01.021364 progress 80 % (9 MB)
112 22:59:01.103121 progress 85 % (9 MB)
113 22:59:01.188076 progress 90 % (10 MB)
114 22:59:01.268050 progress 95 % (10 MB)
115 22:59:01.346750 progress 100 % (11 MB)
116 22:59:01.358196 11 MB downloaded in 1.71 s (6.56 MB/s)
117 22:59:01.359066 end: 1.4.1 http-download (duration 00:00:02) [common]
119 22:59:01.360720 end: 1.4 download-retry (duration 00:00:02) [common]
120 22:59:01.361248 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 22:59:01.361765 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 22:59:01.362253 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:59:01.362749 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 22:59:01.363742 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w
125 22:59:01.364672 makedir: /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin
126 22:59:01.365340 makedir: /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/tests
127 22:59:01.365956 makedir: /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/results
128 22:59:01.366562 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-add-keys
129 22:59:01.367497 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-add-sources
130 22:59:01.368569 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-background-process-start
131 22:59:01.369525 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-background-process-stop
132 22:59:01.370489 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-common-functions
133 22:59:01.371390 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-echo-ipv4
134 22:59:01.372454 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-install-packages
135 22:59:01.373414 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-installed-packages
136 22:59:01.374316 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-os-build
137 22:59:01.375207 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-probe-channel
138 22:59:01.376123 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-probe-ip
139 22:59:01.377055 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-target-ip
140 22:59:01.377949 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-target-mac
141 22:59:01.378828 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-target-storage
142 22:59:01.379718 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-test-case
143 22:59:01.380660 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-test-event
144 22:59:01.381538 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-test-feedback
145 22:59:01.382414 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-test-raise
146 22:59:01.383311 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-test-reference
147 22:59:01.384278 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-test-runner
148 22:59:01.385186 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-test-set
149 22:59:01.386064 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-test-shell
150 22:59:01.386952 Updating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-install-packages (oe)
151 22:59:01.387887 Updating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/bin/lava-installed-packages (oe)
152 22:59:01.388772 Creating /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/environment
153 22:59:01.389479 LAVA metadata
154 22:59:01.389966 - LAVA_JOB_ID=949530
155 22:59:01.390389 - LAVA_DISPATCHER_IP=192.168.6.2
156 22:59:01.391030 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 22:59:01.392842 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 22:59:01.393444 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 22:59:01.393855 skipped lava-vland-overlay
160 22:59:01.394339 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 22:59:01.394842 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 22:59:01.395263 skipped lava-multinode-overlay
163 22:59:01.395742 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 22:59:01.396286 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 22:59:01.396761 Loading test definitions
166 22:59:01.397302 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 22:59:01.397737 Using /lava-949530 at stage 0
168 22:59:01.399849 uuid=949530_1.5.2.4.1 testdef=None
169 22:59:01.400288 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 22:59:01.400566 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 22:59:01.402386 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 22:59:01.403202 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 22:59:01.405546 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 22:59:01.406419 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 22:59:01.408629 runner path: /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/0/tests/0_dmesg test_uuid 949530_1.5.2.4.1
178 22:59:01.409201 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 22:59:01.409989 Creating lava-test-runner.conf files
181 22:59:01.410195 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949530/lava-overlay-g2sbeh_w/lava-949530/0 for stage 0
182 22:59:01.410525 - 0_dmesg
183 22:59:01.410878 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 22:59:01.411164 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 22:59:01.434755 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 22:59:01.435142 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 22:59:01.435411 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 22:59:01.435676 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 22:59:01.435941 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 22:59:02.349067 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 22:59:02.349543 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 22:59:02.349813 extracting modules file /var/lib/lava/dispatcher/tmp/949530/tftp-deploy-6x4ho9rl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949530/extract-overlay-ramdisk-m45xk1_d/ramdisk
193 22:59:03.673757 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 22:59:03.674223 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 22:59:03.674508 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949530/compress-overlay-rxnqg2gt/overlay-1.5.2.5.tar.gz to ramdisk
196 22:59:03.674720 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949530/compress-overlay-rxnqg2gt/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949530/extract-overlay-ramdisk-m45xk1_d/ramdisk
197 22:59:03.704922 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 22:59:03.705321 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 22:59:03.705588 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 22:59:03.705814 Converting downloaded kernel to a uImage
201 22:59:03.706112 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949530/tftp-deploy-6x4ho9rl/kernel/Image /var/lib/lava/dispatcher/tmp/949530/tftp-deploy-6x4ho9rl/kernel/uImage
202 22:59:04.094920 output: Image Name:
203 22:59:04.095346 output: Created: Wed Nov 6 22:59:03 2024
204 22:59:04.095558 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 22:59:04.095762 output: Data Size: 37878272 Bytes = 36990.50 KiB = 36.12 MiB
206 22:59:04.095962 output: Load Address: 01080000
207 22:59:04.096200 output: Entry Point: 01080000
208 22:59:04.096400 output:
209 22:59:04.096729 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 22:59:04.096996 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 22:59:04.097266 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 22:59:04.097522 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 22:59:04.097778 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 22:59:04.098045 Building ramdisk /var/lib/lava/dispatcher/tmp/949530/extract-overlay-ramdisk-m45xk1_d/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949530/extract-overlay-ramdisk-m45xk1_d/ramdisk
215 22:59:06.958498 >> 188218 blocks
216 22:59:15.398434 Adding RAMdisk u-boot header.
217 22:59:15.399077 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949530/extract-overlay-ramdisk-m45xk1_d/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949530/extract-overlay-ramdisk-m45xk1_d/ramdisk.cpio.gz.uboot
218 22:59:15.688273 output: Image Name:
219 22:59:15.688750 output: Created: Wed Nov 6 22:59:15 2024
220 22:59:15.689202 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 22:59:15.689620 output: Data Size: 26778963 Bytes = 26151.33 KiB = 25.54 MiB
222 22:59:15.690050 output: Load Address: 00000000
223 22:59:15.690456 output: Entry Point: 00000000
224 22:59:15.690856 output:
225 22:59:15.691908 rename /var/lib/lava/dispatcher/tmp/949530/extract-overlay-ramdisk-m45xk1_d/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949530/tftp-deploy-6x4ho9rl/ramdisk/ramdisk.cpio.gz.uboot
226 22:59:15.692705 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 22:59:15.693418 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 22:59:15.693977 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 22:59:15.694444 No LXC device requested
230 22:59:15.694957 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 22:59:15.695476 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 22:59:15.695977 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 22:59:15.696441 Checking files for TFTP limit of 4294967296 bytes.
234 22:59:15.698262 end: 1 tftp-deploy (duration 00:00:17) [common]
235 22:59:15.698720 start: 2 uboot-action (timeout 00:05:00) [common]
236 22:59:15.699274 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 22:59:15.699804 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 22:59:15.700354 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 22:59:15.700908 Using kernel file from prepare-kernel: 949530/tftp-deploy-6x4ho9rl/kernel/uImage
240 22:59:15.701547 substitutions:
241 22:59:15.701974 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 22:59:15.702382 - {DTB_ADDR}: 0x01070000
243 22:59:15.702783 - {DTB}: 949530/tftp-deploy-6x4ho9rl/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 22:59:15.703192 - {INITRD}: 949530/tftp-deploy-6x4ho9rl/ramdisk/ramdisk.cpio.gz.uboot
245 22:59:15.703626 - {KERNEL_ADDR}: 0x01080000
246 22:59:15.704069 - {KERNEL}: 949530/tftp-deploy-6x4ho9rl/kernel/uImage
247 22:59:15.704476 - {LAVA_MAC}: None
248 22:59:15.704921 - {PRESEED_CONFIG}: None
249 22:59:15.705326 - {PRESEED_LOCAL}: None
250 22:59:15.705718 - {RAMDISK_ADDR}: 0x08000000
251 22:59:15.706110 - {RAMDISK}: 949530/tftp-deploy-6x4ho9rl/ramdisk/ramdisk.cpio.gz.uboot
252 22:59:15.706505 - {ROOT_PART}: None
253 22:59:15.706898 - {ROOT}: None
254 22:59:15.707286 - {SERVER_IP}: 192.168.6.2
255 22:59:15.707679 - {TEE_ADDR}: 0x83000000
256 22:59:15.708098 - {TEE}: None
257 22:59:15.708498 Parsed boot commands:
258 22:59:15.708881 - setenv autoload no
259 22:59:15.709271 - setenv initrd_high 0xffffffff
260 22:59:15.709656 - setenv fdt_high 0xffffffff
261 22:59:15.710041 - dhcp
262 22:59:15.711647 - setenv serverip 192.168.6.2
263 22:59:15.712106 - tftpboot 0x01080000 949530/tftp-deploy-6x4ho9rl/kernel/uImage
264 22:59:15.712348 - tftpboot 0x08000000 949530/tftp-deploy-6x4ho9rl/ramdisk/ramdisk.cpio.gz.uboot
265 22:59:15.712569 - tftpboot 0x01070000 949530/tftp-deploy-6x4ho9rl/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 22:59:15.712770 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 22:59:15.712968 - bootm 0x01080000 0x08000000 0x01070000
268 22:59:15.713544 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 22:59:15.715052 start: 2.3 connect-device (timeout 00:05:00) [common]
271 22:59:15.715504 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 22:59:15.732004 Setting prompt string to ['lava-test: # ']
273 22:59:15.733553 end: 2.3 connect-device (duration 00:00:00) [common]
274 22:59:15.734153 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 22:59:15.734682 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 22:59:15.735206 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 22:59:15.736390 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 22:59:15.772984 >> OK - accepted request
279 22:59:15.775175 Returned 0 in 0 seconds
280 22:59:15.876351 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 22:59:15.877973 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 22:59:15.878529 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 22:59:15.879028 Setting prompt string to ['Hit any key to stop autoboot']
285 22:59:15.879477 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 22:59:15.881076 Trying 192.168.56.21...
287 22:59:15.881552 Connected to conserv1.
288 22:59:15.882038 Escape character is '^]'.
289 22:59:15.882477
290 22:59:15.882894 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 22:59:15.883332
292 22:59:23.052318 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 22:59:23.052946 bl2_stage_init 0x01
294 22:59:23.053398 bl2_stage_init 0x81
295 22:59:23.057692 hw id: 0x0000 - pwm id 0x01
296 22:59:23.058159 bl2_stage_init 0xc1
297 22:59:23.063564 bl2_stage_init 0x02
298 22:59:23.064126
299 22:59:23.064613 L0:00000000
300 22:59:23.065032 L1:00000703
301 22:59:23.065450 L2:00008067
302 22:59:23.065852 L3:15000000
303 22:59:23.069445 S1:00000000
304 22:59:23.069880 B2:20282000
305 22:59:23.070287 B1:a0f83180
306 22:59:23.070690
307 22:59:23.071091 TE: 72003
308 22:59:23.071492
309 22:59:23.074666 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 22:59:23.075108
311 22:59:23.080713 Board ID = 1
312 22:59:23.081143 Set cpu clk to 24M
313 22:59:23.081549 Set clk81 to 24M
314 22:59:23.086024 Use GP1_pll as DSU clk.
315 22:59:23.086448 DSU clk: 1200 Mhz
316 22:59:23.086853 CPU clk: 1200 MHz
317 22:59:23.091639 Set clk81 to 166.6M
318 22:59:23.097513 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 22:59:23.097951 board id: 1
320 22:59:23.103174 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 22:59:23.114634 fw parse done
322 22:59:23.119648 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 22:59:23.163226 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 22:59:23.174242 PIEI prepare done
325 22:59:23.174667 fastboot data load
326 22:59:23.175075 fastboot data verify
327 22:59:23.179875 verify result: 266
328 22:59:23.185393 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 22:59:23.185819 LPDDR4 probe
330 22:59:23.186224 ddr clk to 1584MHz
331 22:59:23.192416 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 22:59:23.230578
333 22:59:23.231029 dmc_version 0001
334 22:59:23.236313 Check phy result
335 22:59:23.243282 INFO : End of CA training
336 22:59:23.243718 INFO : End of initialization
337 22:59:23.248890 INFO : Training has run successfully!
338 22:59:23.249319 Check phy result
339 22:59:23.254419 INFO : End of initialization
340 22:59:23.254846 INFO : End of read enable training
341 22:59:23.257739 INFO : End of fine write leveling
342 22:59:23.263297 INFO : End of Write leveling coarse delay
343 22:59:23.268907 INFO : Training has run successfully!
344 22:59:23.269339 Check phy result
345 22:59:23.269746 INFO : End of initialization
346 22:59:23.274547 INFO : End of read dq deskew training
347 22:59:23.277867 INFO : End of MPR read delay center optimization
348 22:59:23.283396 INFO : End of write delay center optimization
349 22:59:23.289112 INFO : End of read delay center optimization
350 22:59:23.289537 INFO : End of max read latency training
351 22:59:23.294585 INFO : Training has run successfully!
352 22:59:23.295015 1D training succeed
353 22:59:23.301861 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 22:59:23.350372 Check phy result
355 22:59:23.350846 INFO : End of initialization
356 22:59:23.372756 INFO : End of 2D read delay Voltage center optimization
357 22:59:23.392021 INFO : End of 2D read delay Voltage center optimization
358 22:59:23.443824 INFO : End of 2D write delay Voltage center optimization
359 22:59:23.492990 INFO : End of 2D write delay Voltage center optimization
360 22:59:23.498554 INFO : Training has run successfully!
361 22:59:23.498984
362 22:59:23.499396 channel==0
363 22:59:23.504238 RxClkDly_Margin_A0==78 ps 8
364 22:59:23.504672 TxDqDly_Margin_A0==98 ps 10
365 22:59:23.507459 RxClkDly_Margin_A1==88 ps 9
366 22:59:23.507884 TxDqDly_Margin_A1==88 ps 9
367 22:59:23.513020 TrainedVREFDQ_A0==74
368 22:59:23.513451 TrainedVREFDQ_A1==74
369 22:59:23.513860 VrefDac_Margin_A0==24
370 22:59:23.518628 DeviceVref_Margin_A0==40
371 22:59:23.519052 VrefDac_Margin_A1==23
372 22:59:23.524275 DeviceVref_Margin_A1==40
373 22:59:23.524740
374 22:59:23.525158
375 22:59:23.525564 channel==1
376 22:59:23.525964 RxClkDly_Margin_A0==88 ps 9
377 22:59:23.529802 TxDqDly_Margin_A0==98 ps 10
378 22:59:23.530235 RxClkDly_Margin_A1==88 ps 9
379 22:59:23.535396 TxDqDly_Margin_A1==88 ps 9
380 22:59:23.535828 TrainedVREFDQ_A0==75
381 22:59:23.536265 TrainedVREFDQ_A1==75
382 22:59:23.541145 VrefDac_Margin_A0==22
383 22:59:23.541568 DeviceVref_Margin_A0==39
384 22:59:23.546629 VrefDac_Margin_A1==22
385 22:59:23.547050 DeviceVref_Margin_A1==39
386 22:59:23.547456
387 22:59:23.552203 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 22:59:23.552628
389 22:59:23.580231 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000062
390 22:59:23.585797 2D training succeed
391 22:59:23.591422 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 22:59:23.591854 auto size-- 65535DDR cs0 size: 2048MB
393 22:59:23.596986 DDR cs1 size: 2048MB
394 22:59:23.597412 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 22:59:23.602590 cs0 DataBus test pass
396 22:59:23.603027 cs1 DataBus test pass
397 22:59:23.603434 cs0 AddrBus test pass
398 22:59:23.608248 cs1 AddrBus test pass
399 22:59:23.608683
400 22:59:23.609091 100bdlr_step_size ps== 471
401 22:59:23.609503 result report
402 22:59:23.613797 boot times 0Enable ddr reg access
403 22:59:23.620459 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 22:59:23.634348 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 22:59:24.289431 bl2z: ptr: 05129330, size: 00001e40
406 22:59:24.296563 0.0;M3 CHK:0;cm4_sp_mode 0
407 22:59:24.297011 MVN_1=0x00000000
408 22:59:24.297422 MVN_2=0x00000000
409 22:59:24.308269 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 22:59:24.308700 OPS=0x04
411 22:59:24.309105 ring efuse init
412 22:59:24.313747 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 22:59:24.314191 [0.017319 Inits done]
414 22:59:24.314596 secure task start!
415 22:59:24.321365 high task start!
416 22:59:24.321813 low task start!
417 22:59:24.322222 run into bl31
418 22:59:24.329970 NOTICE: BL31: v1.3(release):4fc40b1
419 22:59:24.337755 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 22:59:24.338191 NOTICE: BL31: G12A normal boot!
421 22:59:24.353408 NOTICE: BL31: BL33 decompress pass
422 22:59:24.359103 ERROR: Error initializing runtime service opteed_fast
423 22:59:27.097756 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 22:59:27.098328 bl2_stage_init 0x01
425 22:59:27.098763 bl2_stage_init 0x81
426 22:59:27.103404 hw id: 0x0000 - pwm id 0x01
427 22:59:27.103896 bl2_stage_init 0xc1
428 22:59:27.108956 bl2_stage_init 0x02
429 22:59:27.109450
430 22:59:27.109850 L0:00000000
431 22:59:27.110237 L1:00000703
432 22:59:27.110624 L2:00008067
433 22:59:27.111008 L3:15000000
434 22:59:27.114619 S1:00000000
435 22:59:27.115034 B2:20282000
436 22:59:27.115424 B1:a0f83180
437 22:59:27.115813
438 22:59:27.116237 TE: 67866
439 22:59:27.116627
440 22:59:27.120131 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 22:59:27.120542
442 22:59:27.125713 Board ID = 1
443 22:59:27.126123 Set cpu clk to 24M
444 22:59:27.126514 Set clk81 to 24M
445 22:59:27.131367 Use GP1_pll as DSU clk.
446 22:59:27.131792 DSU clk: 1200 Mhz
447 22:59:27.132212 CPU clk: 1200 MHz
448 22:59:27.136889 Set clk81 to 166.6M
449 22:59:27.142624 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 22:59:27.143042 board id: 1
451 22:59:27.149743 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 22:59:27.160636 fw parse done
453 22:59:27.166694 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 22:59:27.209754 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 22:59:27.220791 PIEI prepare done
456 22:59:27.221209 fastboot data load
457 22:59:27.221605 fastboot data verify
458 22:59:27.226428 verify result: 266
459 22:59:27.232033 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 22:59:27.232452 LPDDR4 probe
461 22:59:27.232842 ddr clk to 1584MHz
462 22:59:27.239971 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 22:59:27.277718
464 22:59:27.278143 dmc_version 0001
465 22:59:27.284766 Check phy result
466 22:59:27.290795 INFO : End of CA training
467 22:59:27.291260 INFO : End of initialization
468 22:59:27.296408 INFO : Training has run successfully!
469 22:59:27.296846 Check phy result
470 22:59:27.301915 INFO : End of initialization
471 22:59:27.302345 INFO : End of read enable training
472 22:59:27.307651 INFO : End of fine write leveling
473 22:59:27.313145 INFO : End of Write leveling coarse delay
474 22:59:27.313569 INFO : Training has run successfully!
475 22:59:27.313975 Check phy result
476 22:59:27.318737 INFO : End of initialization
477 22:59:27.319157 INFO : End of read dq deskew training
478 22:59:27.324391 INFO : End of MPR read delay center optimization
479 22:59:27.329938 INFO : End of write delay center optimization
480 22:59:27.335646 INFO : End of read delay center optimization
481 22:59:27.336099 INFO : End of max read latency training
482 22:59:27.341145 INFO : Training has run successfully!
483 22:59:27.341567 1D training succeed
484 22:59:27.350340 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 22:59:27.398574 Check phy result
486 22:59:27.399007 INFO : End of initialization
487 22:59:27.425999 INFO : End of 2D read delay Voltage center optimization
488 22:59:27.450167 INFO : End of 2D read delay Voltage center optimization
489 22:59:27.506845 INFO : End of 2D write delay Voltage center optimization
490 22:59:27.560872 INFO : End of 2D write delay Voltage center optimization
491 22:59:27.566484 INFO : Training has run successfully!
492 22:59:27.566907
493 22:59:27.567311 channel==0
494 22:59:27.572079 RxClkDly_Margin_A0==78 ps 8
495 22:59:27.572510 TxDqDly_Margin_A0==98 ps 10
496 22:59:27.575460 RxClkDly_Margin_A1==88 ps 9
497 22:59:27.575881 TxDqDly_Margin_A1==88 ps 9
498 22:59:27.580993 TrainedVREFDQ_A0==74
499 22:59:27.581418 TrainedVREFDQ_A1==74
500 22:59:27.581825 VrefDac_Margin_A0==24
501 22:59:27.586684 DeviceVref_Margin_A0==40
502 22:59:27.587110 VrefDac_Margin_A1==23
503 22:59:27.592210 DeviceVref_Margin_A1==40
504 22:59:27.592635
505 22:59:27.593039
506 22:59:27.593437 channel==1
507 22:59:27.593828 RxClkDly_Margin_A0==78 ps 8
508 22:59:27.597754 TxDqDly_Margin_A0==98 ps 10
509 22:59:27.598178 RxClkDly_Margin_A1==78 ps 8
510 22:59:27.603436 TxDqDly_Margin_A1==78 ps 8
511 22:59:27.603865 TrainedVREFDQ_A0==78
512 22:59:27.604304 TrainedVREFDQ_A1==75
513 22:59:27.608996 VrefDac_Margin_A0==22
514 22:59:27.609435 DeviceVref_Margin_A0==36
515 22:59:27.614697 VrefDac_Margin_A1==22
516 22:59:27.615120 DeviceVref_Margin_A1==39
517 22:59:27.615519
518 22:59:27.620197 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 22:59:27.620624
520 22:59:27.648198 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000015 00000016 dram_vref_reg_value 0x 00000062
521 22:59:27.653777 2D training succeed
522 22:59:27.659442 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 22:59:27.659880 auto size-- 65535DDR cs0 size: 2048MB
524 22:59:27.664988 DDR cs1 size: 2048MB
525 22:59:27.665410 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 22:59:27.670685 cs0 DataBus test pass
527 22:59:27.671109 cs1 DataBus test pass
528 22:59:27.671512 cs0 AddrBus test pass
529 22:59:27.676197 cs1 AddrBus test pass
530 22:59:27.676618
531 22:59:27.677022 100bdlr_step_size ps== 471
532 22:59:27.677427 result report
533 22:59:27.681782 boot times 0Enable ddr reg access
534 22:59:27.689228 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 22:59:27.703104 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 22:59:28.362279 bl2z: ptr: 05129330, size: 00001e40
537 22:59:28.369973 0.0;M3 CHK:0;cm4_sp_mode 0
538 22:59:28.370417 MVN_1=0x00000000
539 22:59:28.370822 MVN_2=0x00000000
540 22:59:28.381479 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 22:59:28.381914 OPS=0x04
542 22:59:28.382324 ring efuse init
543 22:59:28.387010 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 22:59:28.387455 [0.017354 Inits done]
545 22:59:28.387859 secure task start!
546 22:59:28.394517 high task start!
547 22:59:28.394963 low task start!
548 22:59:28.395391 run into bl31
549 22:59:28.403075 NOTICE: BL31: v1.3(release):4fc40b1
550 22:59:28.410546 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 22:59:28.410995 NOTICE: BL31: G12A normal boot!
552 22:59:28.426498 NOTICE: BL31: BL33 decompress pass
553 22:59:28.432152 ERROR: Error initializing runtime service opteed_fast
554 22:59:29.798318 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 22:59:29.798808 bl2_stage_init 0x01
556 22:59:29.799219 bl2_stage_init 0x81
557 22:59:29.803953 hw id: 0x0000 - pwm id 0x01
558 22:59:29.804521 bl2_stage_init 0xc1
559 22:59:29.809471 bl2_stage_init 0x02
560 22:59:29.809902
561 22:59:29.810307 L0:00000000
562 22:59:29.810707 L1:00000703
563 22:59:29.811100 L2:00008067
564 22:59:29.811492 L3:15000000
565 22:59:29.815249 S1:00000000
566 22:59:29.815700 B2:20282000
567 22:59:29.816136 B1:a0f83180
568 22:59:29.816535
569 22:59:29.816936 TE: 68094
570 22:59:29.817333
571 22:59:29.820919 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 22:59:29.821354
573 22:59:29.826460 Board ID = 1
574 22:59:29.826888 Set cpu clk to 24M
575 22:59:29.827290 Set clk81 to 24M
576 22:59:29.832152 Use GP1_pll as DSU clk.
577 22:59:29.832580 DSU clk: 1200 Mhz
578 22:59:29.832982 CPU clk: 1200 MHz
579 22:59:29.837576 Set clk81 to 166.6M
580 22:59:29.843279 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 22:59:29.843703 board id: 1
582 22:59:29.850266 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 22:59:29.861079 fw parse done
584 22:59:29.866946 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 22:59:29.909460 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 22:59:29.920318 PIEI prepare done
587 22:59:29.920744 fastboot data load
588 22:59:29.921154 fastboot data verify
589 22:59:29.926056 verify result: 266
590 22:59:29.931529 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 22:59:29.931955 LPDDR4 probe
592 22:59:29.932401 ddr clk to 1584MHz
593 22:59:29.939522 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 22:59:29.976738
595 22:59:29.977166 dmc_version 0001
596 22:59:29.982677 Check phy result
597 22:59:29.989344 INFO : End of CA training
598 22:59:29.989766 INFO : End of initialization
599 22:59:29.995051 INFO : Training has run successfully!
600 22:59:29.995473 Check phy result
601 22:59:30.000550 INFO : End of initialization
602 22:59:30.000975 INFO : End of read enable training
603 22:59:30.003886 INFO : End of fine write leveling
604 22:59:30.009401 INFO : End of Write leveling coarse delay
605 22:59:30.015074 INFO : Training has run successfully!
606 22:59:30.015496 Check phy result
607 22:59:30.015902 INFO : End of initialization
608 22:59:30.020608 INFO : End of read dq deskew training
609 22:59:30.026202 INFO : End of MPR read delay center optimization
610 22:59:30.026630 INFO : End of write delay center optimization
611 22:59:30.031847 INFO : End of read delay center optimization
612 22:59:30.037430 INFO : End of max read latency training
613 22:59:30.037857 INFO : Training has run successfully!
614 22:59:30.043075 1D training succeed
615 22:59:30.048992 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 22:59:30.096555 Check phy result
617 22:59:30.096980 INFO : End of initialization
618 22:59:30.118935 INFO : End of 2D read delay Voltage center optimization
619 22:59:30.138171 INFO : End of 2D read delay Voltage center optimization
620 22:59:30.189942 INFO : End of 2D write delay Voltage center optimization
621 22:59:30.239156 INFO : End of 2D write delay Voltage center optimization
622 22:59:30.244684 INFO : Training has run successfully!
623 22:59:30.245107
624 22:59:30.245515 channel==0
625 22:59:30.250286 RxClkDly_Margin_A0==88 ps 9
626 22:59:30.250711 TxDqDly_Margin_A0==98 ps 10
627 22:59:30.253675 RxClkDly_Margin_A1==88 ps 9
628 22:59:30.254099 TxDqDly_Margin_A1==98 ps 10
629 22:59:30.259180 TrainedVREFDQ_A0==74
630 22:59:30.259608 TrainedVREFDQ_A1==74
631 22:59:30.264861 VrefDac_Margin_A0==24
632 22:59:30.265290 DeviceVref_Margin_A0==40
633 22:59:30.265692 VrefDac_Margin_A1==23
634 22:59:30.270381 DeviceVref_Margin_A1==40
635 22:59:30.270806
636 22:59:30.271213
637 22:59:30.271611 channel==1
638 22:59:30.272029 RxClkDly_Margin_A0==78 ps 8
639 22:59:30.273870 TxDqDly_Margin_A0==98 ps 10
640 22:59:30.279337 RxClkDly_Margin_A1==88 ps 9
641 22:59:30.279767 TxDqDly_Margin_A1==78 ps 8
642 22:59:30.280204 TrainedVREFDQ_A0==78
643 22:59:30.284963 TrainedVREFDQ_A1==75
644 22:59:30.285394 VrefDac_Margin_A0==22
645 22:59:30.290569 DeviceVref_Margin_A0==36
646 22:59:30.290994 VrefDac_Margin_A1==22
647 22:59:30.291393 DeviceVref_Margin_A1==39
648 22:59:30.291791
649 22:59:30.296177 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 22:59:30.296604
651 22:59:30.329687 soc_vref_reg_value 0x 00000019 00000018 00000017 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000062
652 22:59:30.330138 2D training succeed
653 22:59:30.335257 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 22:59:30.340865 auto size-- 65535DDR cs0 size: 2048MB
655 22:59:30.341293 DDR cs1 size: 2048MB
656 22:59:30.346476 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 22:59:30.346903 cs0 DataBus test pass
658 22:59:30.347307 cs1 DataBus test pass
659 22:59:30.352063 cs0 AddrBus test pass
660 22:59:30.352485 cs1 AddrBus test pass
661 22:59:30.352886
662 22:59:30.357686 100bdlr_step_size ps== 478
663 22:59:30.358123 result report
664 22:59:30.358526 boot times 0Enable ddr reg access
665 22:59:30.367503 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 22:59:30.381321 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 22:59:31.037280 bl2z: ptr: 05129330, size: 00001e40
668 22:59:31.044489 0.0;M3 CHK:0;cm4_sp_mode 0
669 22:59:31.044938 MVN_1=0x00000000
670 22:59:31.045346 MVN_2=0x00000000
671 22:59:31.056032 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 22:59:31.056481 OPS=0x04
673 22:59:31.056891 ring efuse init
674 22:59:31.061612 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 22:59:31.062057 [0.017310 Inits done]
676 22:59:31.062460 secure task start!
677 22:59:31.068057 high task start!
678 22:59:31.068490 low task start!
679 22:59:31.068896 run into bl31
680 22:59:31.077566 NOTICE: BL31: v1.3(release):4fc40b1
681 22:59:31.085381 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 22:59:31.085820 NOTICE: BL31: G12A normal boot!
683 22:59:31.100968 NOTICE: BL31: BL33 decompress pass
684 22:59:31.106667 ERROR: Error initializing runtime service opteed_fast
685 22:59:31.900745
686 22:59:31.901237
687 22:59:31.906275 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 22:59:31.906717
689 22:59:31.909711 Model: Libre Computer AML-S905D3-CC Solitude
690 22:59:32.056540 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 22:59:32.071925 DRAM: 2 GiB (effective 3.8 GiB)
692 22:59:32.172832 Core: 406 devices, 33 uclasses, devicetree: separate
693 22:59:32.178808 WDT: Not starting watchdog@f0d0
694 22:59:32.203842 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 22:59:32.216094 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 22:59:32.221039 ** Bad device specification mmc 0 **
697 22:59:32.231118 Card did not respond to voltage select! : -110
698 22:59:32.238765 ** Bad device specification mmc 0 **
699 22:59:32.239186 Couldn't find partition mmc 0
700 22:59:32.247117 Card did not respond to voltage select! : -110
701 22:59:32.252608 ** Bad device specification mmc 0 **
702 22:59:32.253027 Couldn't find partition mmc 0
703 22:59:32.257666 Error: could not access storage.
704 22:59:32.555077 Net: eth0: ethernet@ff3f0000
705 22:59:32.555631 starting USB...
706 22:59:32.799693 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 22:59:32.800215 Starting the controller
708 22:59:32.806718 USB XHCI 1.10
709 22:59:34.360567 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 22:59:34.368782 scanning usb for storage devices... 0 Storage Device(s) found
712 22:59:34.420209 Hit any key to stop autoboot: 1
713 22:59:34.420985 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 22:59:34.421568 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 22:59:34.422041 Setting prompt string to ['=>']
716 22:59:34.422515 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 22:59:34.434803 0
718 22:59:34.435665 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 22:59:34.536967 => setenv autoload no
721 22:59:34.537578 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 22:59:34.542412 setenv autoload no
724 22:59:34.643826 => setenv initrd_high 0xffffffff
725 22:59:34.644445 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 22:59:34.648239 setenv initrd_high 0xffffffff
728 22:59:34.749599 => setenv fdt_high 0xffffffff
729 22:59:34.750178 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 22:59:34.754523 setenv fdt_high 0xffffffff
732 22:59:34.855928 => dhcp
733 22:59:34.856578 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 22:59:34.860554 dhcp
735 22:59:35.516164 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 22:59:35.516649 Speed: 1000, full duplex
737 22:59:35.517067 BOOTP broadcast 1
738 22:59:35.524789 DHCP client bound to address 192.168.6.21 (8 ms)
740 22:59:35.626190 => setenv serverip 192.168.6.2
741 22:59:35.626761 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
742 22:59:35.631210 setenv serverip 192.168.6.2
744 22:59:35.732587 => tftpboot 0x01080000 949530/tftp-deploy-6x4ho9rl/kernel/uImage
745 22:59:35.733170 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
746 22:59:35.739938 tftpboot 0x01080000 949530/tftp-deploy-6x4ho9rl/kernel/uImage
747 22:59:35.740438 Speed: 1000, full duplex
748 22:59:35.740852 Using ethernet@ff3f0000 device
749 22:59:35.745432 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 22:59:35.751007 Filename '949530/tftp-deploy-6x4ho9rl/kernel/uImage'.
751 22:59:35.754966 Load address: 0x1080000
752 22:59:38.025869 Loading: *################################################## 36.1 MiB
753 22:59:38.026513 15.9 MiB/s
754 22:59:38.026924 done
755 22:59:38.030469 Bytes transferred = 37878336 (241fa40 hex)
757 22:59:38.132087 => tftpboot 0x08000000 949530/tftp-deploy-6x4ho9rl/ramdisk/ramdisk.cpio.gz.uboot
758 22:59:38.132917 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
759 22:59:38.139874 tftpboot 0x08000000 949530/tftp-deploy-6x4ho9rl/ramdisk/ramdisk.cpio.gz.uboot
760 22:59:38.140445 Speed: 1000, full duplex
761 22:59:38.140895 Using ethernet@ff3f0000 device
762 22:59:38.145476 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
763 22:59:38.155051 Filename '949530/tftp-deploy-6x4ho9rl/ramdisk/ramdisk.cpio.gz.uboot'.
764 22:59:38.155621 Load address: 0x8000000
765 22:59:39.783847 Loading: *################################################# UDP wrong checksum 00000005 00003e11
766 22:59:44.785243 T UDP wrong checksum 00000005 00003e11
767 22:59:54.787229 T T UDP wrong checksum 00000005 00003e11
768 23:00:14.790319 T T T T UDP wrong checksum 00000005 00003e11
769 23:00:34.796092 T T T
770 23:00:34.796527 Retry count exceeded; starting again
772 23:00:34.798430 end: 2.4.3 bootloader-commands (duration 00:01:00) [common]
775 23:00:34.800484 end: 2.4 uboot-commands (duration 00:01:19) [common]
777 23:00:34.801947 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
779 23:00:34.803061 end: 2 uboot-action (duration 00:01:19) [common]
781 23:00:34.804745 Cleaning after the job
782 23:00:34.805343 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949530/tftp-deploy-6x4ho9rl/ramdisk
783 23:00:34.806701 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949530/tftp-deploy-6x4ho9rl/kernel
784 23:00:34.851071 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949530/tftp-deploy-6x4ho9rl/dtb
785 23:00:34.852273 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949530/tftp-deploy-6x4ho9rl/modules
786 23:00:34.873747 start: 4.1 power-off (timeout 00:00:30) [common]
787 23:00:34.874403 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
788 23:00:34.924799 >> OK - accepted request
789 23:00:34.926833 Returned 0 in 0 seconds
790 23:00:35.027808 end: 4.1 power-off (duration 00:00:00) [common]
792 23:00:35.029598 start: 4.2 read-feedback (timeout 00:10:00) [common]
793 23:00:35.030727 Listened to connection for namespace 'common' for up to 1s
794 23:00:36.031573 Finalising connection for namespace 'common'
795 23:00:36.032421 Disconnecting from shell: Finalise
796 23:00:36.033000 =>
797 23:00:36.134083 end: 4.2 read-feedback (duration 00:00:01) [common]
798 23:00:36.134859 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949530
799 23:00:36.436177 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949530
800 23:00:36.436789 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.