Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:44:44.302125 lava-dispatcher, installed at version: 2024.01
2 01:44:44.302948 start: 0 validate
3 01:44:44.303429 Start time: 2024-11-07 01:44:44.303398+00:00 (UTC)
4 01:44:44.303998 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:44:44.304558 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:44:44.342271 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:44:44.342798 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 01:44:44.372541 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:44:44.373242 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:44:44.409727 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:44:44.410531 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:44:44.441593 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:44:44.442116 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
14 01:44:44.482084 validate duration: 0.18
16 01:44:44.482972 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:44:44.483297 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:44:44.483602 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:44:44.484275 Not decompressing ramdisk as can be used compressed.
20 01:44:44.484872 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:44:44.485235 saving as /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/ramdisk/initrd.cpio.gz
22 01:44:44.485573 total size: 5628169 (5 MB)
23 01:44:44.528060 progress 0 % (0 MB)
24 01:44:44.532927 progress 5 % (0 MB)
25 01:44:44.538212 progress 10 % (0 MB)
26 01:44:44.542956 progress 15 % (0 MB)
27 01:44:44.547887 progress 20 % (1 MB)
28 01:44:44.552511 progress 25 % (1 MB)
29 01:44:44.557348 progress 30 % (1 MB)
30 01:44:44.562089 progress 35 % (1 MB)
31 01:44:44.566533 progress 40 % (2 MB)
32 01:44:44.571694 progress 45 % (2 MB)
33 01:44:44.575599 progress 50 % (2 MB)
34 01:44:44.579870 progress 55 % (2 MB)
35 01:44:44.584185 progress 60 % (3 MB)
36 01:44:44.587916 progress 65 % (3 MB)
37 01:44:44.592236 progress 70 % (3 MB)
38 01:44:44.596073 progress 75 % (4 MB)
39 01:44:44.600195 progress 80 % (4 MB)
40 01:44:44.603949 progress 85 % (4 MB)
41 01:44:44.608255 progress 90 % (4 MB)
42 01:44:44.612272 progress 95 % (5 MB)
43 01:44:44.615629 progress 100 % (5 MB)
44 01:44:44.616349 5 MB downloaded in 0.13 s (41.04 MB/s)
45 01:44:44.616909 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:44:44.617786 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:44:44.618074 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:44:44.618341 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:44:44.618810 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/kernel/Image
51 01:44:44.619051 saving as /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/kernel/Image
52 01:44:44.619260 total size: 37878272 (36 MB)
53 01:44:44.619473 No compression specified
54 01:44:44.661718 progress 0 % (0 MB)
55 01:44:44.684959 progress 5 % (1 MB)
56 01:44:44.708515 progress 10 % (3 MB)
57 01:44:44.731895 progress 15 % (5 MB)
58 01:44:44.755617 progress 20 % (7 MB)
59 01:44:44.778528 progress 25 % (9 MB)
60 01:44:44.801801 progress 30 % (10 MB)
61 01:44:44.825023 progress 35 % (12 MB)
62 01:44:44.848764 progress 40 % (14 MB)
63 01:44:44.871953 progress 45 % (16 MB)
64 01:44:44.895143 progress 50 % (18 MB)
65 01:44:44.918821 progress 55 % (19 MB)
66 01:44:44.942297 progress 60 % (21 MB)
67 01:44:44.966367 progress 65 % (23 MB)
68 01:44:44.990315 progress 70 % (25 MB)
69 01:44:45.013699 progress 75 % (27 MB)
70 01:44:45.037494 progress 80 % (28 MB)
71 01:44:45.061657 progress 85 % (30 MB)
72 01:44:45.085189 progress 90 % (32 MB)
73 01:44:45.108641 progress 95 % (34 MB)
74 01:44:45.131427 progress 100 % (36 MB)
75 01:44:45.132244 36 MB downloaded in 0.51 s (70.42 MB/s)
76 01:44:45.132732 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:44:45.133539 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:44:45.133813 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:44:45.134079 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:44:45.134532 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:44:45.134797 saving as /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:44:45.135004 total size: 54703 (0 MB)
84 01:44:45.135213 No compression specified
85 01:44:45.168882 progress 59 % (0 MB)
86 01:44:45.169706 progress 100 % (0 MB)
87 01:44:45.170254 0 MB downloaded in 0.04 s (1.48 MB/s)
88 01:44:45.170732 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:44:45.171614 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:44:45.171896 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:44:45.172202 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:44:45.172661 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:44:45.172897 saving as /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/nfsrootfs/full.rootfs.tar
95 01:44:45.173101 total size: 120894716 (115 MB)
96 01:44:45.173308 Using unxz to decompress xz
97 01:44:45.209771 progress 0 % (0 MB)
98 01:44:46.002122 progress 5 % (5 MB)
99 01:44:46.845738 progress 10 % (11 MB)
100 01:44:47.639834 progress 15 % (17 MB)
101 01:44:48.381455 progress 20 % (23 MB)
102 01:44:48.972414 progress 25 % (28 MB)
103 01:44:49.797021 progress 30 % (34 MB)
104 01:44:50.589206 progress 35 % (40 MB)
105 01:44:50.937348 progress 40 % (46 MB)
106 01:44:51.318320 progress 45 % (51 MB)
107 01:44:52.045829 progress 50 % (57 MB)
108 01:44:52.930351 progress 55 % (63 MB)
109 01:44:53.749907 progress 60 % (69 MB)
110 01:44:54.646493 progress 65 % (74 MB)
111 01:44:55.566760 progress 70 % (80 MB)
112 01:44:56.547294 progress 75 % (86 MB)
113 01:44:57.482134 progress 80 % (92 MB)
114 01:44:58.396182 progress 85 % (98 MB)
115 01:44:59.284745 progress 90 % (103 MB)
116 01:45:00.079798 progress 95 % (109 MB)
117 01:45:00.936127 progress 100 % (115 MB)
118 01:45:00.948928 115 MB downloaded in 15.78 s (7.31 MB/s)
119 01:45:00.949588 end: 1.4.1 http-download (duration 00:00:16) [common]
121 01:45:00.950403 end: 1.4 download-retry (duration 00:00:16) [common]
122 01:45:00.950664 start: 1.5 download-retry (timeout 00:09:44) [common]
123 01:45:00.950923 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 01:45:00.951418 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/modules.tar.xz
125 01:45:00.951670 saving as /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/modules/modules.tar
126 01:45:00.951872 total size: 11769360 (11 MB)
127 01:45:00.952117 Using unxz to decompress xz
128 01:45:00.997040 progress 0 % (0 MB)
129 01:45:01.066277 progress 5 % (0 MB)
130 01:45:01.144588 progress 10 % (1 MB)
131 01:45:01.243674 progress 15 % (1 MB)
132 01:45:01.345643 progress 20 % (2 MB)
133 01:45:01.431177 progress 25 % (2 MB)
134 01:45:01.510873 progress 30 % (3 MB)
135 01:45:01.594118 progress 35 % (3 MB)
136 01:45:01.675852 progress 40 % (4 MB)
137 01:45:01.754119 progress 45 % (5 MB)
138 01:45:01.840229 progress 50 % (5 MB)
139 01:45:01.922731 progress 55 % (6 MB)
140 01:45:02.008569 progress 60 % (6 MB)
141 01:45:02.091233 progress 65 % (7 MB)
142 01:45:02.173915 progress 70 % (7 MB)
143 01:45:02.257684 progress 75 % (8 MB)
144 01:45:02.342555 progress 80 % (9 MB)
145 01:45:02.424381 progress 85 % (9 MB)
146 01:45:02.508976 progress 90 % (10 MB)
147 01:45:02.589379 progress 95 % (10 MB)
148 01:45:02.667319 progress 100 % (11 MB)
149 01:45:02.678105 11 MB downloaded in 1.73 s (6.50 MB/s)
150 01:45:02.678674 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:45:02.679526 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:45:02.679795 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 01:45:02.680190 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 01:45:19.048970 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/949465/extract-nfsrootfs-rgtvll3n
156 01:45:19.049588 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 01:45:19.049916 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 01:45:19.050574 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x
159 01:45:19.051065 makedir: /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin
160 01:45:19.051475 makedir: /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/tests
161 01:45:19.051862 makedir: /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/results
162 01:45:19.052261 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-add-keys
163 01:45:19.052810 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-add-sources
164 01:45:19.053318 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-background-process-start
165 01:45:19.053811 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-background-process-stop
166 01:45:19.054326 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-common-functions
167 01:45:19.054813 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-echo-ipv4
168 01:45:19.055286 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-install-packages
169 01:45:19.055755 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-installed-packages
170 01:45:19.056263 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-os-build
171 01:45:19.056746 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-probe-channel
172 01:45:19.057241 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-probe-ip
173 01:45:19.057821 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-target-ip
174 01:45:19.058309 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-target-mac
175 01:45:19.058789 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-target-storage
176 01:45:19.059276 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-test-case
177 01:45:19.059751 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-test-event
178 01:45:19.060281 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-test-feedback
179 01:45:19.060770 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-test-raise
180 01:45:19.061258 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-test-reference
181 01:45:19.061749 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-test-runner
182 01:45:19.062225 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-test-set
183 01:45:19.062688 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-test-shell
184 01:45:19.063164 Updating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-add-keys (debian)
185 01:45:19.063682 Updating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-add-sources (debian)
186 01:45:19.064206 Updating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-install-packages (debian)
187 01:45:19.064713 Updating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-installed-packages (debian)
188 01:45:19.065206 Updating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/bin/lava-os-build (debian)
189 01:45:19.065637 Creating /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/environment
190 01:45:19.066004 LAVA metadata
191 01:45:19.066258 - LAVA_JOB_ID=949465
192 01:45:19.066471 - LAVA_DISPATCHER_IP=192.168.6.2
193 01:45:19.066834 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 01:45:19.067784 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 01:45:19.068116 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 01:45:19.068325 skipped lava-vland-overlay
197 01:45:19.068564 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 01:45:19.068814 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 01:45:19.069028 skipped lava-multinode-overlay
200 01:45:19.069267 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 01:45:19.069511 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 01:45:19.069757 Loading test definitions
203 01:45:19.070028 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 01:45:19.070244 Using /lava-949465 at stage 0
205 01:45:19.071321 uuid=949465_1.6.2.4.1 testdef=None
206 01:45:19.071627 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 01:45:19.071883 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 01:45:19.073532 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 01:45:19.074315 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 01:45:19.076236 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 01:45:19.077054 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 01:45:19.078861 runner path: /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/0/tests/0_timesync-off test_uuid 949465_1.6.2.4.1
215 01:45:19.079402 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 01:45:19.080233 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 01:45:19.080457 Using /lava-949465 at stage 0
219 01:45:19.080803 Fetching tests from https://github.com/kernelci/test-definitions.git
220 01:45:19.081091 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/0/tests/1_kselftest-dt'
221 01:45:22.985078 Running '/usr/bin/git checkout kernelci.org
222 01:45:23.431921 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 01:45:23.433428 uuid=949465_1.6.2.4.5 testdef=None
224 01:45:23.433789 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 01:45:23.434553 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 01:45:23.437486 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 01:45:23.438331 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 01:45:23.442227 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 01:45:23.443118 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 01:45:23.446774 runner path: /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/0/tests/1_kselftest-dt test_uuid 949465_1.6.2.4.5
234 01:45:23.447067 BOARD='meson-g12b-a311d-libretech-cc'
235 01:45:23.447284 BRANCH='mainline'
236 01:45:23.447487 SKIPFILE='/dev/null'
237 01:45:23.447687 SKIP_INSTALL='True'
238 01:45:23.447884 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/kselftest.tar.xz'
239 01:45:23.448110 TST_CASENAME=''
240 01:45:23.448314 TST_CMDFILES='dt'
241 01:45:23.448912 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 01:45:23.449721 Creating lava-test-runner.conf files
244 01:45:23.449936 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949465/lava-overlay-o72fx24x/lava-949465/0 for stage 0
245 01:45:23.450305 - 0_timesync-off
246 01:45:23.450556 - 1_kselftest-dt
247 01:45:23.450906 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 01:45:23.451197 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 01:45:47.621538 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 01:45:47.622037 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 01:45:47.622345 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 01:45:47.622681 end: 1.6.2 lava-overlay (duration 00:00:29) [common]
253 01:45:47.622988 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 01:45:48.233882 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 01:45:48.234363 start: 1.6.4 extract-modules (timeout 00:08:56) [common]
256 01:45:48.234629 extracting modules file /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949465/extract-nfsrootfs-rgtvll3n
257 01:45:49.615696 extracting modules file /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949465/extract-overlay-ramdisk-yyh_uchc/ramdisk
258 01:45:51.026175 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 01:45:51.026744 start: 1.6.5 apply-overlay-tftp (timeout 00:08:53) [common]
260 01:45:51.027035 [common] Applying overlay to NFS
261 01:45:51.027259 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949465/compress-overlay-czysxtjj/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949465/extract-nfsrootfs-rgtvll3n
262 01:45:53.769988 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 01:45:53.770441 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 01:45:53.770748 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 01:45:53.771009 Converting downloaded kernel to a uImage
266 01:45:53.771339 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/kernel/Image /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/kernel/uImage
267 01:45:54.187417 output: Image Name:
268 01:45:54.187825 output: Created: Thu Nov 7 01:45:53 2024
269 01:45:54.188076 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 01:45:54.188287 output: Data Size: 37878272 Bytes = 36990.50 KiB = 36.12 MiB
271 01:45:54.188489 output: Load Address: 01080000
272 01:45:54.188688 output: Entry Point: 01080000
273 01:45:54.188885 output:
274 01:45:54.189215 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 01:45:54.189484 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 01:45:54.189752 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 01:45:54.190005 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 01:45:54.190264 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 01:45:54.190521 Building ramdisk /var/lib/lava/dispatcher/tmp/949465/extract-overlay-ramdisk-yyh_uchc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949465/extract-overlay-ramdisk-yyh_uchc/ramdisk
280 01:45:56.405428 >> 173435 blocks
281 01:46:04.135296 Adding RAMdisk u-boot header.
282 01:46:04.135750 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949465/extract-overlay-ramdisk-yyh_uchc/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949465/extract-overlay-ramdisk-yyh_uchc/ramdisk.cpio.gz.uboot
283 01:46:04.390858 output: Image Name:
284 01:46:04.391265 output: Created: Thu Nov 7 01:46:04 2024
285 01:46:04.391500 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 01:46:04.391738 output: Data Size: 24147299 Bytes = 23581.35 KiB = 23.03 MiB
287 01:46:04.391960 output: Load Address: 00000000
288 01:46:04.392471 output: Entry Point: 00000000
289 01:46:04.392877 output:
290 01:46:04.393945 rename /var/lib/lava/dispatcher/tmp/949465/extract-overlay-ramdisk-yyh_uchc/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/ramdisk/ramdisk.cpio.gz.uboot
291 01:46:04.394685 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 01:46:04.395238 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 01:46:04.395806 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 01:46:04.396305 No LXC device requested
295 01:46:04.396822 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 01:46:04.397339 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 01:46:04.397839 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 01:46:04.398254 Checking files for TFTP limit of 4294967296 bytes.
299 01:46:04.400965 end: 1 tftp-deploy (duration 00:01:20) [common]
300 01:46:04.401550 start: 2 uboot-action (timeout 00:05:00) [common]
301 01:46:04.402085 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 01:46:04.402585 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 01:46:04.403086 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 01:46:04.403616 Using kernel file from prepare-kernel: 949465/tftp-deploy-uamh8ord/kernel/uImage
305 01:46:04.404307 substitutions:
306 01:46:04.404732 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 01:46:04.405138 - {DTB_ADDR}: 0x01070000
308 01:46:04.405540 - {DTB}: 949465/tftp-deploy-uamh8ord/dtb/meson-g12b-a311d-libretech-cc.dtb
309 01:46:04.405944 - {INITRD}: 949465/tftp-deploy-uamh8ord/ramdisk/ramdisk.cpio.gz.uboot
310 01:46:04.406343 - {KERNEL_ADDR}: 0x01080000
311 01:46:04.406735 - {KERNEL}: 949465/tftp-deploy-uamh8ord/kernel/uImage
312 01:46:04.407132 - {LAVA_MAC}: None
313 01:46:04.407564 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/949465/extract-nfsrootfs-rgtvll3n
314 01:46:04.407963 - {NFS_SERVER_IP}: 192.168.6.2
315 01:46:04.408384 - {PRESEED_CONFIG}: None
316 01:46:04.408775 - {PRESEED_LOCAL}: None
317 01:46:04.409167 - {RAMDISK_ADDR}: 0x08000000
318 01:46:04.409555 - {RAMDISK}: 949465/tftp-deploy-uamh8ord/ramdisk/ramdisk.cpio.gz.uboot
319 01:46:04.409942 - {ROOT_PART}: None
320 01:46:04.410325 - {ROOT}: None
321 01:46:04.410711 - {SERVER_IP}: 192.168.6.2
322 01:46:04.411095 - {TEE_ADDR}: 0x83000000
323 01:46:04.411481 - {TEE}: None
324 01:46:04.411866 Parsed boot commands:
325 01:46:04.412276 - setenv autoload no
326 01:46:04.412666 - setenv initrd_high 0xffffffff
327 01:46:04.413049 - setenv fdt_high 0xffffffff
328 01:46:04.413433 - dhcp
329 01:46:04.413819 - setenv serverip 192.168.6.2
330 01:46:04.414207 - tftpboot 0x01080000 949465/tftp-deploy-uamh8ord/kernel/uImage
331 01:46:04.414598 - tftpboot 0x08000000 949465/tftp-deploy-uamh8ord/ramdisk/ramdisk.cpio.gz.uboot
332 01:46:04.414989 - tftpboot 0x01070000 949465/tftp-deploy-uamh8ord/dtb/meson-g12b-a311d-libretech-cc.dtb
333 01:46:04.415378 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/949465/extract-nfsrootfs-rgtvll3n,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 01:46:04.415779 - bootm 0x01080000 0x08000000 0x01070000
335 01:46:04.416327 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 01:46:04.417830 start: 2.3 connect-device (timeout 00:05:00) [common]
338 01:46:04.418256 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 01:46:04.433241 Setting prompt string to ['lava-test: # ']
340 01:46:04.434735 end: 2.3 connect-device (duration 00:00:00) [common]
341 01:46:04.435358 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 01:46:04.436105 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 01:46:04.436707 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 01:46:04.437853 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 01:46:04.474964 >> OK - accepted request
346 01:46:04.477135 Returned 0 in 0 seconds
347 01:46:04.578329 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 01:46:04.580107 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 01:46:04.580682 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 01:46:04.581210 Setting prompt string to ['Hit any key to stop autoboot']
352 01:46:04.581674 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 01:46:04.583251 Trying 192.168.56.21...
354 01:46:04.583731 Connected to conserv1.
355 01:46:04.584210 Escape character is '^]'.
356 01:46:04.584657
357 01:46:04.585107 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 01:46:04.585563
359 01:46:16.591907 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 01:46:16.592359 bl2_stage_init 0x01
361 01:46:16.592617 bl2_stage_init 0x81
362 01:46:16.597422 hw id: 0x0000 - pwm id 0x01
363 01:46:16.597708 bl2_stage_init 0xc1
364 01:46:16.597936 bl2_stage_init 0x02
365 01:46:16.598174
366 01:46:16.603206 L0:00000000
367 01:46:16.603506 L1:20000703
368 01:46:16.603737 L2:00008067
369 01:46:16.603967 L3:14000000
370 01:46:16.605991 B2:00402000
371 01:46:16.606265 B1:e0f83180
372 01:46:16.606501
373 01:46:16.606728 TE: 58124
374 01:46:16.606951
375 01:46:16.617100 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 01:46:16.617421
377 01:46:16.617656 Board ID = 1
378 01:46:16.617879 Set A53 clk to 24M
379 01:46:16.618101 Set A73 clk to 24M
380 01:46:16.622662 Set clk81 to 24M
381 01:46:16.622959 A53 clk: 1200 MHz
382 01:46:16.623186 A73 clk: 1200 MHz
383 01:46:16.626244 CLK81: 166.6M
384 01:46:16.626540 smccc: 00012a92
385 01:46:16.631746 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 01:46:16.637306 board id: 1
387 01:46:16.642433 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 01:46:16.653096 fw parse done
389 01:46:16.659084 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 01:46:16.701714 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 01:46:16.712820 PIEI prepare done
392 01:46:16.713246 fastboot data load
393 01:46:16.713635 fastboot data verify
394 01:46:16.718362 verify result: 266
395 01:46:16.723873 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 01:46:16.724341 LPDDR4 probe
397 01:46:16.724727 ddr clk to 1584MHz
398 01:46:16.731818 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 01:46:16.769349
400 01:46:16.769798 dmc_version 0001
401 01:46:16.775795 Check phy result
402 01:46:16.781605 INFO : End of CA training
403 01:46:16.782029 INFO : End of initialization
404 01:46:16.787247 INFO : Training has run successfully!
405 01:46:16.787660 Check phy result
406 01:46:16.792851 INFO : End of initialization
407 01:46:16.793264 INFO : End of read enable training
408 01:46:16.798372 INFO : End of fine write leveling
409 01:46:16.804166 INFO : End of Write leveling coarse delay
410 01:46:16.804583 INFO : Training has run successfully!
411 01:46:16.804974 Check phy result
412 01:46:16.809588 INFO : End of initialization
413 01:46:16.810003 INFO : End of read dq deskew training
414 01:46:16.815251 INFO : End of MPR read delay center optimization
415 01:46:16.820856 INFO : End of write delay center optimization
416 01:46:16.826583 INFO : End of read delay center optimization
417 01:46:16.827004 INFO : End of max read latency training
418 01:46:16.832156 INFO : Training has run successfully!
419 01:46:16.832572 1D training succeed
420 01:46:16.841291 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 01:46:16.888942 Check phy result
422 01:46:16.889385 INFO : End of initialization
423 01:46:16.911452 INFO : End of 2D read delay Voltage center optimization
424 01:46:16.931700 INFO : End of 2D read delay Voltage center optimization
425 01:46:16.983095 INFO : End of 2D write delay Voltage center optimization
426 01:46:17.033247 INFO : End of 2D write delay Voltage center optimization
427 01:46:17.038783 INFO : Training has run successfully!
428 01:46:17.039202
429 01:46:17.039594 channel==0
430 01:46:17.044286 RxClkDly_Margin_A0==88 ps 9
431 01:46:17.044702 TxDqDly_Margin_A0==98 ps 10
432 01:46:17.047643 RxClkDly_Margin_A1==78 ps 8
433 01:46:17.048078 TxDqDly_Margin_A1==98 ps 10
434 01:46:17.053184 TrainedVREFDQ_A0==74
435 01:46:17.053594 TrainedVREFDQ_A1==74
436 01:46:17.053984 VrefDac_Margin_A0==24
437 01:46:17.058818 DeviceVref_Margin_A0==40
438 01:46:17.059226 VrefDac_Margin_A1==26
439 01:46:17.064325 DeviceVref_Margin_A1==40
440 01:46:17.064729
441 01:46:17.065118
442 01:46:17.065503 channel==1
443 01:46:17.065885 RxClkDly_Margin_A0==98 ps 10
444 01:46:17.067796 TxDqDly_Margin_A0==98 ps 10
445 01:46:17.073422 RxClkDly_Margin_A1==98 ps 10
446 01:46:17.073840 TxDqDly_Margin_A1==88 ps 9
447 01:46:17.074230 TrainedVREFDQ_A0==77
448 01:46:17.079121 TrainedVREFDQ_A1==77
449 01:46:17.079536 VrefDac_Margin_A0==22
450 01:46:17.084813 DeviceVref_Margin_A0==37
451 01:46:17.085227 VrefDac_Margin_A1==24
452 01:46:17.085611 DeviceVref_Margin_A1==37
453 01:46:17.085992
454 01:46:17.090372 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 01:46:17.090783
456 01:46:17.123921 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 01:46:17.124436 2D training succeed
458 01:46:17.129575 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 01:46:17.135158 auto size-- 65535DDR cs0 size: 2048MB
460 01:46:17.135582 DDR cs1 size: 2048MB
461 01:46:17.140717 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 01:46:17.141135 cs0 DataBus test pass
463 01:46:17.141524 cs1 DataBus test pass
464 01:46:17.146277 cs0 AddrBus test pass
465 01:46:17.146702 cs1 AddrBus test pass
466 01:46:17.147088
467 01:46:17.151959 100bdlr_step_size ps== 420
468 01:46:17.152424 result report
469 01:46:17.152812 boot times 0Enable ddr reg access
470 01:46:17.161409 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 01:46:17.175244 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 01:46:17.748867 0.0;M3 CHK:0;cm4_sp_mode 0
473 01:46:17.749474 MVN_1=0x00000000
474 01:46:17.754322 MVN_2=0x00000000
475 01:46:17.760186 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 01:46:17.760670 OPS=0x10
477 01:46:17.761073 ring efuse init
478 01:46:17.761466 chipver efuse init
479 01:46:17.765667 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 01:46:17.771247 [0.018960 Inits done]
481 01:46:17.771694 secure task start!
482 01:46:17.772139 high task start!
483 01:46:17.775854 low task start!
484 01:46:17.776334 run into bl31
485 01:46:17.782542 NOTICE: BL31: v1.3(release):4fc40b1
486 01:46:17.790296 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 01:46:17.790750 NOTICE: BL31: G12A normal boot!
488 01:46:17.816211 NOTICE: BL31: BL33 decompress pass
489 01:46:17.821976 ERROR: Error initializing runtime service opteed_fast
490 01:46:19.054915
491 01:46:19.055562
492 01:46:19.063295 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 01:46:19.063853
494 01:46:19.064298 Model: Libre Computer AML-A311D-CC Alta
495 01:46:19.271708 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 01:46:19.295045 DRAM: 2 GiB (effective 3.8 GiB)
497 01:46:19.438072 Core: 408 devices, 31 uclasses, devicetree: separate
498 01:46:19.443956 WDT: Not starting watchdog@f0d0
499 01:46:19.482683 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 01:46:19.488806 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 01:46:19.502942 ** Bad device specification mmc 0 **
502 01:46:19.508039 Card did not respond to voltage select! : -110
503 01:46:19.512075 ** Bad device specification mmc 0 **
504 01:46:19.512506 Couldn't find partition mmc 0
505 01:46:19.520035 Card did not respond to voltage select! : -110
506 01:46:19.525491 ** Bad device specification mmc 0 **
507 01:46:19.525860 Couldn't find partition mmc 0
508 01:46:19.530526 Error: could not access storage.
509 01:46:20.792277 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 01:46:20.792917 bl2_stage_init 0x01
511 01:46:20.793351 bl2_stage_init 0x81
512 01:46:20.797891 hw id: 0x0000 - pwm id 0x01
513 01:46:20.798374 bl2_stage_init 0xc1
514 01:46:20.798795 bl2_stage_init 0x02
515 01:46:20.799203
516 01:46:20.803441 L0:00000000
517 01:46:20.803899 L1:20000703
518 01:46:20.804356 L2:00008067
519 01:46:20.804763 L3:14000000
520 01:46:20.806293 B2:00402000
521 01:46:20.806747 B1:e0f83180
522 01:46:20.807148
523 01:46:20.807547 TE: 58124
524 01:46:20.807943
525 01:46:20.817386 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 01:46:20.817862
527 01:46:20.818271 Board ID = 1
528 01:46:20.818668 Set A53 clk to 24M
529 01:46:20.819062 Set A73 clk to 24M
530 01:46:20.823105 Set clk81 to 24M
531 01:46:20.823563 A53 clk: 1200 MHz
532 01:46:20.823967 A73 clk: 1200 MHz
533 01:46:20.826349 CLK81: 166.6M
534 01:46:20.826797 smccc: 00012a91
535 01:46:20.832007 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 01:46:20.837584 board id: 1
537 01:46:20.842881 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 01:46:20.853619 fw parse done
539 01:46:20.859515 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 01:46:20.902142 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 01:46:20.913254 PIEI prepare done
542 01:46:20.913722 fastboot data load
543 01:46:20.914139 fastboot data verify
544 01:46:20.918755 verify result: 266
545 01:46:20.924339 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 01:46:20.924798 LPDDR4 probe
547 01:46:20.925203 ddr clk to 1584MHz
548 01:46:20.932328 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 01:46:20.969648
550 01:46:20.970160 dmc_version 0001
551 01:46:20.976280 Check phy result
552 01:46:20.982107 INFO : End of CA training
553 01:46:20.982559 INFO : End of initialization
554 01:46:20.987711 INFO : Training has run successfully!
555 01:46:20.988210 Check phy result
556 01:46:20.993331 INFO : End of initialization
557 01:46:20.993785 INFO : End of read enable training
558 01:46:20.998886 INFO : End of fine write leveling
559 01:46:21.004534 INFO : End of Write leveling coarse delay
560 01:46:21.004987 INFO : Training has run successfully!
561 01:46:21.005390 Check phy result
562 01:46:21.010104 INFO : End of initialization
563 01:46:21.010556 INFO : End of read dq deskew training
564 01:46:21.015686 INFO : End of MPR read delay center optimization
565 01:46:21.021552 INFO : End of write delay center optimization
566 01:46:21.026943 INFO : End of read delay center optimization
567 01:46:21.027443 INFO : End of max read latency training
568 01:46:21.032459 INFO : Training has run successfully!
569 01:46:21.032798 1D training succeed
570 01:46:21.041634 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 01:46:21.089293 Check phy result
572 01:46:21.089712 INFO : End of initialization
573 01:46:21.111927 INFO : End of 2D read delay Voltage center optimization
574 01:46:21.131202 INFO : End of 2D read delay Voltage center optimization
575 01:46:21.182518 INFO : End of 2D write delay Voltage center optimization
576 01:46:21.233002 INFO : End of 2D write delay Voltage center optimization
577 01:46:21.238310 INFO : Training has run successfully!
578 01:46:21.238830
579 01:46:21.239250 channel==0
580 01:46:21.243864 RxClkDly_Margin_A0==88 ps 9
581 01:46:21.244407 TxDqDly_Margin_A0==98 ps 10
582 01:46:21.247172 RxClkDly_Margin_A1==88 ps 9
583 01:46:21.247653 TxDqDly_Margin_A1==98 ps 10
584 01:46:21.252796 TrainedVREFDQ_A0==74
585 01:46:21.253302 TrainedVREFDQ_A1==75
586 01:46:21.258352 VrefDac_Margin_A0==25
587 01:46:21.258821 DeviceVref_Margin_A0==40
588 01:46:21.259231 VrefDac_Margin_A1==24
589 01:46:21.263921 DeviceVref_Margin_A1==39
590 01:46:21.264415
591 01:46:21.264827
592 01:46:21.265228 channel==1
593 01:46:21.265621 RxClkDly_Margin_A0==88 ps 9
594 01:46:21.269547 TxDqDly_Margin_A0==98 ps 10
595 01:46:21.270011 RxClkDly_Margin_A1==88 ps 9
596 01:46:21.275209 TxDqDly_Margin_A1==98 ps 10
597 01:46:21.275698 TrainedVREFDQ_A0==77
598 01:46:21.276146 TrainedVREFDQ_A1==77
599 01:46:21.280754 VrefDac_Margin_A0==23
600 01:46:21.281214 DeviceVref_Margin_A0==37
601 01:46:21.286424 VrefDac_Margin_A1==24
602 01:46:21.286991 DeviceVref_Margin_A1==37
603 01:46:21.287392
604 01:46:21.292007 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 01:46:21.292713
606 01:46:21.319926 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000017 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
607 01:46:21.325490 2D training succeed
608 01:46:21.331032 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 01:46:21.331343 auto size-- 65535DDR cs0 size: 2048MB
610 01:46:21.336639 DDR cs1 size: 2048MB
611 01:46:21.336937 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 01:46:21.342227 cs0 DataBus test pass
613 01:46:21.342513 cs1 DataBus test pass
614 01:46:21.342729 cs0 AddrBus test pass
615 01:46:21.347813 cs1 AddrBus test pass
616 01:46:21.348113
617 01:46:21.348343 100bdlr_step_size ps== 426
618 01:46:21.348566 result report
619 01:46:21.353433 boot times 0Enable ddr reg access
620 01:46:21.361102 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 01:46:21.374683 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 01:46:21.947937 0.0;M3 CHK:0;cm4_sp_mode 0
623 01:46:21.948606 MVN_1=0x00000000
624 01:46:21.953340 MVN_2=0x00000000
625 01:46:21.959105 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 01:46:21.959620 OPS=0x10
627 01:46:21.960105 ring efuse init
628 01:46:21.960553 chipver efuse init
629 01:46:21.967293 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 01:46:21.967805 [0.018961 Inits done]
631 01:46:21.968243 secure task start!
632 01:46:21.974774 high task start!
633 01:46:21.975215 low task start!
634 01:46:21.975606 run into bl31
635 01:46:21.981416 NOTICE: BL31: v1.3(release):4fc40b1
636 01:46:21.989275 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 01:46:21.989740 NOTICE: BL31: G12A normal boot!
638 01:46:22.014536 NOTICE: BL31: BL33 decompress pass
639 01:46:22.020329 ERROR: Error initializing runtime service opteed_fast
640 01:46:23.253256
641 01:46:23.253869
642 01:46:23.261675 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 01:46:23.262141
644 01:46:23.262555 Model: Libre Computer AML-A311D-CC Alta
645 01:46:23.469369 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 01:46:23.493490 DRAM: 2 GiB (effective 3.8 GiB)
647 01:46:23.636474 Core: 408 devices, 31 uclasses, devicetree: separate
648 01:46:23.642342 WDT: Not starting watchdog@f0d0
649 01:46:23.674469 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 01:46:23.687017 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 01:46:23.692116 ** Bad device specification mmc 0 **
652 01:46:23.702341 Card did not respond to voltage select! : -110
653 01:46:23.709105 ** Bad device specification mmc 0 **
654 01:46:23.709546 Couldn't find partition mmc 0
655 01:46:23.718236 Card did not respond to voltage select! : -110
656 01:46:23.723816 ** Bad device specification mmc 0 **
657 01:46:23.724307 Couldn't find partition mmc 0
658 01:46:23.728956 Error: could not access storage.
659 01:46:24.071802 Net: eth0: ethernet@ff3f0000
660 01:46:24.072271 starting USB...
661 01:46:24.324278 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 01:46:24.324837 Starting the controller
663 01:46:24.331371 USB XHCI 1.10
664 01:46:26.042437 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 01:46:26.042858 bl2_stage_init 0x01
666 01:46:26.043082 bl2_stage_init 0x81
667 01:46:26.048111 hw id: 0x0000 - pwm id 0x01
668 01:46:26.048490 bl2_stage_init 0xc1
669 01:46:26.048806 bl2_stage_init 0x02
670 01:46:26.049110
671 01:46:26.053656 L0:00000000
672 01:46:26.054028 L1:20000703
673 01:46:26.054272 L2:00008067
674 01:46:26.054477 L3:14000000
675 01:46:26.059229 B2:00402000
676 01:46:26.059603 B1:e0f83180
677 01:46:26.059923
678 01:46:26.060276 TE: 58167
679 01:46:26.060587
680 01:46:26.064850 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 01:46:26.065132
682 01:46:26.065349 Board ID = 1
683 01:46:26.070426 Set A53 clk to 24M
684 01:46:26.070800 Set A73 clk to 24M
685 01:46:26.071114 Set clk81 to 24M
686 01:46:26.076116 A53 clk: 1200 MHz
687 01:46:26.076476 A73 clk: 1200 MHz
688 01:46:26.076802 CLK81: 166.6M
689 01:46:26.077042 smccc: 00012abe
690 01:46:26.081571 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 01:46:26.087110 board id: 1
692 01:46:26.093033 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 01:46:26.103689 fw parse done
694 01:46:26.109649 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 01:46:26.151441 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 01:46:26.163148 PIEI prepare done
697 01:46:26.163423 fastboot data load
698 01:46:26.163635 fastboot data verify
699 01:46:26.168846 verify result: 266
700 01:46:26.174338 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 01:46:26.174699 LPDDR4 probe
702 01:46:26.174994 ddr clk to 1584MHz
703 01:46:26.182461 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 01:46:26.219649
705 01:46:26.219921 dmc_version 0001
706 01:46:26.226454 Check phy result
707 01:46:26.232247 INFO : End of CA training
708 01:46:26.232498 INFO : End of initialization
709 01:46:26.237857 INFO : Training has run successfully!
710 01:46:26.238107 Check phy result
711 01:46:26.243352 INFO : End of initialization
712 01:46:26.243603 INFO : End of read enable training
713 01:46:26.248984 INFO : End of fine write leveling
714 01:46:26.254616 INFO : End of Write leveling coarse delay
715 01:46:26.254869 INFO : Training has run successfully!
716 01:46:26.255072 Check phy result
717 01:46:26.260210 INFO : End of initialization
718 01:46:26.260559 INFO : End of read dq deskew training
719 01:46:26.265789 INFO : End of MPR read delay center optimization
720 01:46:26.271377 INFO : End of write delay center optimization
721 01:46:26.277009 INFO : End of read delay center optimization
722 01:46:26.277361 INFO : End of max read latency training
723 01:46:26.282568 INFO : Training has run successfully!
724 01:46:26.282820 1D training succeed
725 01:46:26.291721 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 01:46:26.339478 Check phy result
727 01:46:26.339752 INFO : End of initialization
728 01:46:26.360366 INFO : End of 2D read delay Voltage center optimization
729 01:46:26.381592 INFO : End of 2D read delay Voltage center optimization
730 01:46:26.433680 INFO : End of 2D write delay Voltage center optimization
731 01:46:26.483004 INFO : End of 2D write delay Voltage center optimization
732 01:46:26.488576 INFO : Training has run successfully!
733 01:46:26.489022
734 01:46:26.489434 channel==0
735 01:46:26.494045 RxClkDly_Margin_A0==88 ps 9
736 01:46:26.494474 TxDqDly_Margin_A0==98 ps 10
737 01:46:26.497635 RxClkDly_Margin_A1==88 ps 9
738 01:46:26.498075 TxDqDly_Margin_A1==88 ps 9
739 01:46:26.503111 TrainedVREFDQ_A0==74
740 01:46:26.503550 TrainedVREFDQ_A1==74
741 01:46:26.503954 VrefDac_Margin_A0==25
742 01:46:26.508735 DeviceVref_Margin_A0==40
743 01:46:26.509168 VrefDac_Margin_A1==25
744 01:46:26.514320 DeviceVref_Margin_A1==40
745 01:46:26.514756
746 01:46:26.515160
747 01:46:26.515556 channel==1
748 01:46:26.515949 RxClkDly_Margin_A0==98 ps 10
749 01:46:26.517829 TxDqDly_Margin_A0==88 ps 9
750 01:46:26.523603 RxClkDly_Margin_A1==98 ps 10
751 01:46:26.524064 TxDqDly_Margin_A1==98 ps 10
752 01:46:26.524474 TrainedVREFDQ_A0==74
753 01:46:26.529082 TrainedVREFDQ_A1==77
754 01:46:26.529518 VrefDac_Margin_A0==22
755 01:46:26.534699 DeviceVref_Margin_A0==40
756 01:46:26.535137 VrefDac_Margin_A1==22
757 01:46:26.535541 DeviceVref_Margin_A1==37
758 01:46:26.535935
759 01:46:26.543629 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 01:46:26.544103
761 01:46:26.571651 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
762 01:46:26.572171 2D training succeed
763 01:46:26.577171 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 01:46:26.582822 auto size-- 65535DDR cs0 size: 2048MB
765 01:46:26.583275 DDR cs1 size: 2048MB
766 01:46:26.588374 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 01:46:26.588803 cs0 DataBus test pass
768 01:46:26.593853 cs1 DataBus test pass
769 01:46:26.594273 cs0 AddrBus test pass
770 01:46:26.594671 cs1 AddrBus test pass
771 01:46:26.599489
772 01:46:26.599916 100bdlr_step_size ps== 420
773 01:46:26.600360 result report
774 01:46:26.605076 boot times 0Enable ddr reg access
775 01:46:26.611331 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 01:46:26.624816 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 01:46:27.198572 0.0;M3 CHK:0;cm4_sp_mode 0
778 01:46:27.199134 MVN_1=0x00000000
779 01:46:27.204039 MVN_2=0x00000000
780 01:46:27.209784 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 01:46:27.210276 OPS=0x10
782 01:46:27.210676 ring efuse init
783 01:46:27.211061 chipver efuse init
784 01:46:27.215431 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 01:46:27.220931 [0.018961 Inits done]
786 01:46:27.221376 secure task start!
787 01:46:27.221767 high task start!
788 01:46:27.225492 low task start!
789 01:46:27.225936 run into bl31
790 01:46:27.232188 NOTICE: BL31: v1.3(release):4fc40b1
791 01:46:27.239943 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 01:46:27.240425 NOTICE: BL31: G12A normal boot!
793 01:46:27.265363 NOTICE: BL31: BL33 decompress pass
794 01:46:27.271046 ERROR: Error initializing runtime service opteed_fast
795 01:46:28.503859
796 01:46:28.504488
797 01:46:28.512276 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 01:46:28.512770
799 01:46:28.513190 Model: Libre Computer AML-A311D-CC Alta
800 01:46:28.719821 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 01:46:28.743201 DRAM: 2 GiB (effective 3.8 GiB)
802 01:46:28.887105 Core: 408 devices, 31 uclasses, devicetree: separate
803 01:46:28.892702 WDT: Not starting watchdog@f0d0
804 01:46:28.925231 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 01:46:28.937665 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 01:46:28.941801 ** Bad device specification mmc 0 **
807 01:46:28.952976 Card did not respond to voltage select! : -110
808 01:46:28.960872 ** Bad device specification mmc 0 **
809 01:46:28.961338 Couldn't find partition mmc 0
810 01:46:28.969052 Card did not respond to voltage select! : -110
811 01:46:28.974526 ** Bad device specification mmc 0 **
812 01:46:28.974993 Couldn't find partition mmc 0
813 01:46:28.978965 Error: could not access storage.
814 01:46:29.321687 Net: eth0: ethernet@ff3f0000
815 01:46:29.322222 starting USB...
816 01:46:29.573866 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 01:46:29.574474 Starting the controller
818 01:46:29.580007 USB XHCI 1.10
819 01:46:31.744058 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 01:46:31.744684 bl2_stage_init 0x01
821 01:46:31.745092 bl2_stage_init 0x81
822 01:46:31.749600 hw id: 0x0000 - pwm id 0x01
823 01:46:31.750091 bl2_stage_init 0xc1
824 01:46:31.750484 bl2_stage_init 0x02
825 01:46:31.750882
826 01:46:31.755229 L0:00000000
827 01:46:31.755716 L1:20000703
828 01:46:31.756141 L2:00008067
829 01:46:31.756530 L3:14000000
830 01:46:31.760702 B2:00402000
831 01:46:31.761192 B1:e0f83180
832 01:46:31.761576
833 01:46:31.761962 TE: 58124
834 01:46:31.762362
835 01:46:31.766388 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 01:46:31.766883
837 01:46:31.767282 Board ID = 1
838 01:46:31.772025 Set A53 clk to 24M
839 01:46:31.772510 Set A73 clk to 24M
840 01:46:31.772896 Set clk81 to 24M
841 01:46:31.777586 A53 clk: 1200 MHz
842 01:46:31.778080 A73 clk: 1200 MHz
843 01:46:31.778476 CLK81: 166.6M
844 01:46:31.778865 smccc: 00012a92
845 01:46:31.783253 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 01:46:31.788717 board id: 1
847 01:46:31.794410 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 01:46:31.805245 fw parse done
849 01:46:31.810548 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 01:46:31.853065 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 01:46:31.864710 PIEI prepare done
852 01:46:31.865175 fastboot data load
853 01:46:31.865583 fastboot data verify
854 01:46:31.870409 verify result: 266
855 01:46:31.876052 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 01:46:31.876531 LPDDR4 probe
857 01:46:31.876941 ddr clk to 1584MHz
858 01:46:31.883122 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 01:46:31.920982
860 01:46:31.921470 dmc_version 0001
861 01:46:31.926972 Check phy result
862 01:46:31.933755 INFO : End of CA training
863 01:46:31.934217 INFO : End of initialization
864 01:46:31.939416 INFO : Training has run successfully!
865 01:46:31.939874 Check phy result
866 01:46:31.945018 INFO : End of initialization
867 01:46:31.945478 INFO : End of read enable training
868 01:46:31.950558 INFO : End of fine write leveling
869 01:46:31.956271 INFO : End of Write leveling coarse delay
870 01:46:31.956729 INFO : Training has run successfully!
871 01:46:31.957136 Check phy result
872 01:46:31.961784 INFO : End of initialization
873 01:46:31.962250 INFO : End of read dq deskew training
874 01:46:31.967407 INFO : End of MPR read delay center optimization
875 01:46:31.973006 INFO : End of write delay center optimization
876 01:46:31.978519 INFO : End of read delay center optimization
877 01:46:31.978975 INFO : End of max read latency training
878 01:46:31.984268 INFO : Training has run successfully!
879 01:46:31.984726 1D training succeed
880 01:46:31.992563 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 01:46:32.040957 Check phy result
882 01:46:32.041473 INFO : End of initialization
883 01:46:32.062395 INFO : End of 2D read delay Voltage center optimization
884 01:46:32.082391 INFO : End of 2D read delay Voltage center optimization
885 01:46:32.134696 INFO : End of 2D write delay Voltage center optimization
886 01:46:32.183848 INFO : End of 2D write delay Voltage center optimization
887 01:46:32.189514 INFO : Training has run successfully!
888 01:46:32.189978
889 01:46:32.190380 channel==0
890 01:46:32.195008 RxClkDly_Margin_A0==88 ps 9
891 01:46:32.195472 TxDqDly_Margin_A0==98 ps 10
892 01:46:32.200579 RxClkDly_Margin_A1==88 ps 9
893 01:46:32.201043 TxDqDly_Margin_A1==88 ps 9
894 01:46:32.201461 TrainedVREFDQ_A0==74
895 01:46:32.206423 TrainedVREFDQ_A1==74
896 01:46:32.206905 VrefDac_Margin_A0==25
897 01:46:32.207314 DeviceVref_Margin_A0==40
898 01:46:32.211796 VrefDac_Margin_A1==25
899 01:46:32.212285 DeviceVref_Margin_A1==40
900 01:46:32.212671
901 01:46:32.213053
902 01:46:32.213432 channel==1
903 01:46:32.217426 RxClkDly_Margin_A0==88 ps 9
904 01:46:32.217876 TxDqDly_Margin_A0==98 ps 10
905 01:46:32.222999 RxClkDly_Margin_A1==98 ps 10
906 01:46:32.223443 TxDqDly_Margin_A1==88 ps 9
907 01:46:32.228604 TrainedVREFDQ_A0==77
908 01:46:32.229054 TrainedVREFDQ_A1==77
909 01:46:32.229438 VrefDac_Margin_A0==22
910 01:46:32.234470 DeviceVref_Margin_A0==37
911 01:46:32.234914 VrefDac_Margin_A1==22
912 01:46:32.239823 DeviceVref_Margin_A1==37
913 01:46:32.240308
914 01:46:32.240698 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 01:46:32.241079
916 01:46:32.273475 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000016 00000018 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
917 01:46:32.273963 2D training succeed
918 01:46:32.279028 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 01:46:32.284622 auto size-- 65535DDR cs0 size: 2048MB
920 01:46:32.285068 DDR cs1 size: 2048MB
921 01:46:32.290349 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 01:46:32.290796 cs0 DataBus test pass
923 01:46:32.295741 cs1 DataBus test pass
924 01:46:32.296228 cs0 AddrBus test pass
925 01:46:32.296619 cs1 AddrBus test pass
926 01:46:32.296996
927 01:46:32.301360 100bdlr_step_size ps== 420
928 01:46:32.301812 result report
929 01:46:32.306912 boot times 0Enable ddr reg access
930 01:46:32.311410 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 01:46:32.324660 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 01:46:32.897630 0.0;M3 CHK:0;cm4_sp_mode 0
933 01:46:32.898240 MVN_1=0x00000000
934 01:46:32.903142 MVN_2=0x00000000
935 01:46:32.908917 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 01:46:32.909381 OPS=0x10
937 01:46:32.909788 ring efuse init
938 01:46:32.910187 chipver efuse init
939 01:46:32.914489 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 01:46:32.920066 [0.018961 Inits done]
941 01:46:32.920541 secure task start!
942 01:46:32.920960 high task start!
943 01:46:32.923702 low task start!
944 01:46:32.924191 run into bl31
945 01:46:32.931315 NOTICE: BL31: v1.3(release):4fc40b1
946 01:46:32.939143 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 01:46:32.939613 NOTICE: BL31: G12A normal boot!
948 01:46:32.964458 NOTICE: BL31: BL33 decompress pass
949 01:46:32.970134 ERROR: Error initializing runtime service opteed_fast
950 01:46:34.202982
951 01:46:34.203580
952 01:46:34.211418 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 01:46:34.211890
954 01:46:34.212340 Model: Libre Computer AML-A311D-CC Alta
955 01:46:34.419841 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 01:46:34.443229 DRAM: 2 GiB (effective 3.8 GiB)
957 01:46:34.586223 Core: 408 devices, 31 uclasses, devicetree: separate
958 01:46:34.592086 WDT: Not starting watchdog@f0d0
959 01:46:34.624321 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 01:46:34.636852 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 01:46:34.640827 ** Bad device specification mmc 0 **
962 01:46:34.652177 Card did not respond to voltage select! : -110
963 01:46:34.658841 ** Bad device specification mmc 0 **
964 01:46:34.659337 Couldn't find partition mmc 0
965 01:46:34.668123 Card did not respond to voltage select! : -110
966 01:46:34.673601 ** Bad device specification mmc 0 **
967 01:46:34.674074 Couldn't find partition mmc 0
968 01:46:34.677808 Error: could not access storage.
969 01:46:35.022111 Net: eth0: ethernet@ff3f0000
970 01:46:35.022656 starting USB...
971 01:46:35.274035 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 01:46:35.274575 Starting the controller
973 01:46:35.280325 USB XHCI 1.10
974 01:46:36.835185 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 01:46:36.843480 scanning usb for storage devices... 0 Storage Device(s) found
977 01:46:36.894964 Hit any key to stop autoboot: 1
978 01:46:36.896031 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
979 01:46:36.896636 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
980 01:46:36.897107 Setting prompt string to ['=>']
981 01:46:36.897582 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
982 01:46:36.911003 0
983 01:46:36.911853 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 01:46:36.912371 Sending with 10 millisecond of delay
986 01:46:38.046903 => setenv autoload no
987 01:46:38.057687 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
988 01:46:38.062339 setenv autoload no
989 01:46:38.063043 Sending with 10 millisecond of delay
991 01:46:39.859610 => setenv initrd_high 0xffffffff
992 01:46:39.870386 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
993 01:46:39.871187 setenv initrd_high 0xffffffff
994 01:46:39.871885 Sending with 10 millisecond of delay
996 01:46:41.488097 => setenv fdt_high 0xffffffff
997 01:46:41.498845 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
998 01:46:41.499665 setenv fdt_high 0xffffffff
999 01:46:41.500424 Sending with 10 millisecond of delay
1001 01:46:41.792171 => dhcp
1002 01:46:41.802865 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1003 01:46:41.803650 dhcp
1004 01:46:41.804119 Speed: 1000, full duplex
1005 01:46:41.804532 BOOTP broadcast 1
1006 01:46:41.813913 DHCP client bound to address 192.168.6.27 (11 ms)
1007 01:46:41.814650 Sending with 10 millisecond of delay
1009 01:46:43.490991 => setenv serverip 192.168.6.2
1010 01:46:43.501768 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1011 01:46:43.502654 setenv serverip 192.168.6.2
1012 01:46:43.503337 Sending with 10 millisecond of delay
1014 01:46:47.227069 => tftpboot 0x01080000 949465/tftp-deploy-uamh8ord/kernel/uImage
1015 01:46:47.238210 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1016 01:46:47.239121 tftpboot 0x01080000 949465/tftp-deploy-uamh8ord/kernel/uImage
1017 01:46:47.239573 Speed: 1000, full duplex
1018 01:46:47.240028 Using ethernet@ff3f0000 device
1019 01:46:47.240526 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1020 01:46:47.245962 Filename '949465/tftp-deploy-uamh8ord/kernel/uImage'.
1021 01:46:47.249162 Load address: 0x1080000
1022 01:46:49.594882 Loading: *################################################## 36.1 MiB
1023 01:46:49.595508 15.4 MiB/s
1024 01:46:49.595947 done
1025 01:46:49.599263 Bytes transferred = 37878336 (241fa40 hex)
1026 01:46:49.600082 Sending with 10 millisecond of delay
1028 01:46:54.287721 => tftpboot 0x08000000 949465/tftp-deploy-uamh8ord/ramdisk/ramdisk.cpio.gz.uboot
1029 01:46:54.298505 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1030 01:46:54.299309 tftpboot 0x08000000 949465/tftp-deploy-uamh8ord/ramdisk/ramdisk.cpio.gz.uboot
1031 01:46:54.299753 Speed: 1000, full duplex
1032 01:46:54.300263 Using ethernet@ff3f0000 device
1033 01:46:54.301483 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1034 01:46:54.309877 Filename '949465/tftp-deploy-uamh8ord/ramdisk/ramdisk.cpio.gz.uboot'.
1035 01:46:54.310328 Load address: 0x8000000
1036 01:47:01.658732 Loading: *#####T ############################################ UDP wrong checksum 00000005 0000d064
1037 01:47:06.658999 T UDP wrong checksum 00000005 0000d064
1038 01:47:16.662104 T T UDP wrong checksum 00000005 0000d064
1039 01:47:30.101048 T T UDP wrong checksum 000000ff 0000a717
1040 01:47:30.117820 UDP wrong checksum 000000ff 00003e0a
1041 01:47:32.888868 T UDP wrong checksum 000000ff 00000122
1042 01:47:32.938731 UDP wrong checksum 000000ff 00008b14
1043 01:47:36.666194 T UDP wrong checksum 00000005 0000d064
1044 01:47:37.009008 UDP wrong checksum 000000ff 00000d29
1045 01:47:37.050740 UDP wrong checksum 000000ff 0000a91b
1046 01:47:50.596585 T T UDP wrong checksum 000000ff 00000444
1047 01:47:50.608747 UDP wrong checksum 000000ff 00009a36
1048 01:47:51.670303
1049 01:47:51.670927 Retry count exceeded; starting again
1051 01:47:51.672328 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1054 01:47:51.674095 end: 2.4 uboot-commands (duration 00:01:47) [common]
1056 01:47:51.675440 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1058 01:47:51.676719 end: 2 uboot-action (duration 00:01:47) [common]
1060 01:47:51.678398 Cleaning after the job
1061 01:47:51.678972 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/ramdisk
1062 01:47:51.680310 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/kernel
1063 01:47:51.714961 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/dtb
1064 01:47:51.715757 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/nfsrootfs
1065 01:47:51.891204 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949465/tftp-deploy-uamh8ord/modules
1066 01:47:51.914061 start: 4.1 power-off (timeout 00:00:30) [common]
1067 01:47:51.914730 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1068 01:47:51.951734 >> OK - accepted request
1069 01:47:51.953862 Returned 0 in 0 seconds
1070 01:47:52.055008 end: 4.1 power-off (duration 00:00:00) [common]
1072 01:47:52.056101 start: 4.2 read-feedback (timeout 00:10:00) [common]
1073 01:47:52.056972 Listened to connection for namespace 'common' for up to 1s
1074 01:47:53.057223 Finalising connection for namespace 'common'
1075 01:47:53.058027 Disconnecting from shell: Finalise
1076 01:47:53.058621 =>
1077 01:47:53.159789 end: 4.2 read-feedback (duration 00:00:01) [common]
1078 01:47:53.160671 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949465
1079 01:47:56.389718 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949465
1080 01:47:56.390366 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.