Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:48:24.449012 lava-dispatcher, installed at version: 2024.01
2 01:48:24.449827 start: 0 validate
3 01:48:24.450317 Start time: 2024-11-07 01:48:24.450286+00:00 (UTC)
4 01:48:24.450873 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:48:24.451419 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:48:24.489612 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:48:24.490172 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 01:48:24.519404 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:48:24.520066 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:48:24.551521 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:48:24.552033 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:48:24.583366 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:48:24.583846 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
14 01:48:24.619115 validate duration: 0.17
16 01:48:24.619976 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:48:24.620373 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:48:24.620701 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:48:24.621306 Not decompressing ramdisk as can be used compressed.
20 01:48:24.621764 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:48:24.622039 saving as /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/ramdisk/initrd.cpio.gz
22 01:48:24.622305 total size: 5628169 (5 MB)
23 01:48:24.657555 progress 0 % (0 MB)
24 01:48:24.662881 progress 5 % (0 MB)
25 01:48:24.668206 progress 10 % (0 MB)
26 01:48:24.672809 progress 15 % (0 MB)
27 01:48:24.677863 progress 20 % (1 MB)
28 01:48:24.682351 progress 25 % (1 MB)
29 01:48:24.687140 progress 30 % (1 MB)
30 01:48:24.692027 progress 35 % (1 MB)
31 01:48:24.696523 progress 40 % (2 MB)
32 01:48:24.701284 progress 45 % (2 MB)
33 01:48:24.705544 progress 50 % (2 MB)
34 01:48:24.710353 progress 55 % (2 MB)
35 01:48:24.715130 progress 60 % (3 MB)
36 01:48:24.719481 progress 65 % (3 MB)
37 01:48:24.724264 progress 70 % (3 MB)
38 01:48:24.728754 progress 75 % (4 MB)
39 01:48:24.733479 progress 80 % (4 MB)
40 01:48:24.737753 progress 85 % (4 MB)
41 01:48:24.742491 progress 90 % (4 MB)
42 01:48:24.747087 progress 95 % (5 MB)
43 01:48:24.751015 progress 100 % (5 MB)
44 01:48:24.751786 5 MB downloaded in 0.13 s (41.47 MB/s)
45 01:48:24.752447 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:48:24.753560 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:48:24.753918 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:48:24.754246 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:48:24.754805 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/kernel/Image
51 01:48:24.755095 saving as /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/kernel/Image
52 01:48:24.755350 total size: 37878272 (36 MB)
53 01:48:24.755603 No compression specified
54 01:48:24.791355 progress 0 % (0 MB)
55 01:48:24.819340 progress 5 % (1 MB)
56 01:48:24.847336 progress 10 % (3 MB)
57 01:48:24.874106 progress 15 % (5 MB)
58 01:48:24.897233 progress 20 % (7 MB)
59 01:48:24.920089 progress 25 % (9 MB)
60 01:48:24.943206 progress 30 % (10 MB)
61 01:48:24.966465 progress 35 % (12 MB)
62 01:48:24.989530 progress 40 % (14 MB)
63 01:48:25.013020 progress 45 % (16 MB)
64 01:48:25.035940 progress 50 % (18 MB)
65 01:48:25.059136 progress 55 % (19 MB)
66 01:48:25.082335 progress 60 % (21 MB)
67 01:48:25.106011 progress 65 % (23 MB)
68 01:48:25.129157 progress 70 % (25 MB)
69 01:48:25.152519 progress 75 % (27 MB)
70 01:48:25.175752 progress 80 % (28 MB)
71 01:48:25.199482 progress 85 % (30 MB)
72 01:48:25.222671 progress 90 % (32 MB)
73 01:48:25.245936 progress 95 % (34 MB)
74 01:48:25.268477 progress 100 % (36 MB)
75 01:48:25.269238 36 MB downloaded in 0.51 s (70.30 MB/s)
76 01:48:25.269725 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:48:25.270552 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:48:25.270832 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:48:25.271099 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:48:25.271568 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:48:25.271843 saving as /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:48:25.272079 total size: 54703 (0 MB)
84 01:48:25.272291 No compression specified
85 01:48:25.310780 progress 59 % (0 MB)
86 01:48:25.311632 progress 100 % (0 MB)
87 01:48:25.312233 0 MB downloaded in 0.04 s (1.30 MB/s)
88 01:48:25.312746 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:48:25.313576 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:48:25.313840 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:48:25.314103 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:48:25.314552 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:48:25.314797 saving as /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/nfsrootfs/full.rootfs.tar
95 01:48:25.315003 total size: 120894716 (115 MB)
96 01:48:25.315210 Using unxz to decompress xz
97 01:48:25.349472 progress 0 % (0 MB)
98 01:48:26.146922 progress 5 % (5 MB)
99 01:48:26.989615 progress 10 % (11 MB)
100 01:48:27.783015 progress 15 % (17 MB)
101 01:48:28.517874 progress 20 % (23 MB)
102 01:48:29.114339 progress 25 % (28 MB)
103 01:48:29.939862 progress 30 % (34 MB)
104 01:48:30.744451 progress 35 % (40 MB)
105 01:48:31.091726 progress 40 % (46 MB)
106 01:48:31.464491 progress 45 % (51 MB)
107 01:48:32.233510 progress 50 % (57 MB)
108 01:48:33.113684 progress 55 % (63 MB)
109 01:48:33.898990 progress 60 % (69 MB)
110 01:48:34.658415 progress 65 % (74 MB)
111 01:48:35.456394 progress 70 % (80 MB)
112 01:48:36.317812 progress 75 % (86 MB)
113 01:48:37.107445 progress 80 % (92 MB)
114 01:48:37.867712 progress 85 % (98 MB)
115 01:48:38.716200 progress 90 % (103 MB)
116 01:48:39.489979 progress 95 % (109 MB)
117 01:48:40.319482 progress 100 % (115 MB)
118 01:48:40.331962 115 MB downloaded in 15.02 s (7.68 MB/s)
119 01:48:40.333488 end: 1.4.1 http-download (duration 00:00:15) [common]
121 01:48:40.335612 end: 1.4 download-retry (duration 00:00:15) [common]
122 01:48:40.336318 start: 1.5 download-retry (timeout 00:09:44) [common]
123 01:48:40.336986 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 01:48:40.338140 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/modules.tar.xz
125 01:48:40.338738 saving as /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/modules/modules.tar
126 01:48:40.339264 total size: 11769360 (11 MB)
127 01:48:40.339790 Using unxz to decompress xz
128 01:48:40.383881 progress 0 % (0 MB)
129 01:48:40.451539 progress 5 % (0 MB)
130 01:48:40.526570 progress 10 % (1 MB)
131 01:48:40.623614 progress 15 % (1 MB)
132 01:48:40.722069 progress 20 % (2 MB)
133 01:48:40.803419 progress 25 % (2 MB)
134 01:48:40.880242 progress 30 % (3 MB)
135 01:48:40.960812 progress 35 % (3 MB)
136 01:48:41.040771 progress 40 % (4 MB)
137 01:48:41.117197 progress 45 % (5 MB)
138 01:48:41.202539 progress 50 % (5 MB)
139 01:48:41.284728 progress 55 % (6 MB)
140 01:48:41.370295 progress 60 % (6 MB)
141 01:48:41.452282 progress 65 % (7 MB)
142 01:48:41.535035 progress 70 % (7 MB)
143 01:48:41.630816 progress 75 % (8 MB)
144 01:48:41.730797 progress 80 % (9 MB)
145 01:48:41.828287 progress 85 % (9 MB)
146 01:48:41.914973 progress 90 % (10 MB)
147 01:48:41.994872 progress 95 % (10 MB)
148 01:48:42.075380 progress 100 % (11 MB)
149 01:48:42.086243 11 MB downloaded in 1.75 s (6.42 MB/s)
150 01:48:42.087421 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:48:42.089571 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:48:42.090247 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 01:48:42.090906 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 01:49:00.312878 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/949466/extract-nfsrootfs-vl3snngy
156 01:49:00.313468 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
157 01:49:00.313789 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
158 01:49:00.314443 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2
159 01:49:00.314934 makedir: /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin
160 01:49:00.315350 makedir: /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/tests
161 01:49:00.315737 makedir: /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/results
162 01:49:00.316135 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-add-keys
163 01:49:00.316692 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-add-sources
164 01:49:00.317192 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-background-process-start
165 01:49:00.317748 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-background-process-stop
166 01:49:00.318348 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-common-functions
167 01:49:00.318844 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-echo-ipv4
168 01:49:00.319322 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-install-packages
169 01:49:00.319795 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-installed-packages
170 01:49:00.320314 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-os-build
171 01:49:00.320804 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-probe-channel
172 01:49:00.321276 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-probe-ip
173 01:49:00.321747 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-target-ip
174 01:49:00.322217 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-target-mac
175 01:49:00.322693 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-target-storage
176 01:49:00.323173 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-test-case
177 01:49:00.323652 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-test-event
178 01:49:00.324170 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-test-feedback
179 01:49:00.324678 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-test-raise
180 01:49:00.325153 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-test-reference
181 01:49:00.325648 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-test-runner
182 01:49:00.326130 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-test-set
183 01:49:00.326602 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-test-shell
184 01:49:00.327085 Updating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-add-keys (debian)
185 01:49:00.327615 Updating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-add-sources (debian)
186 01:49:00.328145 Updating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-install-packages (debian)
187 01:49:00.328752 Updating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-installed-packages (debian)
188 01:49:00.329269 Updating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/bin/lava-os-build (debian)
189 01:49:00.329712 Creating /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/environment
190 01:49:00.330084 LAVA metadata
191 01:49:00.330340 - LAVA_JOB_ID=949466
192 01:49:00.330555 - LAVA_DISPATCHER_IP=192.168.6.2
193 01:49:00.330924 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
194 01:49:00.331888 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 01:49:00.332229 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
196 01:49:00.332437 skipped lava-vland-overlay
197 01:49:00.332678 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 01:49:00.332929 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
199 01:49:00.333146 skipped lava-multinode-overlay
200 01:49:00.333386 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 01:49:00.333634 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
202 01:49:00.333880 Loading test definitions
203 01:49:00.334151 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
204 01:49:00.334368 Using /lava-949466 at stage 0
205 01:49:00.335476 uuid=949466_1.6.2.4.1 testdef=None
206 01:49:00.335786 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 01:49:00.336072 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
208 01:49:00.337659 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 01:49:00.338453 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
211 01:49:00.340469 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 01:49:00.341300 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
214 01:49:00.343158 runner path: /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/0/tests/0_timesync-off test_uuid 949466_1.6.2.4.1
215 01:49:00.343720 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 01:49:00.344564 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
218 01:49:00.344786 Using /lava-949466 at stage 0
219 01:49:00.345141 Fetching tests from https://github.com/kernelci/test-definitions.git
220 01:49:00.345434 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/0/tests/1_kselftest-rtc'
221 01:49:03.805392 Running '/usr/bin/git checkout kernelci.org
222 01:49:04.443887 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 01:49:04.445415 uuid=949466_1.6.2.4.5 testdef=None
224 01:49:04.445784 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 01:49:04.446546 start: 1.6.2.4.6 test-overlay (timeout 00:09:20) [common]
227 01:49:04.450976 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 01:49:04.451940 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:20) [common]
230 01:49:04.460188 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 01:49:04.461151 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:20) [common]
233 01:49:04.465643 runner path: /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/0/tests/1_kselftest-rtc test_uuid 949466_1.6.2.4.5
234 01:49:04.466038 BOARD='meson-g12b-a311d-libretech-cc'
235 01:49:04.466255 BRANCH='mainline'
236 01:49:04.466485 SKIPFILE='/dev/null'
237 01:49:04.466760 SKIP_INSTALL='True'
238 01:49:04.466969 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/kselftest.tar.xz'
239 01:49:04.467189 TST_CASENAME=''
240 01:49:04.467414 TST_CMDFILES='rtc'
241 01:49:04.468227 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 01:49:04.469245 Creating lava-test-runner.conf files
244 01:49:04.469472 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949466/lava-overlay-d8vpn1b2/lava-949466/0 for stage 0
245 01:49:04.469979 - 0_timesync-off
246 01:49:04.470266 - 1_kselftest-rtc
247 01:49:04.470659 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 01:49:04.470966 start: 1.6.2.5 compress-overlay (timeout 00:09:20) [common]
249 01:49:27.953742 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 01:49:27.954302 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 01:49:27.954616 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 01:49:27.954943 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 01:49:27.955291 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 01:49:28.588858 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 01:49:28.589341 start: 1.6.4 extract-modules (timeout 00:08:56) [common]
256 01:49:28.589593 extracting modules file /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949466/extract-nfsrootfs-vl3snngy
257 01:49:29.957122 extracting modules file /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949466/extract-overlay-ramdisk-c4z65vw8/ramdisk
258 01:49:31.350484 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 01:49:31.350969 start: 1.6.5 apply-overlay-tftp (timeout 00:08:53) [common]
260 01:49:31.351250 [common] Applying overlay to NFS
261 01:49:31.351467 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949466/compress-overlay-2kk_jmi_/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949466/extract-nfsrootfs-vl3snngy
262 01:49:34.108110 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 01:49:34.108588 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 01:49:34.108861 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 01:49:34.109097 Converting downloaded kernel to a uImage
266 01:49:34.109443 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/kernel/Image /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/kernel/uImage
267 01:49:34.511319 output: Image Name:
268 01:49:34.511833 output: Created: Thu Nov 7 01:49:34 2024
269 01:49:34.512182 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 01:49:34.512468 output: Data Size: 37878272 Bytes = 36990.50 KiB = 36.12 MiB
271 01:49:34.512745 output: Load Address: 01080000
272 01:49:34.513019 output: Entry Point: 01080000
273 01:49:34.513280 output:
274 01:49:34.513711 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 01:49:34.514102 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 01:49:34.514451 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 01:49:34.514792 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 01:49:34.515169 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 01:49:34.515497 Building ramdisk /var/lib/lava/dispatcher/tmp/949466/extract-overlay-ramdisk-c4z65vw8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949466/extract-overlay-ramdisk-c4z65vw8/ramdisk
280 01:49:36.733532 >> 173435 blocks
281 01:49:44.901909 Adding RAMdisk u-boot header.
282 01:49:44.902354 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949466/extract-overlay-ramdisk-c4z65vw8/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949466/extract-overlay-ramdisk-c4z65vw8/ramdisk.cpio.gz.uboot
283 01:49:45.214296 output: Image Name:
284 01:49:45.214717 output: Created: Thu Nov 7 01:49:44 2024
285 01:49:45.215138 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 01:49:45.215559 output: Data Size: 24147209 Bytes = 23581.26 KiB = 23.03 MiB
287 01:49:45.215969 output: Load Address: 00000000
288 01:49:45.216437 output: Entry Point: 00000000
289 01:49:45.216844 output:
290 01:49:45.217947 rename /var/lib/lava/dispatcher/tmp/949466/extract-overlay-ramdisk-c4z65vw8/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/ramdisk/ramdisk.cpio.gz.uboot
291 01:49:45.218680 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 01:49:45.219238 end: 1.6 prepare-tftp-overlay (duration 00:01:03) [common]
293 01:49:45.219777 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:39) [common]
294 01:49:45.220260 No LXC device requested
295 01:49:45.220770 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 01:49:45.221289 start: 1.8 deploy-device-env (timeout 00:08:39) [common]
297 01:49:45.221792 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 01:49:45.222206 Checking files for TFTP limit of 4294967296 bytes.
299 01:49:45.224907 end: 1 tftp-deploy (duration 00:01:21) [common]
300 01:49:45.225496 start: 2 uboot-action (timeout 00:05:00) [common]
301 01:49:45.226035 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 01:49:45.226542 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 01:49:45.227057 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 01:49:45.227596 Using kernel file from prepare-kernel: 949466/tftp-deploy-ao731dlr/kernel/uImage
305 01:49:45.228256 substitutions:
306 01:49:45.228679 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 01:49:45.229089 - {DTB_ADDR}: 0x01070000
308 01:49:45.229491 - {DTB}: 949466/tftp-deploy-ao731dlr/dtb/meson-g12b-a311d-libretech-cc.dtb
309 01:49:45.229974 - {INITRD}: 949466/tftp-deploy-ao731dlr/ramdisk/ramdisk.cpio.gz.uboot
310 01:49:45.230411 - {KERNEL_ADDR}: 0x01080000
311 01:49:45.230840 - {KERNEL}: 949466/tftp-deploy-ao731dlr/kernel/uImage
312 01:49:45.231255 - {LAVA_MAC}: None
313 01:49:45.231703 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/949466/extract-nfsrootfs-vl3snngy
314 01:49:45.232145 - {NFS_SERVER_IP}: 192.168.6.2
315 01:49:45.232548 - {PRESEED_CONFIG}: None
316 01:49:45.232951 - {PRESEED_LOCAL}: None
317 01:49:45.233350 - {RAMDISK_ADDR}: 0x08000000
318 01:49:45.233800 - {RAMDISK}: 949466/tftp-deploy-ao731dlr/ramdisk/ramdisk.cpio.gz.uboot
319 01:49:45.234232 - {ROOT_PART}: None
320 01:49:45.234632 - {ROOT}: None
321 01:49:45.235024 - {SERVER_IP}: 192.168.6.2
322 01:49:45.235415 - {TEE_ADDR}: 0x83000000
323 01:49:45.235804 - {TEE}: None
324 01:49:45.236229 Parsed boot commands:
325 01:49:45.236615 - setenv autoload no
326 01:49:45.237009 - setenv initrd_high 0xffffffff
327 01:49:45.237479 - setenv fdt_high 0xffffffff
328 01:49:45.237909 - dhcp
329 01:49:45.238310 - setenv serverip 192.168.6.2
330 01:49:45.238743 - tftpboot 0x01080000 949466/tftp-deploy-ao731dlr/kernel/uImage
331 01:49:45.239161 - tftpboot 0x08000000 949466/tftp-deploy-ao731dlr/ramdisk/ramdisk.cpio.gz.uboot
332 01:49:45.239565 - tftpboot 0x01070000 949466/tftp-deploy-ao731dlr/dtb/meson-g12b-a311d-libretech-cc.dtb
333 01:49:45.239967 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/949466/extract-nfsrootfs-vl3snngy,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 01:49:45.240453 - bootm 0x01080000 0x08000000 0x01070000
335 01:49:45.240993 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 01:49:45.242510 start: 2.3 connect-device (timeout 00:05:00) [common]
338 01:49:45.242936 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 01:49:45.258102 Setting prompt string to ['lava-test: # ']
340 01:49:45.259823 end: 2.3 connect-device (duration 00:00:00) [common]
341 01:49:45.260575 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 01:49:45.261267 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 01:49:45.261892 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 01:49:45.263097 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 01:49:45.300456 >> OK - accepted request
346 01:49:45.303052 Returned 0 in 0 seconds
347 01:49:45.404448 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 01:49:45.406661 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 01:49:45.407413 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 01:49:45.408154 Setting prompt string to ['Hit any key to stop autoboot']
352 01:49:45.408828 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 01:49:45.410943 Trying 192.168.56.21...
354 01:49:45.411620 Connected to conserv1.
355 01:49:45.412213 Escape character is '^]'.
356 01:49:45.412786
357 01:49:45.413380 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 01:49:45.415149
359 01:49:56.584712 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 01:49:56.585212 bl2_stage_init 0x01
361 01:49:56.585510 bl2_stage_init 0x81
362 01:49:56.590128 hw id: 0x0000 - pwm id 0x01
363 01:49:56.590513 bl2_stage_init 0xc1
364 01:49:56.590808 bl2_stage_init 0x02
365 01:49:56.591094
366 01:49:56.595703 L0:00000000
367 01:49:56.596107 L1:20000703
368 01:49:56.596385 L2:00008067
369 01:49:56.596626 L3:14000000
370 01:49:56.601242 B2:00402000
371 01:49:56.601575 B1:e0f83180
372 01:49:56.601831
373 01:49:56.602081 TE: 58124
374 01:49:56.602328
375 01:49:56.606827 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 01:49:56.607142
377 01:49:56.607391 Board ID = 1
378 01:49:56.612466 Set A53 clk to 24M
379 01:49:56.612787 Set A73 clk to 24M
380 01:49:56.613035 Set clk81 to 24M
381 01:49:56.618069 A53 clk: 1200 MHz
382 01:49:56.618384 A73 clk: 1200 MHz
383 01:49:56.618629 CLK81: 166.6M
384 01:49:56.618861 smccc: 00012a92
385 01:49:56.623687 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 01:49:56.629170 board id: 1
387 01:49:56.635192 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 01:49:56.645921 fw parse done
389 01:49:56.651785 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 01:49:56.694410 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 01:49:56.705356 PIEI prepare done
392 01:49:56.705765 fastboot data load
393 01:49:56.706022 fastboot data verify
394 01:49:56.711734 verify result: 266
395 01:49:56.716655 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 01:49:56.717108 LPDDR4 probe
397 01:49:56.717370 ddr clk to 1584MHz
398 01:49:56.724601 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 01:49:56.761830
400 01:49:56.762267 dmc_version 0001
401 01:49:56.768415 Check phy result
402 01:49:56.774212 INFO : End of CA training
403 01:49:56.774533 INFO : End of initialization
404 01:49:56.779837 INFO : Training has run successfully!
405 01:49:56.780388 Check phy result
406 01:49:56.785516 INFO : End of initialization
407 01:49:56.786004 INFO : End of read enable training
408 01:49:56.788885 INFO : End of fine write leveling
409 01:49:56.794483 INFO : End of Write leveling coarse delay
410 01:49:56.800197 INFO : Training has run successfully!
411 01:49:56.800682 Check phy result
412 01:49:56.801125 INFO : End of initialization
413 01:49:56.805717 INFO : End of read dq deskew training
414 01:49:56.811341 INFO : End of MPR read delay center optimization
415 01:49:56.811821 INFO : End of write delay center optimization
416 01:49:56.816889 INFO : End of read delay center optimization
417 01:49:56.822519 INFO : End of max read latency training
418 01:49:56.823006 INFO : Training has run successfully!
419 01:49:56.828159 1D training succeed
420 01:49:56.833952 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 01:49:56.881065 Check phy result
422 01:49:56.881595 INFO : End of initialization
423 01:49:56.903068 INFO : End of 2D read delay Voltage center optimization
424 01:49:56.923249 INFO : End of 2D read delay Voltage center optimization
425 01:49:56.975090 INFO : End of 2D write delay Voltage center optimization
426 01:49:57.024537 INFO : End of 2D write delay Voltage center optimization
427 01:49:57.030081 INFO : Training has run successfully!
428 01:49:57.030625
429 01:49:57.031071 channel==0
430 01:49:57.035645 RxClkDly_Margin_A0==88 ps 9
431 01:49:57.036215 TxDqDly_Margin_A0==98 ps 10
432 01:49:57.038973 RxClkDly_Margin_A1==88 ps 9
433 01:49:57.039475 TxDqDly_Margin_A1==98 ps 10
434 01:49:57.044397 TrainedVREFDQ_A0==74
435 01:49:57.044910 TrainedVREFDQ_A1==74
436 01:49:57.050074 VrefDac_Margin_A0==25
437 01:49:57.050583 DeviceVref_Margin_A0==40
438 01:49:57.051009 VrefDac_Margin_A1==25
439 01:49:57.055586 DeviceVref_Margin_A1==40
440 01:49:57.056118
441 01:49:57.056545
442 01:49:57.056956 channel==1
443 01:49:57.057358 RxClkDly_Margin_A0==88 ps 9
444 01:49:57.059247 TxDqDly_Margin_A0==88 ps 9
445 01:49:57.064726 RxClkDly_Margin_A1==88 ps 9
446 01:49:57.065254 TxDqDly_Margin_A1==88 ps 9
447 01:49:57.065686 TrainedVREFDQ_A0==76
448 01:49:57.070351 TrainedVREFDQ_A1==77
449 01:49:57.070871 VrefDac_Margin_A0==22
450 01:49:57.076000 DeviceVref_Margin_A0==38
451 01:49:57.076536 VrefDac_Margin_A1==24
452 01:49:57.076956 DeviceVref_Margin_A1==37
453 01:49:57.077358
454 01:49:57.081639 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 01:49:57.082185
456 01:49:57.115277 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 01:49:57.115906 2D training succeed
458 01:49:57.120823 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 01:49:57.126396 auto size-- 65535DDR cs0 size: 2048MB
460 01:49:57.126900 DDR cs1 size: 2048MB
461 01:49:57.131836 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 01:49:57.132382 cs0 DataBus test pass
463 01:49:57.132805 cs1 DataBus test pass
464 01:49:57.137457 cs0 AddrBus test pass
465 01:49:57.137969 cs1 AddrBus test pass
466 01:49:57.138392
467 01:49:57.143184 100bdlr_step_size ps== 420
468 01:49:57.143701 result report
469 01:49:57.144175 boot times 0Enable ddr reg access
470 01:49:57.152655 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 01:49:57.166244 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 01:49:57.738037 0.0;M3 CHK:0;cm4_sp_mode 0
473 01:49:57.738654 MVN_1=0x00000000
474 01:49:57.743598 MVN_2=0x00000000
475 01:49:57.749351 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 01:49:57.749838 OPS=0x10
477 01:49:57.750267 ring efuse init
478 01:49:57.750681 chipver efuse init
479 01:49:57.754976 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 01:49:57.760590 [0.018961 Inits done]
481 01:49:57.761060 secure task start!
482 01:49:57.761477 high task start!
483 01:49:57.764814 low task start!
484 01:49:57.765280 run into bl31
485 01:49:57.771839 NOTICE: BL31: v1.3(release):4fc40b1
486 01:49:57.779594 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 01:49:57.780100 NOTICE: BL31: G12A normal boot!
488 01:49:57.804925 NOTICE: BL31: BL33 decompress pass
489 01:49:57.809695 ERROR: Error initializing runtime service opteed_fast
490 01:49:59.043568
491 01:49:59.044089
492 01:49:59.051916 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 01:49:59.052350
494 01:49:59.052582 Model: Libre Computer AML-A311D-CC Alta
495 01:49:59.260285 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 01:49:59.283713 DRAM: 2 GiB (effective 3.8 GiB)
497 01:49:59.426696 Core: 408 devices, 31 uclasses, devicetree: separate
498 01:49:59.432528 WDT: Not starting watchdog@f0d0
499 01:49:59.464791 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 01:49:59.477324 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 01:49:59.482205 ** Bad device specification mmc 0 **
502 01:49:59.492544 Card did not respond to voltage select! : -110
503 01:49:59.500220 ** Bad device specification mmc 0 **
504 01:49:59.500568 Couldn't find partition mmc 0
505 01:49:59.508540 Card did not respond to voltage select! : -110
506 01:49:59.514086 ** Bad device specification mmc 0 **
507 01:49:59.514561 Couldn't find partition mmc 0
508 01:49:59.519136 Error: could not access storage.
509 01:50:00.785175 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 01:50:00.785652 bl2_stage_init 0x01
511 01:50:00.785944 bl2_stage_init 0x81
512 01:50:00.790669 hw id: 0x0000 - pwm id 0x01
513 01:50:00.791082 bl2_stage_init 0xc1
514 01:50:00.791337 bl2_stage_init 0x02
515 01:50:00.791826
516 01:50:00.796296 L0:00000000
517 01:50:00.796947 L1:20000703
518 01:50:00.797431 L2:00008067
519 01:50:00.797894 L3:14000000
520 01:50:00.801956 B2:00402000
521 01:50:00.802553 B1:e0f83180
522 01:50:00.803018
523 01:50:00.803439 TE: 58124
524 01:50:00.803847
525 01:50:00.807666 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 01:50:00.808026
527 01:50:00.808270 Board ID = 1
528 01:50:00.813179 Set A53 clk to 24M
529 01:50:00.813752 Set A73 clk to 24M
530 01:50:00.814232 Set clk81 to 24M
531 01:50:00.818760 A53 clk: 1200 MHz
532 01:50:00.819326 A73 clk: 1200 MHz
533 01:50:00.819797 CLK81: 166.6M
534 01:50:00.820299 smccc: 00012a92
535 01:50:00.824403 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 01:50:00.829950 board id: 1
537 01:50:00.835885 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 01:50:00.846527 fw parse done
539 01:50:00.852464 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 01:50:00.895067 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 01:50:00.906004 PIEI prepare done
542 01:50:00.906597 fastboot data load
543 01:50:00.907075 fastboot data verify
544 01:50:00.911833 verify result: 266
545 01:50:00.917257 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 01:50:00.917827 LPDDR4 probe
547 01:50:00.918291 ddr clk to 1584MHz
548 01:50:00.925361 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 01:50:00.962666
550 01:50:00.963112 dmc_version 0001
551 01:50:00.969283 Check phy result
552 01:50:00.975028 INFO : End of CA training
553 01:50:00.975430 INFO : End of initialization
554 01:50:00.980685 INFO : Training has run successfully!
555 01:50:00.981276 Check phy result
556 01:50:00.986216 INFO : End of initialization
557 01:50:00.986783 INFO : End of read enable training
558 01:50:00.989551 INFO : End of fine write leveling
559 01:50:00.995079 INFO : End of Write leveling coarse delay
560 01:50:01.000778 INFO : Training has run successfully!
561 01:50:01.001354 Check phy result
562 01:50:01.001829 INFO : End of initialization
563 01:50:01.006277 INFO : End of read dq deskew training
564 01:50:01.011857 INFO : End of MPR read delay center optimization
565 01:50:01.012463 INFO : End of write delay center optimization
566 01:50:01.017564 INFO : End of read delay center optimization
567 01:50:01.023095 INFO : End of max read latency training
568 01:50:01.023682 INFO : Training has run successfully!
569 01:50:01.028864 1D training succeed
570 01:50:01.034646 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 01:50:01.082231 Check phy result
572 01:50:01.082822 INFO : End of initialization
573 01:50:01.104909 INFO : End of 2D read delay Voltage center optimization
574 01:50:01.125098 INFO : End of 2D read delay Voltage center optimization
575 01:50:01.177011 INFO : End of 2D write delay Voltage center optimization
576 01:50:01.226304 INFO : End of 2D write delay Voltage center optimization
577 01:50:01.231894 INFO : Training has run successfully!
578 01:50:01.232484
579 01:50:01.232786 channel==0
580 01:50:01.237566 RxClkDly_Margin_A0==98 ps 10
581 01:50:01.238099 TxDqDly_Margin_A0==98 ps 10
582 01:50:01.243080 RxClkDly_Margin_A1==88 ps 9
583 01:50:01.243484 TxDqDly_Margin_A1==98 ps 10
584 01:50:01.243738 TrainedVREFDQ_A0==74
585 01:50:01.248741 TrainedVREFDQ_A1==74
586 01:50:01.249159 VrefDac_Margin_A0==25
587 01:50:01.254263 DeviceVref_Margin_A0==40
588 01:50:01.254776 VrefDac_Margin_A1==24
589 01:50:01.255174 DeviceVref_Margin_A1==40
590 01:50:01.255450
591 01:50:01.255691
592 01:50:01.259925 channel==1
593 01:50:01.260630 RxClkDly_Margin_A0==98 ps 10
594 01:50:01.261072 TxDqDly_Margin_A0==98 ps 10
595 01:50:01.265494 RxClkDly_Margin_A1==98 ps 10
596 01:50:01.266083 TxDqDly_Margin_A1==88 ps 9
597 01:50:01.271055 TrainedVREFDQ_A0==77
598 01:50:01.271544 TrainedVREFDQ_A1==77
599 01:50:01.271975 VrefDac_Margin_A0==22
600 01:50:01.276707 DeviceVref_Margin_A0==37
601 01:50:01.277192 VrefDac_Margin_A1==24
602 01:50:01.282370 DeviceVref_Margin_A1==37
603 01:50:01.282853
604 01:50:01.283280 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 01:50:01.287825
606 01:50:01.315918 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 01:50:01.316578 2D training succeed
608 01:50:01.321606 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 01:50:01.327170 auto size-- 65535DDR cs0 size: 2048MB
610 01:50:01.327660 DDR cs1 size: 2048MB
611 01:50:01.332956 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 01:50:01.333446 cs0 DataBus test pass
613 01:50:01.338521 cs1 DataBus test pass
614 01:50:01.339014 cs0 AddrBus test pass
615 01:50:01.339490 cs1 AddrBus test pass
616 01:50:01.339934
617 01:50:01.343926 100bdlr_step_size ps== 420
618 01:50:01.344485 result report
619 01:50:01.349533 boot times 0Enable ddr reg access
620 01:50:01.355013 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 01:50:01.368935 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 01:50:01.942296 0.0;M3 CHK:0;cm4_sp_mode 0
623 01:50:01.942983 MVN_1=0x00000000
624 01:50:01.947811 MVN_2=0x00000000
625 01:50:01.956208 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 01:50:01.956638 OPS=0x10
627 01:50:01.956850 ring efuse init
628 01:50:01.957053 chipver efuse init
629 01:50:01.961951 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 01:50:01.962347 [0.018961 Inits done]
631 01:50:01.962615 secure task start!
632 01:50:01.969498 high task start!
633 01:50:01.969912 low task start!
634 01:50:01.970141 run into bl31
635 01:50:01.976402 NOTICE: BL31: v1.3(release):4fc40b1
636 01:50:01.983638 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 01:50:01.983931 NOTICE: BL31: G12A normal boot!
638 01:50:02.009144 NOTICE: BL31: BL33 decompress pass
639 01:50:02.014840 ERROR: Error initializing runtime service opteed_fast
640 01:50:03.247599
641 01:50:03.248294
642 01:50:03.256087 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 01:50:03.256621
644 01:50:03.257090 Model: Libre Computer AML-A311D-CC Alta
645 01:50:03.464437 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 01:50:03.487818 DRAM: 2 GiB (effective 3.8 GiB)
647 01:50:03.630911 Core: 408 devices, 31 uclasses, devicetree: separate
648 01:50:03.636621 WDT: Not starting watchdog@f0d0
649 01:50:03.668876 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 01:50:03.681357 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 01:50:03.686308 ** Bad device specification mmc 0 **
652 01:50:03.696625 Card did not respond to voltage select! : -110
653 01:50:03.704294 ** Bad device specification mmc 0 **
654 01:50:03.704833 Couldn't find partition mmc 0
655 01:50:03.712636 Card did not respond to voltage select! : -110
656 01:50:03.718230 ** Bad device specification mmc 0 **
657 01:50:03.718774 Couldn't find partition mmc 0
658 01:50:03.723213 Error: could not access storage.
659 01:50:04.066718 Net: eth0: ethernet@ff3f0000
660 01:50:04.067314 starting USB...
661 01:50:04.318565 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 01:50:04.319213 Starting the controller
663 01:50:04.325489 USB XHCI 1.10
664 01:50:06.033772 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 01:50:06.034464 bl2_stage_init 0x01
666 01:50:06.034949 bl2_stage_init 0x81
667 01:50:06.039317 hw id: 0x0000 - pwm id 0x01
668 01:50:06.039829 bl2_stage_init 0xc1
669 01:50:06.040356 bl2_stage_init 0x02
670 01:50:06.040813
671 01:50:06.044864 L0:00000000
672 01:50:06.045358 L1:20000703
673 01:50:06.045812 L2:00008067
674 01:50:06.046253 L3:14000000
675 01:50:06.050520 B2:00402000
676 01:50:06.051018 B1:e0f83180
677 01:50:06.051467
678 01:50:06.051916 TE: 58124
679 01:50:06.052407
680 01:50:06.056063 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 01:50:06.056567
682 01:50:06.057020 Board ID = 1
683 01:50:06.061668 Set A53 clk to 24M
684 01:50:06.062164 Set A73 clk to 24M
685 01:50:06.062611 Set clk81 to 24M
686 01:50:06.067287 A53 clk: 1200 MHz
687 01:50:06.067780 A73 clk: 1200 MHz
688 01:50:06.068272 CLK81: 166.6M
689 01:50:06.068723 smccc: 00012a92
690 01:50:06.072851 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 01:50:06.078459 board id: 1
692 01:50:06.084418 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 01:50:06.095052 fw parse done
694 01:50:06.100952 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 01:50:06.143581 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 01:50:06.154483 PIEI prepare done
697 01:50:06.154967 fastboot data load
698 01:50:06.155421 fastboot data verify
699 01:50:06.160329 verify result: 266
700 01:50:06.165811 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 01:50:06.166317 LPDDR4 probe
702 01:50:06.166766 ddr clk to 1584MHz
703 01:50:06.173777 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 01:50:06.211102
705 01:50:06.211646 dmc_version 0001
706 01:50:06.217729 Check phy result
707 01:50:06.223618 INFO : End of CA training
708 01:50:06.224146 INFO : End of initialization
709 01:50:06.229206 INFO : Training has run successfully!
710 01:50:06.229708 Check phy result
711 01:50:06.234797 INFO : End of initialization
712 01:50:06.235296 INFO : End of read enable training
713 01:50:06.240440 INFO : End of fine write leveling
714 01:50:06.246006 INFO : End of Write leveling coarse delay
715 01:50:06.246510 INFO : Training has run successfully!
716 01:50:06.246961 Check phy result
717 01:50:06.251590 INFO : End of initialization
718 01:50:06.252127 INFO : End of read dq deskew training
719 01:50:06.257187 INFO : End of MPR read delay center optimization
720 01:50:06.262798 INFO : End of write delay center optimization
721 01:50:06.268459 INFO : End of read delay center optimization
722 01:50:06.268966 INFO : End of max read latency training
723 01:50:06.273975 INFO : Training has run successfully!
724 01:50:06.274475 1D training succeed
725 01:50:06.283275 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 01:50:06.330780 Check phy result
727 01:50:06.331299 INFO : End of initialization
728 01:50:06.352563 INFO : End of 2D read delay Voltage center optimization
729 01:50:06.372736 INFO : End of 2D read delay Voltage center optimization
730 01:50:06.424892 INFO : End of 2D write delay Voltage center optimization
731 01:50:06.474209 INFO : End of 2D write delay Voltage center optimization
732 01:50:06.479760 INFO : Training has run successfully!
733 01:50:06.480318
734 01:50:06.480782 channel==0
735 01:50:06.485370 RxClkDly_Margin_A0==88 ps 9
736 01:50:06.485915 TxDqDly_Margin_A0==98 ps 10
737 01:50:06.490951 RxClkDly_Margin_A1==88 ps 9
738 01:50:06.491464 TxDqDly_Margin_A1==98 ps 10
739 01:50:06.491921 TrainedVREFDQ_A0==74
740 01:50:06.496541 TrainedVREFDQ_A1==74
741 01:50:06.497051 VrefDac_Margin_A0==24
742 01:50:06.498413 DeviceVref_Margin_A0==40
743 01:50:06.502097 VrefDac_Margin_A1==25
744 01:50:06.502406 DeviceVref_Margin_A1==40
745 01:50:06.502637
746 01:50:06.502852
747 01:50:06.507649 channel==1
748 01:50:06.507970 RxClkDly_Margin_A0==98 ps 10
749 01:50:06.508241 TxDqDly_Margin_A0==88 ps 9
750 01:50:06.513417 RxClkDly_Margin_A1==88 ps 9
751 01:50:06.513724 TxDqDly_Margin_A1==88 ps 9
752 01:50:06.518883 TrainedVREFDQ_A0==76
753 01:50:06.519350 TrainedVREFDQ_A1==77
754 01:50:06.519710 VrefDac_Margin_A0==22
755 01:50:06.524466 DeviceVref_Margin_A0==38
756 01:50:06.524808 VrefDac_Margin_A1==24
757 01:50:06.530077 DeviceVref_Margin_A1==37
758 01:50:06.530572
759 01:50:06.530832 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 01:50:06.531053
761 01:50:06.563700 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 01:50:06.564319 2D training succeed
763 01:50:06.569430 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 01:50:06.574836 auto size-- 65535DDR cs0 size: 2048MB
765 01:50:06.575176 DDR cs1 size: 2048MB
766 01:50:06.580404 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 01:50:06.580670 cs0 DataBus test pass
768 01:50:06.586059 cs1 DataBus test pass
769 01:50:06.586377 cs0 AddrBus test pass
770 01:50:06.586597 cs1 AddrBus test pass
771 01:50:06.586810
772 01:50:06.591626 100bdlr_step_size ps== 420
773 01:50:06.591891 result report
774 01:50:06.597179 boot times 0Enable ddr reg access
775 01:50:06.602496 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 01:50:06.616058 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 01:50:07.189909 0.0;M3 CHK:0;cm4_sp_mode 0
778 01:50:07.190576 MVN_1=0x00000000
779 01:50:07.195388 MVN_2=0x00000000
780 01:50:07.201023 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 01:50:07.201577 OPS=0x10
782 01:50:07.202024 ring efuse init
783 01:50:07.202460 chipver efuse init
784 01:50:07.206569 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 01:50:07.212182 [0.018961 Inits done]
786 01:50:07.212651 secure task start!
787 01:50:07.213085 high task start!
788 01:50:07.216749 low task start!
789 01:50:07.217216 run into bl31
790 01:50:07.223479 NOTICE: BL31: v1.3(release):4fc40b1
791 01:50:07.231378 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 01:50:07.231853 NOTICE: BL31: G12A normal boot!
793 01:50:07.256715 NOTICE: BL31: BL33 decompress pass
794 01:50:07.262436 ERROR: Error initializing runtime service opteed_fast
795 01:50:08.495420
796 01:50:08.496137
797 01:50:08.503922 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 01:50:08.504545
799 01:50:08.505025 Model: Libre Computer AML-A311D-CC Alta
800 01:50:08.712155 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 01:50:08.735520 DRAM: 2 GiB (effective 3.8 GiB)
802 01:50:08.878550 Core: 408 devices, 31 uclasses, devicetree: separate
803 01:50:08.884447 WDT: Not starting watchdog@f0d0
804 01:50:08.916687 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 01:50:08.929061 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 01:50:08.934075 ** Bad device specification mmc 0 **
807 01:50:08.944469 Card did not respond to voltage select! : -110
808 01:50:08.952115 ** Bad device specification mmc 0 **
809 01:50:08.952667 Couldn't find partition mmc 0
810 01:50:08.960446 Card did not respond to voltage select! : -110
811 01:50:08.965940 ** Bad device specification mmc 0 **
812 01:50:08.966480 Couldn't find partition mmc 0
813 01:50:08.971067 Error: could not access storage.
814 01:50:09.313581 Net: eth0: ethernet@ff3f0000
815 01:50:09.314226 starting USB...
816 01:50:09.565257 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 01:50:09.565876 Starting the controller
818 01:50:09.572427 USB XHCI 1.10
819 01:50:11.734321 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 01:50:11.734979 bl2_stage_init 0x01
821 01:50:11.735461 bl2_stage_init 0x81
822 01:50:11.739699 hw id: 0x0000 - pwm id 0x01
823 01:50:11.740347 bl2_stage_init 0xc1
824 01:50:11.740882 bl2_stage_init 0x02
825 01:50:11.741386
826 01:50:11.745307 L0:00000000
827 01:50:11.745865 L1:20000703
828 01:50:11.746330 L2:00008067
829 01:50:11.746787 L3:14000000
830 01:50:11.750985 B2:00402000
831 01:50:11.751543 B1:e0f83180
832 01:50:11.752043
833 01:50:11.752504 TE: 58124
834 01:50:11.752961
835 01:50:11.756509 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 01:50:11.757049
837 01:50:11.757512 Board ID = 1
838 01:50:11.762161 Set A53 clk to 24M
839 01:50:11.762710 Set A73 clk to 24M
840 01:50:11.763168 Set clk81 to 24M
841 01:50:11.767643 A53 clk: 1200 MHz
842 01:50:11.768219 A73 clk: 1200 MHz
843 01:50:11.768688 CLK81: 166.6M
844 01:50:11.769137 smccc: 00012a91
845 01:50:11.773343 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 01:50:11.779877 board id: 1
847 01:50:11.784977 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 01:50:11.795311 fw parse done
849 01:50:11.801241 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 01:50:11.843901 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 01:50:11.854837 PIEI prepare done
852 01:50:11.855430 fastboot data load
853 01:50:11.855899 fastboot data verify
854 01:50:11.860560 verify result: 266
855 01:50:11.866146 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 01:50:11.866710 LPDDR4 probe
857 01:50:11.867173 ddr clk to 1584MHz
858 01:50:11.874183 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 01:50:11.910474
860 01:50:11.911058 dmc_version 0001
861 01:50:11.918135 Check phy result
862 01:50:11.923969 INFO : End of CA training
863 01:50:11.924560 INFO : End of initialization
864 01:50:11.929543 INFO : Training has run successfully!
865 01:50:11.930103 Check phy result
866 01:50:11.935127 INFO : End of initialization
867 01:50:11.935672 INFO : End of read enable training
868 01:50:11.940765 INFO : End of fine write leveling
869 01:50:11.946382 INFO : End of Write leveling coarse delay
870 01:50:11.946938 INFO : Training has run successfully!
871 01:50:11.947399 Check phy result
872 01:50:11.951944 INFO : End of initialization
873 01:50:11.952544 INFO : End of read dq deskew training
874 01:50:11.957591 INFO : End of MPR read delay center optimization
875 01:50:11.963122 INFO : End of write delay center optimization
876 01:50:11.968763 INFO : End of read delay center optimization
877 01:50:11.969313 INFO : End of max read latency training
878 01:50:11.974435 INFO : Training has run successfully!
879 01:50:11.974992 1D training succeed
880 01:50:11.983562 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 01:50:12.031060 Check phy result
882 01:50:12.031645 INFO : End of initialization
883 01:50:12.052359 INFO : End of 2D read delay Voltage center optimization
884 01:50:12.073144 INFO : End of 2D read delay Voltage center optimization
885 01:50:12.125228 INFO : End of 2D write delay Voltage center optimization
886 01:50:12.174586 INFO : End of 2D write delay Voltage center optimization
887 01:50:12.180206 INFO : Training has run successfully!
888 01:50:12.180731
889 01:50:12.181195 channel==0
890 01:50:12.185692 RxClkDly_Margin_A0==88 ps 9
891 01:50:12.186216 TxDqDly_Margin_A0==98 ps 10
892 01:50:12.191395 RxClkDly_Margin_A1==88 ps 9
893 01:50:12.191917 TxDqDly_Margin_A1==98 ps 10
894 01:50:12.192641 TrainedVREFDQ_A0==74
895 01:50:12.197021 TrainedVREFDQ_A1==74
896 01:50:12.197516 VrefDac_Margin_A0==25
897 01:50:12.197958 DeviceVref_Margin_A0==40
898 01:50:12.202593 VrefDac_Margin_A1==25
899 01:50:12.203073 DeviceVref_Margin_A1==40
900 01:50:12.203509
901 01:50:12.203941
902 01:50:12.208090 channel==1
903 01:50:12.208638 RxClkDly_Margin_A0==88 ps 9
904 01:50:12.209092 TxDqDly_Margin_A0==98 ps 10
905 01:50:12.213591 RxClkDly_Margin_A1==88 ps 9
906 01:50:12.214074 TxDqDly_Margin_A1==88 ps 9
907 01:50:12.219258 TrainedVREFDQ_A0==77
908 01:50:12.219759 TrainedVREFDQ_A1==77
909 01:50:12.220284 VrefDac_Margin_A0==22
910 01:50:12.224787 DeviceVref_Margin_A0==37
911 01:50:12.225270 VrefDac_Margin_A1==24
912 01:50:12.230423 DeviceVref_Margin_A1==37
913 01:50:12.230897
914 01:50:12.231332 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 01:50:12.231760
916 01:50:12.264026 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
917 01:50:12.264569 2D training succeed
918 01:50:12.269608 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 01:50:12.275253 auto size-- 65535DDR cs0 size: 2048MB
920 01:50:12.275736 DDR cs1 size: 2048MB
921 01:50:12.280775 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 01:50:12.281260 cs0 DataBus test pass
923 01:50:12.286393 cs1 DataBus test pass
924 01:50:12.286864 cs0 AddrBus test pass
925 01:50:12.287295 cs1 AddrBus test pass
926 01:50:12.287718
927 01:50:12.292052 100bdlr_step_size ps== 420
928 01:50:12.292551 result report
929 01:50:12.297617 boot times 0Enable ddr reg access
930 01:50:12.302412 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 01:50:12.316298 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 01:50:12.889916 0.0;M3 CHK:0;cm4_sp_mode 0
933 01:50:12.890589 MVN_1=0x00000000
934 01:50:12.895399 MVN_2=0x00000000
935 01:50:12.901233 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 01:50:12.901752 OPS=0x10
937 01:50:12.902213 ring efuse init
938 01:50:12.902662 chipver efuse init
939 01:50:12.906724 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 01:50:12.912355 [0.018961 Inits done]
941 01:50:12.912916 secure task start!
942 01:50:12.913386 high task start!
943 01:50:12.916926 low task start!
944 01:50:12.917432 run into bl31
945 01:50:12.923628 NOTICE: BL31: v1.3(release):4fc40b1
946 01:50:12.931422 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 01:50:12.931938 NOTICE: BL31: G12A normal boot!
948 01:50:12.956743 NOTICE: BL31: BL33 decompress pass
949 01:50:12.961625 ERROR: Error initializing runtime service opteed_fast
950 01:50:14.195528
951 01:50:14.196298
952 01:50:14.203745 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 01:50:14.204316
954 01:50:14.204825 Model: Libre Computer AML-A311D-CC Alta
955 01:50:14.412409 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 01:50:14.435491 DRAM: 2 GiB (effective 3.8 GiB)
957 01:50:14.578659 Core: 408 devices, 31 uclasses, devicetree: separate
958 01:50:14.584370 WDT: Not starting watchdog@f0d0
959 01:50:14.616654 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 01:50:14.629228 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 01:50:14.634100 ** Bad device specification mmc 0 **
962 01:50:14.644457 Card did not respond to voltage select! : -110
963 01:50:14.652130 ** Bad device specification mmc 0 **
964 01:50:14.652644 Couldn't find partition mmc 0
965 01:50:14.660479 Card did not respond to voltage select! : -110
966 01:50:14.665976 ** Bad device specification mmc 0 **
967 01:50:14.666478 Couldn't find partition mmc 0
968 01:50:14.670994 Error: could not access storage.
969 01:50:15.013620 Net: eth0: ethernet@ff3f0000
970 01:50:15.014265 starting USB...
971 01:50:15.265371 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 01:50:15.265990 Starting the controller
973 01:50:15.272307 USB XHCI 1.10
974 01:50:17.133681 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 01:50:17.134330 bl2_stage_init 0x01
976 01:50:17.134806 bl2_stage_init 0x81
977 01:50:17.139316 hw id: 0x0000 - pwm id 0x01
978 01:50:17.139852 bl2_stage_init 0xc1
979 01:50:17.140373 bl2_stage_init 0x02
980 01:50:17.140826
981 01:50:17.144916 L0:00000000
982 01:50:17.145439 L1:20000703
983 01:50:17.145898 L2:00008067
984 01:50:17.146340 L3:14000000
985 01:50:17.147848 B2:00402000
986 01:50:17.148395 B1:e0f83180
987 01:50:17.148853
988 01:50:17.149305 TE: 58124
989 01:50:17.149748
990 01:50:17.159030 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 01:50:17.159581
992 01:50:17.160075 Board ID = 1
993 01:50:17.160525 Set A53 clk to 24M
994 01:50:17.160965 Set A73 clk to 24M
995 01:50:17.164694 Set clk81 to 24M
996 01:50:17.165231 A53 clk: 1200 MHz
997 01:50:17.165690 A73 clk: 1200 MHz
998 01:50:17.170304 CLK81: 166.6M
999 01:50:17.170852 smccc: 00012a92
1000 01:50:17.175915 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 01:50:17.176510 board id: 1
1002 01:50:17.184436 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 01:50:17.195075 fw parse done
1004 01:50:17.201106 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 01:50:17.243837 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 01:50:17.254542 PIEI prepare done
1007 01:50:17.255118 fastboot data load
1008 01:50:17.255561 fastboot data verify
1009 01:50:17.260295 verify result: 266
1010 01:50:17.265836 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 01:50:17.266378 LPDDR4 probe
1012 01:50:17.266815 ddr clk to 1584MHz
1013 01:50:17.273793 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 01:50:17.311300
1015 01:50:17.311856 dmc_version 0001
1016 01:50:17.317945 Check phy result
1017 01:50:17.323706 INFO : End of CA training
1018 01:50:17.324248 INFO : End of initialization
1019 01:50:17.329342 INFO : Training has run successfully!
1020 01:50:17.329846 Check phy result
1021 01:50:17.335018 INFO : End of initialization
1022 01:50:17.335566 INFO : End of read enable training
1023 01:50:17.338339 INFO : End of fine write leveling
1024 01:50:17.343867 INFO : End of Write leveling coarse delay
1025 01:50:17.349463 INFO : Training has run successfully!
1026 01:50:17.349980 Check phy result
1027 01:50:17.350433 INFO : End of initialization
1028 01:50:17.355186 INFO : End of read dq deskew training
1029 01:50:17.360687 INFO : End of MPR read delay center optimization
1030 01:50:17.361208 INFO : End of write delay center optimization
1031 01:50:17.366489 INFO : End of read delay center optimization
1032 01:50:17.376143 INFO : End of max read latency training
1033 01:50:17.376825 INFO : Training has run successfully!
1034 01:50:17.377765 1D training succeed
1035 01:50:17.383492 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 01:50:17.430827 Check phy result
1037 01:50:17.431459 INFO : End of initialization
1038 01:50:17.452689 INFO : End of 2D read delay Voltage center optimization
1039 01:50:17.472817 INFO : End of 2D read delay Voltage center optimization
1040 01:50:17.524925 INFO : End of 2D write delay Voltage center optimization
1041 01:50:17.574273 INFO : End of 2D write delay Voltage center optimization
1042 01:50:17.579799 INFO : Training has run successfully!
1043 01:50:17.580478
1044 01:50:17.580863 channel==0
1045 01:50:17.585449 RxClkDly_Margin_A0==88 ps 9
1046 01:50:17.586046 TxDqDly_Margin_A0==98 ps 10
1047 01:50:17.591209 RxClkDly_Margin_A1==88 ps 9
1048 01:50:17.591654 TxDqDly_Margin_A1==98 ps 10
1049 01:50:17.591913 TrainedVREFDQ_A0==74
1050 01:50:17.596559 TrainedVREFDQ_A1==74
1051 01:50:17.597000 VrefDac_Margin_A0==25
1052 01:50:17.597318 DeviceVref_Margin_A0==40
1053 01:50:17.602278 VrefDac_Margin_A1==25
1054 01:50:17.602886 DeviceVref_Margin_A1==40
1055 01:50:17.603316
1056 01:50:17.603815
1057 01:50:17.607951 channel==1
1058 01:50:17.608418 RxClkDly_Margin_A0==98 ps 10
1059 01:50:17.608676 TxDqDly_Margin_A0==98 ps 10
1060 01:50:17.613387 RxClkDly_Margin_A1==88 ps 9
1061 01:50:17.613994 TxDqDly_Margin_A1==88 ps 9
1062 01:50:17.619148 TrainedVREFDQ_A0==77
1063 01:50:17.619822 TrainedVREFDQ_A1==77
1064 01:50:17.620219 VrefDac_Margin_A0==22
1065 01:50:17.624616 DeviceVref_Margin_A0==37
1066 01:50:17.625215 VrefDac_Margin_A1==24
1067 01:50:17.630318 DeviceVref_Margin_A1==37
1068 01:50:17.630928
1069 01:50:17.631245 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 01:50:17.631493
1071 01:50:17.663603 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1072 01:50:17.664046 2D training succeed
1073 01:50:17.669253 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 01:50:17.674969 auto size-- 65535DDR cs0 size: 2048MB
1075 01:50:17.675274 DDR cs1 size: 2048MB
1076 01:50:17.680432 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 01:50:17.680732 cs0 DataBus test pass
1078 01:50:17.686024 cs1 DataBus test pass
1079 01:50:17.686319 cs0 AddrBus test pass
1080 01:50:17.686531 cs1 AddrBus test pass
1081 01:50:17.686738
1082 01:50:17.691673 100bdlr_step_size ps== 420
1083 01:50:17.692006 result report
1084 01:50:17.697239 boot times 0Enable ddr reg access
1085 01:50:17.702676 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 01:50:17.716258 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 01:50:18.290004 0.0;M3 CHK:0;cm4_sp_mode 0
1088 01:50:18.290666 MVN_1=0x00000000
1089 01:50:18.295537 MVN_2=0x00000000
1090 01:50:18.301311 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 01:50:18.301881 OPS=0x10
1092 01:50:18.302360 ring efuse init
1093 01:50:18.302822 chipver efuse init
1094 01:50:18.309475 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 01:50:18.310078 [0.018961 Inits done]
1096 01:50:18.317141 secure task start!
1097 01:50:18.317688 high task start!
1098 01:50:18.318151 low task start!
1099 01:50:18.318604 run into bl31
1100 01:50:18.323655 NOTICE: BL31: v1.3(release):4fc40b1
1101 01:50:18.331547 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 01:50:18.332149 NOTICE: BL31: G12A normal boot!
1103 01:50:18.356883 NOTICE: BL31: BL33 decompress pass
1104 01:50:18.362572 ERROR: Error initializing runtime service opteed_fast
1105 01:50:19.595504
1106 01:50:19.596220
1107 01:50:19.603872 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 01:50:19.604437
1109 01:50:19.604910 Model: Libre Computer AML-A311D-CC Alta
1110 01:50:19.812359 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 01:50:19.835637 DRAM: 2 GiB (effective 3.8 GiB)
1112 01:50:19.978647 Core: 408 devices, 31 uclasses, devicetree: separate
1113 01:50:19.984516 WDT: Not starting watchdog@f0d0
1114 01:50:20.016709 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 01:50:20.029177 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 01:50:20.034204 ** Bad device specification mmc 0 **
1117 01:50:20.044453 Card did not respond to voltage select! : -110
1118 01:50:20.052201 ** Bad device specification mmc 0 **
1119 01:50:20.052722 Couldn't find partition mmc 0
1120 01:50:20.060391 Card did not respond to voltage select! : -110
1121 01:50:20.065866 ** Bad device specification mmc 0 **
1122 01:50:20.066379 Couldn't find partition mmc 0
1123 01:50:20.071079 Error: could not access storage.
1124 01:50:20.413635 Net: eth0: ethernet@ff3f0000
1125 01:50:20.414277 starting USB...
1126 01:50:20.665266 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 01:50:20.665877 Starting the controller
1128 01:50:20.672445 USB XHCI 1.10
1129 01:50:22.226393 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 01:50:22.234862 scanning usb for storage devices... 0 Storage Device(s) found
1132 01:50:22.286797 Hit any key to stop autoboot: 1
1133 01:50:22.287712 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 01:50:22.288530 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 01:50:22.289069 Setting prompt string to ['=>']
1136 01:50:22.289607 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 01:50:22.302229 0
1138 01:50:22.303234 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 01:50:22.303806 Sending with 10 millisecond of delay
1141 01:50:23.438919 => setenv autoload no
1142 01:50:23.449806 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 01:50:23.455284 setenv autoload no
1144 01:50:23.456107 Sending with 10 millisecond of delay
1146 01:50:25.253584 => setenv initrd_high 0xffffffff
1147 01:50:25.264376 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 01:50:25.265316 setenv initrd_high 0xffffffff
1149 01:50:25.266071 Sending with 10 millisecond of delay
1151 01:50:26.882645 => setenv fdt_high 0xffffffff
1152 01:50:26.893453 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 01:50:26.894349 setenv fdt_high 0xffffffff
1154 01:50:26.895116 Sending with 10 millisecond of delay
1156 01:50:27.187054 => dhcp
1157 01:50:27.197798 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 01:50:27.198671 dhcp
1159 01:50:27.199149 Speed: 1000, full duplex
1160 01:50:27.199607 BOOTP broadcast 1
1161 01:50:27.206663 DHCP client bound to address 192.168.6.27 (8 ms)
1162 01:50:27.207438 Sending with 10 millisecond of delay
1164 01:50:28.884288 => setenv serverip 192.168.6.2
1165 01:50:28.895166 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 01:50:28.896202 setenv serverip 192.168.6.2
1167 01:50:28.896961 Sending with 10 millisecond of delay
1169 01:50:32.620401 => tftpboot 0x01080000 949466/tftp-deploy-ao731dlr/kernel/uImage
1170 01:50:32.631251 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1171 01:50:32.632258 tftpboot 0x01080000 949466/tftp-deploy-ao731dlr/kernel/uImage
1172 01:50:32.632804 Speed: 1000, full duplex
1173 01:50:32.633294 Using ethernet@ff3f0000 device
1174 01:50:32.634680 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 01:50:32.639825 Filename '949466/tftp-deploy-ao731dlr/kernel/uImage'.
1176 01:50:32.643773 Load address: 0x1080000
1177 01:50:35.171455 Loading: *################################################## 36.1 MiB
1178 01:50:35.172296 14.3 MiB/s
1179 01:50:35.172772 done
1180 01:50:35.174806 Bytes transferred = 37878336 (241fa40 hex)
1181 01:50:35.175582 Sending with 10 millisecond of delay
1183 01:50:39.863881 => tftpboot 0x08000000 949466/tftp-deploy-ao731dlr/ramdisk/ramdisk.cpio.gz.uboot
1184 01:50:39.874774 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 01:50:39.875634 tftpboot 0x08000000 949466/tftp-deploy-ao731dlr/ramdisk/ramdisk.cpio.gz.uboot
1186 01:50:39.876151 Speed: 1000, full duplex
1187 01:50:39.876600 Using ethernet@ff3f0000 device
1188 01:50:39.877534 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 01:50:39.886239 Filename '949466/tftp-deploy-ao731dlr/ramdisk/ramdisk.cpio.gz.uboot'.
1190 01:50:39.886734 Load address: 0x8000000
1191 01:50:46.510388 Loading: *##############################T ################### UDP wrong checksum 00000005 00002144
1192 01:50:49.943299 UDP wrong checksum 000000ff 0000ed63
1193 01:50:49.962679 UDP wrong checksum 000000ff 00007656
1194 01:50:51.512326 T UDP wrong checksum 00000005 00002144
1195 01:50:55.990562 UDP wrong checksum 000000ff 00009d8b
1196 01:50:56.031218 UDP wrong checksum 000000ff 0000307e
1197 01:51:01.513256 T T UDP wrong checksum 00000005 00002144
1198 01:51:01.730577 UDP wrong checksum 000000ff 000090fb
1199 01:51:01.771867 UDP wrong checksum 000000ff 00001aee
1200 01:51:21.517537 T T T UDP wrong checksum 00000005 00002144
1201 01:51:36.522426 T T T
1202 01:51:36.522862 Retry count exceeded; starting again
1204 01:51:36.524483 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1207 01:51:36.525537 end: 2.4 uboot-commands (duration 00:01:51) [common]
1209 01:51:36.526322 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1211 01:51:36.526921 end: 2 uboot-action (duration 00:01:51) [common]
1213 01:51:36.527797 Cleaning after the job
1214 01:51:36.528192 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/ramdisk
1215 01:51:36.529033 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/kernel
1216 01:51:36.541720 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/dtb
1217 01:51:36.542552 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/nfsrootfs
1218 01:51:36.610688 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949466/tftp-deploy-ao731dlr/modules
1219 01:51:36.620807 start: 4.1 power-off (timeout 00:00:30) [common]
1220 01:51:36.621456 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1221 01:51:36.654594 >> OK - accepted request
1222 01:51:36.656703 Returned 0 in 0 seconds
1223 01:51:36.757489 end: 4.1 power-off (duration 00:00:00) [common]
1225 01:51:36.758493 start: 4.2 read-feedback (timeout 00:10:00) [common]
1226 01:51:36.759187 Listened to connection for namespace 'common' for up to 1s
1227 01:51:37.760147 Finalising connection for namespace 'common'
1228 01:51:37.760629 Disconnecting from shell: Finalise
1229 01:51:37.760916 =>
1230 01:51:37.861633 end: 4.2 read-feedback (duration 00:00:01) [common]
1231 01:51:37.862089 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949466
1232 01:51:40.870722 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949466
1233 01:51:40.871370 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.