Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:52:04.364152 lava-dispatcher, installed at version: 2024.01
2 01:52:04.364952 start: 0 validate
3 01:52:04.365425 Start time: 2024-11-07 01:52:04.365395+00:00 (UTC)
4 01:52:04.365958 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:52:04.366503 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:52:04.407348 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:52:04.407894 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 01:52:04.436006 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:52:04.436643 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:52:04.465083 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:52:04.465602 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:52:04.494824 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:52:04.495337 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
14 01:52:04.530476 validate duration: 0.17
16 01:52:04.531363 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:52:04.531673 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:52:04.532281 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:52:04.533062 Not decompressing ramdisk as can be used compressed.
20 01:52:04.533679 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 01:52:04.534087 saving as /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/ramdisk/initrd.cpio.gz
22 01:52:04.534470 total size: 5628140 (5 MB)
23 01:52:04.570611 progress 0 % (0 MB)
24 01:52:04.575224 progress 5 % (0 MB)
25 01:52:04.579679 progress 10 % (0 MB)
26 01:52:04.583470 progress 15 % (0 MB)
27 01:52:04.587619 progress 20 % (1 MB)
28 01:52:04.591429 progress 25 % (1 MB)
29 01:52:04.595601 progress 30 % (1 MB)
30 01:52:04.599798 progress 35 % (1 MB)
31 01:52:04.603533 progress 40 % (2 MB)
32 01:52:04.607597 progress 45 % (2 MB)
33 01:52:04.611326 progress 50 % (2 MB)
34 01:52:04.615465 progress 55 % (2 MB)
35 01:52:04.619560 progress 60 % (3 MB)
36 01:52:04.623262 progress 65 % (3 MB)
37 01:52:04.627498 progress 70 % (3 MB)
38 01:52:04.631350 progress 75 % (4 MB)
39 01:52:04.635404 progress 80 % (4 MB)
40 01:52:04.639051 progress 85 % (4 MB)
41 01:52:04.643101 progress 90 % (4 MB)
42 01:52:04.646911 progress 95 % (5 MB)
43 01:52:04.650222 progress 100 % (5 MB)
44 01:52:04.650863 5 MB downloaded in 0.12 s (46.12 MB/s)
45 01:52:04.651402 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:52:04.652318 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:52:04.652611 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:52:04.652882 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:52:04.653337 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/kernel/Image
51 01:52:04.653574 saving as /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/kernel/Image
52 01:52:04.653782 total size: 37878272 (36 MB)
53 01:52:04.653992 No compression specified
54 01:52:04.688204 progress 0 % (0 MB)
55 01:52:04.712682 progress 5 % (1 MB)
56 01:52:04.737538 progress 10 % (3 MB)
57 01:52:04.762399 progress 15 % (5 MB)
58 01:52:04.786210 progress 20 % (7 MB)
59 01:52:04.809918 progress 25 % (9 MB)
60 01:52:04.833832 progress 30 % (10 MB)
61 01:52:04.857612 progress 35 % (12 MB)
62 01:52:04.881402 progress 40 % (14 MB)
63 01:52:04.905548 progress 45 % (16 MB)
64 01:52:04.928924 progress 50 % (18 MB)
65 01:52:04.952625 progress 55 % (19 MB)
66 01:52:04.976562 progress 60 % (21 MB)
67 01:52:05.000426 progress 65 % (23 MB)
68 01:52:05.024513 progress 70 % (25 MB)
69 01:52:05.048005 progress 75 % (27 MB)
70 01:52:05.071932 progress 80 % (28 MB)
71 01:52:05.095877 progress 85 % (30 MB)
72 01:52:05.120077 progress 90 % (32 MB)
73 01:52:05.143901 progress 95 % (34 MB)
74 01:52:05.166966 progress 100 % (36 MB)
75 01:52:05.167757 36 MB downloaded in 0.51 s (70.28 MB/s)
76 01:52:05.168268 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:52:05.169086 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:52:05.169360 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:52:05.169627 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:52:05.170073 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:52:05.170345 saving as /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:52:05.170553 total size: 54703 (0 MB)
84 01:52:05.170762 No compression specified
85 01:52:05.214583 progress 59 % (0 MB)
86 01:52:05.215433 progress 100 % (0 MB)
87 01:52:05.216034 0 MB downloaded in 0.05 s (1.15 MB/s)
88 01:52:05.216544 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:52:05.217360 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:52:05.217626 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:52:05.217891 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:52:05.218332 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 01:52:05.218573 saving as /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/nfsrootfs/full.rootfs.tar
95 01:52:05.218777 total size: 474398908 (452 MB)
96 01:52:05.218988 Using unxz to decompress xz
97 01:52:05.255235 progress 0 % (0 MB)
98 01:52:06.386910 progress 5 % (22 MB)
99 01:52:07.886282 progress 10 % (45 MB)
100 01:52:08.319512 progress 15 % (67 MB)
101 01:52:09.156948 progress 20 % (90 MB)
102 01:52:09.700761 progress 25 % (113 MB)
103 01:52:10.065693 progress 30 % (135 MB)
104 01:52:10.679075 progress 35 % (158 MB)
105 01:52:11.587477 progress 40 % (181 MB)
106 01:52:12.406054 progress 45 % (203 MB)
107 01:52:13.015934 progress 50 % (226 MB)
108 01:52:13.704537 progress 55 % (248 MB)
109 01:52:14.947632 progress 60 % (271 MB)
110 01:52:16.389163 progress 65 % (294 MB)
111 01:52:18.048756 progress 70 % (316 MB)
112 01:52:21.164657 progress 75 % (339 MB)
113 01:52:23.658381 progress 80 % (361 MB)
114 01:52:26.587171 progress 85 % (384 MB)
115 01:52:29.787352 progress 90 % (407 MB)
116 01:52:32.978154 progress 95 % (429 MB)
117 01:52:36.264564 progress 100 % (452 MB)
118 01:52:36.278800 452 MB downloaded in 31.06 s (14.57 MB/s)
119 01:52:36.279755 end: 1.4.1 http-download (duration 00:00:31) [common]
121 01:52:36.281543 end: 1.4 download-retry (duration 00:00:31) [common]
122 01:52:36.282091 start: 1.5 download-retry (timeout 00:09:28) [common]
123 01:52:36.282625 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 01:52:36.284069 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/modules.tar.xz
125 01:52:36.284593 saving as /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/modules/modules.tar
126 01:52:36.285014 total size: 11769360 (11 MB)
127 01:52:36.285440 Using unxz to decompress xz
128 01:52:36.326824 progress 0 % (0 MB)
129 01:52:36.410659 progress 5 % (0 MB)
130 01:52:36.496542 progress 10 % (1 MB)
131 01:52:36.596682 progress 15 % (1 MB)
132 01:52:36.693982 progress 20 % (2 MB)
133 01:52:36.774398 progress 25 % (2 MB)
134 01:52:36.853339 progress 30 % (3 MB)
135 01:52:36.935490 progress 35 % (3 MB)
136 01:52:37.016039 progress 40 % (4 MB)
137 01:52:37.094992 progress 45 % (5 MB)
138 01:52:37.182204 progress 50 % (5 MB)
139 01:52:37.266668 progress 55 % (6 MB)
140 01:52:37.354760 progress 60 % (6 MB)
141 01:52:37.437834 progress 65 % (7 MB)
142 01:52:37.521418 progress 70 % (7 MB)
143 01:52:37.605846 progress 75 % (8 MB)
144 01:52:37.690908 progress 80 % (9 MB)
145 01:52:37.773064 progress 85 % (9 MB)
146 01:52:37.858206 progress 90 % (10 MB)
147 01:52:37.939344 progress 95 % (10 MB)
148 01:52:38.020220 progress 100 % (11 MB)
149 01:52:38.032377 11 MB downloaded in 1.75 s (6.42 MB/s)
150 01:52:38.033029 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:52:38.033959 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:52:38.034252 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 01:52:38.034535 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 01:52:54.008462 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/949480/extract-nfsrootfs-mu8r7l2x
156 01:52:54.009061 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 01:52:54.009345 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 01:52:54.010039 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr
159 01:52:54.010505 makedir: /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin
160 01:52:54.010853 makedir: /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/tests
161 01:52:54.011176 makedir: /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/results
162 01:52:54.011504 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-add-keys
163 01:52:54.012052 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-add-sources
164 01:52:54.012607 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-background-process-start
165 01:52:54.013113 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-background-process-stop
166 01:52:54.013649 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-common-functions
167 01:52:54.014151 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-echo-ipv4
168 01:52:54.014695 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-install-packages
169 01:52:54.015188 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-installed-packages
170 01:52:54.015678 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-os-build
171 01:52:54.016198 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-probe-channel
172 01:52:54.016700 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-probe-ip
173 01:52:54.017189 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-target-ip
174 01:52:54.017670 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-target-mac
175 01:52:54.018162 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-target-storage
176 01:52:54.018659 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-test-case
177 01:52:54.019152 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-test-event
178 01:52:54.019654 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-test-feedback
179 01:52:54.020190 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-test-raise
180 01:52:54.020776 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-test-reference
181 01:52:54.021279 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-test-runner
182 01:52:54.021780 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-test-set
183 01:52:54.022265 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-test-shell
184 01:52:54.022760 Updating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-install-packages (oe)
185 01:52:54.023309 Updating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/bin/lava-installed-packages (oe)
186 01:52:54.023813 Creating /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/environment
187 01:52:54.024236 LAVA metadata
188 01:52:54.024499 - LAVA_JOB_ID=949480
189 01:52:54.024712 - LAVA_DISPATCHER_IP=192.168.6.2
190 01:52:54.025083 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 01:52:54.026065 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 01:52:54.026378 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 01:52:54.026587 skipped lava-vland-overlay
194 01:52:54.026830 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 01:52:54.027091 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 01:52:54.027309 skipped lava-multinode-overlay
197 01:52:54.027551 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 01:52:54.027801 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 01:52:54.028083 Loading test definitions
200 01:52:54.028371 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 01:52:54.028593 Using /lava-949480 at stage 0
202 01:52:54.029819 uuid=949480_1.6.2.4.1 testdef=None
203 01:52:54.030125 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 01:52:54.030389 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 01:52:54.032191 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 01:52:54.032985 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:10) [common]
208 01:52:54.035195 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 01:52:54.036053 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:10) [common]
211 01:52:54.038167 runner path: /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 949480_1.6.2.4.1
212 01:52:54.038739 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 01:52:54.039492 Creating lava-test-runner.conf files
215 01:52:54.039693 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949480/lava-overlay-s8see4wr/lava-949480/0 for stage 0
216 01:52:54.040052 - 0_v4l2-decoder-conformance-h265
217 01:52:54.040400 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 01:52:54.040672 start: 1.6.2.5 compress-overlay (timeout 00:09:10) [common]
219 01:52:54.062311 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 01:52:54.062701 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
221 01:52:54.062959 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 01:52:54.063223 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 01:52:54.063483 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
224 01:52:54.710624 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 01:52:54.711124 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 01:52:54.711413 extracting modules file /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949480/extract-nfsrootfs-mu8r7l2x
227 01:52:56.182768 extracting modules file /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949480/extract-overlay-ramdisk-2p_l3prb/ramdisk
228 01:52:57.639029 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 01:52:57.639509 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 01:52:57.639783 [common] Applying overlay to NFS
231 01:52:57.640016 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949480/compress-overlay-kpy3ibfq/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949480/extract-nfsrootfs-mu8r7l2x
232 01:52:57.669182 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 01:52:57.669598 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 01:52:57.669872 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 01:52:57.670102 Converting downloaded kernel to a uImage
236 01:52:57.670408 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/kernel/Image /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/kernel/uImage
237 01:52:58.120350 output: Image Name:
238 01:52:58.120777 output: Created: Thu Nov 7 01:52:57 2024
239 01:52:58.120988 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 01:52:58.121194 output: Data Size: 37878272 Bytes = 36990.50 KiB = 36.12 MiB
241 01:52:58.121395 output: Load Address: 01080000
242 01:52:58.121595 output: Entry Point: 01080000
243 01:52:58.121794 output:
244 01:52:58.122132 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 01:52:58.122402 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 01:52:58.122670 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 01:52:58.122922 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 01:52:58.123179 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 01:52:58.123433 Building ramdisk /var/lib/lava/dispatcher/tmp/949480/extract-overlay-ramdisk-2p_l3prb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949480/extract-overlay-ramdisk-2p_l3prb/ramdisk
250 01:53:00.345470 >> 173435 blocks
251 01:53:07.989702 Adding RAMdisk u-boot header.
252 01:53:07.990149 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949480/extract-overlay-ramdisk-2p_l3prb/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949480/extract-overlay-ramdisk-2p_l3prb/ramdisk.cpio.gz.uboot
253 01:53:08.246684 output: Image Name:
254 01:53:08.247103 output: Created: Thu Nov 7 01:53:07 2024
255 01:53:08.247317 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 01:53:08.247521 output: Data Size: 24147203 Bytes = 23581.25 KiB = 23.03 MiB
257 01:53:08.247722 output: Load Address: 00000000
258 01:53:08.247920 output: Entry Point: 00000000
259 01:53:08.248328 output:
260 01:53:08.249473 rename /var/lib/lava/dispatcher/tmp/949480/extract-overlay-ramdisk-2p_l3prb/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/ramdisk/ramdisk.cpio.gz.uboot
261 01:53:08.250243 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 01:53:08.250832 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 01:53:08.251410 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 01:53:08.251903 No LXC device requested
265 01:53:08.252499 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 01:53:08.253060 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 01:53:08.253603 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 01:53:08.254056 Checking files for TFTP limit of 4294967296 bytes.
269 01:53:08.256995 end: 1 tftp-deploy (duration 00:01:04) [common]
270 01:53:08.257618 start: 2 uboot-action (timeout 00:05:00) [common]
271 01:53:08.258190 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 01:53:08.258733 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 01:53:08.259283 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 01:53:08.259851 Using kernel file from prepare-kernel: 949480/tftp-deploy-mqde_a_w/kernel/uImage
275 01:53:08.260586 substitutions:
276 01:53:08.261033 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 01:53:08.261471 - {DTB_ADDR}: 0x01070000
278 01:53:08.261906 - {DTB}: 949480/tftp-deploy-mqde_a_w/dtb/meson-g12b-a311d-libretech-cc.dtb
279 01:53:08.262339 - {INITRD}: 949480/tftp-deploy-mqde_a_w/ramdisk/ramdisk.cpio.gz.uboot
280 01:53:08.262769 - {KERNEL_ADDR}: 0x01080000
281 01:53:08.263198 - {KERNEL}: 949480/tftp-deploy-mqde_a_w/kernel/uImage
282 01:53:08.263627 - {LAVA_MAC}: None
283 01:53:08.264121 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/949480/extract-nfsrootfs-mu8r7l2x
284 01:53:08.264561 - {NFS_SERVER_IP}: 192.168.6.2
285 01:53:08.264988 - {PRESEED_CONFIG}: None
286 01:53:08.265414 - {PRESEED_LOCAL}: None
287 01:53:08.265839 - {RAMDISK_ADDR}: 0x08000000
288 01:53:08.266261 - {RAMDISK}: 949480/tftp-deploy-mqde_a_w/ramdisk/ramdisk.cpio.gz.uboot
289 01:53:08.266684 - {ROOT_PART}: None
290 01:53:08.267108 - {ROOT}: None
291 01:53:08.267530 - {SERVER_IP}: 192.168.6.2
292 01:53:08.267954 - {TEE_ADDR}: 0x83000000
293 01:53:08.268401 - {TEE}: None
294 01:53:08.268828 Parsed boot commands:
295 01:53:08.269237 - setenv autoload no
296 01:53:08.269658 - setenv initrd_high 0xffffffff
297 01:53:08.270077 - setenv fdt_high 0xffffffff
298 01:53:08.270499 - dhcp
299 01:53:08.270921 - setenv serverip 192.168.6.2
300 01:53:08.271343 - tftpboot 0x01080000 949480/tftp-deploy-mqde_a_w/kernel/uImage
301 01:53:08.271765 - tftpboot 0x08000000 949480/tftp-deploy-mqde_a_w/ramdisk/ramdisk.cpio.gz.uboot
302 01:53:08.272258 - tftpboot 0x01070000 949480/tftp-deploy-mqde_a_w/dtb/meson-g12b-a311d-libretech-cc.dtb
303 01:53:08.272692 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/949480/extract-nfsrootfs-mu8r7l2x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 01:53:08.273130 - bootm 0x01080000 0x08000000 0x01070000
305 01:53:08.273669 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 01:53:08.275288 start: 2.3 connect-device (timeout 00:05:00) [common]
308 01:53:08.275744 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 01:53:08.292780 Setting prompt string to ['lava-test: # ']
310 01:53:08.294340 end: 2.3 connect-device (duration 00:00:00) [common]
311 01:53:08.294986 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 01:53:08.295578 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 01:53:08.296221 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 01:53:08.297502 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 01:53:08.336007 >> OK - accepted request
316 01:53:08.338182 Returned 0 in 0 seconds
317 01:53:08.439408 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 01:53:08.441239 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 01:53:08.441858 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 01:53:08.442408 Setting prompt string to ['Hit any key to stop autoboot']
322 01:53:08.442910 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 01:53:08.444655 Trying 192.168.56.21...
324 01:53:08.445186 Connected to conserv1.
325 01:53:08.445656 Escape character is '^]'.
326 01:53:08.446120
327 01:53:08.446588 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 01:53:08.447050
329 01:53:19.594440 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 01:53:19.594866 bl2_stage_init 0x01
331 01:53:19.595092 bl2_stage_init 0x81
332 01:53:19.599940 hw id: 0x0000 - pwm id 0x01
333 01:53:19.600265 bl2_stage_init 0xc1
334 01:53:19.600469 bl2_stage_init 0x02
335 01:53:19.600666
336 01:53:19.605508 L0:00000000
337 01:53:19.605945 L1:20000703
338 01:53:19.606350 L2:00008067
339 01:53:19.606736 L3:14000000
340 01:53:19.608375 B2:00402000
341 01:53:19.608866 B1:e0f83180
342 01:53:19.609312
343 01:53:19.609749 TE: 58124
344 01:53:19.610184
345 01:53:19.619569 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 01:53:19.620081
347 01:53:19.620529 Board ID = 1
348 01:53:19.620960 Set A53 clk to 24M
349 01:53:19.621389 Set A73 clk to 24M
350 01:53:19.625487 Set clk81 to 24M
351 01:53:19.625949 A53 clk: 1200 MHz
352 01:53:19.626381 A73 clk: 1200 MHz
353 01:53:19.630736 CLK81: 166.6M
354 01:53:19.631277 smccc: 00012a91
355 01:53:19.636362 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 01:53:19.636853 board id: 1
357 01:53:19.642796 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 01:53:19.655755 fw parse done
359 01:53:19.660705 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 01:53:19.704217 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 01:53:19.715206 PIEI prepare done
362 01:53:19.715719 fastboot data load
363 01:53:19.716203 fastboot data verify
364 01:53:19.720857 verify result: 266
365 01:53:19.726490 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 01:53:19.726970 LPDDR4 probe
367 01:53:19.727428 ddr clk to 1584MHz
368 01:53:19.734406 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 01:53:19.771653
370 01:53:19.772227 dmc_version 0001
371 01:53:19.778308 Check phy result
372 01:53:19.784279 INFO : End of CA training
373 01:53:19.784763 INFO : End of initialization
374 01:53:19.789785 INFO : Training has run successfully!
375 01:53:19.790264 Check phy result
376 01:53:19.795397 INFO : End of initialization
377 01:53:19.795869 INFO : End of read enable training
378 01:53:19.798658 INFO : End of fine write leveling
379 01:53:19.804208 INFO : End of Write leveling coarse delay
380 01:53:19.809865 INFO : Training has run successfully!
381 01:53:19.810344 Check phy result
382 01:53:19.810793 INFO : End of initialization
383 01:53:19.815433 INFO : End of read dq deskew training
384 01:53:19.821152 INFO : End of MPR read delay center optimization
385 01:53:19.821638 INFO : End of write delay center optimization
386 01:53:19.826633 INFO : End of read delay center optimization
387 01:53:19.832224 INFO : End of max read latency training
388 01:53:19.832720 INFO : Training has run successfully!
389 01:53:19.837776 1D training succeed
390 01:53:19.843841 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 01:53:19.891456 Check phy result
392 01:53:19.892094 INFO : End of initialization
393 01:53:19.913982 INFO : End of 2D read delay Voltage center optimization
394 01:53:19.934214 INFO : End of 2D read delay Voltage center optimization
395 01:53:19.986320 INFO : End of 2D write delay Voltage center optimization
396 01:53:20.035624 INFO : End of 2D write delay Voltage center optimization
397 01:53:20.041154 INFO : Training has run successfully!
398 01:53:20.041645
399 01:53:20.042119 channel==0
400 01:53:20.046704 RxClkDly_Margin_A0==88 ps 9
401 01:53:20.047199 TxDqDly_Margin_A0==98 ps 10
402 01:53:20.052318 RxClkDly_Margin_A1==88 ps 9
403 01:53:20.052801 TxDqDly_Margin_A1==98 ps 10
404 01:53:20.053259 TrainedVREFDQ_A0==74
405 01:53:20.057984 TrainedVREFDQ_A1==74
406 01:53:20.058520 VrefDac_Margin_A0==24
407 01:53:20.058977 DeviceVref_Margin_A0==40
408 01:53:20.063535 VrefDac_Margin_A1==25
409 01:53:20.064059 DeviceVref_Margin_A1==40
410 01:53:20.064515
411 01:53:20.064966
412 01:53:20.069202 channel==1
413 01:53:20.069681 RxClkDly_Margin_A0==98 ps 10
414 01:53:20.070131 TxDqDly_Margin_A0==98 ps 10
415 01:53:20.074799 RxClkDly_Margin_A1==88 ps 9
416 01:53:20.075274 TxDqDly_Margin_A1==88 ps 9
417 01:53:20.080331 TrainedVREFDQ_A0==77
418 01:53:20.080813 TrainedVREFDQ_A1==77
419 01:53:20.081265 VrefDac_Margin_A0==22
420 01:53:20.085929 DeviceVref_Margin_A0==37
421 01:53:20.086402 VrefDac_Margin_A1==24
422 01:53:20.092272 DeviceVref_Margin_A1==37
423 01:53:20.092749
424 01:53:20.093205 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 01:53:20.093647
426 01:53:20.125222 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000017 00000017 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 01:53:20.125833 2D training succeed
428 01:53:20.130751 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 01:53:20.136357 auto size-- 65535DDR cs0 size: 2048MB
430 01:53:20.136855 DDR cs1 size: 2048MB
431 01:53:20.141965 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 01:53:20.142471 cs0 DataBus test pass
433 01:53:20.147556 cs1 DataBus test pass
434 01:53:20.148092 cs0 AddrBus test pass
435 01:53:20.148557 cs1 AddrBus test pass
436 01:53:20.149000
437 01:53:20.153204 100bdlr_step_size ps== 420
438 01:53:20.153692 result report
439 01:53:20.158719 boot times 0Enable ddr reg access
440 01:53:20.164427 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 01:53:20.177566 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 01:53:20.751429 0.0;M3 CHK:0;cm4_sp_mode 0
443 01:53:20.752153 MVN_1=0x00000000
444 01:53:20.756710 MVN_2=0x00000000
445 01:53:20.762566 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 01:53:20.763064 OPS=0x10
447 01:53:20.763527 ring efuse init
448 01:53:20.763976 chipver efuse init
449 01:53:20.770887 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 01:53:20.771430 [0.018961 Inits done]
451 01:53:20.771892 secure task start!
452 01:53:20.778350 high task start!
453 01:53:20.778836 low task start!
454 01:53:20.779291 run into bl31
455 01:53:20.785090 NOTICE: BL31: v1.3(release):4fc40b1
456 01:53:20.791934 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 01:53:20.792494 NOTICE: BL31: G12A normal boot!
458 01:53:20.818296 NOTICE: BL31: BL33 decompress pass
459 01:53:20.823011 ERROR: Error initializing runtime service opteed_fast
460 01:53:22.056640
461 01:53:22.057343
462 01:53:22.065056 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 01:53:22.065627
464 01:53:22.066138 Model: Libre Computer AML-A311D-CC Alta
465 01:53:22.273674 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 01:53:22.296894 DRAM: 2 GiB (effective 3.8 GiB)
467 01:53:22.440064 Core: 408 devices, 31 uclasses, devicetree: separate
468 01:53:22.445744 WDT: Not starting watchdog@f0d0
469 01:53:22.478123 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 01:53:22.490469 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 01:53:22.495502 ** Bad device specification mmc 0 **
472 01:53:22.505777 Card did not respond to voltage select! : -110
473 01:53:22.513502 ** Bad device specification mmc 0 **
474 01:53:22.513838 Couldn't find partition mmc 0
475 01:53:22.521751 Card did not respond to voltage select! : -110
476 01:53:22.527414 ** Bad device specification mmc 0 **
477 01:53:22.527725 Couldn't find partition mmc 0
478 01:53:22.532283 Error: could not access storage.
479 01:53:23.794786 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 01:53:23.795476 bl2_stage_init 0x01
481 01:53:23.795957 bl2_stage_init 0x81
482 01:53:23.800282 hw id: 0x0000 - pwm id 0x01
483 01:53:23.800802 bl2_stage_init 0xc1
484 01:53:23.801266 bl2_stage_init 0x02
485 01:53:23.801715
486 01:53:23.805852 L0:00000000
487 01:53:23.806351 L1:20000703
488 01:53:23.806800 L2:00008067
489 01:53:23.807243 L3:14000000
490 01:53:23.811592 B2:00402000
491 01:53:23.812180 B1:e0f83180
492 01:53:23.812641
493 01:53:23.813087 TE: 58124
494 01:53:23.813529
495 01:53:23.817080 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 01:53:23.817570
497 01:53:23.818023 Board ID = 1
498 01:53:23.822665 Set A53 clk to 24M
499 01:53:23.823155 Set A73 clk to 24M
500 01:53:23.823604 Set clk81 to 24M
501 01:53:23.828253 A53 clk: 1200 MHz
502 01:53:23.828733 A73 clk: 1200 MHz
503 01:53:23.829177 CLK81: 166.6M
504 01:53:23.829620 smccc: 00012a91
505 01:53:23.833857 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 01:53:23.839587 board id: 1
507 01:53:23.845342 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 01:53:23.856038 fw parse done
509 01:53:23.862007 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 01:53:23.904726 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 01:53:23.915660 PIEI prepare done
512 01:53:23.916214 fastboot data load
513 01:53:23.916678 fastboot data verify
514 01:53:23.921324 verify result: 266
515 01:53:23.926865 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 01:53:23.927380 LPDDR4 probe
517 01:53:23.927837 ddr clk to 1584MHz
518 01:53:23.934848 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 01:53:23.972262
520 01:53:23.972808 dmc_version 0001
521 01:53:23.979012 Check phy result
522 01:53:23.984830 INFO : End of CA training
523 01:53:23.985342 INFO : End of initialization
524 01:53:23.990354 INFO : Training has run successfully!
525 01:53:23.990865 Check phy result
526 01:53:23.995866 INFO : End of initialization
527 01:53:23.996405 INFO : End of read enable training
528 01:53:24.001612 INFO : End of fine write leveling
529 01:53:24.007104 INFO : End of Write leveling coarse delay
530 01:53:24.007630 INFO : Training has run successfully!
531 01:53:24.008136 Check phy result
532 01:53:24.012981 INFO : End of initialization
533 01:53:24.013511 INFO : End of read dq deskew training
534 01:53:24.018353 INFO : End of MPR read delay center optimization
535 01:53:24.023904 INFO : End of write delay center optimization
536 01:53:24.029519 INFO : End of read delay center optimization
537 01:53:24.030053 INFO : End of max read latency training
538 01:53:24.035175 INFO : Training has run successfully!
539 01:53:24.035685 1D training succeed
540 01:53:24.044392 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 01:53:24.091925 Check phy result
542 01:53:24.092544 INFO : End of initialization
543 01:53:24.113673 INFO : End of 2D read delay Voltage center optimization
544 01:53:24.133923 INFO : End of 2D read delay Voltage center optimization
545 01:53:24.448941 INFO : End of 2D write delay Voltage center optimization
546 01:53:24.449589 INFO : End of 2D write delay Voltage center optimization
547 01:53:24.449838 INFO : Training has run successfully!
548 01:53:24.450050
549 01:53:24.450273 channel==0
550 01:53:24.450486 RxClkDly_Margin_A0==88 ps 9
551 01:53:24.450699 TxDqDly_Margin_A0==98 ps 10
552 01:53:24.450901 RxClkDly_Margin_A1==88 ps 9
553 01:53:24.451110 TxDqDly_Margin_A1==88 ps 9
554 01:53:24.451320 TrainedVREFDQ_A0==74
555 01:53:24.451640 TrainedVREFDQ_A1==74
556 01:53:24.451964 VrefDac_Margin_A0==25
557 01:53:24.452228 DeviceVref_Margin_A0==40
558 01:53:24.452445 VrefDac_Margin_A1==25
559 01:53:24.452656 DeviceVref_Margin_A1==40
560 01:53:24.452863
561 01:53:24.453063
562 01:53:24.453267 channel==1
563 01:53:24.453472 RxClkDly_Margin_A0==98 ps 10
564 01:53:24.453668 TxDqDly_Margin_A0==88 ps 9
565 01:53:24.453871 RxClkDly_Margin_A1==88 ps 9
566 01:53:24.454065 TxDqDly_Margin_A1==88 ps 9
567 01:53:24.454566 TrainedVREFDQ_A0==77
568 01:53:24.454815 TrainedVREFDQ_A1==77
569 01:53:24.455023 VrefDac_Margin_A0==22
570 01:53:24.455230 DeviceVref_Margin_A0==37
571 01:53:24.455435 VrefDac_Margin_A1==24
572 01:53:24.455638 DeviceVref_Margin_A1==37
573 01:53:24.455832
574 01:53:24.456054 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 01:53:24.456265
576 01:53:24.456462 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
577 01:53:24.456674 2D training succeed
578 01:53:24.456872 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 01:53:24.457076 auto size-- 65535DDR cs0 size: 2048MB
580 01:53:24.457272 DDR cs1 size: 2048MB
581 01:53:24.457594 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 01:53:24.457828 cs0 DataBus test pass
583 01:53:24.458025 cs1 DataBus test pass
584 01:53:24.458217 cs0 AddrBus test pass
585 01:53:24.458409 cs1 AddrBus test pass
586 01:53:24.458600
587 01:53:24.458803 100bdlr_step_size ps== 420
588 01:53:24.459014 result report
589 01:53:24.459216 boot times 0Enable ddr reg access
590 01:53:24.459411 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 01:53:24.459613 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 01:53:24.950883 0.0;M3 CHK:0;cm4_sp_mode 0
593 01:53:24.951316 MVN_1=0x00000000
594 01:53:24.956281 MVN_2=0x00000000
595 01:53:24.962028 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 01:53:24.962304 OPS=0x10
597 01:53:24.962530 ring efuse init
598 01:53:24.962739 chipver efuse init
599 01:53:24.967614 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 01:53:24.973238 [0.018961 Inits done]
601 01:53:24.973509 secure task start!
602 01:53:24.973715 high task start!
603 01:53:24.977876 low task start!
604 01:53:24.978153 run into bl31
605 01:53:24.984545 NOTICE: BL31: v1.3(release):4fc40b1
606 01:53:24.992304 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 01:53:24.992585 NOTICE: BL31: G12A normal boot!
608 01:53:25.017673 NOTICE: BL31: BL33 decompress pass
609 01:53:25.023361 ERROR: Error initializing runtime service opteed_fast
610 01:53:26.256268
611 01:53:26.256671
612 01:53:26.264663 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 01:53:26.265025
614 01:53:26.265257 Model: Libre Computer AML-A311D-CC Alta
615 01:53:26.473211 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 01:53:26.496117 DRAM: 2 GiB (effective 3.8 GiB)
617 01:53:26.639331 Core: 408 devices, 31 uclasses, devicetree: separate
618 01:53:26.645323 WDT: Not starting watchdog@f0d0
619 01:53:26.677568 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 01:53:26.690058 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 01:53:26.695121 ** Bad device specification mmc 0 **
622 01:53:26.705203 Card did not respond to voltage select! : -110
623 01:53:26.712921 ** Bad device specification mmc 0 **
624 01:53:26.713198 Couldn't find partition mmc 0
625 01:53:26.721258 Card did not respond to voltage select! : -110
626 01:53:26.726757 ** Bad device specification mmc 0 **
627 01:53:26.727022 Couldn't find partition mmc 0
628 01:53:26.731880 Error: could not access storage.
629 01:53:27.074451 Net: eth0: ethernet@ff3f0000
630 01:53:27.074860 starting USB...
631 01:53:27.326149 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 01:53:27.326535 Starting the controller
633 01:53:27.333177 USB XHCI 1.10
634 01:53:29.045049 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 01:53:29.045458 bl2_stage_init 0x01
636 01:53:29.045675 bl2_stage_init 0x81
637 01:53:29.050519 hw id: 0x0000 - pwm id 0x01
638 01:53:29.050936 bl2_stage_init 0xc1
639 01:53:29.051259 bl2_stage_init 0x02
640 01:53:29.051569
641 01:53:29.056130 L0:00000000
642 01:53:29.056524 L1:20000703
643 01:53:29.056762 L2:00008067
644 01:53:29.056967 L3:14000000
645 01:53:29.059046 B2:00402000
646 01:53:29.059421 B1:e0f83180
647 01:53:29.059739
648 01:53:29.060088 TE: 58124
649 01:53:29.060404
650 01:53:29.070271 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 01:53:29.070598
652 01:53:29.070819 Board ID = 1
653 01:53:29.071026 Set A53 clk to 24M
654 01:53:29.071227 Set A73 clk to 24M
655 01:53:29.075839 Set clk81 to 24M
656 01:53:29.076131 A53 clk: 1200 MHz
657 01:53:29.076348 A73 clk: 1200 MHz
658 01:53:29.079322 CLK81: 166.6M
659 01:53:29.079643 smccc: 00012a92
660 01:53:29.084943 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 01:53:29.090531 board id: 1
662 01:53:29.095583 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 01:53:29.106321 fw parse done
664 01:53:29.112216 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 01:53:29.153876 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 01:53:29.165828 PIEI prepare done
667 01:53:29.166115 fastboot data load
668 01:53:29.166323 fastboot data verify
669 01:53:29.171343 verify result: 266
670 01:53:29.176911 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 01:53:29.177300 LPDDR4 probe
672 01:53:29.177625 ddr clk to 1584MHz
673 01:53:29.184908 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 01:53:29.222331
675 01:53:29.222656 dmc_version 0001
676 01:53:29.228839 Check phy result
677 01:53:29.234715 INFO : End of CA training
678 01:53:29.235141 INFO : End of initialization
679 01:53:29.240287 INFO : Training has run successfully!
680 01:53:29.240583 Check phy result
681 01:53:29.245938 INFO : End of initialization
682 01:53:29.246347 INFO : End of read enable training
683 01:53:29.251498 INFO : End of fine write leveling
684 01:53:29.257100 INFO : End of Write leveling coarse delay
685 01:53:29.257379 INFO : Training has run successfully!
686 01:53:29.257584 Check phy result
687 01:53:29.262656 INFO : End of initialization
688 01:53:29.263055 INFO : End of read dq deskew training
689 01:53:29.268312 INFO : End of MPR read delay center optimization
690 01:53:29.273950 INFO : End of write delay center optimization
691 01:53:29.279497 INFO : End of read delay center optimization
692 01:53:29.279782 INFO : End of max read latency training
693 01:53:29.285104 INFO : Training has run successfully!
694 01:53:29.285379 1D training succeed
695 01:53:29.294315 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 01:53:29.341928 Check phy result
697 01:53:29.342383 INFO : End of initialization
698 01:53:29.364432 INFO : End of 2D read delay Voltage center optimization
699 01:53:29.384475 INFO : End of 2D read delay Voltage center optimization
700 01:53:29.435609 INFO : End of 2D write delay Voltage center optimization
701 01:53:29.485713 INFO : End of 2D write delay Voltage center optimization
702 01:53:29.491182 INFO : Training has run successfully!
703 01:53:29.491485
704 01:53:29.491707 channel==0
705 01:53:29.496759 RxClkDly_Margin_A0==88 ps 9
706 01:53:29.497179 TxDqDly_Margin_A0==98 ps 10
707 01:53:29.502574 RxClkDly_Margin_A1==88 ps 9
708 01:53:29.503035 TxDqDly_Margin_A1==98 ps 10
709 01:53:29.503285 TrainedVREFDQ_A0==74
710 01:53:29.507946 TrainedVREFDQ_A1==74
711 01:53:29.508264 VrefDac_Margin_A0==24
712 01:53:29.508493 DeviceVref_Margin_A0==40
713 01:53:29.513570 VrefDac_Margin_A1==25
714 01:53:29.513988 DeviceVref_Margin_A1==40
715 01:53:29.514317
716 01:53:29.514638
717 01:53:29.519134 channel==1
718 01:53:29.519549 RxClkDly_Margin_A0==98 ps 10
719 01:53:29.519814 TxDqDly_Margin_A0==98 ps 10
720 01:53:29.524724 RxClkDly_Margin_A1==88 ps 9
721 01:53:29.525145 TxDqDly_Margin_A1==98 ps 10
722 01:53:29.530360 TrainedVREFDQ_A0==77
723 01:53:29.530650 TrainedVREFDQ_A1==77
724 01:53:29.530861 VrefDac_Margin_A0==22
725 01:53:29.535971 DeviceVref_Margin_A0==37
726 01:53:29.536433 VrefDac_Margin_A1==24
727 01:53:29.541547 DeviceVref_Margin_A1==37
728 01:53:29.541980
729 01:53:29.542228 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 01:53:29.547174
731 01:53:29.575102 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000017 00000016 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
732 01:53:29.575611 2D training succeed
733 01:53:29.580784 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 01:53:29.586450 auto size-- 65535DDR cs0 size: 2048MB
735 01:53:29.586763 DDR cs1 size: 2048MB
736 01:53:29.591937 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 01:53:29.592378 cs0 DataBus test pass
738 01:53:29.597560 cs1 DataBus test pass
739 01:53:29.597960 cs0 AddrBus test pass
740 01:53:29.598203 cs1 AddrBus test pass
741 01:53:29.598411
742 01:53:29.603147 100bdlr_step_size ps== 420
743 01:53:29.603440 result report
744 01:53:29.608723 boot times 0Enable ddr reg access
745 01:53:29.613231 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 01:53:29.626671 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 01:53:30.199649 0.0;M3 CHK:0;cm4_sp_mode 0
748 01:53:30.200080 MVN_1=0x00000000
749 01:53:30.205173 MVN_2=0x00000000
750 01:53:30.210933 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 01:53:30.211207 OPS=0x10
752 01:53:30.211414 ring efuse init
753 01:53:30.211614 chipver efuse init
754 01:53:30.219059 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 01:53:30.219321 [0.018961 Inits done]
756 01:53:30.225773 secure task start!
757 01:53:30.226024 high task start!
758 01:53:30.226226 low task start!
759 01:53:30.226420 run into bl31
760 01:53:30.233399 NOTICE: BL31: v1.3(release):4fc40b1
761 01:53:30.240277 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 01:53:30.240546 NOTICE: BL31: G12A normal boot!
763 01:53:30.266585 NOTICE: BL31: BL33 decompress pass
764 01:53:30.271275 ERROR: Error initializing runtime service opteed_fast
765 01:53:31.505097
766 01:53:31.505551
767 01:53:31.513690 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 01:53:31.514065
769 01:53:31.514291 Model: Libre Computer AML-A311D-CC Alta
770 01:53:31.721993 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 01:53:31.744385 DRAM: 2 GiB (effective 3.8 GiB)
772 01:53:31.888389 Core: 408 devices, 31 uclasses, devicetree: separate
773 01:53:31.894228 WDT: Not starting watchdog@f0d0
774 01:53:31.926502 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 01:53:31.938891 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 01:53:31.943908 ** Bad device specification mmc 0 **
777 01:53:31.954296 Card did not respond to voltage select! : -110
778 01:53:31.961902 ** Bad device specification mmc 0 **
779 01:53:31.962212 Couldn't find partition mmc 0
780 01:53:31.970256 Card did not respond to voltage select! : -110
781 01:53:31.975762 ** Bad device specification mmc 0 **
782 01:53:31.976073 Couldn't find partition mmc 0
783 01:53:31.980817 Error: could not access storage.
784 01:53:32.323324 Net: eth0: ethernet@ff3f0000
785 01:53:32.323743 starting USB...
786 01:53:32.575173 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 01:53:32.575635 Starting the controller
788 01:53:32.582135 USB XHCI 1.10
789 01:53:34.746515 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 01:53:34.747090 bl2_stage_init 0x01
791 01:53:34.747348 bl2_stage_init 0x81
792 01:53:34.752158 hw id: 0x0000 - pwm id 0x01
793 01:53:34.752440 bl2_stage_init 0xc1
794 01:53:34.752662 bl2_stage_init 0x02
795 01:53:34.752880
796 01:53:34.757738 L0:00000000
797 01:53:34.758131 L1:20000703
798 01:53:34.758461 L2:00008067
799 01:53:34.758773 L3:14000000
800 01:53:34.763352 B2:00402000
801 01:53:34.763733 B1:e0f83180
802 01:53:34.764099
803 01:53:34.764422 TE: 58124
804 01:53:34.764672
805 01:53:34.768939 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 01:53:34.769219
807 01:53:34.769432 Board ID = 1
808 01:53:34.774462 Set A53 clk to 24M
809 01:53:34.774857 Set A73 clk to 24M
810 01:53:34.775199 Set clk81 to 24M
811 01:53:34.780147 A53 clk: 1200 MHz
812 01:53:34.780524 A73 clk: 1200 MHz
813 01:53:34.780855 CLK81: 166.6M
814 01:53:34.781088 smccc: 00012a92
815 01:53:34.785703 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 01:53:34.791218 board id: 1
817 01:53:34.797146 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 01:53:34.807828 fw parse done
819 01:53:34.813797 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 01:53:34.856427 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 01:53:34.867305 PIEI prepare done
822 01:53:34.867590 fastboot data load
823 01:53:34.867803 fastboot data verify
824 01:53:34.872931 verify result: 266
825 01:53:34.878474 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 01:53:34.878979 LPDDR4 probe
827 01:53:34.879443 ddr clk to 1584MHz
828 01:53:34.886515 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 01:53:34.923799
830 01:53:34.924425 dmc_version 0001
831 01:53:34.930440 Check phy result
832 01:53:34.936326 INFO : End of CA training
833 01:53:34.936830 INFO : End of initialization
834 01:53:34.941867 INFO : Training has run successfully!
835 01:53:34.942367 Check phy result
836 01:53:34.947452 INFO : End of initialization
837 01:53:34.947949 INFO : End of read enable training
838 01:53:34.950940 INFO : End of fine write leveling
839 01:53:34.956458 INFO : End of Write leveling coarse delay
840 01:53:34.962177 INFO : Training has run successfully!
841 01:53:34.962646 Check phy result
842 01:53:34.963082 INFO : End of initialization
843 01:53:34.967656 INFO : End of read dq deskew training
844 01:53:34.973248 INFO : End of MPR read delay center optimization
845 01:53:34.973710 INFO : End of write delay center optimization
846 01:53:34.978851 INFO : End of read delay center optimization
847 01:53:34.984415 INFO : End of max read latency training
848 01:53:34.984866 INFO : Training has run successfully!
849 01:53:34.990082 1D training succeed
850 01:53:34.995923 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 01:53:35.043512 Check phy result
852 01:53:35.044082 INFO : End of initialization
853 01:53:35.065230 INFO : End of 2D read delay Voltage center optimization
854 01:53:35.085459 INFO : End of 2D read delay Voltage center optimization
855 01:53:35.137633 INFO : End of 2D write delay Voltage center optimization
856 01:53:35.187031 INFO : End of 2D write delay Voltage center optimization
857 01:53:35.192418 INFO : Training has run successfully!
858 01:53:35.192880
859 01:53:35.193305 channel==0
860 01:53:35.198193 RxClkDly_Margin_A0==88 ps 9
861 01:53:35.198646 TxDqDly_Margin_A0==98 ps 10
862 01:53:35.201357 RxClkDly_Margin_A1==88 ps 9
863 01:53:35.201803 TxDqDly_Margin_A1==98 ps 10
864 01:53:35.206958 TrainedVREFDQ_A0==74
865 01:53:35.207484 TrainedVREFDQ_A1==74
866 01:53:35.212514 VrefDac_Margin_A0==25
867 01:53:35.213020 DeviceVref_Margin_A0==40
868 01:53:35.213414 VrefDac_Margin_A1==25
869 01:53:35.218180 DeviceVref_Margin_A1==40
870 01:53:35.218617
871 01:53:35.219006
872 01:53:35.219395 channel==1
873 01:53:35.219775 RxClkDly_Margin_A0==98 ps 10
874 01:53:35.221567 TxDqDly_Margin_A0==98 ps 10
875 01:53:35.227161 RxClkDly_Margin_A1==98 ps 10
876 01:53:35.227602 TxDqDly_Margin_A1==88 ps 9
877 01:53:35.228024 TrainedVREFDQ_A0==77
878 01:53:35.232752 TrainedVREFDQ_A1==77
879 01:53:35.233181 VrefDac_Margin_A0==22
880 01:53:35.238364 DeviceVref_Margin_A0==37
881 01:53:35.238790 VrefDac_Margin_A1==22
882 01:53:35.239180 DeviceVref_Margin_A1==37
883 01:53:35.239562
884 01:53:35.243904 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 01:53:35.244359
886 01:53:35.277523 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
887 01:53:35.277991 2D training succeed
888 01:53:35.283180 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 01:53:35.288742 auto size-- 65535DDR cs0 size: 2048MB
890 01:53:35.289171 DDR cs1 size: 2048MB
891 01:53:35.294372 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 01:53:35.294795 cs0 DataBus test pass
893 01:53:35.295187 cs1 DataBus test pass
894 01:53:35.299956 cs0 AddrBus test pass
895 01:53:35.300415 cs1 AddrBus test pass
896 01:53:35.300806
897 01:53:35.305552 100bdlr_step_size ps== 420
898 01:53:35.305993 result report
899 01:53:35.306382 boot times 0Enable ddr reg access
900 01:53:35.315451 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 01:53:35.328948 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 01:53:35.902055 0.0;M3 CHK:0;cm4_sp_mode 0
903 01:53:35.902855 MVN_1=0x00000000
904 01:53:35.907416 MVN_2=0x00000000
905 01:53:35.913170 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 01:53:35.913699 OPS=0x10
907 01:53:35.914159 ring efuse init
908 01:53:35.914621 chipver efuse init
909 01:53:35.918758 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 01:53:35.924390 [0.018961 Inits done]
911 01:53:35.924911 secure task start!
912 01:53:35.925381 high task start!
913 01:53:35.929018 low task start!
914 01:53:35.929522 run into bl31
915 01:53:35.935646 NOTICE: BL31: v1.3(release):4fc40b1
916 01:53:35.943441 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 01:53:35.943954 NOTICE: BL31: G12A normal boot!
918 01:53:35.968792 NOTICE: BL31: BL33 decompress pass
919 01:53:35.974469 ERROR: Error initializing runtime service opteed_fast
920 01:53:37.207486
921 01:53:37.208144
922 01:53:37.215729 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 01:53:37.216215
924 01:53:37.216641 Model: Libre Computer AML-A311D-CC Alta
925 01:53:37.424310 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 01:53:37.447567 DRAM: 2 GiB (effective 3.8 GiB)
927 01:53:37.591292 Core: 408 devices, 31 uclasses, devicetree: separate
928 01:53:37.596506 WDT: Not starting watchdog@f0d0
929 01:53:37.628713 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 01:53:37.641190 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 01:53:37.646157 ** Bad device specification mmc 0 **
932 01:53:37.656508 Card did not respond to voltage select! : -110
933 01:53:37.664154 ** Bad device specification mmc 0 **
934 01:53:37.664593 Couldn't find partition mmc 0
935 01:53:37.672456 Card did not respond to voltage select! : -110
936 01:53:37.677983 ** Bad device specification mmc 0 **
937 01:53:37.678425 Couldn't find partition mmc 0
938 01:53:37.683025 Error: could not access storage.
939 01:53:38.026595 Net: eth0: ethernet@ff3f0000
940 01:53:38.026993 starting USB...
941 01:53:38.278485 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 01:53:38.279079 Starting the controller
943 01:53:38.285308 USB XHCI 1.10
944 01:53:40.146328 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 01:53:40.146944 bl2_stage_init 0x01
946 01:53:40.147380 bl2_stage_init 0x81
947 01:53:40.151846 hw id: 0x0000 - pwm id 0x01
948 01:53:40.152320 bl2_stage_init 0xc1
949 01:53:40.152735 bl2_stage_init 0x02
950 01:53:40.153139
951 01:53:40.157419 L0:00000000
952 01:53:40.157851 L1:20000703
953 01:53:40.158256 L2:00008067
954 01:53:40.158655 L3:14000000
955 01:53:40.160314 B2:00402000
956 01:53:40.160740 B1:e0f83180
957 01:53:40.161142
958 01:53:40.161543 TE: 58124
959 01:53:40.161945
960 01:53:40.171532 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 01:53:40.171972
962 01:53:40.172412 Board ID = 1
963 01:53:40.172812 Set A53 clk to 24M
964 01:53:40.173205 Set A73 clk to 24M
965 01:53:40.177157 Set clk81 to 24M
966 01:53:40.177598 A53 clk: 1200 MHz
967 01:53:40.178000 A73 clk: 1200 MHz
968 01:53:40.180453 CLK81: 166.6M
969 01:53:40.180889 smccc: 00012a92
970 01:53:40.185958 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 01:53:40.191676 board id: 1
972 01:53:40.196929 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 01:53:40.207691 fw parse done
974 01:53:40.213573 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 01:53:40.256180 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 01:53:40.267193 PIEI prepare done
977 01:53:40.267674 fastboot data load
978 01:53:40.268109 fastboot data verify
979 01:53:40.272792 verify result: 266
980 01:53:40.278298 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 01:53:40.278726 LPDDR4 probe
982 01:53:40.279114 ddr clk to 1584MHz
983 01:53:40.286284 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 01:53:40.323610
985 01:53:40.324115 dmc_version 0001
986 01:53:40.330419 Check phy result
987 01:53:40.336146 INFO : End of CA training
988 01:53:40.336570 INFO : End of initialization
989 01:53:40.342580 INFO : Training has run successfully!
990 01:53:40.343019 Check phy result
991 01:53:40.347595 INFO : End of initialization
992 01:53:40.348080 INFO : End of read enable training
993 01:53:40.350813 INFO : End of fine write leveling
994 01:53:40.356627 INFO : End of Write leveling coarse delay
995 01:53:40.361914 INFO : Training has run successfully!
996 01:53:40.362363 Check phy result
997 01:53:40.362770 INFO : End of initialization
998 01:53:40.367432 INFO : End of read dq deskew training
999 01:53:40.373031 INFO : End of MPR read delay center optimization
1000 01:53:40.373504 INFO : End of write delay center optimization
1001 01:53:40.378641 INFO : End of read delay center optimization
1002 01:53:40.384255 INFO : End of max read latency training
1003 01:53:40.384704 INFO : Training has run successfully!
1004 01:53:40.389830 1D training succeed
1005 01:53:40.396019 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 01:53:40.443538 Check phy result
1007 01:53:40.444120 INFO : End of initialization
1008 01:53:40.464974 INFO : End of 2D read delay Voltage center optimization
1009 01:53:40.484217 INFO : End of 2D read delay Voltage center optimization
1010 01:53:40.536275 INFO : End of 2D write delay Voltage center optimization
1011 01:53:40.585442 INFO : End of 2D write delay Voltage center optimization
1012 01:53:40.590972 INFO : Training has run successfully!
1013 01:53:40.591431
1014 01:53:40.591844 channel==0
1015 01:53:40.596503 RxClkDly_Margin_A0==88 ps 9
1016 01:53:40.596982 TxDqDly_Margin_A0==98 ps 10
1017 01:53:40.599955 RxClkDly_Margin_A1==88 ps 9
1018 01:53:40.600442 TxDqDly_Margin_A1==88 ps 9
1019 01:53:40.605523 TrainedVREFDQ_A0==74
1020 01:53:40.605983 TrainedVREFDQ_A1==74
1021 01:53:40.606402 VrefDac_Margin_A0==25
1022 01:53:40.611094 DeviceVref_Margin_A0==40
1023 01:53:40.611544 VrefDac_Margin_A1==25
1024 01:53:40.616693 DeviceVref_Margin_A1==40
1025 01:53:40.617134
1026 01:53:40.617540
1027 01:53:40.617938 channel==1
1028 01:53:40.618329 RxClkDly_Margin_A0==88 ps 9
1029 01:53:40.622240 TxDqDly_Margin_A0==88 ps 9
1030 01:53:40.622677 RxClkDly_Margin_A1==88 ps 9
1031 01:53:40.627911 TxDqDly_Margin_A1==108 ps 11
1032 01:53:40.628381 TrainedVREFDQ_A0==76
1033 01:53:40.628788 TrainedVREFDQ_A1==78
1034 01:53:40.633462 VrefDac_Margin_A0==23
1035 01:53:40.633906 DeviceVref_Margin_A0==38
1036 01:53:40.639016 VrefDac_Margin_A1==23
1037 01:53:40.639454 DeviceVref_Margin_A1==36
1038 01:53:40.639862
1039 01:53:40.644697 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 01:53:40.645153
1041 01:53:40.672668 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1042 01:53:40.678159 2D training succeed
1043 01:53:40.683805 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 01:53:40.684286 auto size-- 65535DDR cs0 size: 2048MB
1045 01:53:40.689383 DDR cs1 size: 2048MB
1046 01:53:40.689815 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 01:53:40.694953 cs0 DataBus test pass
1048 01:53:40.695381 cs1 DataBus test pass
1049 01:53:40.695785 cs0 AddrBus test pass
1050 01:53:40.700550 cs1 AddrBus test pass
1051 01:53:40.700979
1052 01:53:40.701385 100bdlr_step_size ps== 420
1053 01:53:40.701792 result report
1054 01:53:40.706126 boot times 0Enable ddr reg access
1055 01:53:40.713725 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 01:53:40.727154 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 01:53:41.299201 0.0;M3 CHK:0;cm4_sp_mode 0
1058 01:53:41.299793 MVN_1=0x00000000
1059 01:53:41.304618 MVN_2=0x00000000
1060 01:53:41.310380 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 01:53:41.310821 OPS=0x10
1062 01:53:41.311233 ring efuse init
1063 01:53:41.311635 chipver efuse init
1064 01:53:41.316010 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 01:53:41.321579 [0.018961 Inits done]
1066 01:53:41.322045 secure task start!
1067 01:53:41.322455 high task start!
1068 01:53:41.326154 low task start!
1069 01:53:41.326583 run into bl31
1070 01:53:41.332806 NOTICE: BL31: v1.3(release):4fc40b1
1071 01:53:41.340649 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 01:53:41.341087 NOTICE: BL31: G12A normal boot!
1073 01:53:41.366045 NOTICE: BL31: BL33 decompress pass
1074 01:53:41.371770 ERROR: Error initializing runtime service opteed_fast
1075 01:53:42.604682
1076 01:53:42.605268
1077 01:53:42.613146 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 01:53:42.613596
1079 01:53:42.614012 Model: Libre Computer AML-A311D-CC Alta
1080 01:53:42.821541 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 01:53:42.844937 DRAM: 2 GiB (effective 3.8 GiB)
1082 01:53:42.987867 Core: 408 devices, 31 uclasses, devicetree: separate
1083 01:53:42.993682 WDT: Not starting watchdog@f0d0
1084 01:53:43.025939 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 01:53:43.038444 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 01:53:43.043377 ** Bad device specification mmc 0 **
1087 01:53:43.053718 Card did not respond to voltage select! : -110
1088 01:53:43.061359 ** Bad device specification mmc 0 **
1089 01:53:43.061796 Couldn't find partition mmc 0
1090 01:53:43.069688 Card did not respond to voltage select! : -110
1091 01:53:43.075239 ** Bad device specification mmc 0 **
1092 01:53:43.075671 Couldn't find partition mmc 0
1093 01:53:43.080347 Error: could not access storage.
1094 01:53:43.423884 Net: eth0: ethernet@ff3f0000
1095 01:53:43.424528 starting USB...
1096 01:53:43.675696 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 01:53:43.676376 Starting the controller
1098 01:53:43.681700 USB XHCI 1.10
1099 01:53:45.236644 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 01:53:45.244970 scanning usb for storage devices... 0 Storage Device(s) found
1102 01:53:45.296486 Hit any key to stop autoboot: 1
1103 01:53:45.297265 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 01:53:45.297833 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 01:53:45.298291 Setting prompt string to ['=>']
1106 01:53:45.298757 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 01:53:45.312350 0
1108 01:53:45.313209 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 01:53:45.313675 Sending with 10 millisecond of delay
1111 01:53:46.448840 => setenv autoload no
1112 01:53:46.459627 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 01:53:46.464746 setenv autoload no
1114 01:53:46.465572 Sending with 10 millisecond of delay
1116 01:53:48.262940 => setenv initrd_high 0xffffffff
1117 01:53:48.273704 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 01:53:48.274633 setenv initrd_high 0xffffffff
1119 01:53:48.275449 Sending with 10 millisecond of delay
1121 01:53:49.893002 => setenv fdt_high 0xffffffff
1122 01:53:49.903911 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 01:53:49.904943 setenv fdt_high 0xffffffff
1124 01:53:49.905659 Sending with 10 millisecond of delay
1126 01:53:50.197840 => dhcp
1127 01:53:50.208747 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 01:53:50.209675 dhcp
1129 01:53:50.210215 Speed: 1000, full duplex
1130 01:53:50.210762 BOOTP broadcast 1
1131 01:53:50.217593 DHCP client bound to address 192.168.6.27 (9 ms)
1132 01:53:50.218416 Sending with 10 millisecond of delay
1134 01:53:51.896377 => setenv serverip 192.168.6.2
1135 01:53:51.907294 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 01:53:51.908190 setenv serverip 192.168.6.2
1137 01:53:51.908964 Sending with 10 millisecond of delay
1139 01:53:55.635349 => tftpboot 0x01080000 949480/tftp-deploy-mqde_a_w/kernel/uImage
1140 01:53:55.646249 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1141 01:53:55.647165 tftpboot 0x01080000 949480/tftp-deploy-mqde_a_w/kernel/uImage
1142 01:53:55.647660 Speed: 1000, full duplex
1143 01:53:55.648163 Using ethernet@ff3f0000 device
1144 01:53:55.649094 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 01:53:55.654512 Filename '949480/tftp-deploy-mqde_a_w/kernel/uImage'.
1146 01:53:55.658430 Load address: 0x1080000
1147 01:53:58.174247 Loading: *################################################## 36.1 MiB
1148 01:53:58.174934 14.3 MiB/s
1149 01:53:58.175419 done
1150 01:53:58.178604 Bytes transferred = 37878336 (241fa40 hex)
1151 01:53:58.179458 Sending with 10 millisecond of delay
1153 01:54:02.870516 => tftpboot 0x08000000 949480/tftp-deploy-mqde_a_w/ramdisk/ramdisk.cpio.gz.uboot
1154 01:54:02.881409 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1155 01:54:02.882474 tftpboot 0x08000000 949480/tftp-deploy-mqde_a_w/ramdisk/ramdisk.cpio.gz.uboot
1156 01:54:02.883080 Speed: 1000, full duplex
1157 01:54:02.883635 Using ethernet@ff3f0000 device
1158 01:54:02.884257 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 01:54:02.895876 Filename '949480/tftp-deploy-mqde_a_w/ramdisk/ramdisk.cpio.gz.uboot'.
1160 01:54:02.896510 Load address: 0x8000000
1161 01:54:09.720456 Loading: *#############################T #################### UDP wrong checksum 00000005 0000d008
1162 01:54:14.722509 T UDP wrong checksum 00000005 0000d008
1163 01:54:24.725622 T T UDP wrong checksum 00000005 0000d008
1164 01:54:27.727796 UDP wrong checksum 000000ff 000086c2
1165 01:54:27.739775 UDP wrong checksum 000000ff 00000fb5
1166 01:54:44.729093 T T T UDP wrong checksum 00000005 0000d008
1167 01:54:59.734880 T T T
1168 01:54:59.735598 Retry count exceeded; starting again
1170 01:54:59.737377 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1173 01:54:59.739760 end: 2.4 uboot-commands (duration 00:01:51) [common]
1175 01:54:59.741590 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1177 01:54:59.742962 end: 2 uboot-action (duration 00:01:51) [common]
1179 01:54:59.744988 Cleaning after the job
1180 01:54:59.745687 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/ramdisk
1181 01:54:59.747419 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/kernel
1182 01:54:59.774060 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/dtb
1183 01:54:59.775629 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/nfsrootfs
1184 01:54:59.892655 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949480/tftp-deploy-mqde_a_w/modules
1185 01:54:59.915687 start: 4.1 power-off (timeout 00:00:30) [common]
1186 01:54:59.916387 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1187 01:54:59.949969 >> OK - accepted request
1188 01:54:59.952002 Returned 0 in 0 seconds
1189 01:55:00.052915 end: 4.1 power-off (duration 00:00:00) [common]
1191 01:55:00.054790 start: 4.2 read-feedback (timeout 00:10:00) [common]
1192 01:55:00.056068 Listened to connection for namespace 'common' for up to 1s
1193 01:55:01.055803 Finalising connection for namespace 'common'
1194 01:55:01.056323 Disconnecting from shell: Finalise
1195 01:55:01.056587 =>
1196 01:55:01.157395 end: 4.2 read-feedback (duration 00:00:01) [common]
1197 01:55:01.158153 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949480
1198 01:55:03.874864 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949480
1199 01:55:03.875464 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.