Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:01:44.754664 lava-dispatcher, installed at version: 2024.01
2 02:01:44.755462 start: 0 validate
3 02:01:44.755963 Start time: 2024-11-07 02:01:44.755932+00:00 (UTC)
4 02:01:44.756570 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:01:44.757114 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:01:44.800300 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:01:44.800999 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 02:01:44.831397 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:01:44.832104 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:01:44.865258 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:01:44.865804 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:01:44.900254 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:01:44.900782 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
14 02:01:44.941592 validate duration: 0.19
16 02:01:44.942462 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:01:44.942792 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:01:44.943114 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:01:44.943717 Not decompressing ramdisk as can be used compressed.
20 02:01:44.944200 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 02:01:44.944493 saving as /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/ramdisk/initrd.cpio.gz
22 02:01:44.944769 total size: 5628140 (5 MB)
23 02:01:44.979624 progress 0 % (0 MB)
24 02:01:44.987428 progress 5 % (0 MB)
25 02:01:44.995841 progress 10 % (0 MB)
26 02:01:45.001764 progress 15 % (0 MB)
27 02:01:45.005921 progress 20 % (1 MB)
28 02:01:45.009631 progress 25 % (1 MB)
29 02:01:45.013793 progress 30 % (1 MB)
30 02:01:45.018018 progress 35 % (1 MB)
31 02:01:45.021738 progress 40 % (2 MB)
32 02:01:45.025917 progress 45 % (2 MB)
33 02:01:45.029799 progress 50 % (2 MB)
34 02:01:45.033985 progress 55 % (2 MB)
35 02:01:45.038118 progress 60 % (3 MB)
36 02:01:45.041782 progress 65 % (3 MB)
37 02:01:45.045860 progress 70 % (3 MB)
38 02:01:45.049555 progress 75 % (4 MB)
39 02:01:45.053651 progress 80 % (4 MB)
40 02:01:45.057338 progress 85 % (4 MB)
41 02:01:45.061423 progress 90 % (4 MB)
42 02:01:45.065524 progress 95 % (5 MB)
43 02:01:45.068920 progress 100 % (5 MB)
44 02:01:45.069583 5 MB downloaded in 0.12 s (43.01 MB/s)
45 02:01:45.070139 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:01:45.071026 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:01:45.071316 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:01:45.071583 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:01:45.072092 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/kernel/Image
51 02:01:45.072360 saving as /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/kernel/Image
52 02:01:45.072569 total size: 37878272 (36 MB)
53 02:01:45.072778 No compression specified
54 02:01:45.111808 progress 0 % (0 MB)
55 02:01:45.136441 progress 5 % (1 MB)
56 02:01:45.161564 progress 10 % (3 MB)
57 02:01:45.186113 progress 15 % (5 MB)
58 02:01:45.210992 progress 20 % (7 MB)
59 02:01:45.235269 progress 25 % (9 MB)
60 02:01:45.259808 progress 30 % (10 MB)
61 02:01:45.284344 progress 35 % (12 MB)
62 02:01:45.309073 progress 40 % (14 MB)
63 02:01:45.333823 progress 45 % (16 MB)
64 02:01:45.358179 progress 50 % (18 MB)
65 02:01:45.383647 progress 55 % (19 MB)
66 02:01:45.408409 progress 60 % (21 MB)
67 02:01:45.433845 progress 65 % (23 MB)
68 02:01:45.458520 progress 70 % (25 MB)
69 02:01:45.482715 progress 75 % (27 MB)
70 02:01:45.508476 progress 80 % (28 MB)
71 02:01:45.536844 progress 85 % (30 MB)
72 02:01:45.561666 progress 90 % (32 MB)
73 02:01:45.586470 progress 95 % (34 MB)
74 02:01:45.610392 progress 100 % (36 MB)
75 02:01:45.611171 36 MB downloaded in 0.54 s (67.07 MB/s)
76 02:01:45.611658 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:01:45.612530 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:01:45.612810 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:01:45.613075 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:01:45.613554 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 02:01:45.613829 saving as /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/dtb/meson-g12b-a311d-libretech-cc.dtb
83 02:01:45.614035 total size: 54703 (0 MB)
84 02:01:45.614241 No compression specified
85 02:01:45.647242 progress 59 % (0 MB)
86 02:01:45.648128 progress 100 % (0 MB)
87 02:01:45.648688 0 MB downloaded in 0.03 s (1.51 MB/s)
88 02:01:45.649151 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:01:45.649959 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:01:45.650222 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:01:45.650484 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:01:45.650947 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 02:01:45.651189 saving as /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/nfsrootfs/full.rootfs.tar
95 02:01:45.651394 total size: 474398908 (452 MB)
96 02:01:45.651604 Using unxz to decompress xz
97 02:01:45.690783 progress 0 % (0 MB)
98 02:01:46.797357 progress 5 % (22 MB)
99 02:01:48.291341 progress 10 % (45 MB)
100 02:01:48.758963 progress 15 % (67 MB)
101 02:01:49.598736 progress 20 % (90 MB)
102 02:01:50.150196 progress 25 % (113 MB)
103 02:01:50.525996 progress 30 % (135 MB)
104 02:01:51.141416 progress 35 % (158 MB)
105 02:01:52.076885 progress 40 % (181 MB)
106 02:01:52.946151 progress 45 % (203 MB)
107 02:01:53.609816 progress 50 % (226 MB)
108 02:01:54.271167 progress 55 % (248 MB)
109 02:01:55.502548 progress 60 % (271 MB)
110 02:01:57.006456 progress 65 % (294 MB)
111 02:01:58.680213 progress 70 % (316 MB)
112 02:02:01.792621 progress 75 % (339 MB)
113 02:02:04.276444 progress 80 % (361 MB)
114 02:02:07.245690 progress 85 % (384 MB)
115 02:02:10.555544 progress 90 % (407 MB)
116 02:02:13.814274 progress 95 % (429 MB)
117 02:02:17.042789 progress 100 % (452 MB)
118 02:02:17.054441 452 MB downloaded in 31.40 s (14.41 MB/s)
119 02:02:17.055082 end: 1.4.1 http-download (duration 00:00:31) [common]
121 02:02:17.056135 end: 1.4 download-retry (duration 00:00:31) [common]
122 02:02:17.056468 start: 1.5 download-retry (timeout 00:09:28) [common]
123 02:02:17.056751 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 02:02:17.057385 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-15/modules.tar.xz
125 02:02:17.057793 saving as /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/modules/modules.tar
126 02:02:17.058043 total size: 11769360 (11 MB)
127 02:02:17.058274 Using unxz to decompress xz
128 02:02:17.100837 progress 0 % (0 MB)
129 02:02:17.168137 progress 5 % (0 MB)
130 02:02:17.263354 progress 10 % (1 MB)
131 02:02:17.393952 progress 15 % (1 MB)
132 02:02:17.520966 progress 20 % (2 MB)
133 02:02:17.629223 progress 25 % (2 MB)
134 02:02:17.741790 progress 30 % (3 MB)
135 02:02:17.838938 progress 35 % (3 MB)
136 02:02:17.921581 progress 40 % (4 MB)
137 02:02:18.002259 progress 45 % (5 MB)
138 02:02:18.090542 progress 50 % (5 MB)
139 02:02:18.174763 progress 55 % (6 MB)
140 02:02:18.266989 progress 60 % (6 MB)
141 02:02:18.351254 progress 65 % (7 MB)
142 02:02:18.436123 progress 70 % (7 MB)
143 02:02:18.524624 progress 75 % (8 MB)
144 02:02:18.616665 progress 80 % (9 MB)
145 02:02:18.706169 progress 85 % (9 MB)
146 02:02:18.792854 progress 90 % (10 MB)
147 02:02:18.874154 progress 95 % (10 MB)
148 02:02:18.953303 progress 100 % (11 MB)
149 02:02:18.964442 11 MB downloaded in 1.91 s (5.89 MB/s)
150 02:02:18.965061 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:02:18.965885 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:02:18.966149 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 02:02:18.966410 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 02:02:35.069346 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/949556/extract-nfsrootfs-oqy9c88v
156 02:02:35.069955 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 02:02:35.070281 start: 1.6.2 lava-overlay (timeout 00:09:10) [common]
158 02:02:35.070998 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih
159 02:02:35.071521 makedir: /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin
160 02:02:35.072133 makedir: /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/tests
161 02:02:35.072576 makedir: /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/results
162 02:02:35.072935 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-add-keys
163 02:02:35.073580 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-add-sources
164 02:02:35.074232 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-background-process-start
165 02:02:35.074779 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-background-process-stop
166 02:02:35.075331 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-common-functions
167 02:02:35.075864 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-echo-ipv4
168 02:02:35.076440 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-install-packages
169 02:02:35.076963 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-installed-packages
170 02:02:35.077532 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-os-build
171 02:02:35.078056 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-probe-channel
172 02:02:35.078565 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-probe-ip
173 02:02:35.079096 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-target-ip
174 02:02:35.079605 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-target-mac
175 02:02:35.080347 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-target-storage
176 02:02:35.080874 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-test-case
177 02:02:35.081444 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-test-event
178 02:02:35.081994 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-test-feedback
179 02:02:35.082494 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-test-raise
180 02:02:35.083247 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-test-reference
181 02:02:35.083760 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-test-runner
182 02:02:35.084303 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-test-set
183 02:02:35.084829 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-test-shell
184 02:02:35.085340 Updating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-install-packages (oe)
185 02:02:35.085884 Updating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/bin/lava-installed-packages (oe)
186 02:02:35.086396 Creating /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/environment
187 02:02:35.086881 LAVA metadata
188 02:02:35.087154 - LAVA_JOB_ID=949556
189 02:02:35.087370 - LAVA_DISPATCHER_IP=192.168.6.2
190 02:02:35.087758 start: 1.6.2.1 ssh-authorize (timeout 00:09:10) [common]
191 02:02:35.088828 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 02:02:35.089165 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:10) [common]
193 02:02:35.089374 skipped lava-vland-overlay
194 02:02:35.089615 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 02:02:35.089873 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:10) [common]
196 02:02:35.090094 skipped lava-multinode-overlay
197 02:02:35.090337 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 02:02:35.090586 start: 1.6.2.4 test-definition (timeout 00:09:10) [common]
199 02:02:35.090840 Loading test definitions
200 02:02:35.091123 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:10) [common]
201 02:02:35.091341 Using /lava-949556 at stage 0
202 02:02:35.092579 uuid=949556_1.6.2.4.1 testdef=None
203 02:02:35.092919 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 02:02:35.093185 start: 1.6.2.4.2 test-overlay (timeout 00:09:10) [common]
205 02:02:35.095130 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 02:02:35.095944 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:10) [common]
208 02:02:35.098260 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 02:02:35.099118 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:10) [common]
211 02:02:35.101361 runner path: /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 949556_1.6.2.4.1
212 02:02:35.102070 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 02:02:35.102845 Creating lava-test-runner.conf files
215 02:02:35.103048 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949556/lava-overlay-71c21pih/lava-949556/0 for stage 0
216 02:02:35.103416 - 0_v4l2-decoder-conformance-vp9
217 02:02:35.103791 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 02:02:35.104109 start: 1.6.2.5 compress-overlay (timeout 00:09:10) [common]
219 02:02:35.126948 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 02:02:35.127397 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
221 02:02:35.127661 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 02:02:35.127932 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 02:02:35.128244 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
224 02:02:35.803697 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 02:02:35.804183 start: 1.6.4 extract-modules (timeout 00:09:09) [common]
226 02:02:35.804452 extracting modules file /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949556/extract-nfsrootfs-oqy9c88v
227 02:02:37.201846 extracting modules file /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949556/extract-overlay-ramdisk-0ey4d0b5/ramdisk
228 02:02:38.613649 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 02:02:38.614134 start: 1.6.5 apply-overlay-tftp (timeout 00:09:06) [common]
230 02:02:38.614426 [common] Applying overlay to NFS
231 02:02:38.614654 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949556/compress-overlay-ogdgzsy5/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949556/extract-nfsrootfs-oqy9c88v
232 02:02:38.643790 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 02:02:38.644238 start: 1.6.6 prepare-kernel (timeout 00:09:06) [common]
234 02:02:38.644534 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:06) [common]
235 02:02:38.644775 Converting downloaded kernel to a uImage
236 02:02:38.645096 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/kernel/Image /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/kernel/uImage
237 02:02:39.038594 output: Image Name:
238 02:02:39.039021 output: Created: Thu Nov 7 02:02:38 2024
239 02:02:39.039251 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 02:02:39.039468 output: Data Size: 37878272 Bytes = 36990.50 KiB = 36.12 MiB
241 02:02:39.039674 output: Load Address: 01080000
242 02:02:39.039879 output: Entry Point: 01080000
243 02:02:39.040118 output:
244 02:02:39.040465 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 02:02:39.040745 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 02:02:39.041023 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 02:02:39.041286 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 02:02:39.041558 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 02:02:39.041833 Building ramdisk /var/lib/lava/dispatcher/tmp/949556/extract-overlay-ramdisk-0ey4d0b5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949556/extract-overlay-ramdisk-0ey4d0b5/ramdisk
250 02:02:41.266297 >> 173435 blocks
251 02:02:48.944724 Adding RAMdisk u-boot header.
252 02:02:48.945165 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949556/extract-overlay-ramdisk-0ey4d0b5/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949556/extract-overlay-ramdisk-0ey4d0b5/ramdisk.cpio.gz.uboot
253 02:02:49.196698 output: Image Name:
254 02:02:49.197122 output: Created: Thu Nov 7 02:02:48 2024
255 02:02:49.197597 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 02:02:49.198061 output: Data Size: 24147399 Bytes = 23581.44 KiB = 23.03 MiB
257 02:02:49.198516 output: Load Address: 00000000
258 02:02:49.198960 output: Entry Point: 00000000
259 02:02:49.199402 output:
260 02:02:49.200657 rename /var/lib/lava/dispatcher/tmp/949556/extract-overlay-ramdisk-0ey4d0b5/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/ramdisk/ramdisk.cpio.gz.uboot
261 02:02:49.201453 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 02:02:49.202072 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 02:02:49.202681 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 02:02:49.203197 No LXC device requested
265 02:02:49.203761 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 02:02:49.204432 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 02:02:49.205003 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 02:02:49.205463 Checking files for TFTP limit of 4294967296 bytes.
269 02:02:49.208443 end: 1 tftp-deploy (duration 00:01:04) [common]
270 02:02:49.209089 start: 2 uboot-action (timeout 00:05:00) [common]
271 02:02:49.209684 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 02:02:49.210248 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 02:02:49.210823 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 02:02:49.211420 Using kernel file from prepare-kernel: 949556/tftp-deploy-5vn5aopv/kernel/uImage
275 02:02:49.212148 substitutions:
276 02:02:49.212614 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 02:02:49.213065 - {DTB_ADDR}: 0x01070000
278 02:02:49.213512 - {DTB}: 949556/tftp-deploy-5vn5aopv/dtb/meson-g12b-a311d-libretech-cc.dtb
279 02:02:49.213956 - {INITRD}: 949556/tftp-deploy-5vn5aopv/ramdisk/ramdisk.cpio.gz.uboot
280 02:02:49.214399 - {KERNEL_ADDR}: 0x01080000
281 02:02:49.214836 - {KERNEL}: 949556/tftp-deploy-5vn5aopv/kernel/uImage
282 02:02:49.215274 - {LAVA_MAC}: None
283 02:02:49.215753 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/949556/extract-nfsrootfs-oqy9c88v
284 02:02:49.216239 - {NFS_SERVER_IP}: 192.168.6.2
285 02:02:49.216679 - {PRESEED_CONFIG}: None
286 02:02:49.217113 - {PRESEED_LOCAL}: None
287 02:02:49.217547 - {RAMDISK_ADDR}: 0x08000000
288 02:02:49.217976 - {RAMDISK}: 949556/tftp-deploy-5vn5aopv/ramdisk/ramdisk.cpio.gz.uboot
289 02:02:49.218410 - {ROOT_PART}: None
290 02:02:49.218843 - {ROOT}: None
291 02:02:49.219271 - {SERVER_IP}: 192.168.6.2
292 02:02:49.219703 - {TEE_ADDR}: 0x83000000
293 02:02:49.220166 - {TEE}: None
294 02:02:49.220603 Parsed boot commands:
295 02:02:49.221024 - setenv autoload no
296 02:02:49.221456 - setenv initrd_high 0xffffffff
297 02:02:49.221886 - setenv fdt_high 0xffffffff
298 02:02:49.222317 - dhcp
299 02:02:49.222746 - setenv serverip 192.168.6.2
300 02:02:49.223173 - tftpboot 0x01080000 949556/tftp-deploy-5vn5aopv/kernel/uImage
301 02:02:49.223605 - tftpboot 0x08000000 949556/tftp-deploy-5vn5aopv/ramdisk/ramdisk.cpio.gz.uboot
302 02:02:49.224064 - tftpboot 0x01070000 949556/tftp-deploy-5vn5aopv/dtb/meson-g12b-a311d-libretech-cc.dtb
303 02:02:49.224502 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/949556/extract-nfsrootfs-oqy9c88v,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 02:02:49.224952 - bootm 0x01080000 0x08000000 0x01070000
305 02:02:49.225515 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 02:02:49.227175 start: 2.3 connect-device (timeout 00:05:00) [common]
308 02:02:49.227644 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 02:02:49.243038 Setting prompt string to ['lava-test: # ']
310 02:02:49.244687 end: 2.3 connect-device (duration 00:00:00) [common]
311 02:02:49.245393 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 02:02:49.246347 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 02:02:49.247150 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 02:02:49.248484 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 02:02:49.286121 >> OK - accepted request
316 02:02:49.288104 Returned 0 in 0 seconds
317 02:02:49.389359 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 02:02:49.391185 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 02:02:49.391820 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 02:02:49.392458 Setting prompt string to ['Hit any key to stop autoboot']
322 02:02:49.392983 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 02:02:49.394711 Trying 192.168.56.21...
324 02:02:49.395250 Connected to conserv1.
325 02:02:49.395732 Escape character is '^]'.
326 02:02:49.396340
327 02:02:49.396844 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 02:02:49.397348
329 02:03:00.798774 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 02:03:00.799450 bl2_stage_init 0x01
331 02:03:00.799912 bl2_stage_init 0x81
332 02:03:00.804086 hw id: 0x0000 - pwm id 0x01
333 02:03:00.804582 bl2_stage_init 0xc1
334 02:03:00.805021 bl2_stage_init 0x02
335 02:03:00.805455
336 02:03:00.809645 L0:00000000
337 02:03:00.810122 L1:20000703
338 02:03:00.810557 L2:00008067
339 02:03:00.810989 L3:14000000
340 02:03:00.815322 B2:00402000
341 02:03:00.815787 B1:e0f83180
342 02:03:00.816268
343 02:03:00.816706 TE: 58124
344 02:03:00.817145
345 02:03:00.820871 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 02:03:00.821345
347 02:03:00.821783 Board ID = 1
348 02:03:00.826559 Set A53 clk to 24M
349 02:03:00.827025 Set A73 clk to 24M
350 02:03:00.827457 Set clk81 to 24M
351 02:03:00.832075 A53 clk: 1200 MHz
352 02:03:00.832538 A73 clk: 1200 MHz
353 02:03:00.832967 CLK81: 166.6M
354 02:03:00.833392 smccc: 00012a92
355 02:03:00.837642 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 02:03:00.843319 board id: 1
357 02:03:00.849305 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 02:03:00.859696 fw parse done
359 02:03:00.865701 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 02:03:00.908292 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 02:03:00.919196 PIEI prepare done
362 02:03:00.919654 fastboot data load
363 02:03:00.920140 fastboot data verify
364 02:03:00.924827 verify result: 266
365 02:03:00.930415 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 02:03:00.930893 LPDDR4 probe
367 02:03:00.931325 ddr clk to 1584MHz
368 02:03:00.938394 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 02:03:00.975720
370 02:03:00.976249 dmc_version 0001
371 02:03:00.982408 Check phy result
372 02:03:00.988296 INFO : End of CA training
373 02:03:00.988763 INFO : End of initialization
374 02:03:00.993844 INFO : Training has run successfully!
375 02:03:00.994303 Check phy result
376 02:03:00.999435 INFO : End of initialization
377 02:03:00.999891 INFO : End of read enable training
378 02:03:01.005117 INFO : End of fine write leveling
379 02:03:01.010685 INFO : End of Write leveling coarse delay
380 02:03:01.011144 INFO : Training has run successfully!
381 02:03:01.011576 Check phy result
382 02:03:01.016387 INFO : End of initialization
383 02:03:01.016851 INFO : End of read dq deskew training
384 02:03:01.021823 INFO : End of MPR read delay center optimization
385 02:03:01.027493 INFO : End of write delay center optimization
386 02:03:01.033158 INFO : End of read delay center optimization
387 02:03:01.033634 INFO : End of max read latency training
388 02:03:01.038698 INFO : Training has run successfully!
389 02:03:01.039179 1D training succeed
390 02:03:01.047801 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 02:03:01.095488 Check phy result
392 02:03:01.096018 INFO : End of initialization
393 02:03:01.118034 INFO : End of 2D read delay Voltage center optimization
394 02:03:01.138401 INFO : End of 2D read delay Voltage center optimization
395 02:03:01.190377 INFO : End of 2D write delay Voltage center optimization
396 02:03:01.239813 INFO : End of 2D write delay Voltage center optimization
397 02:03:01.245359 INFO : Training has run successfully!
398 02:03:01.245865
399 02:03:01.246322 channel==0
400 02:03:01.250890 RxClkDly_Margin_A0==88 ps 9
401 02:03:01.251388 TxDqDly_Margin_A0==98 ps 10
402 02:03:01.256455 RxClkDly_Margin_A1==88 ps 9
403 02:03:01.256940 TxDqDly_Margin_A1==98 ps 10
404 02:03:01.257388 TrainedVREFDQ_A0==74
405 02:03:01.262003 TrainedVREFDQ_A1==75
406 02:03:01.262491 VrefDac_Margin_A0==24
407 02:03:01.262937 DeviceVref_Margin_A0==40
408 02:03:01.267753 VrefDac_Margin_A1==25
409 02:03:01.268273 DeviceVref_Margin_A1==39
410 02:03:01.268718
411 02:03:01.269161
412 02:03:01.273435 channel==1
413 02:03:01.273915 RxClkDly_Margin_A0==98 ps 10
414 02:03:01.274359 TxDqDly_Margin_A0==98 ps 10
415 02:03:01.278896 RxClkDly_Margin_A1==98 ps 10
416 02:03:01.279378 TxDqDly_Margin_A1==88 ps 9
417 02:03:01.284503 TrainedVREFDQ_A0==77
418 02:03:01.284982 TrainedVREFDQ_A1==77
419 02:03:01.285426 VrefDac_Margin_A0==22
420 02:03:01.290091 DeviceVref_Margin_A0==37
421 02:03:01.290571 VrefDac_Margin_A1==24
422 02:03:01.295625 DeviceVref_Margin_A1==37
423 02:03:01.296131
424 02:03:01.296583 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 02:03:01.301344
426 02:03:01.329378 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 02:03:01.329938 2D training succeed
428 02:03:01.334846 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 02:03:01.340456 auto size-- 65535DDR cs0 size: 2048MB
430 02:03:01.340989 DDR cs1 size: 2048MB
431 02:03:01.346021 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 02:03:01.346551 cs0 DataBus test pass
433 02:03:01.351635 cs1 DataBus test pass
434 02:03:01.352200 cs0 AddrBus test pass
435 02:03:01.352654 cs1 AddrBus test pass
436 02:03:01.353128
437 02:03:01.357361 100bdlr_step_size ps== 420
438 02:03:01.357902 result report
439 02:03:01.362839 boot times 0Enable ddr reg access
440 02:03:01.368327 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 02:03:01.381731 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 02:03:01.955838 0.0;M3 CHK:0;cm4_sp_mode 0
443 02:03:01.956561 MVN_1=0x00000000
444 02:03:01.960948 MVN_2=0x00000000
445 02:03:01.966645 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 02:03:01.967140 OPS=0x10
447 02:03:01.967591 ring efuse init
448 02:03:01.968061 chipver efuse init
449 02:03:01.972434 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 02:03:01.977894 [0.018961 Inits done]
451 02:03:01.978395 secure task start!
452 02:03:01.978836 high task start!
453 02:03:01.982687 low task start!
454 02:03:01.983248 run into bl31
455 02:03:01.989218 NOTICE: BL31: v1.3(release):4fc40b1
456 02:03:01.996936 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 02:03:01.997455 NOTICE: BL31: G12A normal boot!
458 02:03:02.022840 NOTICE: BL31: BL33 decompress pass
459 02:03:02.028564 ERROR: Error initializing runtime service opteed_fast
460 02:03:03.261538
461 02:03:03.262222
462 02:03:03.269829 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 02:03:03.270335
464 02:03:03.270815 Model: Libre Computer AML-A311D-CC Alta
465 02:03:03.478374 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 02:03:03.501864 DRAM: 2 GiB (effective 3.8 GiB)
467 02:03:03.644954 Core: 408 devices, 31 uclasses, devicetree: separate
468 02:03:03.650551 WDT: Not starting watchdog@f0d0
469 02:03:03.682771 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 02:03:03.695182 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 02:03:03.700347 ** Bad device specification mmc 0 **
472 02:03:03.710595 Card did not respond to voltage select! : -110
473 02:03:03.718286 ** Bad device specification mmc 0 **
474 02:03:03.718787 Couldn't find partition mmc 0
475 02:03:03.726535 Card did not respond to voltage select! : -110
476 02:03:03.732043 ** Bad device specification mmc 0 **
477 02:03:03.732542 Couldn't find partition mmc 0
478 02:03:03.737241 Error: could not access storage.
479 02:03:04.999167 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
480 02:03:04.999616 bl2_stage_init 0x81
481 02:03:05.004555 hw id: 0x0000 - pwm id 0x01
482 02:03:05.004967 bl2_stage_init 0xc1
483 02:03:05.005211 bl2_stage_init 0x02
484 02:03:05.005435
485 02:03:05.010252 L0:00000000
486 02:03:05.010628 L1:20000703
487 02:03:05.010856 L2:00008067
488 02:03:05.011064 L3:14000000
489 02:03:05.011276 B2:00402000
490 02:03:05.013147 B1:e0f83180
491 02:03:05.013596
492 02:03:05.013853 TE: 58150
493 02:03:05.014064
494 02:03:05.024157 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 02:03:05.024539
496 02:03:05.024773 Board ID = 1
497 02:03:05.024996 Set A53 clk to 24M
498 02:03:05.025204 Set A73 clk to 24M
499 02:03:05.029797 Set clk81 to 24M
500 02:03:05.030280 A53 clk: 1200 MHz
501 02:03:05.030625 A73 clk: 1200 MHz
502 02:03:05.035612 CLK81: 166.6M
503 02:03:05.036151 smccc: 00012aab
504 02:03:05.041094 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 02:03:05.041517 board id: 1
506 02:03:05.049762 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 02:03:05.060692 fw parse done
508 02:03:05.066408 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 02:03:05.108760 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 02:03:05.119630 PIEI prepare done
511 02:03:05.119973 fastboot data load
512 02:03:05.120239 fastboot data verify
513 02:03:05.125224 verify result: 266
514 02:03:05.130904 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 02:03:05.131257 LPDDR4 probe
516 02:03:05.131488 ddr clk to 1584MHz
517 02:03:05.138824 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 02:03:05.176268
519 02:03:05.176674 dmc_version 0001
520 02:03:05.183157 Check phy result
521 02:03:05.190082 INFO : End of CA training
522 02:03:05.191285 INFO : End of initialization
523 02:03:05.194399 INFO : Training has run successfully!
524 02:03:05.194856 Check phy result
525 02:03:05.200191 INFO : End of initialization
526 02:03:05.200834 INFO : End of read enable training
527 02:03:05.203185 INFO : End of fine write leveling
528 02:03:05.208874 INFO : End of Write leveling coarse delay
529 02:03:05.214387 INFO : Training has run successfully!
530 02:03:05.214762 Check phy result
531 02:03:05.215006 INFO : End of initialization
532 02:03:05.220143 INFO : End of read dq deskew training
533 02:03:05.225589 INFO : End of MPR read delay center optimization
534 02:03:05.226165 INFO : End of write delay center optimization
535 02:03:05.231380 INFO : End of read delay center optimization
536 02:03:05.236849 INFO : End of max read latency training
537 02:03:05.237272 INFO : Training has run successfully!
538 02:03:05.242444 1D training succeed
539 02:03:05.249135 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 02:03:05.295966 Check phy result
541 02:03:05.296466 INFO : End of initialization
542 02:03:05.317916 INFO : End of 2D read delay Voltage center optimization
543 02:03:05.338045 INFO : End of 2D read delay Voltage center optimization
544 02:03:05.390285 INFO : End of 2D write delay Voltage center optimization
545 02:03:05.440062 INFO : End of 2D write delay Voltage center optimization
546 02:03:05.445049 INFO : Training has run successfully!
547 02:03:05.445629
548 02:03:05.446100 channel==0
549 02:03:05.451151 RxClkDly_Margin_A0==88 ps 9
550 02:03:05.454283 TxDqDly_Margin_A0==98 ps 10
551 02:03:05.455238 RxClkDly_Margin_A1==88 ps 9
552 02:03:05.455774 TxDqDly_Margin_A1==98 ps 10
553 02:03:05.459552 TrainedVREFDQ_A0==74
554 02:03:05.460287 TrainedVREFDQ_A1==74
555 02:03:05.460794 VrefDac_Margin_A0==25
556 02:03:05.465177 DeviceVref_Margin_A0==40
557 02:03:05.465792 VrefDac_Margin_A1==23
558 02:03:05.471035 DeviceVref_Margin_A1==40
559 02:03:05.471805
560 02:03:05.472501
561 02:03:05.473092 channel==1
562 02:03:05.473674 RxClkDly_Margin_A0==98 ps 10
563 02:03:05.476397 TxDqDly_Margin_A0==98 ps 10
564 02:03:05.476801 RxClkDly_Margin_A1==88 ps 9
565 02:03:05.481864 TxDqDly_Margin_A1==88 ps 9
566 02:03:05.482328 TrainedVREFDQ_A0==77
567 02:03:05.482592 TrainedVREFDQ_A1==77
568 02:03:05.487478 VrefDac_Margin_A0==22
569 02:03:05.487939 DeviceVref_Margin_A0==37
570 02:03:05.493283 VrefDac_Margin_A1==24
571 02:03:05.493800 DeviceVref_Margin_A1==37
572 02:03:05.494082
573 02:03:05.498689 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 02:03:05.499076
575 02:03:05.526712 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
576 02:03:05.532599 2D training succeed
577 02:03:05.538049 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 02:03:05.538459 auto size-- 65535DDR cs0 size: 2048MB
579 02:03:05.543560 DDR cs1 size: 2048MB
580 02:03:05.543964 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 02:03:05.549013 cs0 DataBus test pass
582 02:03:05.549418 cs1 DataBus test pass
583 02:03:05.549667 cs0 AddrBus test pass
584 02:03:05.554747 cs1 AddrBus test pass
585 02:03:05.555141
586 02:03:05.555368 100bdlr_step_size ps== 420
587 02:03:05.555575 result report
588 02:03:05.560244 boot times 0Enable ddr reg access
589 02:03:05.567923 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 02:03:05.581379 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 02:03:06.154552 0.0;M3 CHK:0;cm4_sp_mode 0
592 02:03:06.155252 MVN_1=0x00000000
593 02:03:06.159901 MVN_2=0x00000000
594 02:03:06.165549 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 02:03:06.166161 OPS=0x10
596 02:03:06.166689 ring efuse init
597 02:03:06.167140 chipver efuse init
598 02:03:06.173847 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 02:03:06.174212 [0.018960 Inits done]
600 02:03:06.181415 secure task start!
601 02:03:06.181766 high task start!
602 02:03:06.181986 low task start!
603 02:03:06.182195 run into bl31
604 02:03:06.188099 NOTICE: BL31: v1.3(release):4fc40b1
605 02:03:06.196057 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 02:03:06.196409 NOTICE: BL31: G12A normal boot!
607 02:03:06.221527 NOTICE: BL31: BL33 decompress pass
608 02:03:06.226964 ERROR: Error initializing runtime service opteed_fast
609 02:03:07.459932
610 02:03:07.460722
611 02:03:07.468322 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 02:03:07.468933
613 02:03:07.469451 Model: Libre Computer AML-A311D-CC Alta
614 02:03:07.676649 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 02:03:07.700126 DRAM: 2 GiB (effective 3.8 GiB)
616 02:03:07.843306 Core: 408 devices, 31 uclasses, devicetree: separate
617 02:03:07.849142 WDT: Not starting watchdog@f0d0
618 02:03:07.881325 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 02:03:07.893678 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 02:03:07.898746 ** Bad device specification mmc 0 **
621 02:03:07.909069 Card did not respond to voltage select! : -110
622 02:03:07.916704 ** Bad device specification mmc 0 **
623 02:03:07.917100 Couldn't find partition mmc 0
624 02:03:07.924915 Card did not respond to voltage select! : -110
625 02:03:07.930728 ** Bad device specification mmc 0 **
626 02:03:07.931403 Couldn't find partition mmc 0
627 02:03:07.935625 Error: could not access storage.
628 02:03:08.278157 Net: eth0: ethernet@ff3f0000
629 02:03:08.278843 starting USB...
630 02:03:08.529716 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 02:03:08.530119 Starting the controller
632 02:03:08.535941 USB XHCI 1.10
633 02:03:10.248985 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
634 02:03:10.249423 bl2_stage_init 0x01
635 02:03:10.249648 bl2_stage_init 0x81
636 02:03:10.254554 hw id: 0x0000 - pwm id 0x01
637 02:03:10.255081 bl2_stage_init 0xc1
638 02:03:10.255498 bl2_stage_init 0x02
639 02:03:10.255892
640 02:03:10.260148 L0:00000000
641 02:03:10.260618 L1:20000703
642 02:03:10.261022 L2:00008067
643 02:03:10.261419 L3:14000000
644 02:03:10.265702 B2:00402000
645 02:03:10.266141 B1:e0f83180
646 02:03:10.266537
647 02:03:10.266933 TE: 58167
648 02:03:10.267327
649 02:03:10.271282 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 02:03:10.271716
651 02:03:10.272145 Board ID = 1
652 02:03:10.276912 Set A53 clk to 24M
653 02:03:10.277370 Set A73 clk to 24M
654 02:03:10.277769 Set clk81 to 24M
655 02:03:10.282485 A53 clk: 1200 MHz
656 02:03:10.282912 A73 clk: 1200 MHz
657 02:03:10.283317 CLK81: 166.6M
658 02:03:10.283711 smccc: 00012abd
659 02:03:10.288123 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 02:03:10.293703 board id: 1
661 02:03:10.299559 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 02:03:10.310620 fw parse done
663 02:03:10.316465 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 02:03:10.358952 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 02:03:10.369821 PIEI prepare done
666 02:03:10.370286 fastboot data load
667 02:03:10.370688 fastboot data verify
668 02:03:10.375477 verify result: 266
669 02:03:10.381082 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 02:03:10.381525 LPDDR4 probe
671 02:03:10.381921 ddr clk to 1584MHz
672 02:03:10.388979 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 02:03:10.426358
674 02:03:10.426887 dmc_version 0001
675 02:03:10.432953 Check phy result
676 02:03:10.438881 INFO : End of CA training
677 02:03:10.439327 INFO : End of initialization
678 02:03:10.444465 INFO : Training has run successfully!
679 02:03:10.444918 Check phy result
680 02:03:10.449996 INFO : End of initialization
681 02:03:10.450443 INFO : End of read enable training
682 02:03:10.453340 INFO : End of fine write leveling
683 02:03:10.458942 INFO : End of Write leveling coarse delay
684 02:03:10.464661 INFO : Training has run successfully!
685 02:03:10.465109 Check phy result
686 02:03:10.465505 INFO : End of initialization
687 02:03:10.470143 INFO : End of read dq deskew training
688 02:03:10.475743 INFO : End of MPR read delay center optimization
689 02:03:10.476208 INFO : End of write delay center optimization
690 02:03:10.481405 INFO : End of read delay center optimization
691 02:03:10.486979 INFO : End of max read latency training
692 02:03:10.487421 INFO : Training has run successfully!
693 02:03:10.492619 1D training succeed
694 02:03:10.498484 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 02:03:10.546070 Check phy result
696 02:03:10.546565 INFO : End of initialization
697 02:03:10.567760 INFO : End of 2D read delay Voltage center optimization
698 02:03:10.587907 INFO : End of 2D read delay Voltage center optimization
699 02:03:10.640078 INFO : End of 2D write delay Voltage center optimization
700 02:03:10.693860 INFO : End of 2D write delay Voltage center optimization
701 02:03:10.694964 INFO : Training has run successfully!
702 02:03:10.695442
703 02:03:10.695850 channel==0
704 02:03:10.700560 RxClkDly_Margin_A0==88 ps 9
705 02:03:10.701102 TxDqDly_Margin_A0==98 ps 10
706 02:03:10.706236 RxClkDly_Margin_A1==88 ps 9
707 02:03:10.706790 TxDqDly_Margin_A1==98 ps 10
708 02:03:10.707208 TrainedVREFDQ_A0==74
709 02:03:10.711800 TrainedVREFDQ_A1==74
710 02:03:10.712332 VrefDac_Margin_A0==25
711 02:03:10.712739 DeviceVref_Margin_A0==40
712 02:03:10.717392 VrefDac_Margin_A1==25
713 02:03:10.717913 DeviceVref_Margin_A1==40
714 02:03:10.718317
715 02:03:10.718714
716 02:03:10.722959 channel==1
717 02:03:10.723437 RxClkDly_Margin_A0==98 ps 10
718 02:03:10.723834 TxDqDly_Margin_A0==98 ps 10
719 02:03:10.728570 RxClkDly_Margin_A1==88 ps 9
720 02:03:10.729096 TxDqDly_Margin_A1==98 ps 10
721 02:03:10.734150 TrainedVREFDQ_A0==77
722 02:03:10.734634 TrainedVREFDQ_A1==77
723 02:03:10.735036 VrefDac_Margin_A0==22
724 02:03:10.739773 DeviceVref_Margin_A0==37
725 02:03:10.740281 VrefDac_Margin_A1==24
726 02:03:10.745361 DeviceVref_Margin_A1==37
727 02:03:10.745856
728 02:03:10.746257 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 02:03:10.750958
730 02:03:10.779040 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
731 02:03:10.779721 2D training succeed
732 02:03:10.784672 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 02:03:10.790333 auto size-- 65535DDR cs0 size: 2048MB
734 02:03:10.790950 DDR cs1 size: 2048MB
735 02:03:10.796125 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 02:03:10.796530 cs0 DataBus test pass
737 02:03:10.801384 cs1 DataBus test pass
738 02:03:10.801784 cs0 AddrBus test pass
739 02:03:10.802025 cs1 AddrBus test pass
740 02:03:10.802252
741 02:03:10.806905 100bdlr_step_size ps== 420
742 02:03:10.807237 result report
743 02:03:10.812798 boot times 0Enable ddr reg access
744 02:03:10.817909 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 02:03:10.831742 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 02:03:11.405065 0.0;M3 CHK:0;cm4_sp_mode 0
747 02:03:11.405494 MVN_1=0x00000000
748 02:03:11.410793 MVN_2=0x00000000
749 02:03:11.416380 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 02:03:11.416739 OPS=0x10
751 02:03:11.416963 ring efuse init
752 02:03:11.417176 chipver efuse init
753 02:03:11.421920 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 02:03:11.427513 [0.018960 Inits done]
755 02:03:11.427795 secure task start!
756 02:03:11.428053 high task start!
757 02:03:11.432107 low task start!
758 02:03:11.432377 run into bl31
759 02:03:11.438754 NOTICE: BL31: v1.3(release):4fc40b1
760 02:03:11.446626 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 02:03:11.446980 NOTICE: BL31: G12A normal boot!
762 02:03:11.471973 NOTICE: BL31: BL33 decompress pass
763 02:03:11.477724 ERROR: Error initializing runtime service opteed_fast
764 02:03:12.710436
765 02:03:12.710870
766 02:03:12.718900 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 02:03:12.719208
768 02:03:12.719430 Model: Libre Computer AML-A311D-CC Alta
769 02:03:12.927423 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 02:03:12.950737 DRAM: 2 GiB (effective 3.8 GiB)
771 02:03:13.093802 Core: 408 devices, 31 uclasses, devicetree: separate
772 02:03:13.099603 WDT: Not starting watchdog@f0d0
773 02:03:13.132074 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 02:03:13.144314 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 02:03:13.148267 ** Bad device specification mmc 0 **
776 02:03:13.159690 Card did not respond to voltage select! : -110
777 02:03:13.166322 ** Bad device specification mmc 0 **
778 02:03:13.166890 Couldn't find partition mmc 0
779 02:03:13.175599 Card did not respond to voltage select! : -110
780 02:03:13.181148 ** Bad device specification mmc 0 **
781 02:03:13.181538 Couldn't find partition mmc 0
782 02:03:13.186166 Error: could not access storage.
783 02:03:13.529728 Net: eth0: ethernet@ff3f0000
784 02:03:13.530305 starting USB...
785 02:03:13.781532 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 02:03:13.781933 Starting the controller
787 02:03:13.788619 USB XHCI 1.10
788 02:03:15.950544 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 02:03:15.951200 bl2_stage_init 0x01
790 02:03:15.951682 bl2_stage_init 0x81
791 02:03:15.956042 hw id: 0x0000 - pwm id 0x01
792 02:03:15.956557 bl2_stage_init 0xc1
793 02:03:15.957026 bl2_stage_init 0x02
794 02:03:15.957478
795 02:03:15.961697 L0:00000000
796 02:03:15.962224 L1:20000703
797 02:03:15.962725 L2:00008067
798 02:03:15.963224 L3:14000000
799 02:03:15.964516 B2:00402000
800 02:03:15.965016 B1:e0f83180
801 02:03:15.965477
802 02:03:15.965928 TE: 58124
803 02:03:15.966384
804 02:03:15.975597 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 02:03:15.976148
806 02:03:15.976617 Board ID = 1
807 02:03:15.977062 Set A53 clk to 24M
808 02:03:15.977510 Set A73 clk to 24M
809 02:03:15.981273 Set clk81 to 24M
810 02:03:15.981601 A53 clk: 1200 MHz
811 02:03:15.981818 A73 clk: 1200 MHz
812 02:03:15.986778 CLK81: 166.6M
813 02:03:15.987071 smccc: 00012a92
814 02:03:15.992419 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 02:03:15.992721 board id: 1
816 02:03:15.998031 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 02:03:16.011775 fw parse done
818 02:03:16.016776 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 02:03:16.060372 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 02:03:16.071309 PIEI prepare done
821 02:03:16.071685 fastboot data load
822 02:03:16.071921 fastboot data verify
823 02:03:16.076953 verify result: 266
824 02:03:16.082568 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 02:03:16.082918 LPDDR4 probe
826 02:03:16.083148 ddr clk to 1584MHz
827 02:03:16.090533 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 02:03:16.126884
829 02:03:16.127289 dmc_version 0001
830 02:03:16.134497 Check phy result
831 02:03:16.140412 INFO : End of CA training
832 02:03:16.140759 INFO : End of initialization
833 02:03:16.145961 INFO : Training has run successfully!
834 02:03:16.146468 Check phy result
835 02:03:16.151618 INFO : End of initialization
836 02:03:16.152253 INFO : End of read enable training
837 02:03:16.157152 INFO : End of fine write leveling
838 02:03:16.162724 INFO : End of Write leveling coarse delay
839 02:03:16.163306 INFO : Training has run successfully!
840 02:03:16.163724 Check phy result
841 02:03:16.169033 INFO : End of initialization
842 02:03:16.169414 INFO : End of read dq deskew training
843 02:03:16.173924 INFO : End of MPR read delay center optimization
844 02:03:16.179514 INFO : End of write delay center optimization
845 02:03:16.185133 INFO : End of read delay center optimization
846 02:03:16.185475 INFO : End of max read latency training
847 02:03:16.190728 INFO : Training has run successfully!
848 02:03:16.191074 1D training succeed
849 02:03:16.199968 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 02:03:16.247576 Check phy result
851 02:03:16.247971 INFO : End of initialization
852 02:03:16.268291 INFO : End of 2D read delay Voltage center optimization
853 02:03:16.289501 INFO : End of 2D read delay Voltage center optimization
854 02:03:16.341556 INFO : End of 2D write delay Voltage center optimization
855 02:03:16.390884 INFO : End of 2D write delay Voltage center optimization
856 02:03:16.396364 INFO : Training has run successfully!
857 02:03:16.396673
858 02:03:16.396899 channel==0
859 02:03:16.402043 RxClkDly_Margin_A0==88 ps 9
860 02:03:16.402355 TxDqDly_Margin_A0==98 ps 10
861 02:03:16.405379 RxClkDly_Margin_A1==88 ps 9
862 02:03:16.405677 TxDqDly_Margin_A1==98 ps 10
863 02:03:16.410943 TrainedVREFDQ_A0==74
864 02:03:16.411236 TrainedVREFDQ_A1==74
865 02:03:16.411457 VrefDac_Margin_A0==25
866 02:03:16.416531 DeviceVref_Margin_A0==40
867 02:03:16.416831 VrefDac_Margin_A1==25
868 02:03:16.422130 DeviceVref_Margin_A1==40
869 02:03:16.422409
870 02:03:16.422619
871 02:03:16.422824 channel==1
872 02:03:16.423025 RxClkDly_Margin_A0==98 ps 10
873 02:03:16.427686 TxDqDly_Margin_A0==98 ps 10
874 02:03:16.427975 RxClkDly_Margin_A1==98 ps 10
875 02:03:16.433357 TxDqDly_Margin_A1==88 ps 9
876 02:03:16.433631 TrainedVREFDQ_A0==77
877 02:03:16.433842 TrainedVREFDQ_A1==77
878 02:03:16.438879 VrefDac_Margin_A0==22
879 02:03:16.439147 DeviceVref_Margin_A0==37
880 02:03:16.444543 VrefDac_Margin_A1==22
881 02:03:16.444826 DeviceVref_Margin_A1==37
882 02:03:16.445038
883 02:03:16.450118 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 02:03:16.450422
885 02:03:16.478134 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
886 02:03:16.483708 2D training succeed
887 02:03:16.489445 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 02:03:16.489754 auto size-- 65535DDR cs0 size: 2048MB
889 02:03:16.494942 DDR cs1 size: 2048MB
890 02:03:16.495223 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 02:03:16.500519 cs0 DataBus test pass
892 02:03:16.500812 cs1 DataBus test pass
893 02:03:16.501019 cs0 AddrBus test pass
894 02:03:16.506144 cs1 AddrBus test pass
895 02:03:16.506454
896 02:03:16.506666 100bdlr_step_size ps== 420
897 02:03:16.506876 result report
898 02:03:16.511713 boot times 0Enable ddr reg access
899 02:03:16.519498 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 02:03:16.532868 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 02:03:17.106629 0.0;M3 CHK:0;cm4_sp_mode 0
902 02:03:17.107059 MVN_1=0x00000000
903 02:03:17.112046 MVN_2=0x00000000
904 02:03:17.117827 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 02:03:17.118110 OPS=0x10
906 02:03:17.118319 ring efuse init
907 02:03:17.118531 chipver efuse init
908 02:03:17.123449 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 02:03:17.129017 [0.018961 Inits done]
910 02:03:17.129281 secure task start!
911 02:03:17.129487 high task start!
912 02:03:17.132719 low task start!
913 02:03:17.132964 run into bl31
914 02:03:17.140323 NOTICE: BL31: v1.3(release):4fc40b1
915 02:03:17.147216 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 02:03:17.147507 NOTICE: BL31: G12A normal boot!
917 02:03:17.173478 NOTICE: BL31: BL33 decompress pass
918 02:03:17.178210 ERROR: Error initializing runtime service opteed_fast
919 02:03:18.412278
920 02:03:18.412712
921 02:03:18.420527 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 02:03:18.420839
923 02:03:18.421061 Model: Libre Computer AML-A311D-CC Alta
924 02:03:18.628907 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 02:03:18.652339 DRAM: 2 GiB (effective 3.8 GiB)
926 02:03:18.795413 Core: 408 devices, 31 uclasses, devicetree: separate
927 02:03:18.801148 WDT: Not starting watchdog@f0d0
928 02:03:18.833463 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 02:03:18.845930 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 02:03:18.850932 ** Bad device specification mmc 0 **
931 02:03:18.861229 Card did not respond to voltage select! : -110
932 02:03:18.868865 ** Bad device specification mmc 0 **
933 02:03:18.869474 Couldn't find partition mmc 0
934 02:03:18.877169 Card did not respond to voltage select! : -110
935 02:03:18.882779 ** Bad device specification mmc 0 **
936 02:03:18.883370 Couldn't find partition mmc 0
937 02:03:18.887021 Error: could not access storage.
938 02:03:19.229335 Net: eth0: ethernet@ff3f0000
939 02:03:19.229999 starting USB...
940 02:03:19.482081 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 02:03:19.482508 Starting the controller
942 02:03:19.489104 USB XHCI 1.10
943 02:03:21.350733 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
944 02:03:21.351435 bl2_stage_init 0x81
945 02:03:21.356303 hw id: 0x0000 - pwm id 0x01
946 02:03:21.356874 bl2_stage_init 0xc1
947 02:03:21.357369 bl2_stage_init 0x02
948 02:03:21.357872
949 02:03:21.361941 L0:00000000
950 02:03:21.362494 L1:20000703
951 02:03:21.362980 L2:00008067
952 02:03:21.363459 L3:14000000
953 02:03:21.363920 B2:00402000
954 02:03:21.367472 B1:e0f83180
955 02:03:21.368075
956 02:03:21.368590 TE: 58150
957 02:03:21.369057
958 02:03:21.372962 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
959 02:03:21.373505
960 02:03:21.373956 Board ID = 1
961 02:03:21.378760 Set A53 clk to 24M
962 02:03:21.379273 Set A73 clk to 24M
963 02:03:21.379719 Set clk81 to 24M
964 02:03:21.384229 A53 clk: 1200 MHz
965 02:03:21.384752 A73 clk: 1200 MHz
966 02:03:21.385196 CLK81: 166.6M
967 02:03:21.385638 smccc: 00012aab
968 02:03:21.389791 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
969 02:03:21.395365 board id: 1
970 02:03:21.401202 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
971 02:03:21.411848 fw parse done
972 02:03:21.417900 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
973 02:03:21.460487 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
974 02:03:21.471364 PIEI prepare done
975 02:03:21.471913 fastboot data load
976 02:03:21.472427 fastboot data verify
977 02:03:21.477071 verify result: 266
978 02:03:21.482547 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
979 02:03:21.483053 LPDDR4 probe
980 02:03:21.483490 ddr clk to 1584MHz
981 02:03:21.490644 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
982 02:03:21.527902
983 02:03:21.528573 dmc_version 0001
984 02:03:21.534690 Check phy result
985 02:03:21.540371 INFO : End of CA training
986 02:03:21.540912 INFO : End of initialization
987 02:03:21.546034 INFO : Training has run successfully!
988 02:03:21.546588 Check phy result
989 02:03:21.551611 INFO : End of initialization
990 02:03:21.552215 INFO : End of read enable training
991 02:03:21.557159 INFO : End of fine write leveling
992 02:03:21.562793 INFO : End of Write leveling coarse delay
993 02:03:21.563331 INFO : Training has run successfully!
994 02:03:21.563774 Check phy result
995 02:03:21.568378 INFO : End of initialization
996 02:03:21.568919 INFO : End of read dq deskew training
997 02:03:21.573995 INFO : End of MPR read delay center optimization
998 02:03:21.579641 INFO : End of write delay center optimization
999 02:03:21.585446 INFO : End of read delay center optimization
1000 02:03:21.585963 INFO : End of max read latency training
1001 02:03:21.591196 INFO : Training has run successfully!
1002 02:03:21.591694 1D training succeed
1003 02:03:21.600045 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 02:03:21.647602 Check phy result
1005 02:03:21.648199 INFO : End of initialization
1006 02:03:21.670898 INFO : End of 2D read delay Voltage center optimization
1007 02:03:21.690139 INFO : End of 2D read delay Voltage center optimization
1008 02:03:21.742146 INFO : End of 2D write delay Voltage center optimization
1009 02:03:21.791293 INFO : End of 2D write delay Voltage center optimization
1010 02:03:21.796846 INFO : Training has run successfully!
1011 02:03:21.797464
1012 02:03:21.797967 channel==0
1013 02:03:21.802400 RxClkDly_Margin_A0==88 ps 9
1014 02:03:21.803029 TxDqDly_Margin_A0==98 ps 10
1015 02:03:21.808112 RxClkDly_Margin_A1==88 ps 9
1016 02:03:21.808710 TxDqDly_Margin_A1==88 ps 9
1017 02:03:21.809435 TrainedVREFDQ_A0==74
1018 02:03:21.813561 TrainedVREFDQ_A1==74
1019 02:03:21.814217 VrefDac_Margin_A0==24
1020 02:03:21.814751 DeviceVref_Margin_A0==40
1021 02:03:21.819133 VrefDac_Margin_A1==24
1022 02:03:21.819680 DeviceVref_Margin_A1==40
1023 02:03:21.820203
1024 02:03:21.820689
1025 02:03:21.821156 channel==1
1026 02:03:21.824744 RxClkDly_Margin_A0==98 ps 10
1027 02:03:21.825275 TxDqDly_Margin_A0==98 ps 10
1028 02:03:21.830304 RxClkDly_Margin_A1==88 ps 9
1029 02:03:21.830860 TxDqDly_Margin_A1==88 ps 9
1030 02:03:21.836164 TrainedVREFDQ_A0==77
1031 02:03:21.836891 TrainedVREFDQ_A1==77
1032 02:03:21.837532 VrefDac_Margin_A0==22
1033 02:03:21.841605 DeviceVref_Margin_A0==37
1034 02:03:21.842161 VrefDac_Margin_A1==24
1035 02:03:21.847102 DeviceVref_Margin_A1==37
1036 02:03:21.847649
1037 02:03:21.848148 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1038 02:03:21.848615
1039 02:03:21.880839 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1040 02:03:21.881548 2D training succeed
1041 02:03:21.886565 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1042 02:03:21.891908 auto size-- 65535DDR cs0 size: 2048MB
1043 02:03:21.892728 DDR cs1 size: 2048MB
1044 02:03:21.897476 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1045 02:03:21.898200 cs0 DataBus test pass
1046 02:03:21.903115 cs1 DataBus test pass
1047 02:03:21.903787 cs0 AddrBus test pass
1048 02:03:21.904338 cs1 AddrBus test pass
1049 02:03:21.904815
1050 02:03:21.908622 100bdlr_step_size ps== 420
1051 02:03:21.909202 result report
1052 02:03:21.914347 boot times 0Enable ddr reg access
1053 02:03:21.919545 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1054 02:03:21.932995 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1055 02:03:22.504979 0.0;M3 CHK:0;cm4_sp_mode 0
1056 02:03:22.505692 MVN_1=0x00000000
1057 02:03:22.510422 MVN_2=0x00000000
1058 02:03:22.516293 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1059 02:03:22.516892 OPS=0x10
1060 02:03:22.517384 ring efuse init
1061 02:03:22.517856 chipver efuse init
1062 02:03:22.521769 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1063 02:03:22.527402 [0.018961 Inits done]
1064 02:03:22.527944 secure task start!
1065 02:03:22.528472 high task start!
1066 02:03:22.531930 low task start!
1067 02:03:22.532481 run into bl31
1068 02:03:22.538684 NOTICE: BL31: v1.3(release):4fc40b1
1069 02:03:22.546505 NOTICE: BL31: Built : 15:58:17, May 22 2019
1070 02:03:22.547135 NOTICE: BL31: G12A normal boot!
1071 02:03:22.571899 NOTICE: BL31: BL33 decompress pass
1072 02:03:22.577576 ERROR: Error initializing runtime service opteed_fast
1073 02:03:23.810418
1074 02:03:23.811085
1075 02:03:23.818786 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1076 02:03:23.819300
1077 02:03:23.819764 Model: Libre Computer AML-A311D-CC Alta
1078 02:03:24.027335 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1079 02:03:24.050671 DRAM: 2 GiB (effective 3.8 GiB)
1080 02:03:24.193825 Core: 408 devices, 31 uclasses, devicetree: separate
1081 02:03:24.208513 WDT: Not starting watchdog@f0d0
1082 02:03:24.231835 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1083 02:03:24.244357 Loading Environment from FAT... Card did not respond to voltage select! : -110
1084 02:03:24.248909 ** Bad device specification mmc 0 **
1085 02:03:24.259514 Card did not respond to voltage select! : -110
1086 02:03:24.267209 ** Bad device specification mmc 0 **
1087 02:03:24.267506 Couldn't find partition mmc 0
1088 02:03:24.275446 Card did not respond to voltage select! : -110
1089 02:03:24.280916 ** Bad device specification mmc 0 **
1090 02:03:24.281196 Couldn't find partition mmc 0
1091 02:03:24.286014 Error: could not access storage.
1092 02:03:24.629679 Net: eth0: ethernet@ff3f0000
1093 02:03:24.630272 starting USB...
1094 02:03:24.881437 Bus usb@ff500000: Register 3000140 NbrPorts 3
1095 02:03:24.882062 Starting the controller
1096 02:03:24.888434 USB XHCI 1.10
1097 02:03:26.444701 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1098 02:03:26.452985 scanning usb for storage devices... 0 Storage Device(s) found
1100 02:03:26.504608 Hit any key to stop autoboot: 1
1101 02:03:26.505536 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1102 02:03:26.506283 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1103 02:03:26.506799 Setting prompt string to ['=>']
1104 02:03:26.507299 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1105 02:03:26.520496 0
1106 02:03:26.521470 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1107 02:03:26.521978 Sending with 10 millisecond of delay
1109 02:03:27.656947 => setenv autoload no
1110 02:03:27.667719 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1111 02:03:27.672678 setenv autoload no
1112 02:03:27.673438 Sending with 10 millisecond of delay
1114 02:03:29.472020 => setenv initrd_high 0xffffffff
1115 02:03:29.482681 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1116 02:03:29.483402 setenv initrd_high 0xffffffff
1117 02:03:29.483943 Sending with 10 millisecond of delay
1119 02:03:31.103833 => setenv fdt_high 0xffffffff
1120 02:03:31.114675 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1121 02:03:31.115556 setenv fdt_high 0xffffffff
1122 02:03:31.116375 Sending with 10 millisecond of delay
1124 02:03:31.408340 => dhcp
1125 02:03:31.419165 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1126 02:03:31.420250 dhcp
1127 02:03:31.420762 Speed: 1000, full duplex
1128 02:03:31.421224 BOOTP broadcast 1
1129 02:03:31.612364 DHCP client bound to address 192.168.6.27 (192 ms)
1130 02:03:31.613308 Sending with 10 millisecond of delay
1132 02:03:33.290338 => setenv serverip 192.168.6.2
1133 02:03:33.301167 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1134 02:03:33.302093 setenv serverip 192.168.6.2
1135 02:03:33.302857 Sending with 10 millisecond of delay
1137 02:03:37.027744 => tftpboot 0x01080000 949556/tftp-deploy-5vn5aopv/kernel/uImage
1138 02:03:37.038713 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1139 02:03:37.039687 tftpboot 0x01080000 949556/tftp-deploy-5vn5aopv/kernel/uImage
1140 02:03:37.040228 Speed: 1000, full duplex
1141 02:03:37.040690 Using ethernet@ff3f0000 device
1142 02:03:37.041478 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1143 02:03:37.047010 Filename '949556/tftp-deploy-5vn5aopv/kernel/uImage'.
1144 02:03:37.050810 Load address: 0x1080000
1145 02:03:39.403851 Loading: *################################################## 36.1 MiB
1146 02:03:39.404537 15.3 MiB/s
1147 02:03:39.405005 done
1148 02:03:39.407080 Bytes transferred = 37878336 (241fa40 hex)
1149 02:03:39.407854 Sending with 10 millisecond of delay
1151 02:03:44.095338 => tftpboot 0x08000000 949556/tftp-deploy-5vn5aopv/ramdisk/ramdisk.cpio.gz.uboot
1152 02:03:44.106184 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1153 02:03:44.107097 tftpboot 0x08000000 949556/tftp-deploy-5vn5aopv/ramdisk/ramdisk.cpio.gz.uboot
1154 02:03:44.107573 Speed: 1000, full duplex
1155 02:03:44.108059 Using ethernet@ff3f0000 device
1156 02:03:44.108835 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1157 02:03:44.117305 Filename '949556/tftp-deploy-5vn5aopv/ramdisk/ramdisk.cpio.gz.uboot'.
1158 02:03:44.117827 Load address: 0x8000000
1159 02:03:51.534060 Loading: *##T ############################################### UDP wrong checksum 00000005 0000d16f
1160 02:03:56.536319 T UDP wrong checksum 00000005 0000d16f
1161 02:04:06.539745 T T UDP wrong checksum 00000005 0000d16f
1162 02:04:15.667237 T UDP wrong checksum 000000ff 0000979a
1163 02:04:15.680372 UDP wrong checksum 000000ff 0000208d
1164 02:04:26.541211 T T UDP wrong checksum 00000005 0000d16f
1165 02:04:26.818080 T UDP wrong checksum 000000ff 0000af4c
1166 02:04:26.877889 UDP wrong checksum 000000ff 0000493f
1167 02:04:41.547690 T T
1168 02:04:41.548162 Retry count exceeded; starting again
1170 02:04:41.549079 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1173 02:04:41.550072 end: 2.4 uboot-commands (duration 00:01:52) [common]
1175 02:04:41.550846 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1177 02:04:41.551443 end: 2 uboot-action (duration 00:01:52) [common]
1179 02:04:41.552374 Cleaning after the job
1180 02:04:41.552719 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/ramdisk
1181 02:04:41.553727 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/kernel
1182 02:04:41.566878 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/dtb
1183 02:04:41.567749 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/nfsrootfs
1184 02:04:41.691204 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949556/tftp-deploy-5vn5aopv/modules
1185 02:04:41.717056 start: 4.1 power-off (timeout 00:00:30) [common]
1186 02:04:41.717982 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1187 02:04:41.753858 >> OK - accepted request
1188 02:04:41.755905 Returned 0 in 0 seconds
1189 02:04:41.856787 end: 4.1 power-off (duration 00:00:00) [common]
1191 02:04:41.857905 start: 4.2 read-feedback (timeout 00:10:00) [common]
1192 02:04:41.858640 Listened to connection for namespace 'common' for up to 1s
1193 02:04:42.859554 Finalising connection for namespace 'common'
1194 02:04:42.860125 Disconnecting from shell: Finalise
1195 02:04:42.860455 =>
1196 02:04:42.961190 end: 4.2 read-feedback (duration 00:00:01) [common]
1197 02:04:42.961695 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949556
1198 02:04:45.944090 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949556
1199 02:04:45.944703 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.