Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 00:11:20.976911 lava-dispatcher, installed at version: 2024.01
2 00:11:20.977689 start: 0 validate
3 00:11:20.978164 Start time: 2024-11-07 00:11:20.978136+00:00 (UTC)
4 00:11:20.978687 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:11:20.979221 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:11:21.013102 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:11:21.013637 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 00:11:21.041978 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:11:21.042581 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 00:11:21.070159 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:11:21.070657 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
12 00:11:21.109541 validate duration: 0.13
14 00:11:21.110404 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:11:21.110759 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:11:21.111080 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:11:21.111844 Not decompressing ramdisk as can be used compressed.
18 00:11:21.112353 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 00:11:21.112629 saving as /var/lib/lava/dispatcher/tmp/949368/tftp-deploy-oat87_aq/ramdisk/rootfs.cpio.gz
20 00:11:21.112907 total size: 47897469 (45 MB)
21 00:11:21.151001 progress 0 % (0 MB)
22 00:11:21.181442 progress 5 % (2 MB)
23 00:11:21.211271 progress 10 % (4 MB)
24 00:11:21.241264 progress 15 % (6 MB)
25 00:11:21.270600 progress 20 % (9 MB)
26 00:11:21.299944 progress 25 % (11 MB)
27 00:11:21.329917 progress 30 % (13 MB)
28 00:11:21.359010 progress 35 % (16 MB)
29 00:11:21.388471 progress 40 % (18 MB)
30 00:11:21.418001 progress 45 % (20 MB)
31 00:11:21.447648 progress 50 % (22 MB)
32 00:11:21.476938 progress 55 % (25 MB)
33 00:11:21.506914 progress 60 % (27 MB)
34 00:11:21.536437 progress 65 % (29 MB)
35 00:11:21.565913 progress 70 % (32 MB)
36 00:11:21.595333 progress 75 % (34 MB)
37 00:11:21.624649 progress 80 % (36 MB)
38 00:11:21.654498 progress 85 % (38 MB)
39 00:11:21.683800 progress 90 % (41 MB)
40 00:11:21.713084 progress 95 % (43 MB)
41 00:11:21.742170 progress 100 % (45 MB)
42 00:11:21.742888 45 MB downloaded in 0.63 s (72.51 MB/s)
43 00:11:21.743467 end: 1.1.1 http-download (duration 00:00:01) [common]
45 00:11:21.744419 end: 1.1 download-retry (duration 00:00:01) [common]
46 00:11:21.744736 start: 1.2 download-retry (timeout 00:09:59) [common]
47 00:11:21.745025 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 00:11:21.745514 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/kernel/Image
49 00:11:21.745787 saving as /var/lib/lava/dispatcher/tmp/949368/tftp-deploy-oat87_aq/kernel/Image
50 00:11:21.746021 total size: 37880320 (36 MB)
51 00:11:21.746255 No compression specified
52 00:11:21.783715 progress 0 % (0 MB)
53 00:11:21.806764 progress 5 % (1 MB)
54 00:11:21.830807 progress 10 % (3 MB)
55 00:11:21.854309 progress 15 % (5 MB)
56 00:11:21.878029 progress 20 % (7 MB)
57 00:11:21.901094 progress 25 % (9 MB)
58 00:11:21.925013 progress 30 % (10 MB)
59 00:11:21.948301 progress 35 % (12 MB)
60 00:11:21.972407 progress 40 % (14 MB)
61 00:11:21.996023 progress 45 % (16 MB)
62 00:11:22.019400 progress 50 % (18 MB)
63 00:11:22.043067 progress 55 % (19 MB)
64 00:11:22.066646 progress 60 % (21 MB)
65 00:11:22.089899 progress 65 % (23 MB)
66 00:11:22.113142 progress 70 % (25 MB)
67 00:11:22.136300 progress 75 % (27 MB)
68 00:11:22.158977 progress 80 % (28 MB)
69 00:11:22.182128 progress 85 % (30 MB)
70 00:11:22.205251 progress 90 % (32 MB)
71 00:11:22.228580 progress 95 % (34 MB)
72 00:11:22.251607 progress 100 % (36 MB)
73 00:11:22.252199 36 MB downloaded in 0.51 s (71.37 MB/s)
74 00:11:22.252701 end: 1.2.1 http-download (duration 00:00:01) [common]
76 00:11:22.253518 end: 1.2 download-retry (duration 00:00:01) [common]
77 00:11:22.253793 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:11:22.254053 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:11:22.254532 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 00:11:22.254819 saving as /var/lib/lava/dispatcher/tmp/949368/tftp-deploy-oat87_aq/dtb/meson-g12b-a311d-libretech-cc.dtb
81 00:11:22.255027 total size: 54703 (0 MB)
82 00:11:22.255235 No compression specified
83 00:11:22.297223 progress 59 % (0 MB)
84 00:11:22.298104 progress 100 % (0 MB)
85 00:11:22.298668 0 MB downloaded in 0.04 s (1.20 MB/s)
86 00:11:22.299170 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:11:22.300014 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:11:22.300288 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:11:22.300554 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:11:22.301048 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/modules.tar.xz
92 00:11:22.301303 saving as /var/lib/lava/dispatcher/tmp/949368/tftp-deploy-oat87_aq/modules/modules.tar
93 00:11:22.301509 total size: 11768476 (11 MB)
94 00:11:22.301720 Using unxz to decompress xz
95 00:11:22.343673 progress 0 % (0 MB)
96 00:11:22.413194 progress 5 % (0 MB)
97 00:11:22.487924 progress 10 % (1 MB)
98 00:11:22.582605 progress 15 % (1 MB)
99 00:11:22.678325 progress 20 % (2 MB)
100 00:11:22.758540 progress 25 % (2 MB)
101 00:11:22.835803 progress 30 % (3 MB)
102 00:11:22.917695 progress 35 % (3 MB)
103 00:11:22.997581 progress 40 % (4 MB)
104 00:11:23.074572 progress 45 % (5 MB)
105 00:11:23.159218 progress 50 % (5 MB)
106 00:11:23.242180 progress 55 % (6 MB)
107 00:11:23.327040 progress 60 % (6 MB)
108 00:11:23.408148 progress 65 % (7 MB)
109 00:11:23.491075 progress 70 % (7 MB)
110 00:11:23.577972 progress 75 % (8 MB)
111 00:11:23.661877 progress 80 % (9 MB)
112 00:11:23.742399 progress 85 % (9 MB)
113 00:11:23.825913 progress 90 % (10 MB)
114 00:11:23.904663 progress 95 % (10 MB)
115 00:11:23.982108 progress 100 % (11 MB)
116 00:11:23.992642 11 MB downloaded in 1.69 s (6.64 MB/s)
117 00:11:23.993243 end: 1.4.1 http-download (duration 00:00:02) [common]
119 00:11:23.994066 end: 1.4 download-retry (duration 00:00:02) [common]
120 00:11:23.994337 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 00:11:23.994602 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 00:11:23.994852 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:11:23.995104 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 00:11:23.995693 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5
125 00:11:23.996423 makedir: /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin
126 00:11:23.997165 makedir: /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/tests
127 00:11:23.997862 makedir: /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/results
128 00:11:23.998558 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-add-keys
129 00:11:23.999603 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-add-sources
130 00:11:24.000668 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-background-process-start
131 00:11:24.001707 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-background-process-stop
132 00:11:24.002823 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-common-functions
133 00:11:24.003851 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-echo-ipv4
134 00:11:24.005019 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-install-packages
135 00:11:24.006024 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-installed-packages
136 00:11:24.006997 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-os-build
137 00:11:24.008027 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-probe-channel
138 00:11:24.009047 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-probe-ip
139 00:11:24.010030 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-target-ip
140 00:11:24.011005 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-target-mac
141 00:11:24.011967 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-target-storage
142 00:11:24.013040 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-test-case
143 00:11:24.014035 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-test-event
144 00:11:24.015006 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-test-feedback
145 00:11:24.016003 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-test-raise
146 00:11:24.016991 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-test-reference
147 00:11:24.017983 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-test-runner
148 00:11:24.019006 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-test-set
149 00:11:24.020007 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-test-shell
150 00:11:24.021024 Updating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-install-packages (oe)
151 00:11:24.022070 Updating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/bin/lava-installed-packages (oe)
152 00:11:24.022966 Creating /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/environment
153 00:11:24.023732 LAVA metadata
154 00:11:24.024309 - LAVA_JOB_ID=949368
155 00:11:24.024786 - LAVA_DISPATCHER_IP=192.168.6.2
156 00:11:24.025497 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 00:11:24.027444 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 00:11:24.028085 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 00:11:24.028511 skipped lava-vland-overlay
160 00:11:24.028995 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 00:11:24.029498 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 00:11:24.029918 skipped lava-multinode-overlay
163 00:11:24.030396 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 00:11:24.030889 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 00:11:24.031362 Loading test definitions
166 00:11:24.031904 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 00:11:24.032218 Using /lava-949368 at stage 0
168 00:11:24.033407 uuid=949368_1.5.2.4.1 testdef=None
169 00:11:24.033743 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 00:11:24.034016 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 00:11:24.035742 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 00:11:24.036654 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 00:11:24.038871 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 00:11:24.039750 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 00:11:24.041894 runner path: /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/0/tests/0_igt-gpu-panfrost test_uuid 949368_1.5.2.4.1
178 00:11:24.042497 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 00:11:24.043329 Creating lava-test-runner.conf files
181 00:11:24.043535 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949368/lava-overlay-x1ejnfs5/lava-949368/0 for stage 0
182 00:11:24.043874 - 0_igt-gpu-panfrost
183 00:11:24.044261 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 00:11:24.044553 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 00:11:24.068341 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 00:11:24.068737 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 00:11:24.069005 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 00:11:24.069269 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 00:11:24.069532 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 00:11:30.935345 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 00:11:30.935858 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 00:11:30.936482 extracting modules file /var/lib/lava/dispatcher/tmp/949368/tftp-deploy-oat87_aq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949368/extract-overlay-ramdisk-s04mdo4_/ramdisk
193 00:11:32.542729 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 00:11:32.543205 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 00:11:32.543488 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949368/compress-overlay-foqamj3d/overlay-1.5.2.5.tar.gz to ramdisk
196 00:11:32.543725 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949368/compress-overlay-foqamj3d/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949368/extract-overlay-ramdisk-s04mdo4_/ramdisk
197 00:11:32.576303 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 00:11:32.576751 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 00:11:32.577028 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 00:11:32.577260 Converting downloaded kernel to a uImage
201 00:11:32.577569 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949368/tftp-deploy-oat87_aq/kernel/Image /var/lib/lava/dispatcher/tmp/949368/tftp-deploy-oat87_aq/kernel/uImage
202 00:11:32.958358 output: Image Name:
203 00:11:32.958773 output: Created: Thu Nov 7 00:11:32 2024
204 00:11:32.958981 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 00:11:32.959184 output: Data Size: 37880320 Bytes = 36992.50 KiB = 36.13 MiB
206 00:11:32.959385 output: Load Address: 01080000
207 00:11:32.959586 output: Entry Point: 01080000
208 00:11:32.959785 output:
209 00:11:32.960159 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 00:11:32.960453 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 00:11:32.960726 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 00:11:32.960984 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 00:11:32.961242 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 00:11:32.961500 Building ramdisk /var/lib/lava/dispatcher/tmp/949368/extract-overlay-ramdisk-s04mdo4_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949368/extract-overlay-ramdisk-s04mdo4_/ramdisk
215 00:11:39.876105 >> 509030 blocks
216 00:12:00.322355 Adding RAMdisk u-boot header.
217 00:12:00.323014 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949368/extract-overlay-ramdisk-s04mdo4_/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949368/extract-overlay-ramdisk-s04mdo4_/ramdisk.cpio.gz.uboot
218 00:12:00.999578 output: Image Name:
219 00:12:00.999972 output: Created: Thu Nov 7 00:12:00 2024
220 00:12:01.000515 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 00:12:01.000975 output: Data Size: 66429713 Bytes = 64872.77 KiB = 63.35 MiB
222 00:12:01.001446 output: Load Address: 00000000
223 00:12:01.001895 output: Entry Point: 00000000
224 00:12:01.002335 output:
225 00:12:01.003517 rename /var/lib/lava/dispatcher/tmp/949368/extract-overlay-ramdisk-s04mdo4_/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949368/tftp-deploy-oat87_aq/ramdisk/ramdisk.cpio.gz.uboot
226 00:12:01.004350 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 00:12:01.004959 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 00:12:01.005547 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 00:12:01.006049 No LXC device requested
230 00:12:01.006607 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 00:12:01.007169 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 00:12:01.007722 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 00:12:01.008217 Checking files for TFTP limit of 4294967296 bytes.
234 00:12:01.011143 end: 1 tftp-deploy (duration 00:00:40) [common]
235 00:12:01.011779 start: 2 uboot-action (timeout 00:05:00) [common]
236 00:12:01.012408 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 00:12:01.012967 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 00:12:01.013528 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 00:12:01.014118 Using kernel file from prepare-kernel: 949368/tftp-deploy-oat87_aq/kernel/uImage
240 00:12:01.014812 substitutions:
241 00:12:01.015274 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 00:12:01.015945 - {DTB_ADDR}: 0x01070000
243 00:12:01.016627 - {DTB}: 949368/tftp-deploy-oat87_aq/dtb/meson-g12b-a311d-libretech-cc.dtb
244 00:12:01.017075 - {INITRD}: 949368/tftp-deploy-oat87_aq/ramdisk/ramdisk.cpio.gz.uboot
245 00:12:01.017498 - {KERNEL_ADDR}: 0x01080000
246 00:12:01.017907 - {KERNEL}: 949368/tftp-deploy-oat87_aq/kernel/uImage
247 00:12:01.018321 - {LAVA_MAC}: None
248 00:12:01.018782 - {PRESEED_CONFIG}: None
249 00:12:01.019198 - {PRESEED_LOCAL}: None
250 00:12:01.019600 - {RAMDISK_ADDR}: 0x08000000
251 00:12:01.020038 - {RAMDISK}: 949368/tftp-deploy-oat87_aq/ramdisk/ramdisk.cpio.gz.uboot
252 00:12:01.020454 - {ROOT_PART}: None
253 00:12:01.020856 - {ROOT}: None
254 00:12:01.021262 - {SERVER_IP}: 192.168.6.2
255 00:12:01.021668 - {TEE_ADDR}: 0x83000000
256 00:12:01.022065 - {TEE}: None
257 00:12:01.022464 Parsed boot commands:
258 00:12:01.022858 - setenv autoload no
259 00:12:01.023253 - setenv initrd_high 0xffffffff
260 00:12:01.023647 - setenv fdt_high 0xffffffff
261 00:12:01.024066 - dhcp
262 00:12:01.024467 - setenv serverip 192.168.6.2
263 00:12:01.024865 - tftpboot 0x01080000 949368/tftp-deploy-oat87_aq/kernel/uImage
264 00:12:01.025263 - tftpboot 0x08000000 949368/tftp-deploy-oat87_aq/ramdisk/ramdisk.cpio.gz.uboot
265 00:12:01.025661 - tftpboot 0x01070000 949368/tftp-deploy-oat87_aq/dtb/meson-g12b-a311d-libretech-cc.dtb
266 00:12:01.026056 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 00:12:01.026453 - bootm 0x01080000 0x08000000 0x01070000
268 00:12:01.026976 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 00:12:01.028519 start: 2.3 connect-device (timeout 00:05:00) [common]
271 00:12:01.028995 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 00:12:01.042454 Setting prompt string to ['lava-test: # ']
273 00:12:01.043941 end: 2.3 connect-device (duration 00:00:00) [common]
274 00:12:01.044630 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 00:12:01.045511 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 00:12:01.046168 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 00:12:01.047382 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 00:12:01.083519 >> OK - accepted request
279 00:12:01.085674 Returned 0 in 0 seconds
280 00:12:01.186855 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 00:12:01.188647 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 00:12:01.189244 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 00:12:01.189761 Setting prompt string to ['Hit any key to stop autoboot']
285 00:12:01.190238 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 00:12:01.191835 Trying 192.168.56.21...
287 00:12:01.192372 Connected to conserv1.
288 00:12:01.192831 Escape character is '^]'.
289 00:12:01.193268
290 00:12:01.193706 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 00:12:01.194152
292 00:12:13.312913 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 00:12:13.313353 bl2_stage_init 0x01
294 00:12:13.313599 bl2_stage_init 0x81
295 00:12:13.318443 hw id: 0x0000 - pwm id 0x01
296 00:12:13.318785 bl2_stage_init 0xc1
297 00:12:13.319015 bl2_stage_init 0x02
298 00:12:13.319237
299 00:12:13.324027 L0:00000000
300 00:12:13.324326 L1:20000703
301 00:12:13.324539 L2:00008067
302 00:12:13.324745 L3:14000000
303 00:12:13.329524 B2:00402000
304 00:12:13.329817 B1:e0f83180
305 00:12:13.330029
306 00:12:13.330237 TE: 58124
307 00:12:13.330441
308 00:12:13.335435 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 00:12:13.335736
310 00:12:13.335950 Board ID = 1
311 00:12:13.340657 Set A53 clk to 24M
312 00:12:13.341166 Set A73 clk to 24M
313 00:12:13.341570 Set clk81 to 24M
314 00:12:13.346210 A53 clk: 1200 MHz
315 00:12:13.346679 A73 clk: 1200 MHz
316 00:12:13.347077 CLK81: 166.6M
317 00:12:13.347466 smccc: 00012a92
318 00:12:13.351887 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 00:12:13.357554 board id: 1
320 00:12:13.363328 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 00:12:13.373949 fw parse done
322 00:12:13.379949 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 00:12:13.422720 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 00:12:13.433488 PIEI prepare done
325 00:12:13.434084 fastboot data load
326 00:12:13.434563 fastboot data verify
327 00:12:13.439057 verify result: 266
328 00:12:13.444647 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 00:12:13.445127 LPDDR4 probe
330 00:12:13.445564 ddr clk to 1584MHz
331 00:12:13.452639 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 00:12:13.489937
333 00:12:13.490552 dmc_version 0001
334 00:12:13.496662 Check phy result
335 00:12:13.502677 INFO : End of CA training
336 00:12:13.503165 INFO : End of initialization
337 00:12:13.508065 INFO : Training has run successfully!
338 00:12:13.508573 Check phy result
339 00:12:13.513630 INFO : End of initialization
340 00:12:13.514106 INFO : End of read enable training
341 00:12:13.519276 INFO : End of fine write leveling
342 00:12:13.524935 INFO : End of Write leveling coarse delay
343 00:12:13.525413 INFO : Training has run successfully!
344 00:12:13.525855 Check phy result
345 00:12:13.530638 INFO : End of initialization
346 00:12:13.531116 INFO : End of read dq deskew training
347 00:12:13.536037 INFO : End of MPR read delay center optimization
348 00:12:13.541811 INFO : End of write delay center optimization
349 00:12:13.547252 INFO : End of read delay center optimization
350 00:12:13.547734 INFO : End of max read latency training
351 00:12:13.552883 INFO : Training has run successfully!
352 00:12:13.553357 1D training succeed
353 00:12:13.562101 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 00:12:13.609759 Check phy result
355 00:12:13.610246 INFO : End of initialization
356 00:12:13.631298 INFO : End of 2D read delay Voltage center optimization
357 00:12:13.651484 INFO : End of 2D read delay Voltage center optimization
358 00:12:13.703379 INFO : End of 2D write delay Voltage center optimization
359 00:12:13.752567 INFO : End of 2D write delay Voltage center optimization
360 00:12:13.758096 INFO : Training has run successfully!
361 00:12:13.758584
362 00:12:13.759024 channel==0
363 00:12:13.763744 RxClkDly_Margin_A0==88 ps 9
364 00:12:13.764276 TxDqDly_Margin_A0==98 ps 10
365 00:12:13.769415 RxClkDly_Margin_A1==88 ps 9
366 00:12:13.769885 TxDqDly_Margin_A1==98 ps 10
367 00:12:13.770324 TrainedVREFDQ_A0==74
368 00:12:13.774960 TrainedVREFDQ_A1==75
369 00:12:13.775431 VrefDac_Margin_A0==25
370 00:12:13.775859 DeviceVref_Margin_A0==40
371 00:12:13.780533 VrefDac_Margin_A1==25
372 00:12:13.780998 DeviceVref_Margin_A1==39
373 00:12:13.781428
374 00:12:13.781862
375 00:12:13.786126 channel==1
376 00:12:13.786596 RxClkDly_Margin_A0==98 ps 10
377 00:12:13.787030 TxDqDly_Margin_A0==98 ps 10
378 00:12:13.791734 RxClkDly_Margin_A1==98 ps 10
379 00:12:13.792337 TxDqDly_Margin_A1==88 ps 9
380 00:12:13.797414 TrainedVREFDQ_A0==77
381 00:12:13.797892 TrainedVREFDQ_A1==77
382 00:12:13.798325 VrefDac_Margin_A0==22
383 00:12:13.803181 DeviceVref_Margin_A0==37
384 00:12:13.803644 VrefDac_Margin_A1==24
385 00:12:13.808465 DeviceVref_Margin_A1==37
386 00:12:13.808930
387 00:12:13.809365 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 00:12:13.814149
389 00:12:13.842157 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
390 00:12:13.842767 2D training succeed
391 00:12:13.847679 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 00:12:13.853298 auto size-- 65535DDR cs0 size: 2048MB
393 00:12:13.853777 DDR cs1 size: 2048MB
394 00:12:13.858822 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 00:12:13.859307 cs0 DataBus test pass
396 00:12:13.864346 cs1 DataBus test pass
397 00:12:13.864816 cs0 AddrBus test pass
398 00:12:13.865246 cs1 AddrBus test pass
399 00:12:13.865672
400 00:12:13.870023 100bdlr_step_size ps== 420
401 00:12:13.870573 result report
402 00:12:13.875622 boot times 0Enable ddr reg access
403 00:12:13.881027 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 00:12:13.894499 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 00:12:14.466500 0.0;M3 CHK:0;cm4_sp_mode 0
406 00:12:14.467183 MVN_1=0x00000000
407 00:12:14.472180 MVN_2=0x00000000
408 00:12:14.477975 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 00:12:14.478471 OPS=0x10
410 00:12:14.478961 ring efuse init
411 00:12:14.479421 chipver efuse init
412 00:12:14.483401 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 00:12:14.489038 [0.018961 Inits done]
414 00:12:14.489568 secure task start!
415 00:12:14.489910 high task start!
416 00:12:14.493564 low task start!
417 00:12:14.494063 run into bl31
418 00:12:14.500209 NOTICE: BL31: v1.3(release):4fc40b1
419 00:12:14.508043 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 00:12:14.508572 NOTICE: BL31: G12A normal boot!
421 00:12:14.533370 NOTICE: BL31: BL33 decompress pass
422 00:12:14.539045 ERROR: Error initializing runtime service opteed_fast
423 00:12:15.771956
424 00:12:15.772402
425 00:12:15.780268 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 00:12:15.780559
427 00:12:15.780778 Model: Libre Computer AML-A311D-CC Alta
428 00:12:15.988871 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 00:12:16.012278 DRAM: 2 GiB (effective 3.8 GiB)
430 00:12:16.155240 Core: 408 devices, 31 uclasses, devicetree: separate
431 00:12:16.161081 WDT: Not starting watchdog@f0d0
432 00:12:16.193401 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 00:12:16.205723 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 00:12:16.210752 ** Bad device specification mmc 0 **
435 00:12:16.221083 Card did not respond to voltage select! : -110
436 00:12:16.228716 ** Bad device specification mmc 0 **
437 00:12:16.229240 Couldn't find partition mmc 0
438 00:12:16.237010 Card did not respond to voltage select! : -110
439 00:12:16.242608 ** Bad device specification mmc 0 **
440 00:12:16.243127 Couldn't find partition mmc 0
441 00:12:16.247668 Error: could not access storage.
442 00:12:17.512933 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 00:12:17.513575 bl2_stage_init 0x01
444 00:12:17.514038 bl2_stage_init 0x81
445 00:12:17.518452 hw id: 0x0000 - pwm id 0x01
446 00:12:17.518929 bl2_stage_init 0xc1
447 00:12:17.519378 bl2_stage_init 0x02
448 00:12:17.519821
449 00:12:17.524084 L0:00000000
450 00:12:17.524564 L1:20000703
451 00:12:17.525010 L2:00008067
452 00:12:17.525449 L3:14000000
453 00:12:17.529738 B2:00402000
454 00:12:17.530202 B1:e0f83180
455 00:12:17.530641
456 00:12:17.531081 TE: 58159
457 00:12:17.531519
458 00:12:17.535252 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 00:12:17.535736
460 00:12:17.536225 Board ID = 1
461 00:12:17.540816 Set A53 clk to 24M
462 00:12:17.541286 Set A73 clk to 24M
463 00:12:17.541731 Set clk81 to 24M
464 00:12:17.546411 A53 clk: 1200 MHz
465 00:12:17.546920 A73 clk: 1200 MHz
466 00:12:17.547367 CLK81: 166.6M
467 00:12:17.547805 smccc: 00012ab5
468 00:12:17.552050 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 00:12:17.557732 board id: 1
470 00:12:17.563489 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 00:12:17.574260 fw parse done
472 00:12:17.580234 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 00:12:17.622831 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 00:12:17.633726 PIEI prepare done
475 00:12:17.634225 fastboot data load
476 00:12:17.634678 fastboot data verify
477 00:12:17.639368 verify result: 266
478 00:12:17.644929 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 00:12:17.645412 LPDDR4 probe
480 00:12:17.645859 ddr clk to 1584MHz
481 00:12:17.652890 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 00:12:17.690146
483 00:12:17.690679 dmc_version 0001
484 00:12:17.696897 Check phy result
485 00:12:17.702831 INFO : End of CA training
486 00:12:17.703337 INFO : End of initialization
487 00:12:17.708307 INFO : Training has run successfully!
488 00:12:17.708814 Check phy result
489 00:12:17.713888 INFO : End of initialization
490 00:12:17.714358 INFO : End of read enable training
491 00:12:17.719480 INFO : End of fine write leveling
492 00:12:17.725064 INFO : End of Write leveling coarse delay
493 00:12:17.725557 INFO : Training has run successfully!
494 00:12:17.726004 Check phy result
495 00:12:17.730833 INFO : End of initialization
496 00:12:17.731304 INFO : End of read dq deskew training
497 00:12:17.736274 INFO : End of MPR read delay center optimization
498 00:12:17.741884 INFO : End of write delay center optimization
499 00:12:17.747473 INFO : End of read delay center optimization
500 00:12:17.747941 INFO : End of max read latency training
501 00:12:17.753063 INFO : Training has run successfully!
502 00:12:17.753529 1D training succeed
503 00:12:17.762268 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 00:12:17.809950 Check phy result
505 00:12:17.810478 INFO : End of initialization
506 00:12:17.831450 INFO : End of 2D read delay Voltage center optimization
507 00:12:17.851593 INFO : End of 2D read delay Voltage center optimization
508 00:12:17.903500 INFO : End of 2D write delay Voltage center optimization
509 00:12:17.952630 INFO : End of 2D write delay Voltage center optimization
510 00:12:17.958188 INFO : Training has run successfully!
511 00:12:17.958669
512 00:12:17.959117 channel==0
513 00:12:17.963816 RxClkDly_Margin_A0==88 ps 9
514 00:12:17.964350 TxDqDly_Margin_A0==98 ps 10
515 00:12:17.969396 RxClkDly_Margin_A1==88 ps 9
516 00:12:17.969876 TxDqDly_Margin_A1==98 ps 10
517 00:12:17.970324 TrainedVREFDQ_A0==74
518 00:12:17.975050 TrainedVREFDQ_A1==74
519 00:12:17.975558 VrefDac_Margin_A0==25
520 00:12:17.976036 DeviceVref_Margin_A0==40
521 00:12:17.980575 VrefDac_Margin_A1==25
522 00:12:17.981042 DeviceVref_Margin_A1==40
523 00:12:17.981485
524 00:12:17.981926
525 00:12:17.986199 channel==1
526 00:12:17.986664 RxClkDly_Margin_A0==98 ps 10
527 00:12:17.987104 TxDqDly_Margin_A0==88 ps 9
528 00:12:17.991834 RxClkDly_Margin_A1==98 ps 10
529 00:12:17.992339 TxDqDly_Margin_A1==88 ps 9
530 00:12:17.997379 TrainedVREFDQ_A0==77
531 00:12:17.997854 TrainedVREFDQ_A1==77
532 00:12:17.998302 VrefDac_Margin_A0==22
533 00:12:18.003029 DeviceVref_Margin_A0==37
534 00:12:18.003539 VrefDac_Margin_A1==22
535 00:12:18.008596 DeviceVref_Margin_A1==37
536 00:12:18.009069
537 00:12:18.009515 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 00:12:18.009951
539 00:12:18.042211 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
540 00:12:18.042769 2D training succeed
541 00:12:18.047824 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 00:12:18.053392 auto size-- 65535DDR cs0 size: 2048MB
543 00:12:18.053869 DDR cs1 size: 2048MB
544 00:12:18.058986 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 00:12:18.059493 cs0 DataBus test pass
546 00:12:18.064591 cs1 DataBus test pass
547 00:12:18.065065 cs0 AddrBus test pass
548 00:12:18.065507 cs1 AddrBus test pass
549 00:12:18.065948
550 00:12:18.070193 100bdlr_step_size ps== 420
551 00:12:18.070679 result report
552 00:12:18.075760 boot times 0Enable ddr reg access
553 00:12:18.081145 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 00:12:18.094629 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 00:12:18.666681 0.0;M3 CHK:0;cm4_sp_mode 0
556 00:12:18.667341 MVN_1=0x00000000
557 00:12:18.672156 MVN_2=0x00000000
558 00:12:18.677923 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 00:12:18.678435 OPS=0x10
560 00:12:18.678897 ring efuse init
561 00:12:18.679362 chipver efuse init
562 00:12:18.683514 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 00:12:18.689075 [0.018961 Inits done]
564 00:12:18.689549 secure task start!
565 00:12:18.689980 high task start!
566 00:12:18.693658 low task start!
567 00:12:18.694108 run into bl31
568 00:12:18.700320 NOTICE: BL31: v1.3(release):4fc40b1
569 00:12:18.708155 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 00:12:18.708620 NOTICE: BL31: G12A normal boot!
571 00:12:18.733551 NOTICE: BL31: BL33 decompress pass
572 00:12:18.739193 ERROR: Error initializing runtime service opteed_fast
573 00:12:19.972438
574 00:12:19.973120
575 00:12:19.981618 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 00:12:19.982151
577 00:12:19.982611 Model: Libre Computer AML-A311D-CC Alta
578 00:12:20.189357 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 00:12:20.212616 DRAM: 2 GiB (effective 3.8 GiB)
580 00:12:20.355645 Core: 408 devices, 31 uclasses, devicetree: separate
581 00:12:20.361412 WDT: Not starting watchdog@f0d0
582 00:12:20.393753 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 00:12:20.406011 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 00:12:20.411122 ** Bad device specification mmc 0 **
585 00:12:20.421389 Card did not respond to voltage select! : -110
586 00:12:20.429137 ** Bad device specification mmc 0 **
587 00:12:20.429570 Couldn't find partition mmc 0
588 00:12:20.437467 Card did not respond to voltage select! : -110
589 00:12:20.442926 ** Bad device specification mmc 0 **
590 00:12:20.443527 Couldn't find partition mmc 0
591 00:12:20.448039 Error: could not access storage.
592 00:12:20.790700 Net: eth0: ethernet@ff3f0000
593 00:12:20.791386 starting USB...
594 00:12:21.152120 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 00:12:21.152524 Starting the controller
596 00:12:21.155247 USB XHCI 1.10
597 00:12:22.763244 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 00:12:22.763931 bl2_stage_init 0x01
599 00:12:22.764455 bl2_stage_init 0x81
600 00:12:22.768684 hw id: 0x0000 - pwm id 0x01
601 00:12:22.769188 bl2_stage_init 0xc1
602 00:12:22.769647 bl2_stage_init 0x02
603 00:12:22.770096
604 00:12:22.774463 L0:00000000
605 00:12:22.774977 L1:20000703
606 00:12:22.775432 L2:00008067
607 00:12:22.775881 L3:14000000
608 00:12:22.777234 B2:00402000
609 00:12:22.777717 B1:e0f83180
610 00:12:22.778162
611 00:12:22.778603 TE: 58124
612 00:12:22.779042
613 00:12:22.788223 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 00:12:22.788735
615 00:12:22.789189 Board ID = 1
616 00:12:22.789630 Set A53 clk to 24M
617 00:12:22.790068 Set A73 clk to 24M
618 00:12:22.793872 Set clk81 to 24M
619 00:12:22.794361 A53 clk: 1200 MHz
620 00:12:22.794808 A73 clk: 1200 MHz
621 00:12:22.799456 CLK81: 166.6M
622 00:12:22.799944 smccc: 00012a92
623 00:12:22.805030 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 00:12:22.805524 board id: 1
625 00:12:22.814025 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 00:12:22.824494 fw parse done
627 00:12:22.830453 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 00:12:22.872989 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 00:12:22.883935 PIEI prepare done
630 00:12:22.884484 fastboot data load
631 00:12:22.884938 fastboot data verify
632 00:12:22.889525 verify result: 266
633 00:12:22.895155 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 00:12:22.895653 LPDDR4 probe
635 00:12:22.896150 ddr clk to 1584MHz
636 00:12:22.903067 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 00:12:22.940562
638 00:12:22.941148 dmc_version 0001
639 00:12:22.947046 Check phy result
640 00:12:22.952981 INFO : End of CA training
641 00:12:22.953475 INFO : End of initialization
642 00:12:22.958572 INFO : Training has run successfully!
643 00:12:22.959056 Check phy result
644 00:12:22.964083 INFO : End of initialization
645 00:12:22.964573 INFO : End of read enable training
646 00:12:22.969733 INFO : End of fine write leveling
647 00:12:22.975483 INFO : End of Write leveling coarse delay
648 00:12:22.976019 INFO : Training has run successfully!
649 00:12:22.976478 Check phy result
650 00:12:22.980979 INFO : End of initialization
651 00:12:22.981465 INFO : End of read dq deskew training
652 00:12:22.986550 INFO : End of MPR read delay center optimization
653 00:12:22.992143 INFO : End of write delay center optimization
654 00:12:22.997806 INFO : End of read delay center optimization
655 00:12:22.998305 INFO : End of max read latency training
656 00:12:23.003543 INFO : Training has run successfully!
657 00:12:23.004079 1D training succeed
658 00:12:23.012557 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 00:12:23.060244 Check phy result
660 00:12:23.060752 INFO : End of initialization
661 00:12:23.081729 INFO : End of 2D read delay Voltage center optimization
662 00:12:23.101835 INFO : End of 2D read delay Voltage center optimization
663 00:12:23.152982 INFO : End of 2D write delay Voltage center optimization
664 00:12:23.202970 INFO : End of 2D write delay Voltage center optimization
665 00:12:23.208525 INFO : Training has run successfully!
666 00:12:23.209018
667 00:12:23.209472 channel==0
668 00:12:23.214215 RxClkDly_Margin_A0==88 ps 9
669 00:12:23.214714 TxDqDly_Margin_A0==98 ps 10
670 00:12:23.217573 RxClkDly_Margin_A1==88 ps 9
671 00:12:23.218053 TxDqDly_Margin_A1==98 ps 10
672 00:12:23.223196 TrainedVREFDQ_A0==74
673 00:12:23.223699 TrainedVREFDQ_A1==74
674 00:12:23.224252 VrefDac_Margin_A0==25
675 00:12:23.228721 DeviceVref_Margin_A0==40
676 00:12:23.229214 VrefDac_Margin_A1==25
677 00:12:23.234363 DeviceVref_Margin_A1==40
678 00:12:23.234845
679 00:12:23.235294
680 00:12:23.235739 channel==1
681 00:12:23.236219 RxClkDly_Margin_A0==98 ps 10
682 00:12:23.239868 TxDqDly_Margin_A0==88 ps 9
683 00:12:23.240387 RxClkDly_Margin_A1==98 ps 10
684 00:12:23.245520 TxDqDly_Margin_A1==98 ps 10
685 00:12:23.246011 TrainedVREFDQ_A0==77
686 00:12:23.246464 TrainedVREFDQ_A1==77
687 00:12:23.251135 VrefDac_Margin_A0==22
688 00:12:23.251621 DeviceVref_Margin_A0==37
689 00:12:23.256653 VrefDac_Margin_A1==22
690 00:12:23.257141 DeviceVref_Margin_A1==37
691 00:12:23.257585
692 00:12:23.262290 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 00:12:23.262822
694 00:12:23.290290 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
695 00:12:23.295865 2D training succeed
696 00:12:23.301514 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 00:12:23.302007 auto size-- 65535DDR cs0 size: 2048MB
698 00:12:23.307069 DDR cs1 size: 2048MB
699 00:12:23.307554 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 00:12:23.312628 cs0 DataBus test pass
701 00:12:23.313121 cs1 DataBus test pass
702 00:12:23.313567 cs0 AddrBus test pass
703 00:12:23.318236 cs1 AddrBus test pass
704 00:12:23.318725
705 00:12:23.319176 100bdlr_step_size ps== 420
706 00:12:23.319629 result report
707 00:12:23.323932 boot times 0Enable ddr reg access
708 00:12:23.331622 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 00:12:23.345044 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 00:12:23.917281 0.0;M3 CHK:0;cm4_sp_mode 0
711 00:12:23.917939 MVN_1=0x00000000
712 00:12:23.922702 MVN_2=0x00000000
713 00:12:23.928550 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 00:12:23.929106 OPS=0x10
715 00:12:23.929584 ring efuse init
716 00:12:23.930059 chipver efuse init
717 00:12:23.934001 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 00:12:23.939672 [0.018961 Inits done]
719 00:12:23.940239 secure task start!
720 00:12:23.940672 high task start!
721 00:12:23.944219 low task start!
722 00:12:23.944717 run into bl31
723 00:12:23.950910 NOTICE: BL31: v1.3(release):4fc40b1
724 00:12:23.958841 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 00:12:23.959351 NOTICE: BL31: G12A normal boot!
726 00:12:23.984011 NOTICE: BL31: BL33 decompress pass
727 00:12:23.989675 ERROR: Error initializing runtime service opteed_fast
728 00:12:25.222920
729 00:12:25.223596
730 00:12:25.231087 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 00:12:25.231645
732 00:12:25.232147 Model: Libre Computer AML-A311D-CC Alta
733 00:12:25.439659 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 00:12:25.462858 DRAM: 2 GiB (effective 3.8 GiB)
735 00:12:25.605885 Core: 408 devices, 31 uclasses, devicetree: separate
736 00:12:25.611762 WDT: Not starting watchdog@f0d0
737 00:12:25.644203 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 00:12:25.656312 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 00:12:25.660539 ** Bad device specification mmc 0 **
740 00:12:25.671663 Card did not respond to voltage select! : -110
741 00:12:25.679152 ** Bad device specification mmc 0 **
742 00:12:25.679568 Couldn't find partition mmc 0
743 00:12:25.687543 Card did not respond to voltage select! : -110
744 00:12:25.693084 ** Bad device specification mmc 0 **
745 00:12:25.693431 Couldn't find partition mmc 0
746 00:12:25.697659 Error: could not access storage.
747 00:12:26.040490 Net: eth0: ethernet@ff3f0000
748 00:12:26.041103 starting USB...
749 00:12:26.292398 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 00:12:26.292992 Starting the controller
751 00:12:26.299247 USB XHCI 1.10
752 00:12:28.463330 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 00:12:28.463745 bl2_stage_init 0x01
754 00:12:28.463967 bl2_stage_init 0x81
755 00:12:28.468925 hw id: 0x0000 - pwm id 0x01
756 00:12:28.469251 bl2_stage_init 0xc1
757 00:12:28.469465 bl2_stage_init 0x02
758 00:12:28.469685
759 00:12:28.474591 L0:00000000
760 00:12:28.474904 L1:20000703
761 00:12:28.475126 L2:00008067
762 00:12:28.475333 L3:14000000
763 00:12:28.480296 B2:00402000
764 00:12:28.480617 B1:e0f83180
765 00:12:28.480832
766 00:12:28.481052 TE: 58167
767 00:12:28.481270
768 00:12:28.485706 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 00:12:28.486037
770 00:12:28.486247 Board ID = 1
771 00:12:28.491358 Set A53 clk to 24M
772 00:12:28.491804 Set A73 clk to 24M
773 00:12:28.492165 Set clk81 to 24M
774 00:12:28.496937 A53 clk: 1200 MHz
775 00:12:28.497369 A73 clk: 1200 MHz
776 00:12:28.497607 CLK81: 166.6M
777 00:12:28.497810 smccc: 00012abe
778 00:12:28.502558 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 00:12:28.508185 board id: 1
780 00:12:28.513458 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 00:12:28.524730 fw parse done
782 00:12:28.530189 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 00:12:28.573322 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 00:12:28.584205 PIEI prepare done
785 00:12:28.584793 fastboot data load
786 00:12:28.585068 fastboot data verify
787 00:12:28.590007 verify result: 266
788 00:12:28.595415 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 00:12:28.595783 LPDDR4 probe
790 00:12:28.596025 ddr clk to 1584MHz
791 00:12:28.602401 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 00:12:28.640754
793 00:12:28.641323 dmc_version 0001
794 00:12:28.646431 Check phy result
795 00:12:28.653313 INFO : End of CA training
796 00:12:28.653657 INFO : End of initialization
797 00:12:28.658669 INFO : Training has run successfully!
798 00:12:28.658960 Check phy result
799 00:12:28.664273 INFO : End of initialization
800 00:12:28.664564 INFO : End of read enable training
801 00:12:28.669875 INFO : End of fine write leveling
802 00:12:28.675497 INFO : End of Write leveling coarse delay
803 00:12:28.675789 INFO : Training has run successfully!
804 00:12:28.676027 Check phy result
805 00:12:28.681200 INFO : End of initialization
806 00:12:28.681490 INFO : End of read dq deskew training
807 00:12:28.686736 INFO : End of MPR read delay center optimization
808 00:12:28.692323 INFO : End of write delay center optimization
809 00:12:28.697902 INFO : End of read delay center optimization
810 00:12:28.698186 INFO : End of max read latency training
811 00:12:28.703507 INFO : Training has run successfully!
812 00:12:28.703799 1D training succeed
813 00:12:28.712484 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 00:12:28.760377 Check phy result
815 00:12:28.760755 INFO : End of initialization
816 00:12:28.781086 INFO : End of 2D read delay Voltage center optimization
817 00:12:28.801871 INFO : End of 2D read delay Voltage center optimization
818 00:12:28.853797 INFO : End of 2D write delay Voltage center optimization
819 00:12:28.903297 INFO : End of 2D write delay Voltage center optimization
820 00:12:28.908694 INFO : Training has run successfully!
821 00:12:28.908983
822 00:12:28.909199 channel==0
823 00:12:28.914346 RxClkDly_Margin_A0==88 ps 9
824 00:12:28.914642 TxDqDly_Margin_A0==98 ps 10
825 00:12:28.919945 RxClkDly_Margin_A1==88 ps 9
826 00:12:28.920253 TxDqDly_Margin_A1==88 ps 9
827 00:12:28.920460 TrainedVREFDQ_A0==74
828 00:12:28.925547 TrainedVREFDQ_A1==74
829 00:12:28.925827 VrefDac_Margin_A0==25
830 00:12:28.926033 DeviceVref_Margin_A0==40
831 00:12:28.931249 VrefDac_Margin_A1==25
832 00:12:28.931531 DeviceVref_Margin_A1==40
833 00:12:28.931733
834 00:12:28.931936
835 00:12:28.932170 channel==1
836 00:12:28.936718 RxClkDly_Margin_A0==98 ps 10
837 00:12:28.936987 TxDqDly_Margin_A0==98 ps 10
838 00:12:28.942323 RxClkDly_Margin_A1==88 ps 9
839 00:12:28.942594 TxDqDly_Margin_A1==88 ps 9
840 00:12:28.947954 TrainedVREFDQ_A0==77
841 00:12:28.948247 TrainedVREFDQ_A1==77
842 00:12:28.948458 VrefDac_Margin_A0==22
843 00:12:28.953525 DeviceVref_Margin_A0==37
844 00:12:28.953811 VrefDac_Margin_A1==24
845 00:12:28.959215 DeviceVref_Margin_A1==37
846 00:12:28.959494
847 00:12:28.959703 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 00:12:28.959907
849 00:12:28.992705 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
850 00:12:28.993080 2D training succeed
851 00:12:28.998349 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 00:12:29.003972 auto size-- 65535DDR cs0 size: 2048MB
853 00:12:29.004286 DDR cs1 size: 2048MB
854 00:12:29.009514 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 00:12:29.009813 cs0 DataBus test pass
856 00:12:29.015218 cs1 DataBus test pass
857 00:12:29.015499 cs0 AddrBus test pass
858 00:12:29.015705 cs1 AddrBus test pass
859 00:12:29.015912
860 00:12:29.020720 100bdlr_step_size ps== 420
861 00:12:29.021010 result report
862 00:12:29.026318 boot times 0Enable ddr reg access
863 00:12:29.031184 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 00:12:29.044871 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 00:12:29.617006 0.0;M3 CHK:0;cm4_sp_mode 0
866 00:12:29.617433 MVN_1=0x00000000
867 00:12:29.622584 MVN_2=0x00000000
868 00:12:29.628319 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 00:12:29.628765 OPS=0x10
870 00:12:29.629005 ring efuse init
871 00:12:29.629211 chipver efuse init
872 00:12:29.633842 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 00:12:29.639413 [0.018961 Inits done]
874 00:12:29.639842 secure task start!
875 00:12:29.640192 high task start!
876 00:12:29.644032 low task start!
877 00:12:29.644305 run into bl31
878 00:12:29.650667 NOTICE: BL31: v1.3(release):4fc40b1
879 00:12:29.657530 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 00:12:29.657951 NOTICE: BL31: G12A normal boot!
881 00:12:29.683888 NOTICE: BL31: BL33 decompress pass
882 00:12:29.689520 ERROR: Error initializing runtime service opteed_fast
883 00:12:30.922706
884 00:12:30.923123
885 00:12:30.930895 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 00:12:30.931336
887 00:12:30.931661 Model: Libre Computer AML-A311D-CC Alta
888 00:12:31.139487 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 00:12:31.162910 DRAM: 2 GiB (effective 3.8 GiB)
890 00:12:31.305782 Core: 408 devices, 31 uclasses, devicetree: separate
891 00:12:31.311900 WDT: Not starting watchdog@f0d0
892 00:12:31.343930 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 00:12:31.356359 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 00:12:31.361351 ** Bad device specification mmc 0 **
895 00:12:31.371674 Card did not respond to voltage select! : -110
896 00:12:31.378358 ** Bad device specification mmc 0 **
897 00:12:31.378858 Couldn't find partition mmc 0
898 00:12:31.387664 Card did not respond to voltage select! : -110
899 00:12:31.393183 ** Bad device specification mmc 0 **
900 00:12:31.393692 Couldn't find partition mmc 0
901 00:12:31.397327 Error: could not access storage.
902 00:12:31.741515 Net: eth0: ethernet@ff3f0000
903 00:12:31.742140 starting USB...
904 00:12:31.993713 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 00:12:31.994324 Starting the controller
906 00:12:32.000278 USB XHCI 1.10
907 00:12:33.863324 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 00:12:33.863977 bl2_stage_init 0x01
909 00:12:33.864492 bl2_stage_init 0x81
910 00:12:33.869019 hw id: 0x0000 - pwm id 0x01
911 00:12:33.869510 bl2_stage_init 0xc1
912 00:12:33.869963 bl2_stage_init 0x02
913 00:12:33.870410
914 00:12:33.874414 L0:00000000
915 00:12:33.874957 L1:20000703
916 00:12:33.875413 L2:00008067
917 00:12:33.875858 L3:14000000
918 00:12:33.880035 B2:00402000
919 00:12:33.880524 B1:e0f83180
920 00:12:33.880975
921 00:12:33.881426 TE: 58167
922 00:12:33.881868
923 00:12:33.885614 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 00:12:33.886123
925 00:12:33.886578 Board ID = 1
926 00:12:33.891262 Set A53 clk to 24M
927 00:12:33.891745 Set A73 clk to 24M
928 00:12:33.892232 Set clk81 to 24M
929 00:12:33.896849 A53 clk: 1200 MHz
930 00:12:33.897333 A73 clk: 1200 MHz
931 00:12:33.897778 CLK81: 166.6M
932 00:12:33.898216 smccc: 00012abd
933 00:12:33.902434 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 00:12:33.908030 board id: 1
935 00:12:33.914018 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 00:12:33.924538 fw parse done
937 00:12:33.930657 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 00:12:33.973133 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 00:12:33.984039 PIEI prepare done
940 00:12:33.984568 fastboot data load
941 00:12:33.985010 fastboot data verify
942 00:12:33.989610 verify result: 266
943 00:12:33.995226 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 00:12:33.995705 LPDDR4 probe
945 00:12:33.996173 ddr clk to 1584MHz
946 00:12:34.003216 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 00:12:34.040484
948 00:12:34.041020 dmc_version 0001
949 00:12:34.047183 Check phy result
950 00:12:34.053116 INFO : End of CA training
951 00:12:34.053600 INFO : End of initialization
952 00:12:34.058708 INFO : Training has run successfully!
953 00:12:34.059191 Check phy result
954 00:12:34.064303 INFO : End of initialization
955 00:12:34.064791 INFO : End of read enable training
956 00:12:34.067615 INFO : End of fine write leveling
957 00:12:34.073185 INFO : End of Write leveling coarse delay
958 00:12:34.078795 INFO : Training has run successfully!
959 00:12:34.079310 Check phy result
960 00:12:34.079737 INFO : End of initialization
961 00:12:34.084419 INFO : End of read dq deskew training
962 00:12:34.090095 INFO : End of MPR read delay center optimization
963 00:12:34.090616 INFO : End of write delay center optimization
964 00:12:34.095448 INFO : End of read delay center optimization
965 00:12:34.101248 INFO : End of max read latency training
966 00:12:34.101774 INFO : Training has run successfully!
967 00:12:34.106790 1D training succeed
968 00:12:34.113164 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 00:12:34.159426 Check phy result
970 00:12:34.159962 INFO : End of initialization
971 00:12:34.182670 INFO : End of 2D read delay Voltage center optimization
972 00:12:34.203197 INFO : End of 2D read delay Voltage center optimization
973 00:12:34.255263 INFO : End of 2D write delay Voltage center optimization
974 00:12:34.304422 INFO : End of 2D write delay Voltage center optimization
975 00:12:34.310221 INFO : Training has run successfully!
976 00:12:34.310751
977 00:12:34.311188 channel==0
978 00:12:34.315700 RxClkDly_Margin_A0==88 ps 9
979 00:12:34.316303 TxDqDly_Margin_A0==98 ps 10
980 00:12:34.321335 RxClkDly_Margin_A1==88 ps 9
981 00:12:34.321859 TxDqDly_Margin_A1==98 ps 10
982 00:12:34.322289 TrainedVREFDQ_A0==74
983 00:12:34.326944 TrainedVREFDQ_A1==74
984 00:12:34.327469 VrefDac_Margin_A0==25
985 00:12:34.327895 DeviceVref_Margin_A0==40
986 00:12:34.332470 VrefDac_Margin_A1==24
987 00:12:34.332988 DeviceVref_Margin_A1==40
988 00:12:34.333410
989 00:12:34.333824
990 00:12:34.338244 channel==1
991 00:12:34.338786 RxClkDly_Margin_A0==98 ps 10
992 00:12:34.339228 TxDqDly_Margin_A0==98 ps 10
993 00:12:34.343661 RxClkDly_Margin_A1==98 ps 10
994 00:12:34.344212 TxDqDly_Margin_A1==88 ps 9
995 00:12:34.349325 TrainedVREFDQ_A0==77
996 00:12:34.349854 TrainedVREFDQ_A1==77
997 00:12:34.350291 VrefDac_Margin_A0==22
998 00:12:34.355008 DeviceVref_Margin_A0==37
999 00:12:34.355534 VrefDac_Margin_A1==22
1000 00:12:34.360504 DeviceVref_Margin_A1==37
1001 00:12:34.361044
1002 00:12:34.361451 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 00:12:34.366210
1004 00:12:34.394188 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
1005 00:12:34.394782 2D training succeed
1006 00:12:34.399745 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 00:12:34.405062 auto size-- 65535DDR cs0 size: 2048MB
1008 00:12:34.405609 DDR cs1 size: 2048MB
1009 00:12:34.410835 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 00:12:34.411344 cs0 DataBus test pass
1011 00:12:34.416383 cs1 DataBus test pass
1012 00:12:34.416898 cs0 AddrBus test pass
1013 00:12:34.417327 cs1 AddrBus test pass
1014 00:12:34.417741
1015 00:12:34.422104 100bdlr_step_size ps== 420
1016 00:12:34.422637 result report
1017 00:12:34.427588 boot times 0Enable ddr reg access
1018 00:12:34.433024 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 00:12:34.446503 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 00:12:35.020217 0.0;M3 CHK:0;cm4_sp_mode 0
1021 00:12:35.020836 MVN_1=0x00000000
1022 00:12:35.025744 MVN_2=0x00000000
1023 00:12:35.031532 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 00:12:35.032096 OPS=0x10
1025 00:12:35.032548 ring efuse init
1026 00:12:35.032972 chipver efuse init
1027 00:12:35.039673 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 00:12:35.040232 [0.018961 Inits done]
1029 00:12:35.047426 secure task start!
1030 00:12:35.047960 high task start!
1031 00:12:35.048429 low task start!
1032 00:12:35.048886 run into bl31
1033 00:12:35.053995 NOTICE: BL31: v1.3(release):4fc40b1
1034 00:12:35.061072 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 00:12:35.061420 NOTICE: BL31: G12A normal boot!
1036 00:12:35.087131 NOTICE: BL31: BL33 decompress pass
1037 00:12:35.092638 ERROR: Error initializing runtime service opteed_fast
1038 00:12:36.325532
1039 00:12:36.325952
1040 00:12:36.333924 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 00:12:36.334365
1042 00:12:36.334717 Model: Libre Computer AML-A311D-CC Alta
1043 00:12:36.542391 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 00:12:36.565762 DRAM: 2 GiB (effective 3.8 GiB)
1045 00:12:36.708729 Core: 408 devices, 31 uclasses, devicetree: separate
1046 00:12:36.714591 WDT: Not starting watchdog@f0d0
1047 00:12:36.746845 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 00:12:36.759286 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 00:12:36.764299 ** Bad device specification mmc 0 **
1050 00:12:36.774635 Card did not respond to voltage select! : -110
1051 00:12:36.782325 ** Bad device specification mmc 0 **
1052 00:12:36.782635 Couldn't find partition mmc 0
1053 00:12:36.790651 Card did not respond to voltage select! : -110
1054 00:12:36.796233 ** Bad device specification mmc 0 **
1055 00:12:36.796542 Couldn't find partition mmc 0
1056 00:12:36.801314 Error: could not access storage.
1057 00:12:37.144748 Net: eth0: ethernet@ff3f0000
1058 00:12:37.145334 starting USB...
1059 00:12:37.396530 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 00:12:37.396904 Starting the controller
1061 00:12:37.403470 USB XHCI 1.10
1062 00:12:38.957564 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 00:12:38.965857 scanning usb for storage devices... 0 Storage Device(s) found
1065 00:12:39.017512 Hit any key to stop autoboot: 1
1066 00:12:39.018319 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1067 00:12:39.018939 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1068 00:12:39.019441 Setting prompt string to ['=>']
1069 00:12:39.019946 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1070 00:12:39.033313 0
1071 00:12:39.034215 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 00:12:39.034737 Sending with 10 millisecond of delay
1074 00:12:40.170232 => setenv autoload no
1075 00:12:40.181037 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1076 00:12:40.186447 setenv autoload no
1077 00:12:40.187241 Sending with 10 millisecond of delay
1079 00:12:41.983899 => setenv initrd_high 0xffffffff
1080 00:12:41.994722 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1081 00:12:41.995589 setenv initrd_high 0xffffffff
1082 00:12:41.996381 Sending with 10 millisecond of delay
1084 00:12:43.612915 => setenv fdt_high 0xffffffff
1085 00:12:43.623761 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1086 00:12:43.624728 setenv fdt_high 0xffffffff
1087 00:12:43.625502 Sending with 10 millisecond of delay
1089 00:12:43.917505 => dhcp
1090 00:12:43.928321 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1091 00:12:43.929242 dhcp
1092 00:12:43.929738 Speed: 1000, full duplex
1093 00:12:43.930194 BOOTP broadcast 1
1094 00:12:43.936327 DHCP client bound to address 192.168.6.27 (8 ms)
1095 00:12:43.937119 Sending with 10 millisecond of delay
1097 00:12:45.614275 => setenv serverip 192.168.6.2
1098 00:12:45.625137 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1099 00:12:45.626130 setenv serverip 192.168.6.2
1100 00:12:45.626919 Sending with 10 millisecond of delay
1102 00:12:49.355498 => tftpboot 0x01080000 949368/tftp-deploy-oat87_aq/kernel/uImage
1103 00:12:49.366447 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 00:12:49.367585 tftpboot 0x01080000 949368/tftp-deploy-oat87_aq/kernel/uImage
1105 00:12:49.368256 Speed: 1000, full duplex
1106 00:12:49.368867 Using ethernet@ff3f0000 device
1107 00:12:49.370306 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 00:12:49.374789 Filename '949368/tftp-deploy-oat87_aq/kernel/uImage'.
1109 00:12:49.378764 Load address: 0x1080000
1110 00:12:51.734217 Loading: *################################################## 36.1 MiB
1111 00:12:51.734834 15.3 MiB/s
1112 00:12:51.735239 done
1113 00:12:51.738734 Bytes transferred = 37880384 (2420240 hex)
1114 00:12:51.739520 Sending with 10 millisecond of delay
1116 00:12:56.435835 => tftpboot 0x08000000 949368/tftp-deploy-oat87_aq/ramdisk/ramdisk.cpio.gz.uboot
1117 00:12:56.446627 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1118 00:12:56.447388 tftpboot 0x08000000 949368/tftp-deploy-oat87_aq/ramdisk/ramdisk.cpio.gz.uboot
1119 00:12:56.447814 Speed: 1000, full duplex
1120 00:12:56.448254 Using ethernet@ff3f0000 device
1121 00:12:56.449363 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 00:12:56.461386 Filename '949368/tftp-deploy-oat87_aq/ramdisk/ramdisk.cpio.gz.uboot'.
1123 00:12:56.461833 Load address: 0x8000000
1124 00:13:05.805498 Loading: *##T ############################################### UDP wrong checksum 0000000f 000075e1
1125 00:13:10.806394 T UDP wrong checksum 0000000f 000075e1
1126 00:13:20.809713 T T UDP wrong checksum 0000000f 000075e1
1127 00:13:26.947009 T UDP wrong checksum 000000ff 00009708
1128 00:13:26.999593 UDP wrong checksum 000000ff 000031fb
1129 00:13:39.607513 T T UDP wrong checksum 000000ff 00009b89
1130 00:13:39.680614 UDP wrong checksum 000000ff 0000207c
1131 00:13:40.813582 T UDP wrong checksum 0000000f 000075e1
1132 00:13:48.910417 T UDP wrong checksum 000000ff 00000333
1133 00:13:48.920766 UDP wrong checksum 000000ff 00009825
1134 00:13:55.817765 T
1135 00:13:55.818215 Retry count exceeded; starting again
1137 00:13:55.819177 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
1140 00:13:55.820263 end: 2.4 uboot-commands (duration 00:01:55) [common]
1142 00:13:55.821038 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1144 00:13:55.821666 end: 2 uboot-action (duration 00:01:55) [common]
1146 00:13:55.822569 Cleaning after the job
1147 00:13:55.822951 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949368/tftp-deploy-oat87_aq/ramdisk
1148 00:13:55.823911 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949368/tftp-deploy-oat87_aq/kernel
1149 00:13:55.846644 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949368/tftp-deploy-oat87_aq/dtb
1150 00:13:55.847725 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949368/tftp-deploy-oat87_aq/modules
1151 00:13:55.883489 start: 4.1 power-off (timeout 00:00:30) [common]
1152 00:13:55.884266 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1153 00:13:55.917633 >> OK - accepted request
1154 00:13:55.920202 Returned 0 in 0 seconds
1155 00:13:56.021165 end: 4.1 power-off (duration 00:00:00) [common]
1157 00:13:56.022215 start: 4.2 read-feedback (timeout 00:10:00) [common]
1158 00:13:56.022903 Listened to connection for namespace 'common' for up to 1s
1159 00:13:57.023329 Finalising connection for namespace 'common'
1160 00:13:57.023820 Disconnecting from shell: Finalise
1161 00:13:57.024147 =>
1162 00:13:57.124804 end: 4.2 read-feedback (duration 00:00:01) [common]
1163 00:13:57.125278 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949368
1164 00:13:57.766716 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949368
1165 00:13:57.767338 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.