Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:30:23.739387 lava-dispatcher, installed at version: 2024.01
2 01:30:23.740227 start: 0 validate
3 01:30:23.740713 Start time: 2024-11-07 01:30:23.740681+00:00 (UTC)
4 01:30:23.741284 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:30:23.741845 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:30:23.782022 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:30:23.782628 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 01:30:23.811695 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:30:23.812404 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:30:23.840823 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:30:23.841355 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:30:23.877578 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:30:23.878102 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
14 01:30:23.916700 validate duration: 0.18
16 01:30:23.917619 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:30:23.917979 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:30:23.918346 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:30:23.919030 Not decompressing ramdisk as can be used compressed.
20 01:30:23.919501 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:30:23.919812 saving as /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/ramdisk/initrd.cpio.gz
22 01:30:23.920147 total size: 5628169 (5 MB)
23 01:30:23.956585 progress 0 % (0 MB)
24 01:30:23.961377 progress 5 % (0 MB)
25 01:30:23.966002 progress 10 % (0 MB)
26 01:30:23.970032 progress 15 % (0 MB)
27 01:30:23.974597 progress 20 % (1 MB)
28 01:30:23.978605 progress 25 % (1 MB)
29 01:30:23.983216 progress 30 % (1 MB)
30 01:30:23.987708 progress 35 % (1 MB)
31 01:30:23.991618 progress 40 % (2 MB)
32 01:30:23.995964 progress 45 % (2 MB)
33 01:30:23.999898 progress 50 % (2 MB)
34 01:30:24.004608 progress 55 % (2 MB)
35 01:30:24.008655 progress 60 % (3 MB)
36 01:30:24.012314 progress 65 % (3 MB)
37 01:30:24.016460 progress 70 % (3 MB)
38 01:30:24.020125 progress 75 % (4 MB)
39 01:30:24.024180 progress 80 % (4 MB)
40 01:30:24.027805 progress 85 % (4 MB)
41 01:30:24.031879 progress 90 % (4 MB)
42 01:30:24.035824 progress 95 % (5 MB)
43 01:30:24.039152 progress 100 % (5 MB)
44 01:30:24.039826 5 MB downloaded in 0.12 s (44.86 MB/s)
45 01:30:24.040418 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:30:24.041363 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:30:24.041656 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:30:24.041931 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:30:24.042419 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/kernel/Image
51 01:30:24.042687 saving as /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/kernel/Image
52 01:30:24.042901 total size: 37880320 (36 MB)
53 01:30:24.043114 No compression specified
54 01:30:24.078743 progress 0 % (0 MB)
55 01:30:24.104200 progress 5 % (1 MB)
56 01:30:24.128525 progress 10 % (3 MB)
57 01:30:24.152260 progress 15 % (5 MB)
58 01:30:24.176284 progress 20 % (7 MB)
59 01:30:24.200292 progress 25 % (9 MB)
60 01:30:24.223963 progress 30 % (10 MB)
61 01:30:24.248088 progress 35 % (12 MB)
62 01:30:24.272017 progress 40 % (14 MB)
63 01:30:24.295967 progress 45 % (16 MB)
64 01:30:24.320209 progress 50 % (18 MB)
65 01:30:24.344158 progress 55 % (19 MB)
66 01:30:24.368118 progress 60 % (21 MB)
67 01:30:24.392210 progress 65 % (23 MB)
68 01:30:24.416321 progress 70 % (25 MB)
69 01:30:24.440475 progress 75 % (27 MB)
70 01:30:24.464225 progress 80 % (28 MB)
71 01:30:24.488479 progress 85 % (30 MB)
72 01:30:24.512209 progress 90 % (32 MB)
73 01:30:24.536685 progress 95 % (34 MB)
74 01:30:24.560276 progress 100 % (36 MB)
75 01:30:24.560784 36 MB downloaded in 0.52 s (69.76 MB/s)
76 01:30:24.561263 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:30:24.562083 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:30:24.562364 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:30:24.562630 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:30:24.563105 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:30:24.563385 saving as /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:30:24.563597 total size: 54703 (0 MB)
84 01:30:24.563807 No compression specified
85 01:30:24.603275 progress 59 % (0 MB)
86 01:30:24.604190 progress 100 % (0 MB)
87 01:30:24.604768 0 MB downloaded in 0.04 s (1.27 MB/s)
88 01:30:24.605356 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:30:24.606259 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:30:24.606534 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:30:24.606801 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:30:24.607270 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:30:24.607522 saving as /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/nfsrootfs/full.rootfs.tar
95 01:30:24.607729 total size: 120894716 (115 MB)
96 01:30:24.607940 Using unxz to decompress xz
97 01:30:24.641811 progress 0 % (0 MB)
98 01:30:25.435896 progress 5 % (5 MB)
99 01:30:26.275202 progress 10 % (11 MB)
100 01:30:27.071379 progress 15 % (17 MB)
101 01:30:27.808117 progress 20 % (23 MB)
102 01:30:28.403225 progress 25 % (28 MB)
103 01:30:29.226479 progress 30 % (34 MB)
104 01:30:30.019487 progress 35 % (40 MB)
105 01:30:30.385117 progress 40 % (46 MB)
106 01:30:30.771566 progress 45 % (51 MB)
107 01:30:31.532375 progress 50 % (57 MB)
108 01:30:32.425162 progress 55 % (63 MB)
109 01:30:33.213574 progress 60 % (69 MB)
110 01:30:34.049356 progress 65 % (74 MB)
111 01:30:34.997715 progress 70 % (80 MB)
112 01:30:35.974078 progress 75 % (86 MB)
113 01:30:36.816657 progress 80 % (92 MB)
114 01:30:37.576511 progress 85 % (98 MB)
115 01:30:38.429639 progress 90 % (103 MB)
116 01:30:39.213229 progress 95 % (109 MB)
117 01:30:40.079997 progress 100 % (115 MB)
118 01:30:40.094878 115 MB downloaded in 15.49 s (7.44 MB/s)
119 01:30:40.095735 end: 1.4.1 http-download (duration 00:00:15) [common]
121 01:30:40.097366 end: 1.4 download-retry (duration 00:00:15) [common]
122 01:30:40.097879 start: 1.5 download-retry (timeout 00:09:44) [common]
123 01:30:40.098385 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 01:30:40.099330 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/modules.tar.xz
125 01:30:40.099804 saving as /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/modules/modules.tar
126 01:30:40.100250 total size: 11768476 (11 MB)
127 01:30:40.100664 Using unxz to decompress xz
128 01:30:40.143387 progress 0 % (0 MB)
129 01:30:40.210951 progress 5 % (0 MB)
130 01:30:40.286511 progress 10 % (1 MB)
131 01:30:40.382359 progress 15 % (1 MB)
132 01:30:40.478961 progress 20 % (2 MB)
133 01:30:40.558698 progress 25 % (2 MB)
134 01:30:40.636403 progress 30 % (3 MB)
135 01:30:40.716587 progress 35 % (3 MB)
136 01:30:40.797095 progress 40 % (4 MB)
137 01:30:40.873570 progress 45 % (5 MB)
138 01:30:40.959244 progress 50 % (5 MB)
139 01:30:41.041753 progress 55 % (6 MB)
140 01:30:41.127274 progress 60 % (6 MB)
141 01:30:41.208962 progress 65 % (7 MB)
142 01:30:41.291330 progress 70 % (7 MB)
143 01:30:41.375684 progress 75 % (8 MB)
144 01:30:41.459651 progress 80 % (9 MB)
145 01:30:41.540257 progress 85 % (9 MB)
146 01:30:41.623725 progress 90 % (10 MB)
147 01:30:41.702530 progress 95 % (10 MB)
148 01:30:41.779703 progress 100 % (11 MB)
149 01:30:41.790222 11 MB downloaded in 1.69 s (6.64 MB/s)
150 01:30:41.791138 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:30:41.792956 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:30:41.793530 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 01:30:41.794105 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 01:30:58.966219 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/949385/extract-nfsrootfs-butlqj7g
156 01:30:58.966826 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 01:30:58.967176 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 01:30:58.967911 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8
159 01:30:58.968525 makedir: /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin
160 01:30:58.968982 makedir: /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/tests
161 01:30:58.969440 makedir: /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/results
162 01:30:58.969826 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-add-keys
163 01:30:58.970565 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-add-sources
164 01:30:58.971255 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-background-process-start
165 01:30:58.971922 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-background-process-stop
166 01:30:58.972603 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-common-functions
167 01:30:58.973144 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-echo-ipv4
168 01:30:58.973674 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-install-packages
169 01:30:58.974191 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-installed-packages
170 01:30:58.974710 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-os-build
171 01:30:58.975227 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-probe-channel
172 01:30:58.975769 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-probe-ip
173 01:30:58.976342 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-target-ip
174 01:30:58.976854 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-target-mac
175 01:30:58.977395 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-target-storage
176 01:30:58.977908 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-test-case
177 01:30:58.978422 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-test-event
178 01:30:58.978959 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-test-feedback
179 01:30:58.979466 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-test-raise
180 01:30:58.979976 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-test-reference
181 01:30:58.980576 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-test-runner
182 01:30:58.981144 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-test-set
183 01:30:58.981689 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-test-shell
184 01:30:58.982219 Updating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-add-keys (debian)
185 01:30:58.982808 Updating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-add-sources (debian)
186 01:30:58.983460 Updating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-install-packages (debian)
187 01:30:58.984077 Updating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-installed-packages (debian)
188 01:30:58.984646 Updating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/bin/lava-os-build (debian)
189 01:30:58.985121 Creating /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/environment
190 01:30:58.985519 LAVA metadata
191 01:30:58.985787 - LAVA_JOB_ID=949385
192 01:30:58.986001 - LAVA_DISPATCHER_IP=192.168.6.2
193 01:30:58.986386 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 01:30:58.987387 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 01:30:58.987729 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 01:30:58.987939 skipped lava-vland-overlay
197 01:30:58.988217 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 01:30:58.988481 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 01:30:58.988706 skipped lava-multinode-overlay
200 01:30:58.988952 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 01:30:58.989205 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 01:30:58.989464 Loading test definitions
203 01:30:58.989751 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 01:30:58.989973 Using /lava-949385 at stage 0
205 01:30:58.991177 uuid=949385_1.6.2.4.1 testdef=None
206 01:30:58.991523 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 01:30:58.991798 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 01:30:58.993545 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 01:30:58.994379 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 01:30:58.996651 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 01:30:58.997544 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 01:30:58.999622 runner path: /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/0/tests/0_timesync-off test_uuid 949385_1.6.2.4.1
215 01:30:59.000384 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 01:30:59.001258 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 01:30:59.001493 Using /lava-949385 at stage 0
219 01:30:59.001869 Fetching tests from https://github.com/kernelci/test-definitions.git
220 01:30:59.002176 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/0/tests/1_kselftest-alsa'
221 01:31:02.453117 Running '/usr/bin/git checkout kernelci.org
222 01:31:02.801314 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 01:31:02.802870 uuid=949385_1.6.2.4.5 testdef=None
224 01:31:02.803298 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 01:31:02.804209 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 01:31:02.807508 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 01:31:02.808484 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 01:31:02.817012 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 01:31:02.818461 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 01:31:02.824554 runner path: /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/0/tests/1_kselftest-alsa test_uuid 949385_1.6.2.4.5
234 01:31:02.824912 BOARD='meson-g12b-a311d-libretech-cc'
235 01:31:02.825194 BRANCH='mainline'
236 01:31:02.825425 SKIPFILE='/dev/null'
237 01:31:02.825641 SKIP_INSTALL='True'
238 01:31:02.825854 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/kselftest.tar.xz'
239 01:31:02.826075 TST_CASENAME=''
240 01:31:02.826293 TST_CMDFILES='alsa'
241 01:31:02.827024 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 01:31:02.827919 Creating lava-test-runner.conf files
244 01:31:02.828211 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949385/lava-overlay-y_ank2w8/lava-949385/0 for stage 0
245 01:31:02.829202 - 0_timesync-off
246 01:31:02.829553 - 1_kselftest-alsa
247 01:31:02.829982 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 01:31:02.830332 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 01:31:26.285885 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 01:31:26.286319 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 01:31:26.286581 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 01:31:26.286849 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 01:31:26.287114 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 01:31:26.901458 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 01:31:26.901939 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 01:31:26.902192 extracting modules file /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949385/extract-nfsrootfs-butlqj7g
257 01:31:28.281563 extracting modules file /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949385/extract-overlay-ramdisk-pk1kwrla/ramdisk
258 01:31:29.744741 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 01:31:29.745224 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 01:31:29.745471 [common] Applying overlay to NFS
261 01:31:29.745682 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949385/compress-overlay-xcl6flr0/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949385/extract-nfsrootfs-butlqj7g
262 01:31:32.490135 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 01:31:32.490601 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 01:31:32.490873 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 01:31:32.491103 Converting downloaded kernel to a uImage
266 01:31:32.491412 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/kernel/Image /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/kernel/uImage
267 01:31:32.925239 output: Image Name:
268 01:31:32.925655 output: Created: Thu Nov 7 01:31:32 2024
269 01:31:32.925881 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 01:31:32.926096 output: Data Size: 37880320 Bytes = 36992.50 KiB = 36.13 MiB
271 01:31:32.926300 output: Load Address: 01080000
272 01:31:32.926502 output: Entry Point: 01080000
273 01:31:32.926702 output:
274 01:31:32.927034 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 01:31:32.927306 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 01:31:32.927581 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 01:31:32.927843 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 01:31:32.928153 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 01:31:32.928399 Building ramdisk /var/lib/lava/dispatcher/tmp/949385/extract-overlay-ramdisk-pk1kwrla/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949385/extract-overlay-ramdisk-pk1kwrla/ramdisk
280 01:31:35.337295 >> 173443 blocks
281 01:31:42.989404 Adding RAMdisk u-boot header.
282 01:31:42.990063 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949385/extract-overlay-ramdisk-pk1kwrla/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949385/extract-overlay-ramdisk-pk1kwrla/ramdisk.cpio.gz.uboot
283 01:31:43.242000 output: Image Name:
284 01:31:43.242417 output: Created: Thu Nov 7 01:31:42 2024
285 01:31:43.242834 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 01:31:43.243247 output: Data Size: 24150387 Bytes = 23584.36 KiB = 23.03 MiB
287 01:31:43.243648 output: Load Address: 00000000
288 01:31:43.244131 output: Entry Point: 00000000
289 01:31:43.244546 output:
290 01:31:43.245589 rename /var/lib/lava/dispatcher/tmp/949385/extract-overlay-ramdisk-pk1kwrla/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/ramdisk/ramdisk.cpio.gz.uboot
291 01:31:43.246303 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 01:31:43.246853 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 01:31:43.247380 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 01:31:43.247843 No LXC device requested
295 01:31:43.248379 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 01:31:43.248894 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 01:31:43.249393 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 01:31:43.249800 Checking files for TFTP limit of 4294967296 bytes.
299 01:31:43.252465 end: 1 tftp-deploy (duration 00:01:19) [common]
300 01:31:43.253049 start: 2 uboot-action (timeout 00:05:00) [common]
301 01:31:43.253573 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 01:31:43.254071 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 01:31:43.254573 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 01:31:43.255100 Using kernel file from prepare-kernel: 949385/tftp-deploy-nuj4pwy4/kernel/uImage
305 01:31:43.255728 substitutions:
306 01:31:43.256170 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 01:31:43.256576 - {DTB_ADDR}: 0x01070000
308 01:31:43.256975 - {DTB}: 949385/tftp-deploy-nuj4pwy4/dtb/meson-g12b-a311d-libretech-cc.dtb
309 01:31:43.257377 - {INITRD}: 949385/tftp-deploy-nuj4pwy4/ramdisk/ramdisk.cpio.gz.uboot
310 01:31:43.257774 - {KERNEL_ADDR}: 0x01080000
311 01:31:43.258166 - {KERNEL}: 949385/tftp-deploy-nuj4pwy4/kernel/uImage
312 01:31:43.258555 - {LAVA_MAC}: None
313 01:31:43.258982 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/949385/extract-nfsrootfs-butlqj7g
314 01:31:43.259379 - {NFS_SERVER_IP}: 192.168.6.2
315 01:31:43.259766 - {PRESEED_CONFIG}: None
316 01:31:43.260185 - {PRESEED_LOCAL}: None
317 01:31:43.260577 - {RAMDISK_ADDR}: 0x08000000
318 01:31:43.260963 - {RAMDISK}: 949385/tftp-deploy-nuj4pwy4/ramdisk/ramdisk.cpio.gz.uboot
319 01:31:43.261347 - {ROOT_PART}: None
320 01:31:43.261730 - {ROOT}: None
321 01:31:43.262115 - {SERVER_IP}: 192.168.6.2
322 01:31:43.262496 - {TEE_ADDR}: 0x83000000
323 01:31:43.262879 - {TEE}: None
324 01:31:43.263260 Parsed boot commands:
325 01:31:43.263631 - setenv autoload no
326 01:31:43.264032 - setenv initrd_high 0xffffffff
327 01:31:43.264418 - setenv fdt_high 0xffffffff
328 01:31:43.264798 - dhcp
329 01:31:43.265178 - setenv serverip 192.168.6.2
330 01:31:43.265561 - tftpboot 0x01080000 949385/tftp-deploy-nuj4pwy4/kernel/uImage
331 01:31:43.265945 - tftpboot 0x08000000 949385/tftp-deploy-nuj4pwy4/ramdisk/ramdisk.cpio.gz.uboot
332 01:31:43.266330 - tftpboot 0x01070000 949385/tftp-deploy-nuj4pwy4/dtb/meson-g12b-a311d-libretech-cc.dtb
333 01:31:43.266713 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/949385/extract-nfsrootfs-butlqj7g,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 01:31:43.267108 - bootm 0x01080000 0x08000000 0x01070000
335 01:31:43.267609 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 01:31:43.269123 start: 2.3 connect-device (timeout 00:05:00) [common]
338 01:31:43.269545 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 01:31:43.283047 Setting prompt string to ['lava-test: # ']
340 01:31:43.285031 end: 2.3 connect-device (duration 00:00:00) [common]
341 01:31:43.285704 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 01:31:43.286288 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 01:31:43.286828 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 01:31:43.288033 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 01:31:43.321944 >> OK - accepted request
346 01:31:43.324071 Returned 0 in 0 seconds
347 01:31:43.425211 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 01:31:43.427222 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 01:31:43.427837 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 01:31:43.428424 Setting prompt string to ['Hit any key to stop autoboot']
352 01:31:43.428891 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 01:31:43.430574 Trying 192.168.56.21...
354 01:31:43.431117 Connected to conserv1.
355 01:31:43.431552 Escape character is '^]'.
356 01:31:43.432207
357 01:31:43.432707 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 01:31:43.433210
359 01:31:54.858499 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 01:31:54.859139 bl2_stage_init 0x01
361 01:31:54.859622 bl2_stage_init 0x81
362 01:31:54.864134 hw id: 0x0000 - pwm id 0x01
363 01:31:54.864651 bl2_stage_init 0xc1
364 01:31:54.865055 bl2_stage_init 0x02
365 01:31:54.865493
366 01:31:54.869495 L0:00000000
367 01:31:54.869985 L1:20000703
368 01:31:54.870382 L2:00008067
369 01:31:54.870773 L3:14000000
370 01:31:54.872541 B2:00402000
371 01:31:54.872983 B1:e0f83180
372 01:31:54.873391
373 01:31:54.873780 TE: 58124
374 01:31:54.874168
375 01:31:54.883761 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 01:31:54.884250
377 01:31:54.884649 Board ID = 1
378 01:31:54.885033 Set A53 clk to 24M
379 01:31:54.885417 Set A73 clk to 24M
380 01:31:54.889303 Set clk81 to 24M
381 01:31:54.889741 A53 clk: 1200 MHz
382 01:31:54.890130 A73 clk: 1200 MHz
383 01:31:54.894936 CLK81: 166.6M
384 01:31:54.895384 smccc: 00012a92
385 01:31:54.900518 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 01:31:54.900979 board id: 1
387 01:31:54.909021 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 01:31:54.919721 fw parse done
389 01:31:54.925692 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 01:31:54.968196 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 01:31:54.979109 PIEI prepare done
392 01:31:54.979555 fastboot data load
393 01:31:54.979949 fastboot data verify
394 01:31:54.984790 verify result: 266
395 01:31:54.990653 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 01:31:54.991162 LPDDR4 probe
397 01:31:54.991577 ddr clk to 1584MHz
398 01:31:54.998396 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 01:31:55.035720
400 01:31:55.036273 dmc_version 0001
401 01:31:55.042395 Check phy result
402 01:31:55.048275 INFO : End of CA training
403 01:31:55.048757 INFO : End of initialization
404 01:31:55.053863 INFO : Training has run successfully!
405 01:31:55.054337 Check phy result
406 01:31:55.059455 INFO : End of initialization
407 01:31:55.059931 INFO : End of read enable training
408 01:31:55.065063 INFO : End of fine write leveling
409 01:31:55.070614 INFO : End of Write leveling coarse delay
410 01:31:55.071084 INFO : Training has run successfully!
411 01:31:55.071495 Check phy result
412 01:31:55.076251 INFO : End of initialization
413 01:31:55.076728 INFO : End of read dq deskew training
414 01:31:55.081894 INFO : End of MPR read delay center optimization
415 01:31:55.087501 INFO : End of write delay center optimization
416 01:31:55.093078 INFO : End of read delay center optimization
417 01:31:55.093567 INFO : End of max read latency training
418 01:31:55.098854 INFO : Training has run successfully!
419 01:31:55.099337 1D training succeed
420 01:31:55.107807 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 01:31:55.155473 Check phy result
422 01:31:55.156007 INFO : End of initialization
423 01:31:55.177130 INFO : End of 2D read delay Voltage center optimization
424 01:31:55.197212 INFO : End of 2D read delay Voltage center optimization
425 01:31:55.249136 INFO : End of 2D write delay Voltage center optimization
426 01:31:55.298392 INFO : End of 2D write delay Voltage center optimization
427 01:31:55.304046 INFO : Training has run successfully!
428 01:31:55.304577
429 01:31:55.305004 channel==0
430 01:31:55.309514 RxClkDly_Margin_A0==88 ps 9
431 01:31:55.310032 TxDqDly_Margin_A0==98 ps 10
432 01:31:55.315229 RxClkDly_Margin_A1==88 ps 9
433 01:31:55.315741 TxDqDly_Margin_A1==98 ps 10
434 01:31:55.316197 TrainedVREFDQ_A0==74
435 01:31:55.320836 TrainedVREFDQ_A1==75
436 01:31:55.321345 VrefDac_Margin_A0==25
437 01:31:55.321761 DeviceVref_Margin_A0==40
438 01:31:55.326315 VrefDac_Margin_A1==25
439 01:31:55.326821 DeviceVref_Margin_A1==39
440 01:31:55.327234
441 01:31:55.327643
442 01:31:55.332053 channel==1
443 01:31:55.332588 RxClkDly_Margin_A0==98 ps 10
444 01:31:55.333011 TxDqDly_Margin_A0==88 ps 9
445 01:31:55.337593 RxClkDly_Margin_A1==98 ps 10
446 01:31:55.338168 TxDqDly_Margin_A1==88 ps 9
447 01:31:55.343230 TrainedVREFDQ_A0==77
448 01:31:55.344113 TrainedVREFDQ_A1==77
449 01:31:55.344627 VrefDac_Margin_A0==22
450 01:31:55.348971 DeviceVref_Margin_A0==37
451 01:31:55.349831 VrefDac_Margin_A1==22
452 01:31:55.354501 DeviceVref_Margin_A1==37
453 01:31:55.355096
454 01:31:55.355523 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 01:31:55.355935
456 01:31:55.387838 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 01:31:55.388507 2D training succeed
458 01:31:55.393437 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 01:31:55.398985 auto size-- 65535DDR cs0 size: 2048MB
460 01:31:55.399377 DDR cs1 size: 2048MB
461 01:31:55.404566 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 01:31:55.405077 cs0 DataBus test pass
463 01:31:55.410209 cs1 DataBus test pass
464 01:31:55.410568 cs0 AddrBus test pass
465 01:31:55.410787 cs1 AddrBus test pass
466 01:31:55.410999
467 01:31:55.415777 100bdlr_step_size ps== 420
468 01:31:55.416170 result report
469 01:31:55.421377 boot times 0Enable ddr reg access
470 01:31:55.426753 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 01:31:55.440219 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 01:31:56.012287 0.0;M3 CHK:0;cm4_sp_mode 0
473 01:31:56.012968 MVN_1=0x00000000
474 01:31:56.017608 MVN_2=0x00000000
475 01:31:56.023400 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 01:31:56.023934 OPS=0x10
477 01:31:56.024456 ring efuse init
478 01:31:56.024924 chipver efuse init
479 01:31:56.028993 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 01:31:56.034643 [0.018961 Inits done]
481 01:31:56.035167 secure task start!
482 01:31:56.035626 high task start!
483 01:31:56.039142 low task start!
484 01:31:56.039628 run into bl31
485 01:31:56.045832 NOTICE: BL31: v1.3(release):4fc40b1
486 01:31:56.053655 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 01:31:56.054178 NOTICE: BL31: G12A normal boot!
488 01:31:56.079016 NOTICE: BL31: BL33 decompress pass
489 01:31:56.084721 ERROR: Error initializing runtime service opteed_fast
490 01:31:57.317639
491 01:31:57.318084
492 01:31:57.325909 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 01:31:57.326368
494 01:31:57.326717 Model: Libre Computer AML-A311D-CC Alta
495 01:31:57.534426 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 01:31:57.557870 DRAM: 2 GiB (effective 3.8 GiB)
497 01:31:57.701009 Core: 408 devices, 31 uclasses, devicetree: separate
498 01:31:57.706801 WDT: Not starting watchdog@f0d0
499 01:31:57.739063 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 01:31:57.751504 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 01:31:57.756457 ** Bad device specification mmc 0 **
502 01:31:57.766814 Card did not respond to voltage select! : -110
503 01:31:57.774440 ** Bad device specification mmc 0 **
504 01:31:57.774989 Couldn't find partition mmc 0
505 01:31:57.782964 Card did not respond to voltage select! : -110
506 01:31:57.788349 ** Bad device specification mmc 0 **
507 01:31:57.788890 Couldn't find partition mmc 0
508 01:31:57.793370 Error: could not access storage.
509 01:31:59.059050 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 01:31:59.059727 bl2_stage_init 0x01
511 01:31:59.060311 bl2_stage_init 0x81
512 01:31:59.064498 hw id: 0x0000 - pwm id 0x01
513 01:31:59.065096 bl2_stage_init 0xc1
514 01:31:59.065591 bl2_stage_init 0x02
515 01:31:59.066103
516 01:31:59.070105 L0:00000000
517 01:31:59.070664 L1:20000703
518 01:31:59.071150 L2:00008067
519 01:31:59.071640 L3:14000000
520 01:31:59.073049 B2:00402000
521 01:31:59.073577 B1:e0f83180
522 01:31:59.074089
523 01:31:59.074566 TE: 58167
524 01:31:59.075024
525 01:31:59.084161 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 01:31:59.084737
527 01:31:59.085211 Board ID = 1
528 01:31:59.085666 Set A53 clk to 24M
529 01:31:59.086119 Set A73 clk to 24M
530 01:31:59.089749 Set clk81 to 24M
531 01:31:59.090237 A53 clk: 1200 MHz
532 01:31:59.090692 A73 clk: 1200 MHz
533 01:31:59.095365 CLK81: 166.6M
534 01:31:59.095933 smccc: 00012abe
535 01:31:59.101051 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 01:31:59.101878 board id: 1
537 01:31:59.109617 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 01:31:59.120218 fw parse done
539 01:31:59.126166 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 01:31:59.168777 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 01:31:59.179663 PIEI prepare done
542 01:31:59.180286 fastboot data load
543 01:31:59.180764 fastboot data verify
544 01:31:59.185286 verify result: 266
545 01:31:59.191016 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 01:31:59.191504 LPDDR4 probe
547 01:31:59.191965 ddr clk to 1584MHz
548 01:31:59.198862 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 01:31:59.236174
550 01:31:59.236695 dmc_version 0001
551 01:31:59.242823 Check phy result
552 01:31:59.248724 INFO : End of CA training
553 01:31:59.249227 INFO : End of initialization
554 01:31:59.254308 INFO : Training has run successfully!
555 01:31:59.254793 Check phy result
556 01:31:59.259892 INFO : End of initialization
557 01:31:59.260414 INFO : End of read enable training
558 01:31:59.265489 INFO : End of fine write leveling
559 01:31:59.271107 INFO : End of Write leveling coarse delay
560 01:31:59.271594 INFO : Training has run successfully!
561 01:31:59.272074 Check phy result
562 01:31:59.276705 INFO : End of initialization
563 01:31:59.277193 INFO : End of read dq deskew training
564 01:31:59.282322 INFO : End of MPR read delay center optimization
565 01:31:59.287923 INFO : End of write delay center optimization
566 01:31:59.293508 INFO : End of read delay center optimization
567 01:31:59.294002 INFO : End of max read latency training
568 01:31:59.299080 INFO : Training has run successfully!
569 01:31:59.299565 1D training succeed
570 01:31:59.308293 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 01:31:59.355940 Check phy result
572 01:31:59.356623 INFO : End of initialization
573 01:31:59.377601 INFO : End of 2D read delay Voltage center optimization
574 01:31:59.397914 INFO : End of 2D read delay Voltage center optimization
575 01:31:59.449946 INFO : End of 2D write delay Voltage center optimization
576 01:31:59.499344 INFO : End of 2D write delay Voltage center optimization
577 01:31:59.504823 INFO : Training has run successfully!
578 01:31:59.505320
579 01:31:59.505778 channel==0
580 01:31:59.510420 RxClkDly_Margin_A0==88 ps 9
581 01:31:59.510909 TxDqDly_Margin_A0==98 ps 10
582 01:31:59.516261 RxClkDly_Margin_A1==88 ps 9
583 01:31:59.516860 TxDqDly_Margin_A1==98 ps 10
584 01:31:59.517338 TrainedVREFDQ_A0==74
585 01:31:59.521743 TrainedVREFDQ_A1==74
586 01:31:59.522255 VrefDac_Margin_A0==25
587 01:31:59.522717 DeviceVref_Margin_A0==40
588 01:31:59.527278 VrefDac_Margin_A1==23
589 01:31:59.527815 DeviceVref_Margin_A1==40
590 01:31:59.528329
591 01:31:59.528792
592 01:31:59.532829 channel==1
593 01:31:59.533313 RxClkDly_Margin_A0==98 ps 10
594 01:31:59.533791 TxDqDly_Margin_A0==98 ps 10
595 01:31:59.538464 RxClkDly_Margin_A1==88 ps 9
596 01:31:59.538960 TxDqDly_Margin_A1==88 ps 9
597 01:31:59.544315 TrainedVREFDQ_A0==77
598 01:31:59.544823 TrainedVREFDQ_A1==77
599 01:31:59.545283 VrefDac_Margin_A0==22
600 01:31:59.549850 DeviceVref_Margin_A0==37
601 01:31:59.550411 VrefDac_Margin_A1==24
602 01:31:59.555372 DeviceVref_Margin_A1==37
603 01:31:59.555922
604 01:31:59.556404 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 01:31:59.556818
606 01:31:59.588833 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 01:31:59.589447 2D training succeed
608 01:31:59.594429 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 01:31:59.600097 auto size-- 65535DDR cs0 size: 2048MB
610 01:31:59.600623 DDR cs1 size: 2048MB
611 01:31:59.605622 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 01:31:59.606124 cs0 DataBus test pass
613 01:31:59.611239 cs1 DataBus test pass
614 01:31:59.611781 cs0 AddrBus test pass
615 01:31:59.612282 cs1 AddrBus test pass
616 01:31:59.612765
617 01:31:59.616864 100bdlr_step_size ps== 420
618 01:31:59.617429 result report
619 01:31:59.622451 boot times 0Enable ddr reg access
620 01:31:59.627797 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 01:31:59.641278 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 01:32:00.215002 0.0;M3 CHK:0;cm4_sp_mode 0
623 01:32:00.215591 MVN_1=0x00000000
624 01:32:00.220460 MVN_2=0x00000000
625 01:32:00.226251 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 01:32:00.226783 OPS=0x10
627 01:32:00.227229 ring efuse init
628 01:32:00.227675 chipver efuse init
629 01:32:00.231807 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 01:32:00.237349 [0.018961 Inits done]
631 01:32:00.237650 secure task start!
632 01:32:00.237862 high task start!
633 01:32:00.241998 low task start!
634 01:32:00.242520 run into bl31
635 01:32:00.248712 NOTICE: BL31: v1.3(release):4fc40b1
636 01:32:00.256506 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 01:32:00.257029 NOTICE: BL31: G12A normal boot!
638 01:32:00.281920 NOTICE: BL31: BL33 decompress pass
639 01:32:00.287541 ERROR: Error initializing runtime service opteed_fast
640 01:32:01.520515
641 01:32:01.521127
642 01:32:01.529042 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 01:32:01.529454
644 01:32:01.529670 Model: Libre Computer AML-A311D-CC Alta
645 01:32:01.737486 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 01:32:01.760739 DRAM: 2 GiB (effective 3.8 GiB)
647 01:32:01.903687 Core: 408 devices, 31 uclasses, devicetree: separate
648 01:32:01.910399 WDT: Not starting watchdog@f0d0
649 01:32:01.941690 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 01:32:01.954281 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 01:32:01.959412 ** Bad device specification mmc 0 **
652 01:32:01.969640 Card did not respond to voltage select! : -110
653 01:32:01.977189 ** Bad device specification mmc 0 **
654 01:32:01.977557 Couldn't find partition mmc 0
655 01:32:01.985593 Card did not respond to voltage select! : -110
656 01:32:01.990991 ** Bad device specification mmc 0 **
657 01:32:01.991411 Couldn't find partition mmc 0
658 01:32:01.996214 Error: could not access storage.
659 01:32:02.338951 Net: eth0: ethernet@ff3f0000
660 01:32:02.339789 starting USB...
661 01:32:02.590506 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 01:32:02.591143 Starting the controller
663 01:32:02.597583 USB XHCI 1.10
664 01:32:04.307723 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 01:32:04.308456 bl2_stage_init 0x01
666 01:32:04.308934 bl2_stage_init 0x81
667 01:32:04.313186 hw id: 0x0000 - pwm id 0x01
668 01:32:04.313755 bl2_stage_init 0xc1
669 01:32:04.314193 bl2_stage_init 0x02
670 01:32:04.314655
671 01:32:04.319037 L0:00000000
672 01:32:04.319593 L1:20000703
673 01:32:04.320080 L2:00008067
674 01:32:04.320533 L3:14000000
675 01:32:04.321715 B2:00402000
676 01:32:04.322224 B1:e0f83180
677 01:32:04.322653
678 01:32:04.323057 TE: 58124
679 01:32:04.323478
680 01:32:04.332855 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 01:32:04.333186
682 01:32:04.333397 Board ID = 1
683 01:32:04.333615 Set A53 clk to 24M
684 01:32:04.333853 Set A73 clk to 24M
685 01:32:04.338457 Set clk81 to 24M
686 01:32:04.339045 A53 clk: 1200 MHz
687 01:32:04.339535 A73 clk: 1200 MHz
688 01:32:04.341886 CLK81: 166.6M
689 01:32:04.342422 smccc: 00012a92
690 01:32:04.347500 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 01:32:04.353038 board id: 1
692 01:32:04.358313 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 01:32:04.368805 fw parse done
694 01:32:04.374829 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 01:32:04.417490 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 01:32:04.428333 PIEI prepare done
697 01:32:04.428954 fastboot data load
698 01:32:04.429435 fastboot data verify
699 01:32:04.433929 verify result: 266
700 01:32:04.439503 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 01:32:04.440146 LPDDR4 probe
702 01:32:04.440642 ddr clk to 1584MHz
703 01:32:04.447490 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 01:32:04.485105
705 01:32:04.485753 dmc_version 0001
706 01:32:04.491566 Check phy result
707 01:32:04.497323 INFO : End of CA training
708 01:32:04.497873 INFO : End of initialization
709 01:32:04.502955 INFO : Training has run successfully!
710 01:32:04.503498 Check phy result
711 01:32:04.508566 INFO : End of initialization
712 01:32:04.509133 INFO : End of read enable training
713 01:32:04.511818 INFO : End of fine write leveling
714 01:32:04.517459 INFO : End of Write leveling coarse delay
715 01:32:04.523090 INFO : Training has run successfully!
716 01:32:04.523679 Check phy result
717 01:32:04.524207 INFO : End of initialization
718 01:32:04.528749 INFO : End of read dq deskew training
719 01:32:04.534295 INFO : End of MPR read delay center optimization
720 01:32:04.534856 INFO : End of write delay center optimization
721 01:32:04.539930 INFO : End of read delay center optimization
722 01:32:04.545514 INFO : End of max read latency training
723 01:32:04.546116 INFO : Training has run successfully!
724 01:32:04.551260 1D training succeed
725 01:32:04.557071 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 01:32:04.604690 Check phy result
727 01:32:04.605308 INFO : End of initialization
728 01:32:04.626417 INFO : End of 2D read delay Voltage center optimization
729 01:32:04.646552 INFO : End of 2D read delay Voltage center optimization
730 01:32:04.698589 INFO : End of 2D write delay Voltage center optimization
731 01:32:04.748020 INFO : End of 2D write delay Voltage center optimization
732 01:32:04.753651 INFO : Training has run successfully!
733 01:32:04.753996
734 01:32:04.754257 channel==0
735 01:32:04.759084 RxClkDly_Margin_A0==88 ps 9
736 01:32:04.759442 TxDqDly_Margin_A0==98 ps 10
737 01:32:04.762444 RxClkDly_Margin_A1==88 ps 9
738 01:32:04.762976 TxDqDly_Margin_A1==98 ps 10
739 01:32:04.768009 TrainedVREFDQ_A0==74
740 01:32:04.768530 TrainedVREFDQ_A1==74
741 01:32:04.773612 VrefDac_Margin_A0==25
742 01:32:04.774118 DeviceVref_Margin_A0==40
743 01:32:04.774538 VrefDac_Margin_A1==25
744 01:32:04.779216 DeviceVref_Margin_A1==40
745 01:32:04.779762
746 01:32:04.780240
747 01:32:04.780669 channel==1
748 01:32:04.781081 RxClkDly_Margin_A0==98 ps 10
749 01:32:04.784758 TxDqDly_Margin_A0==88 ps 9
750 01:32:04.785274 RxClkDly_Margin_A1==88 ps 9
751 01:32:04.790331 TxDqDly_Margin_A1==88 ps 9
752 01:32:04.790890 TrainedVREFDQ_A0==76
753 01:32:04.791335 TrainedVREFDQ_A1==77
754 01:32:04.796030 VrefDac_Margin_A0==22
755 01:32:04.796553 DeviceVref_Margin_A0==38
756 01:32:04.801578 VrefDac_Margin_A1==24
757 01:32:04.802093 DeviceVref_Margin_A1==37
758 01:32:04.802521
759 01:32:04.807160 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 01:32:04.807684
761 01:32:04.835080 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
762 01:32:04.840744 2D training succeed
763 01:32:04.846367 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 01:32:04.846896 auto size-- 65535DDR cs0 size: 2048MB
765 01:32:04.851943 DDR cs1 size: 2048MB
766 01:32:04.852534 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 01:32:04.857698 cs0 DataBus test pass
768 01:32:04.858266 cs1 DataBus test pass
769 01:32:04.858683 cs0 AddrBus test pass
770 01:32:04.863179 cs1 AddrBus test pass
771 01:32:04.863708
772 01:32:04.864181 100bdlr_step_size ps== 420
773 01:32:04.864614 result report
774 01:32:04.868760 boot times 0Enable ddr reg access
775 01:32:04.876374 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 01:32:04.890074 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 01:32:05.462979 0.0;M3 CHK:0;cm4_sp_mode 0
778 01:32:05.463718 MVN_1=0x00000000
779 01:32:05.468467 MVN_2=0x00000000
780 01:32:05.474264 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 01:32:05.474852 OPS=0x10
782 01:32:05.475316 ring efuse init
783 01:32:05.475770 chipver efuse init
784 01:32:05.482692 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 01:32:05.483318 [0.018960 Inits done]
786 01:32:05.483783 secure task start!
787 01:32:05.490198 high task start!
788 01:32:05.490783 low task start!
789 01:32:05.491231 run into bl31
790 01:32:05.496727 NOTICE: BL31: v1.3(release):4fc40b1
791 01:32:05.504413 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 01:32:05.504953 NOTICE: BL31: G12A normal boot!
793 01:32:05.529948 NOTICE: BL31: BL33 decompress pass
794 01:32:05.535670 ERROR: Error initializing runtime service opteed_fast
795 01:32:06.768339
796 01:32:06.768971
797 01:32:06.776825 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 01:32:06.777336
799 01:32:06.777803 Model: Libre Computer AML-A311D-CC Alta
800 01:32:06.985193 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 01:32:07.008633 DRAM: 2 GiB (effective 3.8 GiB)
802 01:32:07.151624 Core: 408 devices, 31 uclasses, devicetree: separate
803 01:32:07.157486 WDT: Not starting watchdog@f0d0
804 01:32:07.189603 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 01:32:07.202368 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 01:32:07.207166 ** Bad device specification mmc 0 **
807 01:32:07.217486 Card did not respond to voltage select! : -110
808 01:32:07.225179 ** Bad device specification mmc 0 **
809 01:32:07.225747 Couldn't find partition mmc 0
810 01:32:07.233375 Card did not respond to voltage select! : -110
811 01:32:07.238963 ** Bad device specification mmc 0 **
812 01:32:07.239477 Couldn't find partition mmc 0
813 01:32:07.244052 Error: could not access storage.
814 01:32:07.586639 Net: eth0: ethernet@ff3f0000
815 01:32:07.587305 starting USB...
816 01:32:07.838454 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 01:32:07.839020 Starting the controller
818 01:32:07.845312 USB XHCI 1.10
819 01:32:10.008064 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 01:32:10.008503 bl2_stage_init 0x01
821 01:32:10.008722 bl2_stage_init 0x81
822 01:32:10.013301 hw id: 0x0000 - pwm id 0x01
823 01:32:10.013804 bl2_stage_init 0xc1
824 01:32:10.014202 bl2_stage_init 0x02
825 01:32:10.014575
826 01:32:10.018876 L0:00000000
827 01:32:10.019258 L1:20000703
828 01:32:10.019501 L2:00008067
829 01:32:10.019831 L3:14000000
830 01:32:10.021797 B2:00402000
831 01:32:10.022154 B1:e0f83180
832 01:32:10.022380
833 01:32:10.022585 TE: 58124
834 01:32:10.022791
835 01:32:10.033245 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 01:32:10.033647
837 01:32:10.033861 Board ID = 1
838 01:32:10.034061 Set A53 clk to 24M
839 01:32:10.034258 Set A73 clk to 24M
840 01:32:10.038518 Set clk81 to 24M
841 01:32:10.038850 A53 clk: 1200 MHz
842 01:32:10.039057 A73 clk: 1200 MHz
843 01:32:10.042046 CLK81: 166.6M
844 01:32:10.042527 smccc: 00012a92
845 01:32:10.047576 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 01:32:10.053214 board id: 1
847 01:32:10.057572 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 01:32:10.068946 fw parse done
849 01:32:10.074924 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 01:32:10.117604 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 01:32:10.128577 PIEI prepare done
852 01:32:10.128984 fastboot data load
853 01:32:10.129226 fastboot data verify
854 01:32:10.134083 verify result: 266
855 01:32:10.139663 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 01:32:10.140046 LPDDR4 probe
857 01:32:10.140311 ddr clk to 1584MHz
858 01:32:10.148115 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 01:32:10.184186
860 01:32:10.184816 dmc_version 0001
861 01:32:10.190696 Check phy result
862 01:32:10.197527 INFO : End of CA training
863 01:32:10.198044 INFO : End of initialization
864 01:32:10.203020 INFO : Training has run successfully!
865 01:32:10.203510 Check phy result
866 01:32:10.208779 INFO : End of initialization
867 01:32:10.209293 INFO : End of read enable training
868 01:32:10.214217 INFO : End of fine write leveling
869 01:32:10.219837 INFO : End of Write leveling coarse delay
870 01:32:10.220372 INFO : Training has run successfully!
871 01:32:10.220830 Check phy result
872 01:32:10.225507 INFO : End of initialization
873 01:32:10.226008 INFO : End of read dq deskew training
874 01:32:10.231063 INFO : End of MPR read delay center optimization
875 01:32:10.236776 INFO : End of write delay center optimization
876 01:32:10.242229 INFO : End of read delay center optimization
877 01:32:10.242725 INFO : End of max read latency training
878 01:32:10.247830 INFO : Training has run successfully!
879 01:32:10.248375 1D training succeed
880 01:32:10.256184 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 01:32:10.303733 Check phy result
882 01:32:10.304365 INFO : End of initialization
883 01:32:10.326140 INFO : End of 2D read delay Voltage center optimization
884 01:32:10.347152 INFO : End of 2D read delay Voltage center optimization
885 01:32:10.399149 INFO : End of 2D write delay Voltage center optimization
886 01:32:10.448375 INFO : End of 2D write delay Voltage center optimization
887 01:32:10.453925 INFO : Training has run successfully!
888 01:32:10.454427
889 01:32:10.454880 channel==0
890 01:32:10.459621 RxClkDly_Margin_A0==88 ps 9
891 01:32:10.460166 TxDqDly_Margin_A0==98 ps 10
892 01:32:10.465124 RxClkDly_Margin_A1==88 ps 9
893 01:32:10.465633 TxDqDly_Margin_A1==98 ps 10
894 01:32:10.466114 TrainedVREFDQ_A0==74
895 01:32:10.470759 TrainedVREFDQ_A1==74
896 01:32:10.471318 VrefDac_Margin_A0==25
897 01:32:10.471769 DeviceVref_Margin_A0==40
898 01:32:10.476297 VrefDac_Margin_A1==25
899 01:32:10.476839 DeviceVref_Margin_A1==40
900 01:32:10.477272
901 01:32:10.477703
902 01:32:10.481886 channel==1
903 01:32:10.482363 RxClkDly_Margin_A0==98 ps 10
904 01:32:10.482797 TxDqDly_Margin_A0==98 ps 10
905 01:32:10.487611 RxClkDly_Margin_A1==98 ps 10
906 01:32:10.488114 TxDqDly_Margin_A1==88 ps 9
907 01:32:10.493059 TrainedVREFDQ_A0==77
908 01:32:10.493534 TrainedVREFDQ_A1==77
909 01:32:10.493965 VrefDac_Margin_A0==22
910 01:32:10.498678 DeviceVref_Margin_A0==37
911 01:32:10.499143 VrefDac_Margin_A1==22
912 01:32:10.504267 DeviceVref_Margin_A1==37
913 01:32:10.504804
914 01:32:10.505244 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 01:32:10.509851
916 01:32:10.537910 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 01:32:10.538457 2D training succeed
918 01:32:10.543578 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 01:32:10.549051 auto size-- 65535DDR cs0 size: 2048MB
920 01:32:10.549529 DDR cs1 size: 2048MB
921 01:32:10.554668 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 01:32:10.555151 cs0 DataBus test pass
923 01:32:10.560267 cs1 DataBus test pass
924 01:32:10.560739 cs0 AddrBus test pass
925 01:32:10.561171 cs1 AddrBus test pass
926 01:32:10.561594
927 01:32:10.565887 100bdlr_step_size ps== 420
928 01:32:10.566371 result report
929 01:32:10.571604 boot times 0Enable ddr reg access
930 01:32:10.575934 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 01:32:10.589556 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 01:32:11.162451 0.0;M3 CHK:0;cm4_sp_mode 0
933 01:32:11.163115 MVN_1=0x00000000
934 01:32:11.167884 MVN_2=0x00000000
935 01:32:11.173639 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 01:32:11.174129 OPS=0x10
937 01:32:11.174582 ring efuse init
938 01:32:11.175025 chipver efuse init
939 01:32:11.179254 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 01:32:11.184826 [0.018961 Inits done]
941 01:32:11.185310 secure task start!
942 01:32:11.185763 high task start!
943 01:32:11.189409 low task start!
944 01:32:11.189891 run into bl31
945 01:32:11.196088 NOTICE: BL31: v1.3(release):4fc40b1
946 01:32:11.203929 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 01:32:11.204502 NOTICE: BL31: G12A normal boot!
948 01:32:11.229416 NOTICE: BL31: BL33 decompress pass
949 01:32:11.234946 ERROR: Error initializing runtime service opteed_fast
950 01:32:12.467842
951 01:32:12.468583
952 01:32:12.476268 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 01:32:12.476773
954 01:32:12.477235 Model: Libre Computer AML-A311D-CC Alta
955 01:32:12.683816 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 01:32:12.708065 DRAM: 2 GiB (effective 3.8 GiB)
957 01:32:12.851082 Core: 408 devices, 31 uclasses, devicetree: separate
958 01:32:12.856071 WDT: Not starting watchdog@f0d0
959 01:32:12.889208 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 01:32:12.901625 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 01:32:12.906574 ** Bad device specification mmc 0 **
962 01:32:12.917079 Card did not respond to voltage select! : -110
963 01:32:12.923778 ** Bad device specification mmc 0 **
964 01:32:12.924359 Couldn't find partition mmc 0
965 01:32:12.932960 Card did not respond to voltage select! : -110
966 01:32:12.938463 ** Bad device specification mmc 0 **
967 01:32:12.938952 Couldn't find partition mmc 0
968 01:32:12.943501 Error: could not access storage.
969 01:32:13.286027 Net: eth0: ethernet@ff3f0000
970 01:32:13.286443 starting USB...
971 01:32:13.537731 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 01:32:13.538297 Starting the controller
973 01:32:13.544733 USB XHCI 1.10
974 01:32:15.407643 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 01:32:15.408072 bl2_stage_init 0x01
976 01:32:15.408299 bl2_stage_init 0x81
977 01:32:15.413125 hw id: 0x0000 - pwm id 0x01
978 01:32:15.413413 bl2_stage_init 0xc1
979 01:32:15.413625 bl2_stage_init 0x02
980 01:32:15.413826
981 01:32:15.418707 L0:00000000
982 01:32:15.419012 L1:20000703
983 01:32:15.419226 L2:00008067
984 01:32:15.419441 L3:14000000
985 01:32:15.424295 B2:00402000
986 01:32:15.424609 B1:e0f83180
987 01:32:15.424823
988 01:32:15.425030 TE: 58159
989 01:32:15.425248
990 01:32:15.429978 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 01:32:15.430267
992 01:32:15.430482 Board ID = 1
993 01:32:15.435533 Set A53 clk to 24M
994 01:32:15.435827 Set A73 clk to 24M
995 01:32:15.436068 Set clk81 to 24M
996 01:32:15.441253 A53 clk: 1200 MHz
997 01:32:15.441554 A73 clk: 1200 MHz
998 01:32:15.441770 CLK81: 166.6M
999 01:32:15.441975 smccc: 00012ab4
1000 01:32:15.446786 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 01:32:15.452551 board id: 1
1002 01:32:15.458265 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 01:32:15.468871 fw parse done
1004 01:32:15.474836 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 01:32:15.517433 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 01:32:15.528269 PIEI prepare done
1007 01:32:15.528612 fastboot data load
1008 01:32:15.528844 fastboot data verify
1009 01:32:15.533827 verify result: 266
1010 01:32:15.539504 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 01:32:15.539831 LPDDR4 probe
1012 01:32:15.540102 ddr clk to 1584MHz
1013 01:32:15.547455 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 01:32:15.584768
1015 01:32:15.585154 dmc_version 0001
1016 01:32:15.591477 Check phy result
1017 01:32:15.597229 INFO : End of CA training
1018 01:32:15.597637 INFO : End of initialization
1019 01:32:15.602857 INFO : Training has run successfully!
1020 01:32:15.603470 Check phy result
1021 01:32:15.608479 INFO : End of initialization
1022 01:32:15.608926 INFO : End of read enable training
1023 01:32:15.611759 INFO : End of fine write leveling
1024 01:32:15.617312 INFO : End of Write leveling coarse delay
1025 01:32:15.622941 INFO : Training has run successfully!
1026 01:32:15.623352 Check phy result
1027 01:32:15.623644 INFO : End of initialization
1028 01:32:15.628554 INFO : End of read dq deskew training
1029 01:32:15.634089 INFO : End of MPR read delay center optimization
1030 01:32:15.634663 INFO : End of write delay center optimization
1031 01:32:15.639715 INFO : End of read delay center optimization
1032 01:32:15.645270 INFO : End of max read latency training
1033 01:32:15.645677 INFO : Training has run successfully!
1034 01:32:15.650928 1D training succeed
1035 01:32:15.656815 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 01:32:15.704463 Check phy result
1037 01:32:15.704932 INFO : End of initialization
1038 01:32:15.727009 INFO : End of 2D read delay Voltage center optimization
1039 01:32:15.747298 INFO : End of 2D read delay Voltage center optimization
1040 01:32:15.798456 INFO : End of 2D write delay Voltage center optimization
1041 01:32:15.848703 INFO : End of 2D write delay Voltage center optimization
1042 01:32:15.854271 INFO : Training has run successfully!
1043 01:32:15.854822
1044 01:32:15.855157 channel==0
1045 01:32:15.859742 RxClkDly_Margin_A0==88 ps 9
1046 01:32:15.860130 TxDqDly_Margin_A0==98 ps 10
1047 01:32:15.865323 RxClkDly_Margin_A1==88 ps 9
1048 01:32:15.865717 TxDqDly_Margin_A1==98 ps 10
1049 01:32:15.866007 TrainedVREFDQ_A0==74
1050 01:32:15.870953 TrainedVREFDQ_A1==74
1051 01:32:15.871326 VrefDac_Margin_A0==24
1052 01:32:15.871609 DeviceVref_Margin_A0==40
1053 01:32:15.876714 VrefDac_Margin_A1==24
1054 01:32:15.877087 DeviceVref_Margin_A1==40
1055 01:32:15.877369
1056 01:32:15.877638
1057 01:32:15.882239 channel==1
1058 01:32:15.882646 RxClkDly_Margin_A0==98 ps 10
1059 01:32:15.882934 TxDqDly_Margin_A0==98 ps 10
1060 01:32:15.887811 RxClkDly_Margin_A1==88 ps 9
1061 01:32:15.888192 TxDqDly_Margin_A1==98 ps 10
1062 01:32:15.893385 TrainedVREFDQ_A0==77
1063 01:32:15.893937 TrainedVREFDQ_A1==78
1064 01:32:15.894382 VrefDac_Margin_A0==22
1065 01:32:15.898953 DeviceVref_Margin_A0==37
1066 01:32:15.899327 VrefDac_Margin_A1==24
1067 01:32:15.904636 DeviceVref_Margin_A1==36
1068 01:32:15.905073
1069 01:32:15.905363 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 01:32:15.910239
1071 01:32:15.938302 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1072 01:32:15.938782 2D training succeed
1073 01:32:15.943827 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 01:32:15.949311 auto size-- 65535DDR cs0 size: 2048MB
1075 01:32:15.949848 DDR cs1 size: 2048MB
1076 01:32:15.955114 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 01:32:15.955503 cs0 DataBus test pass
1078 01:32:15.960608 cs1 DataBus test pass
1079 01:32:15.960979 cs0 AddrBus test pass
1080 01:32:15.961301 cs1 AddrBus test pass
1081 01:32:15.961562
1082 01:32:15.966367 100bdlr_step_size ps== 420
1083 01:32:15.966749 result report
1084 01:32:15.971808 boot times 0Enable ddr reg access
1085 01:32:15.977230 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 01:32:15.989817 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 01:32:16.564482 0.0;M3 CHK:0;cm4_sp_mode 0
1088 01:32:16.565157 MVN_1=0x00000000
1089 01:32:16.569873 MVN_2=0x00000000
1090 01:32:16.575652 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 01:32:16.576056 OPS=0x10
1092 01:32:16.576357 ring efuse init
1093 01:32:16.576627 chipver efuse init
1094 01:32:16.583869 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 01:32:16.584285 [0.018961 Inits done]
1096 01:32:16.591465 secure task start!
1097 01:32:16.591830 high task start!
1098 01:32:16.592328 low task start!
1099 01:32:16.592870 run into bl31
1100 01:32:16.598133 NOTICE: BL31: v1.3(release):4fc40b1
1101 01:32:16.605017 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 01:32:16.605524 NOTICE: BL31: G12A normal boot!
1103 01:32:16.631424 NOTICE: BL31: BL33 decompress pass
1104 01:32:16.636983 ERROR: Error initializing runtime service opteed_fast
1105 01:32:17.869928
1106 01:32:17.870627
1107 01:32:17.877247 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 01:32:17.877801
1109 01:32:17.878286 Model: Libre Computer AML-A311D-CC Alta
1110 01:32:18.086879 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 01:32:18.109146 DRAM: 2 GiB (effective 3.8 GiB)
1112 01:32:18.253071 Core: 408 devices, 31 uclasses, devicetree: separate
1113 01:32:18.258832 WDT: Not starting watchdog@f0d0
1114 01:32:18.291190 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 01:32:18.303568 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 01:32:18.308661 ** Bad device specification mmc 0 **
1117 01:32:18.318891 Card did not respond to voltage select! : -110
1118 01:32:18.326520 ** Bad device specification mmc 0 **
1119 01:32:18.327067 Couldn't find partition mmc 0
1120 01:32:18.334859 Card did not respond to voltage select! : -110
1121 01:32:18.340435 ** Bad device specification mmc 0 **
1122 01:32:18.341001 Couldn't find partition mmc 0
1123 01:32:18.345116 Error: could not access storage.
1124 01:32:18.688052 Net: eth0: ethernet@ff3f0000
1125 01:32:18.688681 starting USB...
1126 01:32:18.939858 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 01:32:18.940437 Starting the controller
1128 01:32:18.946815 USB XHCI 1.10
1129 01:32:20.500865 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 01:32:20.509137 scanning usb for storage devices... 0 Storage Device(s) found
1132 01:32:20.560847 Hit any key to stop autoboot: 1
1133 01:32:20.561730 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 01:32:20.562362 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 01:32:20.562874 Setting prompt string to ['=>']
1136 01:32:20.563386 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 01:32:20.576774 0
1138 01:32:20.577704 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 01:32:20.578228 Sending with 10 millisecond of delay
1141 01:32:21.713015 => setenv autoload no
1142 01:32:21.723864 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 01:32:21.729394 setenv autoload no
1144 01:32:21.730284 Sending with 10 millisecond of delay
1146 01:32:23.527079 => setenv initrd_high 0xffffffff
1147 01:32:23.537889 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 01:32:23.538750 setenv initrd_high 0xffffffff
1149 01:32:23.539510 Sending with 10 millisecond of delay
1151 01:32:25.155751 => setenv fdt_high 0xffffffff
1152 01:32:25.166613 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 01:32:25.167463 setenv fdt_high 0xffffffff
1154 01:32:25.168229 Sending with 10 millisecond of delay
1156 01:32:25.460205 => dhcp
1157 01:32:25.471033 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 01:32:25.471928 dhcp
1159 01:32:25.472480 Speed: 1000, full duplex
1160 01:32:25.472950 BOOTP broadcast 1
1161 01:32:25.479358 DHCP client bound to address 192.168.6.27 (8 ms)
1162 01:32:25.480109 Sending with 10 millisecond of delay
1164 01:32:27.156532 => setenv serverip 192.168.6.2
1165 01:32:27.167379 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 01:32:27.168360 setenv serverip 192.168.6.2
1167 01:32:27.169113 Sending with 10 millisecond of delay
1169 01:32:30.892535 => tftpboot 0x01080000 949385/tftp-deploy-nuj4pwy4/kernel/uImage
1170 01:32:30.903372 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 01:32:30.904291 tftpboot 0x01080000 949385/tftp-deploy-nuj4pwy4/kernel/uImage
1172 01:32:30.904790 Speed: 1000, full duplex
1173 01:32:30.905254 Using ethernet@ff3f0000 device
1174 01:32:30.906043 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 01:32:30.911459 Filename '949385/tftp-deploy-nuj4pwy4/kernel/uImage'.
1176 01:32:30.915590 Load address: 0x1080000
1177 01:32:33.356253 Loading: *################################################## 36.1 MiB
1178 01:32:33.356926 14.8 MiB/s
1179 01:32:33.357420 done
1180 01:32:33.360658 Bytes transferred = 37880384 (2420240 hex)
1181 01:32:33.361550 Sending with 10 millisecond of delay
1183 01:32:38.049015 => tftpboot 0x08000000 949385/tftp-deploy-nuj4pwy4/ramdisk/ramdisk.cpio.gz.uboot
1184 01:32:38.059863 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 01:32:38.060821 tftpboot 0x08000000 949385/tftp-deploy-nuj4pwy4/ramdisk/ramdisk.cpio.gz.uboot
1186 01:32:38.061354 Speed: 1000, full duplex
1187 01:32:38.061828 Using ethernet@ff3f0000 device
1188 01:32:38.062626 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 01:32:38.074549 Filename '949385/tftp-deploy-nuj4pwy4/ramdisk/ramdisk.cpio.gz.uboot'.
1190 01:32:38.075068 Load address: 0x8000000
1191 01:32:44.644463 Loading: *####T ############################################# UDP wrong checksum 00000005 0000afa4
1192 01:32:49.644870 T UDP wrong checksum 00000005 0000afa4
1193 01:32:59.648037 T T UDP wrong checksum 00000005 0000afa4
1194 01:33:02.437484 UDP wrong checksum 000000ff 0000193c
1195 01:33:02.478810 UDP wrong checksum 000000ff 0000a42e
1196 01:33:19.651769 T T T T UDP wrong checksum 00000005 0000afa4
1197 01:33:34.655976 T T
1198 01:33:34.656435 Retry count exceeded; starting again
1200 01:33:34.659425 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1203 01:33:34.660473 end: 2.4 uboot-commands (duration 00:01:51) [common]
1205 01:33:34.661214 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1207 01:33:34.661761 end: 2 uboot-action (duration 00:01:51) [common]
1209 01:33:34.662576 Cleaning after the job
1210 01:33:34.662893 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/ramdisk
1211 01:33:34.663875 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/kernel
1212 01:33:34.678867 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/dtb
1213 01:33:34.680119 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/nfsrootfs
1214 01:33:34.711276 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949385/tftp-deploy-nuj4pwy4/modules
1215 01:33:34.718581 start: 4.1 power-off (timeout 00:00:30) [common]
1216 01:33:34.719205 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1217 01:33:34.756040 >> OK - accepted request
1218 01:33:34.758243 Returned 0 in 0 seconds
1219 01:33:34.858940 end: 4.1 power-off (duration 00:00:00) [common]
1221 01:33:34.859878 start: 4.2 read-feedback (timeout 00:10:00) [common]
1222 01:33:34.860595 Listened to connection for namespace 'common' for up to 1s
1223 01:33:35.861535 Finalising connection for namespace 'common'
1224 01:33:35.862068 Disconnecting from shell: Finalise
1225 01:33:35.862385 =>
1226 01:33:35.963108 end: 4.2 read-feedback (duration 00:00:01) [common]
1227 01:33:35.963765 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949385
1228 01:33:38.864524 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949385
1229 01:33:38.865218 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.