Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:34:03.661246 lava-dispatcher, installed at version: 2024.01
2 01:34:03.662069 start: 0 validate
3 01:34:03.662551 Start time: 2024-11-07 01:34:03.662519+00:00 (UTC)
4 01:34:03.663117 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:34:03.663666 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:34:03.703218 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:34:03.703772 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 01:34:03.740103 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:34:03.740767 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:34:03.778437 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:34:03.779069 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:34:03.808677 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:34:03.809337 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
14 01:34:03.854146 validate duration: 0.19
16 01:34:03.855181 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:34:03.855605 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:34:03.856026 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:34:03.856749 Not decompressing ramdisk as can be used compressed.
20 01:34:03.857303 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:34:03.857662 saving as /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/ramdisk/initrd.cpio.gz
22 01:34:03.858012 total size: 5628169 (5 MB)
23 01:34:03.898437 progress 0 % (0 MB)
24 01:34:03.903945 progress 5 % (0 MB)
25 01:34:03.909439 progress 10 % (0 MB)
26 01:34:03.914127 progress 15 % (0 MB)
27 01:34:03.919230 progress 20 % (1 MB)
28 01:34:03.923843 progress 25 % (1 MB)
29 01:34:03.929158 progress 30 % (1 MB)
30 01:34:03.934275 progress 35 % (1 MB)
31 01:34:03.938699 progress 40 % (2 MB)
32 01:34:03.944137 progress 45 % (2 MB)
33 01:34:03.949069 progress 50 % (2 MB)
34 01:34:03.954300 progress 55 % (2 MB)
35 01:34:03.959481 progress 60 % (3 MB)
36 01:34:03.964130 progress 65 % (3 MB)
37 01:34:03.969357 progress 70 % (3 MB)
38 01:34:03.973931 progress 75 % (4 MB)
39 01:34:03.978945 progress 80 % (4 MB)
40 01:34:03.983480 progress 85 % (4 MB)
41 01:34:03.988372 progress 90 % (4 MB)
42 01:34:03.993965 progress 95 % (5 MB)
43 01:34:03.998175 progress 100 % (5 MB)
44 01:34:03.998978 5 MB downloaded in 0.14 s (38.08 MB/s)
45 01:34:03.999687 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:34:04.000963 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:34:04.001378 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:34:04.001755 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:34:04.002361 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/kernel/Image
51 01:34:04.002688 saving as /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/kernel/Image
52 01:34:04.002969 total size: 37880320 (36 MB)
53 01:34:04.003236 No compression specified
54 01:34:04.044302 progress 0 % (0 MB)
55 01:34:04.072477 progress 5 % (1 MB)
56 01:34:04.105286 progress 10 % (3 MB)
57 01:34:04.132428 progress 15 % (5 MB)
58 01:34:04.160384 progress 20 % (7 MB)
59 01:34:04.184633 progress 25 % (9 MB)
60 01:34:04.208224 progress 30 % (10 MB)
61 01:34:04.233031 progress 35 % (12 MB)
62 01:34:04.257270 progress 40 % (14 MB)
63 01:34:04.283796 progress 45 % (16 MB)
64 01:34:04.309295 progress 50 % (18 MB)
65 01:34:04.333692 progress 55 % (19 MB)
66 01:34:04.358380 progress 60 % (21 MB)
67 01:34:04.383560 progress 65 % (23 MB)
68 01:34:04.408877 progress 70 % (25 MB)
69 01:34:04.433655 progress 75 % (27 MB)
70 01:34:04.458533 progress 80 % (28 MB)
71 01:34:04.483148 progress 85 % (30 MB)
72 01:34:04.507595 progress 90 % (32 MB)
73 01:34:04.533578 progress 95 % (34 MB)
74 01:34:04.558700 progress 100 % (36 MB)
75 01:34:04.559304 36 MB downloaded in 0.56 s (64.94 MB/s)
76 01:34:04.559843 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:34:04.560768 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:34:04.561077 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:34:04.561360 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:34:04.561844 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:34:04.562171 saving as /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:34:04.562395 total size: 54703 (0 MB)
84 01:34:04.562619 No compression specified
85 01:34:04.609167 progress 59 % (0 MB)
86 01:34:04.610062 progress 100 % (0 MB)
87 01:34:04.610667 0 MB downloaded in 0.05 s (1.08 MB/s)
88 01:34:04.611205 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:34:04.612148 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:34:04.612455 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:34:04.612760 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:34:04.613262 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:34:04.613534 saving as /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/nfsrootfs/full.rootfs.tar
95 01:34:04.613743 total size: 120894716 (115 MB)
96 01:34:04.613957 Using unxz to decompress xz
97 01:34:04.647610 progress 0 % (0 MB)
98 01:34:05.623808 progress 5 % (5 MB)
99 01:34:06.457082 progress 10 % (11 MB)
100 01:34:07.246484 progress 15 % (17 MB)
101 01:34:07.978605 progress 20 % (23 MB)
102 01:34:08.573898 progress 25 % (28 MB)
103 01:34:09.392271 progress 30 % (34 MB)
104 01:34:10.189405 progress 35 % (40 MB)
105 01:34:10.560741 progress 40 % (46 MB)
106 01:34:10.954137 progress 45 % (51 MB)
107 01:34:11.718680 progress 50 % (57 MB)
108 01:34:12.611203 progress 55 % (63 MB)
109 01:34:13.387536 progress 60 % (69 MB)
110 01:34:14.149060 progress 65 % (74 MB)
111 01:34:15.014296 progress 70 % (80 MB)
112 01:34:16.004959 progress 75 % (86 MB)
113 01:34:16.933529 progress 80 % (92 MB)
114 01:34:17.831115 progress 85 % (98 MB)
115 01:34:18.822718 progress 90 % (103 MB)
116 01:34:19.603590 progress 95 % (109 MB)
117 01:34:20.441209 progress 100 % (115 MB)
118 01:34:20.454243 115 MB downloaded in 15.84 s (7.28 MB/s)
119 01:34:20.454894 end: 1.4.1 http-download (duration 00:00:16) [common]
121 01:34:20.455711 end: 1.4 download-retry (duration 00:00:16) [common]
122 01:34:20.455975 start: 1.5 download-retry (timeout 00:09:43) [common]
123 01:34:20.456554 start: 1.5.1 http-download (timeout 00:09:43) [common]
124 01:34:20.457479 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/modules.tar.xz
125 01:34:20.458020 saving as /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/modules/modules.tar
126 01:34:20.458472 total size: 11768476 (11 MB)
127 01:34:20.458926 Using unxz to decompress xz
128 01:34:20.505018 progress 0 % (0 MB)
129 01:34:20.573373 progress 5 % (0 MB)
130 01:34:20.649147 progress 10 % (1 MB)
131 01:34:20.745637 progress 15 % (1 MB)
132 01:34:20.842896 progress 20 % (2 MB)
133 01:34:20.927214 progress 25 % (2 MB)
134 01:34:21.006538 progress 30 % (3 MB)
135 01:34:21.086299 progress 35 % (3 MB)
136 01:34:21.166281 progress 40 % (4 MB)
137 01:34:21.242015 progress 45 % (5 MB)
138 01:34:21.326606 progress 50 % (5 MB)
139 01:34:21.408126 progress 55 % (6 MB)
140 01:34:21.493203 progress 60 % (6 MB)
141 01:34:21.575037 progress 65 % (7 MB)
142 01:34:21.656869 progress 70 % (7 MB)
143 01:34:21.740684 progress 75 % (8 MB)
144 01:34:21.824815 progress 80 % (9 MB)
145 01:34:21.905676 progress 85 % (9 MB)
146 01:34:21.991395 progress 90 % (10 MB)
147 01:34:22.073180 progress 95 % (10 MB)
148 01:34:22.151879 progress 100 % (11 MB)
149 01:34:22.162533 11 MB downloaded in 1.70 s (6.59 MB/s)
150 01:34:22.163106 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:34:22.163971 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:34:22.164682 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 01:34:22.165279 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 01:34:38.530899 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/949404/extract-nfsrootfs-ve674bis
156 01:34:38.531487 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 01:34:38.531775 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 01:34:38.532416 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr
159 01:34:38.532851 makedir: /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin
160 01:34:38.533169 makedir: /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/tests
161 01:34:38.533478 makedir: /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/results
162 01:34:38.533808 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-add-keys
163 01:34:38.534330 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-add-sources
164 01:34:38.534832 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-background-process-start
165 01:34:38.535350 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-background-process-stop
166 01:34:38.535893 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-common-functions
167 01:34:38.536413 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-echo-ipv4
168 01:34:38.536880 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-install-packages
169 01:34:38.537342 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-installed-packages
170 01:34:38.537798 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-os-build
171 01:34:38.538253 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-probe-channel
172 01:34:38.538718 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-probe-ip
173 01:34:38.539207 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-target-ip
174 01:34:38.539693 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-target-mac
175 01:34:38.540272 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-target-storage
176 01:34:38.540919 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-test-case
177 01:34:38.541423 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-test-event
178 01:34:38.541895 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-test-feedback
179 01:34:38.542363 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-test-raise
180 01:34:38.542823 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-test-reference
181 01:34:38.543326 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-test-runner
182 01:34:38.543824 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-test-set
183 01:34:38.544317 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-test-shell
184 01:34:38.544798 Updating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-add-keys (debian)
185 01:34:38.545319 Updating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-add-sources (debian)
186 01:34:38.545806 Updating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-install-packages (debian)
187 01:34:38.546294 Updating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-installed-packages (debian)
188 01:34:38.546777 Updating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/bin/lava-os-build (debian)
189 01:34:38.547198 Creating /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/environment
190 01:34:38.547561 LAVA metadata
191 01:34:38.547817 - LAVA_JOB_ID=949404
192 01:34:38.548065 - LAVA_DISPATCHER_IP=192.168.6.2
193 01:34:38.548438 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 01:34:38.549401 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 01:34:38.549720 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 01:34:38.549925 skipped lava-vland-overlay
197 01:34:38.550165 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 01:34:38.550416 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 01:34:38.550633 skipped lava-multinode-overlay
200 01:34:38.550871 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 01:34:38.551120 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 01:34:38.551365 Loading test definitions
203 01:34:38.551639 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 01:34:38.551860 Using /lava-949404 at stage 0
205 01:34:38.552996 uuid=949404_1.6.2.4.1 testdef=None
206 01:34:38.553308 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 01:34:38.553568 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 01:34:38.555122 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 01:34:38.555907 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 01:34:38.557840 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 01:34:38.558660 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 01:34:38.560666 runner path: /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/0/tests/0_timesync-off test_uuid 949404_1.6.2.4.1
215 01:34:38.561258 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 01:34:38.562069 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 01:34:38.562296 Using /lava-949404 at stage 0
219 01:34:38.562647 Fetching tests from https://github.com/kernelci/test-definitions.git
220 01:34:38.562934 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/0/tests/1_kselftest-dt'
221 01:34:41.986568 Running '/usr/bin/git checkout kernelci.org
222 01:34:42.474843 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 01:34:42.477894 uuid=949404_1.6.2.4.5 testdef=None
224 01:34:42.478695 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 01:34:42.480660 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 01:34:42.487871 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 01:34:42.490163 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 01:34:42.498482 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 01:34:42.499669 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 01:34:42.504379 runner path: /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/0/tests/1_kselftest-dt test_uuid 949404_1.6.2.4.5
234 01:34:42.504765 BOARD='meson-g12b-a311d-libretech-cc'
235 01:34:42.505051 BRANCH='mainline'
236 01:34:42.505317 SKIPFILE='/dev/null'
237 01:34:42.505585 SKIP_INSTALL='True'
238 01:34:42.505844 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/kselftest.tar.xz'
239 01:34:42.506107 TST_CASENAME=''
240 01:34:42.506372 TST_CMDFILES='dt'
241 01:34:42.507103 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 01:34:42.508216 Creating lava-test-runner.conf files
244 01:34:42.508520 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949404/lava-overlay-yqco2kzr/lava-949404/0 for stage 0
245 01:34:42.509005 - 0_timesync-off
246 01:34:42.509325 - 1_kselftest-dt
247 01:34:42.509774 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 01:34:42.510154 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 01:35:06.482477 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 01:35:06.482931 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 01:35:06.483194 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 01:35:06.483467 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 01:35:06.483733 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 01:35:07.095082 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 01:35:07.095561 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 01:35:07.095809 extracting modules file /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949404/extract-nfsrootfs-ve674bis
257 01:35:08.474637 extracting modules file /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949404/extract-overlay-ramdisk-ph52mgm_/ramdisk
258 01:35:09.889820 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 01:35:09.890305 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 01:35:09.890590 [common] Applying overlay to NFS
261 01:35:09.890806 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949404/compress-overlay-crjmek5g/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949404/extract-nfsrootfs-ve674bis
262 01:35:12.623593 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 01:35:12.624097 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 01:35:12.624376 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 01:35:12.624606 Converting downloaded kernel to a uImage
266 01:35:12.624918 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/kernel/Image /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/kernel/uImage
267 01:35:13.030440 output: Image Name:
268 01:35:13.030864 output: Created: Thu Nov 7 01:35:12 2024
269 01:35:13.031078 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 01:35:13.031281 output: Data Size: 37880320 Bytes = 36992.50 KiB = 36.13 MiB
271 01:35:13.031480 output: Load Address: 01080000
272 01:35:13.031683 output: Entry Point: 01080000
273 01:35:13.031880 output:
274 01:35:13.032256 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 01:35:13.032532 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 01:35:13.032802 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 01:35:13.033056 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 01:35:13.033314 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 01:35:13.033569 Building ramdisk /var/lib/lava/dispatcher/tmp/949404/extract-overlay-ramdisk-ph52mgm_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949404/extract-overlay-ramdisk-ph52mgm_/ramdisk
280 01:35:15.254641 >> 173443 blocks
281 01:35:22.956308 Adding RAMdisk u-boot header.
282 01:35:22.956984 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949404/extract-overlay-ramdisk-ph52mgm_/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949404/extract-overlay-ramdisk-ph52mgm_/ramdisk.cpio.gz.uboot
283 01:35:23.233654 output: Image Name:
284 01:35:23.234272 output: Created: Thu Nov 7 01:35:22 2024
285 01:35:23.234700 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 01:35:23.235114 output: Data Size: 24150523 Bytes = 23584.50 KiB = 23.03 MiB
287 01:35:23.235522 output: Load Address: 00000000
288 01:35:23.235924 output: Entry Point: 00000000
289 01:35:23.236384 output:
290 01:35:23.237402 rename /var/lib/lava/dispatcher/tmp/949404/extract-overlay-ramdisk-ph52mgm_/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/ramdisk/ramdisk.cpio.gz.uboot
291 01:35:23.238122 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 01:35:23.238675 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 01:35:23.239246 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 01:35:23.239702 No LXC device requested
295 01:35:23.240256 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 01:35:23.240786 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 01:35:23.241290 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 01:35:23.241709 Checking files for TFTP limit of 4294967296 bytes.
299 01:35:23.244392 end: 1 tftp-deploy (duration 00:01:19) [common]
300 01:35:23.244969 start: 2 uboot-action (timeout 00:05:00) [common]
301 01:35:23.245504 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 01:35:23.246011 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 01:35:23.246529 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 01:35:23.247063 Using kernel file from prepare-kernel: 949404/tftp-deploy-uhmqco8q/kernel/uImage
305 01:35:23.247701 substitutions:
306 01:35:23.248147 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 01:35:23.248562 - {DTB_ADDR}: 0x01070000
308 01:35:23.248968 - {DTB}: 949404/tftp-deploy-uhmqco8q/dtb/meson-g12b-a311d-libretech-cc.dtb
309 01:35:23.249373 - {INITRD}: 949404/tftp-deploy-uhmqco8q/ramdisk/ramdisk.cpio.gz.uboot
310 01:35:23.249770 - {KERNEL_ADDR}: 0x01080000
311 01:35:23.250165 - {KERNEL}: 949404/tftp-deploy-uhmqco8q/kernel/uImage
312 01:35:23.250560 - {LAVA_MAC}: None
313 01:35:23.250995 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/949404/extract-nfsrootfs-ve674bis
314 01:35:23.251395 - {NFS_SERVER_IP}: 192.168.6.2
315 01:35:23.251787 - {PRESEED_CONFIG}: None
316 01:35:23.252242 - {PRESEED_LOCAL}: None
317 01:35:23.252687 - {RAMDISK_ADDR}: 0x08000000
318 01:35:23.253104 - {RAMDISK}: 949404/tftp-deploy-uhmqco8q/ramdisk/ramdisk.cpio.gz.uboot
319 01:35:23.253503 - {ROOT_PART}: None
320 01:35:23.253896 - {ROOT}: None
321 01:35:23.254284 - {SERVER_IP}: 192.168.6.2
322 01:35:23.254674 - {TEE_ADDR}: 0x83000000
323 01:35:23.255060 - {TEE}: None
324 01:35:23.255445 Parsed boot commands:
325 01:35:23.255822 - setenv autoload no
326 01:35:23.256237 - setenv initrd_high 0xffffffff
327 01:35:23.256625 - setenv fdt_high 0xffffffff
328 01:35:23.257010 - dhcp
329 01:35:23.257393 - setenv serverip 192.168.6.2
330 01:35:23.257784 - tftpboot 0x01080000 949404/tftp-deploy-uhmqco8q/kernel/uImage
331 01:35:23.258177 - tftpboot 0x08000000 949404/tftp-deploy-uhmqco8q/ramdisk/ramdisk.cpio.gz.uboot
332 01:35:23.258567 - tftpboot 0x01070000 949404/tftp-deploy-uhmqco8q/dtb/meson-g12b-a311d-libretech-cc.dtb
333 01:35:23.258956 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/949404/extract-nfsrootfs-ve674bis,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 01:35:23.259356 - bootm 0x01080000 0x08000000 0x01070000
335 01:35:23.259860 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 01:35:23.261386 start: 2.3 connect-device (timeout 00:05:00) [common]
338 01:35:23.261809 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 01:35:23.276789 Setting prompt string to ['lava-test: # ']
340 01:35:23.278307 end: 2.3 connect-device (duration 00:00:00) [common]
341 01:35:23.278940 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 01:35:23.279776 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 01:35:23.280479 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 01:35:23.281631 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 01:35:23.319857 >> OK - accepted request
346 01:35:23.322169 Returned 0 in 0 seconds
347 01:35:23.423085 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 01:35:23.424808 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 01:35:23.425375 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 01:35:23.425898 Setting prompt string to ['Hit any key to stop autoboot']
352 01:35:23.426372 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 01:35:23.427925 Trying 192.168.56.21...
354 01:35:23.428435 Connected to conserv1.
355 01:35:23.428852 Escape character is '^]'.
356 01:35:23.429278
357 01:35:23.429704 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 01:35:23.430132
359 01:35:34.908304 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 01:35:34.908955 bl2_stage_init 0x01
361 01:35:34.909416 bl2_stage_init 0x81
362 01:35:34.914130 hw id: 0x0000 - pwm id 0x01
363 01:35:34.914733 bl2_stage_init 0xc1
364 01:35:34.915158 bl2_stage_init 0x02
365 01:35:34.915569
366 01:35:34.919525 L0:00000000
367 01:35:34.920156 L1:20000703
368 01:35:34.920594 L2:00008067
369 01:35:34.921004 L3:14000000
370 01:35:34.924974 B2:00402000
371 01:35:34.925471 B1:e0f83180
372 01:35:34.925868
373 01:35:34.926262 TE: 58124
374 01:35:34.926654
375 01:35:34.930688 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 01:35:34.931152
377 01:35:34.931547 Board ID = 1
378 01:35:34.936175 Set A53 clk to 24M
379 01:35:34.936637 Set A73 clk to 24M
380 01:35:34.937030 Set clk81 to 24M
381 01:35:34.941770 A53 clk: 1200 MHz
382 01:35:34.942219 A73 clk: 1200 MHz
383 01:35:34.942609 CLK81: 166.6M
384 01:35:34.942994 smccc: 00012a91
385 01:35:34.947393 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 01:35:34.952868 board id: 1
387 01:35:34.958893 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 01:35:34.969551 fw parse done
389 01:35:34.975506 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 01:35:35.018264 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 01:35:35.029043 PIEI prepare done
392 01:35:35.029484 fastboot data load
393 01:35:35.029885 fastboot data verify
394 01:35:35.034677 verify result: 266
395 01:35:35.040248 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 01:35:35.040682 LPDDR4 probe
397 01:35:35.041073 ddr clk to 1584MHz
398 01:35:35.048219 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 01:35:35.085432
400 01:35:35.085932 dmc_version 0001
401 01:35:35.092103 Check phy result
402 01:35:35.097935 INFO : End of CA training
403 01:35:35.098371 INFO : End of initialization
404 01:35:35.103636 INFO : Training has run successfully!
405 01:35:35.104104 Check phy result
406 01:35:35.109513 INFO : End of initialization
407 01:35:35.109940 INFO : End of read enable training
408 01:35:35.112442 INFO : End of fine write leveling
409 01:35:35.118038 INFO : End of Write leveling coarse delay
410 01:35:35.123655 INFO : Training has run successfully!
411 01:35:35.124124 Check phy result
412 01:35:35.124534 INFO : End of initialization
413 01:35:35.129317 INFO : End of read dq deskew training
414 01:35:35.134891 INFO : End of MPR read delay center optimization
415 01:35:35.135337 INFO : End of write delay center optimization
416 01:35:35.140393 INFO : End of read delay center optimization
417 01:35:35.145994 INFO : End of max read latency training
418 01:35:35.146443 INFO : Training has run successfully!
419 01:35:35.151634 1D training succeed
420 01:35:35.157592 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 01:35:35.205126 Check phy result
422 01:35:35.205600 INFO : End of initialization
423 01:35:35.226801 INFO : End of 2D read delay Voltage center optimization
424 01:35:35.246993 INFO : End of 2D read delay Voltage center optimization
425 01:35:35.298821 INFO : End of 2D write delay Voltage center optimization
426 01:35:35.348095 INFO : End of 2D write delay Voltage center optimization
427 01:35:35.353692 INFO : Training has run successfully!
428 01:35:35.354144
429 01:35:35.354560 channel==0
430 01:35:35.359128 RxClkDly_Margin_A0==88 ps 9
431 01:35:35.359566 TxDqDly_Margin_A0==98 ps 10
432 01:35:35.362524 RxClkDly_Margin_A1==88 ps 9
433 01:35:35.362958 TxDqDly_Margin_A1==98 ps 10
434 01:35:35.368071 TrainedVREFDQ_A0==74
435 01:35:35.368508 TrainedVREFDQ_A1==75
436 01:35:35.368913 VrefDac_Margin_A0==25
437 01:35:35.373723 DeviceVref_Margin_A0==40
438 01:35:35.374152 VrefDac_Margin_A1==25
439 01:35:35.379250 DeviceVref_Margin_A1==39
440 01:35:35.379686
441 01:35:35.380130
442 01:35:35.380540 channel==1
443 01:35:35.380939 RxClkDly_Margin_A0==98 ps 10
444 01:35:35.382826 TxDqDly_Margin_A0==98 ps 10
445 01:35:35.388247 RxClkDly_Margin_A1==98 ps 10
446 01:35:35.388684 TxDqDly_Margin_A1==88 ps 9
447 01:35:35.389090 TrainedVREFDQ_A0==77
448 01:35:35.393907 TrainedVREFDQ_A1==77
449 01:35:35.394339 VrefDac_Margin_A0==22
450 01:35:35.399517 DeviceVref_Margin_A0==37
451 01:35:35.399949 VrefDac_Margin_A1==22
452 01:35:35.400392 DeviceVref_Margin_A1==37
453 01:35:35.400793
454 01:35:35.408557 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 01:35:35.409003
456 01:35:35.434382 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 01:35:35.439840 2D training succeed
458 01:35:35.445469 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 01:35:35.451020 auto size-- 65535DDR cs0 size: 2048MB
460 01:35:35.451456 DDR cs1 size: 2048MB
461 01:35:35.451861 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 01:35:35.456631 cs0 DataBus test pass
463 01:35:35.457066 cs1 DataBus test pass
464 01:35:35.462220 cs0 AddrBus test pass
465 01:35:35.462658 cs1 AddrBus test pass
466 01:35:35.463064
467 01:35:35.463465 100bdlr_step_size ps== 420
468 01:35:35.467832 result report
469 01:35:35.468303 boot times 0Enable ddr reg access
470 01:35:35.473392 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 01:35:35.489962 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 01:35:36.062182 0.0;M3 CHK:0;cm4_sp_mode 0
473 01:35:36.062819 MVN_1=0x00000000
474 01:35:36.067518 MVN_2=0x00000000
475 01:35:36.073265 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 01:35:36.073722 OPS=0x10
477 01:35:36.074136 ring efuse init
478 01:35:36.074535 chipver efuse init
479 01:35:36.078855 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 01:35:36.084446 [0.018961 Inits done]
481 01:35:36.084898 secure task start!
482 01:35:36.085308 high task start!
483 01:35:36.089007 low task start!
484 01:35:36.089438 run into bl31
485 01:35:36.095755 NOTICE: BL31: v1.3(release):4fc40b1
486 01:35:36.103532 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 01:35:36.104035 NOTICE: BL31: G12A normal boot!
488 01:35:36.128885 NOTICE: BL31: BL33 decompress pass
489 01:35:36.134529 ERROR: Error initializing runtime service opteed_fast
490 01:35:37.367578
491 01:35:37.368251
492 01:35:37.375823 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 01:35:37.376318
494 01:35:37.376737 Model: Libre Computer AML-A311D-CC Alta
495 01:35:37.584436 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 01:35:37.607634 DRAM: 2 GiB (effective 3.8 GiB)
497 01:35:37.750655 Core: 408 devices, 31 uclasses, devicetree: separate
498 01:35:37.756514 WDT: Not starting watchdog@f0d0
499 01:35:37.788726 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 01:35:37.801196 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 01:35:37.806176 ** Bad device specification mmc 0 **
502 01:35:37.816511 Card did not respond to voltage select! : -110
503 01:35:37.824159 ** Bad device specification mmc 0 **
504 01:35:37.824593 Couldn't find partition mmc 0
505 01:35:37.832557 Card did not respond to voltage select! : -110
506 01:35:37.838061 ** Bad device specification mmc 0 **
507 01:35:37.838515 Couldn't find partition mmc 0
508 01:35:37.843095 Error: could not access storage.
509 01:35:39.108603 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 01:35:39.109242 bl2_stage_init 0x01
511 01:35:39.109676 bl2_stage_init 0x81
512 01:35:39.114174 hw id: 0x0000 - pwm id 0x01
513 01:35:39.114619 bl2_stage_init 0xc1
514 01:35:39.115036 bl2_stage_init 0x02
515 01:35:39.115438
516 01:35:39.119754 L0:00000000
517 01:35:39.120240 L1:20000703
518 01:35:39.120650 L2:00008067
519 01:35:39.121050 L3:14000000
520 01:35:39.125346 B2:00402000
521 01:35:39.125770 B1:e0f83180
522 01:35:39.126197
523 01:35:39.126629 TE: 58167
524 01:35:39.127039
525 01:35:39.130968 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 01:35:39.131407
527 01:35:39.131816 Board ID = 1
528 01:35:39.136582 Set A53 clk to 24M
529 01:35:39.137064 Set A73 clk to 24M
530 01:35:39.137480 Set clk81 to 24M
531 01:35:39.142168 A53 clk: 1200 MHz
532 01:35:39.142602 A73 clk: 1200 MHz
533 01:35:39.143004 CLK81: 166.6M
534 01:35:39.143400 smccc: 00012abe
535 01:35:39.147723 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 01:35:39.153365 board id: 1
537 01:35:39.159243 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 01:35:39.169911 fw parse done
539 01:35:39.175829 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 01:35:39.218637 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 01:35:39.229465 PIEI prepare done
542 01:35:39.229973 fastboot data load
543 01:35:39.230398 fastboot data verify
544 01:35:39.234960 verify result: 266
545 01:35:39.240583 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 01:35:39.241054 LPDDR4 probe
547 01:35:39.241465 ddr clk to 1584MHz
548 01:35:39.248542 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 01:35:39.285840
550 01:35:39.286364 dmc_version 0001
551 01:35:39.292508 Check phy result
552 01:35:39.298395 INFO : End of CA training
553 01:35:39.298830 INFO : End of initialization
554 01:35:39.303963 INFO : Training has run successfully!
555 01:35:39.304439 Check phy result
556 01:35:39.309559 INFO : End of initialization
557 01:35:39.309983 INFO : End of read enable training
558 01:35:39.312904 INFO : End of fine write leveling
559 01:35:39.318506 INFO : End of Write leveling coarse delay
560 01:35:39.324159 INFO : Training has run successfully!
561 01:35:39.324591 Check phy result
562 01:35:39.324991 INFO : End of initialization
563 01:35:39.329727 INFO : End of read dq deskew training
564 01:35:39.335303 INFO : End of MPR read delay center optimization
565 01:35:39.335730 INFO : End of write delay center optimization
566 01:35:39.340909 INFO : End of read delay center optimization
567 01:35:39.346513 INFO : End of max read latency training
568 01:35:39.346945 INFO : Training has run successfully!
569 01:35:39.352206 1D training succeed
570 01:35:39.357977 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 01:35:39.405674 Check phy result
572 01:35:39.406144 INFO : End of initialization
573 01:35:39.427270 INFO : End of 2D read delay Voltage center optimization
574 01:35:39.446441 INFO : End of 2D read delay Voltage center optimization
575 01:35:39.498449 INFO : End of 2D write delay Voltage center optimization
576 01:35:39.547635 INFO : End of 2D write delay Voltage center optimization
577 01:35:39.553203 INFO : Training has run successfully!
578 01:35:39.553673
579 01:35:39.554108 channel==0
580 01:35:39.558790 RxClkDly_Margin_A0==88 ps 9
581 01:35:39.559260 TxDqDly_Margin_A0==98 ps 10
582 01:35:39.564329 RxClkDly_Margin_A1==88 ps 9
583 01:35:39.564775 TxDqDly_Margin_A1==98 ps 10
584 01:35:39.565185 TrainedVREFDQ_A0==74
585 01:35:39.569927 TrainedVREFDQ_A1==75
586 01:35:39.570410 VrefDac_Margin_A0==25
587 01:35:39.570818 DeviceVref_Margin_A0==40
588 01:35:39.575519 VrefDac_Margin_A1==25
589 01:35:39.575964 DeviceVref_Margin_A1==39
590 01:35:39.576415
591 01:35:39.576814
592 01:35:39.581212 channel==1
593 01:35:39.581642 RxClkDly_Margin_A0==88 ps 9
594 01:35:39.582036 TxDqDly_Margin_A0==98 ps 10
595 01:35:39.586709 RxClkDly_Margin_A1==88 ps 9
596 01:35:39.587132 TxDqDly_Margin_A1==88 ps 9
597 01:35:39.592308 TrainedVREFDQ_A0==77
598 01:35:39.592740 TrainedVREFDQ_A1==77
599 01:35:39.593138 VrefDac_Margin_A0==23
600 01:35:39.597931 DeviceVref_Margin_A0==37
601 01:35:39.598349 VrefDac_Margin_A1==24
602 01:35:39.603511 DeviceVref_Margin_A1==37
603 01:35:39.603928
604 01:35:39.604360 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 01:35:39.604754
606 01:35:39.637200 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
607 01:35:39.637682 2D training succeed
608 01:35:39.642724 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 01:35:39.648329 auto size-- 65535DDR cs0 size: 2048MB
610 01:35:39.648757 DDR cs1 size: 2048MB
611 01:35:39.653934 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 01:35:39.654366 cs0 DataBus test pass
613 01:35:39.659520 cs1 DataBus test pass
614 01:35:39.659963 cs0 AddrBus test pass
615 01:35:39.660409 cs1 AddrBus test pass
616 01:35:39.660803
617 01:35:39.665198 100bdlr_step_size ps== 420
618 01:35:39.665632 result report
619 01:35:39.670724 boot times 0Enable ddr reg access
620 01:35:39.676038 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 01:35:39.689450 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 01:35:40.261660 0.0;M3 CHK:0;cm4_sp_mode 0
623 01:35:40.262306 MVN_1=0x00000000
624 01:35:40.267050 MVN_2=0x00000000
625 01:35:40.272765 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 01:35:40.273261 OPS=0x10
627 01:35:40.273696 ring efuse init
628 01:35:40.274127 chipver efuse init
629 01:35:40.278332 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 01:35:40.283946 [0.018960 Inits done]
631 01:35:40.284464 secure task start!
632 01:35:40.284857 high task start!
633 01:35:40.288516 low task start!
634 01:35:40.288939 run into bl31
635 01:35:40.295297 NOTICE: BL31: v1.3(release):4fc40b1
636 01:35:40.302986 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 01:35:40.303436 NOTICE: BL31: G12A normal boot!
638 01:35:40.328429 NOTICE: BL31: BL33 decompress pass
639 01:35:40.334002 ERROR: Error initializing runtime service opteed_fast
640 01:35:41.567054
641 01:35:41.567698
642 01:35:41.575423 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 01:35:41.575897
644 01:35:41.576354 Model: Libre Computer AML-A311D-CC Alta
645 01:35:41.784017 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 01:35:41.807264 DRAM: 2 GiB (effective 3.8 GiB)
647 01:35:41.950240 Core: 408 devices, 31 uclasses, devicetree: separate
648 01:35:41.956138 WDT: Not starting watchdog@f0d0
649 01:35:41.988463 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 01:35:42.000732 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 01:35:42.005798 ** Bad device specification mmc 0 **
652 01:35:42.016058 Card did not respond to voltage select! : -110
653 01:35:42.023743 ** Bad device specification mmc 0 **
654 01:35:42.024092 Couldn't find partition mmc 0
655 01:35:42.032145 Card did not respond to voltage select! : -110
656 01:35:42.037627 ** Bad device specification mmc 0 **
657 01:35:42.038206 Couldn't find partition mmc 0
658 01:35:42.042689 Error: could not access storage.
659 01:35:42.385271 Net: eth0: ethernet@ff3f0000
660 01:35:42.385895 starting USB...
661 01:35:42.636948 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 01:35:42.637558 Starting the controller
663 01:35:42.643900 USB XHCI 1.10
664 01:35:44.359061 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 01:35:44.359468 bl2_stage_init 0x01
666 01:35:44.359714 bl2_stage_init 0x81
667 01:35:44.364420 hw id: 0x0000 - pwm id 0x01
668 01:35:44.364753 bl2_stage_init 0xc1
669 01:35:44.364994 bl2_stage_init 0x02
670 01:35:44.365225
671 01:35:44.370044 L0:00000000
672 01:35:44.370369 L1:20000703
673 01:35:44.370601 L2:00008067
674 01:35:44.370836 L3:14000000
675 01:35:44.372968 B2:00402000
676 01:35:44.373286 B1:e0f83180
677 01:35:44.373530
678 01:35:44.373761 TE: 58124
679 01:35:44.373975
680 01:35:44.384182 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 01:35:44.384556
682 01:35:44.384808 Board ID = 1
683 01:35:44.385052 Set A53 clk to 24M
684 01:35:44.385281 Set A73 clk to 24M
685 01:35:44.389604 Set clk81 to 24M
686 01:35:44.389912 A53 clk: 1200 MHz
687 01:35:44.390136 A73 clk: 1200 MHz
688 01:35:44.395245 CLK81: 166.6M
689 01:35:44.395563 smccc: 00012a91
690 01:35:44.400875 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 01:35:44.401219 board id: 1
692 01:35:44.409429 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 01:35:44.420144 fw parse done
694 01:35:44.426085 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 01:35:44.468744 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 01:35:44.479608 PIEI prepare done
697 01:35:44.480138 fastboot data load
698 01:35:44.480420 fastboot data verify
699 01:35:44.485214 verify result: 266
700 01:35:44.490772 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 01:35:44.491106 LPDDR4 probe
702 01:35:44.491339 ddr clk to 1584MHz
703 01:35:44.498713 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 01:35:44.536105
705 01:35:44.536498 dmc_version 0001
706 01:35:44.542761 Check phy result
707 01:35:44.548519 INFO : End of CA training
708 01:35:44.548870 INFO : End of initialization
709 01:35:44.554121 INFO : Training has run successfully!
710 01:35:44.554475 Check phy result
711 01:35:44.559757 INFO : End of initialization
712 01:35:44.560141 INFO : End of read enable training
713 01:35:44.563023 INFO : End of fine write leveling
714 01:35:44.568572 INFO : End of Write leveling coarse delay
715 01:35:44.574214 INFO : Training has run successfully!
716 01:35:44.574592 Check phy result
717 01:35:44.574858 INFO : End of initialization
718 01:35:44.579782 INFO : End of read dq deskew training
719 01:35:44.583190 INFO : End of MPR read delay center optimization
720 01:35:44.588804 INFO : End of write delay center optimization
721 01:35:44.594385 INFO : End of read delay center optimization
722 01:35:44.594748 INFO : End of max read latency training
723 01:35:44.599932 INFO : Training has run successfully!
724 01:35:44.600331 1D training succeed
725 01:35:44.608128 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 01:35:44.655894 Check phy result
727 01:35:44.656333 INFO : End of initialization
728 01:35:44.677576 INFO : End of 2D read delay Voltage center optimization
729 01:35:44.697764 INFO : End of 2D read delay Voltage center optimization
730 01:35:44.749880 INFO : End of 2D write delay Voltage center optimization
731 01:35:44.799163 INFO : End of 2D write delay Voltage center optimization
732 01:35:44.804707 INFO : Training has run successfully!
733 01:35:44.805077
734 01:35:44.805351 channel==0
735 01:35:44.810253 RxClkDly_Margin_A0==88 ps 9
736 01:35:44.810625 TxDqDly_Margin_A0==98 ps 10
737 01:35:44.815942 RxClkDly_Margin_A1==88 ps 9
738 01:35:44.816357 TxDqDly_Margin_A1==98 ps 10
739 01:35:44.816605 TrainedVREFDQ_A0==74
740 01:35:44.821537 TrainedVREFDQ_A1==75
741 01:35:44.821898 VrefDac_Margin_A0==24
742 01:35:44.822144 DeviceVref_Margin_A0==40
743 01:35:44.827079 VrefDac_Margin_A1==25
744 01:35:44.827425 DeviceVref_Margin_A1==39
745 01:35:44.827669
746 01:35:44.827919
747 01:35:44.832663 channel==1
748 01:35:44.833018 RxClkDly_Margin_A0==88 ps 9
749 01:35:44.833269 TxDqDly_Margin_A0==88 ps 9
750 01:35:44.838385 RxClkDly_Margin_A1==88 ps 9
751 01:35:44.838733 TxDqDly_Margin_A1==88 ps 9
752 01:35:44.843907 TrainedVREFDQ_A0==77
753 01:35:44.844283 TrainedVREFDQ_A1==77
754 01:35:44.844530 VrefDac_Margin_A0==22
755 01:35:44.849493 DeviceVref_Margin_A0==37
756 01:35:44.849844 VrefDac_Margin_A1==24
757 01:35:44.855050 DeviceVref_Margin_A1==37
758 01:35:44.855395
759 01:35:44.855650 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 01:35:44.855875
761 01:35:44.888671 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
762 01:35:44.889350 2D training succeed
763 01:35:44.894226 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 01:35:44.899695 auto size-- 65535DDR cs0 size: 2048MB
765 01:35:44.900248 DDR cs1 size: 2048MB
766 01:35:44.905438 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 01:35:44.905959 cs0 DataBus test pass
768 01:35:44.911001 cs1 DataBus test pass
769 01:35:44.911510 cs0 AddrBus test pass
770 01:35:44.912038 cs1 AddrBus test pass
771 01:35:44.912527
772 01:35:44.916626 100bdlr_step_size ps== 420
773 01:35:44.917171 result report
774 01:35:44.922189 boot times 0Enable ddr reg access
775 01:35:44.927326 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 01:35:44.941107 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 01:35:45.514577 0.0;M3 CHK:0;cm4_sp_mode 0
778 01:35:45.515275 MVN_1=0x00000000
779 01:35:45.520091 MVN_2=0x00000000
780 01:35:45.525953 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 01:35:45.526529 OPS=0x10
782 01:35:45.526982 ring efuse init
783 01:35:45.527435 chipver efuse init
784 01:35:45.531411 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 01:35:45.537049 [0.018961 Inits done]
786 01:35:45.537586 secure task start!
787 01:35:45.538039 high task start!
788 01:35:45.541610 low task start!
789 01:35:45.542107 run into bl31
790 01:35:45.548286 NOTICE: BL31: v1.3(release):4fc40b1
791 01:35:45.556135 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 01:35:45.556738 NOTICE: BL31: G12A normal boot!
793 01:35:45.581496 NOTICE: BL31: BL33 decompress pass
794 01:35:45.587156 ERROR: Error initializing runtime service opteed_fast
795 01:35:46.820201
796 01:35:46.820879
797 01:35:46.828439 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 01:35:46.828942
799 01:35:46.829391 Model: Libre Computer AML-A311D-CC Alta
800 01:35:47.037004 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 01:35:47.060287 DRAM: 2 GiB (effective 3.8 GiB)
802 01:35:47.203261 Core: 408 devices, 31 uclasses, devicetree: separate
803 01:35:47.209045 WDT: Not starting watchdog@f0d0
804 01:35:47.241316 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 01:35:47.253786 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 01:35:47.258756 ** Bad device specification mmc 0 **
807 01:35:47.269105 Card did not respond to voltage select! : -110
808 01:35:47.276753 ** Bad device specification mmc 0 **
809 01:35:47.277243 Couldn't find partition mmc 0
810 01:35:47.285115 Card did not respond to voltage select! : -110
811 01:35:47.290602 ** Bad device specification mmc 0 **
812 01:35:47.291083 Couldn't find partition mmc 0
813 01:35:47.295668 Error: could not access storage.
814 01:35:47.639329 Net: eth0: ethernet@ff3f0000
815 01:35:47.640042 starting USB...
816 01:35:47.891003 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 01:35:47.891666 Starting the controller
818 01:35:47.897937 USB XHCI 1.10
819 01:35:50.060799 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 01:35:50.061482 bl2_stage_init 0x01
821 01:35:50.061963 bl2_stage_init 0x81
822 01:35:50.066295 hw id: 0x0000 - pwm id 0x01
823 01:35:50.066839 bl2_stage_init 0xc1
824 01:35:50.067301 bl2_stage_init 0x02
825 01:35:50.067753
826 01:35:50.071941 L0:00000000
827 01:35:50.072504 L1:20000703
828 01:35:50.072964 L2:00008067
829 01:35:50.073412 L3:14000000
830 01:35:50.077476 B2:00402000
831 01:35:50.078007 B1:e0f83180
832 01:35:50.078460
833 01:35:50.078909 TE: 58124
834 01:35:50.079360
835 01:35:50.083009 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 01:35:50.083542
837 01:35:50.084035 Board ID = 1
838 01:35:50.088845 Set A53 clk to 24M
839 01:35:50.089398 Set A73 clk to 24M
840 01:35:50.089852 Set clk81 to 24M
841 01:35:50.094328 A53 clk: 1200 MHz
842 01:35:50.094887 A73 clk: 1200 MHz
843 01:35:50.095361 CLK81: 166.6M
844 01:35:50.095814 smccc: 00012a92
845 01:35:50.100040 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 01:35:50.105521 board id: 1
847 01:35:50.111498 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 01:35:50.121944 fw parse done
849 01:35:50.127925 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 01:35:50.170446 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 01:35:50.181388 PIEI prepare done
852 01:35:50.181939 fastboot data load
853 01:35:50.182404 fastboot data verify
854 01:35:50.187105 verify result: 266
855 01:35:50.192702 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 01:35:50.193236 LPDDR4 probe
857 01:35:50.193697 ddr clk to 1584MHz
858 01:35:50.200579 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 01:35:50.237841
860 01:35:50.238276 dmc_version 0001
861 01:35:50.245380 Check phy result
862 01:35:50.250624 INFO : End of CA training
863 01:35:50.251218 INFO : End of initialization
864 01:35:50.256157 INFO : Training has run successfully!
865 01:35:50.256583 Check phy result
866 01:35:50.263119 INFO : End of initialization
867 01:35:50.263572 INFO : End of read enable training
868 01:35:50.267311 INFO : End of fine write leveling
869 01:35:50.272849 INFO : End of Write leveling coarse delay
870 01:35:50.273465 INFO : Training has run successfully!
871 01:35:50.273741 Check phy result
872 01:35:50.279872 INFO : End of initialization
873 01:35:50.280327 INFO : End of read dq deskew training
874 01:35:50.285033 INFO : End of MPR read delay center optimization
875 01:35:50.289744 INFO : End of write delay center optimization
876 01:35:50.295219 INFO : End of read delay center optimization
877 01:35:50.295642 INFO : End of max read latency training
878 01:35:50.300847 INFO : Training has run successfully!
879 01:35:50.301446 1D training succeed
880 01:35:50.310049 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 01:35:50.357557 Check phy result
882 01:35:50.357984 INFO : End of initialization
883 01:35:50.379708 INFO : End of 2D read delay Voltage center optimization
884 01:35:50.400423 INFO : End of 2D read delay Voltage center optimization
885 01:35:50.451550 INFO : End of 2D write delay Voltage center optimization
886 01:35:50.500881 INFO : End of 2D write delay Voltage center optimization
887 01:35:50.506388 INFO : Training has run successfully!
888 01:35:50.506739
889 01:35:50.506971 channel==0
890 01:35:50.512072 RxClkDly_Margin_A0==88 ps 9
891 01:35:50.512425 TxDqDly_Margin_A0==98 ps 10
892 01:35:50.515422 RxClkDly_Margin_A1==88 ps 9
893 01:35:50.515746 TxDqDly_Margin_A1==88 ps 9
894 01:35:50.521047 TrainedVREFDQ_A0==74
895 01:35:50.521376 TrainedVREFDQ_A1==74
896 01:35:50.521604 VrefDac_Margin_A0==25
897 01:35:50.526624 DeviceVref_Margin_A0==40
898 01:35:50.526958 VrefDac_Margin_A1==25
899 01:35:50.532238 DeviceVref_Margin_A1==40
900 01:35:50.532567
901 01:35:50.532787
902 01:35:50.532999 channel==1
903 01:35:50.533210 RxClkDly_Margin_A0==88 ps 9
904 01:35:50.535567 TxDqDly_Margin_A0==98 ps 10
905 01:35:50.541136 RxClkDly_Margin_A1==98 ps 10
906 01:35:50.541473 TxDqDly_Margin_A1==88 ps 9
907 01:35:50.541689 TrainedVREFDQ_A0==77
908 01:35:50.546817 TrainedVREFDQ_A1==77
909 01:35:50.547157 VrefDac_Margin_A0==22
910 01:35:50.552331 DeviceVref_Margin_A0==37
911 01:35:50.552676 VrefDac_Margin_A1==24
912 01:35:50.552892 DeviceVref_Margin_A1==37
913 01:35:50.553100
914 01:35:50.561316 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 01:35:50.561669
916 01:35:50.587133 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000018 dram_vref_reg_value 0x 00000060
917 01:35:50.592758 2D training succeed
918 01:35:50.596113 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 01:35:50.601646 auto size-- 65535DDR cs0 size: 2048MB
920 01:35:50.601939 DDR cs1 size: 2048MB
921 01:35:50.607254 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 01:35:50.607549 cs0 DataBus test pass
923 01:35:50.612878 cs1 DataBus test pass
924 01:35:50.613170 cs0 AddrBus test pass
925 01:35:50.613386 cs1 AddrBus test pass
926 01:35:50.613593
927 01:35:50.618469 100bdlr_step_size ps== 420
928 01:35:50.618772 result report
929 01:35:50.624088 boot times 0Enable ddr reg access
930 01:35:50.629342 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 01:35:50.642828 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 01:35:51.216565 0.0;M3 CHK:0;cm4_sp_mode 0
933 01:35:51.217196 MVN_1=0x00000000
934 01:35:51.221996 MVN_2=0x00000000
935 01:35:51.227784 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 01:35:51.228322 OPS=0x10
937 01:35:51.228738 ring efuse init
938 01:35:51.229141 chipver efuse init
939 01:35:51.233339 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 01:35:51.238948 [0.018961 Inits done]
941 01:35:51.239402 secure task start!
942 01:35:51.239808 high task start!
943 01:35:51.243517 low task start!
944 01:35:51.243960 run into bl31
945 01:35:51.250171 NOTICE: BL31: v1.3(release):4fc40b1
946 01:35:51.257989 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 01:35:51.258448 NOTICE: BL31: G12A normal boot!
948 01:35:51.283327 NOTICE: BL31: BL33 decompress pass
949 01:35:51.289007 ERROR: Error initializing runtime service opteed_fast
950 01:35:52.521817
951 01:35:52.522250
952 01:35:52.530222 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 01:35:52.530644
954 01:35:52.530962 Model: Libre Computer AML-A311D-CC Alta
955 01:35:52.738667 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 01:35:52.762084 DRAM: 2 GiB (effective 3.8 GiB)
957 01:35:52.905011 Core: 408 devices, 31 uclasses, devicetree: separate
958 01:35:52.910911 WDT: Not starting watchdog@f0d0
959 01:35:52.943125 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 01:35:52.955586 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 01:35:52.960524 ** Bad device specification mmc 0 **
962 01:35:52.970900 Card did not respond to voltage select! : -110
963 01:35:52.978512 ** Bad device specification mmc 0 **
964 01:35:52.978961 Couldn't find partition mmc 0
965 01:35:52.986901 Card did not respond to voltage select! : -110
966 01:35:52.992381 ** Bad device specification mmc 0 **
967 01:35:52.992843 Couldn't find partition mmc 0
968 01:35:52.997431 Error: could not access storage.
969 01:35:53.340143 Net: eth0: ethernet@ff3f0000
970 01:35:53.340757 starting USB...
971 01:35:53.591735 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 01:35:53.592328 Starting the controller
973 01:35:53.599380 USB XHCI 1.10
974 01:35:55.460288 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 01:35:55.460896 bl2_stage_init 0x01
976 01:35:55.461325 bl2_stage_init 0x81
977 01:35:55.465816 hw id: 0x0000 - pwm id 0x01
978 01:35:55.466271 bl2_stage_init 0xc1
979 01:35:55.466681 bl2_stage_init 0x02
980 01:35:55.467085
981 01:35:55.471396 L0:00000000
982 01:35:55.471835 L1:20000703
983 01:35:55.472298 L2:00008067
984 01:35:55.472704 L3:14000000
985 01:35:55.477015 B2:00402000
986 01:35:55.477451 B1:e0f83180
987 01:35:55.477857
988 01:35:55.478261 TE: 58159
989 01:35:55.478662
990 01:35:55.482602 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 01:35:55.483050
992 01:35:55.483459 Board ID = 1
993 01:35:55.488200 Set A53 clk to 24M
994 01:35:55.488644 Set A73 clk to 24M
995 01:35:55.489054 Set clk81 to 24M
996 01:35:55.493800 A53 clk: 1200 MHz
997 01:35:55.494239 A73 clk: 1200 MHz
998 01:35:55.494645 CLK81: 166.6M
999 01:35:55.495042 smccc: 00012ab5
1000 01:35:55.499390 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 01:35:55.505030 board id: 1
1002 01:35:55.510893 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 01:35:55.521555 fw parse done
1004 01:35:55.527555 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 01:35:55.570264 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 01:35:55.581057 PIEI prepare done
1007 01:35:55.581513 fastboot data load
1008 01:35:55.581907 fastboot data verify
1009 01:35:55.586699 verify result: 266
1010 01:35:55.592264 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 01:35:55.592698 LPDDR4 probe
1012 01:35:55.593088 ddr clk to 1584MHz
1013 01:35:55.600291 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 01:35:55.637562
1015 01:35:55.638106 dmc_version 0001
1016 01:35:55.644296 Check phy result
1017 01:35:55.650091 INFO : End of CA training
1018 01:35:55.650512 INFO : End of initialization
1019 01:35:55.655682 INFO : Training has run successfully!
1020 01:35:55.656211 Check phy result
1021 01:35:55.661458 INFO : End of initialization
1022 01:35:55.661901 INFO : End of read enable training
1023 01:35:55.664686 INFO : End of fine write leveling
1024 01:35:55.670197 INFO : End of Write leveling coarse delay
1025 01:35:55.675843 INFO : Training has run successfully!
1026 01:35:55.676310 Check phy result
1027 01:35:55.676717 INFO : End of initialization
1028 01:35:55.681446 INFO : End of read dq deskew training
1029 01:35:55.687005 INFO : End of MPR read delay center optimization
1030 01:35:55.687440 INFO : End of write delay center optimization
1031 01:35:55.692612 INFO : End of read delay center optimization
1032 01:35:55.698365 INFO : End of max read latency training
1033 01:35:55.698848 INFO : Training has run successfully!
1034 01:35:55.703965 1D training succeed
1035 01:35:55.709880 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 01:35:55.757630 Check phy result
1037 01:35:55.758120 INFO : End of initialization
1038 01:35:55.778954 INFO : End of 2D read delay Voltage center optimization
1039 01:35:55.799100 INFO : End of 2D read delay Voltage center optimization
1040 01:35:55.851025 INFO : End of 2D write delay Voltage center optimization
1041 01:35:55.900316 INFO : End of 2D write delay Voltage center optimization
1042 01:35:55.905821 INFO : Training has run successfully!
1043 01:35:55.906263
1044 01:35:55.906674 channel==0
1045 01:35:55.911418 RxClkDly_Margin_A0==88 ps 9
1046 01:35:55.911865 TxDqDly_Margin_A0==98 ps 10
1047 01:35:55.916926 RxClkDly_Margin_A1==88 ps 9
1048 01:35:55.917366 TxDqDly_Margin_A1==98 ps 10
1049 01:35:55.917776 TrainedVREFDQ_A0==74
1050 01:35:55.922598 TrainedVREFDQ_A1==74
1051 01:35:55.923035 VrefDac_Margin_A0==25
1052 01:35:55.923439 DeviceVref_Margin_A0==40
1053 01:35:55.928247 VrefDac_Margin_A1==24
1054 01:35:55.928696 DeviceVref_Margin_A1==40
1055 01:35:55.929101
1056 01:35:55.929502
1057 01:35:55.933860 channel==1
1058 01:35:55.934302 RxClkDly_Margin_A0==98 ps 10
1059 01:35:55.934704 TxDqDly_Margin_A0==88 ps 9
1060 01:35:55.939433 RxClkDly_Margin_A1==98 ps 10
1061 01:35:55.939875 TxDqDly_Margin_A1==98 ps 10
1062 01:35:55.944991 TrainedVREFDQ_A0==77
1063 01:35:55.945445 TrainedVREFDQ_A1==77
1064 01:35:55.945853 VrefDac_Margin_A0==22
1065 01:35:55.950623 DeviceVref_Margin_A0==37
1066 01:35:55.951106 VrefDac_Margin_A1==22
1067 01:35:55.956255 DeviceVref_Margin_A1==37
1068 01:35:55.956728
1069 01:35:55.957141 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 01:35:55.961819
1071 01:35:55.989655 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1072 01:35:55.990155 2D training succeed
1073 01:35:55.995269 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 01:35:56.000871 auto size-- 65535DDR cs0 size: 2048MB
1075 01:35:56.001313 DDR cs1 size: 2048MB
1076 01:35:56.006459 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 01:35:56.006891 cs0 DataBus test pass
1078 01:35:56.012071 cs1 DataBus test pass
1079 01:35:56.012506 cs0 AddrBus test pass
1080 01:35:56.012912 cs1 AddrBus test pass
1081 01:35:56.013313
1082 01:35:56.017660 100bdlr_step_size ps== 420
1083 01:35:56.018106 result report
1084 01:35:56.023294 boot times 0Enable ddr reg access
1085 01:35:56.028742 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 01:35:56.042219 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 01:35:56.614251 0.0;M3 CHK:0;cm4_sp_mode 0
1088 01:35:56.614877 MVN_1=0x00000000
1089 01:35:56.619657 MVN_2=0x00000000
1090 01:35:56.625407 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 01:35:56.625858 OPS=0x10
1092 01:35:56.626265 ring efuse init
1093 01:35:56.626670 chipver efuse init
1094 01:35:56.630998 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 01:35:56.636575 [0.018961 Inits done]
1096 01:35:56.637012 secure task start!
1097 01:35:56.637414 high task start!
1098 01:35:56.641146 low task start!
1099 01:35:56.641577 run into bl31
1100 01:35:56.647854 NOTICE: BL31: v1.3(release):4fc40b1
1101 01:35:56.655665 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 01:35:56.656154 NOTICE: BL31: G12A normal boot!
1103 01:35:56.681633 NOTICE: BL31: BL33 decompress pass
1104 01:35:56.687273 ERROR: Error initializing runtime service opteed_fast
1105 01:35:57.920257
1106 01:35:57.920889
1107 01:35:57.928602 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 01:35:57.929080
1109 01:35:57.929507 Model: Libre Computer AML-A311D-CC Alta
1110 01:35:58.137081 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 01:35:58.160434 DRAM: 2 GiB (effective 3.8 GiB)
1112 01:35:58.303395 Core: 408 devices, 31 uclasses, devicetree: separate
1113 01:35:58.309255 WDT: Not starting watchdog@f0d0
1114 01:35:58.341588 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 01:35:58.353991 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 01:35:58.358954 ** Bad device specification mmc 0 **
1117 01:35:58.369310 Card did not respond to voltage select! : -110
1118 01:35:58.376936 ** Bad device specification mmc 0 **
1119 01:35:58.377385 Couldn't find partition mmc 0
1120 01:35:58.385303 Card did not respond to voltage select! : -110
1121 01:35:58.390796 ** Bad device specification mmc 0 **
1122 01:35:58.391243 Couldn't find partition mmc 0
1123 01:35:58.395851 Error: could not access storage.
1124 01:35:58.739496 Net: eth0: ethernet@ff3f0000
1125 01:35:58.740148 starting USB...
1126 01:35:58.991225 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 01:35:58.991651 Starting the controller
1128 01:35:58.998137 USB XHCI 1.10
1129 01:36:00.555405 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 01:36:00.563722 scanning usb for storage devices... 0 Storage Device(s) found
1132 01:36:00.615555 Hit any key to stop autoboot: 1
1133 01:36:00.616381 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 01:36:00.616729 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 01:36:00.616981 Setting prompt string to ['=>']
1136 01:36:00.617233 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 01:36:00.631575 0
1138 01:36:00.632566 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 01:36:00.633127 Sending with 10 millisecond of delay
1141 01:36:01.768103 => setenv autoload no
1142 01:36:01.778957 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1143 01:36:01.784315 setenv autoload no
1144 01:36:01.785125 Sending with 10 millisecond of delay
1146 01:36:03.582310 => setenv initrd_high 0xffffffff
1147 01:36:03.593164 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 01:36:03.594060 setenv initrd_high 0xffffffff
1149 01:36:03.594827 Sending with 10 millisecond of delay
1151 01:36:05.212985 => setenv fdt_high 0xffffffff
1152 01:36:05.223767 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 01:36:05.224643 setenv fdt_high 0xffffffff
1154 01:36:05.225226 Sending with 10 millisecond of delay
1156 01:36:05.518689 => dhcp
1157 01:36:05.530118 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 01:36:05.530817 dhcp
1159 01:36:05.531073 Speed: 1000, full duplex
1160 01:36:05.531285 BOOTP broadcast 1
1161 01:36:05.537355 DHCP client bound to address 192.168.6.27 (8 ms)
1162 01:36:05.539302 Sending with 10 millisecond of delay
1164 01:36:07.215946 => setenv serverip 192.168.6.2
1165 01:36:07.226811 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 01:36:07.227725 setenv serverip 192.168.6.2
1167 01:36:07.228479 Sending with 10 millisecond of delay
1169 01:36:10.951615 => tftpboot 0x01080000 949404/tftp-deploy-uhmqco8q/kernel/uImage
1170 01:36:10.962431 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 01:36:10.963305 tftpboot 0x01080000 949404/tftp-deploy-uhmqco8q/kernel/uImage
1172 01:36:10.963751 Speed: 1000, full duplex
1173 01:36:10.964206 Using ethernet@ff3f0000 device
1174 01:36:10.965207 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 01:36:10.970636 Filename '949404/tftp-deploy-uhmqco8q/kernel/uImage'.
1176 01:36:10.974798 Load address: 0x1080000
1177 01:36:13.276571 Loading: *################################################## 36.1 MiB
1178 01:36:13.277186 15.7 MiB/s
1179 01:36:13.277619 done
1180 01:36:13.281067 Bytes transferred = 37880384 (2420240 hex)
1181 01:36:13.281864 Sending with 10 millisecond of delay
1183 01:36:17.969657 => tftpboot 0x08000000 949404/tftp-deploy-uhmqco8q/ramdisk/ramdisk.cpio.gz.uboot
1184 01:36:17.980492 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 01:36:17.981386 tftpboot 0x08000000 949404/tftp-deploy-uhmqco8q/ramdisk/ramdisk.cpio.gz.uboot
1186 01:36:17.981837 Speed: 1000, full duplex
1187 01:36:17.982252 Using ethernet@ff3f0000 device
1188 01:36:17.983370 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 01:36:17.995059 Filename '949404/tftp-deploy-uhmqco8q/ramdisk/ramdisk.cpio.gz.uboot'.
1190 01:36:17.995604 Load address: 0x8000000
1191 01:36:22.947030 Loading: *### UDP wrong checksum 000000ff 0000edb4
1192 01:36:22.985548 UDP wrong checksum 000000ff 000078a7
1193 01:36:24.570242 T ############################################## UDP wrong checksum 00000005 00008483
1194 01:36:29.572378 T UDP wrong checksum 00000005 00008483
1195 01:36:39.574358 T T UDP wrong checksum 00000005 00008483
1196 01:36:43.297762 UDP wrong checksum 000000ff 00001516
1197 01:36:43.347608 UDP wrong checksum 000000ff 00009f08
1198 01:36:59.578297 T T T T UDP wrong checksum 00000005 00008483
1199 01:37:14.581842 T T
1200 01:37:14.582280 Retry count exceeded; starting again
1202 01:37:14.584398 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1205 01:37:14.585399 end: 2.4 uboot-commands (duration 00:01:51) [common]
1207 01:37:14.586151 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1209 01:37:14.587025 end: 2 uboot-action (duration 00:01:51) [common]
1211 01:37:14.588233 Cleaning after the job
1212 01:37:14.589074 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/ramdisk
1213 01:37:14.590679 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/kernel
1214 01:37:14.621047 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/dtb
1215 01:37:14.622377 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/nfsrootfs
1216 01:37:14.670479 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949404/tftp-deploy-uhmqco8q/modules
1217 01:37:14.680380 start: 4.1 power-off (timeout 00:00:30) [common]
1218 01:37:14.681134 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1219 01:37:14.717402 >> OK - accepted request
1220 01:37:14.719593 Returned 0 in 0 seconds
1221 01:37:14.820524 end: 4.1 power-off (duration 00:00:00) [common]
1223 01:37:14.821670 start: 4.2 read-feedback (timeout 00:10:00) [common]
1224 01:37:14.822452 Listened to connection for namespace 'common' for up to 1s
1225 01:37:15.823370 Finalising connection for namespace 'common'
1226 01:37:15.823881 Disconnecting from shell: Finalise
1227 01:37:15.824205 =>
1228 01:37:15.924889 end: 4.2 read-feedback (duration 00:00:01) [common]
1229 01:37:15.925296 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949404
1230 01:37:18.841391 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949404
1231 01:37:18.842255 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.