Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 00:08:01.002591 lava-dispatcher, installed at version: 2024.01
2 00:08:01.003364 start: 0 validate
3 00:08:01.003833 Start time: 2024-11-07 00:08:01.003802+00:00 (UTC)
4 00:08:01.004383 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:08:01.004930 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:08:01.044858 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:08:01.045406 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 00:08:01.078714 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:08:01.079337 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 00:08:01.111838 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:08:01.112460 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:08:01.144813 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 00:08:01.145446 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
14 00:08:01.187254 validate duration: 0.18
16 00:08:01.188193 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:08:01.188575 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:08:01.188912 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:08:01.189536 Not decompressing ramdisk as can be used compressed.
20 00:08:01.190013 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 00:08:01.190331 saving as /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/ramdisk/initrd.cpio.gz
22 00:08:01.190631 total size: 5628140 (5 MB)
23 00:08:01.231339 progress 0 % (0 MB)
24 00:08:01.237209 progress 5 % (0 MB)
25 00:08:01.243147 progress 10 % (0 MB)
26 00:08:01.248338 progress 15 % (0 MB)
27 00:08:01.254249 progress 20 % (1 MB)
28 00:08:01.259517 progress 25 % (1 MB)
29 00:08:01.265301 progress 30 % (1 MB)
30 00:08:01.271577 progress 35 % (1 MB)
31 00:08:01.276765 progress 40 % (2 MB)
32 00:08:01.282445 progress 45 % (2 MB)
33 00:08:01.287619 progress 50 % (2 MB)
34 00:08:01.293726 progress 55 % (2 MB)
35 00:08:01.299615 progress 60 % (3 MB)
36 00:08:01.304596 progress 65 % (3 MB)
37 00:08:01.310128 progress 70 % (3 MB)
38 00:08:01.315096 progress 75 % (4 MB)
39 00:08:01.321631 progress 80 % (4 MB)
40 00:08:01.327279 progress 85 % (4 MB)
41 00:08:01.332933 progress 90 % (4 MB)
42 00:08:01.338026 progress 95 % (5 MB)
43 00:08:01.342348 progress 100 % (5 MB)
44 00:08:01.343484 5 MB downloaded in 0.15 s (35.12 MB/s)
45 00:08:01.344341 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:08:01.345609 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:08:01.346028 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:08:01.346450 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:08:01.347371 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/kernel/Image
51 00:08:01.347768 saving as /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/kernel/Image
52 00:08:01.348662 total size: 37880320 (36 MB)
53 00:08:01.348988 No compression specified
54 00:08:01.392311 progress 0 % (0 MB)
55 00:08:01.423238 progress 5 % (1 MB)
56 00:08:01.454746 progress 10 % (3 MB)
57 00:08:01.485562 progress 15 % (5 MB)
58 00:08:01.517369 progress 20 % (7 MB)
59 00:08:01.547699 progress 25 % (9 MB)
60 00:08:01.571506 progress 30 % (10 MB)
61 00:08:01.595669 progress 35 % (12 MB)
62 00:08:01.619562 progress 40 % (14 MB)
63 00:08:01.643630 progress 45 % (16 MB)
64 00:08:01.667342 progress 50 % (18 MB)
65 00:08:01.691075 progress 55 % (19 MB)
66 00:08:01.715097 progress 60 % (21 MB)
67 00:08:01.738896 progress 65 % (23 MB)
68 00:08:01.762606 progress 70 % (25 MB)
69 00:08:01.786246 progress 75 % (27 MB)
70 00:08:01.809825 progress 80 % (28 MB)
71 00:08:01.833344 progress 85 % (30 MB)
72 00:08:01.856910 progress 90 % (32 MB)
73 00:08:01.880609 progress 95 % (34 MB)
74 00:08:01.903974 progress 100 % (36 MB)
75 00:08:01.904482 36 MB downloaded in 0.56 s (65.00 MB/s)
76 00:08:01.904949 end: 1.2.1 http-download (duration 00:00:01) [common]
78 00:08:01.905756 end: 1.2 download-retry (duration 00:00:01) [common]
79 00:08:01.906028 start: 1.3 download-retry (timeout 00:09:59) [common]
80 00:08:01.906293 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 00:08:01.906781 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 00:08:01.907049 saving as /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/dtb/meson-g12b-a311d-libretech-cc.dtb
83 00:08:01.907258 total size: 54703 (0 MB)
84 00:08:01.907467 No compression specified
85 00:08:01.943144 progress 59 % (0 MB)
86 00:08:01.944051 progress 100 % (0 MB)
87 00:08:01.944659 0 MB downloaded in 0.04 s (1.40 MB/s)
88 00:08:01.945196 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:08:01.946028 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:08:01.946302 start: 1.4 download-retry (timeout 00:09:59) [common]
92 00:08:01.946567 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 00:08:01.947028 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 00:08:01.947284 saving as /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/nfsrootfs/full.rootfs.tar
95 00:08:01.947493 total size: 474398908 (452 MB)
96 00:08:01.947707 Using unxz to decompress xz
97 00:08:01.985164 progress 0 % (0 MB)
98 00:08:03.102229 progress 5 % (22 MB)
99 00:08:04.536355 progress 10 % (45 MB)
100 00:08:04.988325 progress 15 % (67 MB)
101 00:08:05.775053 progress 20 % (90 MB)
102 00:08:06.339837 progress 25 % (113 MB)
103 00:08:06.727876 progress 30 % (135 MB)
104 00:08:07.336030 progress 35 % (158 MB)
105 00:08:08.170514 progress 40 % (181 MB)
106 00:08:08.922217 progress 45 % (203 MB)
107 00:08:09.497333 progress 50 % (226 MB)
108 00:08:10.143781 progress 55 % (248 MB)
109 00:08:11.367666 progress 60 % (271 MB)
110 00:08:12.877289 progress 65 % (294 MB)
111 00:08:14.545371 progress 70 % (316 MB)
112 00:08:17.820847 progress 75 % (339 MB)
113 00:08:20.247167 progress 80 % (361 MB)
114 00:08:23.143034 progress 85 % (384 MB)
115 00:08:26.269683 progress 90 % (407 MB)
116 00:08:29.426617 progress 95 % (429 MB)
117 00:08:32.563837 progress 100 % (452 MB)
118 00:08:32.576766 452 MB downloaded in 30.63 s (14.77 MB/s)
119 00:08:32.577704 end: 1.4.1 http-download (duration 00:00:31) [common]
121 00:08:32.579458 end: 1.4 download-retry (duration 00:00:31) [common]
122 00:08:32.580082 start: 1.5 download-retry (timeout 00:09:29) [common]
123 00:08:32.580672 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 00:08:32.581532 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/modules.tar.xz
125 00:08:32.582032 saving as /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/modules/modules.tar
126 00:08:32.582479 total size: 11768476 (11 MB)
127 00:08:32.582934 Using unxz to decompress xz
128 00:08:32.630380 progress 0 % (0 MB)
129 00:08:32.697484 progress 5 % (0 MB)
130 00:08:32.772260 progress 10 % (1 MB)
131 00:08:32.867181 progress 15 % (1 MB)
132 00:08:32.963318 progress 20 % (2 MB)
133 00:08:33.042503 progress 25 % (2 MB)
134 00:08:33.119713 progress 30 % (3 MB)
135 00:08:33.200533 progress 35 % (3 MB)
136 00:08:33.280810 progress 40 % (4 MB)
137 00:08:33.358287 progress 45 % (5 MB)
138 00:08:33.443082 progress 50 % (5 MB)
139 00:08:33.526122 progress 55 % (6 MB)
140 00:08:33.611375 progress 60 % (6 MB)
141 00:08:33.693377 progress 65 % (7 MB)
142 00:08:33.775398 progress 70 % (7 MB)
143 00:08:33.861277 progress 75 % (8 MB)
144 00:08:33.945136 progress 80 % (9 MB)
145 00:08:34.026085 progress 85 % (9 MB)
146 00:08:34.109738 progress 90 % (10 MB)
147 00:08:34.188897 progress 95 % (10 MB)
148 00:08:34.267634 progress 100 % (11 MB)
149 00:08:34.278166 11 MB downloaded in 1.70 s (6.62 MB/s)
150 00:08:34.278749 end: 1.5.1 http-download (duration 00:00:02) [common]
152 00:08:34.279608 end: 1.5 download-retry (duration 00:00:02) [common]
153 00:08:34.279886 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 00:08:34.280395 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 00:08:49.798669 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/949360/extract-nfsrootfs-g56yu928
156 00:08:49.799276 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 00:08:49.799562 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 00:08:49.800295 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p
159 00:08:49.800770 makedir: /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin
160 00:08:49.801116 makedir: /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/tests
161 00:08:49.801429 makedir: /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/results
162 00:08:49.801758 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-add-keys
163 00:08:49.802272 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-add-sources
164 00:08:49.802763 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-background-process-start
165 00:08:49.803257 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-background-process-stop
166 00:08:49.803771 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-common-functions
167 00:08:49.804292 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-echo-ipv4
168 00:08:49.804799 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-install-packages
169 00:08:49.805307 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-installed-packages
170 00:08:49.805775 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-os-build
171 00:08:49.806235 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-probe-channel
172 00:08:49.806724 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-probe-ip
173 00:08:49.807187 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-target-ip
174 00:08:49.807650 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-target-mac
175 00:08:49.808161 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-target-storage
176 00:08:49.808680 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-test-case
177 00:08:49.809177 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-test-event
178 00:08:49.809640 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-test-feedback
179 00:08:49.810104 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-test-raise
180 00:08:49.810569 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-test-reference
181 00:08:49.811029 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-test-runner
182 00:08:49.811497 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-test-set
183 00:08:49.811958 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-test-shell
184 00:08:49.812488 Updating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-install-packages (oe)
185 00:08:49.813037 Updating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/bin/lava-installed-packages (oe)
186 00:08:49.813469 Creating /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/environment
187 00:08:49.813826 LAVA metadata
188 00:08:49.814078 - LAVA_JOB_ID=949360
189 00:08:49.814288 - LAVA_DISPATCHER_IP=192.168.6.2
190 00:08:49.814640 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 00:08:49.815572 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 00:08:49.815872 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 00:08:49.816102 skipped lava-vland-overlay
194 00:08:49.816344 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 00:08:49.816595 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 00:08:49.816811 skipped lava-multinode-overlay
197 00:08:49.817051 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 00:08:49.817300 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 00:08:49.817542 Loading test definitions
200 00:08:49.817814 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 00:08:49.818033 Using /lava-949360 at stage 0
202 00:08:49.819144 uuid=949360_1.6.2.4.1 testdef=None
203 00:08:49.819441 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 00:08:49.819699 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 00:08:49.821532 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 00:08:49.822320 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 00:08:49.824473 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 00:08:49.825294 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 00:08:49.827322 runner path: /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 949360_1.6.2.4.1
212 00:08:49.827879 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 00:08:49.828653 Creating lava-test-runner.conf files
215 00:08:49.828852 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949360/lava-overlay-em5vm93p/lava-949360/0 for stage 0
216 00:08:49.829174 - 0_v4l2-decoder-conformance-h264
217 00:08:49.829508 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 00:08:49.829776 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 00:08:49.851296 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 00:08:49.851662 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 00:08:49.851918 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 00:08:49.852211 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 00:08:49.852474 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 00:08:50.466554 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 00:08:50.467024 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 00:08:50.467272 extracting modules file /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949360/extract-nfsrootfs-g56yu928
227 00:08:51.840452 extracting modules file /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949360/extract-overlay-ramdisk-o6533h_j/ramdisk
228 00:08:53.244272 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 00:08:53.244728 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 00:08:53.245007 [common] Applying overlay to NFS
231 00:08:53.245220 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949360/compress-overlay-seipllfi/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949360/extract-nfsrootfs-g56yu928
232 00:08:53.274332 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 00:08:53.274722 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 00:08:53.274996 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 00:08:53.275224 Converting downloaded kernel to a uImage
236 00:08:53.275529 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/kernel/Image /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/kernel/uImage
237 00:08:53.673472 output: Image Name:
238 00:08:53.673864 output: Created: Thu Nov 7 00:08:53 2024
239 00:08:53.674076 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 00:08:53.674280 output: Data Size: 37880320 Bytes = 36992.50 KiB = 36.13 MiB
241 00:08:53.674482 output: Load Address: 01080000
242 00:08:53.674681 output: Entry Point: 01080000
243 00:08:53.674878 output:
244 00:08:53.675208 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 00:08:53.675477 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 00:08:53.675745 start: 1.6.7 configure-preseed-file (timeout 00:09:08) [common]
247 00:08:53.676033 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 00:08:53.676306 start: 1.6.8 compress-ramdisk (timeout 00:09:08) [common]
249 00:08:53.676566 Building ramdisk /var/lib/lava/dispatcher/tmp/949360/extract-overlay-ramdisk-o6533h_j/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949360/extract-overlay-ramdisk-o6533h_j/ramdisk
250 00:08:55.892343 >> 173443 blocks
251 00:09:03.560161 Adding RAMdisk u-boot header.
252 00:09:03.560846 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949360/extract-overlay-ramdisk-o6533h_j/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949360/extract-overlay-ramdisk-o6533h_j/ramdisk.cpio.gz.uboot
253 00:09:03.851118 output: Image Name:
254 00:09:03.851770 output: Created: Thu Nov 7 00:09:03 2024
255 00:09:03.852653 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 00:09:03.853138 output: Data Size: 24150017 Bytes = 23584.00 KiB = 23.03 MiB
257 00:09:03.853600 output: Load Address: 00000000
258 00:09:03.854055 output: Entry Point: 00000000
259 00:09:03.854501 output:
260 00:09:03.855693 rename /var/lib/lava/dispatcher/tmp/949360/extract-overlay-ramdisk-o6533h_j/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/ramdisk/ramdisk.cpio.gz.uboot
261 00:09:03.856571 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 00:09:03.857213 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 00:09:03.857820 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 00:09:03.858343 No LXC device requested
265 00:09:03.858922 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 00:09:03.859501 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 00:09:03.860108 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 00:09:03.860593 Checking files for TFTP limit of 4294967296 bytes.
269 00:09:03.863645 end: 1 tftp-deploy (duration 00:01:03) [common]
270 00:09:03.864509 start: 2 uboot-action (timeout 00:05:00) [common]
271 00:09:03.865123 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 00:09:03.865701 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 00:09:03.866285 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 00:09:03.866901 Using kernel file from prepare-kernel: 949360/tftp-deploy-zkbe9cn4/kernel/uImage
275 00:09:03.867620 substitutions:
276 00:09:03.868122 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 00:09:03.868585 - {DTB_ADDR}: 0x01070000
278 00:09:03.869033 - {DTB}: 949360/tftp-deploy-zkbe9cn4/dtb/meson-g12b-a311d-libretech-cc.dtb
279 00:09:03.869479 - {INITRD}: 949360/tftp-deploy-zkbe9cn4/ramdisk/ramdisk.cpio.gz.uboot
280 00:09:03.869923 - {KERNEL_ADDR}: 0x01080000
281 00:09:03.870361 - {KERNEL}: 949360/tftp-deploy-zkbe9cn4/kernel/uImage
282 00:09:03.870801 - {LAVA_MAC}: None
283 00:09:03.871281 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/949360/extract-nfsrootfs-g56yu928
284 00:09:03.871730 - {NFS_SERVER_IP}: 192.168.6.2
285 00:09:03.872210 - {PRESEED_CONFIG}: None
286 00:09:03.872656 - {PRESEED_LOCAL}: None
287 00:09:03.873109 - {RAMDISK_ADDR}: 0x08000000
288 00:09:03.873543 - {RAMDISK}: 949360/tftp-deploy-zkbe9cn4/ramdisk/ramdisk.cpio.gz.uboot
289 00:09:03.873978 - {ROOT_PART}: None
290 00:09:03.874412 - {ROOT}: None
291 00:09:03.874850 - {SERVER_IP}: 192.168.6.2
292 00:09:03.875293 - {TEE_ADDR}: 0x83000000
293 00:09:03.875736 - {TEE}: None
294 00:09:03.876228 Parsed boot commands:
295 00:09:03.876672 - setenv autoload no
296 00:09:03.877172 - setenv initrd_high 0xffffffff
297 00:09:03.877630 - setenv fdt_high 0xffffffff
298 00:09:03.878095 - dhcp
299 00:09:03.878544 - setenv serverip 192.168.6.2
300 00:09:03.878977 - tftpboot 0x01080000 949360/tftp-deploy-zkbe9cn4/kernel/uImage
301 00:09:03.879407 - tftpboot 0x08000000 949360/tftp-deploy-zkbe9cn4/ramdisk/ramdisk.cpio.gz.uboot
302 00:09:03.879832 - tftpboot 0x01070000 949360/tftp-deploy-zkbe9cn4/dtb/meson-g12b-a311d-libretech-cc.dtb
303 00:09:03.880300 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/949360/extract-nfsrootfs-g56yu928,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 00:09:03.880749 - bootm 0x01080000 0x08000000 0x01070000
305 00:09:03.881337 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 00:09:03.883029 start: 2.3 connect-device (timeout 00:05:00) [common]
308 00:09:03.883510 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 00:09:03.900040 Setting prompt string to ['lava-test: # ']
310 00:09:03.901726 end: 2.3 connect-device (duration 00:00:00) [common]
311 00:09:03.902394 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 00:09:03.903014 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 00:09:03.903616 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 00:09:03.904929 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 00:09:03.946686 >> OK - accepted request
316 00:09:03.948831 Returned 0 in 0 seconds
317 00:09:04.050064 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 00:09:04.051949 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 00:09:04.052678 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 00:09:04.053286 Setting prompt string to ['Hit any key to stop autoboot']
322 00:09:04.053857 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 00:09:04.055727 Trying 192.168.56.21...
324 00:09:04.056312 Connected to conserv1.
325 00:09:04.056830 Escape character is '^]'.
326 00:09:04.057391
327 00:09:04.057936 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 00:09:04.058387
329 00:09:15.431752 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 00:09:15.432289 bl2_stage_init 0x01
331 00:09:15.432550 bl2_stage_init 0x81
332 00:09:15.437179 hw id: 0x0000 - pwm id 0x01
333 00:09:15.437592 bl2_stage_init 0xc1
334 00:09:15.437847 bl2_stage_init 0x02
335 00:09:15.438078
336 00:09:15.442694 L0:00000000
337 00:09:15.443094 L1:20000703
338 00:09:15.443352 L2:00008067
339 00:09:15.443581 L3:14000000
340 00:09:15.445736 B2:00402000
341 00:09:15.446121 B1:e0f83180
342 00:09:15.446368
343 00:09:15.446598 TE: 58167
344 00:09:15.446823
345 00:09:15.456948 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 00:09:15.457387
347 00:09:15.457625 Board ID = 1
348 00:09:15.457853 Set A53 clk to 24M
349 00:09:15.458091 Set A73 clk to 24M
350 00:09:15.462586 Set clk81 to 24M
351 00:09:15.462982 A53 clk: 1200 MHz
352 00:09:15.463214 A73 clk: 1200 MHz
353 00:09:15.468088 CLK81: 166.6M
354 00:09:15.468489 smccc: 00012abe
355 00:09:15.473678 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 00:09:15.474084 board id: 1
357 00:09:15.482204 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 00:09:15.492889 fw parse done
359 00:09:15.498811 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 00:09:15.541452 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 00:09:15.552387 PIEI prepare done
362 00:09:15.553033 fastboot data load
363 00:09:15.553505 fastboot data verify
364 00:09:15.558048 verify result: 266
365 00:09:15.563730 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 00:09:15.564196 LPDDR4 probe
367 00:09:15.564480 ddr clk to 1584MHz
368 00:09:15.571673 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 00:09:15.608914
370 00:09:15.609361 dmc_version 0001
371 00:09:15.615623 Check phy result
372 00:09:15.621492 INFO : End of CA training
373 00:09:15.621930 INFO : End of initialization
374 00:09:15.627036 INFO : Training has run successfully!
375 00:09:15.627471 Check phy result
376 00:09:15.632739 INFO : End of initialization
377 00:09:15.633158 INFO : End of read enable training
378 00:09:15.636012 INFO : End of fine write leveling
379 00:09:15.641521 INFO : End of Write leveling coarse delay
380 00:09:15.647089 INFO : Training has run successfully!
381 00:09:15.647694 Check phy result
382 00:09:15.648224 INFO : End of initialization
383 00:09:15.652751 INFO : End of read dq deskew training
384 00:09:15.658281 INFO : End of MPR read delay center optimization
385 00:09:15.658896 INFO : End of write delay center optimization
386 00:09:15.663866 INFO : End of read delay center optimization
387 00:09:15.669461 INFO : End of max read latency training
388 00:09:15.670030 INFO : Training has run successfully!
389 00:09:15.675069 1D training succeed
390 00:09:15.681030 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 00:09:15.728623 Check phy result
392 00:09:15.729230 INFO : End of initialization
393 00:09:15.750408 INFO : End of 2D read delay Voltage center optimization
394 00:09:15.770632 INFO : End of 2D read delay Voltage center optimization
395 00:09:15.822757 INFO : End of 2D write delay Voltage center optimization
396 00:09:15.872148 INFO : End of 2D write delay Voltage center optimization
397 00:09:15.877554 INFO : Training has run successfully!
398 00:09:15.877991
399 00:09:15.878267 channel==0
400 00:09:15.883278 RxClkDly_Margin_A0==88 ps 9
401 00:09:15.883729 TxDqDly_Margin_A0==98 ps 10
402 00:09:15.886529 RxClkDly_Margin_A1==88 ps 9
403 00:09:15.886955 TxDqDly_Margin_A1==98 ps 10
404 00:09:15.892125 TrainedVREFDQ_A0==74
405 00:09:15.892574 TrainedVREFDQ_A1==74
406 00:09:15.897590 VrefDac_Margin_A0==25
407 00:09:15.898017 DeviceVref_Margin_A0==40
408 00:09:15.898275 VrefDac_Margin_A1==25
409 00:09:15.903313 DeviceVref_Margin_A1==40
410 00:09:15.903751
411 00:09:15.904084
412 00:09:15.904381 channel==1
413 00:09:15.904668 RxClkDly_Margin_A0==98 ps 10
414 00:09:15.908815 TxDqDly_Margin_A0==98 ps 10
415 00:09:15.909256 RxClkDly_Margin_A1==98 ps 10
416 00:09:15.914476 TxDqDly_Margin_A1==88 ps 9
417 00:09:15.914901 TrainedVREFDQ_A0==77
418 00:09:15.915184 TrainedVREFDQ_A1==77
419 00:09:15.920117 VrefDac_Margin_A0==22
420 00:09:15.920552 DeviceVref_Margin_A0==37
421 00:09:15.926041 VrefDac_Margin_A1==24
422 00:09:15.926482 DeviceVref_Margin_A1==37
423 00:09:15.926774
424 00:09:15.931260 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 00:09:15.931699
426 00:09:15.959245 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000016 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 00:09:15.964788 2D training succeed
428 00:09:15.970423 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 00:09:15.970854 auto size-- 65535DDR cs0 size: 2048MB
430 00:09:15.976033 DDR cs1 size: 2048MB
431 00:09:15.976460 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 00:09:15.981613 cs0 DataBus test pass
433 00:09:15.982067 cs1 DataBus test pass
434 00:09:15.982345 cs0 AddrBus test pass
435 00:09:15.987193 cs1 AddrBus test pass
436 00:09:15.987624
437 00:09:15.987895 100bdlr_step_size ps== 420
438 00:09:15.988197 result report
439 00:09:15.992768 boot times 0Enable ddr reg access
440 00:09:16.000658 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 00:09:16.014153 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 00:09:16.587142 0.0;M3 CHK:0;cm4_sp_mode 0
443 00:09:16.587790 MVN_1=0x00000000
444 00:09:16.592608 MVN_2=0x00000000
445 00:09:16.598276 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 00:09:16.598782 OPS=0x10
447 00:09:16.599198 ring efuse init
448 00:09:16.599601 chipver efuse init
449 00:09:16.606622 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 00:09:16.607143 [0.018960 Inits done]
451 00:09:16.607551 secure task start!
452 00:09:16.614242 high task start!
453 00:09:16.614757 low task start!
454 00:09:16.615174 run into bl31
455 00:09:16.620893 NOTICE: BL31: v1.3(release):4fc40b1
456 00:09:16.628722 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 00:09:16.629245 NOTICE: BL31: G12A normal boot!
458 00:09:16.653945 NOTICE: BL31: BL33 decompress pass
459 00:09:16.659724 ERROR: Error initializing runtime service opteed_fast
460 00:09:17.892628
461 00:09:17.893219
462 00:09:17.901100 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 00:09:17.901561
464 00:09:17.901982 Model: Libre Computer AML-A311D-CC Alta
465 00:09:18.109538 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 00:09:18.132859 DRAM: 2 GiB (effective 3.8 GiB)
467 00:09:18.275911 Core: 408 devices, 31 uclasses, devicetree: separate
468 00:09:18.281621 WDT: Not starting watchdog@f0d0
469 00:09:19.541953 MMC: G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
470 00:09:19.542375 bl2_stage_init 0x01
471 00:09:19.542600 bl2_stage_init 0x81
472 00:09:19.547659 hw id: 0x0000 - pwm id 0x01
473 00:09:19.548108 bl2_stage_init 0xc1
474 00:09:19.548448 bl2_stage_init 0x02
475 00:09:19.548765
476 00:09:19.553246 L0:00000000
477 00:09:19.553614 L1:20000703
478 00:09:19.553853 L2:00008067
479 00:09:19.554061 L3:14000000
480 00:09:19.558901 B2:00402000
481 00:09:19.559271 B1:e0f83180
482 00:09:19.559588
483 00:09:19.559901 TE: 58167
484 00:09:19.560249
485 00:09:19.564374 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
486 00:09:19.564656
487 00:09:19.564872 Board ID = 1
488 00:09:19.569960 Set A53 clk to 24M
489 00:09:19.570233 Set A73 clk to 24M
490 00:09:19.570449 Set clk81 to 24M
491 00:09:19.575489 A53 clk: 1200 MHz
492 00:09:19.575864 A73 clk: 1200 MHz
493 00:09:19.576213 CLK81: 166.6M
494 00:09:19.576525 smccc: 00012abd
495 00:09:19.581065 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
496 00:09:19.586667 board id: 1
497 00:09:19.592547 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
498 00:09:19.603163 fw parse done
499 00:09:19.609175 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
500 00:09:19.651797 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
501 00:09:19.662717 PIEI prepare done
502 00:09:19.663172 fastboot data load
503 00:09:19.663591 fastboot data verify
504 00:09:19.668448 verify result: 266
505 00:09:19.673924 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
506 00:09:19.674355 LPDDR4 probe
507 00:09:19.674763 ddr clk to 1584MHz
508 00:09:19.681925 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 00:09:19.719267
510 00:09:19.719712 dmc_version 0001
511 00:09:19.725893 Check phy result
512 00:09:19.731761 INFO : End of CA training
513 00:09:19.732217 INFO : End of initialization
514 00:09:19.737354 INFO : Training has run successfully!
515 00:09:19.737804 Check phy result
516 00:09:19.742974 INFO : End of initialization
517 00:09:19.743406 INFO : End of read enable training
518 00:09:19.748595 INFO : End of fine write leveling
519 00:09:19.754176 INFO : End of Write leveling coarse delay
520 00:09:19.754608 INFO : Training has run successfully!
521 00:09:19.755016 Check phy result
522 00:09:19.759773 INFO : End of initialization
523 00:09:19.760227 INFO : End of read dq deskew training
524 00:09:19.765284 INFO : End of MPR read delay center optimization
525 00:09:19.770953 INFO : End of write delay center optimization
526 00:09:19.776650 INFO : End of read delay center optimization
527 00:09:19.777088 INFO : End of max read latency training
528 00:09:19.782232 INFO : Training has run successfully!
529 00:09:19.782662 1D training succeed
530 00:09:19.791437 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
531 00:09:19.839003 Check phy result
532 00:09:19.839471 INFO : End of initialization
533 00:09:19.860732 INFO : End of 2D read delay Voltage center optimization
534 00:09:19.880191 INFO : End of 2D read delay Voltage center optimization
535 00:09:19.932214 INFO : End of 2D write delay Voltage center optimization
536 00:09:19.981459 INFO : End of 2D write delay Voltage center optimization
537 00:09:19.987053 INFO : Training has run successfully!
538 00:09:19.987488
539 00:09:19.987900 channel==0
540 00:09:19.992720 RxClkDly_Margin_A0==88 ps 9
541 00:09:19.993163 TxDqDly_Margin_A0==98 ps 10
542 00:09:19.996289 RxClkDly_Margin_A1==88 ps 9
543 00:09:19.996758 TxDqDly_Margin_A1==98 ps 10
544 00:09:20.001796 TrainedVREFDQ_A0==74
545 00:09:20.002232 TrainedVREFDQ_A1==74
546 00:09:20.002642 VrefDac_Margin_A0==25
547 00:09:20.007583 DeviceVref_Margin_A0==40
548 00:09:20.008036 VrefDac_Margin_A1==24
549 00:09:20.012981 DeviceVref_Margin_A1==40
550 00:09:20.013409
551 00:09:20.013819
552 00:09:20.014221 channel==1
553 00:09:20.014625 RxClkDly_Margin_A0==88 ps 9
554 00:09:20.018479 TxDqDly_Margin_A0==98 ps 10
555 00:09:20.018910 RxClkDly_Margin_A1==88 ps 9
556 00:09:20.024064 TxDqDly_Margin_A1==88 ps 9
557 00:09:20.024509 TrainedVREFDQ_A0==77
558 00:09:20.024923 TrainedVREFDQ_A1==77
559 00:09:20.029712 VrefDac_Margin_A0==23
560 00:09:20.030140 DeviceVref_Margin_A0==37
561 00:09:20.035304 VrefDac_Margin_A1==24
562 00:09:20.035750 DeviceVref_Margin_A1==37
563 00:09:20.036189
564 00:09:20.040901 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
565 00:09:20.041337
566 00:09:20.068822 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
567 00:09:20.074471 2D training succeed
568 00:09:20.080044 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
569 00:09:20.080513 auto size-- 65535DDR cs0 size: 2048MB
570 00:09:20.085539 DDR cs1 size: 2048MB
571 00:09:20.085976 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
572 00:09:20.091178 cs0 DataBus test pass
573 00:09:20.091605 cs1 DataBus test pass
574 00:09:20.092041 cs0 AddrBus test pass
575 00:09:20.096752 cs1 AddrBus test pass
576 00:09:20.097181
577 00:09:20.097589 100bdlr_step_size ps== 420
578 00:09:20.097996 result report
579 00:09:20.102350 boot times 0Enable ddr reg access
580 00:09:20.109815 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
581 00:09:20.123301 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
582 00:09:20.697097 0.0;M3 CHK:0;cm4_sp_mode 0
583 00:09:20.697533 MVN_1=0x00000000
584 00:09:20.702799 MVN_2=0x00000000
585 00:09:20.708487 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
586 00:09:20.708836 OPS=0x10
587 00:09:20.709066 ring efuse init
588 00:09:20.709284 chipver efuse init
589 00:09:20.714004 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
590 00:09:20.719474 [0.018961 Inits done]
591 00:09:20.719815 secure task start!
592 00:09:20.720123 high task start!
593 00:09:20.724085 low task start!
594 00:09:20.724426 run into bl31
595 00:09:20.730622 NOTICE: BL31: v1.3(release):4fc40b1
596 00:09:20.738551 NOTICE: BL31: Built : 15:58:17, May 22 2019
597 00:09:20.739103 NOTICE: BL31: G12A normal boot!
598 00:09:20.763829 NOTICE: BL31: BL33 decompress pass
599 00:09:20.769482 ERROR: Error initializing runtime service opteed_fast
600 00:09:22.002491
601 00:09:22.003173
602 00:09:22.010865 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
603 00:09:22.011414
604 00:09:22.011884 Model: Libre Computer AML-A311D-CC Alta
605 00:09:22.219284 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
606 00:09:22.242663 DRAM: 2 GiB (effective 3.8 GiB)
607 00:09:22.385670 Core: 408 devices, 31 uclasses, devicetree: separate
608 00:09:22.391613 WDT: Not starting watchdog@f0d0
609 00:09:22.423789 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
610 00:09:22.436232 Loading Environment from FAT... Card did not respond to voltage select! : -110
611 00:09:22.441257 ** Bad device specification mmc 0 **
612 00:09:22.451568 Card did not respond to voltage select! : -110
613 00:09:22.459212 ** Bad device specification mmc 0 **
614 00:09:22.459767 Couldn't find partition mmc 0
615 00:09:22.467535 Card did not respond to voltage select! : -110
616 00:09:22.473040 ** Bad device specification mmc 0 **
617 00:09:22.473567 Couldn't find partition mmc 0
618 00:09:22.478114 Error: could not access storage.
619 00:09:22.820754 Net: eth0: ethernet@ff3f0000
620 00:09:22.821412 starting USB...
621 00:09:23.072615 Bus usb@ff500000: Register 3000140 NbrPorts 3
622 00:09:23.073291 Starting the controller
623 00:09:23.079484 USB XHCI 1.10
624 00:09:24.792026 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
625 00:09:24.792456 bl2_stage_init 0x01
626 00:09:24.792707 bl2_stage_init 0x81
627 00:09:24.797544 hw id: 0x0000 - pwm id 0x01
628 00:09:24.797868 bl2_stage_init 0xc1
629 00:09:24.798095 bl2_stage_init 0x02
630 00:09:24.798309
631 00:09:24.803164 L0:00000000
632 00:09:24.803486 L1:20000703
633 00:09:24.803716 L2:00008067
634 00:09:24.803932 L3:14000000
635 00:09:24.806024 B2:00402000
636 00:09:24.806320 B1:e0f83180
637 00:09:24.806551
638 00:09:24.806766 TE: 58124
639 00:09:24.807006
640 00:09:24.817231 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
641 00:09:24.817569
642 00:09:24.817819 Board ID = 1
643 00:09:24.818043 Set A53 clk to 24M
644 00:09:24.818255 Set A73 clk to 24M
645 00:09:24.822812 Set clk81 to 24M
646 00:09:24.823117 A53 clk: 1200 MHz
647 00:09:24.823339 A73 clk: 1200 MHz
648 00:09:24.828399 CLK81: 166.6M
649 00:09:24.828700 smccc: 00012a92
650 00:09:24.834017 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
651 00:09:24.834314 board id: 1
652 00:09:24.842417 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
653 00:09:24.853278 fw parse done
654 00:09:24.859230 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 00:09:24.901901 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
656 00:09:24.912791 PIEI prepare done
657 00:09:24.913257 fastboot data load
658 00:09:24.913521 fastboot data verify
659 00:09:24.918483 verify result: 266
660 00:09:24.924076 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
661 00:09:24.924400 LPDDR4 probe
662 00:09:24.924638 ddr clk to 1584MHz
663 00:09:24.932038 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 00:09:24.969300
665 00:09:24.969860 dmc_version 0001
666 00:09:24.975999 Check phy result
667 00:09:24.981857 INFO : End of CA training
668 00:09:24.982167 INFO : End of initialization
669 00:09:24.987436 INFO : Training has run successfully!
670 00:09:24.987888 Check phy result
671 00:09:24.993017 INFO : End of initialization
672 00:09:24.993326 INFO : End of read enable training
673 00:09:24.998648 INFO : End of fine write leveling
674 00:09:25.004247 INFO : End of Write leveling coarse delay
675 00:09:25.004555 INFO : Training has run successfully!
676 00:09:25.004780 Check phy result
677 00:09:25.009863 INFO : End of initialization
678 00:09:25.010312 INFO : End of read dq deskew training
679 00:09:25.015523 INFO : End of MPR read delay center optimization
680 00:09:25.021082 INFO : End of write delay center optimization
681 00:09:25.026607 INFO : End of read delay center optimization
682 00:09:25.026923 INFO : End of max read latency training
683 00:09:25.032229 INFO : Training has run successfully!
684 00:09:25.032680 1D training succeed
685 00:09:25.041403 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
686 00:09:25.089249 Check phy result
687 00:09:25.089659 INFO : End of initialization
688 00:09:25.111851 INFO : End of 2D read delay Voltage center optimization
689 00:09:25.132251 INFO : End of 2D read delay Voltage center optimization
690 00:09:25.184300 INFO : End of 2D write delay Voltage center optimization
691 00:09:25.233615 INFO : End of 2D write delay Voltage center optimization
692 00:09:25.239034 INFO : Training has run successfully!
693 00:09:25.239738
694 00:09:25.240384 channel==0
695 00:09:25.244520 RxClkDly_Margin_A0==88 ps 9
696 00:09:25.245187 TxDqDly_Margin_A0==98 ps 10
697 00:09:25.247763 RxClkDly_Margin_A1==88 ps 9
698 00:09:25.248403 TxDqDly_Margin_A1==98 ps 10
699 00:09:25.253348 TrainedVREFDQ_A0==74
700 00:09:25.254055 TrainedVREFDQ_A1==75
701 00:09:25.259158 VrefDac_Margin_A0==25
702 00:09:25.259851 DeviceVref_Margin_A0==40
703 00:09:25.260473 VrefDac_Margin_A1==24
704 00:09:25.264596 DeviceVref_Margin_A1==39
705 00:09:25.265269
706 00:09:25.265839
707 00:09:25.266390 channel==1
708 00:09:25.266918 RxClkDly_Margin_A0==98 ps 10
709 00:09:25.270205 TxDqDly_Margin_A0==98 ps 10
710 00:09:25.270854 RxClkDly_Margin_A1==88 ps 9
711 00:09:25.275707 TxDqDly_Margin_A1==88 ps 9
712 00:09:25.276498 TrainedVREFDQ_A0==77
713 00:09:25.277085 TrainedVREFDQ_A1==77
714 00:09:25.281395 VrefDac_Margin_A0==22
715 00:09:25.282050 DeviceVref_Margin_A0==37
716 00:09:25.286975 VrefDac_Margin_A1==24
717 00:09:25.287618 DeviceVref_Margin_A1==37
718 00:09:25.288205
719 00:09:25.292676 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
720 00:09:25.293336
721 00:09:25.320572 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
722 00:09:25.326141 2D training succeed
723 00:09:25.331758 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
724 00:09:25.332566 auto size-- 65535DDR cs0 size: 2048MB
725 00:09:25.337302 DDR cs1 size: 2048MB
726 00:09:25.337809 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
727 00:09:25.342961 cs0 DataBus test pass
728 00:09:25.343450 cs1 DataBus test pass
729 00:09:25.343898 cs0 AddrBus test pass
730 00:09:25.348483 cs1 AddrBus test pass
731 00:09:25.348984
732 00:09:25.349431 100bdlr_step_size ps== 426
733 00:09:25.349884 result report
734 00:09:25.354083 boot times 0Enable ddr reg access
735 00:09:25.361841 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
736 00:09:25.375321 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
737 00:09:25.948930 0.0;M3 CHK:0;cm4_sp_mode 0
738 00:09:25.949616 MVN_1=0x00000000
739 00:09:25.954375 MVN_2=0x00000000
740 00:09:25.960184 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
741 00:09:25.960794 OPS=0x10
742 00:09:25.961254 ring efuse init
743 00:09:25.961698 chipver efuse init
744 00:09:25.965739 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
745 00:09:25.971313 [0.018961 Inits done]
746 00:09:25.971801 secure task start!
747 00:09:25.972293 high task start!
748 00:09:25.975977 low task start!
749 00:09:25.976476 run into bl31
750 00:09:25.982550 NOTICE: BL31: v1.3(release):4fc40b1
751 00:09:25.990418 NOTICE: BL31: Built : 15:58:17, May 22 2019
752 00:09:25.990923 NOTICE: BL31: G12A normal boot!
753 00:09:26.015769 NOTICE: BL31: BL33 decompress pass
754 00:09:26.021397 ERROR: Error initializing runtime service opteed_fast
755 00:09:27.254271
756 00:09:27.254953
757 00:09:27.262686 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
758 00:09:27.263289
759 00:09:27.263762 Model: Libre Computer AML-A311D-CC Alta
760 00:09:27.471118 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
761 00:09:27.494444 DRAM: 2 GiB (effective 3.8 GiB)
762 00:09:27.637461 Core: 408 devices, 31 uclasses, devicetree: separate
763 00:09:27.643274 WDT: Not starting watchdog@f0d0
764 00:09:27.675599 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
765 00:09:27.688040 Loading Environment from FAT... Card did not respond to voltage select! : -110
766 00:09:27.693010 ** Bad device specification mmc 0 **
767 00:09:27.703315 Card did not respond to voltage select! : -110
768 00:09:27.711014 ** Bad device specification mmc 0 **
769 00:09:27.711358 Couldn't find partition mmc 0
770 00:09:27.719339 Card did not respond to voltage select! : -110
771 00:09:27.724807 ** Bad device specification mmc 0 **
772 00:09:27.725143 Couldn't find partition mmc 0
773 00:09:27.729952 Error: could not access storage.
774 00:09:28.073480 Net: eth0: ethernet@ff3f0000
775 00:09:28.073909 starting USB...
776 00:09:28.325339 Bus usb@ff500000: Register 3000140 NbrPorts 3
777 00:09:28.326013 Starting the controller
778 00:09:28.332340 USB XHCI 1.10
779 00:09:30.493635 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
780 00:09:30.494299 bl2_stage_init 0x01
781 00:09:30.494773 bl2_stage_init 0x81
782 00:09:30.499297 hw id: 0x0000 - pwm id 0x01
783 00:09:30.499848 bl2_stage_init 0xc1
784 00:09:30.500398 bl2_stage_init 0x02
785 00:09:30.500861
786 00:09:30.504805 L0:00000000
787 00:09:30.505336 L1:20000703
788 00:09:30.505793 L2:00008067
789 00:09:30.506241 L3:14000000
790 00:09:30.510627 B2:00402000
791 00:09:30.511165 B1:e0f83180
792 00:09:30.511622
793 00:09:30.512116 TE: 58167
794 00:09:30.512576
795 00:09:30.516110 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
796 00:09:30.516632
797 00:09:30.517092 Board ID = 1
798 00:09:30.521667 Set A53 clk to 24M
799 00:09:30.522188 Set A73 clk to 24M
800 00:09:30.522638 Set clk81 to 24M
801 00:09:30.527295 A53 clk: 1200 MHz
802 00:09:30.527813 A73 clk: 1200 MHz
803 00:09:30.528311 CLK81: 166.6M
804 00:09:30.528760 smccc: 00012abd
805 00:09:30.532804 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
806 00:09:30.538420 board id: 1
807 00:09:30.544359 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
808 00:09:30.554965 fw parse done
809 00:09:30.560595 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
810 00:09:30.603641 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
811 00:09:30.614479 PIEI prepare done
812 00:09:30.615040 fastboot data load
813 00:09:30.615517 fastboot data verify
814 00:09:30.620054 verify result: 266
815 00:09:30.625561 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
816 00:09:30.626090 LPDDR4 probe
817 00:09:30.626551 ddr clk to 1584MHz
818 00:09:30.633605 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 00:09:30.670929
820 00:09:30.671495 dmc_version 0001
821 00:09:30.677566 Check phy result
822 00:09:30.683383 INFO : End of CA training
823 00:09:30.683918 INFO : End of initialization
824 00:09:30.689053 INFO : Training has run successfully!
825 00:09:30.689571 Check phy result
826 00:09:30.694673 INFO : End of initialization
827 00:09:30.695193 INFO : End of read enable training
828 00:09:30.697950 INFO : End of fine write leveling
829 00:09:30.703527 INFO : End of Write leveling coarse delay
830 00:09:30.709133 INFO : Training has run successfully!
831 00:09:30.709662 Check phy result
832 00:09:30.710118 INFO : End of initialization
833 00:09:30.714850 INFO : End of read dq deskew training
834 00:09:30.720312 INFO : End of MPR read delay center optimization
835 00:09:30.720836 INFO : End of write delay center optimization
836 00:09:30.725879 INFO : End of read delay center optimization
837 00:09:30.731461 INFO : End of max read latency training
838 00:09:30.732012 INFO : Training has run successfully!
839 00:09:30.737056 1D training succeed
840 00:09:30.742393 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
841 00:09:30.790602 Check phy result
842 00:09:30.791170 INFO : End of initialization
843 00:09:30.812365 INFO : End of 2D read delay Voltage center optimization
844 00:09:30.832637 INFO : End of 2D read delay Voltage center optimization
845 00:09:30.884603 INFO : End of 2D write delay Voltage center optimization
846 00:09:30.934046 INFO : End of 2D write delay Voltage center optimization
847 00:09:30.939709 INFO : Training has run successfully!
848 00:09:30.940274
849 00:09:30.940737 channel==0
850 00:09:30.945279 RxClkDly_Margin_A0==88 ps 9
851 00:09:30.945796 TxDqDly_Margin_A0==98 ps 10
852 00:09:30.948541 RxClkDly_Margin_A1==88 ps 9
853 00:09:30.949055 TxDqDly_Margin_A1==98 ps 10
854 00:09:30.954058 TrainedVREFDQ_A0==74
855 00:09:30.954576 TrainedVREFDQ_A1==74
856 00:09:30.959741 VrefDac_Margin_A0==25
857 00:09:30.960314 DeviceVref_Margin_A0==40
858 00:09:30.960770 VrefDac_Margin_A1==25
859 00:09:30.965240 DeviceVref_Margin_A1==40
860 00:09:30.965772
861 00:09:30.966212
862 00:09:30.966645 channel==1
863 00:09:30.967076 RxClkDly_Margin_A0==98 ps 10
864 00:09:30.970975 TxDqDly_Margin_A0==98 ps 10
865 00:09:30.971487 RxClkDly_Margin_A1==98 ps 10
866 00:09:30.976479 TxDqDly_Margin_A1==88 ps 9
867 00:09:30.976991 TrainedVREFDQ_A0==77
868 00:09:30.977428 TrainedVREFDQ_A1==77
869 00:09:30.982032 VrefDac_Margin_A0==22
870 00:09:30.982539 DeviceVref_Margin_A0==37
871 00:09:30.987546 VrefDac_Margin_A1==22
872 00:09:30.988106 DeviceVref_Margin_A1==37
873 00:09:30.988542
874 00:09:30.993315 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
875 00:09:30.993827
876 00:09:31.021189 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
877 00:09:31.026894 2D training succeed
878 00:09:31.032462 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
879 00:09:31.032972 auto size-- 65535DDR cs0 size: 2048MB
880 00:09:31.037906 DDR cs1 size: 2048MB
881 00:09:31.038408 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
882 00:09:31.043608 cs0 DataBus test pass
883 00:09:31.044183 cs1 DataBus test pass
884 00:09:31.044616 cs0 AddrBus test pass
885 00:09:31.049335 cs1 AddrBus test pass
886 00:09:31.049871
887 00:09:31.050326 100bdlr_step_size ps== 420
888 00:09:31.050784 result report
889 00:09:31.054841 boot times 0Enable ddr reg access
890 00:09:31.062543 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
891 00:09:31.076023 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
892 00:09:31.649584 0.0;M3 CHK:0;cm4_sp_mode 0
893 00:09:31.650273 MVN_1=0x00000000
894 00:09:31.655123 MVN_2=0x00000000
895 00:09:31.660903 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
896 00:09:31.661456 OPS=0x10
897 00:09:31.661922 ring efuse init
898 00:09:31.662378 chipver efuse init
899 00:09:31.669020 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
900 00:09:31.669597 [0.018961 Inits done]
901 00:09:31.676726 secure task start!
902 00:09:31.677334 high task start!
903 00:09:31.677826 low task start!
904 00:09:31.678283 run into bl31
905 00:09:31.683366 NOTICE: BL31: v1.3(release):4fc40b1
906 00:09:31.691137 NOTICE: BL31: Built : 15:58:17, May 22 2019
907 00:09:31.691683 NOTICE: BL31: G12A normal boot!
908 00:09:31.716463 NOTICE: BL31: BL33 decompress pass
909 00:09:31.722183 ERROR: Error initializing runtime service opteed_fast
910 00:09:32.955091
911 00:09:32.955760
912 00:09:32.963435 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
913 00:09:32.964021
914 00:09:32.964491 Model: Libre Computer AML-A311D-CC Alta
915 00:09:33.171819 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
916 00:09:33.195198 DRAM: 2 GiB (effective 3.8 GiB)
917 00:09:33.338231 Core: 408 devices, 31 uclasses, devicetree: separate
918 00:09:33.344169 WDT: Not starting watchdog@f0d0
919 00:09:33.376376 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
920 00:09:33.388758 Loading Environment from FAT... Card did not respond to voltage select! : -110
921 00:09:33.393787 ** Bad device specification mmc 0 **
922 00:09:33.404135 Card did not respond to voltage select! : -110
923 00:09:33.411810 ** Bad device specification mmc 0 **
924 00:09:33.412467 Couldn't find partition mmc 0
925 00:09:33.420137 Card did not respond to voltage select! : -110
926 00:09:33.425558 ** Bad device specification mmc 0 **
927 00:09:33.426125 Couldn't find partition mmc 0
928 00:09:33.430679 Error: could not access storage.
929 00:09:33.774273 Net: eth0: ethernet@ff3f0000
930 00:09:33.774932 starting USB...
931 00:09:34.026015 Bus usb@ff500000: Register 3000140 NbrPorts 3
932 00:09:34.026645 Starting the controller
933 00:09:34.032964 USB XHCI 1.10
934 00:09:35.893393 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
935 00:09:35.893808 bl2_stage_init 0x01
936 00:09:35.894034 bl2_stage_init 0x81
937 00:09:35.898967 hw id: 0x0000 - pwm id 0x01
938 00:09:35.899360 bl2_stage_init 0xc1
939 00:09:35.899606 bl2_stage_init 0x02
940 00:09:35.899821
941 00:09:35.904564 L0:00000000
942 00:09:35.904889 L1:20000703
943 00:09:35.905108 L2:00008067
944 00:09:35.905314 L3:14000000
945 00:09:35.910344 B2:00402000
946 00:09:35.910625 B1:e0f83180
947 00:09:35.910841
948 00:09:35.911062 TE: 58167
949 00:09:35.911272
950 00:09:35.915785 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
951 00:09:35.916089
952 00:09:35.916322 Board ID = 1
953 00:09:35.921381 Set A53 clk to 24M
954 00:09:35.921663 Set A73 clk to 24M
955 00:09:35.921876 Set clk81 to 24M
956 00:09:35.926962 A53 clk: 1200 MHz
957 00:09:35.927242 A73 clk: 1200 MHz
958 00:09:35.927456 CLK81: 166.6M
959 00:09:35.927665 smccc: 00012abd
960 00:09:35.932579 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
961 00:09:35.938330 board id: 1
962 00:09:35.943128 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
963 00:09:35.954802 fw parse done
964 00:09:35.959780 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
965 00:09:36.003377 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
966 00:09:36.014288 PIEI prepare done
967 00:09:36.014598 fastboot data load
968 00:09:36.014828 fastboot data verify
969 00:09:36.019782 verify result: 266
970 00:09:36.025423 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
971 00:09:36.026007 LPDDR4 probe
972 00:09:36.026459 ddr clk to 1584MHz
973 00:09:36.033508 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
974 00:09:36.070893
975 00:09:36.071497 dmc_version 0001
976 00:09:36.077367 Check phy result
977 00:09:36.083584 INFO : End of CA training
978 00:09:36.084191 INFO : End of initialization
979 00:09:36.088977 INFO : Training has run successfully!
980 00:09:36.089475 Check phy result
981 00:09:36.094586 INFO : End of initialization
982 00:09:36.095167 INFO : End of read enable training
983 00:09:36.100123 INFO : End of fine write leveling
984 00:09:36.105885 INFO : End of Write leveling coarse delay
985 00:09:36.106454 INFO : Training has run successfully!
986 00:09:36.106948 Check phy result
987 00:09:36.111408 INFO : End of initialization
988 00:09:36.112051 INFO : End of read dq deskew training
989 00:09:36.116838 INFO : End of MPR read delay center optimization
990 00:09:36.123556 INFO : End of write delay center optimization
991 00:09:36.128102 INFO : End of read delay center optimization
992 00:09:36.128672 INFO : End of max read latency training
993 00:09:36.133673 INFO : Training has run successfully!
994 00:09:36.134222 1D training succeed
995 00:09:36.142928 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
996 00:09:36.190574 Check phy result
997 00:09:36.190960 INFO : End of initialization
998 00:09:36.212308 INFO : End of 2D read delay Voltage center optimization
999 00:09:36.232619 INFO : End of 2D read delay Voltage center optimization
1000 00:09:36.284641 INFO : End of 2D write delay Voltage center optimization
1001 00:09:36.333912 INFO : End of 2D write delay Voltage center optimization
1002 00:09:36.339527 INFO : Training has run successfully!
1003 00:09:36.339872
1004 00:09:36.340161 channel==0
1005 00:09:36.345218 RxClkDly_Margin_A0==88 ps 9
1006 00:09:36.345706 TxDqDly_Margin_A0==108 ps 11
1007 00:09:36.348625 RxClkDly_Margin_A1==88 ps 9
1008 00:09:36.348989 TxDqDly_Margin_A1==98 ps 10
1009 00:09:36.354161 TrainedVREFDQ_A0==74
1010 00:09:36.354695 TrainedVREFDQ_A1==75
1011 00:09:36.355111 VrefDac_Margin_A0==25
1012 00:09:36.359778 DeviceVref_Margin_A0==40
1013 00:09:36.360338 VrefDac_Margin_A1==25
1014 00:09:36.365257 DeviceVref_Margin_A1==39
1015 00:09:36.365729
1016 00:09:36.366135
1017 00:09:36.366528 channel==1
1018 00:09:36.366922 RxClkDly_Margin_A0==98 ps 10
1019 00:09:36.368756 TxDqDly_Margin_A0==88 ps 9
1020 00:09:36.374262 RxClkDly_Margin_A1==88 ps 9
1021 00:09:36.374720 TxDqDly_Margin_A1==88 ps 9
1022 00:09:36.375128 TrainedVREFDQ_A0==76
1023 00:09:36.379969 TrainedVREFDQ_A1==77
1024 00:09:36.380446 VrefDac_Margin_A0==22
1025 00:09:36.385539 DeviceVref_Margin_A0==38
1026 00:09:36.385984 VrefDac_Margin_A1==24
1027 00:09:36.386384 DeviceVref_Margin_A1==37
1028 00:09:36.386774
1029 00:09:36.394555 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1030 00:09:36.394997
1031 00:09:36.420256 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000019 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1032 00:09:36.425953 2D training succeed
1033 00:09:36.431536 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1034 00:09:36.432002 auto size-- 65535DDR cs0 size: 2048MB
1035 00:09:36.437037 DDR cs1 size: 2048MB
1036 00:09:36.437481 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1037 00:09:36.442646 cs0 DataBus test pass
1038 00:09:36.443085 cs1 DataBus test pass
1039 00:09:36.448225 cs0 AddrBus test pass
1040 00:09:36.448660 cs1 AddrBus test pass
1041 00:09:36.449056
1042 00:09:36.449453 100bdlr_step_size ps== 420
1043 00:09:36.453819 result report
1044 00:09:36.454257 boot times 0Enable ddr reg access
1045 00:09:36.462351 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1046 00:09:36.475749 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1047 00:09:37.049538 0.0;M3 CHK:0;cm4_sp_mode 0
1048 00:09:37.049968 MVN_1=0x00000000
1049 00:09:37.054982 MVN_2=0x00000000
1050 00:09:37.060752 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1051 00:09:37.061104 OPS=0x10
1052 00:09:37.061347 ring efuse init
1053 00:09:37.061568 chipver efuse init
1054 00:09:37.069038 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1055 00:09:37.069380 [0.018961 Inits done]
1056 00:09:37.069628 secure task start!
1057 00:09:37.076515 high task start!
1058 00:09:37.076816 low task start!
1059 00:09:37.077052 run into bl31
1060 00:09:37.083060 NOTICE: BL31: v1.3(release):4fc40b1
1061 00:09:37.090936 NOTICE: BL31: Built : 15:58:17, May 22 2019
1062 00:09:37.091311 NOTICE: BL31: G12A normal boot!
1063 00:09:37.116325 NOTICE: BL31: BL33 decompress pass
1064 00:09:37.121924 ERROR: Error initializing runtime service opteed_fast
1065 00:09:38.354961
1066 00:09:38.355638
1067 00:09:38.363285 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1068 00:09:38.363844
1069 00:09:38.364364 Model: Libre Computer AML-A311D-CC Alta
1070 00:09:38.571639 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1071 00:09:38.594176 DRAM: 2 GiB (effective 3.8 GiB)
1072 00:09:38.737989 Core: 408 devices, 31 uclasses, devicetree: separate
1073 00:09:38.743799 WDT: Not starting watchdog@f0d0
1074 00:09:38.776086 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1075 00:09:38.788656 Loading Environment from FAT... Card did not respond to voltage select! : -110
1076 00:09:38.793101 ** Bad device specification mmc 0 **
1077 00:09:38.803838 Card did not respond to voltage select! : -110
1078 00:09:38.811487 ** Bad device specification mmc 0 **
1079 00:09:38.811941 Couldn't find partition mmc 0
1080 00:09:38.819844 Card did not respond to voltage select! : -110
1081 00:09:38.825413 ** Bad device specification mmc 0 **
1082 00:09:38.825852 Couldn't find partition mmc 0
1083 00:09:38.830394 Error: could not access storage.
1084 00:09:39.172884 Net: eth0: ethernet@ff3f0000
1085 00:09:39.173299 starting USB...
1086 00:09:39.424718 Bus usb@ff500000: Register 3000140 NbrPorts 3
1087 00:09:39.425338 Starting the controller
1088 00:09:39.431654 USB XHCI 1.10
1089 00:09:40.985728 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1090 00:09:40.994182 scanning usb for storage devices... 0 Storage Device(s) found
1092 00:09:41.045427 Hit any key to stop autoboot: 1
1093 00:09:41.046298 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1094 00:09:41.046684 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1095 00:09:41.046973 Setting prompt string to ['=>']
1096 00:09:41.047252 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1097 00:09:41.051564 0
1098 00:09:41.052280 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1099 00:09:41.052599 Sending with 10 millisecond of delay
1101 00:09:42.187873 => setenv autoload no
1102 00:09:42.198535 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1103 00:09:42.201303 setenv autoload no
1104 00:09:42.201849 Sending with 10 millisecond of delay
1106 00:09:43.998593 => setenv initrd_high 0xffffffff
1107 00:09:44.009401 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1108 00:09:44.010305 setenv initrd_high 0xffffffff
1109 00:09:44.011012 Sending with 10 millisecond of delay
1111 00:09:45.628141 => setenv fdt_high 0xffffffff
1112 00:09:45.639108 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1113 00:09:45.640242 setenv fdt_high 0xffffffff
1114 00:09:45.641136 Sending with 10 millisecond of delay
1116 00:09:45.933370 => dhcp
1117 00:09:45.944103 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1118 00:09:45.944686 dhcp
1119 00:09:45.944933 Speed: 1000, full duplex
1120 00:09:45.945149 BOOTP broadcast 1
1121 00:09:45.953765 DHCP client bound to address 192.168.6.27 (10 ms)
1122 00:09:45.954287 Sending with 10 millisecond of delay
1124 00:09:47.631214 => setenv serverip 192.168.6.2
1125 00:09:47.641798 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1126 00:09:47.642384 setenv serverip 192.168.6.2
1127 00:09:47.642847 Sending with 10 millisecond of delay
1129 00:09:51.365142 => tftpboot 0x01080000 949360/tftp-deploy-zkbe9cn4/kernel/uImage
1130 00:09:51.375738 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1131 00:09:51.376303 tftpboot 0x01080000 949360/tftp-deploy-zkbe9cn4/kernel/uImage
1132 00:09:51.376543 Speed: 1000, full duplex
1133 00:09:51.376753 Using ethernet@ff3f0000 device
1134 00:09:51.378342 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1135 00:09:51.383859 Filename '949360/tftp-deploy-zkbe9cn4/kernel/uImage'.
1136 00:09:51.387755 Load address: 0x1080000
1137 00:09:52.837367 Loading: *############################## UDP wrong checksum 000000ff 0000534e
1138 00:09:52.877334 # UDP wrong checksum 000000ff 0000ee40
1139 00:09:53.723502 ################### 36.1 MiB
1140 00:09:53.724215 15.5 MiB/s
1141 00:09:53.724708 done
1142 00:09:53.727843 Bytes transferred = 37880384 (2420240 hex)
1143 00:09:53.728729 Sending with 10 millisecond of delay
1145 00:09:58.415533 => tftpboot 0x08000000 949360/tftp-deploy-zkbe9cn4/ramdisk/ramdisk.cpio.gz.uboot
1146 00:09:58.426419 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1147 00:09:58.427333 tftpboot 0x08000000 949360/tftp-deploy-zkbe9cn4/ramdisk/ramdisk.cpio.gz.uboot
1148 00:09:58.427805 Speed: 1000, full duplex
1149 00:09:58.428289 Using ethernet@ff3f0000 device
1150 00:09:58.429282 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1151 00:09:58.441160 Filename '949360/tftp-deploy-zkbe9cn4/ramdisk/ramdisk.cpio.gz.uboot'.
1152 00:09:58.441689 Load address: 0x8000000
1153 00:10:04.948930 Loading: *T ################################################# UDP wrong checksum 00000005 0000e901
1154 00:10:09.949545 T UDP wrong checksum 00000005 0000e901
1155 00:10:19.952010 T T UDP wrong checksum 00000005 0000e901
1156 00:10:29.568661 T UDP wrong checksum 000000ff 0000dffc
1157 00:10:29.579655 UDP wrong checksum 000000ff 000073ef
1158 00:10:35.440923 T T UDP wrong checksum 000000ff 00005a1a
1159 00:10:35.450022 UDP wrong checksum 000000ff 0000ef0c
1160 00:10:39.958148 T UDP wrong checksum 00000005 0000e901
1161 00:10:42.014469 UDP wrong checksum 000000ff 00003153
1162 00:10:42.036493 UDP wrong checksum 000000ff 0000c845
1163 00:10:50.121455 T T UDP wrong checksum 000000ff 0000a085
1164 00:10:50.172705 UDP wrong checksum 000000ff 00002578
1165 00:10:54.960137
1166 00:10:54.960796 Retry count exceeded; starting again
1168 00:10:54.962383 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1171 00:10:54.964582 end: 2.4 uboot-commands (duration 00:01:51) [common]
1173 00:10:54.966144 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1175 00:10:54.967328 end: 2 uboot-action (duration 00:01:51) [common]
1177 00:10:54.969035 Cleaning after the job
1178 00:10:54.969633 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/ramdisk
1179 00:10:54.971267 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/kernel
1180 00:10:55.015748 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/dtb
1181 00:10:55.017544 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/nfsrootfs
1182 00:10:55.355584 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949360/tftp-deploy-zkbe9cn4/modules
1183 00:10:55.380156 start: 4.1 power-off (timeout 00:00:30) [common]
1184 00:10:55.380833 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1185 00:10:55.415360 >> OK - accepted request
1186 00:10:55.417555 Returned 0 in 0 seconds
1187 00:10:55.518382 end: 4.1 power-off (duration 00:00:00) [common]
1189 00:10:55.519352 start: 4.2 read-feedback (timeout 00:10:00) [common]
1190 00:10:55.520040 Listened to connection for namespace 'common' for up to 1s
1191 00:10:56.520945 Finalising connection for namespace 'common'
1192 00:10:56.521437 Disconnecting from shell: Finalise
1193 00:10:56.521731 =>
1194 00:10:56.622360 end: 4.2 read-feedback (duration 00:00:01) [common]
1195 00:10:56.622741 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949360
1196 00:10:59.104339 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949360
1197 00:10:59.104962 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.