Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:37:43.803315 lava-dispatcher, installed at version: 2024.01
2 01:37:43.804156 start: 0 validate
3 01:37:43.804646 Start time: 2024-11-07 01:37:43.804613+00:00 (UTC)
4 01:37:43.805191 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:37:43.805743 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:37:43.851659 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:37:43.852236 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 01:37:43.880157 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:37:43.880799 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:37:43.911706 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:37:43.912297 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:37:43.943880 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:37:43.944408 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
14 01:37:43.982634 validate duration: 0.18
16 01:37:43.983521 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:37:43.983874 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:37:43.984239 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:37:43.984839 Not decompressing ramdisk as can be used compressed.
20 01:37:43.985303 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 01:37:43.985595 saving as /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/ramdisk/initrd.cpio.gz
22 01:37:43.985879 total size: 5628140 (5 MB)
23 01:37:44.017720 progress 0 % (0 MB)
24 01:37:44.024941 progress 5 % (0 MB)
25 01:37:44.032783 progress 10 % (0 MB)
26 01:37:44.039734 progress 15 % (0 MB)
27 01:37:44.044011 progress 20 % (1 MB)
28 01:37:44.047657 progress 25 % (1 MB)
29 01:37:44.051765 progress 30 % (1 MB)
30 01:37:44.055779 progress 35 % (1 MB)
31 01:37:44.059391 progress 40 % (2 MB)
32 01:37:44.063423 progress 45 % (2 MB)
33 01:37:44.067004 progress 50 % (2 MB)
34 01:37:44.070975 progress 55 % (2 MB)
35 01:37:44.074948 progress 60 % (3 MB)
36 01:37:44.078522 progress 65 % (3 MB)
37 01:37:44.082470 progress 70 % (3 MB)
38 01:37:44.086123 progress 75 % (4 MB)
39 01:37:44.090125 progress 80 % (4 MB)
40 01:37:44.093779 progress 85 % (4 MB)
41 01:37:44.097710 progress 90 % (4 MB)
42 01:37:44.101496 progress 95 % (5 MB)
43 01:37:44.104755 progress 100 % (5 MB)
44 01:37:44.105415 5 MB downloaded in 0.12 s (44.91 MB/s)
45 01:37:44.105988 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:37:44.106909 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:37:44.107228 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:37:44.107518 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:37:44.108022 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/kernel/Image
51 01:37:44.108286 saving as /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/kernel/Image
52 01:37:44.108513 total size: 37880320 (36 MB)
53 01:37:44.108740 No compression specified
54 01:37:44.146897 progress 0 % (0 MB)
55 01:37:44.170563 progress 5 % (1 MB)
56 01:37:44.194727 progress 10 % (3 MB)
57 01:37:44.218562 progress 15 % (5 MB)
58 01:37:44.242529 progress 20 % (7 MB)
59 01:37:44.266674 progress 25 % (9 MB)
60 01:37:44.290012 progress 30 % (10 MB)
61 01:37:44.313769 progress 35 % (12 MB)
62 01:37:44.337769 progress 40 % (14 MB)
63 01:37:44.361415 progress 45 % (16 MB)
64 01:37:44.385283 progress 50 % (18 MB)
65 01:37:44.409828 progress 55 % (19 MB)
66 01:37:44.434193 progress 60 % (21 MB)
67 01:37:44.457938 progress 65 % (23 MB)
68 01:37:44.482079 progress 70 % (25 MB)
69 01:37:44.506014 progress 75 % (27 MB)
70 01:37:44.529703 progress 80 % (28 MB)
71 01:37:44.554225 progress 85 % (30 MB)
72 01:37:44.578368 progress 90 % (32 MB)
73 01:37:44.602577 progress 95 % (34 MB)
74 01:37:44.626395 progress 100 % (36 MB)
75 01:37:44.626908 36 MB downloaded in 0.52 s (69.69 MB/s)
76 01:37:44.627402 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:37:44.628280 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:37:44.628581 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:37:44.628864 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:37:44.629327 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:37:44.629609 saving as /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:37:44.629827 total size: 54703 (0 MB)
84 01:37:44.630047 No compression specified
85 01:37:44.662550 progress 59 % (0 MB)
86 01:37:44.663399 progress 100 % (0 MB)
87 01:37:44.663963 0 MB downloaded in 0.03 s (1.53 MB/s)
88 01:37:44.664490 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:37:44.665339 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:37:44.665621 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:37:44.665902 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:37:44.666367 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 01:37:44.666620 saving as /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/nfsrootfs/full.rootfs.tar
95 01:37:44.666837 total size: 474398908 (452 MB)
96 01:37:44.667057 Using unxz to decompress xz
97 01:37:44.702304 progress 0 % (0 MB)
98 01:37:45.869505 progress 5 % (22 MB)
99 01:37:47.304146 progress 10 % (45 MB)
100 01:37:47.731535 progress 15 % (67 MB)
101 01:37:48.539185 progress 20 % (90 MB)
102 01:37:49.068835 progress 25 % (113 MB)
103 01:37:49.414873 progress 30 % (135 MB)
104 01:37:50.022009 progress 35 % (158 MB)
105 01:37:50.890565 progress 40 % (181 MB)
106 01:37:51.630291 progress 45 % (203 MB)
107 01:37:52.207225 progress 50 % (226 MB)
108 01:37:52.853832 progress 55 % (248 MB)
109 01:37:54.064350 progress 60 % (271 MB)
110 01:37:55.471168 progress 65 % (294 MB)
111 01:37:57.065126 progress 70 % (316 MB)
112 01:38:00.179895 progress 75 % (339 MB)
113 01:38:02.637348 progress 80 % (361 MB)
114 01:38:05.570597 progress 85 % (384 MB)
115 01:38:08.777103 progress 90 % (407 MB)
116 01:38:11.973686 progress 95 % (429 MB)
117 01:38:15.208514 progress 100 % (452 MB)
118 01:38:15.221730 452 MB downloaded in 30.55 s (14.81 MB/s)
119 01:38:15.222452 end: 1.4.1 http-download (duration 00:00:31) [common]
121 01:38:15.223456 end: 1.4 download-retry (duration 00:00:31) [common]
122 01:38:15.223784 start: 1.5 download-retry (timeout 00:09:29) [common]
123 01:38:15.224336 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 01:38:15.225516 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/clang-16/modules.tar.xz
125 01:38:15.226137 saving as /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/modules/modules.tar
126 01:38:15.226658 total size: 11768476 (11 MB)
127 01:38:15.227197 Using unxz to decompress xz
128 01:38:15.276524 progress 0 % (0 MB)
129 01:38:15.344353 progress 5 % (0 MB)
130 01:38:15.420972 progress 10 % (1 MB)
131 01:38:15.517593 progress 15 % (1 MB)
132 01:38:15.615310 progress 20 % (2 MB)
133 01:38:15.696515 progress 25 % (2 MB)
134 01:38:15.775271 progress 30 % (3 MB)
135 01:38:15.855828 progress 35 % (3 MB)
136 01:38:15.936610 progress 40 % (4 MB)
137 01:38:16.013644 progress 45 % (5 MB)
138 01:38:16.100295 progress 50 % (5 MB)
139 01:38:16.182652 progress 55 % (6 MB)
140 01:38:16.268787 progress 60 % (6 MB)
141 01:38:16.351059 progress 65 % (7 MB)
142 01:38:16.434133 progress 70 % (7 MB)
143 01:38:16.519072 progress 75 % (8 MB)
144 01:38:16.604074 progress 80 % (9 MB)
145 01:38:16.685791 progress 85 % (9 MB)
146 01:38:16.769978 progress 90 % (10 MB)
147 01:38:16.849698 progress 95 % (10 MB)
148 01:38:16.927935 progress 100 % (11 MB)
149 01:38:16.938548 11 MB downloaded in 1.71 s (6.56 MB/s)
150 01:38:16.939109 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:38:16.939934 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:38:16.940542 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 01:38:16.941135 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 01:38:33.161694 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/949440/extract-nfsrootfs-zp0xzfqc
156 01:38:33.162432 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 01:38:33.162791 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 01:38:33.163523 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02
159 01:38:33.164094 makedir: /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin
160 01:38:33.164511 makedir: /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/tests
161 01:38:33.164898 makedir: /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/results
162 01:38:33.165310 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-add-keys
163 01:38:33.165961 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-add-sources
164 01:38:33.166597 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-background-process-start
165 01:38:33.167263 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-background-process-stop
166 01:38:33.167944 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-common-functions
167 01:38:33.168614 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-echo-ipv4
168 01:38:33.169222 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-install-packages
169 01:38:33.169841 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-installed-packages
170 01:38:33.170437 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-os-build
171 01:38:33.171034 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-probe-channel
172 01:38:33.171645 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-probe-ip
173 01:38:33.172271 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-target-ip
174 01:38:33.172885 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-target-mac
175 01:38:33.173484 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-target-storage
176 01:38:33.174139 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-test-case
177 01:38:33.174758 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-test-event
178 01:38:33.175388 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-test-feedback
179 01:38:33.176013 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-test-raise
180 01:38:33.176670 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-test-reference
181 01:38:33.177274 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-test-runner
182 01:38:33.177890 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-test-set
183 01:38:33.178485 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-test-shell
184 01:38:33.179106 Updating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-install-packages (oe)
185 01:38:33.179783 Updating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/bin/lava-installed-packages (oe)
186 01:38:33.180408 Creating /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/environment
187 01:38:33.180927 LAVA metadata
188 01:38:33.181256 - LAVA_JOB_ID=949440
189 01:38:33.181520 - LAVA_DISPATCHER_IP=192.168.6.2
190 01:38:33.181984 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 01:38:33.183179 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 01:38:33.183571 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 01:38:33.183825 skipped lava-vland-overlay
194 01:38:33.184153 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 01:38:33.184471 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 01:38:33.184738 skipped lava-multinode-overlay
197 01:38:33.185034 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 01:38:33.185345 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 01:38:33.185650 Loading test definitions
200 01:38:33.185993 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 01:38:33.186269 Using /lava-949440 at stage 0
202 01:38:33.187778 uuid=949440_1.6.2.4.1 testdef=None
203 01:38:33.188213 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 01:38:33.188535 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 01:38:33.192401 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 01:38:33.193478 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 01:38:33.196433 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 01:38:33.197512 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 01:38:33.200190 runner path: /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 949440_1.6.2.4.1
212 01:38:33.201005 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 01:38:33.201947 Creating lava-test-runner.conf files
215 01:38:33.202195 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949440/lava-overlay-7lc7pb02/lava-949440/0 for stage 0
216 01:38:33.202644 - 0_v4l2-decoder-conformance-vp9
217 01:38:33.203090 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 01:38:33.203432 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 01:38:33.230761 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 01:38:33.231312 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 01:38:33.231636 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 01:38:33.231971 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 01:38:33.232326 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 01:38:33.915153 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 01:38:33.915622 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 01:38:33.915872 extracting modules file /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949440/extract-nfsrootfs-zp0xzfqc
227 01:38:35.465691 extracting modules file /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949440/extract-overlay-ramdisk-lqwne9fb/ramdisk
228 01:38:37.250562 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 01:38:37.251158 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 01:38:37.251506 [common] Applying overlay to NFS
231 01:38:37.251769 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949440/compress-overlay-c3ff914v/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949440/extract-nfsrootfs-zp0xzfqc
232 01:38:37.288338 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 01:38:37.288895 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 01:38:37.289231 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 01:38:37.289518 Converting downloaded kernel to a uImage
236 01:38:37.289907 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/kernel/Image /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/kernel/uImage
237 01:38:37.678734 output: Image Name:
238 01:38:37.679156 output: Created: Thu Nov 7 01:38:37 2024
239 01:38:37.679369 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 01:38:37.679575 output: Data Size: 37880320 Bytes = 36992.50 KiB = 36.13 MiB
241 01:38:37.679776 output: Load Address: 01080000
242 01:38:37.679975 output: Entry Point: 01080000
243 01:38:37.680213 output:
244 01:38:37.680553 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 01:38:37.680823 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 01:38:37.681096 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 01:38:37.681351 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 01:38:37.681609 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 01:38:37.681877 Building ramdisk /var/lib/lava/dispatcher/tmp/949440/extract-overlay-ramdisk-lqwne9fb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949440/extract-overlay-ramdisk-lqwne9fb/ramdisk
250 01:38:40.410110 >> 173443 blocks
251 01:38:48.099730 Adding RAMdisk u-boot header.
252 01:38:48.100266 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949440/extract-overlay-ramdisk-lqwne9fb/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949440/extract-overlay-ramdisk-lqwne9fb/ramdisk.cpio.gz.uboot
253 01:38:48.351682 output: Image Name:
254 01:38:48.352295 output: Created: Thu Nov 7 01:38:48 2024
255 01:38:48.352807 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 01:38:48.353232 output: Data Size: 24149891 Bytes = 23583.88 KiB = 23.03 MiB
257 01:38:48.353644 output: Load Address: 00000000
258 01:38:48.354049 output: Entry Point: 00000000
259 01:38:48.354447 output:
260 01:38:48.355490 rename /var/lib/lava/dispatcher/tmp/949440/extract-overlay-ramdisk-lqwne9fb/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/ramdisk/ramdisk.cpio.gz.uboot
261 01:38:48.356323 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 01:38:48.356912 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
263 01:38:48.357503 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 01:38:48.357983 No LXC device requested
265 01:38:48.358512 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 01:38:48.359043 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 01:38:48.359560 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 01:38:48.360009 Checking files for TFTP limit of 4294967296 bytes.
269 01:38:48.362721 end: 1 tftp-deploy (duration 00:01:04) [common]
270 01:38:48.363350 start: 2 uboot-action (timeout 00:05:00) [common]
271 01:38:48.363908 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 01:38:48.364495 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 01:38:48.365044 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 01:38:48.365609 Using kernel file from prepare-kernel: 949440/tftp-deploy-5a4t3n63/kernel/uImage
275 01:38:48.366277 substitutions:
276 01:38:48.366705 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 01:38:48.367124 - {DTB_ADDR}: 0x01070000
278 01:38:48.367541 - {DTB}: 949440/tftp-deploy-5a4t3n63/dtb/meson-g12b-a311d-libretech-cc.dtb
279 01:38:48.367950 - {INITRD}: 949440/tftp-deploy-5a4t3n63/ramdisk/ramdisk.cpio.gz.uboot
280 01:38:48.368403 - {KERNEL_ADDR}: 0x01080000
281 01:38:48.368813 - {KERNEL}: 949440/tftp-deploy-5a4t3n63/kernel/uImage
282 01:38:48.369220 - {LAVA_MAC}: None
283 01:38:48.369672 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/949440/extract-nfsrootfs-zp0xzfqc
284 01:38:48.370092 - {NFS_SERVER_IP}: 192.168.6.2
285 01:38:48.370494 - {PRESEED_CONFIG}: None
286 01:38:48.370898 - {PRESEED_LOCAL}: None
287 01:38:48.371300 - {RAMDISK_ADDR}: 0x08000000
288 01:38:48.371694 - {RAMDISK}: 949440/tftp-deploy-5a4t3n63/ramdisk/ramdisk.cpio.gz.uboot
289 01:38:48.372131 - {ROOT_PART}: None
290 01:38:48.372552 - {ROOT}: None
291 01:38:48.372955 - {SERVER_IP}: 192.168.6.2
292 01:38:48.373365 - {TEE_ADDR}: 0x83000000
293 01:38:48.373767 - {TEE}: None
294 01:38:48.374168 Parsed boot commands:
295 01:38:48.374558 - setenv autoload no
296 01:38:48.374953 - setenv initrd_high 0xffffffff
297 01:38:48.375347 - setenv fdt_high 0xffffffff
298 01:38:48.375739 - dhcp
299 01:38:48.376165 - setenv serverip 192.168.6.2
300 01:38:48.376567 - tftpboot 0x01080000 949440/tftp-deploy-5a4t3n63/kernel/uImage
301 01:38:48.376975 - tftpboot 0x08000000 949440/tftp-deploy-5a4t3n63/ramdisk/ramdisk.cpio.gz.uboot
302 01:38:48.377374 - tftpboot 0x01070000 949440/tftp-deploy-5a4t3n63/dtb/meson-g12b-a311d-libretech-cc.dtb
303 01:38:48.377769 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/949440/extract-nfsrootfs-zp0xzfqc,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 01:38:48.378179 - bootm 0x01080000 0x08000000 0x01070000
305 01:38:48.378715 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 01:38:48.380295 start: 2.3 connect-device (timeout 00:05:00) [common]
308 01:38:48.380761 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 01:38:48.395845 Setting prompt string to ['lava-test: # ']
310 01:38:48.397416 end: 2.3 connect-device (duration 00:00:00) [common]
311 01:38:48.398056 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 01:38:48.398646 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 01:38:48.399217 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 01:38:48.400400 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 01:38:48.436786 >> OK - accepted request
316 01:38:48.438922 Returned 0 in 0 seconds
317 01:38:48.540111 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 01:38:48.541842 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 01:38:48.542439 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 01:38:48.542988 Setting prompt string to ['Hit any key to stop autoboot']
322 01:38:48.543482 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 01:38:48.545125 Trying 192.168.56.21...
324 01:38:48.545655 Connected to conserv1.
325 01:38:48.546095 Escape character is '^]'.
326 01:38:48.546521
327 01:38:48.546960 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 01:38:48.547402
329 01:39:00.069598 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 01:39:00.070159 bl2_stage_init 0x01
331 01:39:00.070408 bl2_stage_init 0x81
332 01:39:00.075094 hw id: 0x0000 - pwm id 0x01
333 01:39:00.075420 bl2_stage_init 0xc1
334 01:39:00.075624 bl2_stage_init 0x02
335 01:39:00.075824
336 01:39:00.080592 L0:00000000
337 01:39:00.080912 L1:20000703
338 01:39:00.081133 L2:00008067
339 01:39:00.081333 L3:14000000
340 01:39:00.086211 B2:00402000
341 01:39:00.086512 B1:e0f83180
342 01:39:00.086713
343 01:39:00.086914 TE: 58124
344 01:39:00.087112
345 01:39:00.091861 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 01:39:00.092199
347 01:39:00.092403 Board ID = 1
348 01:39:00.097425 Set A53 clk to 24M
349 01:39:00.097732 Set A73 clk to 24M
350 01:39:00.097935 Set clk81 to 24M
351 01:39:00.102976 A53 clk: 1200 MHz
352 01:39:00.103268 A73 clk: 1200 MHz
353 01:39:00.103467 CLK81: 166.6M
354 01:39:00.103664 smccc: 00012a92
355 01:39:00.108616 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 01:39:00.114254 board id: 1
357 01:39:00.120148 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 01:39:00.130923 fw parse done
359 01:39:00.136801 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 01:39:00.179487 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 01:39:00.190099 PIEI prepare done
362 01:39:00.190444 fastboot data load
363 01:39:00.190653 fastboot data verify
364 01:39:00.195860 verify result: 266
365 01:39:00.201279 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 01:39:00.201745 LPDDR4 probe
367 01:39:00.202143 ddr clk to 1584MHz
368 01:39:00.209323 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 01:39:00.246211
370 01:39:00.246826 dmc_version 0001
371 01:39:00.253456 Check phy result
372 01:39:00.259326 INFO : End of CA training
373 01:39:00.259916 INFO : End of initialization
374 01:39:00.264932 INFO : Training has run successfully!
375 01:39:00.265507 Check phy result
376 01:39:00.270576 INFO : End of initialization
377 01:39:00.271267 INFO : End of read enable training
378 01:39:00.276090 INFO : End of fine write leveling
379 01:39:00.281649 INFO : End of Write leveling coarse delay
380 01:39:00.282194 INFO : Training has run successfully!
381 01:39:00.282642 Check phy result
382 01:39:00.287208 INFO : End of initialization
383 01:39:00.287705 INFO : End of read dq deskew training
384 01:39:00.293034 INFO : End of MPR read delay center optimization
385 01:39:00.298771 INFO : End of write delay center optimization
386 01:39:00.304035 INFO : End of read delay center optimization
387 01:39:00.304519 INFO : End of max read latency training
388 01:39:00.309545 INFO : Training has run successfully!
389 01:39:00.310038 1D training succeed
390 01:39:00.318748 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 01:39:00.366490 Check phy result
392 01:39:00.367122 INFO : End of initialization
393 01:39:00.388733 INFO : End of 2D read delay Voltage center optimization
394 01:39:00.409260 INFO : End of 2D read delay Voltage center optimization
395 01:39:00.459903 INFO : End of 2D write delay Voltage center optimization
396 01:39:00.510074 INFO : End of 2D write delay Voltage center optimization
397 01:39:00.515578 INFO : Training has run successfully!
398 01:39:00.516103
399 01:39:00.516561 channel==0
400 01:39:00.521131 RxClkDly_Margin_A0==88 ps 9
401 01:39:00.521603 TxDqDly_Margin_A0==98 ps 10
402 01:39:00.526823 RxClkDly_Margin_A1==88 ps 9
403 01:39:00.527296 TxDqDly_Margin_A1==88 ps 9
404 01:39:00.527739 TrainedVREFDQ_A0==74
405 01:39:00.532344 TrainedVREFDQ_A1==74
406 01:39:00.532821 VrefDac_Margin_A0==24
407 01:39:00.533259 DeviceVref_Margin_A0==40
408 01:39:00.537904 VrefDac_Margin_A1==24
409 01:39:00.538376 DeviceVref_Margin_A1==40
410 01:39:00.538813
411 01:39:00.539249
412 01:39:00.539683 channel==1
413 01:39:00.543692 RxClkDly_Margin_A0==88 ps 9
414 01:39:00.544207 TxDqDly_Margin_A0==98 ps 10
415 01:39:00.549106 RxClkDly_Margin_A1==98 ps 10
416 01:39:00.549578 TxDqDly_Margin_A1==88 ps 9
417 01:39:00.554805 TrainedVREFDQ_A0==77
418 01:39:00.555274 TrainedVREFDQ_A1==77
419 01:39:00.555713 VrefDac_Margin_A0==22
420 01:39:00.560322 DeviceVref_Margin_A0==37
421 01:39:00.560790 VrefDac_Margin_A1==24
422 01:39:00.565905 DeviceVref_Margin_A1==37
423 01:39:00.566388
424 01:39:00.566828 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 01:39:00.567262
426 01:39:00.599554 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
427 01:39:00.600176 2D training succeed
428 01:39:00.605093 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 01:39:00.610829 auto size-- 65535DDR cs0 size: 2048MB
430 01:39:00.611303 DDR cs1 size: 2048MB
431 01:39:00.616311 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 01:39:00.616778 cs0 DataBus test pass
433 01:39:00.621903 cs1 DataBus test pass
434 01:39:00.622367 cs0 AddrBus test pass
435 01:39:00.622805 cs1 AddrBus test pass
436 01:39:00.623231
437 01:39:00.627592 100bdlr_step_size ps== 420
438 01:39:00.628096 result report
439 01:39:00.633239 boot times 0Enable ddr reg access
440 01:39:00.637414 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 01:39:00.651095 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 01:39:01.224028 0.0;M3 CHK:0;cm4_sp_mode 0
443 01:39:01.224705 MVN_1=0x00000000
444 01:39:01.229367 MVN_2=0x00000000
445 01:39:01.235401 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 01:39:01.235929 OPS=0x10
447 01:39:01.236409 ring efuse init
448 01:39:01.236845 chipver efuse init
449 01:39:01.243462 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 01:39:01.243961 [0.018961 Inits done]
451 01:39:01.244435 secure task start!
452 01:39:01.250921 high task start!
453 01:39:01.251393 low task start!
454 01:39:01.251832 run into bl31
455 01:39:01.257651 NOTICE: BL31: v1.3(release):4fc40b1
456 01:39:01.265317 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 01:39:01.265800 NOTICE: BL31: G12A normal boot!
458 01:39:01.290696 NOTICE: BL31: BL33 decompress pass
459 01:39:01.296633 ERROR: Error initializing runtime service opteed_fast
460 01:39:02.529241
461 01:39:02.529876
462 01:39:02.537611 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 01:39:02.538197
464 01:39:02.538689 Model: Libre Computer AML-A311D-CC Alta
465 01:39:02.745999 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 01:39:02.769502 DRAM: 2 GiB (effective 3.8 GiB)
467 01:39:02.912522 Core: 408 devices, 31 uclasses, devicetree: separate
468 01:39:02.918261 WDT: Not starting watchdog@f0d0
469 01:39:02.950585 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 01:39:02.963098 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 01:39:02.967949 ** Bad device specification mmc 0 **
472 01:39:02.978310 Card did not respond to voltage select! : -110
473 01:39:02.985926 ** Bad device specification mmc 0 **
474 01:39:02.986429 Couldn't find partition mmc 0
475 01:39:02.994290 Card did not respond to voltage select! : -110
476 01:39:02.999784 ** Bad device specification mmc 0 **
477 01:39:03.000311 Couldn't find partition mmc 0
478 01:39:03.004882 Error: could not access storage.
479 01:39:04.269942 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 01:39:04.270403 bl2_stage_init 0x01
481 01:39:04.270641 bl2_stage_init 0x81
482 01:39:04.275433 hw id: 0x0000 - pwm id 0x01
483 01:39:04.276034 bl2_stage_init 0xc1
484 01:39:04.276411 bl2_stage_init 0x02
485 01:39:04.276741
486 01:39:04.281042 L0:00000000
487 01:39:04.281421 L1:20000703
488 01:39:04.281660 L2:00008067
489 01:39:04.281875 L3:14000000
490 01:39:04.286612 B2:00402000
491 01:39:04.287155 B1:e0f83180
492 01:39:04.287518
493 01:39:04.287852 TE: 58167
494 01:39:04.288340
495 01:39:04.292307 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 01:39:04.292832
497 01:39:04.293295 Board ID = 1
498 01:39:04.297813 Set A53 clk to 24M
499 01:39:04.298317 Set A73 clk to 24M
500 01:39:04.298769 Set clk81 to 24M
501 01:39:04.303416 A53 clk: 1200 MHz
502 01:39:04.303913 A73 clk: 1200 MHz
503 01:39:04.304422 CLK81: 166.6M
504 01:39:04.304872 smccc: 00012abe
505 01:39:04.309020 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 01:39:04.314599 board id: 1
507 01:39:04.320471 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 01:39:04.331269 fw parse done
509 01:39:04.337093 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 01:39:04.379726 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 01:39:04.390653 PIEI prepare done
512 01:39:04.391182 fastboot data load
513 01:39:04.391646 fastboot data verify
514 01:39:04.396378 verify result: 266
515 01:39:04.401910 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 01:39:04.402424 LPDDR4 probe
517 01:39:04.402880 ddr clk to 1584MHz
518 01:39:04.410354 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 01:39:04.447272
520 01:39:04.447917 dmc_version 0001
521 01:39:04.453863 Check phy result
522 01:39:04.459684 INFO : End of CA training
523 01:39:04.460429 INFO : End of initialization
524 01:39:04.465446 INFO : Training has run successfully!
525 01:39:04.466143 Check phy result
526 01:39:04.470896 INFO : End of initialization
527 01:39:04.471527 INFO : End of read enable training
528 01:39:04.476433 INFO : End of fine write leveling
529 01:39:04.482132 INFO : End of Write leveling coarse delay
530 01:39:04.482885 INFO : Training has run successfully!
531 01:39:04.483491 Check phy result
532 01:39:04.487680 INFO : End of initialization
533 01:39:04.488315 INFO : End of read dq deskew training
534 01:39:04.493368 INFO : End of MPR read delay center optimization
535 01:39:04.498898 INFO : End of write delay center optimization
536 01:39:04.504539 INFO : End of read delay center optimization
537 01:39:04.505170 INFO : End of max read latency training
538 01:39:04.510118 INFO : Training has run successfully!
539 01:39:04.510976 1D training succeed
540 01:39:04.519288 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 01:39:04.566975 Check phy result
542 01:39:04.567419 INFO : End of initialization
543 01:39:04.588580 INFO : End of 2D read delay Voltage center optimization
544 01:39:04.608622 INFO : End of 2D read delay Voltage center optimization
545 01:39:04.660489 INFO : End of 2D write delay Voltage center optimization
546 01:39:04.710347 INFO : End of 2D write delay Voltage center optimization
547 01:39:04.715323 INFO : Training has run successfully!
548 01:39:04.715636
549 01:39:04.715883 channel==0
550 01:39:04.720816 RxClkDly_Margin_A0==88 ps 9
551 01:39:04.721124 TxDqDly_Margin_A0==98 ps 10
552 01:39:04.726657 RxClkDly_Margin_A1==88 ps 9
553 01:39:04.726989 TxDqDly_Margin_A1==98 ps 10
554 01:39:04.727224 TrainedVREFDQ_A0==74
555 01:39:04.732107 TrainedVREFDQ_A1==74
556 01:39:04.732555 VrefDac_Margin_A0==25
557 01:39:04.732924 DeviceVref_Margin_A0==40
558 01:39:04.737651 VrefDac_Margin_A1==25
559 01:39:04.738083 DeviceVref_Margin_A1==40
560 01:39:04.738445
561 01:39:04.738711
562 01:39:04.743365 channel==1
563 01:39:04.743703 RxClkDly_Margin_A0==98 ps 10
564 01:39:04.743952 TxDqDly_Margin_A0==98 ps 10
565 01:39:04.749264 RxClkDly_Margin_A1==88 ps 9
566 01:39:04.749601 TxDqDly_Margin_A1==88 ps 9
567 01:39:04.754437 TrainedVREFDQ_A0==76
568 01:39:04.755011 TrainedVREFDQ_A1==77
569 01:39:04.755450 VrefDac_Margin_A0==22
570 01:39:04.760064 DeviceVref_Margin_A0==38
571 01:39:04.760403 VrefDac_Margin_A1==24
572 01:39:04.765586 DeviceVref_Margin_A1==37
573 01:39:04.765935
574 01:39:04.766164 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 01:39:04.766397
576 01:39:04.799199 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
577 01:39:04.799594 2D training succeed
578 01:39:04.804929 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 01:39:04.810430 auto size-- 65535DDR cs0 size: 2048MB
580 01:39:04.810779 DDR cs1 size: 2048MB
581 01:39:04.817077 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 01:39:04.818881 cs0 DataBus test pass
583 01:39:04.821601 cs1 DataBus test pass
584 01:39:04.822200 cs0 AddrBus test pass
585 01:39:04.822424 cs1 AddrBus test pass
586 01:39:04.822632
587 01:39:04.827357 100bdlr_step_size ps== 420
588 01:39:04.827674 result report
589 01:39:04.833852 boot times 0Enable ddr reg access
590 01:39:04.838219 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 01:39:04.852136 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 01:39:05.423757 0.0;M3 CHK:0;cm4_sp_mode 0
593 01:39:05.424228 MVN_1=0x00000000
594 01:39:05.429336 MVN_2=0x00000000
595 01:39:05.435032 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 01:39:05.435365 OPS=0x10
597 01:39:05.435582 ring efuse init
598 01:39:05.435786 chipver efuse init
599 01:39:05.440749 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 01:39:05.446338 [0.018961 Inits done]
601 01:39:05.446670 secure task start!
602 01:39:05.446880 high task start!
603 01:39:05.451073 low task start!
604 01:39:05.451386 run into bl31
605 01:39:05.457587 NOTICE: BL31: v1.3(release):4fc40b1
606 01:39:05.465375 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 01:39:05.465698 NOTICE: BL31: G12A normal boot!
608 01:39:05.490542 NOTICE: BL31: BL33 decompress pass
609 01:39:05.496295 ERROR: Error initializing runtime service opteed_fast
610 01:39:06.729241
611 01:39:06.729650
612 01:39:06.737506 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 01:39:06.737883
614 01:39:06.738207 Model: Libre Computer AML-A311D-CC Alta
615 01:39:06.946011 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 01:39:06.968380 DRAM: 2 GiB (effective 3.8 GiB)
617 01:39:07.112288 Core: 408 devices, 31 uclasses, devicetree: separate
618 01:39:07.118238 WDT: Not starting watchdog@f0d0
619 01:39:07.150503 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 01:39:07.163011 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 01:39:07.167027 ** Bad device specification mmc 0 **
622 01:39:07.178279 Card did not respond to voltage select! : -110
623 01:39:07.185866 ** Bad device specification mmc 0 **
624 01:39:07.186181 Couldn't find partition mmc 0
625 01:39:07.194197 Card did not respond to voltage select! : -110
626 01:39:07.199665 ** Bad device specification mmc 0 **
627 01:39:07.200017 Couldn't find partition mmc 0
628 01:39:07.203879 Error: could not access storage.
629 01:39:07.547520 Net: eth0: ethernet@ff3f0000
630 01:39:07.547944 starting USB...
631 01:39:07.800191 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 01:39:07.800762 Starting the controller
633 01:39:07.807055 USB XHCI 1.10
634 01:39:09.519945 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 01:39:09.520410 bl2_stage_init 0x01
636 01:39:09.520623 bl2_stage_init 0x81
637 01:39:09.525535 hw id: 0x0000 - pwm id 0x01
638 01:39:09.525964 bl2_stage_init 0xc1
639 01:39:09.526273 bl2_stage_init 0x02
640 01:39:09.526575
641 01:39:09.531145 L0:00000000
642 01:39:09.531463 L1:20000703
643 01:39:09.531666 L2:00008067
644 01:39:09.531863 L3:14000000
645 01:39:09.534110 B2:00402000
646 01:39:09.534377 B1:e0f83180
647 01:39:09.534579
648 01:39:09.534777 TE: 58124
649 01:39:09.534973
650 01:39:09.545274 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 01:39:09.545621
652 01:39:09.545835 Board ID = 1
653 01:39:09.546033 Set A53 clk to 24M
654 01:39:09.546229 Set A73 clk to 24M
655 01:39:09.550843 Set clk81 to 24M
656 01:39:09.551272 A53 clk: 1200 MHz
657 01:39:09.551595 A73 clk: 1200 MHz
658 01:39:09.556523 CLK81: 166.6M
659 01:39:09.556981 smccc: 00012a91
660 01:39:09.562058 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 01:39:09.562378 board id: 1
662 01:39:09.569808 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 01:39:09.581309 fw parse done
664 01:39:09.587215 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 01:39:09.629767 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 01:39:09.640830 PIEI prepare done
667 01:39:09.641194 fastboot data load
668 01:39:09.641434 fastboot data verify
669 01:39:09.646368 verify result: 266
670 01:39:09.651894 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 01:39:09.652452 LPDDR4 probe
672 01:39:09.652922 ddr clk to 1584MHz
673 01:39:09.659910 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 01:39:09.697277
675 01:39:09.697808 dmc_version 0001
676 01:39:09.703874 Check phy result
677 01:39:09.709751 INFO : End of CA training
678 01:39:09.710268 INFO : End of initialization
679 01:39:09.715295 INFO : Training has run successfully!
680 01:39:09.715791 Check phy result
681 01:39:09.720881 INFO : End of initialization
682 01:39:09.721380 INFO : End of read enable training
683 01:39:09.726424 INFO : End of fine write leveling
684 01:39:09.732087 INFO : End of Write leveling coarse delay
685 01:39:09.732609 INFO : Training has run successfully!
686 01:39:09.733081 Check phy result
687 01:39:09.737634 INFO : End of initialization
688 01:39:09.738130 INFO : End of read dq deskew training
689 01:39:09.743284 INFO : End of MPR read delay center optimization
690 01:39:09.748876 INFO : End of write delay center optimization
691 01:39:09.754510 INFO : End of read delay center optimization
692 01:39:09.754851 INFO : End of max read latency training
693 01:39:09.760164 INFO : Training has run successfully!
694 01:39:09.760526 1D training succeed
695 01:39:09.769319 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 01:39:09.816862 Check phy result
697 01:39:09.817431 INFO : End of initialization
698 01:39:09.839514 INFO : End of 2D read delay Voltage center optimization
699 01:39:09.859694 INFO : End of 2D read delay Voltage center optimization
700 01:39:09.911787 INFO : End of 2D write delay Voltage center optimization
701 01:39:09.961210 INFO : End of 2D write delay Voltage center optimization
702 01:39:09.966681 INFO : Training has run successfully!
703 01:39:09.967032
704 01:39:09.967254 channel==0
705 01:39:09.972357 RxClkDly_Margin_A0==88 ps 9
706 01:39:09.972757 TxDqDly_Margin_A0==98 ps 10
707 01:39:09.975577 RxClkDly_Margin_A1==88 ps 9
708 01:39:09.976117 TxDqDly_Margin_A1==98 ps 10
709 01:39:09.981189 TrainedVREFDQ_A0==74
710 01:39:09.981556 TrainedVREFDQ_A1==75
711 01:39:09.986689 VrefDac_Margin_A0==24
712 01:39:09.987047 DeviceVref_Margin_A0==40
713 01:39:09.987264 VrefDac_Margin_A1==24
714 01:39:09.992385 DeviceVref_Margin_A1==39
715 01:39:09.992935
716 01:39:09.993291
717 01:39:09.993628 channel==1
718 01:39:09.993962 RxClkDly_Margin_A0==98 ps 10
719 01:39:09.997999 TxDqDly_Margin_A0==88 ps 9
720 01:39:09.998358 RxClkDly_Margin_A1==98 ps 10
721 01:39:10.003577 TxDqDly_Margin_A1==88 ps 9
722 01:39:10.004093 TrainedVREFDQ_A0==77
723 01:39:10.004449 TrainedVREFDQ_A1==77
724 01:39:10.009200 VrefDac_Margin_A0==22
725 01:39:10.009544 DeviceVref_Margin_A0==37
726 01:39:10.014812 VrefDac_Margin_A1==22
727 01:39:10.015336 DeviceVref_Margin_A1==37
728 01:39:10.015720
729 01:39:10.020345 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 01:39:10.020722
731 01:39:10.048268 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
732 01:39:10.054000 2D training succeed
733 01:39:10.059535 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 01:39:10.060325 auto size-- 65535DDR cs0 size: 2048MB
735 01:39:10.065128 DDR cs1 size: 2048MB
736 01:39:10.065840 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 01:39:10.070653 cs0 DataBus test pass
738 01:39:10.071061 cs1 DataBus test pass
739 01:39:10.071300 cs0 AddrBus test pass
740 01:39:10.076418 cs1 AddrBus test pass
741 01:39:10.076814
742 01:39:10.077048 100bdlr_step_size ps== 420
743 01:39:10.077278 result report
744 01:39:10.081879 boot times 0Enable ddr reg access
745 01:39:10.089575 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 01:39:10.103049 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 01:39:10.676842 0.0;M3 CHK:0;cm4_sp_mode 0
748 01:39:10.677285 MVN_1=0x00000000
749 01:39:10.682314 MVN_2=0x00000000
750 01:39:10.688024 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 01:39:10.688572 OPS=0x10
752 01:39:10.688997 ring efuse init
753 01:39:10.689399 chipver efuse init
754 01:39:10.693577 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 01:39:10.699229 [0.018961 Inits done]
756 01:39:10.699753 secure task start!
757 01:39:10.700214 high task start!
758 01:39:10.703779 low task start!
759 01:39:10.704227 run into bl31
760 01:39:10.710425 NOTICE: BL31: v1.3(release):4fc40b1
761 01:39:10.718270 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 01:39:10.718799 NOTICE: BL31: G12A normal boot!
763 01:39:10.743611 NOTICE: BL31: BL33 decompress pass
764 01:39:10.749263 ERROR: Error initializing runtime service opteed_fast
765 01:39:11.982315
766 01:39:11.983098
767 01:39:11.990725 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 01:39:11.991419
769 01:39:11.991967 Model: Libre Computer AML-A311D-CC Alta
770 01:39:12.199049 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 01:39:12.222511 DRAM: 2 GiB (effective 3.8 GiB)
772 01:39:12.365503 Core: 408 devices, 31 uclasses, devicetree: separate
773 01:39:12.371206 WDT: Not starting watchdog@f0d0
774 01:39:12.403543 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 01:39:12.415927 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 01:39:12.420893 ** Bad device specification mmc 0 **
777 01:39:12.431382 Card did not respond to voltage select! : -110
778 01:39:12.438887 ** Bad device specification mmc 0 **
779 01:39:12.439241 Couldn't find partition mmc 0
780 01:39:12.447250 Card did not respond to voltage select! : -110
781 01:39:12.452801 ** Bad device specification mmc 0 **
782 01:39:12.453345 Couldn't find partition mmc 0
783 01:39:12.457875 Error: could not access storage.
784 01:39:12.800322 Net: eth0: ethernet@ff3f0000
785 01:39:12.801000 starting USB...
786 01:39:13.052210 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 01:39:13.052879 Starting the controller
788 01:39:13.058993 USB XHCI 1.10
789 01:39:15.221883 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 01:39:15.222324 bl2_stage_init 0x01
791 01:39:15.222588 bl2_stage_init 0x81
792 01:39:15.227351 hw id: 0x0000 - pwm id 0x01
793 01:39:15.227816 bl2_stage_init 0xc1
794 01:39:15.228233 bl2_stage_init 0x02
795 01:39:15.228614
796 01:39:15.232921 L0:00000000
797 01:39:15.233245 L1:20000703
798 01:39:15.233480 L2:00008067
799 01:39:15.233708 L3:14000000
800 01:39:15.235811 B2:00402000
801 01:39:15.236255 B1:e0f83180
802 01:39:15.236633
803 01:39:15.237014 TE: 58159
804 01:39:15.237393
805 01:39:15.247012 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 01:39:15.247542
807 01:39:15.247815 Board ID = 1
808 01:39:15.248075 Set A53 clk to 24M
809 01:39:15.248303 Set A73 clk to 24M
810 01:39:15.252694 Set clk81 to 24M
811 01:39:15.253042 A53 clk: 1200 MHz
812 01:39:15.253278 A73 clk: 1200 MHz
813 01:39:15.256074 CLK81: 166.6M
814 01:39:15.256538 smccc: 00012ab5
815 01:39:15.261622 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 01:39:15.267242 board id: 1
817 01:39:15.272446 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 01:39:15.283142 fw parse done
819 01:39:15.289079 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 01:39:15.331616 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 01:39:15.342606 PIEI prepare done
822 01:39:15.342945 fastboot data load
823 01:39:15.343636 fastboot data verify
824 01:39:15.348146 verify result: 266
825 01:39:15.353858 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 01:39:15.354164 LPDDR4 probe
827 01:39:15.354419 ddr clk to 1584MHz
828 01:39:15.361812 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 01:39:15.399144
830 01:39:15.399576 dmc_version 0001
831 01:39:15.405706 Check phy result
832 01:39:15.411567 INFO : End of CA training
833 01:39:15.411965 INFO : End of initialization
834 01:39:15.417141 INFO : Training has run successfully!
835 01:39:15.417520 Check phy result
836 01:39:15.422809 INFO : End of initialization
837 01:39:15.423306 INFO : End of read enable training
838 01:39:15.428304 INFO : End of fine write leveling
839 01:39:15.433933 INFO : End of Write leveling coarse delay
840 01:39:15.434289 INFO : Training has run successfully!
841 01:39:15.434875 Check phy result
842 01:39:15.439589 INFO : End of initialization
843 01:39:15.439938 INFO : End of read dq deskew training
844 01:39:15.445109 INFO : End of MPR read delay center optimization
845 01:39:15.450869 INFO : End of write delay center optimization
846 01:39:15.456313 INFO : End of read delay center optimization
847 01:39:15.456663 INFO : End of max read latency training
848 01:39:15.461943 INFO : Training has run successfully!
849 01:39:15.462446 1D training succeed
850 01:39:15.471165 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 01:39:15.518876 Check phy result
852 01:39:15.519311 INFO : End of initialization
853 01:39:15.541475 INFO : End of 2D read delay Voltage center optimization
854 01:39:15.561663 INFO : End of 2D read delay Voltage center optimization
855 01:39:15.613714 INFO : End of 2D write delay Voltage center optimization
856 01:39:15.663139 INFO : End of 2D write delay Voltage center optimization
857 01:39:15.668559 INFO : Training has run successfully!
858 01:39:15.669063
859 01:39:15.669508 channel==0
860 01:39:15.674195 RxClkDly_Margin_A0==88 ps 9
861 01:39:15.674675 TxDqDly_Margin_A0==98 ps 10
862 01:39:15.677520 RxClkDly_Margin_A1==88 ps 9
863 01:39:15.677985 TxDqDly_Margin_A1==98 ps 10
864 01:39:15.683035 TrainedVREFDQ_A0==74
865 01:39:15.683578 TrainedVREFDQ_A1==74
866 01:39:15.688583 VrefDac_Margin_A0==24
867 01:39:15.689126 DeviceVref_Margin_A0==40
868 01:39:15.689521 VrefDac_Margin_A1==24
869 01:39:15.694187 DeviceVref_Margin_A1==40
870 01:39:15.694645
871 01:39:15.695041
872 01:39:15.695428 channel==1
873 01:39:15.695808 RxClkDly_Margin_A0==98 ps 10
874 01:39:15.699890 TxDqDly_Margin_A0==88 ps 9
875 01:39:15.700375 RxClkDly_Margin_A1==88 ps 9
876 01:39:15.705391 TxDqDly_Margin_A1==88 ps 9
877 01:39:15.705844 TrainedVREFDQ_A0==77
878 01:39:15.706239 TrainedVREFDQ_A1==77
879 01:39:15.711021 VrefDac_Margin_A0==22
880 01:39:15.711451 DeviceVref_Margin_A0==37
881 01:39:15.716669 VrefDac_Margin_A1==24
882 01:39:15.717107 DeviceVref_Margin_A1==37
883 01:39:15.717497
884 01:39:15.722099 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 01:39:15.722530
886 01:39:15.750088 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
887 01:39:15.755662 2D training succeed
888 01:39:15.761268 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 01:39:15.761711 auto size-- 65535DDR cs0 size: 2048MB
890 01:39:15.766900 DDR cs1 size: 2048MB
891 01:39:15.767328 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 01:39:15.772453 cs0 DataBus test pass
893 01:39:15.772897 cs1 DataBus test pass
894 01:39:15.773285 cs0 AddrBus test pass
895 01:39:15.778043 cs1 AddrBus test pass
896 01:39:15.778468
897 01:39:15.778856 100bdlr_step_size ps== 420
898 01:39:15.779247 result report
899 01:39:15.783685 boot times 0Enable ddr reg access
900 01:39:15.791329 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 01:39:15.804895 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 01:39:16.378045 0.0;M3 CHK:0;cm4_sp_mode 0
903 01:39:16.378485 MVN_1=0x00000000
904 01:39:16.383357 MVN_2=0x00000000
905 01:39:16.389113 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 01:39:16.389418 OPS=0x10
907 01:39:16.389661 ring efuse init
908 01:39:16.389890 chipver efuse init
909 01:39:16.394735 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 01:39:16.400347 [0.018961 Inits done]
911 01:39:16.400805 secure task start!
912 01:39:16.401189 high task start!
913 01:39:16.404935 low task start!
914 01:39:16.405361 run into bl31
915 01:39:16.411653 NOTICE: BL31: v1.3(release):4fc40b1
916 01:39:16.419420 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 01:39:16.419775 NOTICE: BL31: G12A normal boot!
918 01:39:16.444753 NOTICE: BL31: BL33 decompress pass
919 01:39:16.450405 ERROR: Error initializing runtime service opteed_fast
920 01:39:17.683437
921 01:39:17.683962
922 01:39:17.691774 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 01:39:17.692380
924 01:39:17.692834 Model: Libre Computer AML-A311D-CC Alta
925 01:39:17.900404 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 01:39:17.923684 DRAM: 2 GiB (effective 3.8 GiB)
927 01:39:18.066733 Core: 408 devices, 31 uclasses, devicetree: separate
928 01:39:18.072512 WDT: Not starting watchdog@f0d0
929 01:39:18.104780 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 01:39:18.117249 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 01:39:18.122234 ** Bad device specification mmc 0 **
932 01:39:18.132478 Card did not respond to voltage select! : -110
933 01:39:18.140252 ** Bad device specification mmc 0 **
934 01:39:18.140848 Couldn't find partition mmc 0
935 01:39:18.148491 Card did not respond to voltage select! : -110
936 01:39:18.153998 ** Bad device specification mmc 0 **
937 01:39:18.154383 Couldn't find partition mmc 0
938 01:39:18.159065 Error: could not access storage.
939 01:39:18.501580 Net: eth0: ethernet@ff3f0000
940 01:39:18.502278 starting USB...
941 01:39:18.753396 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 01:39:18.753913 Starting the controller
943 01:39:18.760441 USB XHCI 1.10
944 01:39:20.314288 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 01:39:20.322630 scanning usb for storage devices... 0 Storage Device(s) found
947 01:39:20.374342 Hit any key to stop autoboot: 1
948 01:39:20.375123 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
949 01:39:20.375955 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
950 01:39:20.376591 Setting prompt string to ['=>']
951 01:39:20.376931 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
952 01:39:20.390375 0
953 01:39:20.391397 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 01:39:20.391804 Sending with 10 millisecond of delay
956 01:39:21.527668 => setenv autoload no
957 01:39:21.541902 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
958 01:39:21.546890 setenv autoload no
959 01:39:21.547633 Sending with 10 millisecond of delay
961 01:39:23.345277 => setenv initrd_high 0xffffffff
962 01:39:23.356276 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
963 01:39:23.357211 setenv initrd_high 0xffffffff
964 01:39:23.357953 Sending with 10 millisecond of delay
966 01:39:24.976908 => setenv fdt_high 0xffffffff
967 01:39:24.987555 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
968 01:39:24.988277 setenv fdt_high 0xffffffff
969 01:39:24.988774 Sending with 10 millisecond of delay
971 01:39:25.280187 => dhcp
972 01:39:25.290760 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
973 01:39:25.291284 dhcp
974 01:39:25.291530 Speed: 1000, full duplex
975 01:39:25.291748 BOOTP broadcast 1
976 01:39:25.299804 DHCP client bound to address 192.168.6.27 (9 ms)
977 01:39:25.300316 Sending with 10 millisecond of delay
979 01:39:26.976409 => setenv serverip 192.168.6.2
980 01:39:26.986981 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
981 01:39:26.987537 setenv serverip 192.168.6.2
982 01:39:26.988030 Sending with 10 millisecond of delay
984 01:39:30.722807 => tftpboot 0x01080000 949440/tftp-deploy-5a4t3n63/kernel/uImage
985 01:39:30.733375 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
986 01:39:30.733945 tftpboot 0x01080000 949440/tftp-deploy-5a4t3n63/kernel/uImage
987 01:39:30.734177 Speed: 1000, full duplex
988 01:39:30.734385 Using ethernet@ff3f0000 device
989 01:39:30.736094 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
990 01:39:30.741693 Filename '949440/tftp-deploy-5a4t3n63/kernel/uImage'.
991 01:39:30.745430 Load address: 0x1080000
992 01:39:33.680927 Loading: *################################################## 36.1 MiB
993 01:39:33.681517 12.3 MiB/s
994 01:39:33.681919 done
995 01:39:33.684373 Bytes transferred = 37880384 (2420240 hex)
996 01:39:33.685182 Sending with 10 millisecond of delay
998 01:39:38.377435 => tftpboot 0x08000000 949440/tftp-deploy-5a4t3n63/ramdisk/ramdisk.cpio.gz.uboot
999 01:39:38.388266 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1000 01:39:38.389188 tftpboot 0x08000000 949440/tftp-deploy-5a4t3n63/ramdisk/ramdisk.cpio.gz.uboot
1001 01:39:38.389630 Speed: 1000, full duplex
1002 01:39:38.390041 Using ethernet@ff3f0000 device
1003 01:39:38.391633 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1004 01:39:38.400311 Filename '949440/tftp-deploy-5a4t3n63/ramdisk/ramdisk.cpio.gz.uboot'.
1005 01:39:38.401060 Load address: 0x8000000
1006 01:39:38.646713 Loading: *###### UDP wrong checksum 000000ff 00007fe1
1007 01:39:38.686749 # UDP wrong checksum 000000ff 00000fd4
1008 01:39:40.056643 ############ UDP wrong checksum 000000ff 0000d7c9
1009 01:39:40.098914 UDP wrong checksum 000000ff 00006abc
1010 01:39:45.033243 T ############################## UDP wrong checksum 00000005 00006520
1011 01:39:47.658204 UDP wrong checksum 000000ff 0000a96f
1012 01:39:47.729526 UDP wrong checksum 000000ff 00003462
1013 01:39:50.034641 T UDP wrong checksum 00000005 00006520
1014 01:40:00.036571 T T UDP wrong checksum 00000005 00006520
1015 01:40:05.009170 UDP wrong checksum 000000ff 00008cb3
1016 01:40:05.090719 T UDP wrong checksum 000000ff 000028a6
1017 01:40:20.040475 T T T UDP wrong checksum 00000005 00006520
1018 01:40:28.907686 T UDP wrong checksum 000000ff 00005d94
1019 01:40:28.921775 UDP wrong checksum 000000ff 0000e686
1020 01:40:30.920671 T UDP wrong checksum 000000ff 0000c26d
1021 01:40:30.971107 UDP wrong checksum 000000ff 00005360
1022 01:40:35.044707
1023 01:40:35.045389 Retry count exceeded; starting again
1025 01:40:35.046952 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1028 01:40:35.049139 end: 2.4 uboot-commands (duration 00:01:47) [common]
1030 01:40:35.050693 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1032 01:40:35.051878 end: 2 uboot-action (duration 00:01:47) [common]
1034 01:40:35.053594 Cleaning after the job
1035 01:40:35.054198 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/ramdisk
1036 01:40:35.055441 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/kernel
1037 01:40:35.062645 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/dtb
1038 01:40:35.063967 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/nfsrootfs
1039 01:40:35.137289 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949440/tftp-deploy-5a4t3n63/modules
1040 01:40:35.144388 start: 4.1 power-off (timeout 00:00:30) [common]
1041 01:40:35.145002 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1042 01:40:35.181770 >> OK - accepted request
1043 01:40:35.183955 Returned 0 in 0 seconds
1044 01:40:35.284750 end: 4.1 power-off (duration 00:00:00) [common]
1046 01:40:35.285788 start: 4.2 read-feedback (timeout 00:10:00) [common]
1047 01:40:35.286449 Listened to connection for namespace 'common' for up to 1s
1048 01:40:36.286558 Finalising connection for namespace 'common'
1049 01:40:36.287345 Disconnecting from shell: Finalise
1050 01:40:36.287917 =>
1051 01:40:36.389212 end: 4.2 read-feedback (duration 00:00:01) [common]
1052 01:40:36.389949 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949440
1053 01:40:39.018813 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949440
1054 01:40:39.019426 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.