Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:57:55.378929 lava-dispatcher, installed at version: 2024.01
2 21:57:55.379704 start: 0 validate
3 21:57:55.380236 Start time: 2024-11-06 21:57:55.380206+00:00 (UTC)
4 21:57:55.380762 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:57:55.381301 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 21:57:55.423196 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:57:55.423753 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 21:57:55.451348 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:57:55.452028 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:57:56.496540 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:57:56.497075 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 21:57:56.547281 validate duration: 1.17
14 21:57:56.548372 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:57:56.549019 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:57:56.549588 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:57:56.550616 Not decompressing ramdisk as can be used compressed.
18 21:57:56.551405 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 21:57:56.551857 saving as /var/lib/lava/dispatcher/tmp/949264/tftp-deploy-_nq3udz9/ramdisk/rootfs.cpio.gz
20 21:57:56.552377 total size: 8181887 (7 MB)
21 21:57:56.595349 progress 0 % (0 MB)
22 21:57:56.607400 progress 5 % (0 MB)
23 21:57:56.613812 progress 10 % (0 MB)
24 21:57:56.620497 progress 15 % (1 MB)
25 21:57:56.626689 progress 20 % (1 MB)
26 21:57:56.633340 progress 25 % (1 MB)
27 21:57:56.639343 progress 30 % (2 MB)
28 21:57:56.646005 progress 35 % (2 MB)
29 21:57:56.654116 progress 40 % (3 MB)
30 21:57:56.660496 progress 45 % (3 MB)
31 21:57:56.666930 progress 50 % (3 MB)
32 21:57:56.673518 progress 55 % (4 MB)
33 21:57:56.679633 progress 60 % (4 MB)
34 21:57:56.685991 progress 65 % (5 MB)
35 21:57:56.693222 progress 70 % (5 MB)
36 21:57:56.700883 progress 75 % (5 MB)
37 21:57:56.708121 progress 80 % (6 MB)
38 21:57:56.714734 progress 85 % (6 MB)
39 21:57:56.720817 progress 90 % (7 MB)
40 21:57:56.727365 progress 95 % (7 MB)
41 21:57:56.733344 progress 100 % (7 MB)
42 21:57:56.734300 7 MB downloaded in 0.18 s (42.89 MB/s)
43 21:57:56.735046 end: 1.1.1 http-download (duration 00:00:00) [common]
45 21:57:56.736363 end: 1.1 download-retry (duration 00:00:00) [common]
46 21:57:56.736818 start: 1.2 download-retry (timeout 00:10:00) [common]
47 21:57:56.737259 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 21:57:56.737894 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/kernel/Image
49 21:57:56.738281 saving as /var/lib/lava/dispatcher/tmp/949264/tftp-deploy-_nq3udz9/kernel/Image
50 21:57:56.738614 total size: 45713920 (43 MB)
51 21:57:56.738873 No compression specified
52 21:57:56.774213 progress 0 % (0 MB)
53 21:57:56.805588 progress 5 % (2 MB)
54 21:57:56.835347 progress 10 % (4 MB)
55 21:57:56.864879 progress 15 % (6 MB)
56 21:57:56.894451 progress 20 % (8 MB)
57 21:57:56.923327 progress 25 % (10 MB)
58 21:57:56.952596 progress 30 % (13 MB)
59 21:57:56.982251 progress 35 % (15 MB)
60 21:57:57.011719 progress 40 % (17 MB)
61 21:57:57.040614 progress 45 % (19 MB)
62 21:57:57.070029 progress 50 % (21 MB)
63 21:57:57.099505 progress 55 % (24 MB)
64 21:57:57.128628 progress 60 % (26 MB)
65 21:57:57.157775 progress 65 % (28 MB)
66 21:57:57.187217 progress 70 % (30 MB)
67 21:57:57.216571 progress 75 % (32 MB)
68 21:57:57.245900 progress 80 % (34 MB)
69 21:57:57.274932 progress 85 % (37 MB)
70 21:57:57.304543 progress 90 % (39 MB)
71 21:57:57.334036 progress 95 % (41 MB)
72 21:57:57.362892 progress 100 % (43 MB)
73 21:57:57.363408 43 MB downloaded in 0.62 s (69.78 MB/s)
74 21:57:57.363897 end: 1.2.1 http-download (duration 00:00:01) [common]
76 21:57:57.364754 end: 1.2 download-retry (duration 00:00:01) [common]
77 21:57:57.365028 start: 1.3 download-retry (timeout 00:09:59) [common]
78 21:57:57.365291 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 21:57:57.365806 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 21:57:57.366115 saving as /var/lib/lava/dispatcher/tmp/949264/tftp-deploy-_nq3udz9/dtb/meson-g12b-a311d-libretech-cc.dtb
81 21:57:57.366327 total size: 54703 (0 MB)
82 21:57:57.366538 No compression specified
83 21:57:57.405583 progress 59 % (0 MB)
84 21:57:57.406435 progress 100 % (0 MB)
85 21:57:57.406988 0 MB downloaded in 0.04 s (1.28 MB/s)
86 21:57:57.407475 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:57:57.408341 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:57:57.408607 start: 1.4 download-retry (timeout 00:09:59) [common]
90 21:57:57.408871 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 21:57:57.409337 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/modules.tar.xz
92 21:57:57.409581 saving as /var/lib/lava/dispatcher/tmp/949264/tftp-deploy-_nq3udz9/modules/modules.tar
93 21:57:57.409788 total size: 11608172 (11 MB)
94 21:57:57.409999 Using unxz to decompress xz
95 21:57:57.443961 progress 0 % (0 MB)
96 21:57:57.511248 progress 5 % (0 MB)
97 21:57:57.587488 progress 10 % (1 MB)
98 21:57:57.688389 progress 15 % (1 MB)
99 21:57:57.783541 progress 20 % (2 MB)
100 21:57:57.863520 progress 25 % (2 MB)
101 21:57:57.944228 progress 30 % (3 MB)
102 21:57:58.023932 progress 35 % (3 MB)
103 21:57:58.105658 progress 40 % (4 MB)
104 21:57:58.187861 progress 45 % (5 MB)
105 21:57:58.279306 progress 50 % (5 MB)
106 21:57:58.357397 progress 55 % (6 MB)
107 21:57:58.442720 progress 60 % (6 MB)
108 21:57:58.523493 progress 65 % (7 MB)
109 21:57:58.599745 progress 70 % (7 MB)
110 21:57:58.680892 progress 75 % (8 MB)
111 21:57:58.776564 progress 80 % (8 MB)
112 21:57:58.867969 progress 85 % (9 MB)
113 21:57:58.947845 progress 90 % (9 MB)
114 21:57:59.116522 progress 95 % (10 MB)
115 21:57:59.264069 progress 100 % (11 MB)
116 21:57:59.276009 11 MB downloaded in 1.87 s (5.93 MB/s)
117 21:57:59.276953 end: 1.4.1 http-download (duration 00:00:02) [common]
119 21:57:59.278713 end: 1.4 download-retry (duration 00:00:02) [common]
120 21:57:59.279293 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 21:57:59.279866 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 21:57:59.280457 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:57:59.281018 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 21:57:59.282039 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb
125 21:57:59.282956 makedir: /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin
126 21:57:59.283648 makedir: /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/tests
127 21:57:59.284380 makedir: /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/results
128 21:57:59.285042 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-add-keys
129 21:57:59.286065 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-add-sources
130 21:57:59.287111 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-background-process-start
131 21:57:59.288220 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-background-process-stop
132 21:57:59.289368 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-common-functions
133 21:57:59.290385 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-echo-ipv4
134 21:57:59.291377 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-install-packages
135 21:57:59.292399 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-installed-packages
136 21:57:59.293396 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-os-build
137 21:57:59.294389 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-probe-channel
138 21:57:59.295368 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-probe-ip
139 21:57:59.296392 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-target-ip
140 21:57:59.297396 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-target-mac
141 21:57:59.298483 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-target-storage
142 21:57:59.299505 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-test-case
143 21:57:59.300549 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-test-event
144 21:57:59.301563 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-test-feedback
145 21:57:59.302570 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-test-raise
146 21:57:59.303560 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-test-reference
147 21:57:59.304599 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-test-runner
148 21:57:59.305595 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-test-set
149 21:57:59.306571 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-test-shell
150 21:57:59.307582 Updating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-install-packages (oe)
151 21:57:59.308690 Updating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/bin/lava-installed-packages (oe)
152 21:57:59.309611 Creating /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/environment
153 21:57:59.310390 LAVA metadata
154 21:57:59.310922 - LAVA_JOB_ID=949264
155 21:57:59.311399 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:57:59.312187 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 21:57:59.314322 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:57:59.315021 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 21:57:59.315488 skipped lava-vland-overlay
160 21:57:59.316066 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:57:59.316649 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 21:57:59.317124 skipped lava-multinode-overlay
163 21:57:59.317662 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:57:59.318218 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 21:57:59.318750 Loading test definitions
166 21:57:59.319362 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 21:57:59.319851 Using /lava-949264 at stage 0
168 21:57:59.322480 uuid=949264_1.5.2.4.1 testdef=None
169 21:57:59.323144 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:57:59.323726 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 21:57:59.327798 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:57:59.329548 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 21:57:59.334207 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:57:59.335885 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 21:57:59.338347 runner path: /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/0/tests/0_dmesg test_uuid 949264_1.5.2.4.1
178 21:57:59.338949 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:57:59.339786 Creating lava-test-runner.conf files
181 21:57:59.340049 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949264/lava-overlay-45qg4pdb/lava-949264/0 for stage 0
182 21:57:59.340515 - 0_dmesg
183 21:57:59.340901 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:57:59.341213 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 21:57:59.367254 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:57:59.367728 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 21:57:59.368055 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:57:59.368392 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:57:59.368677 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 21:58:00.409868 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 21:58:00.410520 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 21:58:00.410912 extracting modules file /var/lib/lava/dispatcher/tmp/949264/tftp-deploy-_nq3udz9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949264/extract-overlay-ramdisk-tjamrt4b/ramdisk
193 21:58:01.952431 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 21:58:01.952929 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 21:58:01.953235 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949264/compress-overlay-r_ayd5nb/overlay-1.5.2.5.tar.gz to ramdisk
196 21:58:01.953452 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949264/compress-overlay-r_ayd5nb/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949264/extract-overlay-ramdisk-tjamrt4b/ramdisk
197 21:58:01.984060 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:58:01.984504 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 21:58:01.984778 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 21:58:01.985013 Converting downloaded kernel to a uImage
201 21:58:01.985332 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949264/tftp-deploy-_nq3udz9/kernel/Image /var/lib/lava/dispatcher/tmp/949264/tftp-deploy-_nq3udz9/kernel/uImage
202 21:58:02.449427 output: Image Name:
203 21:58:02.449871 output: Created: Wed Nov 6 21:58:01 2024
204 21:58:02.450105 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:58:02.450320 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 21:58:02.450536 output: Load Address: 01080000
207 21:58:02.450746 output: Entry Point: 01080000
208 21:58:02.450977 output:
209 21:58:02.451363 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 21:58:02.451689 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 21:58:02.452035 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 21:58:02.452341 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:58:02.452613 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 21:58:02.452884 Building ramdisk /var/lib/lava/dispatcher/tmp/949264/extract-overlay-ramdisk-tjamrt4b/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949264/extract-overlay-ramdisk-tjamrt4b/ramdisk
215 21:58:04.922760 >> 181608 blocks
216 21:58:13.539031 Adding RAMdisk u-boot header.
217 21:58:13.539485 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949264/extract-overlay-ramdisk-tjamrt4b/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949264/extract-overlay-ramdisk-tjamrt4b/ramdisk.cpio.gz.uboot
218 21:58:13.813692 output: Image Name:
219 21:58:13.814114 output: Created: Wed Nov 6 21:58:13 2024
220 21:58:13.814536 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:58:13.814951 output: Data Size: 26062673 Bytes = 25451.83 KiB = 24.86 MiB
222 21:58:13.815356 output: Load Address: 00000000
223 21:58:13.815756 output: Entry Point: 00000000
224 21:58:13.816209 output:
225 21:58:13.817489 rename /var/lib/lava/dispatcher/tmp/949264/extract-overlay-ramdisk-tjamrt4b/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949264/tftp-deploy-_nq3udz9/ramdisk/ramdisk.cpio.gz.uboot
226 21:58:13.818211 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 21:58:13.818762 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 21:58:13.819298 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 21:58:13.819759 No LXC device requested
230 21:58:13.820321 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:58:13.820848 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 21:58:13.821354 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:58:13.821774 Checking files for TFTP limit of 4294967296 bytes.
234 21:58:13.824461 end: 1 tftp-deploy (duration 00:00:17) [common]
235 21:58:13.825046 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:58:13.825579 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:58:13.826088 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:58:13.826618 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:58:13.827152 Using kernel file from prepare-kernel: 949264/tftp-deploy-_nq3udz9/kernel/uImage
240 21:58:13.827756 substitutions:
241 21:58:13.828212 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:58:13.828625 - {DTB_ADDR}: 0x01070000
243 21:58:13.829028 - {DTB}: 949264/tftp-deploy-_nq3udz9/dtb/meson-g12b-a311d-libretech-cc.dtb
244 21:58:13.829431 - {INITRD}: 949264/tftp-deploy-_nq3udz9/ramdisk/ramdisk.cpio.gz.uboot
245 21:58:13.829833 - {KERNEL_ADDR}: 0x01080000
246 21:58:13.830228 - {KERNEL}: 949264/tftp-deploy-_nq3udz9/kernel/uImage
247 21:58:13.830625 - {LAVA_MAC}: None
248 21:58:13.831064 - {PRESEED_CONFIG}: None
249 21:58:13.831464 - {PRESEED_LOCAL}: None
250 21:58:13.831859 - {RAMDISK_ADDR}: 0x08000000
251 21:58:13.832287 - {RAMDISK}: 949264/tftp-deploy-_nq3udz9/ramdisk/ramdisk.cpio.gz.uboot
252 21:58:13.832689 - {ROOT_PART}: None
253 21:58:13.833088 - {ROOT}: None
254 21:58:13.833481 - {SERVER_IP}: 192.168.6.2
255 21:58:13.833879 - {TEE_ADDR}: 0x83000000
256 21:58:13.834270 - {TEE}: None
257 21:58:13.834662 Parsed boot commands:
258 21:58:13.835045 - setenv autoload no
259 21:58:13.835434 - setenv initrd_high 0xffffffff
260 21:58:13.835824 - setenv fdt_high 0xffffffff
261 21:58:13.836245 - dhcp
262 21:58:13.836639 - setenv serverip 192.168.6.2
263 21:58:13.837028 - tftpboot 0x01080000 949264/tftp-deploy-_nq3udz9/kernel/uImage
264 21:58:13.837417 - tftpboot 0x08000000 949264/tftp-deploy-_nq3udz9/ramdisk/ramdisk.cpio.gz.uboot
265 21:58:13.837806 - tftpboot 0x01070000 949264/tftp-deploy-_nq3udz9/dtb/meson-g12b-a311d-libretech-cc.dtb
266 21:58:13.838196 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:58:13.838593 - bootm 0x01080000 0x08000000 0x01070000
268 21:58:13.839100 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:58:13.840642 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:58:13.841101 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 21:58:13.855968 Setting prompt string to ['lava-test: # ']
273 21:58:13.857504 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:58:13.858120 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:58:13.858720 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:58:13.859333 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:58:13.860517 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 21:58:13.901289 >> OK - accepted request
279 21:58:13.903569 Returned 0 in 0 seconds
280 21:58:14.004641 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:58:14.006310 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:58:14.006893 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:58:14.007420 Setting prompt string to ['Hit any key to stop autoboot']
285 21:58:14.007883 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:58:14.009566 Trying 192.168.56.21...
287 21:58:14.010063 Connected to conserv1.
288 21:58:14.010484 Escape character is '^]'.
289 21:58:14.010911
290 21:58:14.011342 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 21:58:14.011788
292 21:58:24.974193 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 21:58:24.974624 bl2_stage_init 0x01
294 21:58:24.974878 bl2_stage_init 0x81
295 21:58:24.979779 hw id: 0x0000 - pwm id 0x01
296 21:58:24.980128 bl2_stage_init 0xc1
297 21:58:24.980369 bl2_stage_init 0x02
298 21:58:24.980617
299 21:58:24.985366 L0:00000000
300 21:58:24.985643 L1:20000703
301 21:58:24.985868 L2:00008067
302 21:58:24.986085 L3:14000000
303 21:58:24.990938 B2:00402000
304 21:58:24.991219 B1:e0f83180
305 21:58:24.991438
306 21:58:24.991652 TE: 58167
307 21:58:24.991864
308 21:58:24.996519 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 21:58:24.996798
310 21:58:24.997026 Board ID = 1
311 21:58:25.002139 Set A53 clk to 24M
312 21:58:25.002426 Set A73 clk to 24M
313 21:58:25.002650 Set clk81 to 24M
314 21:58:25.007764 A53 clk: 1200 MHz
315 21:58:25.008082 A73 clk: 1200 MHz
316 21:58:25.008310 CLK81: 166.6M
317 21:58:25.008535 smccc: 00012abd
318 21:58:25.013329 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 21:58:25.019095 board id: 1
320 21:58:25.024390 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 21:58:25.035599 fw parse done
322 21:58:25.041511 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 21:58:25.084201 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 21:58:25.094955 PIEI prepare done
325 21:58:25.095247 fastboot data load
326 21:58:25.095474 fastboot data verify
327 21:58:25.100611 verify result: 266
328 21:58:25.106231 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 21:58:25.106521 LPDDR4 probe
330 21:58:25.106755 ddr clk to 1584MHz
331 21:58:25.114264 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 21:58:25.151626
333 21:58:25.152024 dmc_version 0001
334 21:58:25.158178 Check phy result
335 21:58:25.164064 INFO : End of CA training
336 21:58:25.164371 INFO : End of initialization
337 21:58:25.169632 INFO : Training has run successfully!
338 21:58:25.169925 Check phy result
339 21:58:25.175208 INFO : End of initialization
340 21:58:25.175496 INFO : End of read enable training
341 21:58:25.178510 INFO : End of fine write leveling
342 21:58:25.184176 INFO : End of Write leveling coarse delay
343 21:58:25.189774 INFO : Training has run successfully!
344 21:58:25.190067 Check phy result
345 21:58:25.190295 INFO : End of initialization
346 21:58:25.195414 INFO : End of read dq deskew training
347 21:58:25.200948 INFO : End of MPR read delay center optimization
348 21:58:25.201236 INFO : End of write delay center optimization
349 21:58:25.206552 INFO : End of read delay center optimization
350 21:58:25.212191 INFO : End of max read latency training
351 21:58:25.212483 INFO : Training has run successfully!
352 21:58:25.217744 1D training succeed
353 21:58:25.223602 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 21:58:25.271284 Check phy result
355 21:58:25.271882 INFO : End of initialization
356 21:58:25.292970 INFO : End of 2D read delay Voltage center optimization
357 21:58:25.313211 INFO : End of 2D read delay Voltage center optimization
358 21:58:25.365301 INFO : End of 2D write delay Voltage center optimization
359 21:58:25.414602 INFO : End of 2D write delay Voltage center optimization
360 21:58:25.420199 INFO : Training has run successfully!
361 21:58:25.420702
362 21:58:25.421151 channel==0
363 21:58:25.425768 RxClkDly_Margin_A0==88 ps 9
364 21:58:25.426282 TxDqDly_Margin_A0==98 ps 10
365 21:58:25.431470 RxClkDly_Margin_A1==88 ps 9
366 21:58:25.431966 TxDqDly_Margin_A1==88 ps 9
367 21:58:25.432470 TrainedVREFDQ_A0==74
368 21:58:25.437067 TrainedVREFDQ_A1==74
369 21:58:25.437556 VrefDac_Margin_A0==25
370 21:58:25.437999 DeviceVref_Margin_A0==40
371 21:58:25.442512 VrefDac_Margin_A1==25
372 21:58:25.443007 DeviceVref_Margin_A1==40
373 21:58:25.443449
374 21:58:25.443881
375 21:58:25.444362 channel==1
376 21:58:25.448140 RxClkDly_Margin_A0==98 ps 10
377 21:58:25.448621 TxDqDly_Margin_A0==88 ps 9
378 21:58:25.453702 RxClkDly_Margin_A1==98 ps 10
379 21:58:25.454187 TxDqDly_Margin_A1==88 ps 9
380 21:58:25.459453 TrainedVREFDQ_A0==77
381 21:58:25.459954 TrainedVREFDQ_A1==77
382 21:58:25.460431 VrefDac_Margin_A0==22
383 21:58:25.464964 DeviceVref_Margin_A0==37
384 21:58:25.465453 VrefDac_Margin_A1==22
385 21:58:25.470568 DeviceVref_Margin_A1==37
386 21:58:25.471050
387 21:58:25.471495 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 21:58:25.471928
389 21:58:25.504268 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 21:58:25.504898 2D training succeed
391 21:58:25.509786 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 21:58:25.515487 auto size-- 65535DDR cs0 size: 2048MB
393 21:58:25.515972 DDR cs1 size: 2048MB
394 21:58:25.521001 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 21:58:25.521474 cs0 DataBus test pass
396 21:58:25.526616 cs1 DataBus test pass
397 21:58:25.527092 cs0 AddrBus test pass
398 21:58:25.527531 cs1 AddrBus test pass
399 21:58:25.527962
400 21:58:25.532206 100bdlr_step_size ps== 420
401 21:58:25.532678 result report
402 21:58:25.537819 boot times 0Enable ddr reg access
403 21:58:25.543053 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 21:58:25.556609 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 21:58:26.130278 0.0;M3 CHK:0;cm4_sp_mode 0
406 21:58:26.130934 MVN_1=0x00000000
407 21:58:26.135729 MVN_2=0x00000000
408 21:58:26.141548 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 21:58:26.142076 OPS=0x10
410 21:58:26.142529 ring efuse init
411 21:58:26.142968 chipver efuse init
412 21:58:26.149776 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 21:58:26.150299 [0.018961 Inits done]
414 21:58:26.150745 secure task start!
415 21:58:26.157216 high task start!
416 21:58:26.157696 low task start!
417 21:58:26.158134 run into bl31
418 21:58:26.163917 NOTICE: BL31: v1.3(release):4fc40b1
419 21:58:26.171541 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 21:58:26.172041 NOTICE: BL31: G12A normal boot!
421 21:58:26.197105 NOTICE: BL31: BL33 decompress pass
422 21:58:26.202761 ERROR: Error initializing runtime service opteed_fast
423 21:58:27.435671
424 21:58:27.436350
425 21:58:27.443082 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 21:58:27.443572
427 21:58:27.444067 Model: Libre Computer AML-A311D-CC Alta
428 21:58:27.652643 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 21:58:27.675878 DRAM: 2 GiB (effective 3.8 GiB)
430 21:58:27.818815 Core: 408 devices, 31 uclasses, devicetree: separate
431 21:58:27.824697 WDT: Not starting watchdog@f0d0
432 21:58:27.856949 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 21:58:27.869402 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 21:58:27.874366 ** Bad device specification mmc 0 **
435 21:58:27.884747 Card did not respond to voltage select! : -110
436 21:58:27.891586 ** Bad device specification mmc 0 **
437 21:58:27.892115 Couldn't find partition mmc 0
438 21:58:27.900785 Card did not respond to voltage select! : -110
439 21:58:27.906235 ** Bad device specification mmc 0 **
440 21:58:27.906727 Couldn't find partition mmc 0
441 21:58:27.911317 Error: could not access storage.
442 21:58:29.174758 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 21:58:29.175403 bl2_stage_init 0x01
444 21:58:29.175871 bl2_stage_init 0x81
445 21:58:29.180323 hw id: 0x0000 - pwm id 0x01
446 21:58:29.180803 bl2_stage_init 0xc1
447 21:58:29.181253 bl2_stage_init 0x02
448 21:58:29.181696
449 21:58:29.185928 L0:00000000
450 21:58:29.186414 L1:20000703
451 21:58:29.186864 L2:00008067
452 21:58:29.187303 L3:14000000
453 21:58:29.188808 B2:00402000
454 21:58:29.189276 B1:e0f83180
455 21:58:29.189718
456 21:58:29.190158 TE: 58167
457 21:58:29.190604
458 21:58:29.200035 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 21:58:29.200517
460 21:58:29.200969 Board ID = 1
461 21:58:29.201409 Set A53 clk to 24M
462 21:58:29.201846 Set A73 clk to 24M
463 21:58:29.205591 Set clk81 to 24M
464 21:58:29.206059 A53 clk: 1200 MHz
465 21:58:29.206506 A73 clk: 1200 MHz
466 21:58:29.211182 CLK81: 166.6M
467 21:58:29.211648 smccc: 00012abe
468 21:58:29.216943 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 21:58:29.217417 board id: 1
470 21:58:29.225402 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 21:58:29.236118 fw parse done
472 21:58:29.242022 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 21:58:29.284643 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 21:58:29.295572 PIEI prepare done
475 21:58:29.296079 fastboot data load
476 21:58:29.296536 fastboot data verify
477 21:58:29.301278 verify result: 266
478 21:58:29.306793 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 21:58:29.307266 LPDDR4 probe
480 21:58:29.307712 ddr clk to 1584MHz
481 21:58:29.314797 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 21:58:29.352113
483 21:58:29.352597 dmc_version 0001
484 21:58:29.358719 Check phy result
485 21:58:29.364572 INFO : End of CA training
486 21:58:29.365038 INFO : End of initialization
487 21:58:29.370206 INFO : Training has run successfully!
488 21:58:29.370674 Check phy result
489 21:58:29.375813 INFO : End of initialization
490 21:58:29.376315 INFO : End of read enable training
491 21:58:29.381412 INFO : End of fine write leveling
492 21:58:29.387042 INFO : End of Write leveling coarse delay
493 21:58:29.387508 INFO : Training has run successfully!
494 21:58:29.387954 Check phy result
495 21:58:29.392619 INFO : End of initialization
496 21:58:29.393091 INFO : End of read dq deskew training
497 21:58:29.398171 INFO : End of MPR read delay center optimization
498 21:58:29.403788 INFO : End of write delay center optimization
499 21:58:29.409367 INFO : End of read delay center optimization
500 21:58:29.409833 INFO : End of max read latency training
501 21:58:29.415044 INFO : Training has run successfully!
502 21:58:29.415510 1D training succeed
503 21:58:29.424226 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 21:58:29.471772 Check phy result
505 21:58:29.472323 INFO : End of initialization
506 21:58:29.493500 INFO : End of 2D read delay Voltage center optimization
507 21:58:29.513755 INFO : End of 2D read delay Voltage center optimization
508 21:58:29.565800 INFO : End of 2D write delay Voltage center optimization
509 21:58:29.615198 INFO : End of 2D write delay Voltage center optimization
510 21:58:29.620672 INFO : Training has run successfully!
511 21:58:29.621154
512 21:58:29.621606 channel==0
513 21:58:29.626248 RxClkDly_Margin_A0==88 ps 9
514 21:58:29.626719 TxDqDly_Margin_A0==98 ps 10
515 21:58:29.629572 RxClkDly_Margin_A1==88 ps 9
516 21:58:29.630037 TxDqDly_Margin_A1==98 ps 10
517 21:58:29.635209 TrainedVREFDQ_A0==74
518 21:58:29.635678 TrainedVREFDQ_A1==74
519 21:58:29.636161 VrefDac_Margin_A0==25
520 21:58:29.640791 DeviceVref_Margin_A0==40
521 21:58:29.641256 VrefDac_Margin_A1==25
522 21:58:29.646376 DeviceVref_Margin_A1==40
523 21:58:29.646852
524 21:58:29.647300
525 21:58:29.647741 channel==1
526 21:58:29.648218 RxClkDly_Margin_A0==98 ps 10
527 21:58:29.652056 TxDqDly_Margin_A0==98 ps 10
528 21:58:29.652534 RxClkDly_Margin_A1==88 ps 9
529 21:58:29.657562 TxDqDly_Margin_A1==98 ps 10
530 21:58:29.658036 TrainedVREFDQ_A0==77
531 21:58:29.658485 TrainedVREFDQ_A1==77
532 21:58:29.663197 VrefDac_Margin_A0==22
533 21:58:29.663663 DeviceVref_Margin_A0==37
534 21:58:29.668788 VrefDac_Margin_A1==24
535 21:58:29.669254 DeviceVref_Margin_A1==37
536 21:58:29.669698
537 21:58:29.674376 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 21:58:29.674843
539 21:58:29.702401 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
540 21:58:29.708071 2D training succeed
541 21:58:29.713598 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 21:58:29.714079 auto size-- 65535DDR cs0 size: 2048MB
543 21:58:29.719213 DDR cs1 size: 2048MB
544 21:58:29.719685 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 21:58:29.724816 cs0 DataBus test pass
546 21:58:29.725303 cs1 DataBus test pass
547 21:58:29.725757 cs0 AddrBus test pass
548 21:58:29.730363 cs1 AddrBus test pass
549 21:58:29.730836
550 21:58:29.731287 100bdlr_step_size ps== 420
551 21:58:29.731740 result report
552 21:58:29.736083 boot times 0Enable ddr reg access
553 21:58:29.743756 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 21:58:29.756415 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 21:58:30.330922 0.0;M3 CHK:0;cm4_sp_mode 0
556 21:58:30.331531 MVN_1=0x00000000
557 21:58:30.336366 MVN_2=0x00000000
558 21:58:30.342123 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 21:58:30.342633 OPS=0x10
560 21:58:30.343093 ring efuse init
561 21:58:30.343562 chipver efuse init
562 21:58:30.350341 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 21:58:30.350852 [0.018960 Inits done]
564 21:58:30.357905 secure task start!
565 21:58:30.358363 high task start!
566 21:58:30.358789 low task start!
567 21:58:30.359210 run into bl31
568 21:58:30.364546 NOTICE: BL31: v1.3(release):4fc40b1
569 21:58:30.372344 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 21:58:30.372811 NOTICE: BL31: G12A normal boot!
571 21:58:30.397748 NOTICE: BL31: BL33 decompress pass
572 21:58:30.403391 ERROR: Error initializing runtime service opteed_fast
573 21:58:31.636314
574 21:58:31.636944
575 21:58:31.644638 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 21:58:31.645115
577 21:58:31.645551 Model: Libre Computer AML-A311D-CC Alta
578 21:58:31.853041 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 21:58:31.876431 DRAM: 2 GiB (effective 3.8 GiB)
580 21:58:32.019492 Core: 408 devices, 31 uclasses, devicetree: separate
581 21:58:32.025409 WDT: Not starting watchdog@f0d0
582 21:58:32.057524 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 21:58:32.070084 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 21:58:32.075006 ** Bad device specification mmc 0 **
585 21:58:32.085381 Card did not respond to voltage select! : -110
586 21:58:32.093013 ** Bad device specification mmc 0 **
587 21:58:32.093478 Couldn't find partition mmc 0
588 21:58:32.101310 Card did not respond to voltage select! : -110
589 21:58:32.106841 ** Bad device specification mmc 0 **
590 21:58:32.107306 Couldn't find partition mmc 0
591 21:58:32.111882 Error: could not access storage.
592 21:58:32.455511 Net: eth0: ethernet@ff3f0000
593 21:58:32.456138 starting USB...
594 21:58:32.707241 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 21:58:32.707803 Starting the controller
596 21:58:32.714239 USB XHCI 1.10
597 21:58:34.426534 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 21:58:34.427184 bl2_stage_init 0x01
599 21:58:34.427660 bl2_stage_init 0x81
600 21:58:34.432130 hw id: 0x0000 - pwm id 0x01
601 21:58:34.432624 bl2_stage_init 0xc1
602 21:58:34.433082 bl2_stage_init 0x02
603 21:58:34.433532
604 21:58:34.437753 L0:00000000
605 21:58:34.438251 L1:20000703
606 21:58:34.438705 L2:00008067
607 21:58:34.439150 L3:14000000
608 21:58:34.443313 B2:00402000
609 21:58:34.443794 B1:e0f83180
610 21:58:34.444283
611 21:58:34.444741 TE: 58124
612 21:58:34.445188
613 21:58:34.448981 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 21:58:34.449526
615 21:58:34.449982 Board ID = 1
616 21:58:34.454514 Set A53 clk to 24M
617 21:58:34.455047 Set A73 clk to 24M
618 21:58:34.455516 Set clk81 to 24M
619 21:58:34.460170 A53 clk: 1200 MHz
620 21:58:34.460687 A73 clk: 1200 MHz
621 21:58:34.461142 CLK81: 166.6M
622 21:58:34.461701 smccc: 00012a92
623 21:58:34.465766 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 21:58:34.471268 board id: 1
625 21:58:34.476859 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 21:58:34.488026 fw parse done
627 21:58:34.493851 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 21:58:34.535520 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 21:58:34.547292 PIEI prepare done
630 21:58:34.547823 fastboot data load
631 21:58:34.548321 fastboot data verify
632 21:58:34.552924 verify result: 266
633 21:58:34.558482 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 21:58:34.558980 LPDDR4 probe
635 21:58:34.559432 ddr clk to 1584MHz
636 21:58:34.566508 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 21:58:34.603912
638 21:58:34.604468 dmc_version 0001
639 21:58:34.610428 Check phy result
640 21:58:34.616231 INFO : End of CA training
641 21:58:34.616708 INFO : End of initialization
642 21:58:34.622016 INFO : Training has run successfully!
643 21:58:34.622497 Check phy result
644 21:58:34.627550 INFO : End of initialization
645 21:58:34.628060 INFO : End of read enable training
646 21:58:34.633061 INFO : End of fine write leveling
647 21:58:34.638714 INFO : End of Write leveling coarse delay
648 21:58:34.639192 INFO : Training has run successfully!
649 21:58:34.639639 Check phy result
650 21:58:34.644260 INFO : End of initialization
651 21:58:34.644733 INFO : End of read dq deskew training
652 21:58:34.649890 INFO : End of MPR read delay center optimization
653 21:58:34.655477 INFO : End of write delay center optimization
654 21:58:34.661072 INFO : End of read delay center optimization
655 21:58:34.661552 INFO : End of max read latency training
656 21:58:34.666848 INFO : Training has run successfully!
657 21:58:34.667326 1D training succeed
658 21:58:34.675839 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 21:58:34.723477 Check phy result
660 21:58:34.724015 INFO : End of initialization
661 21:58:34.744478 INFO : End of 2D read delay Voltage center optimization
662 21:58:34.765133 INFO : End of 2D read delay Voltage center optimization
663 21:58:34.816801 INFO : End of 2D write delay Voltage center optimization
664 21:58:34.866287 INFO : End of 2D write delay Voltage center optimization
665 21:58:34.871840 INFO : Training has run successfully!
666 21:58:34.872358
667 21:58:34.872813 channel==0
668 21:58:34.877456 RxClkDly_Margin_A0==88 ps 9
669 21:58:34.877932 TxDqDly_Margin_A0==98 ps 10
670 21:58:34.883063 RxClkDly_Margin_A1==88 ps 9
671 21:58:34.883549 TxDqDly_Margin_A1==98 ps 10
672 21:58:34.884037 TrainedVREFDQ_A0==74
673 21:58:34.888758 TrainedVREFDQ_A1==74
674 21:58:34.889234 VrefDac_Margin_A0==25
675 21:58:34.889680 DeviceVref_Margin_A0==40
676 21:58:34.894231 VrefDac_Margin_A1==25
677 21:58:34.894698 DeviceVref_Margin_A1==40
678 21:58:34.895141
679 21:58:34.895580
680 21:58:34.899854 channel==1
681 21:58:34.900363 RxClkDly_Margin_A0==98 ps 10
682 21:58:34.900808 TxDqDly_Margin_A0==88 ps 9
683 21:58:34.905424 RxClkDly_Margin_A1==88 ps 9
684 21:58:34.905897 TxDqDly_Margin_A1==88 ps 9
685 21:58:34.911013 TrainedVREFDQ_A0==77
686 21:58:34.911485 TrainedVREFDQ_A1==77
687 21:58:34.911933 VrefDac_Margin_A0==22
688 21:58:34.916770 DeviceVref_Margin_A0==37
689 21:58:34.917241 VrefDac_Margin_A1==24
690 21:58:34.922231 DeviceVref_Margin_A1==37
691 21:58:34.922706
692 21:58:34.923151 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 21:58:34.923592
694 21:58:34.955832 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000019 00000017 00000017 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
695 21:58:34.956388 2D training succeed
696 21:58:34.961450 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 21:58:34.967049 auto size-- 65535DDR cs0 size: 2048MB
698 21:58:34.967529 DDR cs1 size: 2048MB
699 21:58:34.972617 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 21:58:34.973092 cs0 DataBus test pass
701 21:58:34.978224 cs1 DataBus test pass
702 21:58:34.978701 cs0 AddrBus test pass
703 21:58:34.979150 cs1 AddrBus test pass
704 21:58:34.979589
705 21:58:34.983849 100bdlr_step_size ps== 420
706 21:58:34.984366 result report
707 21:58:34.989452 boot times 0Enable ddr reg access
708 21:58:34.994729 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 21:58:35.008189 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 21:58:35.580244 0.0;M3 CHK:0;cm4_sp_mode 0
711 21:58:35.580818 MVN_1=0x00000000
712 21:58:35.585675 MVN_2=0x00000000
713 21:58:35.591482 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 21:58:35.592065 OPS=0x10
715 21:58:35.592515 ring efuse init
716 21:58:35.592942 chipver efuse init
717 21:58:35.597017 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 21:58:35.602590 [0.018961 Inits done]
719 21:58:35.603053 secure task start!
720 21:58:35.603480 high task start!
721 21:58:35.607172 low task start!
722 21:58:35.607628 run into bl31
723 21:58:35.613812 NOTICE: BL31: v1.3(release):4fc40b1
724 21:58:35.621619 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 21:58:35.622082 NOTICE: BL31: G12A normal boot!
726 21:58:35.646984 NOTICE: BL31: BL33 decompress pass
727 21:58:35.652718 ERROR: Error initializing runtime service opteed_fast
728 21:58:36.885604
729 21:58:36.886208
730 21:58:36.894177 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 21:58:36.894675
732 21:58:36.895100 Model: Libre Computer AML-A311D-CC Alta
733 21:58:37.101608 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 21:58:37.125904 DRAM: 2 GiB (effective 3.8 GiB)
735 21:58:37.268852 Core: 408 devices, 31 uclasses, devicetree: separate
736 21:58:37.274782 WDT: Not starting watchdog@f0d0
737 21:58:37.307024 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 21:58:37.319425 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 21:58:37.324460 ** Bad device specification mmc 0 **
740 21:58:37.334826 Card did not respond to voltage select! : -110
741 21:58:37.342451 ** Bad device specification mmc 0 **
742 21:58:37.342945 Couldn't find partition mmc 0
743 21:58:37.350814 Card did not respond to voltage select! : -110
744 21:58:37.356307 ** Bad device specification mmc 0 **
745 21:58:37.356786 Couldn't find partition mmc 0
746 21:58:37.361406 Error: could not access storage.
747 21:58:37.704872 Net: eth0: ethernet@ff3f0000
748 21:58:37.705489 starting USB...
749 21:58:37.956666 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 21:58:37.957196 Starting the controller
751 21:58:37.962766 USB XHCI 1.10
752 21:58:40.125000 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 21:58:40.125609 bl2_stage_init 0x01
754 21:58:40.126038 bl2_stage_init 0x81
755 21:58:40.130594 hw id: 0x0000 - pwm id 0x01
756 21:58:40.131079 bl2_stage_init 0xc1
757 21:58:40.131495 bl2_stage_init 0x02
758 21:58:40.131897
759 21:58:40.136169 L0:00000000
760 21:58:40.136639 L1:20000703
761 21:58:40.137045 L2:00008067
762 21:58:40.137443 L3:14000000
763 21:58:40.141784 B2:00402000
764 21:58:40.142253 B1:e0f83180
765 21:58:40.142660
766 21:58:40.143065 TE: 58159
767 21:58:40.143461
768 21:58:40.147346 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 21:58:40.147819
770 21:58:40.148266 Board ID = 1
771 21:58:40.152935 Set A53 clk to 24M
772 21:58:40.153402 Set A73 clk to 24M
773 21:58:40.153811 Set clk81 to 24M
774 21:58:40.158556 A53 clk: 1200 MHz
775 21:58:40.159026 A73 clk: 1200 MHz
776 21:58:40.159429 CLK81: 166.6M
777 21:58:40.159825 smccc: 00012ab5
778 21:58:40.164176 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 21:58:40.169803 board id: 1
780 21:58:40.175647 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 21:58:40.186345 fw parse done
782 21:58:40.192244 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 21:58:40.233895 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 21:58:40.245815 PIEI prepare done
785 21:58:40.246289 fastboot data load
786 21:58:40.246704 fastboot data verify
787 21:58:40.251429 verify result: 266
788 21:58:40.257010 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 21:58:40.257479 LPDDR4 probe
790 21:58:40.257888 ddr clk to 1584MHz
791 21:58:40.264614 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 21:58:40.302070
793 21:58:40.302555 dmc_version 0001
794 21:58:40.308085 Check phy result
795 21:58:40.314834 INFO : End of CA training
796 21:58:40.315299 INFO : End of initialization
797 21:58:40.320410 INFO : Training has run successfully!
798 21:58:40.320871 Check phy result
799 21:58:40.326033 INFO : End of initialization
800 21:58:40.326498 INFO : End of read enable training
801 21:58:40.331616 INFO : End of fine write leveling
802 21:58:40.337227 INFO : End of Write leveling coarse delay
803 21:58:40.337688 INFO : Training has run successfully!
804 21:58:40.338101 Check phy result
805 21:58:40.342797 INFO : End of initialization
806 21:58:40.343289 INFO : End of read dq deskew training
807 21:58:40.348458 INFO : End of MPR read delay center optimization
808 21:58:40.354003 INFO : End of write delay center optimization
809 21:58:40.359617 INFO : End of read delay center optimization
810 21:58:40.360129 INFO : End of max read latency training
811 21:58:40.365284 INFO : Training has run successfully!
812 21:58:40.365761 1D training succeed
813 21:58:40.374396 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 21:58:40.421089 Check phy result
815 21:58:40.421580 INFO : End of initialization
816 21:58:40.444245 INFO : End of 2D read delay Voltage center optimization
817 21:58:40.464240 INFO : End of 2D read delay Voltage center optimization
818 21:58:40.516395 INFO : End of 2D write delay Voltage center optimization
819 21:58:40.565581 INFO : End of 2D write delay Voltage center optimization
820 21:58:40.571167 INFO : Training has run successfully!
821 21:58:40.571470
822 21:58:40.571688 channel==0
823 21:58:40.576638 RxClkDly_Margin_A0==88 ps 9
824 21:58:40.576898 TxDqDly_Margin_A0==98 ps 10
825 21:58:40.582350 RxClkDly_Margin_A1==88 ps 9
826 21:58:40.582655 TxDqDly_Margin_A1==88 ps 9
827 21:58:40.582874 TrainedVREFDQ_A0==74
828 21:58:40.588132 TrainedVREFDQ_A1==74
829 21:58:40.588671 VrefDac_Margin_A0==24
830 21:58:40.589096 DeviceVref_Margin_A0==40
831 21:58:40.593653 VrefDac_Margin_A1==24
832 21:58:40.594107 DeviceVref_Margin_A1==40
833 21:58:40.594495
834 21:58:40.594885
835 21:58:40.595273 channel==1
836 21:58:40.599249 RxClkDly_Margin_A0==98 ps 10
837 21:58:40.599706 TxDqDly_Margin_A0==98 ps 10
838 21:58:40.604755 RxClkDly_Margin_A1==98 ps 10
839 21:58:40.605205 TxDqDly_Margin_A1==88 ps 9
840 21:58:40.610398 TrainedVREFDQ_A0==77
841 21:58:40.610848 TrainedVREFDQ_A1==77
842 21:58:40.611239 VrefDac_Margin_A0==22
843 21:58:40.616013 DeviceVref_Margin_A0==37
844 21:58:40.616467 VrefDac_Margin_A1==22
845 21:58:40.621604 DeviceVref_Margin_A1==37
846 21:58:40.622055
847 21:58:40.622444 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 21:58:40.622828
849 21:58:40.655206 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
850 21:58:40.655729 2D training succeed
851 21:58:40.660786 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 21:58:40.666384 auto size-- 65535DDR cs0 size: 2048MB
853 21:58:40.666838 DDR cs1 size: 2048MB
854 21:58:40.671955 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 21:58:40.672435 cs0 DataBus test pass
856 21:58:40.677653 cs1 DataBus test pass
857 21:58:40.678104 cs0 AddrBus test pass
858 21:58:40.678496 cs1 AddrBus test pass
859 21:58:40.678880
860 21:58:40.683166 100bdlr_step_size ps== 420
861 21:58:40.683624 result report
862 21:58:40.688764 boot times 0Enable ddr reg access
863 21:58:40.693253 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 21:58:40.707673 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 21:58:41.279623 0.0;M3 CHK:0;cm4_sp_mode 0
866 21:58:41.280282 MVN_1=0x00000000
867 21:58:41.285139 MVN_2=0x00000000
868 21:58:41.290879 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 21:58:41.291371 OPS=0x10
870 21:58:41.291792 ring efuse init
871 21:58:41.292232 chipver efuse init
872 21:58:41.296487 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 21:58:41.302072 [0.018961 Inits done]
874 21:58:41.302536 secure task start!
875 21:58:41.302942 high task start!
876 21:58:41.306751 low task start!
877 21:58:41.307211 run into bl31
878 21:58:41.313311 NOTICE: BL31: v1.3(release):4fc40b1
879 21:58:41.321142 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 21:58:41.321613 NOTICE: BL31: G12A normal boot!
881 21:58:41.346505 NOTICE: BL31: BL33 decompress pass
882 21:58:41.352202 ERROR: Error initializing runtime service opteed_fast
883 21:58:42.585003
884 21:58:42.585631
885 21:58:42.593476 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 21:58:42.593984
887 21:58:42.594404 Model: Libre Computer AML-A311D-CC Alta
888 21:58:42.801908 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 21:58:42.825199 DRAM: 2 GiB (effective 3.8 GiB)
890 21:58:42.968234 Core: 408 devices, 31 uclasses, devicetree: separate
891 21:58:42.973193 WDT: Not starting watchdog@f0d0
892 21:58:43.006319 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 21:58:43.018838 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 21:58:43.022976 ** Bad device specification mmc 0 **
895 21:58:43.034116 Card did not respond to voltage select! : -110
896 21:58:43.040859 ** Bad device specification mmc 0 **
897 21:58:43.041320 Couldn't find partition mmc 0
898 21:58:43.050124 Card did not respond to voltage select! : -110
899 21:58:43.055641 ** Bad device specification mmc 0 **
900 21:58:43.056142 Couldn't find partition mmc 0
901 21:58:43.059707 Error: could not access storage.
902 21:58:43.402649 Net: eth0: ethernet@ff3f0000
903 21:58:43.403216 starting USB...
904 21:58:43.655012 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 21:58:43.655581 Starting the controller
906 21:58:43.662026 USB XHCI 1.10
907 21:58:45.216233 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 21:58:45.224636 scanning usb for storage devices... 0 Storage Device(s) found
910 21:58:45.276124 Hit any key to stop autoboot: 1
911 21:58:45.277170 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
912 21:58:45.277787 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
913 21:58:45.278269 Setting prompt string to ['=>']
914 21:58:45.278762 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
915 21:58:45.292045 0
916 21:58:45.292951 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 21:58:45.293448 Sending with 10 millisecond of delay
919 21:58:46.428249 => setenv autoload no
920 21:58:46.439042 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
921 21:58:46.443929 setenv autoload no
922 21:58:46.444671 Sending with 10 millisecond of delay
924 21:58:48.241435 => setenv initrd_high 0xffffffff
925 21:58:48.252192 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
926 21:58:48.253035 setenv initrd_high 0xffffffff
927 21:58:48.253746 Sending with 10 millisecond of delay
929 21:58:49.869712 => setenv fdt_high 0xffffffff
930 21:58:49.880477 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
931 21:58:49.881292 setenv fdt_high 0xffffffff
932 21:58:49.881995 Sending with 10 millisecond of delay
934 21:58:50.173787 => dhcp
935 21:58:50.184531 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
936 21:58:50.185354 dhcp
937 21:58:50.185783 Speed: 1000, full duplex
938 21:58:50.186193 BOOTP broadcast 1
939 21:58:50.196088 DHCP client bound to address 192.168.6.27 (11 ms)
940 21:58:50.196831 Sending with 10 millisecond of delay
942 21:58:51.873346 => setenv serverip 192.168.6.2
943 21:58:51.884140 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
944 21:58:51.885016 setenv serverip 192.168.6.2
945 21:58:51.885703 Sending with 10 millisecond of delay
947 21:58:55.614371 => tftpboot 0x01080000 949264/tftp-deploy-_nq3udz9/kernel/uImage
948 21:58:55.624968 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
949 21:58:55.625523 tftpboot 0x 01080000 949264/tftp-deploy-_nq3udz9/kernel/uImage
950 21:58:55.625782 Speed: 1000, full duplex
951 21:58:55.626009 Using ethernet@ff3f0000 device
952 21:58:55.627604 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
953 21:58:55.633093 Filename '949264/tftp-deploy-_nq3udz9/kernel/uImage'.
954 21:58:55.636953 Load address: 0x1080000
955 21:58:58.600404 Loading: *################################################## 43.6 MiB
956 21:58:58.601095 14.7 MiB/s
957 21:58:58.601575 done
958 21:58:58.604504 Bytes transferred = 45713984 (2b98a40 hex)
959 21:58:58.605391 Sending with 10 millisecond of delay
961 21:59:03.293281 => tftpboot 0x08000000 949264/tftp-deploy-_nq3udz9/ramdisk/ramdisk.cpio.gz.uboot
962 21:59:03.304099 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
963 21:59:03.304981 tftpboot 0x08000000 949264/tftp-deploy-_nq3udz9/ramdisk/ramdisk.cpio.gz.uboot
964 21:59:03.305469 Speed: 1000, full duplex
965 21:59:03.305928 Using ethernet@ff3f0000 device
966 21:59:03.306974 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
967 21:59:03.315594 Filename '949264/tftp-deploy-_nq3udz9/ramdisk/ramdisk.cpio.gz.uboot'.
968 21:59:03.316175 Load address: 0x8000000
969 21:59:09.196278 Loading: *###############T ###### UDP wrong checksum 00000005 0000d538
970 21:59:10.640500 ############################ UDP wrong checksum 00000005 00003c72
971 21:59:15.639846 T UDP wrong checksum 00000005 00003c72
972 21:59:25.644097 T T UDP wrong checksum 00000005 00003c72
973 21:59:37.743004 T T UDP wrong checksum 000000ff 00008489
974 21:59:37.756530 UDP wrong checksum 000000ff 00000d7c
975 21:59:45.647950 T T UDP wrong checksum 00000005 00003c72
976 22:00:00.652066 T T
977 22:00:00.652440 Retry count exceeded; starting again
979 22:00:00.653312 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
982 22:00:00.654298 end: 2.4 uboot-commands (duration 00:01:47) [common]
984 22:00:00.655058 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
986 22:00:00.655817 end: 2 uboot-action (duration 00:01:47) [common]
988 22:00:00.657489 Cleaning after the job
989 22:00:00.658031 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949264/tftp-deploy-_nq3udz9/ramdisk
990 22:00:00.659483 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949264/tftp-deploy-_nq3udz9/kernel
991 22:00:00.706081 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949264/tftp-deploy-_nq3udz9/dtb
992 22:00:00.706951 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949264/tftp-deploy-_nq3udz9/modules
993 22:00:00.726924 start: 4.1 power-off (timeout 00:00:30) [common]
994 22:00:00.727562 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
995 22:00:00.760316 >> OK - accepted request
996 22:00:00.762597 Returned 0 in 0 seconds
997 22:00:00.863412 end: 4.1 power-off (duration 00:00:00) [common]
999 22:00:00.865078 start: 4.2 read-feedback (timeout 00:10:00) [common]
1000 22:00:00.866199 Listened to connection for namespace 'common' for up to 1s
1001 22:00:01.867020 Finalising connection for namespace 'common'
1002 22:00:01.867747 Disconnecting from shell: Finalise
1003 22:00:01.868326 =>
1004 22:00:01.969311 end: 4.2 read-feedback (duration 00:00:01) [common]
1005 22:00:01.970006 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949264
1006 22:00:02.286505 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949264
1007 22:00:02.287106 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.