Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:48:19.663578 lava-dispatcher, installed at version: 2024.01
2 23:48:19.664408 start: 0 validate
3 23:48:19.664885 Start time: 2024-11-06 23:48:19.664854+00:00 (UTC)
4 23:48:19.665450 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:48:19.665987 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:48:19.703539 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:48:19.704125 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:48:19.738754 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:48:19.739437 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 23:48:19.766984 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:48:19.767477 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 23:48:19.802539 validate duration: 0.14
14 23:48:19.803419 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:48:19.803764 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:48:19.804104 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:48:19.804720 Not decompressing ramdisk as can be used compressed.
18 23:48:19.805160 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 23:48:19.805437 saving as /var/lib/lava/dispatcher/tmp/949202/tftp-deploy-0hwv2rmv/ramdisk/rootfs.cpio.gz
20 23:48:19.805715 total size: 47897469 (45 MB)
21 23:48:19.837175 progress 0 % (0 MB)
22 23:48:19.867579 progress 5 % (2 MB)
23 23:48:19.897285 progress 10 % (4 MB)
24 23:48:19.926939 progress 15 % (6 MB)
25 23:48:19.956398 progress 20 % (9 MB)
26 23:48:19.985565 progress 25 % (11 MB)
27 23:48:20.014840 progress 30 % (13 MB)
28 23:48:20.044097 progress 35 % (16 MB)
29 23:48:20.073284 progress 40 % (18 MB)
30 23:48:20.102502 progress 45 % (20 MB)
31 23:48:20.131671 progress 50 % (22 MB)
32 23:48:20.160846 progress 55 % (25 MB)
33 23:48:20.190332 progress 60 % (27 MB)
34 23:48:20.219436 progress 65 % (29 MB)
35 23:48:20.248618 progress 70 % (32 MB)
36 23:48:20.277710 progress 75 % (34 MB)
37 23:48:20.306634 progress 80 % (36 MB)
38 23:48:20.335905 progress 85 % (38 MB)
39 23:48:20.365011 progress 90 % (41 MB)
40 23:48:20.393932 progress 95 % (43 MB)
41 23:48:20.421854 progress 100 % (45 MB)
42 23:48:20.422614 45 MB downloaded in 0.62 s (74.05 MB/s)
43 23:48:20.423190 end: 1.1.1 http-download (duration 00:00:01) [common]
45 23:48:20.424133 end: 1.1 download-retry (duration 00:00:01) [common]
46 23:48:20.424450 start: 1.2 download-retry (timeout 00:09:59) [common]
47 23:48:20.424742 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 23:48:20.425226 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/kernel/Image
49 23:48:20.425480 saving as /var/lib/lava/dispatcher/tmp/949202/tftp-deploy-0hwv2rmv/kernel/Image
50 23:48:20.425694 total size: 45713920 (43 MB)
51 23:48:20.425911 No compression specified
52 23:48:20.461588 progress 0 % (0 MB)
53 23:48:20.489524 progress 5 % (2 MB)
54 23:48:20.517792 progress 10 % (4 MB)
55 23:48:20.545685 progress 15 % (6 MB)
56 23:48:20.573549 progress 20 % (8 MB)
57 23:48:20.600956 progress 25 % (10 MB)
58 23:48:20.628938 progress 30 % (13 MB)
59 23:48:20.656996 progress 35 % (15 MB)
60 23:48:20.684969 progress 40 % (17 MB)
61 23:48:20.712195 progress 45 % (19 MB)
62 23:48:20.740163 progress 50 % (21 MB)
63 23:48:20.767845 progress 55 % (24 MB)
64 23:48:20.795472 progress 60 % (26 MB)
65 23:48:20.823014 progress 65 % (28 MB)
66 23:48:20.850891 progress 70 % (30 MB)
67 23:48:20.881256 progress 75 % (32 MB)
68 23:48:20.909215 progress 80 % (34 MB)
69 23:48:20.936612 progress 85 % (37 MB)
70 23:48:20.964406 progress 90 % (39 MB)
71 23:48:20.992249 progress 95 % (41 MB)
72 23:48:21.018915 progress 100 % (43 MB)
73 23:48:21.019441 43 MB downloaded in 0.59 s (73.43 MB/s)
74 23:48:21.019919 end: 1.2.1 http-download (duration 00:00:01) [common]
76 23:48:21.020758 end: 1.2 download-retry (duration 00:00:01) [common]
77 23:48:21.021035 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:48:21.021299 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:48:21.021756 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 23:48:21.022029 saving as /var/lib/lava/dispatcher/tmp/949202/tftp-deploy-0hwv2rmv/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 23:48:21.022236 total size: 53209 (0 MB)
82 23:48:21.022445 No compression specified
83 23:48:21.066343 progress 61 % (0 MB)
84 23:48:21.067179 progress 100 % (0 MB)
85 23:48:21.067717 0 MB downloaded in 0.05 s (1.12 MB/s)
86 23:48:21.068203 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:48:21.069015 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:48:21.069276 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:48:21.069539 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:48:21.069990 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/modules.tar.xz
92 23:48:21.070231 saving as /var/lib/lava/dispatcher/tmp/949202/tftp-deploy-0hwv2rmv/modules/modules.tar
93 23:48:21.070435 total size: 11608172 (11 MB)
94 23:48:21.070644 Using unxz to decompress xz
95 23:48:21.109565 progress 0 % (0 MB)
96 23:48:21.190965 progress 5 % (0 MB)
97 23:48:21.282489 progress 10 % (1 MB)
98 23:48:21.379342 progress 15 % (1 MB)
99 23:48:21.471039 progress 20 % (2 MB)
100 23:48:21.549845 progress 25 % (2 MB)
101 23:48:21.630717 progress 30 % (3 MB)
102 23:48:21.704946 progress 35 % (3 MB)
103 23:48:21.782089 progress 40 % (4 MB)
104 23:48:21.858206 progress 45 % (5 MB)
105 23:48:21.942357 progress 50 % (5 MB)
106 23:48:22.019610 progress 55 % (6 MB)
107 23:48:22.104417 progress 60 % (6 MB)
108 23:48:22.185316 progress 65 % (7 MB)
109 23:48:22.262487 progress 70 % (7 MB)
110 23:48:22.344916 progress 75 % (8 MB)
111 23:48:22.428753 progress 80 % (8 MB)
112 23:48:22.509060 progress 85 % (9 MB)
113 23:48:22.587885 progress 90 % (9 MB)
114 23:48:22.666602 progress 95 % (10 MB)
115 23:48:22.744545 progress 100 % (11 MB)
116 23:48:22.755550 11 MB downloaded in 1.69 s (6.57 MB/s)
117 23:48:22.756291 end: 1.4.1 http-download (duration 00:00:02) [common]
119 23:48:22.757908 end: 1.4 download-retry (duration 00:00:02) [common]
120 23:48:22.758428 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 23:48:22.758941 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 23:48:22.759426 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:48:22.759922 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 23:48:22.760931 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9
125 23:48:22.761742 makedir: /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin
126 23:48:22.762365 makedir: /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/tests
127 23:48:22.762983 makedir: /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/results
128 23:48:22.763621 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-add-keys
129 23:48:22.764650 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-add-sources
130 23:48:22.765594 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-background-process-start
131 23:48:22.766521 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-background-process-stop
132 23:48:22.767490 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-common-functions
133 23:48:22.768427 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-echo-ipv4
134 23:48:22.769322 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-install-packages
135 23:48:22.770234 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-installed-packages
136 23:48:22.771111 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-os-build
137 23:48:22.772010 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-probe-channel
138 23:48:22.772901 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-probe-ip
139 23:48:22.773799 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-target-ip
140 23:48:22.774670 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-target-mac
141 23:48:22.775559 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-target-storage
142 23:48:22.776497 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-test-case
143 23:48:22.777412 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-test-event
144 23:48:22.778297 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-test-feedback
145 23:48:22.779172 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-test-raise
146 23:48:22.780096 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-test-reference
147 23:48:22.781021 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-test-runner
148 23:48:22.781916 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-test-set
149 23:48:22.782790 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-test-shell
150 23:48:22.783676 Updating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-install-packages (oe)
151 23:48:22.784678 Updating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/bin/lava-installed-packages (oe)
152 23:48:22.785489 Creating /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/environment
153 23:48:22.786188 LAVA metadata
154 23:48:22.786662 - LAVA_JOB_ID=949202
155 23:48:22.787084 - LAVA_DISPATCHER_IP=192.168.6.2
156 23:48:22.787737 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 23:48:22.789656 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 23:48:22.790263 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 23:48:22.790675 skipped lava-vland-overlay
160 23:48:22.791159 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 23:48:22.791662 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 23:48:22.792120 skipped lava-multinode-overlay
163 23:48:22.792606 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 23:48:22.793101 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 23:48:22.793577 Loading test definitions
166 23:48:22.794117 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 23:48:22.794553 Using /lava-949202 at stage 0
168 23:48:22.796432 uuid=949202_1.5.2.4.1 testdef=None
169 23:48:22.796752 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 23:48:22.797035 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 23:48:22.798904 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 23:48:22.799716 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 23:48:22.801923 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 23:48:22.802787 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 23:48:22.804922 runner path: /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/0/tests/0_igt-gpu-panfrost test_uuid 949202_1.5.2.4.1
178 23:48:22.805512 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 23:48:22.806323 Creating lava-test-runner.conf files
181 23:48:22.806529 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949202/lava-overlay-i19_utn9/lava-949202/0 for stage 0
182 23:48:22.806883 - 0_igt-gpu-panfrost
183 23:48:22.807261 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 23:48:22.807546 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 23:48:22.831023 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 23:48:22.831444 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 23:48:22.831711 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 23:48:22.831999 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 23:48:22.832271 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 23:48:29.998491 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 23:48:29.998970 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 23:48:29.999221 extracting modules file /var/lib/lava/dispatcher/tmp/949202/tftp-deploy-0hwv2rmv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949202/extract-overlay-ramdisk-viho4lb0/ramdisk
193 23:48:31.436151 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 23:48:31.436632 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 23:48:31.436913 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949202/compress-overlay-aduxnh_t/overlay-1.5.2.5.tar.gz to ramdisk
196 23:48:31.437129 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949202/compress-overlay-aduxnh_t/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949202/extract-overlay-ramdisk-viho4lb0/ramdisk
197 23:48:31.467450 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 23:48:31.467865 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 23:48:31.468162 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 23:48:31.468393 Converting downloaded kernel to a uImage
201 23:48:31.468695 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949202/tftp-deploy-0hwv2rmv/kernel/Image /var/lib/lava/dispatcher/tmp/949202/tftp-deploy-0hwv2rmv/kernel/uImage
202 23:48:31.946613 output: Image Name:
203 23:48:31.947031 output: Created: Wed Nov 6 23:48:31 2024
204 23:48:31.947241 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 23:48:31.947446 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 23:48:31.947648 output: Load Address: 01080000
207 23:48:31.947849 output: Entry Point: 01080000
208 23:48:31.948088 output:
209 23:48:31.948424 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 23:48:31.948689 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 23:48:31.948958 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 23:48:31.949212 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 23:48:31.949470 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 23:48:31.949722 Building ramdisk /var/lib/lava/dispatcher/tmp/949202/extract-overlay-ramdisk-viho4lb0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949202/extract-overlay-ramdisk-viho4lb0/ramdisk
215 23:48:39.108337 >> 502412 blocks
216 23:49:00.219891 Adding RAMdisk u-boot header.
217 23:49:00.220589 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949202/extract-overlay-ramdisk-viho4lb0/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949202/extract-overlay-ramdisk-viho4lb0/ramdisk.cpio.gz.uboot
218 23:49:00.900091 output: Image Name:
219 23:49:00.900709 output: Created: Wed Nov 6 23:49:00 2024
220 23:49:00.901119 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 23:49:00.901518 output: Data Size: 65712509 Bytes = 64172.37 KiB = 62.67 MiB
222 23:49:00.901914 output: Load Address: 00000000
223 23:49:00.902306 output: Entry Point: 00000000
224 23:49:00.902698 output:
225 23:49:00.903782 rename /var/lib/lava/dispatcher/tmp/949202/extract-overlay-ramdisk-viho4lb0/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949202/tftp-deploy-0hwv2rmv/ramdisk/ramdisk.cpio.gz.uboot
226 23:49:00.904535 end: 1.5.8 compress-ramdisk (duration 00:00:29) [common]
227 23:49:00.905089 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 23:49:00.905619 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 23:49:00.906071 No LXC device requested
230 23:49:00.906578 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 23:49:00.907085 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 23:49:00.907581 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 23:49:00.908012 Checking files for TFTP limit of 4294967296 bytes.
234 23:49:00.910679 end: 1 tftp-deploy (duration 00:00:41) [common]
235 23:49:00.911261 start: 2 uboot-action (timeout 00:05:00) [common]
236 23:49:00.911790 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 23:49:00.912335 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 23:49:00.912846 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 23:49:00.913380 Using kernel file from prepare-kernel: 949202/tftp-deploy-0hwv2rmv/kernel/uImage
240 23:49:00.914012 substitutions:
241 23:49:00.914433 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 23:49:00.914839 - {DTB_ADDR}: 0x01070000
243 23:49:00.915241 - {DTB}: 949202/tftp-deploy-0hwv2rmv/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 23:49:00.915641 - {INITRD}: 949202/tftp-deploy-0hwv2rmv/ramdisk/ramdisk.cpio.gz.uboot
245 23:49:00.916066 - {KERNEL_ADDR}: 0x01080000
246 23:49:00.916468 - {KERNEL}: 949202/tftp-deploy-0hwv2rmv/kernel/uImage
247 23:49:00.916885 - {LAVA_MAC}: None
248 23:49:00.917329 - {PRESEED_CONFIG}: None
249 23:49:00.917733 - {PRESEED_LOCAL}: None
250 23:49:00.918129 - {RAMDISK_ADDR}: 0x08000000
251 23:49:00.918518 - {RAMDISK}: 949202/tftp-deploy-0hwv2rmv/ramdisk/ramdisk.cpio.gz.uboot
252 23:49:00.918913 - {ROOT_PART}: None
253 23:49:00.919302 - {ROOT}: None
254 23:49:00.919694 - {SERVER_IP}: 192.168.6.2
255 23:49:00.920118 - {TEE_ADDR}: 0x83000000
256 23:49:00.920519 - {TEE}: None
257 23:49:00.920910 Parsed boot commands:
258 23:49:00.921291 - setenv autoload no
259 23:49:00.921681 - setenv initrd_high 0xffffffff
260 23:49:00.922071 - setenv fdt_high 0xffffffff
261 23:49:00.922455 - dhcp
262 23:49:00.922841 - setenv serverip 192.168.6.2
263 23:49:00.923229 - tftpboot 0x01080000 949202/tftp-deploy-0hwv2rmv/kernel/uImage
264 23:49:00.923616 - tftpboot 0x08000000 949202/tftp-deploy-0hwv2rmv/ramdisk/ramdisk.cpio.gz.uboot
265 23:49:00.924030 - tftpboot 0x01070000 949202/tftp-deploy-0hwv2rmv/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 23:49:00.924430 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 23:49:00.924828 - bootm 0x01080000 0x08000000 0x01070000
268 23:49:00.925338 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 23:49:00.926872 start: 2.3 connect-device (timeout 00:05:00) [common]
271 23:49:00.927321 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 23:49:00.942679 Setting prompt string to ['lava-test: # ']
273 23:49:00.944196 end: 2.3 connect-device (duration 00:00:00) [common]
274 23:49:00.944801 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 23:49:00.945354 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 23:49:00.945883 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 23:49:00.947026 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 23:49:00.982762 >> OK - accepted request
279 23:49:00.985139 Returned 0 in 0 seconds
280 23:49:01.086219 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 23:49:01.087820 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 23:49:01.088462 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 23:49:01.088971 Setting prompt string to ['Hit any key to stop autoboot']
285 23:49:01.089423 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 23:49:01.091004 Trying 192.168.56.21...
287 23:49:01.091487 Connected to conserv1.
288 23:49:01.091940 Escape character is '^]'.
289 23:49:01.092414
290 23:49:01.092870 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 23:49:01.093332
292 23:49:08.401586 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 23:49:08.402211 bl2_stage_init 0x01
294 23:49:08.402657 bl2_stage_init 0x81
295 23:49:08.407246 hw id: 0x0000 - pwm id 0x01
296 23:49:08.407705 bl2_stage_init 0xc1
297 23:49:08.412865 bl2_stage_init 0x02
298 23:49:08.413307
299 23:49:08.413720 L0:00000000
300 23:49:08.414119 L1:00000703
301 23:49:08.414515 L2:00008067
302 23:49:08.414910 L3:15000000
303 23:49:08.418321 S1:00000000
304 23:49:08.418750 B2:20282000
305 23:49:08.419150 B1:a0f83180
306 23:49:08.419543
307 23:49:08.419935 TE: 71226
308 23:49:08.420379
309 23:49:08.423941 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 23:49:08.424397
311 23:49:08.429545 Board ID = 1
312 23:49:08.429965 Set cpu clk to 24M
313 23:49:08.430365 Set clk81 to 24M
314 23:49:08.435193 Use GP1_pll as DSU clk.
315 23:49:08.435632 DSU clk: 1200 Mhz
316 23:49:08.436066 CPU clk: 1200 MHz
317 23:49:08.440801 Set clk81 to 166.6M
318 23:49:08.446227 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 23:49:08.446664 board id: 1
320 23:49:08.452789 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 23:49:08.464329 fw parse done
322 23:49:08.469544 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 23:49:08.512778 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 23:49:08.524582 PIEI prepare done
325 23:49:08.525011 fastboot data load
326 23:49:08.525420 fastboot data verify
327 23:49:08.530221 verify result: 266
328 23:49:08.535785 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 23:49:08.536267 LPDDR4 probe
330 23:49:08.536668 ddr clk to 1584MHz
331 23:49:08.542995 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 23:49:08.581529
333 23:49:08.582057 dmc_version 0001
334 23:49:08.588243 Check phy result
335 23:49:08.594591 INFO : End of CA training
336 23:49:08.595025 INFO : End of initialization
337 23:49:08.600211 INFO : Training has run successfully!
338 23:49:08.600641 Check phy result
339 23:49:08.605737 INFO : End of initialization
340 23:49:08.606159 INFO : End of read enable training
341 23:49:08.611325 INFO : End of fine write leveling
342 23:49:08.617031 INFO : End of Write leveling coarse delay
343 23:49:08.617457 INFO : Training has run successfully!
344 23:49:08.617860 Check phy result
345 23:49:08.622566 INFO : End of initialization
346 23:49:08.622993 INFO : End of read dq deskew training
347 23:49:08.628283 INFO : End of MPR read delay center optimization
348 23:49:08.633811 INFO : End of write delay center optimization
349 23:49:08.639360 INFO : End of read delay center optimization
350 23:49:08.639803 INFO : End of max read latency training
351 23:49:08.644958 INFO : Training has run successfully!
352 23:49:08.645390 1D training succeed
353 23:49:08.653934 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 23:49:08.701648 Check phy result
355 23:49:08.702118 INFO : End of initialization
356 23:49:08.729240 INFO : End of 2D read delay Voltage center optimization
357 23:49:08.753166 INFO : End of 2D read delay Voltage center optimization
358 23:49:08.810391 INFO : End of 2D write delay Voltage center optimization
359 23:49:08.864501 INFO : End of 2D write delay Voltage center optimization
360 23:49:08.870005 INFO : Training has run successfully!
361 23:49:08.870436
362 23:49:08.870846 channel==0
363 23:49:08.875618 RxClkDly_Margin_A0==78 ps 8
364 23:49:08.876098 TxDqDly_Margin_A0==98 ps 10
365 23:49:08.881223 RxClkDly_Margin_A1==88 ps 9
366 23:49:08.881643 TxDqDly_Margin_A1==88 ps 9
367 23:49:08.882046 TrainedVREFDQ_A0==74
368 23:49:08.886823 TrainedVREFDQ_A1==75
369 23:49:08.887251 VrefDac_Margin_A0==24
370 23:49:08.887647 DeviceVref_Margin_A0==40
371 23:49:08.892460 VrefDac_Margin_A1==23
372 23:49:08.892890 DeviceVref_Margin_A1==39
373 23:49:08.893286
374 23:49:08.893682
375 23:49:08.894078 channel==1
376 23:49:08.898033 RxClkDly_Margin_A0==88 ps 9
377 23:49:08.898460 TxDqDly_Margin_A0==98 ps 10
378 23:49:08.903589 RxClkDly_Margin_A1==78 ps 8
379 23:49:08.904058 TxDqDly_Margin_A1==78 ps 8
380 23:49:08.909213 TrainedVREFDQ_A0==78
381 23:49:08.909658 TrainedVREFDQ_A1==75
382 23:49:08.910061 VrefDac_Margin_A0==22
383 23:49:08.914868 DeviceVref_Margin_A0==36
384 23:49:08.915290 VrefDac_Margin_A1==22
385 23:49:08.920452 DeviceVref_Margin_A1==39
386 23:49:08.920884
387 23:49:08.921287 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 23:49:08.921684
389 23:49:08.954042 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000018 00000018 00000017 00000017 00000018 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 23:49:08.954621 2D training succeed
391 23:49:08.959582 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 23:49:08.965268 auto size-- 65535DDR cs0 size: 2048MB
393 23:49:08.965711 DDR cs1 size: 2048MB
394 23:49:08.970828 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 23:49:08.971258 cs0 DataBus test pass
396 23:49:08.976412 cs1 DataBus test pass
397 23:49:08.976852 cs0 AddrBus test pass
398 23:49:08.977253 cs1 AddrBus test pass
399 23:49:08.977647
400 23:49:08.981973 100bdlr_step_size ps== 471
401 23:49:08.982413 result report
402 23:49:08.987668 boot times 0Enable ddr reg access
403 23:49:08.992296 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 23:49:09.006396 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 23:49:09.664654 bl2z: ptr: 05129330, size: 00001e40
406 23:49:09.673768 0.0;M3 CHK:0;cm4_sp_mode 0
407 23:49:09.674300 MVN_1=0x00000000
408 23:49:09.674710 MVN_2=0x00000000
409 23:49:09.685229 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 23:49:09.685682 OPS=0x04
411 23:49:09.686093 ring efuse init
412 23:49:09.690851 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 23:49:09.691300 [0.017354 Inits done]
414 23:49:09.691698 secure task start!
415 23:49:09.698719 high task start!
416 23:49:09.699154 low task start!
417 23:49:09.699556 run into bl31
418 23:49:09.707217 NOTICE: BL31: v1.3(release):4fc40b1
419 23:49:09.714566 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 23:49:09.715012 NOTICE: BL31: G12A normal boot!
421 23:49:09.730586 NOTICE: BL31: BL33 decompress pass
422 23:49:09.736198 ERROR: Error initializing runtime service opteed_fast
423 23:49:12.450312 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 23:49:12.450722 bl2_stage_init 0x01
425 23:49:12.450932 bl2_stage_init 0x81
426 23:49:12.455804 hw id: 0x0000 - pwm id 0x01
427 23:49:12.456114 bl2_stage_init 0xc1
428 23:49:12.461413 bl2_stage_init 0x02
429 23:49:12.461699
430 23:49:12.461903 L0:00000000
431 23:49:12.462100 L1:00000703
432 23:49:12.462293 L2:00008067
433 23:49:12.462485 L3:15000000
434 23:49:12.467001 S1:00000000
435 23:49:12.467273 B2:20282000
436 23:49:12.467473 B1:a0f83180
437 23:49:12.467668
438 23:49:12.467864 TE: 70153
439 23:49:12.468225
440 23:49:12.472743 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 23:49:12.473284
442 23:49:12.478382 Board ID = 1
443 23:49:12.478902 Set cpu clk to 24M
444 23:49:12.479335 Set clk81 to 24M
445 23:49:12.483938 Use GP1_pll as DSU clk.
446 23:49:12.484491 DSU clk: 1200 Mhz
447 23:49:12.484926 CPU clk: 1200 MHz
448 23:49:12.489493 Set clk81 to 166.6M
449 23:49:12.495106 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 23:49:12.495636 board id: 1
451 23:49:12.502322 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 23:49:12.513289 fw parse done
453 23:49:12.519191 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 23:49:12.561390 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 23:49:12.573434 PIEI prepare done
456 23:49:12.573984 fastboot data load
457 23:49:12.574423 fastboot data verify
458 23:49:12.579038 verify result: 266
459 23:49:12.584601 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 23:49:12.585126 LPDDR4 probe
461 23:49:12.585560 ddr clk to 1584MHz
462 23:49:12.592610 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 23:49:12.630376
464 23:49:12.630939 dmc_version 0001
465 23:49:12.637386 Check phy result
466 23:49:12.643377 INFO : End of CA training
467 23:49:12.643904 INFO : End of initialization
468 23:49:12.648982 INFO : Training has run successfully!
469 23:49:12.649516 Check phy result
470 23:49:12.654564 INFO : End of initialization
471 23:49:12.655096 INFO : End of read enable training
472 23:49:12.660178 INFO : End of fine write leveling
473 23:49:12.665810 INFO : End of Write leveling coarse delay
474 23:49:12.666345 INFO : Training has run successfully!
475 23:49:12.666801 Check phy result
476 23:49:12.671354 INFO : End of initialization
477 23:49:12.671887 INFO : End of read dq deskew training
478 23:49:12.676961 INFO : End of MPR read delay center optimization
479 23:49:12.682587 INFO : End of write delay center optimization
480 23:49:12.688152 INFO : End of read delay center optimization
481 23:49:12.688678 INFO : End of max read latency training
482 23:49:12.693818 INFO : Training has run successfully!
483 23:49:12.694353 1D training succeed
484 23:49:12.702906 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 23:49:12.751218 Check phy result
486 23:49:12.751787 INFO : End of initialization
487 23:49:12.778553 INFO : End of 2D read delay Voltage center optimization
488 23:49:12.801958 INFO : End of 2D read delay Voltage center optimization
489 23:49:12.859441 INFO : End of 2D write delay Voltage center optimization
490 23:49:12.913446 INFO : End of 2D write delay Voltage center optimization
491 23:49:12.919058 INFO : Training has run successfully!
492 23:49:12.919584
493 23:49:12.920083 channel==0
494 23:49:12.924660 RxClkDly_Margin_A0==78 ps 8
495 23:49:12.925194 TxDqDly_Margin_A0==98 ps 10
496 23:49:12.928015 RxClkDly_Margin_A1==88 ps 9
497 23:49:12.928543 TxDqDly_Margin_A1==98 ps 10
498 23:49:12.933616 TrainedVREFDQ_A0==74
499 23:49:12.934149 TrainedVREFDQ_A1==75
500 23:49:12.934612 VrefDac_Margin_A0==23
501 23:49:12.939170 DeviceVref_Margin_A0==40
502 23:49:12.939695 VrefDac_Margin_A1==22
503 23:49:12.944828 DeviceVref_Margin_A1==39
504 23:49:12.945359
505 23:49:12.945816
506 23:49:12.946260 channel==1
507 23:49:12.946698 RxClkDly_Margin_A0==88 ps 9
508 23:49:12.950367 TxDqDly_Margin_A0==88 ps 9
509 23:49:12.950900 RxClkDly_Margin_A1==78 ps 8
510 23:49:12.956063 TxDqDly_Margin_A1==88 ps 9
511 23:49:12.956602 TrainedVREFDQ_A0==77
512 23:49:12.957063 TrainedVREFDQ_A1==77
513 23:49:12.961585 VrefDac_Margin_A0==22
514 23:49:12.962114 DeviceVref_Margin_A0==37
515 23:49:12.967177 VrefDac_Margin_A1==22
516 23:49:12.967703 DeviceVref_Margin_A1==37
517 23:49:12.968214
518 23:49:12.972860 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 23:49:12.973391
520 23:49:13.000797 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 23:49:13.006342 2D training succeed
522 23:49:13.011969 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 23:49:13.012545 auto size-- 65535DDR cs0 size: 2048MB
524 23:49:13.017618 DDR cs1 size: 2048MB
525 23:49:13.018145 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 23:49:13.023182 cs0 DataBus test pass
527 23:49:13.023708 cs1 DataBus test pass
528 23:49:13.024204 cs0 AddrBus test pass
529 23:49:13.028867 cs1 AddrBus test pass
530 23:49:13.029397
531 23:49:13.029858 100bdlr_step_size ps== 471
532 23:49:13.030316 result report
533 23:49:13.034370 boot times 0Enable ddr reg access
534 23:49:13.041913 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 23:49:13.054779 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 23:49:13.716866 bl2z: ptr: 05129330, size: 00001e40
537 23:49:13.725140 0.0;M3 CHK:0;cm4_sp_mode 0
538 23:49:13.725700 MVN_1=0x00000000
539 23:49:13.726163 MVN_2=0x00000000
540 23:49:13.736436 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 23:49:13.736984 OPS=0x04
542 23:49:13.737451 ring efuse init
543 23:49:13.742250 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 23:49:13.742793 [0.017354 Inits done]
545 23:49:13.743251 secure task start!
546 23:49:13.749488 high task start!
547 23:49:13.750019 low task start!
548 23:49:13.750476 run into bl31
549 23:49:13.758071 NOTICE: BL31: v1.3(release):4fc40b1
550 23:49:13.765812 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 23:49:13.766351 NOTICE: BL31: G12A normal boot!
552 23:49:13.781443 NOTICE: BL31: BL33 decompress pass
553 23:49:13.787130 ERROR: Error initializing runtime service opteed_fast
554 23:49:15.150442 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 23:49:15.151096 bl2_stage_init 0x01
556 23:49:15.151595 bl2_stage_init 0x81
557 23:49:15.155859 hw id: 0x0000 - pwm id 0x01
558 23:49:15.156427 bl2_stage_init 0xc1
559 23:49:15.160039 bl2_stage_init 0x02
560 23:49:15.160571
561 23:49:15.161046 L0:00000000
562 23:49:15.161504 L1:00000703
563 23:49:15.165670 L2:00008067
564 23:49:15.166205 L3:15000000
565 23:49:15.166658 S1:00000000
566 23:49:15.167122 B2:20282000
567 23:49:15.167567 B1:a0f83180
568 23:49:15.168054
569 23:49:15.171159 TE: 69717
570 23:49:15.171699
571 23:49:15.176725 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 23:49:15.177278
573 23:49:15.177777 Board ID = 1
574 23:49:15.178251 Set cpu clk to 24M
575 23:49:15.180277 Set clk81 to 24M
576 23:49:15.180823 Use GP1_pll as DSU clk.
577 23:49:15.185725 DSU clk: 1200 Mhz
578 23:49:15.186268 CPU clk: 1200 MHz
579 23:49:15.186748 Set clk81 to 166.6M
580 23:49:15.191269 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 23:49:15.196879 board id: 1
582 23:49:15.201142 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 23:49:15.213074 fw parse done
584 23:49:15.218926 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 23:49:15.262069 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 23:49:15.273175 PIEI prepare done
587 23:49:15.273583 fastboot data load
588 23:49:15.273876 fastboot data verify
589 23:49:15.278776 verify result: 266
590 23:49:15.284287 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 23:49:15.284628 LPDDR4 probe
592 23:49:15.284900 ddr clk to 1584MHz
593 23:49:15.292247 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 23:49:15.330183
595 23:49:15.330709 dmc_version 0001
596 23:49:15.337114 Check phy result
597 23:49:15.343035 INFO : End of CA training
598 23:49:15.343505 INFO : End of initialization
599 23:49:15.348672 INFO : Training has run successfully!
600 23:49:15.349138 Check phy result
601 23:49:15.354246 INFO : End of initialization
602 23:49:15.354713 INFO : End of read enable training
603 23:49:15.359863 INFO : End of fine write leveling
604 23:49:15.365432 INFO : End of Write leveling coarse delay
605 23:49:15.365894 INFO : Training has run successfully!
606 23:49:15.366277 Check phy result
607 23:49:15.371037 INFO : End of initialization
608 23:49:15.371495 INFO : End of read dq deskew training
609 23:49:15.376685 INFO : End of MPR read delay center optimization
610 23:49:15.382279 INFO : End of write delay center optimization
611 23:49:15.387855 INFO : End of read delay center optimization
612 23:49:15.388354 INFO : End of max read latency training
613 23:49:15.393464 INFO : Training has run successfully!
614 23:49:15.393940 1D training succeed
615 23:49:15.402680 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 23:49:15.450923 Check phy result
617 23:49:15.451463 INFO : End of initialization
618 23:49:15.478327 INFO : End of 2D read delay Voltage center optimization
619 23:49:15.501583 INFO : End of 2D read delay Voltage center optimization
620 23:49:15.558820 INFO : End of 2D write delay Voltage center optimization
621 23:49:15.613158 INFO : End of 2D write delay Voltage center optimization
622 23:49:15.618702 INFO : Training has run successfully!
623 23:49:15.619069
624 23:49:15.619364 channel==0
625 23:49:15.624275 RxClkDly_Margin_A0==78 ps 8
626 23:49:15.624617 TxDqDly_Margin_A0==88 ps 9
627 23:49:15.627659 RxClkDly_Margin_A1==88 ps 9
628 23:49:15.628016 TxDqDly_Margin_A1==98 ps 10
629 23:49:15.633220 TrainedVREFDQ_A0==74
630 23:49:15.633557 TrainedVREFDQ_A1==75
631 23:49:15.633834 VrefDac_Margin_A0==24
632 23:49:15.638803 DeviceVref_Margin_A0==40
633 23:49:15.639138 VrefDac_Margin_A1==23
634 23:49:15.644396 DeviceVref_Margin_A1==39
635 23:49:15.644731
636 23:49:15.644996
637 23:49:15.645262 channel==1
638 23:49:15.645518 RxClkDly_Margin_A0==88 ps 9
639 23:49:15.647766 TxDqDly_Margin_A0==98 ps 10
640 23:49:15.653356 RxClkDly_Margin_A1==78 ps 8
641 23:49:15.653701 TxDqDly_Margin_A1==88 ps 9
642 23:49:15.653972 TrainedVREFDQ_A0==78
643 23:49:15.659127 TrainedVREFDQ_A1==75
644 23:49:15.659455 VrefDac_Margin_A0==22
645 23:49:15.664647 DeviceVref_Margin_A0==36
646 23:49:15.664984 VrefDac_Margin_A1==22
647 23:49:15.665250 DeviceVref_Margin_A1==39
648 23:49:15.665506
649 23:49:15.670163 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 23:49:15.670645
651 23:49:15.703768 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 23:49:15.704347 2D training succeed
653 23:49:15.709398 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 23:49:15.715109 auto size-- 65535DDR cs0 size: 2048MB
655 23:49:15.715622 DDR cs1 size: 2048MB
656 23:49:15.720582 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 23:49:15.721039 cs0 DataBus test pass
658 23:49:15.721424 cs1 DataBus test pass
659 23:49:15.726185 cs0 AddrBus test pass
660 23:49:15.726649 cs1 AddrBus test pass
661 23:49:15.727005
662 23:49:15.731794 100bdlr_step_size ps== 478
663 23:49:15.732311 result report
664 23:49:15.732731 boot times 0Enable ddr reg access
665 23:49:15.741455 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 23:49:15.755365 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 23:49:16.414706 bl2z: ptr: 05129330, size: 00001e40
668 23:49:16.422563 0.0;M3 CHK:0;cm4_sp_mode 0
669 23:49:16.422911 MVN_1=0x00000000
670 23:49:16.423183 MVN_2=0x00000000
671 23:49:16.434163 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 23:49:16.434655 OPS=0x04
673 23:49:16.435044 ring efuse init
674 23:49:16.437014 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 23:49:16.442406 [0.017354 Inits done]
676 23:49:16.442726 secure task start!
677 23:49:16.442990 high task start!
678 23:49:16.443245 low task start!
679 23:49:16.445977 run into bl31
680 23:49:16.455618 NOTICE: BL31: v1.3(release):4fc40b1
681 23:49:16.463391 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 23:49:16.463852 NOTICE: BL31: G12A normal boot!
683 23:49:16.479041 NOTICE: BL31: BL33 decompress pass
684 23:49:16.484692 ERROR: Error initializing runtime service opteed_fast
685 23:49:17.280165
686 23:49:17.280740
687 23:49:17.285569 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 23:49:17.285904
689 23:49:17.289101 Model: Libre Computer AML-S905D3-CC Solitude
690 23:49:17.436124 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 23:49:17.451468 DRAM: 2 GiB (effective 3.8 GiB)
692 23:49:17.552391 Core: 406 devices, 33 uclasses, devicetree: separate
693 23:49:17.558322 WDT: Not starting watchdog@f0d0
694 23:49:17.583351 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 23:49:17.595601 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 23:49:17.600568 ** Bad device specification mmc 0 **
697 23:49:17.610686 Card did not respond to voltage select! : -110
698 23:49:17.618442 ** Bad device specification mmc 0 **
699 23:49:17.618889 Couldn't find partition mmc 0
700 23:49:17.626620 Card did not respond to voltage select! : -110
701 23:49:17.632257 ** Bad device specification mmc 0 **
702 23:49:17.632567 Couldn't find partition mmc 0
703 23:49:17.637196 Error: could not access storage.
704 23:49:17.934859 Net: eth0: ethernet@ff3f0000
705 23:49:17.935505 starting USB...
706 23:49:18.179584 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 23:49:18.180263 Starting the controller
708 23:49:18.186528 USB XHCI 1.10
709 23:49:19.742592 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 23:49:19.750940 scanning usb for storage devices... 0 Storage Device(s) found
712 23:49:19.802585 Hit any key to stop autoboot: 1
713 23:49:19.803534 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 23:49:19.804343 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 23:49:19.804900 Setting prompt string to ['=>']
716 23:49:19.805418 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 23:49:19.817000 0
718 23:49:19.817976 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 23:49:19.919259 => setenv autoload no
721 23:49:19.920062 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 23:49:19.925754 setenv autoload no
724 23:49:20.027347 => setenv initrd_high 0xffffffff
725 23:49:20.028064 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 23:49:20.032606 setenv initrd_high 0xffffffff
728 23:49:20.134199 => setenv fdt_high 0xffffffff
729 23:49:20.134965 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 23:49:20.139374 setenv fdt_high 0xffffffff
732 23:49:20.240959 => dhcp
733 23:49:20.241686 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 23:49:20.246178 dhcp
735 23:49:20.901415 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 23:49:20.902042 Speed: 1000, full duplex
737 23:49:20.902492 BOOTP broadcast 1
738 23:49:21.150055 BOOTP broadcast 2
739 23:49:21.163581 DHCP client bound to address 192.168.6.21 (261 ms)
741 23:49:21.265170 => setenv serverip 192.168.6.2
742 23:49:21.265902 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
743 23:49:21.270339 setenv serverip 192.168.6.2
745 23:49:21.371878 => tftpboot 0x01080000 949202/tftp-deploy-0hwv2rmv/kernel/uImage
746 23:49:21.372646 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
747 23:49:21.379279 tftpboot 0x01080000 949202/tftp-deploy-0hwv2rmv/kernel/uImage
748 23:49:21.379810 Speed: 1000, full duplex
749 23:49:21.380344 Using ethernet@ff3f0000 device
750 23:49:21.384811 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 23:49:21.390332 Filename '949202/tftp-deploy-0hwv2rmv/kernel/uImage'.
752 23:49:21.394198 Load address: 0x1080000
753 23:49:23.210417 Loading: *############################## UDP wrong checksum 00000005 000090af
754 23:49:23.635345 ######## UDP wrong checksum 000000ff 00008fb3
755 23:49:23.681413 UDP wrong checksum 000000ff 000020a6
756 23:49:24.343310 ############ 43.6 MiB
757 23:49:24.343913 14.8 MiB/s
758 23:49:24.344414 done
759 23:49:24.347684 Bytes transferred = 45713984 (2b98a40 hex)
761 23:49:24.449226 => tftpboot 0x08000000 949202/tftp-deploy-0hwv2rmv/ramdisk/ramdisk.cpio.gz.uboot
762 23:49:24.449881 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
763 23:49:24.456346 tftpboot 0x08000000 949202/tftp-deploy-0hwv2rmv/ramdisk/ramdisk.cpio.gz.uboot
764 23:49:24.456834 Speed: 1000, full duplex
765 23:49:24.457278 Using ethernet@ff3f0000 device
766 23:49:24.461899 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
767 23:49:24.471659 Filename '949202/tftp-deploy-0hwv2rmv/ramdisk/ramdisk.cpio.gz.uboot'.
768 23:49:24.472198 Load address: 0x8000000
769 23:49:28.614316 Loading: *################################################# UDP wrong checksum 0000000f 00003bff
770 23:49:30.182062 UDP wrong checksum 000000ff 000088a8
771 23:49:30.192087 UDP wrong checksum 000000ff 00001d9b
772 23:49:32.752916 UDP wrong checksum 000000ff 0000ee2b
773 23:49:32.774478 UDP wrong checksum 000000ff 0000851e
774 23:49:33.614060 T UDP wrong checksum 0000000f 00003bff
775 23:49:35.423395 UDP wrong checksum 000000ff 0000f28d
776 23:49:35.493217 UDP wrong checksum 000000ff 00007e80
777 23:49:43.616117 T T UDP wrong checksum 0000000f 00003bff
778 23:49:45.575574 UDP wrong checksum 000000ff 00008eb8
779 23:49:45.585912 UDP wrong checksum 000000ff 000017ab
780 23:49:57.203745 T T UDP wrong checksum 000000ff 00009ddb
781 23:49:57.264187 UDP wrong checksum 000000ff 000038ce
782 23:50:03.620109 T T UDP wrong checksum 0000000f 00003bff
783 23:50:23.624896 T T T
784 23:50:23.625336 Retry count exceeded; starting again
786 23:50:23.626651 end: 2.4.3 bootloader-commands (duration 00:01:04) [common]
789 23:50:23.627560 end: 2.4 uboot-commands (duration 00:01:23) [common]
791 23:50:23.628305 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
793 23:50:23.628845 end: 2 uboot-action (duration 00:01:23) [common]
795 23:50:23.629631 Cleaning after the job
796 23:50:23.629931 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949202/tftp-deploy-0hwv2rmv/ramdisk
797 23:50:23.630707 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949202/tftp-deploy-0hwv2rmv/kernel
798 23:50:23.675601 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949202/tftp-deploy-0hwv2rmv/dtb
799 23:50:23.676397 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949202/tftp-deploy-0hwv2rmv/modules
800 23:50:23.695454 start: 4.1 power-off (timeout 00:00:30) [common]
801 23:50:23.696148 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
802 23:50:23.728061 >> OK - accepted request
803 23:50:23.730142 Returned 0 in 0 seconds
804 23:50:23.830996 end: 4.1 power-off (duration 00:00:00) [common]
806 23:50:23.831999 start: 4.2 read-feedback (timeout 00:10:00) [common]
807 23:50:23.832891 Listened to connection for namespace 'common' for up to 1s
808 23:50:24.833107 Finalising connection for namespace 'common'
809 23:50:24.833863 Disconnecting from shell: Finalise
810 23:50:24.834438 =>
811 23:50:24.935476 end: 4.2 read-feedback (duration 00:00:01) [common]
812 23:50:24.936233 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949202
813 23:50:25.716735 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949202
814 23:50:25.717370 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.