Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 8
- Errors: 0
- Boot result: PASS
- Kernel Errors: 6
1 23:23:38.660069 lava-dispatcher, installed at version: 2024.01
2 23:23:38.660857 start: 0 validate
3 23:23:38.661330 Start time: 2024-11-06 23:23:38.661299+00:00 (UTC)
4 23:23:38.661856 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:23:38.662379 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:23:38.703371 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:23:38.703893 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:23:38.735216 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:23:38.736144 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 23:23:38.767897 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:23:38.768406 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:23:38.799362 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 23:23:38.799840 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 23:23:38.844411 validate duration: 0.18
16 23:23:38.846330 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:23:38.847131 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:23:38.847919 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:23:38.849175 Not decompressing ramdisk as can be used compressed.
20 23:23:38.850127 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:23:38.850782 saving as /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/ramdisk/initrd.cpio.gz
22 23:23:38.851426 total size: 5628169 (5 MB)
23 23:23:38.894550 progress 0 % (0 MB)
24 23:23:38.902427 progress 5 % (0 MB)
25 23:23:38.910330 progress 10 % (0 MB)
26 23:23:38.917221 progress 15 % (0 MB)
27 23:23:38.924539 progress 20 % (1 MB)
28 23:23:38.928187 progress 25 % (1 MB)
29 23:23:38.932215 progress 30 % (1 MB)
30 23:23:38.936299 progress 35 % (1 MB)
31 23:23:38.940399 progress 40 % (2 MB)
32 23:23:38.944408 progress 45 % (2 MB)
33 23:23:38.947974 progress 50 % (2 MB)
34 23:23:38.952015 progress 55 % (2 MB)
35 23:23:38.955914 progress 60 % (3 MB)
36 23:23:38.959473 progress 65 % (3 MB)
37 23:23:38.963475 progress 70 % (3 MB)
38 23:23:38.967057 progress 75 % (4 MB)
39 23:23:38.971042 progress 80 % (4 MB)
40 23:23:38.974588 progress 85 % (4 MB)
41 23:23:38.978469 progress 90 % (4 MB)
42 23:23:38.982084 progress 95 % (5 MB)
43 23:23:38.985330 progress 100 % (5 MB)
44 23:23:38.985970 5 MB downloaded in 0.13 s (39.90 MB/s)
45 23:23:38.986510 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:23:38.987402 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:23:38.987694 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:23:38.987963 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:23:38.988458 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/kernel/Image
51 23:23:38.988702 saving as /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/kernel/Image
52 23:23:38.988912 total size: 45713920 (43 MB)
53 23:23:38.989121 No compression specified
54 23:23:39.030130 progress 0 % (0 MB)
55 23:23:39.057958 progress 5 % (2 MB)
56 23:23:39.085905 progress 10 % (4 MB)
57 23:23:39.113645 progress 15 % (6 MB)
58 23:23:39.141042 progress 20 % (8 MB)
59 23:23:39.168357 progress 25 % (10 MB)
60 23:23:39.196128 progress 30 % (13 MB)
61 23:23:39.223822 progress 35 % (15 MB)
62 23:23:39.251491 progress 40 % (17 MB)
63 23:23:39.278732 progress 45 % (19 MB)
64 23:23:39.306442 progress 50 % (21 MB)
65 23:23:39.333986 progress 55 % (24 MB)
66 23:23:39.361616 progress 60 % (26 MB)
67 23:23:39.389093 progress 65 % (28 MB)
68 23:23:39.416775 progress 70 % (30 MB)
69 23:23:39.444264 progress 75 % (32 MB)
70 23:23:39.471930 progress 80 % (34 MB)
71 23:23:39.499121 progress 85 % (37 MB)
72 23:23:39.526774 progress 90 % (39 MB)
73 23:23:39.554309 progress 95 % (41 MB)
74 23:23:39.581492 progress 100 % (43 MB)
75 23:23:39.581987 43 MB downloaded in 0.59 s (73.51 MB/s)
76 23:23:39.582465 end: 1.2.1 http-download (duration 00:00:01) [common]
78 23:23:39.583286 end: 1.2 download-retry (duration 00:00:01) [common]
79 23:23:39.583561 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:23:39.583826 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:23:39.584317 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 23:23:39.584586 saving as /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/dtb/meson-g12b-a311d-libretech-cc.dtb
83 23:23:39.584794 total size: 54703 (0 MB)
84 23:23:39.585002 No compression specified
85 23:23:39.627370 progress 59 % (0 MB)
86 23:23:39.628222 progress 100 % (0 MB)
87 23:23:39.628778 0 MB downloaded in 0.04 s (1.19 MB/s)
88 23:23:39.629258 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:23:39.630071 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:23:39.630333 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:23:39.630594 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:23:39.631040 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:23:39.631276 saving as /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/nfsrootfs/full.rootfs.tar
95 23:23:39.631477 total size: 120894716 (115 MB)
96 23:23:39.631684 Using unxz to decompress xz
97 23:23:39.668031 progress 0 % (0 MB)
98 23:23:40.453552 progress 5 % (5 MB)
99 23:23:41.281915 progress 10 % (11 MB)
100 23:23:42.069471 progress 15 % (17 MB)
101 23:23:42.799168 progress 20 % (23 MB)
102 23:23:43.392262 progress 25 % (28 MB)
103 23:23:44.210374 progress 30 % (34 MB)
104 23:23:44.994082 progress 35 % (40 MB)
105 23:23:45.363149 progress 40 % (46 MB)
106 23:23:45.746851 progress 45 % (51 MB)
107 23:23:46.460465 progress 50 % (57 MB)
108 23:23:47.341470 progress 55 % (63 MB)
109 23:23:48.124034 progress 60 % (69 MB)
110 23:23:48.890616 progress 65 % (74 MB)
111 23:23:49.672877 progress 70 % (80 MB)
112 23:23:50.492628 progress 75 % (86 MB)
113 23:23:51.280611 progress 80 % (92 MB)
114 23:23:52.041133 progress 85 % (98 MB)
115 23:23:52.889893 progress 90 % (103 MB)
116 23:23:53.656349 progress 95 % (109 MB)
117 23:23:54.479029 progress 100 % (115 MB)
118 23:23:54.491401 115 MB downloaded in 14.86 s (7.76 MB/s)
119 23:23:54.492383 end: 1.4.1 http-download (duration 00:00:15) [common]
121 23:23:54.494163 end: 1.4 download-retry (duration 00:00:15) [common]
122 23:23:54.494741 start: 1.5 download-retry (timeout 00:09:44) [common]
123 23:23:54.495319 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 23:23:54.496276 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/modules.tar.xz
125 23:23:54.496801 saving as /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/modules/modules.tar
126 23:23:54.497261 total size: 11608172 (11 MB)
127 23:23:54.497729 Using unxz to decompress xz
128 23:23:54.544654 progress 0 % (0 MB)
129 23:23:54.609903 progress 5 % (0 MB)
130 23:23:54.683062 progress 10 % (1 MB)
131 23:23:54.778011 progress 15 % (1 MB)
132 23:23:54.870343 progress 20 % (2 MB)
133 23:23:54.949022 progress 25 % (2 MB)
134 23:23:55.023854 progress 30 % (3 MB)
135 23:23:55.098330 progress 35 % (3 MB)
136 23:23:55.174666 progress 40 % (4 MB)
137 23:23:55.250538 progress 45 % (5 MB)
138 23:23:55.334226 progress 50 % (5 MB)
139 23:23:55.410404 progress 55 % (6 MB)
140 23:23:55.494603 progress 60 % (6 MB)
141 23:23:55.574952 progress 65 % (7 MB)
142 23:23:55.653377 progress 70 % (7 MB)
143 23:23:55.737754 progress 75 % (8 MB)
144 23:23:55.823500 progress 80 % (8 MB)
145 23:23:55.906821 progress 85 % (9 MB)
146 23:23:55.987753 progress 90 % (9 MB)
147 23:23:56.067700 progress 95 % (10 MB)
148 23:23:56.147780 progress 100 % (11 MB)
149 23:23:56.158977 11 MB downloaded in 1.66 s (6.66 MB/s)
150 23:23:56.159636 end: 1.5.1 http-download (duration 00:00:02) [common]
152 23:23:56.161035 end: 1.5 download-retry (duration 00:00:02) [common]
153 23:23:56.161571 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 23:23:56.162086 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 23:24:12.796403 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/949203/extract-nfsrootfs-ql3hr6om
156 23:24:12.797013 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 23:24:12.797300 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 23:24:12.798041 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i
159 23:24:12.798511 makedir: /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin
160 23:24:12.798842 makedir: /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/tests
161 23:24:12.799160 makedir: /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/results
162 23:24:12.799490 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-add-keys
163 23:24:12.800052 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-add-sources
164 23:24:12.800569 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-background-process-start
165 23:24:12.801098 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-background-process-stop
166 23:24:12.801648 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-common-functions
167 23:24:12.802146 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-echo-ipv4
168 23:24:12.802708 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-install-packages
169 23:24:12.803195 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-installed-packages
170 23:24:12.803663 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-os-build
171 23:24:12.804170 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-probe-channel
172 23:24:12.804682 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-probe-ip
173 23:24:12.805177 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-target-ip
174 23:24:12.805661 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-target-mac
175 23:24:12.806133 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-target-storage
176 23:24:12.806614 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-test-case
177 23:24:12.807083 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-test-event
178 23:24:12.807546 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-test-feedback
179 23:24:12.808041 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-test-raise
180 23:24:12.808546 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-test-reference
181 23:24:12.809052 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-test-runner
182 23:24:12.809557 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-test-set
183 23:24:12.810030 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-test-shell
184 23:24:12.810529 Updating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-add-keys (debian)
185 23:24:12.811085 Updating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-add-sources (debian)
186 23:24:12.811591 Updating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-install-packages (debian)
187 23:24:12.812130 Updating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-installed-packages (debian)
188 23:24:12.812647 Updating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/bin/lava-os-build (debian)
189 23:24:12.813085 Creating /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/environment
190 23:24:12.813466 LAVA metadata
191 23:24:12.813725 - LAVA_JOB_ID=949203
192 23:24:12.813938 - LAVA_DISPATCHER_IP=192.168.6.2
193 23:24:12.814305 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 23:24:12.815284 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 23:24:12.815597 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 23:24:12.815803 skipped lava-vland-overlay
197 23:24:12.816071 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 23:24:12.816325 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 23:24:12.816543 skipped lava-multinode-overlay
200 23:24:12.816781 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 23:24:12.817027 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 23:24:12.817269 Loading test definitions
203 23:24:12.817541 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 23:24:12.817759 Using /lava-949203 at stage 0
205 23:24:12.818831 uuid=949203_1.6.2.4.1 testdef=None
206 23:24:12.819135 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 23:24:12.819394 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 23:24:12.820963 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 23:24:12.821749 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 23:24:12.823666 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 23:24:12.824564 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 23:24:12.826380 runner path: /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/0/tests/0_timesync-off test_uuid 949203_1.6.2.4.1
215 23:24:12.826950 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 23:24:12.827813 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 23:24:12.828081 Using /lava-949203 at stage 0
219 23:24:12.828466 Fetching tests from https://github.com/kernelci/test-definitions.git
220 23:24:12.828799 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/0/tests/1_kselftest-alsa'
221 23:24:16.145085 Running '/usr/bin/git checkout kernelci.org
222 23:24:16.337923 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 23:24:16.339376 uuid=949203_1.6.2.4.5 testdef=None
224 23:24:16.339720 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 23:24:16.340503 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
227 23:24:16.343441 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 23:24:16.344319 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
230 23:24:16.348076 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 23:24:16.348953 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 23:24:16.352569 runner path: /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/0/tests/1_kselftest-alsa test_uuid 949203_1.6.2.4.5
234 23:24:16.352862 BOARD='meson-g12b-a311d-libretech-cc'
235 23:24:16.353066 BRANCH='mainline'
236 23:24:16.353261 SKIPFILE='/dev/null'
237 23:24:16.353458 SKIP_INSTALL='True'
238 23:24:16.353651 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 23:24:16.353847 TST_CASENAME=''
240 23:24:16.354039 TST_CMDFILES='alsa'
241 23:24:16.354611 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 23:24:16.355401 Creating lava-test-runner.conf files
244 23:24:16.355605 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949203/lava-overlay-8h6vod_i/lava-949203/0 for stage 0
245 23:24:16.355952 - 0_timesync-off
246 23:24:16.356219 - 1_kselftest-alsa
247 23:24:16.356556 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 23:24:16.356837 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 23:24:39.648801 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 23:24:39.649261 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 23:24:39.649525 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 23:24:39.649796 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 23:24:39.650060 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 23:24:40.280334 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 23:24:40.280827 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
256 23:24:40.281097 extracting modules file /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949203/extract-nfsrootfs-ql3hr6om
257 23:24:41.773248 extracting modules file /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949203/extract-overlay-ramdisk-8w362q1b/ramdisk
258 23:24:43.468650 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 23:24:43.469209 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 23:24:43.469576 [common] Applying overlay to NFS
261 23:24:43.469855 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949203/compress-overlay-11q18dzg/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949203/extract-nfsrootfs-ql3hr6om
262 23:24:46.766226 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 23:24:46.766800 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 23:24:46.767191 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 23:24:46.767509 Converting downloaded kernel to a uImage
266 23:24:46.767915 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/kernel/Image /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/kernel/uImage
267 23:24:47.243754 output: Image Name:
268 23:24:47.244206 output: Created: Wed Nov 6 23:24:46 2024
269 23:24:47.244418 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 23:24:47.244624 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 23:24:47.244825 output: Load Address: 01080000
272 23:24:47.245026 output: Entry Point: 01080000
273 23:24:47.245223 output:
274 23:24:47.245558 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 23:24:47.245828 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 23:24:47.246096 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 23:24:47.246350 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 23:24:47.246606 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 23:24:47.246862 Building ramdisk /var/lib/lava/dispatcher/tmp/949203/extract-overlay-ramdisk-8w362q1b/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949203/extract-overlay-ramdisk-8w362q1b/ramdisk
280 23:24:49.489276 >> 166825 blocks
281 23:24:57.231584 Adding RAMdisk u-boot header.
282 23:24:57.232073 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949203/extract-overlay-ramdisk-8w362q1b/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949203/extract-overlay-ramdisk-8w362q1b/ramdisk.cpio.gz.uboot
283 23:24:57.476774 output: Image Name:
284 23:24:57.477185 output: Created: Wed Nov 6 23:24:57 2024
285 23:24:57.477396 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 23:24:57.477602 output: Data Size: 23432700 Bytes = 22883.50 KiB = 22.35 MiB
287 23:24:57.477803 output: Load Address: 00000000
288 23:24:57.478001 output: Entry Point: 00000000
289 23:24:57.478200 output:
290 23:24:57.478806 rename /var/lib/lava/dispatcher/tmp/949203/extract-overlay-ramdisk-8w362q1b/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/ramdisk/ramdisk.cpio.gz.uboot
291 23:24:57.479222 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 23:24:57.479509 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 23:24:57.479806 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 23:24:57.480175 No LXC device requested
295 23:24:57.480745 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 23:24:57.481334 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 23:24:57.481877 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 23:24:57.482330 Checking files for TFTP limit of 4294967296 bytes.
299 23:24:57.485284 end: 1 tftp-deploy (duration 00:01:19) [common]
300 23:24:57.485909 start: 2 uboot-action (timeout 00:05:00) [common]
301 23:24:57.486482 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 23:24:57.487025 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 23:24:57.487576 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 23:24:57.488181 Using kernel file from prepare-kernel: 949203/tftp-deploy-9co4o65t/kernel/uImage
305 23:24:57.488872 substitutions:
306 23:24:57.489319 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 23:24:57.489762 - {DTB_ADDR}: 0x01070000
308 23:24:57.490204 - {DTB}: 949203/tftp-deploy-9co4o65t/dtb/meson-g12b-a311d-libretech-cc.dtb
309 23:24:57.490642 - {INITRD}: 949203/tftp-deploy-9co4o65t/ramdisk/ramdisk.cpio.gz.uboot
310 23:24:57.491076 - {KERNEL_ADDR}: 0x01080000
311 23:24:57.491507 - {KERNEL}: 949203/tftp-deploy-9co4o65t/kernel/uImage
312 23:24:57.491940 - {LAVA_MAC}: None
313 23:24:57.492455 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/949203/extract-nfsrootfs-ql3hr6om
314 23:24:57.492894 - {NFS_SERVER_IP}: 192.168.6.2
315 23:24:57.493322 - {PRESEED_CONFIG}: None
316 23:24:57.493750 - {PRESEED_LOCAL}: None
317 23:24:57.494179 - {RAMDISK_ADDR}: 0x08000000
318 23:24:57.494601 - {RAMDISK}: 949203/tftp-deploy-9co4o65t/ramdisk/ramdisk.cpio.gz.uboot
319 23:24:57.495027 - {ROOT_PART}: None
320 23:24:57.495451 - {ROOT}: None
321 23:24:57.495872 - {SERVER_IP}: 192.168.6.2
322 23:24:57.496328 - {TEE_ADDR}: 0x83000000
323 23:24:57.496751 - {TEE}: None
324 23:24:57.497172 Parsed boot commands:
325 23:24:57.497583 - setenv autoload no
326 23:24:57.498005 - setenv initrd_high 0xffffffff
327 23:24:57.498428 - setenv fdt_high 0xffffffff
328 23:24:57.498850 - dhcp
329 23:24:57.499271 - setenv serverip 192.168.6.2
330 23:24:57.499697 - tftpboot 0x01080000 949203/tftp-deploy-9co4o65t/kernel/uImage
331 23:24:57.500165 - tftpboot 0x08000000 949203/tftp-deploy-9co4o65t/ramdisk/ramdisk.cpio.gz.uboot
332 23:24:57.500602 - tftpboot 0x01070000 949203/tftp-deploy-9co4o65t/dtb/meson-g12b-a311d-libretech-cc.dtb
333 23:24:57.501029 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/949203/extract-nfsrootfs-ql3hr6om,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 23:24:57.501467 - bootm 0x01080000 0x08000000 0x01070000
335 23:24:57.502012 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 23:24:57.503638 start: 2.3 connect-device (timeout 00:05:00) [common]
338 23:24:57.504127 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 23:24:57.519224 Setting prompt string to ['lava-test: # ']
340 23:24:57.520909 end: 2.3 connect-device (duration 00:00:00) [common]
341 23:24:57.521588 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 23:24:57.522207 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 23:24:57.522927 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 23:24:57.524241 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 23:24:57.560495 >> OK - accepted request
346 23:24:57.562666 Returned 0 in 0 seconds
347 23:24:57.663805 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 23:24:57.665565 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 23:24:57.666161 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 23:24:57.666713 Setting prompt string to ['Hit any key to stop autoboot']
352 23:24:57.667209 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 23:24:57.668941 Trying 192.168.56.21...
354 23:24:57.669469 Connected to conserv1.
355 23:24:57.669912 Escape character is '^]'.
356 23:24:57.670366
357 23:24:57.670827 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 23:24:57.671286
359 23:25:09.545527 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 23:25:09.546197 bl2_stage_init 0x01
361 23:25:09.546667 bl2_stage_init 0x81
362 23:25:09.550854 hw id: 0x0000 - pwm id 0x01
363 23:25:09.551368 bl2_stage_init 0xc1
364 23:25:09.551829 bl2_stage_init 0x02
365 23:25:09.552332
366 23:25:09.556455 L0:00000000
367 23:25:09.556968 L1:20000703
368 23:25:09.557427 L2:00008067
369 23:25:09.557873 L3:14000000
370 23:25:09.559459 B2:00402000
371 23:25:09.559944 B1:e0f83180
372 23:25:09.560414
373 23:25:09.560850 TE: 58167
374 23:25:09.561283
375 23:25:09.570888 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 23:25:09.571376
377 23:25:09.571810 Board ID = 1
378 23:25:09.572274 Set A53 clk to 24M
379 23:25:09.572706 Set A73 clk to 24M
380 23:25:09.576249 Set clk81 to 24M
381 23:25:09.576714 A53 clk: 1200 MHz
382 23:25:09.577144 A73 clk: 1200 MHz
383 23:25:09.581857 CLK81: 166.6M
384 23:25:09.582317 smccc: 00012abe
385 23:25:09.587457 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 23:25:09.587918 board id: 1
387 23:25:09.596240 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 23:25:09.606652 fw parse done
389 23:25:09.612519 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 23:25:09.654144 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 23:25:09.666019 PIEI prepare done
392 23:25:09.666479 fastboot data load
393 23:25:09.666913 fastboot data verify
394 23:25:09.672364 verify result: 266
395 23:25:09.677257 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 23:25:09.677733 LPDDR4 probe
397 23:25:09.678191 ddr clk to 1584MHz
398 23:25:09.685181 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 23:25:09.722459
400 23:25:09.722957 dmc_version 0001
401 23:25:09.729122 Check phy result
402 23:25:09.734981 INFO : End of CA training
403 23:25:09.735462 INFO : End of initialization
404 23:25:09.740636 INFO : Training has run successfully!
405 23:25:09.741119 Check phy result
406 23:25:09.746221 INFO : End of initialization
407 23:25:09.746704 INFO : End of read enable training
408 23:25:09.749593 INFO : End of fine write leveling
409 23:25:09.755114 INFO : End of Write leveling coarse delay
410 23:25:09.760700 INFO : Training has run successfully!
411 23:25:09.761191 Check phy result
412 23:25:09.761653 INFO : End of initialization
413 23:25:09.766314 INFO : End of read dq deskew training
414 23:25:09.771927 INFO : End of MPR read delay center optimization
415 23:25:09.772454 INFO : End of write delay center optimization
416 23:25:09.777577 INFO : End of read delay center optimization
417 23:25:09.783102 INFO : End of max read latency training
418 23:25:09.783590 INFO : Training has run successfully!
419 23:25:09.788729 1D training succeed
420 23:25:09.794624 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 23:25:09.842289 Check phy result
422 23:25:09.842812 INFO : End of initialization
423 23:25:09.863825 INFO : End of 2D read delay Voltage center optimization
424 23:25:09.883911 INFO : End of 2D read delay Voltage center optimization
425 23:25:09.935804 INFO : End of 2D write delay Voltage center optimization
426 23:25:09.985009 INFO : End of 2D write delay Voltage center optimization
427 23:25:09.990597 INFO : Training has run successfully!
428 23:25:09.991068
429 23:25:09.991523 channel==0
430 23:25:09.996227 RxClkDly_Margin_A0==88 ps 9
431 23:25:09.996704 TxDqDly_Margin_A0==98 ps 10
432 23:25:09.999622 RxClkDly_Margin_A1==88 ps 9
433 23:25:10.000125 TxDqDly_Margin_A1==98 ps 10
434 23:25:10.005110 TrainedVREFDQ_A0==74
435 23:25:10.005585 TrainedVREFDQ_A1==74
436 23:25:10.006032 VrefDac_Margin_A0==25
437 23:25:10.010756 DeviceVref_Margin_A0==40
438 23:25:10.011241 VrefDac_Margin_A1==25
439 23:25:10.016353 DeviceVref_Margin_A1==40
440 23:25:10.016828
441 23:25:10.017278
442 23:25:10.017720 channel==1
443 23:25:10.018154 RxClkDly_Margin_A0==98 ps 10
444 23:25:10.021890 TxDqDly_Margin_A0==98 ps 10
445 23:25:10.022368 RxClkDly_Margin_A1==98 ps 10
446 23:25:10.027611 TxDqDly_Margin_A1==88 ps 9
447 23:25:10.028127 TrainedVREFDQ_A0==77
448 23:25:10.028582 TrainedVREFDQ_A1==77
449 23:25:10.033121 VrefDac_Margin_A0==22
450 23:25:10.033593 DeviceVref_Margin_A0==37
451 23:25:10.038760 VrefDac_Margin_A1==22
452 23:25:10.039238 DeviceVref_Margin_A1==37
453 23:25:10.039685
454 23:25:10.044325 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 23:25:10.044802
456 23:25:10.072355 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
457 23:25:10.077910 2D training succeed
458 23:25:10.083610 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 23:25:10.084124 auto size-- 65535DDR cs0 size: 2048MB
460 23:25:10.089141 DDR cs1 size: 2048MB
461 23:25:10.089610 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 23:25:10.094711 cs0 DataBus test pass
463 23:25:10.095180 cs1 DataBus test pass
464 23:25:10.095623 cs0 AddrBus test pass
465 23:25:10.100362 cs1 AddrBus test pass
466 23:25:10.100834
467 23:25:10.101281 100bdlr_step_size ps== 420
468 23:25:10.101734 result report
469 23:25:10.105916 boot times 0Enable ddr reg access
470 23:25:10.112765 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 23:25:10.127074 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 23:25:10.699083 0.0;M3 CHK:0;cm4_sp_mode 0
473 23:25:10.699655 MVN_1=0x00000000
474 23:25:10.704677 MVN_2=0x00000000
475 23:25:10.710428 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 23:25:10.710913 OPS=0x10
477 23:25:10.711364 ring efuse init
478 23:25:10.711804 chipver efuse init
479 23:25:10.715952 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 23:25:10.721671 [0.018961 Inits done]
481 23:25:10.722152 secure task start!
482 23:25:10.722598 high task start!
483 23:25:10.726121 low task start!
484 23:25:10.726597 run into bl31
485 23:25:10.732796 NOTICE: BL31: v1.3(release):4fc40b1
486 23:25:10.739676 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 23:25:10.740196 NOTICE: BL31: G12A normal boot!
488 23:25:10.766059 NOTICE: BL31: BL33 decompress pass
489 23:25:10.771760 ERROR: Error initializing runtime service opteed_fast
490 23:25:12.004711
491 23:25:12.005371
492 23:25:12.013012 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 23:25:12.013519
494 23:25:12.013979 Model: Libre Computer AML-A311D-CC Alta
495 23:25:12.221438 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 23:25:12.244955 DRAM: 2 GiB (effective 3.8 GiB)
497 23:25:12.387959 Core: 408 devices, 31 uclasses, devicetree: separate
498 23:25:12.393719 WDT: Not starting watchdog@f0d0
499 23:25:12.425934 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 23:25:12.438409 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 23:25:12.443380 ** Bad device specification mmc 0 **
502 23:25:12.453713 Card did not respond to voltage select! : -110
503 23:25:12.461357 ** Bad device specification mmc 0 **
504 23:25:12.461837 Couldn't find partition mmc 0
505 23:25:12.469738 Card did not respond to voltage select! : -110
506 23:25:12.475255 ** Bad device specification mmc 0 **
507 23:25:12.475740 Couldn't find partition mmc 0
508 23:25:12.479358 Error: could not access storage.
509 23:25:13.745519 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 23:25:13.746193 bl2_stage_init 0x01
511 23:25:13.746678 bl2_stage_init 0x81
512 23:25:13.751098 hw id: 0x0000 - pwm id 0x01
513 23:25:13.751586 bl2_stage_init 0xc1
514 23:25:13.752101 bl2_stage_init 0x02
515 23:25:13.752562
516 23:25:13.756686 L0:00000000
517 23:25:13.757171 L1:20000703
518 23:25:13.757622 L2:00008067
519 23:25:13.758065 L3:14000000
520 23:25:13.759545 B2:00402000
521 23:25:13.760045 B1:e0f83180
522 23:25:13.760502
523 23:25:13.760951 TE: 58167
524 23:25:13.761395
525 23:25:13.770813 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 23:25:13.771311
527 23:25:13.771761 Board ID = 1
528 23:25:13.772245 Set A53 clk to 24M
529 23:25:13.772689 Set A73 clk to 24M
530 23:25:13.776494 Set clk81 to 24M
531 23:25:13.776977 A53 clk: 1200 MHz
532 23:25:13.777423 A73 clk: 1200 MHz
533 23:25:13.782057 CLK81: 166.6M
534 23:25:13.782531 smccc: 00012abd
535 23:25:13.787557 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 23:25:13.788065 board id: 1
537 23:25:13.796189 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 23:25:13.806857 fw parse done
539 23:25:13.811837 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 23:25:13.855425 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 23:25:13.866376 PIEI prepare done
542 23:25:13.866902 fastboot data load
543 23:25:13.867370 fastboot data verify
544 23:25:13.872087 verify result: 266
545 23:25:13.877598 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 23:25:13.878098 LPDDR4 probe
547 23:25:13.878552 ddr clk to 1584MHz
548 23:25:13.885548 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 23:25:13.922887
550 23:25:13.923438 dmc_version 0001
551 23:25:13.929463 Check phy result
552 23:25:13.935543 INFO : End of CA training
553 23:25:13.936054 INFO : End of initialization
554 23:25:13.940946 INFO : Training has run successfully!
555 23:25:13.941427 Check phy result
556 23:25:13.946568 INFO : End of initialization
557 23:25:13.947043 INFO : End of read enable training
558 23:25:13.949903 INFO : End of fine write leveling
559 23:25:13.955501 INFO : End of Write leveling coarse delay
560 23:25:13.961190 INFO : Training has run successfully!
561 23:25:13.961681 Check phy result
562 23:25:13.962130 INFO : End of initialization
563 23:25:13.966709 INFO : End of read dq deskew training
564 23:25:13.972305 INFO : End of MPR read delay center optimization
565 23:25:13.972789 INFO : End of write delay center optimization
566 23:25:13.977886 INFO : End of read delay center optimization
567 23:25:13.983458 INFO : End of max read latency training
568 23:25:13.983941 INFO : Training has run successfully!
569 23:25:13.989135 1D training succeed
570 23:25:13.994982 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 23:25:14.041639 Check phy result
572 23:25:14.042149 INFO : End of initialization
573 23:25:14.064344 INFO : End of 2D read delay Voltage center optimization
574 23:25:14.084549 INFO : End of 2D read delay Voltage center optimization
575 23:25:14.135720 INFO : End of 2D write delay Voltage center optimization
576 23:25:14.186010 INFO : End of 2D write delay Voltage center optimization
577 23:25:14.191502 INFO : Training has run successfully!
578 23:25:14.191975
579 23:25:14.192482 channel==0
580 23:25:14.197185 RxClkDly_Margin_A0==88 ps 9
581 23:25:14.197659 TxDqDly_Margin_A0==98 ps 10
582 23:25:14.202707 RxClkDly_Margin_A1==88 ps 9
583 23:25:14.203178 TxDqDly_Margin_A1==98 ps 10
584 23:25:14.203629 TrainedVREFDQ_A0==74
585 23:25:14.208293 TrainedVREFDQ_A1==74
586 23:25:14.208766 VrefDac_Margin_A0==25
587 23:25:14.209210 DeviceVref_Margin_A0==40
588 23:25:14.213989 VrefDac_Margin_A1==25
589 23:25:14.214464 DeviceVref_Margin_A1==40
590 23:25:14.214911
591 23:25:14.215356
592 23:25:14.219514 channel==1
593 23:25:14.220019 RxClkDly_Margin_A0==98 ps 10
594 23:25:14.220473 TxDqDly_Margin_A0==98 ps 10
595 23:25:14.225188 RxClkDly_Margin_A1==88 ps 9
596 23:25:14.225662 TxDqDly_Margin_A1==108 ps 11
597 23:25:14.230701 TrainedVREFDQ_A0==77
598 23:25:14.231179 TrainedVREFDQ_A1==77
599 23:25:14.231628 VrefDac_Margin_A0==22
600 23:25:14.236277 DeviceVref_Margin_A0==37
601 23:25:14.236746 VrefDac_Margin_A1==24
602 23:25:14.241907 DeviceVref_Margin_A1==37
603 23:25:14.242384
604 23:25:14.242832 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 23:25:14.247495
606 23:25:14.275492 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 23:25:14.276063 2D training succeed
608 23:25:14.281204 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 23:25:14.286678 auto size-- 65535DDR cs0 size: 2048MB
610 23:25:14.287161 DDR cs1 size: 2048MB
611 23:25:14.292294 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 23:25:14.292770 cs0 DataBus test pass
613 23:25:14.297950 cs1 DataBus test pass
614 23:25:14.298446 cs0 AddrBus test pass
615 23:25:14.298893 cs1 AddrBus test pass
616 23:25:14.299329
617 23:25:14.303537 100bdlr_step_size ps== 420
618 23:25:14.304058 result report
619 23:25:14.309200 boot times 0Enable ddr reg access
620 23:25:14.314627 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 23:25:14.328147 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 23:25:14.901734 0.0;M3 CHK:0;cm4_sp_mode 0
623 23:25:14.902393 MVN_1=0x00000000
624 23:25:14.906804 MVN_2=0x00000000
625 23:25:14.912540 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 23:25:14.913078 OPS=0x10
627 23:25:14.913541 ring efuse init
628 23:25:14.914000 chipver efuse init
629 23:25:14.918127 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 23:25:14.923692 [0.018961 Inits done]
631 23:25:14.924214 secure task start!
632 23:25:14.924645 high task start!
633 23:25:14.929682 low task start!
634 23:25:14.930143 run into bl31
635 23:25:14.935082 NOTICE: BL31: v1.3(release):4fc40b1
636 23:25:14.942825 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 23:25:14.943291 NOTICE: BL31: G12A normal boot!
638 23:25:14.968174 NOTICE: BL31: BL33 decompress pass
639 23:25:14.973822 ERROR: Error initializing runtime service opteed_fast
640 23:25:16.206942
641 23:25:16.207608
642 23:25:16.215214 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 23:25:16.215724
644 23:25:16.216224 Model: Libre Computer AML-A311D-CC Alta
645 23:25:16.423533 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 23:25:16.446008 DRAM: 2 GiB (effective 3.8 GiB)
647 23:25:16.590073 Core: 408 devices, 31 uclasses, devicetree: separate
648 23:25:16.595841 WDT: Not starting watchdog@f0d0
649 23:25:16.628097 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 23:25:16.641006 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 23:25:16.644660 ** Bad device specification mmc 0 **
652 23:25:16.655967 Card did not respond to voltage select! : -110
653 23:25:16.663560 ** Bad device specification mmc 0 **
654 23:25:16.664073 Couldn't find partition mmc 0
655 23:25:16.671819 Card did not respond to voltage select! : -110
656 23:25:16.677380 ** Bad device specification mmc 0 **
657 23:25:16.677866 Couldn't find partition mmc 0
658 23:25:16.682463 Error: could not access storage.
659 23:25:17.025023 Net: eth0: ethernet@ff3f0000
660 23:25:17.025567 starting USB...
661 23:25:17.276860 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 23:25:17.277398 Starting the controller
663 23:25:17.283883 USB XHCI 1.10
664 23:25:18.997424 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 23:25:18.997876 bl2_stage_init 0x01
666 23:25:18.998127 bl2_stage_init 0x81
667 23:25:19.003071 hw id: 0x0000 - pwm id 0x01
668 23:25:19.003619 bl2_stage_init 0xc1
669 23:25:19.003969 bl2_stage_init 0x02
670 23:25:19.004369
671 23:25:19.008994 L0:00000000
672 23:25:19.009369 L1:20000703
673 23:25:19.009603 L2:00008067
674 23:25:19.009833 L3:14000000
675 23:25:19.011895 B2:00402000
676 23:25:19.012226 B1:e0f83180
677 23:25:19.012455
678 23:25:19.012666 TE: 58124
679 23:25:19.012885
680 23:25:19.022407 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 23:25:19.022796
682 23:25:19.023029 Board ID = 1
683 23:25:19.023253 Set A53 clk to 24M
684 23:25:19.023469 Set A73 clk to 24M
685 23:25:19.028364 Set clk81 to 24M
686 23:25:19.029108 A53 clk: 1200 MHz
687 23:25:19.030040 A73 clk: 1200 MHz
688 23:25:19.031789 CLK81: 166.6M
689 23:25:19.032437 smccc: 00012a91
690 23:25:19.037201 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 23:25:19.042841 board id: 1
692 23:25:19.047971 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 23:25:19.058827 fw parse done
694 23:25:19.064697 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 23:25:19.106093 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 23:25:19.118516 PIEI prepare done
697 23:25:19.118916 fastboot data load
698 23:25:19.119142 fastboot data verify
699 23:25:19.123723 verify result: 266
700 23:25:19.129150 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 23:25:19.129575 LPDDR4 probe
702 23:25:19.129851 ddr clk to 1584MHz
703 23:25:19.137155 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 23:25:19.174446
705 23:25:19.175056 dmc_version 0001
706 23:25:19.181100 Check phy result
707 23:25:19.186936 INFO : End of CA training
708 23:25:19.187499 INFO : End of initialization
709 23:25:19.192622 INFO : Training has run successfully!
710 23:25:19.193008 Check phy result
711 23:25:19.198130 INFO : End of initialization
712 23:25:19.198678 INFO : End of read enable training
713 23:25:19.203884 INFO : End of fine write leveling
714 23:25:19.209375 INFO : End of Write leveling coarse delay
715 23:25:19.209754 INFO : Training has run successfully!
716 23:25:19.210009 Check phy result
717 23:25:19.214939 INFO : End of initialization
718 23:25:19.215438 INFO : End of read dq deskew training
719 23:25:19.220600 INFO : End of MPR read delay center optimization
720 23:25:19.226117 INFO : End of write delay center optimization
721 23:25:19.232006 INFO : End of read delay center optimization
722 23:25:19.232403 INFO : End of max read latency training
723 23:25:19.237476 INFO : Training has run successfully!
724 23:25:19.237826 1D training succeed
725 23:25:19.246535 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 23:25:19.294307 Check phy result
727 23:25:19.294981 INFO : End of initialization
728 23:25:19.316212 INFO : End of 2D read delay Voltage center optimization
729 23:25:19.336270 INFO : End of 2D read delay Voltage center optimization
730 23:25:19.388213 INFO : End of 2D write delay Voltage center optimization
731 23:25:19.437604 INFO : End of 2D write delay Voltage center optimization
732 23:25:19.443086 INFO : Training has run successfully!
733 23:25:19.443661
734 23:25:19.444183 channel==0
735 23:25:19.448573 RxClkDly_Margin_A0==88 ps 9
736 23:25:19.449098 TxDqDly_Margin_A0==98 ps 10
737 23:25:19.454403 RxClkDly_Margin_A1==88 ps 9
738 23:25:19.454982 TxDqDly_Margin_A1==88 ps 9
739 23:25:19.455448 TrainedVREFDQ_A0==74
740 23:25:19.459913 TrainedVREFDQ_A1==74
741 23:25:19.460465 VrefDac_Margin_A0==25
742 23:25:19.460923 DeviceVref_Margin_A0==40
743 23:25:19.465464 VrefDac_Margin_A1==25
744 23:25:19.465976 DeviceVref_Margin_A1==40
745 23:25:19.466435
746 23:25:19.466887
747 23:25:19.467335 channel==1
748 23:25:19.471166 RxClkDly_Margin_A0==98 ps 10
749 23:25:19.471741 TxDqDly_Margin_A0==98 ps 10
750 23:25:19.476766 RxClkDly_Margin_A1==88 ps 9
751 23:25:19.477290 TxDqDly_Margin_A1==88 ps 9
752 23:25:19.482295 TrainedVREFDQ_A0==77
753 23:25:19.482824 TrainedVREFDQ_A1==77
754 23:25:19.483284 VrefDac_Margin_A0==22
755 23:25:19.487937 DeviceVref_Margin_A0==37
756 23:25:19.488476 VrefDac_Margin_A1==24
757 23:25:19.493570 DeviceVref_Margin_A1==37
758 23:25:19.494080
759 23:25:19.494646 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 23:25:19.495161
761 23:25:19.527207 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 23:25:19.527832 2D training succeed
763 23:25:19.532673 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 23:25:19.538302 auto size-- 65535DDR cs0 size: 2048MB
765 23:25:19.538864 DDR cs1 size: 2048MB
766 23:25:19.544012 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 23:25:19.544568 cs0 DataBus test pass
768 23:25:19.549477 cs1 DataBus test pass
769 23:25:19.550016 cs0 AddrBus test pass
770 23:25:19.550450 cs1 AddrBus test pass
771 23:25:19.550884
772 23:25:19.555050 100bdlr_step_size ps== 420
773 23:25:19.555542 result report
774 23:25:19.560667 boot times 0Enable ddr reg access
775 23:25:19.566038 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 23:25:19.579423 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 23:25:20.153669 0.0;M3 CHK:0;cm4_sp_mode 0
778 23:25:20.154129 MVN_1=0x00000000
779 23:25:20.158820 MVN_2=0x00000000
780 23:25:20.164527 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 23:25:20.164911 OPS=0x10
782 23:25:20.165134 ring efuse init
783 23:25:20.165344 chipver efuse init
784 23:25:20.170066 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 23:25:20.175612 [0.018961 Inits done]
786 23:25:20.176026 secure task start!
787 23:25:20.176252 high task start!
788 23:25:20.180225 low task start!
789 23:25:20.180584 run into bl31
790 23:25:20.186886 NOTICE: BL31: v1.3(release):4fc40b1
791 23:25:20.194646 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 23:25:20.194950 NOTICE: BL31: G12A normal boot!
793 23:25:20.220141 NOTICE: BL31: BL33 decompress pass
794 23:25:20.225826 ERROR: Error initializing runtime service opteed_fast
795 23:25:21.458592
796 23:25:21.459017
797 23:25:21.466986 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 23:25:21.467367
799 23:25:21.467702 Model: Libre Computer AML-A311D-CC Alta
800 23:25:21.675527 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 23:25:21.698972 DRAM: 2 GiB (effective 3.8 GiB)
802 23:25:21.841928 Core: 408 devices, 31 uclasses, devicetree: separate
803 23:25:21.847857 WDT: Not starting watchdog@f0d0
804 23:25:21.880207 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 23:25:21.892475 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 23:25:21.897545 ** Bad device specification mmc 0 **
807 23:25:21.907865 Card did not respond to voltage select! : -110
808 23:25:21.915532 ** Bad device specification mmc 0 **
809 23:25:21.916094 Couldn't find partition mmc 0
810 23:25:21.923871 Card did not respond to voltage select! : -110
811 23:25:21.929366 ** Bad device specification mmc 0 **
812 23:25:21.929876 Couldn't find partition mmc 0
813 23:25:21.934299 Error: could not access storage.
814 23:25:22.276837 Net: eth0: ethernet@ff3f0000
815 23:25:22.277451 starting USB...
816 23:25:22.528629 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 23:25:22.529230 Starting the controller
818 23:25:22.535677 USB XHCI 1.10
819 23:25:24.677249 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 23:25:24.677879 bl2_stage_init 0x01
821 23:25:24.678309 bl2_stage_init 0x81
822 23:25:24.682915 hw id: 0x0000 - pwm id 0x01
823 23:25:24.683397 bl2_stage_init 0xc1
824 23:25:24.683814 bl2_stage_init 0x02
825 23:25:24.684294
826 23:25:24.688527 L0:00000000
827 23:25:24.688996 L1:20000703
828 23:25:24.689407 L2:00008067
829 23:25:24.689811 L3:14000000
830 23:25:24.694027 B2:00402000
831 23:25:24.694498 B1:e0f83180
832 23:25:24.694907
833 23:25:24.695313 TE: 58167
834 23:25:24.695739
835 23:25:24.699614 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 23:25:24.700140
837 23:25:24.700563 Board ID = 1
838 23:25:24.705283 Set A53 clk to 24M
839 23:25:24.705766 Set A73 clk to 24M
840 23:25:24.706176 Set clk81 to 24M
841 23:25:24.710852 A53 clk: 1200 MHz
842 23:25:24.711327 A73 clk: 1200 MHz
843 23:25:24.711738 CLK81: 166.6M
844 23:25:24.712174 smccc: 00012abe
845 23:25:24.716424 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 23:25:24.722072 board id: 1
847 23:25:24.728100 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 23:25:24.738482 fw parse done
849 23:25:24.744476 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 23:25:24.787053 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 23:25:24.798051 PIEI prepare done
852 23:25:24.798544 fastboot data load
853 23:25:24.798961 fastboot data verify
854 23:25:24.803612 verify result: 266
855 23:25:24.809199 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 23:25:24.809674 LPDDR4 probe
857 23:25:24.810083 ddr clk to 1584MHz
858 23:25:24.817133 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 23:25:24.854449
860 23:25:24.854985 dmc_version 0001
861 23:25:24.861165 Check phy result
862 23:25:24.867027 INFO : End of CA training
863 23:25:24.867496 INFO : End of initialization
864 23:25:24.872623 INFO : Training has run successfully!
865 23:25:24.873123 Check phy result
866 23:25:24.878234 INFO : End of initialization
867 23:25:24.878711 INFO : End of read enable training
868 23:25:24.881581 INFO : End of fine write leveling
869 23:25:24.887155 INFO : End of Write leveling coarse delay
870 23:25:24.892804 INFO : Training has run successfully!
871 23:25:24.893290 Check phy result
872 23:25:24.893701 INFO : End of initialization
873 23:25:24.898425 INFO : End of read dq deskew training
874 23:25:24.904060 INFO : End of MPR read delay center optimization
875 23:25:24.904546 INFO : End of write delay center optimization
876 23:25:24.909615 INFO : End of read delay center optimization
877 23:25:24.915226 INFO : End of max read latency training
878 23:25:24.915707 INFO : Training has run successfully!
879 23:25:24.920800 1D training succeed
880 23:25:24.926657 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 23:25:24.974198 Check phy result
882 23:25:24.974722 INFO : End of initialization
883 23:25:24.996631 INFO : End of 2D read delay Voltage center optimization
884 23:25:25.016751 INFO : End of 2D read delay Voltage center optimization
885 23:25:25.068664 INFO : End of 2D write delay Voltage center optimization
886 23:25:25.117952 INFO : End of 2D write delay Voltage center optimization
887 23:25:25.123472 INFO : Training has run successfully!
888 23:25:25.123953
889 23:25:25.124422 channel==0
890 23:25:25.129125 RxClkDly_Margin_A0==88 ps 9
891 23:25:25.129608 TxDqDly_Margin_A0==98 ps 10
892 23:25:25.134671 RxClkDly_Margin_A1==78 ps 8
893 23:25:25.135141 TxDqDly_Margin_A1==88 ps 9
894 23:25:25.135551 TrainedVREFDQ_A0==74
895 23:25:25.140259 TrainedVREFDQ_A1==74
896 23:25:25.140729 VrefDac_Margin_A0==24
897 23:25:25.141133 DeviceVref_Margin_A0==40
898 23:25:25.145840 VrefDac_Margin_A1==26
899 23:25:25.146317 DeviceVref_Margin_A1==40
900 23:25:25.146748
901 23:25:25.147163
902 23:25:25.147568 channel==1
903 23:25:25.154068 RxClkDly_Margin_A0==98 ps 10
904 23:25:25.156209 TxDqDly_Margin_A0==98 ps 10
905 23:25:25.156692 RxClkDly_Margin_A1==98 ps 10
906 23:25:25.157083 TxDqDly_Margin_A1==88 ps 9
907 23:25:25.161718 TrainedVREFDQ_A0==77
908 23:25:25.162203 TrainedVREFDQ_A1==77
909 23:25:25.167343 VrefDac_Margin_A0==22
910 23:25:25.167810 DeviceVref_Margin_A0==37
911 23:25:25.168239 VrefDac_Margin_A1==22
912 23:25:25.172862 DeviceVref_Margin_A1==37
913 23:25:25.173334
914 23:25:25.178461 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 23:25:25.178936
916 23:25:25.206468 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000017 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
917 23:25:25.206995 2D training succeed
918 23:25:25.212089 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 23:25:25.217647 auto size-- 65535DDR cs0 size: 2048MB
920 23:25:25.218107 DDR cs1 size: 2048MB
921 23:25:25.223259 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 23:25:25.223715 cs0 DataBus test pass
923 23:25:25.228837 cs1 DataBus test pass
924 23:25:25.229310 cs0 AddrBus test pass
925 23:25:25.234460 cs1 AddrBus test pass
926 23:25:25.234926
927 23:25:25.235317 100bdlr_step_size ps== 420
928 23:25:25.235714 result report
929 23:25:25.240076 boot times 0Enable ddr reg access
930 23:25:25.246384 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 23:25:25.259884 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 23:25:25.831948 0.0;M3 CHK:0;cm4_sp_mode 0
933 23:25:25.832621 MVN_1=0x00000000
934 23:25:25.837416 MVN_2=0x00000000
935 23:25:25.843179 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 23:25:25.843674 OPS=0x10
937 23:25:25.844138 ring efuse init
938 23:25:25.844548 chipver efuse init
939 23:25:25.851514 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 23:25:25.852054 [0.018961 Inits done]
941 23:25:25.859122 secure task start!
942 23:25:25.859602 high task start!
943 23:25:25.860046 low task start!
944 23:25:25.860460 run into bl31
945 23:25:25.865670 NOTICE: BL31: v1.3(release):4fc40b1
946 23:25:25.873626 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 23:25:25.874103 NOTICE: BL31: G12A normal boot!
948 23:25:25.898715 NOTICE: BL31: BL33 decompress pass
949 23:25:25.904436 ERROR: Error initializing runtime service opteed_fast
950 23:25:27.137283
951 23:25:27.137878
952 23:25:27.145725 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 23:25:27.146226
954 23:25:27.146648 Model: Libre Computer AML-A311D-CC Alta
955 23:25:27.354208 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 23:25:27.377583 DRAM: 2 GiB (effective 3.8 GiB)
957 23:25:27.520468 Core: 408 devices, 31 uclasses, devicetree: separate
958 23:25:27.525462 WDT: Not starting watchdog@f0d0
959 23:25:27.558596 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 23:25:27.571096 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 23:25:27.576090 ** Bad device specification mmc 0 **
962 23:25:27.586360 Card did not respond to voltage select! : -110
963 23:25:27.594062 ** Bad device specification mmc 0 **
964 23:25:27.594536 Couldn't find partition mmc 0
965 23:25:27.602290 Card did not respond to voltage select! : -110
966 23:25:27.607915 ** Bad device specification mmc 0 **
967 23:25:27.608430 Couldn't find partition mmc 0
968 23:25:27.613039 Error: could not access storage.
969 23:25:27.956508 Net: eth0: ethernet@ff3f0000
970 23:25:27.957089 starting USB...
971 23:25:28.208376 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 23:25:28.208958 Starting the controller
973 23:25:28.215287 USB XHCI 1.10
974 23:25:29.769218 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 23:25:29.776732 scanning usb for storage devices... 0 Storage Device(s) found
977 23:25:29.828268 Hit any key to stop autoboot: 1
978 23:25:29.829296 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
979 23:25:29.829942 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
980 23:25:29.830460 Setting prompt string to ['=>']
981 23:25:29.830985 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
982 23:25:29.834144 0
983 23:25:29.835022 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 23:25:29.835558 Sending with 10 millisecond of delay
986 23:25:30.970726 => setenv autoload no
987 23:25:30.981504 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
988 23:25:30.986547 setenv autoload no
989 23:25:30.987291 Sending with 10 millisecond of delay
991 23:25:32.784678 => setenv initrd_high 0xffffffff
992 23:25:32.795436 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
993 23:25:32.796314 setenv initrd_high 0xffffffff
994 23:25:32.797034 Sending with 10 millisecond of delay
996 23:25:34.413250 => setenv fdt_high 0xffffffff
997 23:25:34.424029 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
998 23:25:34.424841 setenv fdt_high 0xffffffff
999 23:25:34.425554 Sending with 10 millisecond of delay
1001 23:25:34.717340 => dhcp
1002 23:25:34.728044 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1003 23:25:34.728827 dhcp
1004 23:25:34.729258 Speed: 1000, full duplex
1005 23:25:34.729664 BOOTP broadcast 1
1006 23:25:34.887322 DHCP client bound to address 192.168.6.27 (159 ms)
1007 23:25:34.888095 Sending with 10 millisecond of delay
1009 23:25:36.564886 => setenv serverip 192.168.6.2
1010 23:25:36.575761 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1011 23:25:36.576673 setenv serverip 192.168.6.2
1012 23:25:36.577415 Sending with 10 millisecond of delay
1014 23:25:40.301937 => tftpboot 0x01080000 949203/tftp-deploy-9co4o65t/kernel/uImage
1015 23:25:40.312789 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1016 23:25:40.313693 tftpboot 0x01080000 949203/tftp-deploy-9co4o65t/kernel/uImage
1017 23:25:40.314184 Speed: 1000, full duplex
1018 23:25:40.314692 Using ethernet@ff3f0000 device
1019 23:25:40.315257 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1020 23:25:40.320844 Filename '949203/tftp-deploy-9co4o65t/kernel/uImage'.
1021 23:25:40.324681 Load address: 0x1080000
1022 23:25:43.221069 Loading: *################################################## 43.6 MiB
1023 23:25:43.221600 15 MiB/s
1024 23:25:43.221883 done
1025 23:25:43.223839 Bytes transferred = 45713984 (2b98a40 hex)
1026 23:25:43.224609 Sending with 10 millisecond of delay
1028 23:25:47.911969 => tftpboot 0x08000000 949203/tftp-deploy-9co4o65t/ramdisk/ramdisk.cpio.gz.uboot
1029 23:25:47.922808 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1030 23:25:47.923740 tftpboot 0x08000000 949203/tftp-deploy-9co4o65t/ramdisk/ramdisk.cpio.gz.uboot
1031 23:25:47.924296 Speed: 1000, full duplex
1032 23:25:47.924763 Using ethernet@ff3f0000 device
1033 23:25:47.925571 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1034 23:25:47.937286 Filename '949203/tftp-deploy-9co4o65t/ramdisk/ramdisk.cpio.gz.uboot'.
1035 23:25:47.937879 Load address: 0x8000000
1036 23:25:54.478472 Loading: *#####################T ############################# 22.3 MiB
1037 23:25:54.479091 3.4 MiB/s
1038 23:25:54.479515 done
1039 23:25:54.482629 Bytes transferred = 23432764 (1658e3c hex)
1040 23:25:54.483366 Sending with 10 millisecond of delay
1042 23:25:59.651488 => tftpboot 0x01070000 949203/tftp-deploy-9co4o65t/dtb/meson-g12b-a311d-libretech-cc.dtb
1043 23:25:59.662302 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
1044 23:25:59.663114 tftpboot 0x01070000 949203/tftp-deploy-9co4o65t/dtb/meson-g12b-a311d-libretech-cc.dtb
1045 23:25:59.663581 Speed: 1000, full duplex
1046 23:25:59.664028 Using ethernet@ff3f0000 device
1047 23:25:59.667420 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1048 23:25:59.680045 Filename '949203/tftp-deploy-9co4o65t/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1049 23:25:59.680524 Load address: 0x1070000
1050 23:25:59.696246 Loading: *################################################## 53.4 KiB
1051 23:25:59.696706 3.1 MiB/s
1052 23:25:59.697113 done
1053 23:25:59.702252 Bytes transferred = 54703 (d5af hex)
1054 23:25:59.702959 Sending with 10 millisecond of delay
1056 23:26:13.000285 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/949203/extract-nfsrootfs-ql3hr6om,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1057 23:26:13.011084 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:44)
1058 23:26:13.012058 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/949203/extract-nfsrootfs-ql3hr6om,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1059 23:26:13.012787 Sending with 10 millisecond of delay
1061 23:26:15.351449 => bootm 0x01080000 0x08000000 0x01070000
1062 23:26:15.362047 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1063 23:26:15.362439 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:42)
1064 23:26:15.363064 bootm 0x01080000 0x08000000 0x01070000
1065 23:26:15.363355 ## Booting kernel from Legacy Image at 01080000 ...
1066 23:26:15.366741 Image Name:
1067 23:26:15.372280 Image Type: AArch64 Linux Kernel Image (uncompressed)
1068 23:26:15.372607 Data Size: 45713920 Bytes = 43.6 MiB
1069 23:26:15.377728 Load Address: 01080000
1070 23:26:15.378061 Entry Point: 01080000
1071 23:26:15.573029 Verifying Checksum ... OK
1072 23:26:15.573461 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1073 23:26:15.578397 Image Name:
1074 23:26:15.583908 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1075 23:26:15.584416 Data Size: 23432700 Bytes = 22.3 MiB
1076 23:26:15.589495 Load Address: 00000000
1077 23:26:15.589809 Entry Point: 00000000
1078 23:26:15.691721 Verifying Checksum ... OK
1079 23:26:15.692360 ## Flattened Device Tree blob at 01070000
1080 23:26:15.697158 Booting using the fdt blob at 0x1070000
1081 23:26:15.697626 Working FDT set to 1070000
1082 23:26:15.701586 Loading Kernel Image
1083 23:26:15.852451 Loading Ramdisk to 7e9a7000, end 7ffffdfc ... OK
1084 23:26:15.860727 Loading Device Tree to 000000007e996000, end 000000007e9a65ae ... OK
1085 23:26:15.861225 Working FDT set to 7e996000
1086 23:26:15.861647
1087 23:26:15.862532 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1088 23:26:15.863106 start: 2.4.4 auto-login-action (timeout 00:03:42) [common]
1089 23:26:15.863568 Setting prompt string to ['Linux version [0-9]']
1090 23:26:15.864066 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1091 23:26:15.864543 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1092 23:26:15.865568 Starting kernel ...
1093 23:26:15.866016
1094 23:26:15.900970 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1095 23:26:15.901915 start: 2.4.4.1 login-action (timeout 00:03:42) [common]
1096 23:26:15.902440 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1097 23:26:15.902904 Setting prompt string to []
1098 23:26:15.903391 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1099 23:26:15.903848 Using line separator: #'\n'#
1100 23:26:15.904302 No login prompt set.
1101 23:26:15.904743 Parsing kernel messages
1102 23:26:15.905140 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1103 23:26:15.905900 [login-action] Waiting for messages, (timeout 00:03:42)
1104 23:26:15.906348 Waiting using forced prompt support (timeout 00:01:51)
1105 23:26:15.917567 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j365602-arm64-gcc-12-defconfig-pvlx7) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Nov 6 21:27:37 UTC 2024
1106 23:26:15.923003 [ 0.000000] KASLR disabled due to lack of seed
1107 23:26:15.928556 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1108 23:26:15.934083 [ 0.000000] efi: UEFI not found.
1109 23:26:15.939550 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1110 23:26:15.945053 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1111 23:26:15.956226 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1112 23:26:15.967146 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1113 23:26:15.972733 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1114 23:26:15.983702 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1115 23:26:15.994731 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1116 23:26:16.000329 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1117 23:26:16.005840 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1118 23:26:16.011315 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1119 23:26:16.011777 [ 0.000000] Zone ranges:
1120 23:26:16.016849 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1121 23:26:16.022341 [ 0.000000] DMA32 empty
1122 23:26:16.022789 [ 0.000000] Normal empty
1123 23:26:16.027859 [ 0.000000] Movable zone start for each node
1124 23:26:16.033442 [ 0.000000] Early memory node ranges
1125 23:26:16.038874 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1126 23:26:16.044400 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1127 23:26:16.049934 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1128 23:26:16.055544 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1129 23:26:16.082830 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1130 23:26:16.088342 [ 0.000000] psci: probing for conduit method from DT.
1131 23:26:16.088778 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1132 23:26:16.097409 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1133 23:26:16.097872 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1134 23:26:16.102921 [ 0.000000] psci: SMC Calling Convention v1.1
1135 23:26:16.108403 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1136 23:26:16.117553 [ 0.000000] Detected VIPT I-cache on CPU0
1137 23:26:16.117990 [ 0.000000] CPU features: detected: ARM erratum 845719
1138 23:26:16.123015 [ 0.000000] alternatives: applying boot alternatives
1139 23:26:16.145133 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/949203/extract-nfsrootfs-ql3hr6om,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1140 23:26:16.156154 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1141 23:26:16.161645 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1142 23:26:16.167179 <6>[ 0.000000] Fallback order for Node 0: 0
1143 23:26:16.172720 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1144 23:26:16.178267 <6>[ 0.000000] Policy zone: DMA
1145 23:26:16.183730 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1146 23:26:16.189268 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1147 23:26:16.194777 <6>[ 0.000000] software IO TLB: area num 8.
1148 23:26:16.202297 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1149 23:26:16.248858 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1150 23:26:16.254360 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1151 23:26:16.259894 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1152 23:26:16.265471 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1153 23:26:16.270912 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1154 23:26:16.276652 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1155 23:26:16.281958 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1156 23:26:16.287440 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1157 23:26:16.298579 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1158 23:26:16.309597 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1159 23:26:16.315064 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1160 23:26:16.320587 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1161 23:26:16.321051 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1162 23:26:16.330438 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1163 23:26:16.343104 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1164 23:26:16.352171 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1165 23:26:16.357704 <6>[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1166 23:26:16.363230 <6>[ 0.008796] Console: colour dummy device 80x25
1167 23:26:16.374295 <6>[ 0.012941] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1168 23:26:16.379804 <6>[ 0.023295] pid_max: default: 32768 minimum: 301
1169 23:26:16.385370 <6>[ 0.028191] LSM: initializing lsm=capability
1170 23:26:16.390839 <6>[ 0.032730] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1171 23:26:16.401901 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1172 23:26:16.407396 <6>[ 0.052298] rcu: Hierarchical SRCU implementation.
1173 23:26:16.412906 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1174 23:26:16.418525 <6>[ 0.058881] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1175 23:26:16.423942 <6>[ 0.071579] EFI services will not be available.
1176 23:26:16.427867 <6>[ 0.075234] smp: Bringing up secondary CPUs ...
1177 23:26:16.441122 <6>[ 0.077133] Detected VIPT I-cache on CPU1
1178 23:26:16.446613 <6>[ 0.077254] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1179 23:26:16.452137 <6>[ 0.078594] CPU features: detected: Spectre-v2
1180 23:26:16.457670 <6>[ 0.078609] CPU features: detected: Spectre-v4
1181 23:26:16.463159 <6>[ 0.078615] CPU features: detected: Spectre-BHB
1182 23:26:16.468686 <6>[ 0.078620] CPU features: detected: ARM erratum 858921
1183 23:26:16.474206 <6>[ 0.078628] Detected VIPT I-cache on CPU2
1184 23:26:16.479747 <6>[ 0.078701] arch_timer: Enabling local workaround for ARM erratum 858921
1185 23:26:16.485263 <6>[ 0.078719] arch_timer: CPU2: Trapping CNTVCT access
1186 23:26:16.490781 <6>[ 0.078729] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1187 23:26:16.496333 <6>[ 0.079672] Detected VIPT I-cache on CPU3
1188 23:26:16.501819 <6>[ 0.079718] arch_timer: Enabling local workaround for ARM erratum 858921
1189 23:26:16.507317 <6>[ 0.079728] arch_timer: CPU3: Trapping CNTVCT access
1190 23:26:16.512866 <6>[ 0.079736] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1191 23:26:16.518383 <6>[ 0.083590] Detected VIPT I-cache on CPU4
1192 23:26:16.523896 <6>[ 0.083636] arch_timer: Enabling local workaround for ARM erratum 858921
1193 23:26:16.529422 <6>[ 0.083646] arch_timer: CPU4: Trapping CNTVCT access
1194 23:26:16.540510 <6>[ 0.083653] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1195 23:26:16.540945 <6>[ 0.091622] Detected VIPT I-cache on CPU5
1196 23:26:16.551538 <6>[ 0.091670] arch_timer: Enabling local workaround for ARM erratum 858921
1197 23:26:16.551971 <6>[ 0.091680] arch_timer: CPU5: Trapping CNTVCT access
1198 23:26:16.562643 <6>[ 0.091688] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1199 23:26:16.563078 <6>[ 0.091811] smp: Brought up 1 node, 6 CPUs
1200 23:26:16.568064 <6>[ 0.213037] SMP: Total of 6 processors activated.
1201 23:26:16.573642 <6>[ 0.217943] CPU: All CPU(s) started at EL2
1202 23:26:16.579078 <6>[ 0.222292] CPU features: detected: 32-bit EL0 Support
1203 23:26:16.584639 <6>[ 0.227605] CPU features: detected: 32-bit EL1 Support
1204 23:26:16.590141 <6>[ 0.232951] CPU features: detected: CRC32 instructions
1205 23:26:16.595651 <6>[ 0.238355] alternatives: applying system-wide alternatives
1206 23:26:16.613636 <6>[ 0.245533] Memory: 3557436K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187796K reserved, 262144K cma-reserved)
1207 23:26:16.614148 <6>[ 0.259891] devtmpfs: initialized
1208 23:26:16.624618 <6>[ 0.269026] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1209 23:26:16.630088 <6>[ 0.273378] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1210 23:26:16.635641 <6>[ 0.284185] 21392 pages in range for non-PLT usage
1211 23:26:16.641138 <6>[ 0.284196] 512912 pages in range for PLT usage
1212 23:26:16.646654 <6>[ 0.285739] pinctrl core: initialized pinctrl subsystem
1213 23:26:16.652204 <6>[ 0.297793] DMI not present or invalid.
1214 23:26:16.657692 <6>[ 0.302117] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1215 23:26:16.663266 <6>[ 0.306851] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1216 23:26:16.674294 <6>[ 0.313631] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1217 23:26:16.679804 <6>[ 0.321731] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1218 23:26:16.685336 <6>[ 0.329209] audit: initializing netlink subsys (disabled)
1219 23:26:16.696357 <5>[ 0.334945] audit: type=2000 audit(0.256:1): state=initialized audit_enabled=0 res=1
1220 23:26:16.701874 <6>[ 0.336351] thermal_sys: Registered thermal governor 'step_wise'
1221 23:26:16.707401 <6>[ 0.342714] thermal_sys: Registered thermal governor 'power_allocator'
1222 23:26:16.712962 <6>[ 0.348976] cpuidle: using governor menu
1223 23:26:16.718437 <6>[ 0.360012] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1224 23:26:16.724019 <6>[ 0.366890] ASID allocator initialised with 65536 entries
1225 23:26:16.732248 <6>[ 0.374378] Serial: AMBA PL011 UART driver
1226 23:26:16.739309 <6>[ 0.385004] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1227 23:26:16.755202 <6>[ 0.400388] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1228 23:26:16.766254 <6>[ 0.403051] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1229 23:26:16.771765 <6>[ 0.416184] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1230 23:26:16.777299 <6>[ 0.419435] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1231 23:26:16.788330 <6>[ 0.427850] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1232 23:26:16.793868 <6>[ 0.435478] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1233 23:26:16.804879 <6>[ 0.449052] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1234 23:26:16.810395 <6>[ 0.451300] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1235 23:26:16.815927 <6>[ 0.457782] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1236 23:26:16.821441 <6>[ 0.464760] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1237 23:26:16.832586 <6>[ 0.471229] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1238 23:26:16.838013 <6>[ 0.478213] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1239 23:26:16.843575 <6>[ 0.484683] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1240 23:26:16.849074 <6>[ 0.491668] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1241 23:26:16.854523 <6>[ 0.499676] ACPI: Interpreter disabled.
1242 23:26:16.860104 <6>[ 0.505035] iommu: Default domain type: Translated
1243 23:26:16.865747 <6>[ 0.507202] iommu: DMA domain TLB invalidation policy: strict mode
1244 23:26:16.871219 <5>[ 0.513909] SCSI subsystem initialized
1245 23:26:16.876694 <6>[ 0.517868] usbcore: registered new interface driver usbfs
1246 23:26:16.882168 <6>[ 0.523260] usbcore: registered new interface driver hub
1247 23:26:16.887800 <6>[ 0.528775] usbcore: registered new device driver usb
1248 23:26:16.893249 <6>[ 0.535046] pps_core: LinuxPPS API ver. 1 registered
1249 23:26:16.898764 <6>[ 0.539195] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1250 23:26:16.904331 <6>[ 0.548514] PTP clock support registered
1251 23:26:16.909759 <6>[ 0.552756] EDAC MC: Ver: 3.0.0
1252 23:26:16.915269 <6>[ 0.556419] scmi_core: SCMI protocol bus registered
1253 23:26:16.915773 <6>[ 0.562061] FPGA manager framework
1254 23:26:16.920799 <6>[ 0.564777] Advanced Linux Sound Architecture Driver Initialized.
1255 23:26:16.926340 <6>[ 0.571712] vgaarb: loaded
1256 23:26:16.931837 <6>[ 0.574285] clocksource: Switched to clocksource arch_sys_counter
1257 23:26:16.937360 <5>[ 0.580418] VFS: Disk quotas dquot_6.6.0
1258 23:26:16.942873 <6>[ 0.584408] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1259 23:26:16.948401 <6>[ 0.591620] pnp: PnP ACPI: disabled
1260 23:26:16.953945 <6>[ 0.599999] NET: Registered PF_INET protocol family
1261 23:26:16.959462 <6>[ 0.600445] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1262 23:26:16.970471 <6>[ 0.610594] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1263 23:26:16.976071 <6>[ 0.616611] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1264 23:26:16.987083 <6>[ 0.624507] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1265 23:26:16.992590 <6>[ 0.632745] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1266 23:26:16.998108 <6>[ 0.640536] TCP: Hash tables configured (established 32768 bind 32768)
1267 23:26:17.003757 <6>[ 0.647017] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1268 23:26:17.014724 <6>[ 0.653863] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1269 23:26:17.020200 <6>[ 0.661284] NET: Registered PF_UNIX/PF_LOCAL protocol family
1270 23:26:17.025752 <6>[ 0.667360] RPC: Registered named UNIX socket transport module.
1271 23:26:17.031218 <6>[ 0.673152] RPC: Registered udp transport module.
1272 23:26:17.036725 <6>[ 0.678057] RPC: Registered tcp transport module.
1273 23:26:17.042224 <6>[ 0.682972] RPC: Registered tcp-with-tls transport module.
1274 23:26:17.047765 <6>[ 0.688665] RPC: Registered tcp NFSv4.1 backchannel transport module.
1275 23:26:17.053641 <6>[ 0.695314] PCI: CLS 0 bytes, default 64
1276 23:26:17.054144 <6>[ 0.699709] Unpacking initramfs...
1277 23:26:17.059137 <6>[ 0.708929] kvm [1]: nv: 554 coarse grained trap handlers
1278 23:26:17.064622 <6>[ 0.709233] kvm [1]: IPA Size Limit: 40 bits
1279 23:26:17.070120 <6>[ 0.714923] kvm [1]: vgic interrupt IRQ9
1280 23:26:17.075726 <6>[ 0.717608] kvm [1]: Hyp nVHE mode initialized successfully
1281 23:26:17.081224 <5>[ 0.727336] Initialise system trusted keyrings
1282 23:26:17.086690 <6>[ 0.728176] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1283 23:26:17.092219 <6>[ 0.734942] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1284 23:26:17.097692 <5>[ 0.740965] NFS: Registering the id_resolver key type
1285 23:26:17.103242 <5>[ 0.746008] Key type id_resolver registered
1286 23:26:17.108786 <5>[ 0.750364] Key type id_legacy registered
1287 23:26:17.114293 <6>[ 0.754619] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1288 23:26:17.119807 <6>[ 0.761489] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1289 23:26:17.126326 <6>[ 0.769267] 9p: Installing v9fs 9p2000 file system support
1290 23:26:17.165269 <5>[ 0.815946] Key type asymmetric registered
1291 23:26:17.170821 <5>[ 0.815989] Asymmetric key parser 'x509' registered
1292 23:26:17.181794 <6>[ 0.819852] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1293 23:26:17.182314 <6>[ 0.827373] io scheduler mq-deadline registered
1294 23:26:17.187350 <6>[ 0.832111] io scheduler kyber registered
1295 23:26:17.192878 <6>[ 0.836377] io scheduler bfq registered
1296 23:26:17.198322 <6>[ 0.842267] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1297 23:26:17.215805 <6>[ 0.862741] ledtrig-cpu: registered to indicate activity on CPUs
1298 23:26:17.248187 <6>[ 0.893885] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1299 23:26:17.267905 <6>[ 0.907346] Serial: 8250/16550 driver, 4 ports<6>[ 0.911985] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1300 23:26:17.271231 <6>[ 0.921627] printk: legacy console [ttyAML0] enabled
1301 23:26:17.276771 <6>[ 0.921627] printk: legacy console [ttyAML0] enabled
1302 23:26:17.282301 <6>[ 0.926422] printk: legacy bootconsole [meson0] disabled
1303 23:26:17.287840 <6>[ 0.926422] printk: legacy bootconsole [meson0] disabled
1304 23:26:17.293390 <6>[ 0.939097] msm_serial: driver initialized
1305 23:26:17.298928 <6>[ 0.942376] SuperH (H)SCI(F) driver initialized
1306 23:26:17.304544 <6>[ 0.946884] STM32 USART driver initialized
1307 23:26:17.305043 <5>[ 0.953108] random: crng init done
1308 23:26:17.310015 <6>[ 0.958799] loop: module loaded
1309 23:26:17.317176 <6>[ 0.960068] megasas: 07.727.03.00-rc1
1310 23:26:17.322791 <6>[ 0.969067] tun: Universal TUN/TAP device driver, 1.6
1311 23:26:17.323308 <6>[ 0.970269] thunder_xcv, ver 1.0
1312 23:26:17.328276 <6>[ 0.972237] thunder_bgx, ver 1.0
1313 23:26:17.328837 <6>[ 0.975709] nicpf, ver 1.0
1314 23:26:17.339398 <6>[ 0.980313] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1315 23:26:17.344916 <6>[ 0.986097] hns3: Copyright (c) 2017 Huawei Corporation.
1316 23:26:17.345450 <6>[ 0.991687] hclge is initializing
1317 23:26:17.350472 <6>[ 0.995225] e1000: Intel(R) PRO/1000 Network Driver
1318 23:26:17.356056 <6>[ 1.000303] e1000: Copyright (c) 1999-2006 Intel Corporation.
1319 23:26:17.361573 <6>[ 1.006341] e1000e: Intel(R) PRO/1000 Network Driver
1320 23:26:17.367115 <6>[ 1.011484] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1321 23:26:17.372642 <6>[ 1.017675] igb: Intel(R) Gigabit Ethernet Network Driver
1322 23:26:17.383763 <6>[ 1.023270] igb: Copyright (c) 2007-2014 Intel Corporation.
1323 23:26:17.389262 <6>[ 1.029104] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1324 23:26:17.394839 <6>[ 1.035577] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1325 23:26:17.400419 <6>[ 1.042368] sky2: driver version 1.30
1326 23:26:17.400938 <6>[ 1.047470] VFIO - User Level meta-driver version: 0.3
1327 23:26:17.413729 <6>[ 1.054910] usbcore: registered new interface driver usb-storage
1328 23:26:17.414263 <6>[ 1.061033] i2c_dev: i2c /dev entries driver
1329 23:26:17.426981 <6>[ 1.072117] sdhci: Secure Digital Host Controller Interface driver
1330 23:26:17.427541 <6>[ 1.072922] sdhci: Copyright(c) Pierre Ossman
1331 23:26:17.438108 <6>[ 1.078642] Synopsys Designware Multimedia Card Interface Driver
1332 23:26:17.443665 <6>[ 1.085150] sdhci-pltfm: SDHCI platform and OF driver helper
1333 23:26:17.444273 <6>[ 1.092837] meson-sm: secure-monitor enabled
1334 23:26:17.456511 <6>[ 1.095357] usbcore: registered new interface driver usbhid
1335 23:26:17.457041 <6>[ 1.099979] usbhid: USB HID core driver
1336 23:26:17.464138 <6>[ 1.114793] NET: Registered PF_PACKET protocol family
1337 23:26:17.469696 <6>[ 1.114884] 9pnet: Installing 9P2000 support
1338 23:26:17.476765 <5>[ 1.119036] Key type dns_resolver registered
1339 23:26:17.482296 <6>[ 1.130598] registered taskstats version 1
1340 23:26:17.487836 <5>[ 1.130752] Loading compiled-in X.509 certificates
1341 23:26:17.490449 <6>[ 1.139409] Demotion targets for Node 0: null
1342 23:26:17.531847 <6>[ 1.182498] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1343 23:26:17.537394 <6>[ 1.182542] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1344 23:26:17.548497 <4>[ 1.192707] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1345 23:26:17.554024 <4>[ 1.195337] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1346 23:26:17.559549 <6>[ 1.202867] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1347 23:26:17.565132 <6>[ 1.212190] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1348 23:26:17.576227 <6>[ 1.215577] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1349 23:26:17.587299 <6>[ 1.223571] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1350 23:26:17.592855 <6>[ 1.233108] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1351 23:26:17.598374 <6>[ 1.239325] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1352 23:26:17.603937 <6>[ 1.244951] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1353 23:26:17.609480 <6>[ 1.252834] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1354 23:26:17.615048 <6>[ 1.260096] hub 1-0:1.0: USB hub found
1355 23:26:17.620572 <6>[ 1.263602] hub 1-0:1.0: 2 ports detected
1356 23:26:17.626121 <6>[ 1.269651] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1357 23:26:17.631669 <6>[ 1.276609] hub 2-0:1.0: USB hub found
1358 23:26:17.636744 <6>[ 1.280149] hub 2-0:1.0: 1 port detected
1359 23:26:17.660908 <6>[ 1.308908] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1360 23:26:17.671876 <6>[ 1.319087] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1361 23:26:17.706441 <6>[ 1.353298] Trying to probe devices needed for running init ...
1362 23:26:17.868111 <6>[ 1.514321] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1363 23:26:18.008161 <6>[ 1.658534] Freeing initrd memory: 22880K
1364 23:26:18.013602 <6>[ 1.661744] mmc0: new ultra high speed SDR104 SDXC card at address e624
1365 23:26:18.019150 <6>[ 1.664559] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1366 23:26:18.023102 <6>[ 1.670406] mmcblk0: p1
1367 23:26:18.057494 <6>[ 1.707941] hub 1-1:1.0: USB hub found
1368 23:26:18.063211 <6>[ 1.708246] hub 1-1:1.0: 4 ports detected
1369 23:26:18.132274 <6>[ 1.778423] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1370 23:26:18.170183 <6>[ 1.820588] hub 2-1:1.0: USB hub found
1371 23:26:18.175825 <6>[ 1.821416] hub 2-1:1.0: 4 ports detected
1372 23:26:30.000069 <6>[ 13.650354] clk: Disabling unused clocks
1373 23:26:30.005362 <6>[ 13.650521] PM: genpd: Disabling unused power domains
1374 23:26:30.013682 <6>[ 13.654215] ALSA device list:
1375 23:26:30.014153 <6>[ 13.657422] No soundcards found.
1376 23:26:30.019232 <6>[ 13.669802] Freeing unused kernel memory: 10432K
1377 23:26:30.025629 <6>[ 13.669904] Run /init as init process
1378 23:26:30.030960 Loading, please wait...
1379 23:26:30.069091 Starting systemd-udevd version 252.22-1~deb12u1
1380 23:26:30.512026 <6>[ 14.158103] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1381 23:26:30.524613 <4>[ 14.169664] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1382 23:26:30.530316 <3>[ 14.172822] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1383 23:26:30.541455 <6>[ 14.178743] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1384 23:26:30.546675 <6>[ 14.186942] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1385 23:26:30.552256 <6>[ 14.193152] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1386 23:26:30.557816 <6>[ 14.200021] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1387 23:26:30.563360 <6>[ 14.206685] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1388 23:26:30.574476 <6>[ 14.212101] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1389 23:26:30.580012 <6>[ 14.219807] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1390 23:26:30.585543 <6>[ 14.227540] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1391 23:26:30.591108 <6>[ 14.230815] meson-vrtc ff8000a8.rtc: registered as rtc0
1392 23:26:30.596749 <6>[ 14.232971] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1393 23:26:30.607819 <6>[ 14.238468] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1394 23:26:30.613414 <6>[ 14.245710] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1395 23:26:30.618928 <6>[ 14.249966] mc: Linux media interface: v0.10
1396 23:26:30.624446 <6>[ 14.256943] panfrost ffe40000.gpu: clock rate = 24000000
1397 23:26:30.629989 <6>[ 14.263117] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1398 23:26:30.635555 <6>[ 14.264313] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1399 23:26:30.641093 <6>[ 14.264321] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1400 23:26:30.646647 <6>[ 14.264325] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1401 23:26:30.657664 <3>[ 14.268014] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1402 23:26:30.668770 <6>[ 14.302369] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1403 23:26:30.674340 <6>[ 14.319412] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1404 23:26:30.679884 <6>[ 14.319632] videodev: Linux video capture interface: v2.00
1405 23:26:30.690923 <6>[ 14.324239] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1406 23:26:30.696549 <6>[ 14.324250] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1407 23:26:30.713140 <6>[ 14.324258] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1408 23:26:30.718741 <6>[ 14.329938] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1409 23:26:30.724276 <3>[ 14.330054] meson-drm ff900000.vpu: DSI transceiver device is disabled
1410 23:26:30.735321 <6>[ 14.338050] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1411 23:26:30.740115 <6>[ 14.366618] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1412 23:26:30.748458 <6>[ 14.397280] Registered IR keymap rc-empty
1413 23:26:30.927958 <6>[ 14.398990] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1414 23:26:30.933528 <6>[ 14.401441] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1415 23:26:30.944564 <6>[ 14.401572] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1416 23:26:30.945071 <6>[ 14.403640] rc rc0: sw decoder init
1417 23:26:30.950143 <6>[ 14.403686] meson-ir ff808000.ir: receiver initialized
1418 23:26:30.961214 <4>[ 14.405759] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1419 23:26:30.972309 <6>[ 14.406451] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1420 23:26:30.977888 <6>[ 14.426302] usbcore: registered new device driver onboard-usb-dev
1421 23:26:30.983449 <6>[ 14.431033] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1422 23:26:30.988978 <4>[ 14.458320] rc rc0: two consecutive events of type space
1423 23:26:31.000072 <6>[ 14.555095] Console: switching to colour frame buffer device 128x48
1424 23:26:31.004794 <6>[ 14.645868] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1425 23:26:31.241177 <6>[ 14.891892] hub 1-1:1.0: USB hub found
1426 23:26:31.246860 <6>[ 14.892188] hub 1-1:1.0: 4 ports detected
1427 23:26:31.389146 <4>[ 15.034321] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1428 23:26:31.394700 <3>[ 15.036717] onboard-usb-dev 1-1: Failed to suspend device, error -32
1429 23:26:31.400652 <3>[ 15.043135] onboard-usb-dev 1-1: can't set config #1, error -71
1430 23:26:31.417118 <4>[ 15.062315] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1431 23:26:31.422683 <6>[ 15.064628] onboard-usb-dev 1-1: USB disconnect, device number 2
1432 23:26:31.429295 <3>[ 15.070795] onboard-usb-dev 1-1: Failed to suspend device, error -32
1433 23:26:31.675886 <6>[ 15.322329] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1434 23:26:31.849317 <6>[ 15.500034] hub 1-1:1.0: USB hub found
1435 23:26:31.855041 <6>[ 15.500347] hub 1-1:1.0: 4 ports detected
1436 23:26:31.861721 Begin: Loading essential drivers ... done.
1437 23:26:31.867239 Begin: Running /scripts/init-premount ... done.
1438 23:26:31.872782 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1439 23:26:31.881856 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1440 23:26:31.885604 Device /sys/class/net/end0 found
1441 23:26:31.886070 done.
1442 23:26:31.896069 Begin: Waiting up to 180 secs for any network device to become available ... done.
1443 23:26:31.937147 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1444 23:26:31.942749 <6>[ 15.585714] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1445 23:26:32.012914 <6>[ 15.659904] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1446 23:26:32.032005 <6>[ 15.674446] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=25)
1447 23:26:32.045426 <6>[ 15.690551] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1448 23:26:32.051009 <6>[ 15.692759] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1449 23:26:32.060302 <6>[ 15.700330] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1450 23:26:32.269716 <6>[ 15.915900] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1451 23:26:33.089367 IP-Config: no response after 2 secs - giving up
1452 23:26:33.141891 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1453 23:26:35.024438 <6>[ 18.665692] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1454 23:26:36.171019 IP-Config: no response after 3 secs - giving up
1455 23:26:36.219760 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1456 23:26:36.229506 IP-Config: end0 guessed broadcast address 192.168.6.255
1457 23:26:36.235022 IP-Config: end0 complete (dhcp from 192.168.6.1):
1458 23:26:36.240480 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1459 23:26:36.249537 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1460 23:26:36.255062 rootserver: 192.168.6.1 rootpath:
1461 23:26:36.255638 filename :
1462 23:26:36.357592 done.
1463 23:26:36.367909 Begin: Running /scripts/nfs-bottom ... done.
1464 23:26:36.387563 Begin: Running /scripts/init-bottom ... done.
1465 23:26:36.701158 <30>[ 20.347225] systemd[1]: System time before build time, advancing clock.
1466 23:26:36.751087 <6>[ 20.401503] NET: Registered PF_INET6 protocol family
1467 23:26:36.756445 <6>[ 20.403740] Segment Routing with IPv6
1468 23:26:36.761627 <6>[ 20.405009] In-situ OAM (IOAM) with IPv6
1469 23:26:36.837234 <30>[ 20.460168] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1470 23:26:36.842837 <30>[ 20.487558] systemd[1]: Detected architecture arm64.
1471 23:26:36.843293
1472 23:26:36.850221 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1473 23:26:36.850664
1474 23:26:36.861247 <30>[ 20.507983] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1475 23:26:37.552398 <30>[ 21.198060] systemd[1]: Queued start job for default target graphical.target.
1476 23:26:37.595591 <30>[ 21.240676] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1477 23:26:37.604107 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1478 23:26:37.615279 <30>[ 21.259251] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1479 23:26:37.622599 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1480 23:26:37.634253 <30>[ 21.279327] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1481 23:26:37.643226 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1482 23:26:37.654225 <30>[ 21.299050] systemd[1]: Created slice user.slice - User and Session Slice.
1483 23:26:37.660595 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1484 23:26:37.674545 <30>[ 21.314553] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1485 23:26:37.680414 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1486 23:26:37.691423 <30>[ 21.334491] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1487 23:26:37.703459 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1488 23:26:37.720128 <30>[ 21.354462] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1489 23:26:37.725670 <30>[ 21.368525] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1490 23:26:37.738884 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1491 23:26:37.744461 <30>[ 21.390378] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1492 23:26:37.752427 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1493 23:26:37.769355 <30>[ 21.414467] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1494 23:26:37.782912 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1495 23:26:37.788479 <30>[ 21.434424] systemd[1]: Reached target paths.target - Path Units.
1496 23:26:37.796891 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1497 23:26:37.802452 <30>[ 21.450391] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1498 23:26:37.814206 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1499 23:26:37.819759 <30>[ 21.466378] systemd[1]: Reached target slices.target - Slice Units.
1500 23:26:37.827924 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1501 23:26:37.833482 <30>[ 21.482404] systemd[1]: Reached target swap.target - Swaps.
1502 23:26:37.841287 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1503 23:26:37.853223 <30>[ 21.498402] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1504 23:26:37.862264 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1505 23:26:37.877464 <30>[ 21.522590] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1506 23:26:37.886686 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1507 23:26:37.899552 <30>[ 21.544706] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1508 23:26:37.908339 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1509 23:26:37.922183 <30>[ 21.567318] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1510 23:26:37.935204 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1511 23:26:37.940761 <30>[ 21.586732] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1512 23:26:37.947567 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1513 23:26:37.958618 <30>[ 21.603302] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1514 23:26:37.964222 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1515 23:26:37.979121 <30>[ 21.624292] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1516 23:26:37.984687 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1517 23:26:37.997480 <30>[ 21.642621] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1518 23:26:38.005959 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1519 23:26:38.045391 <30>[ 21.690526] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1520 23:26:38.052284 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1521 23:26:38.064021 <30>[ 21.709020] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1522 23:26:38.071561 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1523 23:26:38.087528 <30>[ 21.732693] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1524 23:26:38.096016 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1525 23:26:38.114386 <30>[ 21.751056] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1526 23:26:38.125465 <30>[ 21.767436] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1527 23:26:38.130800 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1528 23:26:38.148812 <30>[ 21.793994] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1529 23:26:38.156774 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1530 23:26:38.170957 <30>[ 21.816089] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1531 23:26:38.178651 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1532 23:26:38.193886 <6>[ 21.839018] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1533 23:26:38.204960 <30>[ 21.842724] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1534 23:26:38.209872 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1535 23:26:38.229160 <30>[ 21.874268] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1536 23:26:38.236741 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1537 23:26:38.255749 <30>[ 21.900891] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1538 23:26:38.263025 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1539 23:26:38.279248 <30>[ 21.924348] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1540 23:26:38.288711 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
<6>[ 21.935533] fuse: init (API version 7.41)
1541 23:26:38.289263
1542 23:26:38.311268 <30>[ 21.956372] systemd[1]: Starting systemd-journald.service - Journal Service...
1543 23:26:38.317626 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1544 23:26:38.336543 <30>[ 21.981670] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1545 23:26:38.344068 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1546 23:26:38.355318 <30>[ 22.000426] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1547 23:26:38.364690 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1548 23:26:38.379659 <30>[ 22.024843] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1549 23:26:38.388501 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1550 23:26:38.409487 <30>[ 22.054575] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1551 23:26:38.417461 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1552 23:26:38.436508 <30>[ 22.081631] systemd[1]: Started systemd-journald.service - Journal Service.
1553 23:26:38.443331 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1554 23:26:38.454773 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1555 23:26:38.469030 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1556 23:26:38.481215 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1557 23:26:38.494247 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1558 23:26:38.506496 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1559 23:26:38.518471 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1560 23:26:38.530262 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1561 23:26:38.542480 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1562 23:26:38.554267 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1563 23:26:38.566487 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1564 23:26:38.578197 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1565 23:26:38.590216 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1566 23:26:38.602126 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1567 23:26:38.614543 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1568 23:26:38.664228 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1569 23:26:38.670751 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1570 23:26:38.687333 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1571 23:26:38.699649 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1572 23:26:38.716813 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1573 23:26:38.727813 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1574 23:26:38.743449 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1575 23:26:38.751689 <46>[ 22.396857] systemd-journald[235]: Received client request to flush runtime journal.
1576 23:26:38.762673 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1577 23:26:38.776394 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1578 23:26:38.788187 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1579 23:26:38.799204 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1580 23:26:38.811108 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1581 23:26:38.857349 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1582 23:26:39.037526 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1583 23:26:39.044906 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1584 23:26:39.061223 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1585 23:26:39.128360 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1586 23:26:39.147971 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1587 23:26:39.162167 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1588 23:26:39.323108 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1589 23:26:39.381303 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1590 23:26:39.432256 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1591 23:26:39.472258 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1592 23:26:39.526296 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1593 23:26:39.531804 <5>[ 23.178731] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1594 23:26:39.539839 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1595 23:26:39.578155 <5>[ 23.223100] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1596 23:26:39.583489 <5>[ 23.224130] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1597 23:26:39.589021 <4>[ 23.232180] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1598 23:26:39.597243 <6>[ 23.240269] cfg80211: failed to load regulatory.db
1599 23:26:39.608684 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1600 23:26:39.674042 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1601 23:26:39.680618 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1602 23:26:39.707264 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1603 23:26:39.749302 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1604 23:26:39.756970 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1605 23:26:39.783646 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1606 23:26:39.807043 <46>[ 23.441180] systemd-journald[235]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1607 23:26:39.820921 <46>[ 23.453676] systemd-journald[235]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1608 23:26:39.857119 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1609 23:26:39.875242 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1610 23:26:39.886767 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1611 23:26:39.955944 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1612 23:26:39.967432 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1613 23:26:39.986058 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1614 23:26:39.992870 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1615 23:26:40.026493 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1616 23:26:40.053465 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1617 23:26:40.061942 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1618 23:26:40.081028 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1619 23:26:40.092328 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1620 23:26:40.105939 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1621 23:26:40.124691 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1622 23:26:40.132195 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1623 23:26:40.138959 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1624 23:26:40.148863 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1625 23:26:40.189408 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1626 23:26:40.205024 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1627 23:26:40.227831 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1628 23:26:40.254110 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1629 23:26:40.270276 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1630 23:26:40.285593 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1631 23:26:40.300552 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1632 23:26:40.314693 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1633 23:26:40.333502 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1634 23:26:40.352041 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1635 23:26:40.400309 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1636 23:26:40.414022 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1637 23:26:40.431793 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1638 23:26:40.438643 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1639 23:26:40.454146 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1640 23:26:40.470405 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1641 23:26:40.517572 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1642 23:26:40.565473 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1643 23:26:40.648225
1644 23:26:40.648869 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1645 23:26:40.649348
1646 23:26:40.655314 debian-bookworm-arm64 login: root (automatic login)
1647 23:26:40.655882
1648 23:26:40.807739 Linux debian-bookworm-arm64 6.12.0-rc6 #1 SMP PREEMPT Wed Nov 6 21:27:37 UTC 2024 aarch64
1649 23:26:40.808417
1650 23:26:40.813322 The programs included with the Debian GNU/Linux system are free software;
1651 23:26:40.819017 the exact distribution terms for each program are described in the
1652 23:26:40.824402 individual files in /usr/share/doc/*/copyright.
1653 23:26:40.824965
1654 23:26:40.829938 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1655 23:26:40.833124 permitted by applicable law.
1656 23:26:41.494668 Matched prompt #10: / #
1658 23:26:41.496391 Setting prompt string to ['/ #']
1659 23:26:41.497000 end: 2.4.4.1 login-action (duration 00:00:26) [common]
1661 23:26:41.498481 end: 2.4.4 auto-login-action (duration 00:00:26) [common]
1662 23:26:41.499063 start: 2.4.5 expect-shell-connection (timeout 00:03:16) [common]
1663 23:26:41.499540 Setting prompt string to ['/ #']
1664 23:26:41.500010 Forcing a shell prompt, looking for ['/ #']
1666 23:26:41.551041 / #
1667 23:26:41.551678 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1668 23:26:41.552211 Waiting using forced prompt support (timeout 00:02:30)
1669 23:26:41.558615
1670 23:26:41.559496 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1671 23:26:41.560138 start: 2.4.6 export-device-env (timeout 00:03:16) [common]
1672 23:26:41.560646 Sending with 10 millisecond of delay
1674 23:26:46.549759 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/949203/extract-nfsrootfs-ql3hr6om'
1675 23:26:46.560798 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/949203/extract-nfsrootfs-ql3hr6om'
1676 23:26:46.561647 Sending with 10 millisecond of delay
1678 23:26:48.659759 / # export NFS_SERVER_IP='192.168.6.2'
1679 23:26:48.670770 export NFS_SERVER_IP='192.168.6.2'
1680 23:26:48.671690 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1681 23:26:48.672377 end: 2.4 uboot-commands (duration 00:01:51) [common]
1682 23:26:48.673021 end: 2 uboot-action (duration 00:01:51) [common]
1683 23:26:48.673635 start: 3 lava-test-retry (timeout 00:06:50) [common]
1684 23:26:48.674271 start: 3.1 lava-test-shell (timeout 00:06:50) [common]
1685 23:26:48.674780 Using namespace: common
1687 23:26:48.776062 / # #
1688 23:26:48.776798 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1689 23:26:48.781244 #
1690 23:26:48.782126 Using /lava-949203
1692 23:26:48.883420 / # export SHELL=/bin/bash
1693 23:26:48.889189 export SHELL=/bin/bash
1695 23:26:48.990771 / # . /lava-949203/environment
1696 23:26:48.995906 . /lava-949203/environment
1698 23:26:49.100497 / # /lava-949203/bin/lava-test-runner /lava-949203/0
1699 23:26:49.101608 Test shell timeout: 10s (minimum of the action and connection timeout)
1700 23:26:49.104614 /lava-949203/bin/lava-test-runner /lava-949203/0
1701 23:26:49.316542 + export TESTRUN_ID=0_timesync-off
1702 23:26:49.324446 + TESTRUN_ID=0_timesync-off
1703 23:26:49.325008 + cd /lava-949203/0/tests/0_timesync-off
1704 23:26:49.325475 ++ cat uuid
1705 23:26:49.331266 + UUID=949203_1.6.2.4.1
1706 23:26:49.331757 + set +x
1707 23:26:49.339753 <LAVA_SIGNAL_STARTRUN 0_timesync-off 949203_1.6.2.4.1>
1708 23:26:49.340335 + systemctl stop systemd-timesyncd
1709 23:26:49.341097 Received signal: <STARTRUN> 0_timesync-off 949203_1.6.2.4.1
1710 23:26:49.341591 Starting test lava.0_timesync-off (949203_1.6.2.4.1)
1711 23:26:49.342201 Skipping test definition patterns.
1712 23:26:49.385912 + set +x
1713 23:26:49.386545 <LAVA_SIGNAL_ENDRUN 0_timesync-off 949203_1.6.2.4.1>
1714 23:26:49.387269 Received signal: <ENDRUN> 0_timesync-off 949203_1.6.2.4.1
1715 23:26:49.387804 Ending use of test pattern.
1716 23:26:49.388284 Ending test lava.0_timesync-off (949203_1.6.2.4.1), duration 0.05
1718 23:26:49.479033 + export TESTRUN_ID=1_kselftest-alsa
1719 23:26:49.487500 + TESTRUN_ID=1_kselftest-alsa
1720 23:26:49.488057 + cd /lava-949203/0/tests/1_kselftest-alsa
1721 23:26:49.488514 ++ cat uuid
1722 23:26:49.496388 + UUID=949203_1.6.2.4.5
1723 23:26:49.496875 + set +x
1724 23:26:49.502045 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 949203_1.6.2.4.5>
1725 23:26:49.502520 + cd ./automated/linux/kselftest/
1726 23:26:49.503243 Received signal: <STARTRUN> 1_kselftest-alsa 949203_1.6.2.4.5
1727 23:26:49.503704 Starting test lava.1_kselftest-alsa (949203_1.6.2.4.5)
1728 23:26:49.504276 Skipping test definition patterns.
1729 23:26:49.531018 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1730 23:26:49.558201 INFO: install_deps skipped
1731 23:26:49.667332 --2024-11-06 23:26:49-- http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/kselftest.tar.xz
1732 23:26:49.689486 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1733 23:26:49.835446 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1734 23:26:49.988556 HTTP request sent, awaiting response... 200 OK
1735 23:26:49.989207 Length: 6928700 (6.6M) [application/octet-stream]
1736 23:26:49.994067 Saving to: 'kselftest_armhf.tar.gz'
1737 23:26:49.994545
1738 23:26:51.181081
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 49.92K 174KB/s
kselftest_armhf.tar 3%[ ] 218.67K 380KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.01MB/s
kselftest_armhf.tar 53%[=========> ] 3.51M 3.05MB/s
kselftest_armhf.tar 100%[===================>] 6.61M 5.56MB/s in 1.2s
1739 23:26:51.181773
1740 23:26:51.272345 2024-11-06 23:26:51 (5.56 MB/s) - 'kselftest_armhf.tar.gz' saved [6928700/6928700]
1741 23:26:51.273043
1742 23:27:00.438366 skiplist:
1743 23:27:00.439023 ========================================
1744 23:27:00.443826 ========================================
1745 23:27:00.489762 alsa:mixer-test
1746 23:27:00.490378 alsa:pcm-test
1747 23:27:00.490837 alsa:test-pcmtest-driver
1748 23:27:00.493839 alsa:utimer-test
1749 23:27:00.506169 ============== Tests to run ===============
1750 23:27:00.506681 alsa:mixer-test
1751 23:27:00.511646 alsa:pcm-test
1752 23:27:00.512198 alsa:test-pcmtest-driver
1753 23:27:00.512652 alsa:utimer-test
1754 23:27:00.519884 ===========End Tests to run ===============
1755 23:27:00.520423 shardfile-alsa pass
1756 23:27:00.640631 <12>[ 44.289907] kselftest: Running tests in alsa
1757 23:27:00.648724 TAP version 13
1758 23:27:00.658658 1..4
1759 23:27:00.681602 # timeout set to 45
1760 23:27:00.682122 # selftests: alsa: mixer-test
1761 23:27:00.822099 # TAP version 13
1762 23:27:00.822752 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1763 23:27:00.827520 # 1..427
1764 23:27:00.827847 # ok 1 get_value.LCALTA.60
1765 23:27:00.828408 # # LCALTA.60 TDMOUT_A SRC SEL
1766 23:27:00.833135 # ok 2 name.LCALTA.60
1767 23:27:00.833650 # ok 3 write_default.LCALTA.60
1768 23:27:00.838711 # ok 4 write_valid.LCALTA.60
1769 23:27:00.839215 # ok 5 write_invalid.LCALTA.60
1770 23:27:00.844272 # ok 6 event_missing.LCALTA.60
1771 23:27:00.844942 # ok 7 event_spurious.LCALTA.60
1772 23:27:00.849880 # ok 8 get_value.LCALTA.59
1773 23:27:00.850473 # # LCALTA.59 TDMOUT_B SRC SEL
1774 23:27:00.855378 # ok 9 name.LCALTA.59
1775 23:27:00.855972 # ok 10 write_default.LCALTA.59
1776 23:27:00.860945 # ok 11 write_valid.LCALTA.59
1777 23:27:00.861534 # ok 12 write_invalid.LCALTA.59
1778 23:27:00.866379 # ok 13 event_missing.LCALTA.59
1779 23:27:00.866966 # ok 14 event_spurious.LCALTA.59
1780 23:27:00.872116 # ok 15 get_value.LCALTA.58
1781 23:27:00.872711 # # LCALTA.58 TDMOUT_C SRC SEL
1782 23:27:00.877544 # ok 16 name.LCALTA.58
1783 23:27:00.878140 # ok 17 write_default.LCALTA.58
1784 23:27:00.883012 # ok 18 write_valid.LCALTA.58
1785 23:27:00.883619 # ok 19 write_invalid.LCALTA.58
1786 23:27:00.888534 # ok 20 event_missing.LCALTA.58
1787 23:27:00.889133 # ok 21 event_spurious.LCALTA.58
1788 23:27:00.894179 # ok 22 get_value.LCALTA.57
1789 23:27:00.894789 # # LCALTA.57 TDMIN_A SRC SEL
1790 23:27:00.895339 # ok 23 name.LCALTA.57
1791 23:27:00.899754 # ok 24 write_default.LCALTA.57
1792 23:27:00.900456 # ok 25 write_valid.LCALTA.57
1793 23:27:00.905313 # ok 26 write_invalid.LCALTA.57
1794 23:27:00.905950 # ok 27 event_missing.LCALTA.57
1795 23:27:00.910895 # ok 28 event_spurious.LCALTA.57
1796 23:27:00.911567 # ok 29 get_value.LCALTA.56
1797 23:27:00.916363 # # LCALTA.56 TDMIN_B SRC SEL
1798 23:27:00.916982 # ok 30 name.LCALTA.56
1799 23:27:00.921953 # ok 31 write_default.LCALTA.56
1800 23:27:00.932985 # ok 32 write_val<3>[ 44.571511] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1801 23:27:00.933663 id.LCALTA.56
1802 23:27:00.938431 # ok 33 write_invalid.LCALTA.56
1803 23:27:00.939054 # ok 34 event_missing.LCALTA.56
1804 23:27:00.944040 # ok 35 event_spurious.LCALTA.56
1805 23:27:00.944648 # ok 36 get_value.LCALTA.55
1806 23:27:00.949592 # # LCALTA.55 TDMIN_C SRC SEL
1807 23:27:00.950298 # ok 37 name.LCALTA.55
1808 23:27:00.955084 # ok 38 write_default.LCALTA.55
1809 23:27:00.955485 # ok 39 write_valid.LCALTA.55
1810 23:27:00.960639 # ok 40 write_invalid.LCALTA.55
1811 23:27:00.961341 # ok 41 event_missing.LCALTA.55
1812 23:27:00.966263 # ok 42 event_spurious.LCALTA.55
1813 23:27:00.966941 # ok 43 get_value.LCALTA.54
1814 23:27:00.971765 # # LCALTA.54 ACODEC Left DAC Sel
1815 23:27:00.972539 # ok 44 name.LCALTA.54
1816 23:27:00.977287 # ok 45 write_default.LCALTA.54
1817 23:27:00.977959 # ok 46 write_valid.LCALTA.54
1818 23:27:00.982818 # ok 47 write_invalid.LCALTA.54
1819 23:27:00.983489 # ok 48 event_missing.LCALTA.54
1820 23:27:00.988385 # ok 49 event_spurious.LCALTA.54
1821 23:27:00.989069 # ok 50 get_value.LCALTA.53
1822 23:27:00.993908 # # LCALTA.53 ACODEC Right DAC Sel
1823 23:27:00.994513 # ok 51 name.LCALTA.53
1824 23:27:00.999475 # ok 52 write_default.LCALTA.53
1825 23:27:01.000098 # ok 53 write_valid.LCALTA.53
1826 23:27:01.005024 # ok 54 write_invalid.LCALTA.53
1827 23:27:01.005662 # ok 55 event_missing.LCALTA.53
1828 23:27:01.010541 # ok 56 event_spurious.LCALTA.53
1829 23:27:01.011139 # ok 57 get_value.LCALTA.52
1830 23:27:01.016108 # # LCALTA.52 TOACODEC OUT EN Switch
1831 23:27:01.016722 # ok 58 name.LCALTA.52
1832 23:27:01.021666 # ok 59 write_default.LCALTA.52
1833 23:27:01.022293 # ok 60 write_valid.LCALTA.52
1834 23:27:01.027187 # ok 61 write_invalid.LCALTA.52
1835 23:27:01.027813 # ok 62 event_missing.LCALTA.52
1836 23:27:01.032742 # ok 63 event_spurious.LCALTA.52
1837 23:27:01.033352 # ok 64 get_value.LCALTA.51
1838 23:27:01.038327 # # LCALTA.51 TOACODEC SRC
1839 23:27:01.038988 # ok 65 name.LCALTA.51
1840 23:27:01.043841 # ok 66 write_default.LCALTA.51
1841 23:27:01.044764 # ok 67 write_valid.LCALTA.51
1842 23:27:01.049375 # ok 68 write_invalid.LCALTA.51
1843 23:27:01.049994 # ok 69 event_missing.LCALTA.51
1844 23:27:01.054928 # ok 70 event_spurious.LCALTA.51
1845 23:27:01.055532 # ok 71 get_value.LCALTA.50
1846 23:27:01.060445 # # LCALTA.50 TOHDMITX SPDIF SRC
1847 23:27:01.061063 # ok 72 name.LCALTA.50
1848 23:27:01.061612 # ok 73 write_default.LCALTA.50
1849 23:27:01.066031 # ok 74 write_valid.LCALTA.50
1850 23:27:01.066628 # ok 75 write_invalid.LCALTA.50
1851 23:27:01.071578 # ok 76 event_missing.LCALTA.50
1852 23:27:01.077135 # ok 77 event_spurious.LCALTA.50
1853 23:27:01.077808 # ok 78 get_value.LCALTA.49
1854 23:27:01.078362 # # LCALTA.49 TOHDMITX Switch
1855 23:27:01.082646 # ok 79 name.LCALTA.49
1856 23:27:01.083252 # ok 80 write_default.LCALTA.49
1857 23:27:01.088230 # ok 81 write_valid.LCALTA.49
1858 23:27:01.088824 # ok 82 write_invalid.LCALTA.49
1859 23:27:01.093741 # ok 83 event_missing.LCALTA.49
1860 23:27:01.094334 # ok 84 event_spurious.LCALTA.49
1861 23:27:01.099284 # ok 85 get_value.LCALTA.48
1862 23:27:01.099870 # # LCALTA.48 TOHDMITX I2S SRC
1863 23:27:01.104839 # ok 86 name.LCALTA.48
1864 23:27:01.105458 # ok 87 write_default.LCALTA.48
1865 23:27:01.110369 # ok 88 write_valid.LCALTA.48
1866 23:27:01.110976 # ok 89 write_invalid.LCALTA.48
1867 23:27:01.115939 # ok 90 event_missing.LCALTA.48
1868 23:27:01.116567 # ok 91 event_spurious.LCALTA.48
1869 23:27:01.121466 # ok 92 get_value.LCALTA.47
1870 23:27:01.122062 # # LCALTA.47 TODDR_C SRC SEL
1871 23:27:01.127054 # ok 93 name.LCALTA.47
1872 23:27:01.127657 # ok 94 write_default.LCALTA.47
1873 23:27:01.132570 # ok 95 write_valid.LCALTA.47
1874 23:27:01.133171 # ok 96 write_invalid.LCALTA.47
1875 23:27:01.138127 # ok 97 event_missing.LCALTA.47
1876 23:27:01.138720 # ok 98 event_spurious.LCALTA.47
1877 23:27:01.143692 # ok 99 get_value.LCALTA.46
1878 23:27:01.144361 # # LCALTA.46 TODDR_B SRC SEL
1879 23:27:01.144913 # ok 100 name.LCALTA.46
1880 23:27:01.149211 # ok 101 write_default.LCALTA.46
1881 23:27:01.154753 # ok 102 write_valid.LCALTA.46
1882 23:27:01.155345 # ok 103 write_invalid.LCALTA.46
1883 23:27:01.160286 # ok 104 event_missing.LCALTA.46
1884 23:27:01.160894 # ok 105 event_spurious.LCALTA.46
1885 23:27:01.165848 # ok 106 get_value.LCALTA.45
1886 23:27:01.166463 # # LCALTA.45 TODDR_A SRC SEL
1887 23:27:01.167003 # ok 107 name.LCALTA.45
1888 23:27:01.171401 # ok 108 write_default.LCALTA.45
1889 23:27:01.176885 # ok 109 write_valid.LCALTA.45
1890 23:27:01.177504 # ok 110 write_invalid.LCALTA.45
1891 23:27:01.182559 # ok 111 event_missing.LCALTA.45
1892 23:27:01.183253 # ok 112 event_spurious.LCALTA.45
1893 23:27:01.188074 # ok 113 get_value.LCALTA.44
1894 23:27:01.188689 # # LCALTA.44 FRDDR_C SINK 3 SEL
1895 23:27:01.193610 # ok 114 name.LCALTA.44
1896 23:27:01.194249 # ok 115 write_default.LCALTA.44
1897 23:27:01.199144 # ok 116 write_valid.LCALTA.44
1898 23:27:01.199752 # ok 117 write_invalid.LCALTA.44
1899 23:27:01.204679 # ok 118 event_missing.LCALTA.44
1900 23:27:01.205314 # ok 119 event_spurious.LCALTA.44
1901 23:27:01.210210 # ok 120 get_value.LCALTA.43
1902 23:27:01.210815 # # LCALTA.43 FRDDR_C SINK 2 SEL
1903 23:27:01.215741 # ok 121 name.LCALTA.43
1904 23:27:01.216234 # ok 122 write_default.LCALTA.43
1905 23:27:01.221292 # ok 123 write_valid.LCALTA.43
1906 23:27:01.221923 # ok 124 write_invalid.LCALTA.43
1907 23:27:01.226829 # ok 125 event_missing.LCALTA.43
1908 23:27:01.227434 # ok 126 event_spurious.LCALTA.43
1909 23:27:01.232412 # ok 127 get_value.LCALTA.42
1910 23:27:01.233029 # # LCALTA.42 FRDDR_C SINK 1 SEL
1911 23:27:01.237980 # ok 128 name.LCALTA.42
1912 23:27:01.238617 # ok 129 write_default.LCALTA.42
1913 23:27:01.243510 # ok 130 write_valid.LCALTA.42
1914 23:27:01.243855 # ok 131 write_invalid.LCALTA.42
1915 23:27:01.249077 # ok 132 event_missing.LCALTA.42
1916 23:27:01.249567 # ok 133 event_spurious.LCALTA.42
1917 23:27:01.254591 # ok 134 get_value.LCALTA.41
1918 23:27:01.255070 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1919 23:27:01.260207 # ok 135 name.LCALTA.41
1920 23:27:01.260696 # ok 136 write_default.LCALTA.41
1921 23:27:01.265722 # ok 137 write_valid.LCALTA.41
1922 23:27:01.266193 # ok 138 write_invalid.LCALTA.41
1923 23:27:01.271224 # ok 139 event_missing.LCALTA.41
1924 23:27:01.271703 # ok 140 event_spurious.LCALTA.41
1925 23:27:01.276785 # ok 141 get_value.LCALTA.40
1926 23:27:01.277265 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1927 23:27:01.282336 # ok 142 name.LCALTA.40
1928 23:27:01.282859 # ok 143 write_default.LCALTA.40
1929 23:27:01.287884 # ok 144 write_valid.LCALTA.40
1930 23:27:01.288455 # ok 145 write_invalid.LCALTA.40
1931 23:27:01.293451 # ok 146 event_missing.LCALTA.40
1932 23:27:01.293928 # ok 147 event_spurious.LCALTA.40
1933 23:27:01.298974 # ok 148 get_value.LCALTA.39
1934 23:27:01.304534 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1935 23:27:01.305006 # ok 149 name.LCALTA.39
1936 23:27:01.305403 # ok 150 write_default.LCALTA.39
1937 23:27:01.310113 # ok 151 write_valid.LCALTA.39
1938 23:27:01.310633 # ok 152 write_invalid.LCALTA.39
1939 23:27:01.315698 # ok 153 event_missing.LCALTA.39
1940 23:27:01.321162 # ok 154 event_spurious.LCALTA.39
1941 23:27:01.321625 # ok 155 get_value.LCALTA.38
1942 23:27:01.326756 # # LCALTA.38 FRDDR_B SINK 3 SEL
1943 23:27:01.327250 # ok 156 name.LCALTA.38
1944 23:27:01.327646 # ok 157 write_default.LCALTA.38
1945 23:27:01.332369 # ok 158 write_valid.LCALTA.38
1946 23:27:01.332815 # ok 159 write_invalid.LCALTA.38
1947 23:27:01.337804 # ok 160 event_missing.LCALTA.38
1948 23:27:01.343356 # ok 161 event_spurious.LCALTA.38
1949 23:27:01.343785 # ok 162 get_value.LCALTA.37
1950 23:27:01.348919 # # LCALTA.37 FRDDR_B SINK 2 SEL
1951 23:27:01.349419 # ok 163 name.LCALTA.37
1952 23:27:01.349811 # ok 164 write_default.LCALTA.37
1953 23:27:01.354421 # ok 165 write_valid.LCALTA.37
1954 23:27:01.360014 # ok 166 write_invalid.LCALTA.37
1955 23:27:01.360531 # ok 167 event_missing.LCALTA.37
1956 23:27:01.365538 # ok 168 event_spurious.LCALTA.37
1957 23:27:01.365978 # ok 169 get_value.LCALTA.36
1958 23:27:01.371073 # # LCALTA.36 FRDDR_B SINK 1 SEL
1959 23:27:01.371522 # ok 170 name.LCALTA.36
1960 23:27:01.376717 # ok 171 write_default.LCALTA.36
1961 23:27:01.377224 # ok 172 write_valid.LCALTA.36
1962 23:27:01.382186 # ok 173 write_invalid.LCALTA.36
1963 23:27:01.382640 # ok 174 event_missing.LCALTA.36
1964 23:27:01.387754 # ok 175 event_spurious.LCALTA.36
1965 23:27:01.388243 # ok 176 get_value.LCALTA.35
1966 23:27:01.393239 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1967 23:27:01.393692 # ok 177 name.LCALTA.35
1968 23:27:01.398830 # ok 178 write_default.LCALTA.35
1969 23:27:01.399329 # ok 179 write_valid.LCALTA.35
1970 23:27:01.404347 # ok 180 write_invalid.LCALTA.35
1971 23:27:01.404798 # ok 181 event_missing.LCALTA.35
1972 23:27:01.409881 # ok 182 event_spurious.LCALTA.35
1973 23:27:01.410322 # ok 183 get_value.LCALTA.34
1974 23:27:01.415443 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1975 23:27:01.415898 # ok 184 name.LCALTA.34
1976 23:27:01.420974 # ok 185 write_default.LCALTA.34
1977 23:27:01.421466 # ok 186 write_valid.LCALTA.34
1978 23:27:01.426559 # ok 187 write_invalid.LCALTA.34
1979 23:27:01.427055 # ok 188 event_missing.LCALTA.34
1980 23:27:01.432081 # ok 189 event_spurious.LCALTA.34
1981 23:27:01.432554 # ok 190 get_value.LCALTA.33
1982 23:27:01.437710 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1983 23:27:01.438187 # ok 191 name.LCALTA.33
1984 23:27:01.443189 # ok 192 write_default.LCALTA.33
1985 23:27:01.443660 # ok 193 write_valid.LCALTA.33
1986 23:27:01.448700 # ok 194 write_invalid.LCALTA.33
1987 23:27:01.449176 # ok 195 event_missing.LCALTA.33
1988 23:27:01.454319 # ok 196 event_spurious.LCALTA.33
1989 23:27:01.454826 # ok 197 get_value.LCALTA.32
1990 23:27:01.459849 # # LCALTA.32 FRDDR_A SINK 3 SEL
1991 23:27:01.460351 # ok 198 name.LCALTA.32
1992 23:27:01.465350 # ok 199 write_default.LCALTA.32
1993 23:27:01.465824 # ok 200 write_valid.LCALTA.32
1994 23:27:01.470925 # ok 201 write_invalid.LCALTA.32
1995 23:27:01.471403 # ok 202 event_missing.LCALTA.32
1996 23:27:01.476462 # ok 203 event_spurious.LCALTA.32
1997 23:27:01.476929 # ok 204 get_value.LCALTA.31
1998 23:27:01.481993 # # LCALTA.31 FRDDR_A SINK 2 SEL
1999 23:27:01.482460 # ok 205 name.LCALTA.31
2000 23:27:01.487549 # ok 206 write_default.LCALTA.31
2001 23:27:01.488043 # ok 207 write_valid.LCALTA.31
2002 23:27:01.493104 # ok 208 write_invalid.LCALTA.31
2003 23:27:01.493580 # ok 209 event_missing.LCALTA.31
2004 23:27:01.498751 # ok 210 event_spurious.LCALTA.31
2005 23:27:01.499274 # ok 211 get_value.LCALTA.30
2006 23:27:01.504239 # # LCALTA.30 FRDDR_A SINK 1 SEL
2007 23:27:01.504734 # ok 212 name.LCALTA.30
2008 23:27:01.509762 # ok 213 write_default.LCALTA.30
2009 23:27:01.510227 # ok 214 write_valid.LCALTA.30
2010 23:27:01.515300 # ok 215 write_invalid.LCALTA.30
2011 23:27:01.520837 # ok 216 event_missing.LCALTA.30
2012 23:27:01.521301 # ok 217 event_spurious.LCALTA.30
2013 23:27:01.526364 # ok 218 get_value.LCALTA.29
2014 23:27:01.526833 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2015 23:27:01.531925 # ok 219 name.LCALTA.29
2016 23:27:01.532415 # ok 220 write_default.LCALTA.29
2017 23:27:01.537489 # ok 221 write_valid.LCALTA.29
2018 23:27:01.537956 # ok 222 write_invalid.LCALTA.29
2019 23:27:01.543021 # ok 223 event_missing.LCALTA.29
2020 23:27:01.543490 # ok 224 event_spurious.LCALTA.29
2021 23:27:01.548561 # ok 225 get_value.LCALTA.28
2022 23:27:01.549029 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2023 23:27:01.554095 # ok 226 name.LCALTA.28
2024 23:27:01.554553 # ok 227 write_default.LCALTA.28
2025 23:27:01.559730 # ok 228 write_valid.LCALTA.28
2026 23:27:01.560240 # ok 229 write_invalid.LCALTA.28
2027 23:27:01.565240 # ok 230 event_missing.LCALTA.28
2028 23:27:01.565721 # ok 231 event_spurious.LCALTA.28
2029 23:27:01.570762 # ok 232 get_value.LCALTA.27
2030 23:27:01.571221 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2031 23:27:01.576290 # ok 233 name.LCALTA.27
2032 23:27:01.576746 # ok 234 write_default.LCALTA.27
2033 23:27:01.581852 # ok 235 write_valid.LCALTA.27
2034 23:27:01.582314 # ok 236 write_invalid.LCALTA.27
2035 23:27:01.587397 # ok 237 event_missing.LCALTA.27
2036 23:27:01.587870 # ok 238 event_spurious.LCALTA.27
2037 23:27:01.592967 # ok 239 get_value.LCALTA.26
2038 23:27:01.593458 # # LCALTA.26 ELD
2039 23:27:01.598480 # ok 240 name.LCALTA.26
2040 23:27:01.598950 # # ELD is not writeable
2041 23:27:01.604052 # ok 241 # SKIP write_default.LCALTA.26
2042 23:27:01.604519 # # ELD is not writeable
2043 23:27:01.609603 # ok 242 # SKIP write_valid.LCALTA.26
2044 23:27:01.610076 # # ELD is not writeable
2045 23:27:01.615174 # ok 243 # SKIP write_invalid.LCALTA.26
2046 23:27:01.615712 # ok 244 event_missing.LCALTA.26
2047 23:27:01.620775 # ok 245 event_spurious.LCALTA.26
2048 23:27:01.621252 # ok 246 get_value.LCALTA.25
2049 23:27:01.626232 # # LCALTA.25 IEC958 Playback Default
2050 23:27:01.626698 # ok 247 name.LCALTA.25
2051 23:27:01.631770 # ok 248 write_default.LCALTA.25
2052 23:27:01.632268 # ok 249 # SKIP write_valid.LCALTA.25
2053 23:27:01.637319 # ok 250 # SKIP write_invalid.LCALTA.25
2054 23:27:01.642868 # ok 251 event_missing.LCALTA.25
2055 23:27:01.643337 # ok 252 event_spurious.LCALTA.25
2056 23:27:01.648387 # ok 253 get_value.LCALTA.24
2057 23:27:01.648860 # # LCALTA.24 IEC958 Playback Mask
2058 23:27:01.649276 # ok 254 name.LCALTA.24
2059 23:27:01.653940 # # IEC958 Playback Mask is not writeable
2060 23:27:01.659558 # ok 255 # SKIP write_default.LCALTA.24
2061 23:27:01.659912 # # IEC958 Playback Mask is not writeable
2062 23:27:01.665125 # ok 256 # SKIP write_valid.LCALTA.24
2063 23:27:01.670666 # # IEC958 Playback Mask is not writeable
2064 23:27:01.671182 # ok 257 # SKIP write_invalid.LCALTA.24
2065 23:27:01.676270 # ok 258 event_missing.LCALTA.24
2066 23:27:01.676791 # ok 259 event_spurious.LCALTA.24
2067 23:27:01.681796 # ok 260 get_value.LCALTA.23
2068 23:27:01.682299 # # LCALTA.23 Playback Channel Map
2069 23:27:01.687291 # ok 261 name.LCALTA.23
2070 23:27:01.692878 # # Playback Channel Map is not writeable
2071 23:27:01.693219 # ok 262 # SKIP write_default.LCALTA.23
2072 23:27:01.698470 # # Playback Channel Map is not writeable
2073 23:27:01.698996 # ok 263 # SKIP write_valid.LCALTA.23
2074 23:27:01.703950 # # Playback Channel Map is not writeable
2075 23:27:01.709551 # ok 264 # SKIP write_invalid.LCALTA.23
2076 23:27:01.710069 # ok 265 event_missing.LCALTA.23
2077 23:27:01.715072 # ok 266 event_spurious.LCALTA.23
2078 23:27:01.715581 # ok 267 get_value.LCALTA.22
2079 23:27:01.720582 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2080 23:27:01.721093 # ok 268 name.LCALTA.22
2081 23:27:01.726125 # ok 269 write_default.LCALTA.22
2082 23:27:01.726627 # ok 270 write_valid.LCALTA.22
2083 23:27:01.731693 # ok 271 write_invalid.LCALTA.22
2084 23:27:01.732235 # ok 272 event_missing.LCALTA.22
2085 23:27:01.737230 # ok 273 event_spurious.LCALTA.22
2086 23:27:01.742814 # ok 274 get_value.LCALTA.21
2087 23:27:01.743319 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2088 23:27:01.743717 # ok 275 name.LCALTA.21
2089 23:27:01.748324 # ok 276 write_default.LCALTA.21
2090 23:27:01.753879 # ok 277 write_valid.LCALTA.21
2091 23:27:01.754387 # ok 278 write_invalid.LCALTA.21
2092 23:27:01.759534 # ok 279 event_missing.LCALTA.21
2093 23:27:01.760101 # ok 280 event_spurious.LCALTA.21
2094 23:27:01.764957 # ok 281 get_value.LCALTA.20
2095 23:27:01.765465 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2096 23:27:01.770494 # ok 282 name.LCALTA.20
2097 23:27:01.771002 # ok 283 write_default.LCALTA.20
2098 23:27:01.776127 # ok 284 write_valid.LCALTA.20
2099 23:27:01.776633 # ok 285 write_invalid.LCALTA.20
2100 23:27:01.781621 # ok 286 event_missing.LCALTA.20
2101 23:27:01.782127 # ok 287 event_spurious.LCALTA.20
2102 23:27:01.787166 # ok 288 get_value.LCALTA.19
2103 23:27:01.787685 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2104 23:27:01.792694 # ok 289 name.LCALTA.19
2105 23:27:01.793197 # ok 290 write_default.LCALTA.19
2106 23:27:01.798248 # ok 291 write_valid.LCALTA.19
2107 23:27:01.798755 # ok 292 write_invalid.LCALTA.19
2108 23:27:01.803842 # ok 293 event_missing.LCALTA.19
2109 23:27:01.804386 # ok 294 event_spurious.LCALTA.19
2110 23:27:01.809342 # ok 295 get_value.LCALTA.18
2111 23:27:01.809855 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2112 23:27:01.814873 # ok 296 name.LCALTA.18
2113 23:27:01.815379 # ok 297 write_default.LCALTA.18
2114 23:27:01.820452 # ok 298 write_valid.LCALTA.18
2115 23:27:01.820958 # ok 299 write_invalid.LCALTA.18
2116 23:27:01.826012 # ok 300 event_missing.LCALTA.18
2117 23:27:01.826367 # ok 301 event_spurious.LCALTA.18
2118 23:27:01.831529 # ok 302 get_value.LCALTA.17
2119 23:27:01.837086 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2120 23:27:01.837601 # ok 303 name.LCALTA.17
2121 23:27:01.837995 # ok 304 write_default.LCALTA.17
2122 23:27:01.842612 # ok 305 write_valid.LCALTA.17
2123 23:27:01.848203 # ok 306 write_invalid.LCALTA.17
2124 23:27:01.848716 # ok 307 event_missing.LCALTA.17
2125 23:27:01.853750 # ok 308 event_spurious.LCALTA.17
2126 23:27:01.854259 # ok 309 get_value.LCALTA.16
2127 23:27:01.859258 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2128 23:27:01.859763 # ok 310 name.LCALTA.16
2129 23:27:01.864817 # ok 311 write_default.LCALTA.16
2130 23:27:01.865318 # ok 312 write_valid.LCALTA.16
2131 23:27:01.870341 # ok 313 write_invalid.LCALTA.16
2132 23:27:01.870841 # ok 314 event_missing.LCALTA.16
2133 23:27:01.875913 # ok 315 event_spurious.LCALTA.16
2134 23:27:01.876452 # ok 316 get_value.LCALTA.15
2135 23:27:01.881430 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2136 23:27:01.881943 # ok 317 name.LCALTA.15
2137 23:27:01.886990 # ok 318 write_default.LCALTA.15
2138 23:27:01.887491 # ok 319 write_valid.LCALTA.15
2139 23:27:01.892562 # ok 320 write_invalid.LCALTA.15
2140 23:27:01.893100 # ok 321 event_missing.LCALTA.15
2141 23:27:01.898095 # ok 322 event_spurious.LCALTA.15
2142 23:27:01.898606 # ok 323 get_value.LCALTA.14
2143 23:27:01.903658 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2144 23:27:01.904213 # ok 324 name.LCALTA.14
2145 23:27:01.909176 # ok 325 write_default.LCALTA.14
2146 23:27:01.909680 # ok 326 write_valid.LCALTA.14
2147 23:27:01.914733 # ok 327 write_invalid.LCALTA.14
2148 23:27:01.915255 # ok 328 event_missing.LCALTA.14
2149 23:27:01.920305 # ok 329 event_spurious.LCALTA.14
2150 23:27:01.920825 # ok 330 get_value.LCALTA.13
2151 23:27:01.925842 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2152 23:27:01.926383 # ok 331 name.LCALTA.13
2153 23:27:01.931400 # ok 332 write_default.LCALTA.13
2154 23:27:01.931929 # ok 333 write_valid.LCALTA.13
2155 23:27:01.936855 # ok 334 write_invalid.LCALTA.13
2156 23:27:01.937371 # ok 335 event_missing.LCALTA.13
2157 23:27:01.942478 # ok 336 event_spurious.LCALTA.13
2158 23:27:01.942996 # ok 337 get_value.LCALTA.12
2159 23:27:01.948022 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2160 23:27:01.948531 # ok 338 name.LCALTA.12
2161 23:27:01.953566 # ok 339 write_default.LCALTA.12
2162 23:27:01.959099 # ok 340 write_valid.LCALTA.12
2163 23:27:01.959598 # ok 341 write_invalid.LCALTA.12
2164 23:27:01.964653 # ok 342 event_missing.LCALTA.12
2165 23:27:01.965161 # ok 343 event_spurious.LCALTA.12
2166 23:27:01.970120 # ok 344 get_value.LCALTA.11
2167 23:27:01.970657 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2168 23:27:01.975766 # ok 345 name.LCALTA.11
2169 23:27:01.976314 # ok 346 write_default.LCALTA.11
2170 23:27:01.981295 # ok 347 write_valid.LCALTA.11
2171 23:27:01.981602 # ok 348 write_invalid.LCALTA.11
2172 23:27:01.986852 # ok 349 event_missing.LCALTA.11
2173 23:27:01.987401 # ok 350 event_spurious.LCALTA.11
2174 23:27:01.992362 # ok 351 get_value.LCALTA.10
2175 23:27:01.992729 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2176 23:27:01.997947 # ok 352 name.LCALTA.10
2177 23:27:01.998304 # ok 353 write_default.LCALTA.10
2178 23:27:02.003397 # ok 354 write_valid.LCALTA.10
2179 23:27:02.003750 # ok 355 write_invalid.LCALTA.10
2180 23:27:02.008987 # ok 356 event_missing.LCALTA.10
2181 23:27:02.009345 # ok 357 event_spurious.LCALTA.10
2182 23:27:02.014492 # ok 358 get_value.LCALTA.9
2183 23:27:02.014858 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2184 23:27:02.020087 # ok 359 name.LCALTA.9
2185 23:27:02.020450 # ok 360 write_default.LCALTA.9
2186 23:27:02.025582 # ok 361 write_valid.LCALTA.9
2187 23:27:02.025939 # ok 362 write_invalid.LCALTA.9
2188 23:27:02.031139 # ok 363 event_missing.LCALTA.9
2189 23:27:02.031499 # ok 364 event_spurious.LCALTA.9
2190 23:27:02.036681 # ok 365 get_value.LCALTA.8
2191 23:27:02.037037 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2192 23:27:02.042310 # ok 366 name.LCALTA.8
2193 23:27:02.042668 # ok 367 write_default.LCALTA.8
2194 23:27:02.047842 # ok 368 write_valid.LCALTA.8
2195 23:27:02.048232 # ok 369 write_invalid.LCALTA.8
2196 23:27:02.053323 # ok 370 event_missing.LCALTA.8
2197 23:27:02.053680 # ok 371 event_spurious.LCALTA.8
2198 23:27:02.059295 # ok 372 get_value.LCALTA.7
2199 23:27:02.060712 # # LCALTA.7 ACODEC Unmute Ramp Switch
2200 23:27:02.064496 # ok 373 name.LCALTA.7
2201 23:27:02.064877 # ok 374 write_default.LCALTA.7
2202 23:27:02.070052 # ok 375 write_valid.LCALTA.7
2203 23:27:02.070452 # ok 376 write_invalid.LCALTA.7
2204 23:27:02.075497 # ok 377 event_missing.LCALTA.7
2205 23:27:02.075916 # ok 378 event_spurious.LCALTA.7
2206 23:27:02.081094 # ok 379 get_value.LCALTA.6
2207 23:27:02.081511 # # LCALTA.6 ACODEC Mute Ramp Switch
2208 23:27:02.086589 # ok 380 name.LCALTA.6
2209 23:27:02.086981 # ok 381 write_default.LCALTA.6
2210 23:27:02.092239 # ok 382 write_valid.LCALTA.6
2211 23:27:02.092635 # ok 383 write_invalid.LCALTA.6
2212 23:27:02.097751 # ok 384 event_missing.LCALTA.6
2213 23:27:02.098179 # ok 385 event_spurious.LCALTA.6
2214 23:27:02.103264 # ok 386 get_value.LCALTA.5
2215 23:27:02.103659 # # LCALTA.5 ACODEC Volume Ramp Switch
2216 23:27:02.108844 # ok 387 name.LCALTA.5
2217 23:27:02.109255 # ok 388 write_default.LCALTA.5
2218 23:27:02.114529 # ok 389 write_valid.LCALTA.5
2219 23:27:02.115268 # ok 390 write_invalid.LCALTA.5
2220 23:27:02.121740 # ok 391 event_missing.LCALTA.5
2221 23:27:02.122173 # ok 392 event_spurious.LCALTA.5
2222 23:27:02.125601 # ok 393 get_value.LCALTA.4
2223 23:27:02.126195 # # LCALTA.4 ACODEC Ramp Rate
2224 23:27:02.131142 # ok 394 name.LCALTA.4
2225 23:27:02.131739 # ok 395 write_default.LCALTA.4
2226 23:27:02.136707 # ok 396 write_valid.LCALTA.4
2227 23:27:02.137374 # ok 397 write_invalid.LCALTA.4
2228 23:27:02.142208 # ok 398 event_missing.LCALTA.4
2229 23:27:02.142662 # ok 399 event_spurious.LCALTA.4
2230 23:27:02.148720 # ok 400 get_value.LCALTA.3
2231 23:27:02.149372 # # LCALTA.3 ACODEC Playback Volume
2232 23:27:02.153571 # ok 401 name.LCALTA.3
2233 23:27:02.154018 # ok 402 write_default.LCALTA.3
2234 23:27:02.158861 # ok 403 write_valid.LCALTA.3
2235 23:27:02.159449 # ok 404 write_invalid.LCALTA.3
2236 23:27:02.165711 # ok 405 event_missing.LCALTA.3
2237 23:27:02.166333 # ok 406 event_spurious.LCALTA.3
2238 23:27:02.169955 # ok 407 get_value.LCALTA.2
2239 23:27:02.170554 # # LCALTA.2 ACODEC Playback Switch
2240 23:27:02.175965 # ok 408 name.LCALTA.2
2241 23:27:02.176629 # ok 409 write_default.LCALTA.2
2242 23:27:02.181030 # ok 410 write_valid.LCALTA.2
2243 23:27:02.181617 # ok 411 write_invalid.LCALTA.2
2244 23:27:02.186574 # ok 412 event_missing.LCALTA.2
2245 23:27:02.186957 # ok 413 event_spurious.LCALTA.2
2246 23:27:02.193040 # ok 414 get_value.LCALTA.1
2247 23:27:02.194796 # # LCALTA.1 ACODEC Playback Channel Mode
2248 23:27:02.197584 # ok 415 name.LCALTA.1
2249 23:27:02.198366 # ok 416 write_default.LCALTA.1
2250 23:27:02.203120 # ok 417 write_valid.LCALTA.1
2251 23:27:02.203707 # ok 418 write_invalid.LCALTA.1
2252 23:27:02.208739 # ok 419 event_missing.LCALTA.1
2253 23:27:02.209359 # ok 420 event_spurious.LCALTA.1
2254 23:27:02.214282 # ok 421 get_value.LCALTA.0
2255 23:27:02.214849 # # LCALTA.0 TOACODEC Lane Select
2256 23:27:02.220508 # ok 422 name.LCALTA.0
2257 23:27:02.221105 # ok 423 write_default.LCALTA.0
2258 23:27:02.225916 # ok 424 write_valid.LCALTA.0
2259 23:27:02.226519 # ok 425 write_invalid.LCALTA.0
2260 23:27:02.230948 # ok 426 event_missing.LCALTA.0
2261 23:27:02.231498 # ok 427 event_spurious.LCALTA.0
2262 23:27:02.236917 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2263 23:27:02.242009 ok 1 selftests: alsa: mixer-test
2264 23:27:02.242576 # timeout set to 45
2265 23:27:02.242976 # selftests: alsa: pcm-test
2266 23:27:02.247554 # TAP version 13
2267 23:27:02.248148 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2268 23:27:02.253112 # # LCALTA.0 - fe.dai-link-0 (*)
2269 23:27:02.253683 # # LCALTA.0 - fe.dai-link-1 (*)
2270 23:27:02.258663 # # LCALTA.0 - fe.dai-link-2 (*)
2271 23:27:02.259252 # # LCALTA.0 - fe.dai-link-3 (*)
2272 23:27:02.264254 # # LCALTA.0 - fe.dai-link-4 (*)
2273 23:27:02.264859 # # LCALTA.0 - fe.dai-link-5 (*)
2274 23:27:02.269776 # 1..42
2275 23:27:02.275294 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2276 23:27:02.275914 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2277 23:27:02.280903 # # snd_pcm_hw_params: Invalid argument
2278 23:27:02.287462 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2279 23:27:02.291956 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2280 23:27:02.292608 # # snd_pcm_hw_params: Invalid argument
2281 23:27:02.297497 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2282 23:27:02.303054 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2283 23:27:02.308641 # # snd_pcm_hw_params: Invalid argument
2284 23:27:02.314179 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2285 23:27:02.319708 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2286 23:27:02.320335 # # snd_pcm_hw_params: Invalid argument
2287 23:27:02.325265 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2288 23:27:02.330813 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2289 23:27:02.336357 # # snd_pcm_hw_params: Invalid argument
2290 23:27:02.341949 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2291 23:27:02.347408 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2292 23:27:02.347938 # # snd_pcm_hw_params: Invalid argument
2293 23:27:02.353006 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2294 23:27:02.358592 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2295 23:27:02.364117 # # snd_pcm_hw_params: Invalid argument
2296 23:27:02.369654 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2297 23:27:02.370244 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2298 23:27:02.375175 # # snd_pcm_hw_params: Invalid argument
2299 23:27:02.381169 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2300 23:27:02.386342 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2301 23:27:02.386916 # # snd_pcm_hw_params: Invalid argument
2302 23:27:02.397321 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2303 23:27:02.397915 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2304 23:27:02.402952 # # snd_pcm_hw_params: Invalid argument
2305 23:27:02.408866 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2306 23:27:02.413981 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2307 23:27:02.414408 # # snd_pcm_hw_params: Invalid argument
2308 23:27:02.419666 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2309 23:27:02.425119 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2310 23:27:02.430716 # # snd_pcm_hw_params: Invalid argument
2311 23:27:02.436529 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2312 23:27:02.441778 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2313 23:27:02.442247 # # snd_pcm_hw_params: Invalid argument
2314 23:27:02.447930 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2315 23:27:02.452788 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2316 23:27:02.458428 # # snd_pcm_hw_params: Invalid argument
2317 23:27:02.464015 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2318 23:27:02.469488 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2319 23:27:02.469935 # # snd_pcm_hw_params: Invalid argument
2320 23:27:02.475049 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2321 23:27:02.480526 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2322 23:27:02.486201 # # snd_pcm_hw_params: Invalid argument
2323 23:27:02.491946 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2324 23:27:02.492402 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2325 23:27:02.497400 # # snd_pcm_hw_params: Invalid argument
2326 23:27:02.502691 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2327 23:27:02.508168 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2328 23:27:02.513805 # # snd_pcm_hw_params: Invalid argument
2329 23:27:02.519360 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2330 23:27:02.519848 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2331 23:27:02.525077 # # snd_pcm_hw_params: Invalid argument
2332 23:27:02.530570 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2333 23:27:02.536050 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2334 23:27:02.541563 # # snd_pcm_hw_params: Invalid argument
2335 23:27:02.547094 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2336 23:27:02.547501 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2337 23:27:02.552866 # # snd_pcm_hw_params: Invalid argument
2338 23:27:02.558199 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2339 23:27:02.563731 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2340 23:27:02.564156 # # snd_pcm_hw_params: Invalid argument
2341 23:27:02.569364 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2342 23:27:02.574725 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2343 23:27:02.580760 # # snd_pcm_hw_params: Invalid argument
2344 23:27:02.586049 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2345 23:27:02.591747 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2346 23:27:02.592239 # # snd_pcm_hw_params: Invalid argument
2347 23:27:02.596982 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2348 23:27:02.603265 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2349 23:27:02.608041 # # snd_pcm_hw_params: Invalid argument
2350 23:27:02.613607 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2351 23:27:02.619027 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2352 23:27:02.619586 # # snd_pcm_hw_params: Invalid argument
2353 23:27:02.624714 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2354 23:27:02.631157 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2355 23:27:02.635872 # # snd_pcm_hw_params: Invalid argument
2356 23:27:02.642160 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2357 23:27:02.648390 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2358 23:27:02.649399 # # snd_pcm_hw_params: Invalid argument
2359 23:27:02.652510 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2360 23:27:02.661072 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2361 23:27:02.663582 # # snd_pcm_hw_params: Invalid argument
2362 23:27:02.669831 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2363 23:27:02.674757 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2364 23:27:02.675211 # # snd_pcm_hw_params: Invalid argument
2365 23:27:02.680290 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2366 23:27:02.685723 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2367 23:27:02.691322 # # snd_pcm_hw_params: Invalid argument
2368 23:27:02.696851 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2369 23:27:02.702667 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2370 23:27:02.703062 # # snd_pcm_hw_params: Invalid argument
2371 23:27:02.707953 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2372 23:27:02.713546 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2373 23:27:02.718974 # # snd_pcm_hw_params: Invalid argument
2374 23:27:02.724535 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2375 23:27:02.730235 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2376 23:27:02.730613 # # snd_pcm_hw_params: Invalid argument
2377 23:27:02.735703 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2378 23:27:02.741193 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2379 23:27:02.746683 # # snd_pcm_hw_params: Invalid argument
2380 23:27:02.752315 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2381 23:27:02.760395 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2382 23:27:02.761036 # # snd_pcm_hw_params: Invalid argument
2383 23:27:02.763775 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2384 23:27:02.769043 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2385 23:27:02.774472 # # snd_pcm_hw_params: Invalid argument
2386 23:27:02.780058 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2387 23:27:02.785576 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2388 23:27:02.786166 # # snd_pcm_hw_params: Invalid argument
2389 23:27:02.791135 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2390 23:27:02.796737 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2391 23:27:02.802920 # # snd_pcm_hw_params: Invalid argument
2392 23:27:02.808190 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2393 23:27:02.814428 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2394 23:27:02.814990 # # snd_pcm_hw_params: Invalid argument
2395 23:27:02.819005 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2396 23:27:02.825828 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2397 23:27:02.830208 # # snd_pcm_hw_params: Invalid argument
2398 23:27:02.836196 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2399 23:27:02.841071 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2400 23:27:02.841584 # # snd_pcm_hw_params: Invalid argument
2401 23:27:02.846792 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2402 23:27:02.852088 ok 2 selftests: alsa: pcm-test
2403 23:27:02.852590 # timeout set to 45
2404 23:27:02.857704 # selftests: alsa: test-pcmtest-driver
2405 23:27:02.858203 # TAP version 13
2406 23:27:02.858643 # 1..5
2407 23:27:02.863197 # # Starting 5 tests from 1 test cases.
2408 23:27:02.863689 # # RUN pcmtest.playback ...
2409 23:27:02.868805 # # SKIP Can't read patterns. Probably, module isn't loaded
2410 23:27:02.874740 # # OK pcmtest.playback
2411 23:27:02.880064 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2412 23:27:02.885882 # # RUN pcmtest.capture ...
2413 23:27:02.891127 # # SKIP Can't read patterns. Probably, module isn't loaded
2414 23:27:02.896537 # # OK pcmtest.capture
2415 23:27:02.902175 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2416 23:27:02.907657 # # RUN pcmtest.ni_capture ...
2417 23:27:02.913222 # # SKIP Can't read patterns. Probably, module isn't loaded
2418 23:27:02.913736 # # OK pcmtest.ni_capture
2419 23:27:02.924369 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2420 23:27:02.925068 # # RUN pcmtest.ni_playback ...
2421 23:27:02.929813 # # SKIP Can't read patterns. Probably, module isn't loaded
2422 23:27:02.935353 # # OK pcmtest.ni_playback
2423 23:27:02.940989 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2424 23:27:02.946434 # # RUN pcmtest.reset_ioctl ...
2425 23:27:02.952438 # # SKIP Can't read patterns. Probably, module isn't loaded
2426 23:27:02.957565 # # OK pcmtest.reset_ioctl
2427 23:27:02.963181 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2428 23:27:02.968732 # # PASSED: 5 / 5 tests passed.
2429 23:27:02.974628 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2430 23:27:02.975058 ok 3 selftests: alsa: test-pcmtest-driver
2431 23:27:02.979728 # timeout set to 45
2432 23:27:02.980166 # selftests: alsa: utimer-test
2433 23:27:02.980416 # TAP version 13
2434 23:27:02.980650 # 1..2
2435 23:27:02.985369 # # Starting 2 tests from 2 test cases.
2436 23:27:02.990788 # # RUN global.wrong_timers_test ...
2437 23:27:02.996403 # # OK global.wrong_timers_test
2438 23:27:02.996829 # ok 1 global.wrong_timers_test
2439 23:27:03.001915 # # RUN timer_f.utimer ...
2440 23:27:03.008211 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2441 23:27:03.012981 # # utimer: Test terminated by assertion
2442 23:27:03.018504 # # FAIL timer_f.utimer
2443 23:27:03.019084 # not ok 2 timer_f.utimer
2444 23:27:03.024149 # # FAILED: 1 / 2 tests passed.
2445 23:27:03.031533 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2446 23:27:03.032174 not ok 4 selftests: alsa: utimer-test # exit=1
2447 23:27:03.888020 alsa_mixer-test_get_value_LCALTA_60 pass
2448 23:27:03.893683 alsa_mixer-test_name_LCALTA_60 pass
2449 23:27:03.894285 alsa_mixer-test_write_default_LCALTA_60 pass
2450 23:27:03.898756 alsa_mixer-test_write_valid_LCALTA_60 pass
2451 23:27:03.904385 alsa_mixer-test_write_invalid_LCALTA_60 pass
2452 23:27:03.909917 alsa_mixer-test_event_missing_LCALTA_60 pass
2453 23:27:03.910363 alsa_mixer-test_event_spurious_LCALTA_60 pass
2454 23:27:03.915551 alsa_mixer-test_get_value_LCALTA_59 pass
2455 23:27:03.921049 alsa_mixer-test_name_LCALTA_59 pass
2456 23:27:03.921478 alsa_mixer-test_write_default_LCALTA_59 pass
2457 23:27:03.926657 alsa_mixer-test_write_valid_LCALTA_59 pass
2458 23:27:03.932217 alsa_mixer-test_write_invalid_LCALTA_59 pass
2459 23:27:03.932773 alsa_mixer-test_event_missing_LCALTA_59 pass
2460 23:27:03.937756 alsa_mixer-test_event_spurious_LCALTA_59 pass
2461 23:27:03.943274 alsa_mixer-test_get_value_LCALTA_58 pass
2462 23:27:03.943819 alsa_mixer-test_name_LCALTA_58 pass
2463 23:27:03.948823 alsa_mixer-test_write_default_LCALTA_58 pass
2464 23:27:03.954366 alsa_mixer-test_write_valid_LCALTA_58 pass
2465 23:27:03.954940 alsa_mixer-test_write_invalid_LCALTA_58 pass
2466 23:27:03.960001 alsa_mixer-test_event_missing_LCALTA_58 pass
2467 23:27:03.965475 alsa_mixer-test_event_spurious_LCALTA_58 pass
2468 23:27:03.970991 alsa_mixer-test_get_value_LCALTA_57 pass
2469 23:27:03.971503 alsa_mixer-test_name_LCALTA_57 pass
2470 23:27:03.976536 alsa_mixer-test_write_default_LCALTA_57 pass
2471 23:27:03.982159 alsa_mixer-test_write_valid_LCALTA_57 pass
2472 23:27:03.982669 alsa_mixer-test_write_invalid_LCALTA_57 pass
2473 23:27:03.987649 alsa_mixer-test_event_missing_LCALTA_57 pass
2474 23:27:03.993224 alsa_mixer-test_event_spurious_LCALTA_57 pass
2475 23:27:03.993729 alsa_mixer-test_get_value_LCALTA_56 pass
2476 23:27:03.998714 alsa_mixer-test_name_LCALTA_56 pass
2477 23:27:04.004280 alsa_mixer-test_write_default_LCALTA_56 pass
2478 23:27:04.004786 alsa_mixer-test_write_valid_LCALTA_56 pass
2479 23:27:04.009829 alsa_mixer-test_write_invalid_LCALTA_56 pass
2480 23:27:04.015368 alsa_mixer-test_event_missing_LCALTA_56 pass
2481 23:27:04.020942 alsa_mixer-test_event_spurious_LCALTA_56 pass
2482 23:27:04.021455 alsa_mixer-test_get_value_LCALTA_55 pass
2483 23:27:04.026479 alsa_mixer-test_name_LCALTA_55 pass
2484 23:27:04.032061 alsa_mixer-test_write_default_LCALTA_55 pass
2485 23:27:04.032567 alsa_mixer-test_write_valid_LCALTA_55 pass
2486 23:27:04.037522 alsa_mixer-test_write_invalid_LCALTA_55 pass
2487 23:27:04.043142 alsa_mixer-test_event_missing_LCALTA_55 pass
2488 23:27:04.043632 alsa_mixer-test_event_spurious_LCALTA_55 pass
2489 23:27:04.048629 alsa_mixer-test_get_value_LCALTA_54 pass
2490 23:27:04.054189 alsa_mixer-test_name_LCALTA_54 pass
2491 23:27:04.054680 alsa_mixer-test_write_default_LCALTA_54 pass
2492 23:27:04.059743 alsa_mixer-test_write_valid_LCALTA_54 pass
2493 23:27:04.065283 alsa_mixer-test_write_invalid_LCALTA_54 pass
2494 23:27:04.065785 alsa_mixer-test_event_missing_LCALTA_54 pass
2495 23:27:04.070859 alsa_mixer-test_event_spurious_LCALTA_54 pass
2496 23:27:04.076418 alsa_mixer-test_get_value_LCALTA_53 pass
2497 23:27:04.076926 alsa_mixer-test_name_LCALTA_53 pass
2498 23:27:04.081923 alsa_mixer-test_write_default_LCALTA_53 pass
2499 23:27:04.087508 alsa_mixer-test_write_valid_LCALTA_53 pass
2500 23:27:04.092999 alsa_mixer-test_write_invalid_LCALTA_53 pass
2501 23:27:04.093517 alsa_mixer-test_event_missing_LCALTA_53 pass
2502 23:27:04.098564 alsa_mixer-test_event_spurious_LCALTA_53 pass
2503 23:27:04.104207 alsa_mixer-test_get_value_LCALTA_52 pass
2504 23:27:04.104706 alsa_mixer-test_name_LCALTA_52 pass
2505 23:27:04.109654 alsa_mixer-test_write_default_LCALTA_52 pass
2506 23:27:04.115231 alsa_mixer-test_write_valid_LCALTA_52 pass
2507 23:27:04.115727 alsa_mixer-test_write_invalid_LCALTA_52 pass
2508 23:27:04.120759 alsa_mixer-test_event_missing_LCALTA_52 pass
2509 23:27:04.126274 alsa_mixer-test_event_spurious_LCALTA_52 pass
2510 23:27:04.126767 alsa_mixer-test_get_value_LCALTA_51 pass
2511 23:27:04.131868 alsa_mixer-test_name_LCALTA_51 pass
2512 23:27:04.137370 alsa_mixer-test_write_default_LCALTA_51 pass
2513 23:27:04.137869 alsa_mixer-test_write_valid_LCALTA_51 pass
2514 23:27:04.142951 alsa_mixer-test_write_invalid_LCALTA_51 pass
2515 23:27:04.148465 alsa_mixer-test_event_missing_LCALTA_51 pass
2516 23:27:04.154065 alsa_mixer-test_event_spurious_LCALTA_51 pass
2517 23:27:04.154567 alsa_mixer-test_get_value_LCALTA_50 pass
2518 23:27:04.159589 alsa_mixer-test_name_LCALTA_50 pass
2519 23:27:04.165172 alsa_mixer-test_write_default_LCALTA_50 pass
2520 23:27:04.165671 alsa_mixer-test_write_valid_LCALTA_50 pass
2521 23:27:04.170700 alsa_mixer-test_write_invalid_LCALTA_50 pass
2522 23:27:04.176263 alsa_mixer-test_event_missing_LCALTA_50 pass
2523 23:27:04.176768 alsa_mixer-test_event_spurious_LCALTA_50 pass
2524 23:27:04.181789 alsa_mixer-test_get_value_LCALTA_49 pass
2525 23:27:04.187321 alsa_mixer-test_name_LCALTA_49 pass
2526 23:27:04.187815 alsa_mixer-test_write_default_LCALTA_49 pass
2527 23:27:04.192850 alsa_mixer-test_write_valid_LCALTA_49 pass
2528 23:27:04.198413 alsa_mixer-test_write_invalid_LCALTA_49 pass
2529 23:27:04.203967 alsa_mixer-test_event_missing_LCALTA_49 pass
2530 23:27:04.204497 alsa_mixer-test_event_spurious_LCALTA_49 pass
2531 23:27:04.209491 alsa_mixer-test_get_value_LCALTA_48 pass
2532 23:27:04.209983 alsa_mixer-test_name_LCALTA_48 pass
2533 23:27:04.215051 alsa_mixer-test_write_default_LCALTA_48 pass
2534 23:27:04.220584 alsa_mixer-test_write_valid_LCALTA_48 pass
2535 23:27:04.226156 alsa_mixer-test_write_invalid_LCALTA_48 pass
2536 23:27:04.226648 alsa_mixer-test_event_missing_LCALTA_48 pass
2537 23:27:04.231687 alsa_mixer-test_event_spurious_LCALTA_48 pass
2538 23:27:04.237243 alsa_mixer-test_get_value_LCALTA_47 pass
2539 23:27:04.237735 alsa_mixer-test_name_LCALTA_47 pass
2540 23:27:04.242746 alsa_mixer-test_write_default_LCALTA_47 pass
2541 23:27:04.248329 alsa_mixer-test_write_valid_LCALTA_47 pass
2542 23:27:04.248820 alsa_mixer-test_write_invalid_LCALTA_47 pass
2543 23:27:04.253880 alsa_mixer-test_event_missing_LCALTA_47 pass
2544 23:27:04.259409 alsa_mixer-test_event_spurious_LCALTA_47 pass
2545 23:27:04.264937 alsa_mixer-test_get_value_LCALTA_46 pass
2546 23:27:04.265434 alsa_mixer-test_name_LCALTA_46 pass
2547 23:27:04.270492 alsa_mixer-test_write_default_LCALTA_46 pass
2548 23:27:04.276103 alsa_mixer-test_write_valid_LCALTA_46 pass
2549 23:27:04.276603 alsa_mixer-test_write_invalid_LCALTA_46 pass
2550 23:27:04.281596 alsa_mixer-test_event_missing_LCALTA_46 pass
2551 23:27:04.287207 alsa_mixer-test_event_spurious_LCALTA_46 pass
2552 23:27:04.287703 alsa_mixer-test_get_value_LCALTA_45 pass
2553 23:27:04.292702 alsa_mixer-test_name_LCALTA_45 pass
2554 23:27:04.298226 alsa_mixer-test_write_default_LCALTA_45 pass
2555 23:27:04.298716 alsa_mixer-test_write_valid_LCALTA_45 pass
2556 23:27:04.303783 alsa_mixer-test_write_invalid_LCALTA_45 pass
2557 23:27:04.309329 alsa_mixer-test_event_missing_LCALTA_45 pass
2558 23:27:04.309826 alsa_mixer-test_event_spurious_LCALTA_45 pass
2559 23:27:04.314891 alsa_mixer-test_get_value_LCALTA_44 pass
2560 23:27:04.320444 alsa_mixer-test_name_LCALTA_44 pass
2561 23:27:04.320930 alsa_mixer-test_write_default_LCALTA_44 pass
2562 23:27:04.325949 alsa_mixer-test_write_valid_LCALTA_44 pass
2563 23:27:04.331514 alsa_mixer-test_write_invalid_LCALTA_44 pass
2564 23:27:04.337097 alsa_mixer-test_event_missing_LCALTA_44 pass
2565 23:27:04.337582 alsa_mixer-test_event_spurious_LCALTA_44 pass
2566 23:27:04.342626 alsa_mixer-test_get_value_LCALTA_43 pass
2567 23:27:04.348259 alsa_mixer-test_name_LCALTA_43 pass
2568 23:27:04.348748 alsa_mixer-test_write_default_LCALTA_43 pass
2569 23:27:04.353687 alsa_mixer-test_write_valid_LCALTA_43 pass
2570 23:27:04.359268 alsa_mixer-test_write_invalid_LCALTA_43 pass
2571 23:27:04.359756 alsa_mixer-test_event_missing_LCALTA_43 pass
2572 23:27:04.364824 alsa_mixer-test_event_spurious_LCALTA_43 pass
2573 23:27:04.370330 alsa_mixer-test_get_value_LCALTA_42 pass
2574 23:27:04.370816 alsa_mixer-test_name_LCALTA_42 pass
2575 23:27:04.375867 alsa_mixer-test_write_default_LCALTA_42 pass
2576 23:27:04.381450 alsa_mixer-test_write_valid_LCALTA_42 pass
2577 23:27:04.381936 alsa_mixer-test_write_invalid_LCALTA_42 pass
2578 23:27:04.386988 alsa_mixer-test_event_missing_LCALTA_42 pass
2579 23:27:04.392537 alsa_mixer-test_event_spurious_LCALTA_42 pass
2580 23:27:04.398063 alsa_mixer-test_get_value_LCALTA_41 pass
2581 23:27:04.398548 alsa_mixer-test_name_LCALTA_41 pass
2582 23:27:04.403617 alsa_mixer-test_write_default_LCALTA_41 pass
2583 23:27:04.409196 alsa_mixer-test_write_valid_LCALTA_41 pass
2584 23:27:04.409690 alsa_mixer-test_write_invalid_LCALTA_41 pass
2585 23:27:04.414704 alsa_mixer-test_event_missing_LCALTA_41 pass
2586 23:27:04.420285 alsa_mixer-test_event_spurious_LCALTA_41 pass
2587 23:27:04.420772 alsa_mixer-test_get_value_LCALTA_40 pass
2588 23:27:04.425809 alsa_mixer-test_name_LCALTA_40 pass
2589 23:27:04.431356 alsa_mixer-test_write_default_LCALTA_40 pass
2590 23:27:04.431843 alsa_mixer-test_write_valid_LCALTA_40 pass
2591 23:27:04.436907 alsa_mixer-test_write_invalid_LCALTA_40 pass
2592 23:27:04.442445 alsa_mixer-test_event_missing_LCALTA_40 pass
2593 23:27:04.448035 alsa_mixer-test_event_spurious_LCALTA_40 pass
2594 23:27:04.448528 alsa_mixer-test_get_value_LCALTA_39 pass
2595 23:27:04.453539 alsa_mixer-test_name_LCALTA_39 pass
2596 23:27:04.459062 alsa_mixer-test_write_default_LCALTA_39 pass
2597 23:27:04.459551 alsa_mixer-test_write_valid_LCALTA_39 pass
2598 23:27:04.464640 alsa_mixer-test_write_invalid_LCALTA_39 pass
2599 23:27:04.470225 alsa_mixer-test_event_missing_LCALTA_39 pass
2600 23:27:04.470717 alsa_mixer-test_event_spurious_LCALTA_39 pass
2601 23:27:04.475712 alsa_mixer-test_get_value_LCALTA_38 pass
2602 23:27:04.481284 alsa_mixer-test_name_LCALTA_38 pass
2603 23:27:04.481769 alsa_mixer-test_write_default_LCALTA_38 pass
2604 23:27:04.486841 alsa_mixer-test_write_valid_LCALTA_38 pass
2605 23:27:04.492360 alsa_mixer-test_write_invalid_LCALTA_38 pass
2606 23:27:04.492849 alsa_mixer-test_event_missing_LCALTA_38 pass
2607 23:27:04.497920 alsa_mixer-test_event_spurious_LCALTA_38 pass
2608 23:27:04.503455 alsa_mixer-test_get_value_LCALTA_37 pass
2609 23:27:04.503943 alsa_mixer-test_name_LCALTA_37 pass
2610 23:27:04.509036 alsa_mixer-test_write_default_LCALTA_37 pass
2611 23:27:04.514560 alsa_mixer-test_write_valid_LCALTA_37 pass
2612 23:27:04.520136 alsa_mixer-test_write_invalid_LCALTA_37 pass
2613 23:27:04.520628 alsa_mixer-test_event_missing_LCALTA_37 pass
2614 23:27:04.525633 alsa_mixer-test_event_spurious_LCALTA_37 pass
2615 23:27:04.531220 alsa_mixer-test_get_value_LCALTA_36 pass
2616 23:27:04.531703 alsa_mixer-test_name_LCALTA_36 pass
2617 23:27:04.536759 alsa_mixer-test_write_default_LCALTA_36 pass
2618 23:27:04.542273 alsa_mixer-test_write_valid_LCALTA_36 pass
2619 23:27:04.542756 alsa_mixer-test_write_invalid_LCALTA_36 pass
2620 23:27:04.547812 alsa_mixer-test_event_missing_LCALTA_36 pass
2621 23:27:04.553360 alsa_mixer-test_event_spurious_LCALTA_36 pass
2622 23:27:04.553848 alsa_mixer-test_get_value_LCALTA_35 pass
2623 23:27:04.558936 alsa_mixer-test_name_LCALTA_35 pass
2624 23:27:04.564492 alsa_mixer-test_write_default_LCALTA_35 pass
2625 23:27:04.564983 alsa_mixer-test_write_valid_LCALTA_35 pass
2626 23:27:04.570022 alsa_mixer-test_write_invalid_LCALTA_35 pass
2627 23:27:04.575556 alsa_mixer-test_event_missing_LCALTA_35 pass
2628 23:27:04.581129 alsa_mixer-test_event_spurious_LCALTA_35 pass
2629 23:27:04.581614 alsa_mixer-test_get_value_LCALTA_34 pass
2630 23:27:04.586679 alsa_mixer-test_name_LCALTA_34 pass
2631 23:27:04.592261 alsa_mixer-test_write_default_LCALTA_34 pass
2632 23:27:04.592751 alsa_mixer-test_write_valid_LCALTA_34 pass
2633 23:27:04.597776 alsa_mixer-test_write_invalid_LCALTA_34 pass
2634 23:27:04.603314 alsa_mixer-test_event_missing_LCALTA_34 pass
2635 23:27:04.603806 alsa_mixer-test_event_spurious_LCALTA_34 pass
2636 23:27:04.608882 alsa_mixer-test_get_value_LCALTA_33 pass
2637 23:27:04.614414 alsa_mixer-test_name_LCALTA_33 pass
2638 23:27:04.614915 alsa_mixer-test_write_default_LCALTA_33 pass
2639 23:27:04.619947 alsa_mixer-test_write_valid_LCALTA_33 pass
2640 23:27:04.625494 alsa_mixer-test_write_invalid_LCALTA_33 pass
2641 23:27:04.631055 alsa_mixer-test_event_missing_LCALTA_33 pass
2642 23:27:04.631550 alsa_mixer-test_event_spurious_LCALTA_33 pass
2643 23:27:04.636608 alsa_mixer-test_get_value_LCALTA_32 pass
2644 23:27:04.637102 alsa_mixer-test_name_LCALTA_32 pass
2645 23:27:04.642141 alsa_mixer-test_write_default_LCALTA_32 pass
2646 23:27:04.647691 alsa_mixer-test_write_valid_LCALTA_32 pass
2647 23:27:04.653254 alsa_mixer-test_write_invalid_LCALTA_32 pass
2648 23:27:04.653742 alsa_mixer-test_event_missing_LCALTA_32 pass
2649 23:27:04.658770 alsa_mixer-test_event_spurious_LCALTA_32 pass
2650 23:27:04.664359 alsa_mixer-test_get_value_LCALTA_31 pass
2651 23:27:04.664863 alsa_mixer-test_name_LCALTA_31 pass
2652 23:27:04.669894 alsa_mixer-test_write_default_LCALTA_31 pass
2653 23:27:04.675411 alsa_mixer-test_write_valid_LCALTA_31 pass
2654 23:27:04.675905 alsa_mixer-test_write_invalid_LCALTA_31 pass
2655 23:27:04.681004 alsa_mixer-test_event_missing_LCALTA_31 pass
2656 23:27:04.686523 alsa_mixer-test_event_spurious_LCALTA_31 pass
2657 23:27:04.692087 alsa_mixer-test_get_value_LCALTA_30 pass
2658 23:27:04.692584 alsa_mixer-test_name_LCALTA_30 pass
2659 23:27:04.697595 alsa_mixer-test_write_default_LCALTA_30 pass
2660 23:27:04.703159 alsa_mixer-test_write_valid_LCALTA_30 pass
2661 23:27:04.703650 alsa_mixer-test_write_invalid_LCALTA_30 pass
2662 23:27:04.708719 alsa_mixer-test_event_missing_LCALTA_30 pass
2663 23:27:04.714250 alsa_mixer-test_event_spurious_LCALTA_30 pass
2664 23:27:04.714747 alsa_mixer-test_get_value_LCALTA_29 pass
2665 23:27:04.719799 alsa_mixer-test_name_LCALTA_29 pass
2666 23:27:04.725337 alsa_mixer-test_write_default_LCALTA_29 pass
2667 23:27:04.725835 alsa_mixer-test_write_valid_LCALTA_29 pass
2668 23:27:04.730883 alsa_mixer-test_write_invalid_LCALTA_29 pass
2669 23:27:04.736430 alsa_mixer-test_event_missing_LCALTA_29 pass
2670 23:27:04.736923 alsa_mixer-test_event_spurious_LCALTA_29 pass
2671 23:27:04.741992 alsa_mixer-test_get_value_LCALTA_28 pass
2672 23:27:04.747528 alsa_mixer-test_name_LCALTA_28 pass
2673 23:27:04.748061 alsa_mixer-test_write_default_LCALTA_28 pass
2674 23:27:04.753087 alsa_mixer-test_write_valid_LCALTA_28 pass
2675 23:27:04.758620 alsa_mixer-test_write_invalid_LCALTA_28 pass
2676 23:27:04.764245 alsa_mixer-test_event_missing_LCALTA_28 pass
2677 23:27:04.764765 alsa_mixer-test_event_spurious_LCALTA_28 pass
2678 23:27:04.769720 alsa_mixer-test_get_value_LCALTA_27 pass
2679 23:27:04.775256 alsa_mixer-test_name_LCALTA_27 pass
2680 23:27:04.775768 alsa_mixer-test_write_default_LCALTA_27 pass
2681 23:27:04.780811 alsa_mixer-test_write_valid_LCALTA_27 pass
2682 23:27:04.786327 alsa_mixer-test_write_invalid_LCALTA_27 pass
2683 23:27:04.786886 alsa_mixer-test_event_missing_LCALTA_27 pass
2684 23:27:04.791926 alsa_mixer-test_event_spurious_LCALTA_27 pass
2685 23:27:04.797380 alsa_mixer-test_get_value_LCALTA_26 pass
2686 23:27:04.797915 alsa_mixer-test_name_LCALTA_26 pass
2687 23:27:04.803044 alsa_mixer-test_write_default_LCALTA_26 skip
2688 23:27:04.808549 alsa_mixer-test_write_valid_LCALTA_26 skip
2689 23:27:04.809058 alsa_mixer-test_write_invalid_LCALTA_26 skip
2690 23:27:04.814098 alsa_mixer-test_event_missing_LCALTA_26 pass
2691 23:27:04.819502 alsa_mixer-test_event_spurious_LCALTA_26 pass
2692 23:27:04.825118 alsa_mixer-test_get_value_LCALTA_25 pass
2693 23:27:04.825443 alsa_mixer-test_name_LCALTA_25 pass
2694 23:27:04.830743 alsa_mixer-test_write_default_LCALTA_25 pass
2695 23:27:04.836263 alsa_mixer-test_write_valid_LCALTA_25 skip
2696 23:27:04.836804 alsa_mixer-test_write_invalid_LCALTA_25 skip
2697 23:27:04.841782 alsa_mixer-test_event_missing_LCALTA_25 pass
2698 23:27:04.847230 alsa_mixer-test_event_spurious_LCALTA_25 pass
2699 23:27:04.847590 alsa_mixer-test_get_value_LCALTA_24 pass
2700 23:27:04.852924 alsa_mixer-test_name_LCALTA_24 pass
2701 23:27:04.858475 alsa_mixer-test_write_default_LCALTA_24 skip
2702 23:27:04.859008 alsa_mixer-test_write_valid_LCALTA_24 skip
2703 23:27:04.864067 alsa_mixer-test_write_invalid_LCALTA_24 skip
2704 23:27:04.869543 alsa_mixer-test_event_missing_LCALTA_24 pass
2705 23:27:04.875083 alsa_mixer-test_event_spurious_LCALTA_24 pass
2706 23:27:04.875592 alsa_mixer-test_get_value_LCALTA_23 pass
2707 23:27:04.880651 alsa_mixer-test_name_LCALTA_23 pass
2708 23:27:04.886198 alsa_mixer-test_write_default_LCALTA_23 skip
2709 23:27:04.886701 alsa_mixer-test_write_valid_LCALTA_23 skip
2710 23:27:04.891747 alsa_mixer-test_write_invalid_LCALTA_23 skip
2711 23:27:04.897299 alsa_mixer-test_event_missing_LCALTA_23 pass
2712 23:27:04.897805 alsa_mixer-test_event_spurious_LCALTA_23 pass
2713 23:27:04.902838 alsa_mixer-test_get_value_LCALTA_22 pass
2714 23:27:04.908406 alsa_mixer-test_name_LCALTA_22 pass
2715 23:27:04.908906 alsa_mixer-test_write_default_LCALTA_22 pass
2716 23:27:04.913936 alsa_mixer-test_write_valid_LCALTA_22 pass
2717 23:27:04.919488 alsa_mixer-test_write_invalid_LCALTA_22 pass
2718 23:27:04.920027 alsa_mixer-test_event_missing_LCALTA_22 pass
2719 23:27:04.925040 alsa_mixer-test_event_spurious_LCALTA_22 pass
2720 23:27:04.930571 alsa_mixer-test_get_value_LCALTA_21 pass
2721 23:27:04.931065 alsa_mixer-test_name_LCALTA_21 pass
2722 23:27:04.936131 alsa_mixer-test_write_default_LCALTA_21 pass
2723 23:27:04.941679 alsa_mixer-test_write_valid_LCALTA_21 pass
2724 23:27:04.947198 alsa_mixer-test_write_invalid_LCALTA_21 pass
2725 23:27:04.947704 alsa_mixer-test_event_missing_LCALTA_21 pass
2726 23:27:04.952774 alsa_mixer-test_event_spurious_LCALTA_21 pass
2727 23:27:04.958358 alsa_mixer-test_get_value_LCALTA_20 pass
2728 23:27:04.958864 alsa_mixer-test_name_LCALTA_20 pass
2729 23:27:04.963874 alsa_mixer-test_write_default_LCALTA_20 pass
2730 23:27:04.969423 alsa_mixer-test_write_valid_LCALTA_20 pass
2731 23:27:04.969923 alsa_mixer-test_write_invalid_LCALTA_20 pass
2732 23:27:04.974955 alsa_mixer-test_event_missing_LCALTA_20 pass
2733 23:27:04.980499 alsa_mixer-test_event_spurious_LCALTA_20 pass
2734 23:27:04.980999 alsa_mixer-test_get_value_LCALTA_19 pass
2735 23:27:04.986050 alsa_mixer-test_name_LCALTA_19 pass
2736 23:27:04.991559 alsa_mixer-test_write_default_LCALTA_19 pass
2737 23:27:04.992076 alsa_mixer-test_write_valid_LCALTA_19 pass
2738 23:27:04.997124 alsa_mixer-test_write_invalid_LCALTA_19 pass
2739 23:27:05.002646 alsa_mixer-test_event_missing_LCALTA_19 pass
2740 23:27:05.008228 alsa_mixer-test_event_spurious_LCALTA_19 pass
2741 23:27:05.008722 alsa_mixer-test_get_value_LCALTA_18 pass
2742 23:27:05.013767 alsa_mixer-test_name_LCALTA_18 pass
2743 23:27:05.019336 alsa_mixer-test_write_default_LCALTA_18 pass
2744 23:27:05.019865 alsa_mixer-test_write_valid_LCALTA_18 pass
2745 23:27:05.024881 alsa_mixer-test_write_invalid_LCALTA_18 pass
2746 23:27:05.030406 alsa_mixer-test_event_missing_LCALTA_18 pass
2747 23:27:05.030891 alsa_mixer-test_event_spurious_LCALTA_18 pass
2748 23:27:05.035943 alsa_mixer-test_get_value_LCALTA_17 pass
2749 23:27:05.041479 alsa_mixer-test_name_LCALTA_17 pass
2750 23:27:05.041965 alsa_mixer-test_write_default_LCALTA_17 pass
2751 23:27:05.047012 alsa_mixer-test_write_valid_LCALTA_17 pass
2752 23:27:05.052564 alsa_mixer-test_write_invalid_LCALTA_17 pass
2753 23:27:05.058131 alsa_mixer-test_event_missing_LCALTA_17 pass
2754 23:27:05.058610 alsa_mixer-test_event_spurious_LCALTA_17 pass
2755 23:27:05.063658 alsa_mixer-test_get_value_LCALTA_16 pass
2756 23:27:05.064173 alsa_mixer-test_name_LCALTA_16 pass
2757 23:27:05.069299 alsa_mixer-test_write_default_LCALTA_16 pass
2758 23:27:05.074749 alsa_mixer-test_write_valid_LCALTA_16 pass
2759 23:27:05.080345 alsa_mixer-test_write_invalid_LCALTA_16 pass
2760 23:27:05.080821 alsa_mixer-test_event_missing_LCALTA_16 pass
2761 23:27:05.085851 alsa_mixer-test_event_spurious_LCALTA_16 pass
2762 23:27:05.091415 alsa_mixer-test_get_value_LCALTA_15 pass
2763 23:27:05.091887 alsa_mixer-test_name_LCALTA_15 pass
2764 23:27:05.096956 alsa_mixer-test_write_default_LCALTA_15 pass
2765 23:27:05.102502 alsa_mixer-test_write_valid_LCALTA_15 pass
2766 23:27:05.102988 alsa_mixer-test_write_invalid_LCALTA_15 pass
2767 23:27:05.108058 alsa_mixer-test_event_missing_LCALTA_15 pass
2768 23:27:05.113573 alsa_mixer-test_event_spurious_LCALTA_15 pass
2769 23:27:05.119158 alsa_mixer-test_get_value_LCALTA_14 pass
2770 23:27:05.119639 alsa_mixer-test_name_LCALTA_14 pass
2771 23:27:05.124683 alsa_mixer-test_write_default_LCALTA_14 pass
2772 23:27:05.130283 alsa_mixer-test_write_valid_LCALTA_14 pass
2773 23:27:05.130763 alsa_mixer-test_write_invalid_LCALTA_14 pass
2774 23:27:05.135789 alsa_mixer-test_event_missing_LCALTA_14 pass
2775 23:27:05.141352 alsa_mixer-test_event_spurious_LCALTA_14 pass
2776 23:27:05.141834 alsa_mixer-test_get_value_LCALTA_13 pass
2777 23:27:05.146860 alsa_mixer-test_name_LCALTA_13 pass
2778 23:27:05.152429 alsa_mixer-test_write_default_LCALTA_13 pass
2779 23:27:05.152904 alsa_mixer-test_write_valid_LCALTA_13 pass
2780 23:27:05.157962 alsa_mixer-test_write_invalid_LCALTA_13 pass
2781 23:27:05.163486 alsa_mixer-test_event_missing_LCALTA_13 pass
2782 23:27:05.163962 alsa_mixer-test_event_spurious_LCALTA_13 pass
2783 23:27:05.169064 alsa_mixer-test_get_value_LCALTA_12 pass
2784 23:27:05.174588 alsa_mixer-test_name_LCALTA_12 pass
2785 23:27:05.175067 alsa_mixer-test_write_default_LCALTA_12 pass
2786 23:27:05.180189 alsa_mixer-test_write_valid_LCALTA_12 pass
2787 23:27:05.185708 alsa_mixer-test_write_invalid_LCALTA_12 pass
2788 23:27:05.191310 alsa_mixer-test_event_missing_LCALTA_12 pass
2789 23:27:05.191781 alsa_mixer-test_event_spurious_LCALTA_12 pass
2790 23:27:05.196769 alsa_mixer-test_get_value_LCALTA_11 pass
2791 23:27:05.202361 alsa_mixer-test_name_LCALTA_11 pass
2792 23:27:05.202831 alsa_mixer-test_write_default_LCALTA_11 pass
2793 23:27:05.207888 alsa_mixer-test_write_valid_LCALTA_11 pass
2794 23:27:05.213460 alsa_mixer-test_write_invalid_LCALTA_11 pass
2795 23:27:05.213946 alsa_mixer-test_event_missing_LCALTA_11 pass
2796 23:27:05.218961 alsa_mixer-test_event_spurious_LCALTA_11 pass
2797 23:27:05.224566 alsa_mixer-test_get_value_LCALTA_10 pass
2798 23:27:05.225079 alsa_mixer-test_name_LCALTA_10 pass
2799 23:27:05.230083 alsa_mixer-test_write_default_LCALTA_10 pass
2800 23:27:05.235635 alsa_mixer-test_write_valid_LCALTA_10 pass
2801 23:27:05.236170 alsa_mixer-test_write_invalid_LCALTA_10 pass
2802 23:27:05.241172 alsa_mixer-test_event_missing_LCALTA_10 pass
2803 23:27:05.246725 alsa_mixer-test_event_spurious_LCALTA_10 pass
2804 23:27:05.252352 alsa_mixer-test_get_value_LCALTA_9 pass
2805 23:27:05.252858 alsa_mixer-test_name_LCALTA_9 pass
2806 23:27:05.257812 alsa_mixer-test_write_default_LCALTA_9 pass
2807 23:27:05.263364 alsa_mixer-test_write_valid_LCALTA_9 pass
2808 23:27:05.263856 alsa_mixer-test_write_invalid_LCALTA_9 pass
2809 23:27:05.268899 alsa_mixer-test_event_missing_LCALTA_9 pass
2810 23:27:05.274454 alsa_mixer-test_event_spurious_LCALTA_9 pass
2811 23:27:05.274975 alsa_mixer-test_get_value_LCALTA_8 pass
2812 23:27:05.280037 alsa_mixer-test_name_LCALTA_8 pass
2813 23:27:05.285594 alsa_mixer-test_write_default_LCALTA_8 pass
2814 23:27:05.286131 alsa_mixer-test_write_valid_LCALTA_8 pass
2815 23:27:05.291124 alsa_mixer-test_write_invalid_LCALTA_8 pass
2816 23:27:05.296668 alsa_mixer-test_event_missing_LCALTA_8 pass
2817 23:27:05.297187 alsa_mixer-test_event_spurious_LCALTA_8 pass
2818 23:27:05.302233 alsa_mixer-test_get_value_LCALTA_7 pass
2819 23:27:05.307773 alsa_mixer-test_name_LCALTA_7 pass
2820 23:27:05.308347 alsa_mixer-test_write_default_LCALTA_7 pass
2821 23:27:05.313395 alsa_mixer-test_write_valid_LCALTA_7 pass
2822 23:27:05.318892 alsa_mixer-test_write_invalid_LCALTA_7 pass
2823 23:27:05.319427 alsa_mixer-test_event_missing_LCALTA_7 pass
2824 23:27:05.324465 alsa_mixer-test_event_spurious_LCALTA_7 pass
2825 23:27:05.329939 alsa_mixer-test_get_value_LCALTA_6 pass
2826 23:27:05.330477 alsa_mixer-test_name_LCALTA_6 pass
2827 23:27:05.335486 alsa_mixer-test_write_default_LCALTA_6 pass
2828 23:27:05.341044 alsa_mixer-test_write_valid_LCALTA_6 pass
2829 23:27:05.341567 alsa_mixer-test_write_invalid_LCALTA_6 pass
2830 23:27:05.346583 alsa_mixer-test_event_missing_LCALTA_6 pass
2831 23:27:05.352159 alsa_mixer-test_event_spurious_LCALTA_6 pass
2832 23:27:05.352681 alsa_mixer-test_get_value_LCALTA_5 pass
2833 23:27:05.357677 alsa_mixer-test_name_LCALTA_5 pass
2834 23:27:05.363234 alsa_mixer-test_write_default_LCALTA_5 pass
2835 23:27:05.363772 alsa_mixer-test_write_valid_LCALTA_5 pass
2836 23:27:05.368779 alsa_mixer-test_write_invalid_LCALTA_5 pass
2837 23:27:05.374376 alsa_mixer-test_event_missing_LCALTA_5 pass
2838 23:27:05.374904 alsa_mixer-test_event_spurious_LCALTA_5 pass
2839 23:27:05.379845 alsa_mixer-test_get_value_LCALTA_4 pass
2840 23:27:05.385393 alsa_mixer-test_name_LCALTA_4 pass
2841 23:27:05.385885 alsa_mixer-test_write_default_LCALTA_4 pass
2842 23:27:05.390954 alsa_mixer-test_write_valid_LCALTA_4 pass
2843 23:27:05.396505 alsa_mixer-test_write_invalid_LCALTA_4 pass
2844 23:27:05.397034 alsa_mixer-test_event_missing_LCALTA_4 pass
2845 23:27:05.402092 alsa_mixer-test_event_spurious_LCALTA_4 pass
2846 23:27:05.407629 alsa_mixer-test_get_value_LCALTA_3 pass
2847 23:27:05.408188 alsa_mixer-test_name_LCALTA_3 pass
2848 23:27:05.413144 alsa_mixer-test_write_default_LCALTA_3 pass
2849 23:27:05.418672 alsa_mixer-test_write_valid_LCALTA_3 pass
2850 23:27:05.419201 alsa_mixer-test_write_invalid_LCALTA_3 pass
2851 23:27:05.424288 alsa_mixer-test_event_missing_LCALTA_3 pass
2852 23:27:05.429788 alsa_mixer-test_event_spurious_LCALTA_3 pass
2853 23:27:05.430314 alsa_mixer-test_get_value_LCALTA_2 pass
2854 23:27:05.435369 alsa_mixer-test_name_LCALTA_2 pass
2855 23:27:05.440894 alsa_mixer-test_write_default_LCALTA_2 pass
2856 23:27:05.441423 alsa_mixer-test_write_valid_LCALTA_2 pass
2857 23:27:05.446415 alsa_mixer-test_write_invalid_LCALTA_2 pass
2858 23:27:05.452019 alsa_mixer-test_event_missing_LCALTA_2 pass
2859 23:27:05.457502 alsa_mixer-test_event_spurious_LCALTA_2 pass
2860 23:27:05.458024 alsa_mixer-test_get_value_LCALTA_1 pass
2861 23:27:05.463056 alsa_mixer-test_name_LCALTA_1 pass
2862 23:27:05.463560 alsa_mixer-test_write_default_LCALTA_1 pass
2863 23:27:05.468612 alsa_mixer-test_write_valid_LCALTA_1 pass
2864 23:27:05.474164 alsa_mixer-test_write_invalid_LCALTA_1 pass
2865 23:27:05.479681 alsa_mixer-test_event_missing_LCALTA_1 pass
2866 23:27:05.480222 alsa_mixer-test_event_spurious_LCALTA_1 pass
2867 23:27:05.485256 alsa_mixer-test_get_value_LCALTA_0 pass
2868 23:27:05.485748 alsa_mixer-test_name_LCALTA_0 pass
2869 23:27:05.490757 alsa_mixer-test_write_default_LCALTA_0 pass
2870 23:27:05.496370 alsa_mixer-test_write_valid_LCALTA_0 pass
2871 23:27:05.501894 alsa_mixer-test_write_invalid_LCALTA_0 pass
2872 23:27:05.502403 alsa_mixer-test_event_missing_LCALTA_0 pass
2873 23:27:05.507444 alsa_mixer-test_event_spurious_LCALTA_0 pass
2874 23:27:05.507972 alsa_mixer-test pass
2875 23:27:05.513009 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2876 23:27:05.518538 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2877 23:27:05.524086 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2878 23:27:05.529617 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2879 23:27:05.530136 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2880 23:27:05.535127 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2881 23:27:05.540716 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2882 23:27:05.546248 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2883 23:27:05.551800 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2884 23:27:05.557402 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2885 23:27:05.558019 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2886 23:27:05.562920 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2887 23:27:05.568410 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2888 23:27:05.573976 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2889 23:27:05.579503 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2890 23:27:05.585073 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2891 23:27:05.585565 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2892 23:27:05.590633 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2893 23:27:05.596221 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2894 23:27:05.601701 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2895 23:27:05.607262 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2896 23:27:05.612788 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2897 23:27:05.613265 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2898 23:27:05.618349 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2899 23:27:05.623868 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2900 23:27:05.629460 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2901 23:27:05.634968 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2902 23:27:05.640522 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2903 23:27:05.640991 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2904 23:27:05.646052 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2905 23:27:05.651627 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2906 23:27:05.657200 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2907 23:27:05.662706 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2908 23:27:05.668278 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2909 23:27:05.673830 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2910 23:27:05.674308 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2911 23:27:05.679405 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2912 23:27:05.684922 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2913 23:27:05.690437 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2914 23:27:05.696041 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2915 23:27:05.701549 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2916 23:27:05.702033 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2917 23:27:05.707099 alsa_pcm-test pass
2918 23:27:05.712645 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2919 23:27:05.723714 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2920 23:27:05.729327 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2921 23:27:05.740353 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2922 23:27:05.745943 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2923 23:27:05.751493 alsa_test-pcmtest-driver pass
2924 23:27:05.757026 alsa_utimer-test_global_wrong_timers_test pass
2925 23:27:05.757533 alsa_utimer-test_timer_f_utimer fail
2926 23:27:05.762675 alsa_utimer-test fail
2927 23:27:05.763236 + ../../utils/send-to-lava.sh ./output/result.txt
2928 23:27:05.768196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2929 23:27:05.769169 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2931 23:27:05.779188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2932 23:27:05.780054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2934 23:27:05.784944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2935 23:27:05.785735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2937 23:27:05.798242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2938 23:27:05.799039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2940 23:27:05.846208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2941 23:27:05.846969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2943 23:27:05.894522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2944 23:27:05.895327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2946 23:27:05.946660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2947 23:27:05.947477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2949 23:27:06.001995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2950 23:27:06.002813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2952 23:27:06.055165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2953 23:27:06.055966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2955 23:27:06.111208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2956 23:27:06.112086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2958 23:27:06.175112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2959 23:27:06.175939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2961 23:27:06.229697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2962 23:27:06.230566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2964 23:27:06.280561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2965 23:27:06.281429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2967 23:27:06.339513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2968 23:27:06.340246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2970 23:27:06.387906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2971 23:27:06.388848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2973 23:27:06.436287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2974 23:27:06.436944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2976 23:27:06.488967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2977 23:27:06.489642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2979 23:27:06.536350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2980 23:27:06.536990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2982 23:27:06.592494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2983 23:27:06.593144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2985 23:27:06.648309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2986 23:27:06.649248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2988 23:27:06.697601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2989 23:27:06.698245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2991 23:27:06.750362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2992 23:27:06.751281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2994 23:27:06.803508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2995 23:27:06.804462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2997 23:27:06.851087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2998 23:27:06.851716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
3000 23:27:06.908289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
3001 23:27:06.908913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
3003 23:27:06.961584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3004 23:27:06.962204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3006 23:27:07.014054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3007 23:27:07.014679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3009 23:27:07.058716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3010 23:27:07.059386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3012 23:27:07.112041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3013 23:27:07.112713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3015 23:27:07.164125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3016 23:27:07.164769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3018 23:27:07.218260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3019 23:27:07.218926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3021 23:27:07.273548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3022 23:27:07.274199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3024 23:27:07.323432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3025 23:27:07.324177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3027 23:27:07.372574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3028 23:27:07.373396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3030 23:27:07.422124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3031 23:27:07.422929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3033 23:27:07.474108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3034 23:27:07.474907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3036 23:27:07.519290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3037 23:27:07.520108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3039 23:27:07.567275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3040 23:27:07.568099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3042 23:27:07.626567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3043 23:27:07.627452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3045 23:27:07.674266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3046 23:27:07.675126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3048 23:27:07.731199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3049 23:27:07.732090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3051 23:27:07.784343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3052 23:27:07.785253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3054 23:27:07.829068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3055 23:27:07.830023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3057 23:27:07.882986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3058 23:27:07.883850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3060 23:27:07.930180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3061 23:27:07.931026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3063 23:27:07.980232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3064 23:27:07.981094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3066 23:27:08.029011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3067 23:27:08.029889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3069 23:27:08.078205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3070 23:27:08.079036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3072 23:27:08.134083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3073 23:27:08.134929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3075 23:27:08.177895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3076 23:27:08.178909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3078 23:27:08.232452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3079 23:27:08.233437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3081 23:27:08.279549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3082 23:27:08.280512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3084 23:27:08.329497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3085 23:27:08.330451 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3087 23:27:08.381845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3088 23:27:08.382884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3090 23:27:08.436029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3091 23:27:08.436687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3093 23:27:08.481164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3094 23:27:08.481841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3096 23:27:08.534642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3097 23:27:08.535577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3099 23:27:08.579647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3100 23:27:08.580745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3102 23:27:08.639971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3103 23:27:08.641013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3105 23:27:08.693579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3106 23:27:08.694309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3108 23:27:08.751836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3109 23:27:08.752843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3111 23:27:08.798759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3112 23:27:08.799783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3114 23:27:08.854734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3115 23:27:08.855661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3117 23:27:08.903957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3118 23:27:08.905087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3120 23:27:08.953818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3121 23:27:08.954818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3123 23:27:09.004575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3124 23:27:09.005623 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3126 23:27:09.057455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3127 23:27:09.058481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3129 23:27:09.114018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3130 23:27:09.114917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3132 23:27:09.167533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3133 23:27:09.168499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3135 23:27:09.215612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3136 23:27:09.216699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3138 23:27:09.270074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3139 23:27:09.270999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3141 23:27:09.323729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3142 23:27:09.324686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3144 23:27:09.371904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3145 23:27:09.372941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3147 23:27:09.423088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3148 23:27:09.424083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3150 23:27:09.476248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3151 23:27:09.477107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3153 23:27:09.529153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3154 23:27:09.530091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3156 23:27:09.574157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3157 23:27:09.575115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3159 23:27:09.622694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3160 23:27:09.623723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3162 23:27:09.681016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3163 23:27:09.681902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3165 23:27:09.726370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3166 23:27:09.727307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3168 23:27:09.781865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3169 23:27:09.782731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3171 23:27:09.829455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3172 23:27:09.830350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3174 23:27:09.881805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3175 23:27:09.882705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3177 23:27:09.926739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3178 23:27:09.927392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3180 23:27:09.988844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3181 23:27:09.989714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3183 23:27:10.038600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3184 23:27:10.039536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3186 23:27:10.091647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3187 23:27:10.092484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3189 23:27:10.143300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3190 23:27:10.143941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3192 23:27:10.193588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3193 23:27:10.194374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3195 23:27:10.255219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3196 23:27:10.256911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3198 23:27:10.307857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3199 23:27:10.308809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3201 23:27:10.360955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3202 23:27:10.362412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3204 23:27:10.414913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3205 23:27:10.415836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3207 23:27:10.470636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3208 23:27:10.472299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3210 23:27:10.528211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3211 23:27:10.529696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3213 23:27:10.580758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3214 23:27:10.581673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3216 23:27:10.638451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3217 23:27:10.639932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3219 23:27:10.685993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3220 23:27:10.686917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3222 23:27:10.734194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3223 23:27:10.735116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3225 23:27:10.783506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3226 23:27:10.784582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3228 23:27:10.833974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3229 23:27:10.834948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3231 23:27:10.884511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3232 23:27:10.885408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3234 23:27:10.934208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3235 23:27:10.935195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3237 23:27:10.991407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3238 23:27:10.992361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3240 23:27:11.051197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3241 23:27:11.052117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3243 23:27:11.097481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3244 23:27:11.098480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3246 23:27:11.150581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3247 23:27:11.151568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3249 23:27:11.209031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3250 23:27:11.210002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3252 23:27:11.263468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3253 23:27:11.264437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3255 23:27:11.311117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3256 23:27:11.312114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3258 23:27:11.362399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3259 23:27:11.363466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3261 23:27:11.416431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3262 23:27:11.417832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3264 23:27:11.469125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3265 23:27:11.470228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3267 23:27:11.522196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3268 23:27:11.523112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3270 23:27:11.565837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3271 23:27:11.566850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3273 23:27:11.619144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3274 23:27:11.620153 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3276 23:27:11.667679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3277 23:27:11.668687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3279 23:27:11.711773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3280 23:27:11.712789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3282 23:27:11.761739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3283 23:27:11.762588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3285 23:27:11.812273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3286 23:27:11.813109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3288 23:27:11.869908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3289 23:27:11.870689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3291 23:27:11.919519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3292 23:27:11.920337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3294 23:27:11.970186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3295 23:27:11.970946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3297 23:27:12.020378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3298 23:27:12.021177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3300 23:27:12.072123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3301 23:27:12.072913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3303 23:27:12.120074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3304 23:27:12.120681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3306 23:27:12.174253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3307 23:27:12.174984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3309 23:27:12.231127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3310 23:27:12.232032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3312 23:27:12.284493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3313 23:27:12.285308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3315 23:27:12.343544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3316 23:27:12.344170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3318 23:27:12.390565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3319 23:27:12.391355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3321 23:27:12.695482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3322 23:27:12.696321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3324 23:27:12.747538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3325 23:27:12.748376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3327 23:27:12.797332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3328 23:27:12.798187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3330 23:27:12.850790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3331 23:27:12.851564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3333 23:27:12.911233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3334 23:27:12.912106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3336 23:27:12.972824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3337 23:27:12.973697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3339 23:27:13.024470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3340 23:27:13.025285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3342 23:27:13.076443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3343 23:27:13.077283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3345 23:27:13.127764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3346 23:27:13.128529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3348 23:27:13.178862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3349 23:27:13.179614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3351 23:27:13.232408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3352 23:27:13.233251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3354 23:27:13.283811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3355 23:27:13.284656 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3357 23:27:13.333968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3358 23:27:13.334721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3360 23:27:13.388230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3361 23:27:13.388988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3363 23:27:13.433301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3364 23:27:13.434030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3366 23:27:13.481719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3367 23:27:13.482558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3369 23:27:13.528257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3370 23:27:13.529096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3372 23:27:13.582389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3373 23:27:13.583231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3375 23:27:13.637217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3376 23:27:13.637995 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3378 23:27:13.687581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3379 23:27:13.688441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3381 23:27:13.739654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3382 23:27:13.740568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3384 23:27:13.783047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3385 23:27:13.783919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3387 23:27:13.829147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3388 23:27:13.830043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3390 23:27:13.886887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3391 23:27:13.887524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3393 23:27:13.937540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3394 23:27:13.938144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3396 23:27:13.989648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3397 23:27:13.990490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3399 23:27:14.041469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3400 23:27:14.042066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3402 23:27:14.094894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3403 23:27:14.095811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3405 23:27:14.145890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3406 23:27:14.146789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3408 23:27:14.197960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3409 23:27:14.198846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3411 23:27:14.247625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3412 23:27:14.248537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3414 23:27:14.299448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3415 23:27:14.300316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3417 23:27:14.347072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3418 23:27:14.347893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3420 23:27:14.407246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3421 23:27:14.408108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3423 23:27:14.462016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3424 23:27:14.462825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3426 23:27:14.515719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3427 23:27:14.516586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3429 23:27:14.570384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3430 23:27:14.571239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3432 23:27:14.625534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3433 23:27:14.626397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3435 23:27:14.680819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3436 23:27:14.681689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3438 23:27:14.741355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3439 23:27:14.742223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3441 23:27:14.793622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3442 23:27:14.794449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3444 23:27:14.844957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3445 23:27:14.845763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3447 23:27:14.898536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3448 23:27:14.899331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3450 23:27:14.951729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3451 23:27:14.952538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3453 23:27:15.004796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3454 23:27:15.005579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3456 23:27:15.052120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3457 23:27:15.052948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3459 23:27:15.097148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3460 23:27:15.097928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3462 23:27:15.147107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3463 23:27:15.147883 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3465 23:27:15.197387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3466 23:27:15.198218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3468 23:27:15.252925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3469 23:27:15.253785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3471 23:27:15.305360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3472 23:27:15.306180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3474 23:27:15.350924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3475 23:27:15.351757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3477 23:27:15.408034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3478 23:27:15.408893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3480 23:27:15.461336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3481 23:27:15.462190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3483 23:27:15.509092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3484 23:27:15.509927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3486 23:27:15.559694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3487 23:27:15.560549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3489 23:27:15.608648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3490 23:27:15.609449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3492 23:27:15.658862 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3494 23:27:15.661189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3495 23:27:15.707947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3496 23:27:15.708773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3498 23:27:15.759041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3499 23:27:15.759831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3501 23:27:15.805449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3502 23:27:15.806298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3504 23:27:15.855529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3505 23:27:15.856360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3507 23:27:15.906014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3508 23:27:15.906875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3510 23:27:15.962039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3511 23:27:15.962872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3513 23:27:16.018399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3514 23:27:16.019223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3516 23:27:16.073275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3517 23:27:16.074106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3519 23:27:16.123586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3520 23:27:16.124478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3522 23:27:16.180974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3523 23:27:16.181808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3525 23:27:16.234927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3526 23:27:16.235771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3528 23:27:16.284519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3529 23:27:16.285398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3531 23:27:16.330014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3532 23:27:16.330923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3534 23:27:16.375502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3535 23:27:16.376390 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3537 23:27:16.433273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3538 23:27:16.434061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3540 23:27:16.482871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3541 23:27:16.483645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3543 23:27:16.533593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3544 23:27:16.534368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3546 23:27:16.577210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3547 23:27:16.578030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3549 23:27:16.618455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3550 23:27:16.619219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3552 23:27:16.659642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3553 23:27:16.660438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3555 23:27:16.711100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3556 23:27:16.711872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3558 23:27:16.762732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3559 23:27:16.763510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3561 23:27:16.817585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3562 23:27:16.818356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3564 23:27:16.863154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3565 23:27:16.863947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3567 23:27:16.921538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3568 23:27:16.922372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3570 23:27:16.965654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3571 23:27:16.966420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3573 23:27:17.008783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3574 23:27:17.009568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3576 23:27:17.066711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3577 23:27:17.067351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3579 23:27:17.118620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3580 23:27:17.119542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3582 23:27:17.167314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3583 23:27:17.168226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3585 23:27:17.219023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3586 23:27:17.219657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3588 23:27:17.273318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3589 23:27:17.274176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3591 23:27:17.330706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3592 23:27:17.331561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3594 23:27:17.378345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3595 23:27:17.379234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3597 23:27:17.430920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3598 23:27:17.431835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3600 23:27:17.481092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3601 23:27:17.481994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3603 23:27:17.534356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3604 23:27:17.535244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3606 23:27:17.584881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3607 23:27:17.585780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3609 23:27:17.641568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3610 23:27:17.642461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3612 23:27:17.687703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3613 23:27:17.688632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3615 23:27:17.731590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3616 23:27:17.732272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3618 23:27:17.779750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3619 23:27:17.780395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3621 23:27:17.821793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3622 23:27:17.822436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3624 23:27:17.882539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3625 23:27:17.883410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3627 23:27:17.930688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3628 23:27:17.931326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3630 23:27:17.983763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3631 23:27:17.984493 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3633 23:27:18.034309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3634 23:27:18.034910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3636 23:27:18.089871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3637 23:27:18.090787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3639 23:27:18.141227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3640 23:27:18.142095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3642 23:27:18.196720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3643 23:27:18.197608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3645 23:27:18.251221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3646 23:27:18.252053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3648 23:27:18.311795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3649 23:27:18.312583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3651 23:27:18.365855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3652 23:27:18.366586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3654 23:27:18.411066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3655 23:27:18.411808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3657 23:27:18.473123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3658 23:27:18.474035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3660 23:27:18.525150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3661 23:27:18.526000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3663 23:27:18.577135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3664 23:27:18.577997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3666 23:27:18.632453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3667 23:27:18.633303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3669 23:27:18.681855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3670 23:27:18.682632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3672 23:27:18.727522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3673 23:27:18.728309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3675 23:27:18.772442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3676 23:27:18.773319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3678 23:27:18.820484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3679 23:27:18.821324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3681 23:27:18.868380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3682 23:27:18.869265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3684 23:27:18.928940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3685 23:27:18.929802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3687 23:27:18.979963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3688 23:27:18.980862 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3690 23:27:19.029283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3691 23:27:19.030234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3693 23:27:19.086643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3694 23:27:19.087479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3696 23:27:19.134541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3697 23:27:19.135282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3699 23:27:19.185583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3700 23:27:19.186428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3702 23:27:19.235861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3703 23:27:19.236739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3705 23:27:19.293819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3706 23:27:19.294680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3708 23:27:19.346918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3709 23:27:19.347779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3711 23:27:19.400698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3712 23:27:19.401619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3714 23:27:19.453474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3715 23:27:19.454304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3717 23:27:19.498476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3718 23:27:19.499317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3720 23:27:19.543923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3721 23:27:19.544791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3723 23:27:19.591341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3724 23:27:19.592184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3726 23:27:19.653004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3727 23:27:19.653827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3729 23:27:19.703744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3730 23:27:19.704631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3732 23:27:19.763362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3733 23:27:19.764178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3735 23:27:19.815169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3736 23:27:19.816052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3738 23:27:19.873881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3739 23:27:19.874776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3741 23:27:19.930295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3742 23:27:19.931247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3744 23:27:19.980481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3745 23:27:19.981494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3747 23:27:20.039505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3748 23:27:20.040403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3750 23:27:20.083658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3751 23:27:20.084549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3753 23:27:20.133568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3754 23:27:20.134421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3756 23:27:20.183332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3757 23:27:20.184194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3759 23:27:20.238863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3760 23:27:20.239739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3762 23:27:20.297247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3763 23:27:20.298103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3765 23:27:20.352389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3766 23:27:20.353246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3768 23:27:20.403315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3769 23:27:20.404190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3771 23:27:20.461592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3772 23:27:20.462648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3774 23:27:20.513573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3775 23:27:20.514419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3777 23:27:20.562615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3778 23:27:20.563454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3780 23:27:20.618389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3781 23:27:20.619185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3783 23:27:20.661979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3784 23:27:20.662778 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3786 23:27:20.717188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3787 23:27:20.717975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3789 23:27:20.773369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3790 23:27:20.774249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3792 23:27:20.820882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3793 23:27:20.822219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3795 23:27:20.865457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3796 23:27:20.866354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3798 23:27:20.922628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3799 23:27:20.923548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3801 23:27:20.974454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3802 23:27:20.975401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3804 23:27:21.020566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3805 23:27:21.021185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3807 23:27:21.078956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3808 23:27:21.079657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3810 23:27:21.133551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3811 23:27:21.134205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3813 23:27:21.181616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3814 23:27:21.182511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3816 23:27:21.233308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3817 23:27:21.234226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3819 23:27:21.280958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3820 23:27:21.281792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3822 23:27:21.334105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3823 23:27:21.334878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3825 23:27:21.389971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3826 23:27:21.390597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3828 23:27:21.439396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3829 23:27:21.440358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3831 23:27:21.499839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3832 23:27:21.500822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3834 23:27:21.541551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3835 23:27:21.542527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3837 23:27:21.591563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3838 23:27:21.592604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3840 23:27:21.639018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3841 23:27:21.640091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3843 23:27:21.689223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3844 23:27:21.689844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3846 23:27:21.734092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3847 23:27:21.734993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3849 23:27:21.778900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3850 23:27:21.779631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3852 23:27:21.821634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3853 23:27:21.822645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3855 23:27:21.874781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3856 23:27:21.875843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3858 23:27:21.927162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3859 23:27:21.928425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3861 23:27:21.979546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3862 23:27:21.980860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3864 23:27:22.031792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3865 23:27:22.032901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3867 23:27:22.082203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3868 23:27:22.083320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3870 23:27:22.128276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3871 23:27:22.129533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3873 23:27:22.173729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3874 23:27:22.174852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3876 23:27:22.221791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3877 23:27:22.222640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3879 23:27:22.276619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3880 23:27:22.277452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3882 23:27:22.330702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3883 23:27:22.331519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3885 23:27:22.374681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3886 23:27:22.375491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3888 23:27:22.429266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3889 23:27:22.430081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3891 23:27:22.479353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3892 23:27:22.480188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3894 23:27:22.525928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3895 23:27:22.526737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3897 23:27:22.578436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3898 23:27:22.579285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3900 23:27:22.631348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3901 23:27:22.632166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3903 23:27:22.676502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3904 23:27:22.677312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3906 23:27:22.730048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3907 23:27:22.730875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3909 23:27:22.780020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3910 23:27:22.780839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3912 23:27:22.825863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3913 23:27:22.826722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3915 23:27:22.885581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3916 23:27:22.886447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3918 23:27:22.943739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3919 23:27:22.944614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3921 23:27:22.999571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3922 23:27:23.000437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3924 23:27:23.057833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3925 23:27:23.058682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3927 23:27:23.117686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3928 23:27:23.118496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3930 23:27:23.177104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3931 23:27:23.177905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3933 23:27:23.236021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3934 23:27:23.236847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3936 23:27:23.295689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3937 23:27:23.296634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3939 23:27:23.341328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3940 23:27:23.342057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3942 23:27:23.400352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3943 23:27:23.401189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3945 23:27:23.461042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3946 23:27:23.461893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3948 23:27:23.521191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3949 23:27:23.521982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3951 23:27:23.573585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3952 23:27:23.574366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3954 23:27:23.623469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3955 23:27:23.624044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3957 23:27:23.670296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3958 23:27:23.671069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3960 23:27:23.729284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3961 23:27:23.730055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3963 23:27:23.775691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3964 23:27:23.776565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3966 23:27:23.827369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3967 23:27:23.828227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3969 23:27:23.881593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3970 23:27:23.882324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3972 23:27:23.935545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3973 23:27:23.936534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3975 23:27:23.990328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3976 23:27:23.991270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3978 23:27:24.041934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3979 23:27:24.042868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3981 23:27:24.099928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3982 23:27:24.100835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3984 23:27:24.153785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3985 23:27:24.154730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3987 23:27:24.206165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3988 23:27:24.207073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3990 23:27:24.256173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3991 23:27:24.256826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3993 23:27:24.305307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3994 23:27:24.305942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3996 23:27:24.356078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3997 23:27:24.356947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3999 23:27:24.413741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
4000 23:27:24.414413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
4002 23:27:24.460950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
4003 23:27:24.461575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4005 23:27:24.511201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4006 23:27:24.511850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4008 23:27:24.571121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4009 23:27:24.572013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4011 23:27:24.623231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4012 23:27:24.624084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4014 23:27:24.673038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4015 23:27:24.673920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4017 23:27:24.718620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4018 23:27:24.719725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4020 23:27:24.761224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4021 23:27:24.761970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4023 23:27:24.806463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4024 23:27:24.807853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4026 23:27:24.858077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4027 23:27:24.860858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4029 23:27:24.908081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4030 23:27:24.908957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4032 23:27:24.959164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4033 23:27:24.960379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4035 23:27:25.005726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4036 23:27:25.007190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4038 23:27:25.058746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4039 23:27:25.059640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4041 23:27:25.100619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4042 23:27:25.102291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4044 23:27:25.154544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4045 23:27:25.155411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4047 23:27:25.198145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4048 23:27:25.199160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4050 23:27:25.246346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4051 23:27:25.246982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4053 23:27:25.295067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4054 23:27:25.295930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4056 23:27:25.338013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4057 23:27:25.339004 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4059 23:27:25.383696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4060 23:27:25.385074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4062 23:27:25.429540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4063 23:27:25.430294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4065 23:27:25.483481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4066 23:27:25.484325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4068 23:27:25.526081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4069 23:27:25.526976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4071 23:27:25.578937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4072 23:27:25.579726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4074 23:27:25.629227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4075 23:27:25.630013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4077 23:27:25.681965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4078 23:27:25.682718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4080 23:27:25.736861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4081 23:27:25.737615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4083 23:27:25.780373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4084 23:27:25.781124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4086 23:27:25.824570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4087 23:27:25.825374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4089 23:27:25.881345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4090 23:27:25.882218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4092 23:27:25.936257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4093 23:27:25.937069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4095 23:27:25.979729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4096 23:27:25.980551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4098 23:27:26.030944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4099 23:27:26.031697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4101 23:27:26.075839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4102 23:27:26.076591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4104 23:27:26.117646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4105 23:27:26.118372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4107 23:27:26.166423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4108 23:27:26.167227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4110 23:27:26.212635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4111 23:27:26.213489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4113 23:27:26.272406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4114 23:27:26.273276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4116 23:27:26.327148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4117 23:27:26.328041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4119 23:27:26.373277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4120 23:27:26.374136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4122 23:27:26.427787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4123 23:27:26.428730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4125 23:27:26.474536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4126 23:27:26.475538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4128 23:27:26.527260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4129 23:27:26.528379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4131 23:27:26.578290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4132 23:27:26.579365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4134 23:27:26.631303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4135 23:27:26.632406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4137 23:27:26.691697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4138 23:27:26.692822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4140 23:27:26.746440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4141 23:27:26.747463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4143 23:27:26.807027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4144 23:27:26.807748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4146 23:27:26.851304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4147 23:27:26.852149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4149 23:27:26.904190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4150 23:27:26.905047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4152 23:27:26.961924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4153 23:27:26.962816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4155 23:27:27.009316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4156 23:27:27.010279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4158 23:27:27.064214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4159 23:27:27.065142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4161 23:27:27.114732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4162 23:27:27.115638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4164 23:27:27.167022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4165 23:27:27.167921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4167 23:27:27.217238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4168 23:27:27.218158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4170 23:27:27.276716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4171 23:27:27.277412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4173 23:27:27.329090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4174 23:27:27.329950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4176 23:27:27.374515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4177 23:27:27.375334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4179 23:27:27.430400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4180 23:27:27.431226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4182 23:27:27.475617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4183 23:27:27.476443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4185 23:27:27.528860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4186 23:27:27.529669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4188 23:27:27.576270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4189 23:27:27.577076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4191 23:27:27.628536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4192 23:27:27.629340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4194 23:27:27.682635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4195 23:27:27.683457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4197 23:27:27.733364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4198 23:27:27.734236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4200 23:27:27.784203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4201 23:27:27.785075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4203 23:27:27.840280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4204 23:27:27.841134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4206 23:27:27.893023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4207 23:27:27.893877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4209 23:27:28.192129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4210 23:27:28.192763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4211 23:27:28.193208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4212 23:27:28.193639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4213 23:27:28.194055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4214 23:27:28.194802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4216 23:27:28.196194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4218 23:27:28.197449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4220 23:27:28.198673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4222 23:27:28.199877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4224 23:27:28.201202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4225 23:27:28.201901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4227 23:27:28.236347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4228 23:27:28.236996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4230 23:27:28.304839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4231 23:27:28.305504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4233 23:27:28.348143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4234 23:27:28.348982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4236 23:27:28.397037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4237 23:27:28.397848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4239 23:27:28.453542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4240 23:27:28.454336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4242 23:27:28.503818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4243 23:27:28.504691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4245 23:27:28.554202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4246 23:27:28.555027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4248 23:27:28.608873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4249 23:27:28.609740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4251 23:27:28.666492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4252 23:27:28.667349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4254 23:27:28.717458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4255 23:27:28.718294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4257 23:27:28.763867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4258 23:27:28.764749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4260 23:27:28.816232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4261 23:27:28.817091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4263 23:27:28.864968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4264 23:27:28.865621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4266 23:27:28.914836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4267 23:27:28.915423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4269 23:27:28.966519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4270 23:27:28.967123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4272 23:27:29.016888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4273 23:27:29.017587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4275 23:27:29.074898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4276 23:27:29.075589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4278 23:27:29.124217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4279 23:27:29.124938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4281 23:27:29.180229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4282 23:27:29.180880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4284 23:27:29.235277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4285 23:27:29.236115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4287 23:27:29.288063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4288 23:27:29.288891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4290 23:27:29.349465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4291 23:27:29.350284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4293 23:27:29.406265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4294 23:27:29.407193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4296 23:27:29.459046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4297 23:27:29.459969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4299 23:27:29.511830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4300 23:27:29.512754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4302 23:27:29.563075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4303 23:27:29.563895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4305 23:27:29.621702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4306 23:27:29.622490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4308 23:27:29.676502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4309 23:27:29.677287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4311 23:27:29.739872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4312 23:27:29.740753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4314 23:27:29.794988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4315 23:27:29.795823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4317 23:27:29.842633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4318 23:27:29.843434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4320 23:27:29.901685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4321 23:27:29.902515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4323 23:27:29.955249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4324 23:27:29.956082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4326 23:27:30.007377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4327 23:27:30.008182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4329 23:27:30.064461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4330 23:27:30.065253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4332 23:27:30.108601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4333 23:27:30.109619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4335 23:27:30.160376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4336 23:27:30.161256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4338 23:27:30.211119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4339 23:27:30.212154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4341 23:27:30.259568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4342 23:27:30.260570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4344 23:27:30.317519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4345 23:27:30.318395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4347 23:27:30.371001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4348 23:27:30.371878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4350 23:27:30.433416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4351 23:27:30.434260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4353 23:27:30.484288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4354 23:27:30.485274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4356 23:27:30.533253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4357 23:27:30.534120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4359 23:27:30.579744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4360 23:27:30.580582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4362 23:27:30.631824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4363 23:27:30.632679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4365 23:27:30.676097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4366 23:27:30.676919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4368 23:27:30.724326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4370 23:27:30.729573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4371 23:27:30.730046 + set +x
4372 23:27:30.735566 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 949203_1.6.2.4.5>
4373 23:27:30.736061 <LAVA_TEST_RUNNER EXIT>
4374 23:27:30.736721 Received signal: <ENDRUN> 1_kselftest-alsa 949203_1.6.2.4.5
4375 23:27:30.737167 Ending use of test pattern.
4376 23:27:30.737567 Ending test lava.1_kselftest-alsa (949203_1.6.2.4.5), duration 41.23
4378 23:27:30.739049 ok: lava_test_shell seems to have completed
4379 23:27:30.761696 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4380 23:27:30.763445 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4381 23:27:30.764052 end: 3 lava-test-retry (duration 00:00:42) [common]
4382 23:27:30.764625 start: 4 finalize (timeout 00:06:08) [common]
4383 23:27:30.765193 start: 4.1 power-off (timeout 00:00:30) [common]
4384 23:27:30.766149 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4385 23:27:30.800821 >> OK - accepted request
4386 23:27:30.804017 Returned 0 in 0 seconds
4387 23:27:30.905232 end: 4.1 power-off (duration 00:00:00) [common]
4389 23:27:30.907025 start: 4.2 read-feedback (timeout 00:06:08) [common]
4390 23:27:30.908238 Listened to connection for namespace 'common' for up to 1s
4391 23:27:31.908994 Finalising connection for namespace 'common'
4392 23:27:31.909766 Disconnecting from shell: Finalise
4393 23:27:31.910286 / #
4394 23:27:32.011253 end: 4.2 read-feedback (duration 00:00:01) [common]
4395 23:27:32.012037 end: 4 finalize (duration 00:00:01) [common]
4396 23:27:32.012718 Cleaning after the job
4397 23:27:32.013331 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/ramdisk
4398 23:27:32.026791 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/kernel
4399 23:27:32.069915 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/dtb
4400 23:27:32.070851 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/nfsrootfs
4401 23:27:32.234190 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949203/tftp-deploy-9co4o65t/modules
4402 23:27:32.253930 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949203
4403 23:27:35.699115 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949203
4404 23:27:35.699680 Job finished correctly