Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 00:00:40.337732 lava-dispatcher, installed at version: 2024.01
2 00:00:40.338553 start: 0 validate
3 00:00:40.339034 Start time: 2024-11-07 00:00:40.339003+00:00 (UTC)
4 00:00:40.339590 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:00:40.340157 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:00:40.378184 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:00:40.378716 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 00:00:40.408450 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:00:40.409070 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 00:00:40.444442 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:00:40.444938 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:00:40.477259 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 00:00:40.477774 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 00:00:40.515075 validate duration: 0.18
16 00:00:40.516004 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:00:40.516363 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:00:40.516725 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:00:40.517341 Not decompressing ramdisk as can be used compressed.
20 00:00:40.517816 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 00:00:40.518121 saving as /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/ramdisk/initrd.cpio.gz
22 00:00:40.518428 total size: 5628140 (5 MB)
23 00:00:40.555574 progress 0 % (0 MB)
24 00:00:40.563701 progress 5 % (0 MB)
25 00:00:40.571295 progress 10 % (0 MB)
26 00:00:40.578130 progress 15 % (0 MB)
27 00:00:40.583014 progress 20 % (1 MB)
28 00:00:40.586561 progress 25 % (1 MB)
29 00:00:40.590505 progress 30 % (1 MB)
30 00:00:40.594521 progress 35 % (1 MB)
31 00:00:40.598108 progress 40 % (2 MB)
32 00:00:40.601952 progress 45 % (2 MB)
33 00:00:40.605421 progress 50 % (2 MB)
34 00:00:40.609305 progress 55 % (2 MB)
35 00:00:40.613130 progress 60 % (3 MB)
36 00:00:40.616586 progress 65 % (3 MB)
37 00:00:40.620474 progress 70 % (3 MB)
38 00:00:40.623891 progress 75 % (4 MB)
39 00:00:40.627708 progress 80 % (4 MB)
40 00:00:40.631010 progress 85 % (4 MB)
41 00:00:40.634737 progress 90 % (4 MB)
42 00:00:40.638345 progress 95 % (5 MB)
43 00:00:40.641604 progress 100 % (5 MB)
44 00:00:40.642235 5 MB downloaded in 0.12 s (43.36 MB/s)
45 00:00:40.642779 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:00:40.643648 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:00:40.643937 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:00:40.644241 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:00:40.644720 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/kernel/Image
51 00:00:40.644962 saving as /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/kernel/Image
52 00:00:40.645171 total size: 45713920 (43 MB)
53 00:00:40.645379 No compression specified
54 00:00:40.680490 progress 0 % (0 MB)
55 00:00:40.707836 progress 5 % (2 MB)
56 00:00:40.735683 progress 10 % (4 MB)
57 00:00:40.762935 progress 15 % (6 MB)
58 00:00:40.790203 progress 20 % (8 MB)
59 00:00:40.817239 progress 25 % (10 MB)
60 00:00:40.844551 progress 30 % (13 MB)
61 00:00:40.872002 progress 35 % (15 MB)
62 00:00:40.901967 progress 40 % (17 MB)
63 00:00:40.931339 progress 45 % (19 MB)
64 00:00:40.959496 progress 50 % (21 MB)
65 00:00:40.987439 progress 55 % (24 MB)
66 00:00:41.015771 progress 60 % (26 MB)
67 00:00:41.044294 progress 65 % (28 MB)
68 00:00:41.072544 progress 70 % (30 MB)
69 00:00:41.102012 progress 75 % (32 MB)
70 00:00:41.131526 progress 80 % (34 MB)
71 00:00:41.160318 progress 85 % (37 MB)
72 00:00:41.188763 progress 90 % (39 MB)
73 00:00:41.216490 progress 95 % (41 MB)
74 00:00:41.243482 progress 100 % (43 MB)
75 00:00:41.244045 43 MB downloaded in 0.60 s (72.80 MB/s)
76 00:00:41.244528 end: 1.2.1 http-download (duration 00:00:01) [common]
78 00:00:41.245335 end: 1.2 download-retry (duration 00:00:01) [common]
79 00:00:41.245607 start: 1.3 download-retry (timeout 00:09:59) [common]
80 00:00:41.245869 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 00:00:41.246346 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 00:00:41.246610 saving as /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/dtb/meson-g12b-a311d-libretech-cc.dtb
83 00:00:41.246815 total size: 54703 (0 MB)
84 00:00:41.247022 No compression specified
85 00:00:41.281807 progress 59 % (0 MB)
86 00:00:41.282652 progress 100 % (0 MB)
87 00:00:41.283196 0 MB downloaded in 0.04 s (1.43 MB/s)
88 00:00:41.283674 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:00:41.284536 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:00:41.284802 start: 1.4 download-retry (timeout 00:09:59) [common]
92 00:00:41.285061 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 00:00:41.285520 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 00:00:41.285755 saving as /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/nfsrootfs/full.rootfs.tar
95 00:00:41.285958 total size: 474398908 (452 MB)
96 00:00:41.286165 Using unxz to decompress xz
97 00:00:41.321248 progress 0 % (0 MB)
98 00:00:42.408950 progress 5 % (22 MB)
99 00:00:43.841335 progress 10 % (45 MB)
100 00:00:44.251904 progress 15 % (67 MB)
101 00:00:45.112350 progress 20 % (90 MB)
102 00:00:45.646195 progress 25 % (113 MB)
103 00:00:46.002587 progress 30 % (135 MB)
104 00:00:46.600780 progress 35 % (158 MB)
105 00:00:47.534255 progress 40 % (181 MB)
106 00:00:48.395738 progress 45 % (203 MB)
107 00:00:49.118894 progress 50 % (226 MB)
108 00:00:49.731743 progress 55 % (248 MB)
109 00:00:50.923800 progress 60 % (271 MB)
110 00:00:52.398810 progress 65 % (294 MB)
111 00:00:54.027813 progress 70 % (316 MB)
112 00:00:57.121879 progress 75 % (339 MB)
113 00:00:59.576065 progress 80 % (361 MB)
114 00:01:02.483215 progress 85 % (384 MB)
115 00:01:05.660169 progress 90 % (407 MB)
116 00:01:08.839600 progress 95 % (429 MB)
117 00:01:12.007153 progress 100 % (452 MB)
118 00:01:12.021011 452 MB downloaded in 30.74 s (14.72 MB/s)
119 00:01:12.021987 end: 1.4.1 http-download (duration 00:00:31) [common]
121 00:01:12.023783 end: 1.4 download-retry (duration 00:00:31) [common]
122 00:01:12.024425 start: 1.5 download-retry (timeout 00:09:28) [common]
123 00:01:12.025012 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 00:01:12.025916 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/modules.tar.xz
125 00:01:12.026434 saving as /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/modules/modules.tar
126 00:01:12.026896 total size: 11608172 (11 MB)
127 00:01:12.027367 Using unxz to decompress xz
128 00:01:12.071646 progress 0 % (0 MB)
129 00:01:12.138216 progress 5 % (0 MB)
130 00:01:12.211637 progress 10 % (1 MB)
131 00:01:12.306758 progress 15 % (1 MB)
132 00:01:12.398291 progress 20 % (2 MB)
133 00:01:12.476854 progress 25 % (2 MB)
134 00:01:12.551666 progress 30 % (3 MB)
135 00:01:12.624821 progress 35 % (3 MB)
136 00:01:12.700991 progress 40 % (4 MB)
137 00:01:12.776358 progress 45 % (5 MB)
138 00:01:12.859921 progress 50 % (5 MB)
139 00:01:12.935942 progress 55 % (6 MB)
140 00:01:13.019866 progress 60 % (6 MB)
141 00:01:13.099802 progress 65 % (7 MB)
142 00:01:13.175294 progress 70 % (7 MB)
143 00:01:13.255885 progress 75 % (8 MB)
144 00:01:13.338662 progress 80 % (8 MB)
145 00:01:13.417895 progress 85 % (9 MB)
146 00:01:13.495866 progress 90 % (9 MB)
147 00:01:13.572645 progress 95 % (10 MB)
148 00:01:13.649769 progress 100 % (11 MB)
149 00:01:13.660779 11 MB downloaded in 1.63 s (6.78 MB/s)
150 00:01:13.661467 end: 1.5.1 http-download (duration 00:00:02) [common]
152 00:01:13.662524 end: 1.5 download-retry (duration 00:00:02) [common]
153 00:01:13.662861 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 00:01:13.663187 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 00:01:30.223195 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/949255/extract-nfsrootfs-7sajd6v_
156 00:01:30.223815 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 00:01:30.224179 start: 1.6.2 lava-overlay (timeout 00:09:10) [common]
158 00:01:30.225042 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt
159 00:01:30.225583 makedir: /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin
160 00:01:30.226000 makedir: /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/tests
161 00:01:30.226402 makedir: /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/results
162 00:01:30.226796 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-add-keys
163 00:01:30.228175 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-add-sources
164 00:01:30.228816 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-background-process-start
165 00:01:30.229356 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-background-process-stop
166 00:01:30.229907 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-common-functions
167 00:01:30.230421 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-echo-ipv4
168 00:01:30.230916 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-install-packages
169 00:01:30.231412 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-installed-packages
170 00:01:30.231900 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-os-build
171 00:01:30.232433 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-probe-channel
172 00:01:30.232928 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-probe-ip
173 00:01:30.233414 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-target-ip
174 00:01:30.233900 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-target-mac
175 00:01:30.234381 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-target-storage
176 00:01:30.234871 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-test-case
177 00:01:30.235357 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-test-event
178 00:01:30.235833 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-test-feedback
179 00:01:30.236379 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-test-raise
180 00:01:30.236946 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-test-reference
181 00:01:30.237443 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-test-runner
182 00:01:30.237938 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-test-set
183 00:01:30.238425 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-test-shell
184 00:01:30.238919 Updating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-install-packages (oe)
185 00:01:30.239458 Updating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/bin/lava-installed-packages (oe)
186 00:01:30.239904 Creating /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/environment
187 00:01:30.240312 LAVA metadata
188 00:01:30.240578 - LAVA_JOB_ID=949255
189 00:01:30.240795 - LAVA_DISPATCHER_IP=192.168.6.2
190 00:01:30.241163 start: 1.6.2.1 ssh-authorize (timeout 00:09:10) [common]
191 00:01:30.242121 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 00:01:30.242444 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:10) [common]
193 00:01:30.242654 skipped lava-vland-overlay
194 00:01:30.242894 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 00:01:30.243146 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:10) [common]
196 00:01:30.243361 skipped lava-multinode-overlay
197 00:01:30.243600 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 00:01:30.243848 start: 1.6.2.4 test-definition (timeout 00:09:10) [common]
199 00:01:30.244130 Loading test definitions
200 00:01:30.244412 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:10) [common]
201 00:01:30.244634 Using /lava-949255 at stage 0
202 00:01:30.245786 uuid=949255_1.6.2.4.1 testdef=None
203 00:01:30.246096 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 00:01:30.246361 start: 1.6.2.4.2 test-overlay (timeout 00:09:10) [common]
205 00:01:30.248083 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 00:01:30.248889 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:10) [common]
208 00:01:30.251018 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 00:01:30.251861 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:10) [common]
211 00:01:30.253951 runner path: /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 949255_1.6.2.4.1
212 00:01:30.254549 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 00:01:30.255332 Creating lava-test-runner.conf files
215 00:01:30.255536 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949255/lava-overlay-8kh_dhtt/lava-949255/0 for stage 0
216 00:01:30.255877 - 0_v4l2-decoder-conformance-h264
217 00:01:30.256253 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 00:01:30.256535 start: 1.6.2.5 compress-overlay (timeout 00:09:10) [common]
219 00:01:30.277798 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 00:01:30.278166 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
221 00:01:30.278428 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 00:01:30.278694 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 00:01:30.278960 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
224 00:01:30.893514 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 00:01:30.893996 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 00:01:30.894251 extracting modules file /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949255/extract-nfsrootfs-7sajd6v_
227 00:01:32.242449 extracting modules file /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949255/extract-overlay-ramdisk-5hbl9en3/ramdisk
228 00:01:33.624032 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 00:01:33.624519 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 00:01:33.624802 [common] Applying overlay to NFS
231 00:01:33.625019 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949255/compress-overlay-jh8uing4/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949255/extract-nfsrootfs-7sajd6v_
232 00:01:33.653864 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 00:01:33.654244 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 00:01:33.654523 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 00:01:33.654754 Converting downloaded kernel to a uImage
236 00:01:33.655063 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/kernel/Image /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/kernel/uImage
237 00:01:34.118201 output: Image Name:
238 00:01:34.118632 output: Created: Thu Nov 7 00:01:33 2024
239 00:01:34.118846 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 00:01:34.119052 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 00:01:34.119256 output: Load Address: 01080000
242 00:01:34.119457 output: Entry Point: 01080000
243 00:01:34.119656 output:
244 00:01:34.120025 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 00:01:34.120314 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 00:01:34.120588 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 00:01:34.120847 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 00:01:34.121107 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 00:01:34.121373 Building ramdisk /var/lib/lava/dispatcher/tmp/949255/extract-overlay-ramdisk-5hbl9en3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949255/extract-overlay-ramdisk-5hbl9en3/ramdisk
250 00:01:36.466228 >> 166825 blocks
251 00:01:44.348444 Adding RAMdisk u-boot header.
252 00:01:44.349087 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949255/extract-overlay-ramdisk-5hbl9en3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949255/extract-overlay-ramdisk-5hbl9en3/ramdisk.cpio.gz.uboot
253 00:01:44.594379 output: Image Name:
254 00:01:44.594787 output: Created: Thu Nov 7 00:01:44 2024
255 00:01:44.595003 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 00:01:44.595210 output: Data Size: 23430887 Bytes = 22881.73 KiB = 22.35 MiB
257 00:01:44.595413 output: Load Address: 00000000
258 00:01:44.595612 output: Entry Point: 00000000
259 00:01:44.595811 output:
260 00:01:44.596855 rename /var/lib/lava/dispatcher/tmp/949255/extract-overlay-ramdisk-5hbl9en3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/ramdisk/ramdisk.cpio.gz.uboot
261 00:01:44.597666 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 00:01:44.598266 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
263 00:01:44.598842 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 00:01:44.599370 No LXC device requested
265 00:01:44.599923 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 00:01:44.600526 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 00:01:44.601078 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 00:01:44.601538 Checking files for TFTP limit of 4294967296 bytes.
269 00:01:44.604464 end: 1 tftp-deploy (duration 00:01:04) [common]
270 00:01:44.605091 start: 2 uboot-action (timeout 00:05:00) [common]
271 00:01:44.605667 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 00:01:44.606211 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 00:01:44.606766 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 00:01:44.607337 Using kernel file from prepare-kernel: 949255/tftp-deploy-7p3crbb3/kernel/uImage
275 00:01:44.608047 substitutions:
276 00:01:44.608500 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 00:01:44.608940 - {DTB_ADDR}: 0x01070000
278 00:01:44.609380 - {DTB}: 949255/tftp-deploy-7p3crbb3/dtb/meson-g12b-a311d-libretech-cc.dtb
279 00:01:44.609816 - {INITRD}: 949255/tftp-deploy-7p3crbb3/ramdisk/ramdisk.cpio.gz.uboot
280 00:01:44.610251 - {KERNEL_ADDR}: 0x01080000
281 00:01:44.610682 - {KERNEL}: 949255/tftp-deploy-7p3crbb3/kernel/uImage
282 00:01:44.611113 - {LAVA_MAC}: None
283 00:01:44.611585 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/949255/extract-nfsrootfs-7sajd6v_
284 00:01:44.612063 - {NFS_SERVER_IP}: 192.168.6.2
285 00:01:44.612274 - {PRESEED_CONFIG}: None
286 00:01:44.612472 - {PRESEED_LOCAL}: None
287 00:01:44.612667 - {RAMDISK_ADDR}: 0x08000000
288 00:01:44.612862 - {RAMDISK}: 949255/tftp-deploy-7p3crbb3/ramdisk/ramdisk.cpio.gz.uboot
289 00:01:44.613144 - {ROOT_PART}: None
290 00:01:44.613582 - {ROOT}: None
291 00:01:44.614011 - {SERVER_IP}: 192.168.6.2
292 00:01:44.614458 - {TEE_ADDR}: 0x83000000
293 00:01:44.614887 - {TEE}: None
294 00:01:44.615313 Parsed boot commands:
295 00:01:44.615729 - setenv autoload no
296 00:01:44.616211 - setenv initrd_high 0xffffffff
297 00:01:44.616643 - setenv fdt_high 0xffffffff
298 00:01:44.617071 - dhcp
299 00:01:44.617498 - setenv serverip 192.168.6.2
300 00:01:44.617924 - tftpboot 0x01080000 949255/tftp-deploy-7p3crbb3/kernel/uImage
301 00:01:44.618357 - tftpboot 0x08000000 949255/tftp-deploy-7p3crbb3/ramdisk/ramdisk.cpio.gz.uboot
302 00:01:44.618784 - tftpboot 0x01070000 949255/tftp-deploy-7p3crbb3/dtb/meson-g12b-a311d-libretech-cc.dtb
303 00:01:44.619211 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/949255/extract-nfsrootfs-7sajd6v_,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 00:01:44.619651 - bootm 0x01080000 0x08000000 0x01070000
305 00:01:44.620230 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 00:01:44.621874 start: 2.3 connect-device (timeout 00:05:00) [common]
308 00:01:44.622338 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 00:01:44.638181 Setting prompt string to ['lava-test: # ']
310 00:01:44.639793 end: 2.3 connect-device (duration 00:00:00) [common]
311 00:01:44.640474 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 00:01:44.641074 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 00:01:44.641661 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 00:01:44.642870 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 00:01:44.679920 >> OK - accepted request
316 00:01:44.681951 Returned 0 in 0 seconds
317 00:01:44.783177 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 00:01:44.784989 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 00:01:44.785601 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 00:01:44.786165 Setting prompt string to ['Hit any key to stop autoboot']
322 00:01:44.786665 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 00:01:44.788392 Trying 192.168.56.21...
324 00:01:44.788917 Connected to conserv1.
325 00:01:44.789371 Escape character is '^]'.
326 00:01:44.789834
327 00:01:44.790289 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 00:01:44.790754
329 00:01:56.359283 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 00:01:56.360629 bl2_stage_init 0x01
331 00:01:56.361820 bl2_stage_init 0x81
332 00:01:56.364927 hw id: 0x0000 - pwm id 0x01
333 00:01:56.366153 bl2_stage_init 0xc1
334 00:01:56.367124 bl2_stage_init 0x02
335 00:01:56.367957
336 00:01:56.370549 L0:00000000
337 00:01:56.371399 L1:20000703
338 00:01:56.372296 L2:00008067
339 00:01:56.373064 L3:14000000
340 00:01:56.376094 B2:00402000
341 00:01:56.376743 B1:e0f83180
342 00:01:56.377204
343 00:01:56.377652 TE: 58124
344 00:01:56.378096
345 00:01:56.381261 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 00:01:56.381788
347 00:01:56.382233 Board ID = 1
348 00:01:56.387129 Set A53 clk to 24M
349 00:01:56.388155 Set A73 clk to 24M
350 00:01:56.388788 Set clk81 to 24M
351 00:01:56.393224 A53 clk: 1200 MHz
352 00:01:56.393643 A73 clk: 1200 MHz
353 00:01:56.393858 CLK81: 166.6M
354 00:01:56.394065 smccc: 00012a92
355 00:01:56.398349 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 00:01:56.403753 board id: 1
357 00:01:56.409757 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 00:01:56.420199 fw parse done
359 00:01:56.426195 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 00:01:56.468833 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 00:01:56.480245 PIEI prepare done
362 00:01:56.480991 fastboot data load
363 00:01:56.481467 fastboot data verify
364 00:01:56.485549 verify result: 266
365 00:01:56.490967 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 00:01:56.491388 LPDDR4 probe
367 00:01:56.491629 ddr clk to 1584MHz
368 00:01:56.499015 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 00:01:56.536381
370 00:01:56.536893 dmc_version 0001
371 00:01:56.543096 Check phy result
372 00:01:56.548644 INFO : End of CA training
373 00:01:56.548967 INFO : End of initialization
374 00:01:56.554254 INFO : Training has run successfully!
375 00:01:56.554554 Check phy result
376 00:01:56.559894 INFO : End of initialization
377 00:01:56.560301 INFO : End of read enable training
378 00:01:56.565642 INFO : End of fine write leveling
379 00:01:56.571377 INFO : End of Write leveling coarse delay
380 00:01:56.572018 INFO : Training has run successfully!
381 00:01:56.572449 Check phy result
382 00:01:56.576767 INFO : End of initialization
383 00:01:56.577402 INFO : End of read dq deskew training
384 00:01:56.582384 INFO : End of MPR read delay center optimization
385 00:01:56.587909 INFO : End of write delay center optimization
386 00:01:56.593585 INFO : End of read delay center optimization
387 00:01:56.594307 INFO : End of max read latency training
388 00:01:56.599215 INFO : Training has run successfully!
389 00:01:56.599869 1D training succeed
390 00:01:56.608401 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 00:01:56.656019 Check phy result
392 00:01:56.656633 INFO : End of initialization
393 00:01:56.678566 INFO : End of 2D read delay Voltage center optimization
394 00:01:56.698865 INFO : End of 2D read delay Voltage center optimization
395 00:01:56.750804 INFO : End of 2D write delay Voltage center optimization
396 00:01:56.804602 INFO : End of 2D write delay Voltage center optimization
397 00:01:56.805213 INFO : Training has run successfully!
398 00:01:56.805672
399 00:01:56.806124 channel==0
400 00:01:56.810319 RxClkDly_Margin_A0==88 ps 9
401 00:01:56.810884 TxDqDly_Margin_A0==98 ps 10
402 00:01:56.815949 RxClkDly_Margin_A1==88 ps 9
403 00:01:56.816603 TxDqDly_Margin_A1==88 ps 9
404 00:01:56.821488 TrainedVREFDQ_A0==74
405 00:01:56.822078 TrainedVREFDQ_A1==74
406 00:01:56.822546 VrefDac_Margin_A0==25
407 00:01:56.827155 DeviceVref_Margin_A0==40
408 00:01:56.827719 VrefDac_Margin_A1==24
409 00:01:56.828218 DeviceVref_Margin_A1==40
410 00:01:56.828671
411 00:01:56.832805
412 00:01:56.833371 channel==1
413 00:01:56.833835 RxClkDly_Margin_A0==98 ps 10
414 00:01:56.838170 TxDqDly_Margin_A0==88 ps 9
415 00:01:56.838731 RxClkDly_Margin_A1==98 ps 10
416 00:01:56.841630 TxDqDly_Margin_A1==88 ps 9
417 00:01:56.842201 TrainedVREFDQ_A0==77
418 00:01:56.847170 TrainedVREFDQ_A1==77
419 00:01:56.847738 VrefDac_Margin_A0==22
420 00:01:56.848307 DeviceVref_Margin_A0==37
421 00:01:56.852712 VrefDac_Margin_A1==22
422 00:01:56.853280 DeviceVref_Margin_A1==37
423 00:01:56.853863
424 00:01:56.860681 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 00:01:56.861081
426 00:01:56.886540 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 00:01:56.891918 2D training succeed
428 00:01:56.897970 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 00:01:56.903121 auto size-- 65535DDR cs0 size: 2048MB
430 00:01:56.903654 DDR cs1 size: 2048MB
431 00:01:56.904909 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 00:01:56.908719 cs0 DataBus test pass
433 00:01:56.909180 cs1 DataBus test pass
434 00:01:56.914231 cs0 AddrBus test pass
435 00:01:56.914658 cs1 AddrBus test pass
436 00:01:56.914887
437 00:01:56.915121 100bdlr_step_size ps== 420
438 00:01:56.919908 result report
439 00:01:56.921654 boot times 0Enable ddr reg access
440 00:01:56.928467 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 00:01:56.941983 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 00:01:57.515643 0.0;M3 CHK:0;cm4_sp_mode 0
443 00:01:57.516342 MVN_1=0x00000000
444 00:01:57.521031 MVN_2=0x00000000
445 00:01:57.526787 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 00:01:57.527300 OPS=0x10
447 00:01:57.527751 ring efuse init
448 00:01:57.528235 chipver efuse init
449 00:01:57.532415 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 00:01:57.538064 [0.018961 Inits done]
451 00:01:57.538587 secure task start!
452 00:01:57.539005 high task start!
453 00:01:57.542542 low task start!
454 00:01:57.543000 run into bl31
455 00:01:57.549297 NOTICE: BL31: v1.3(release):4fc40b1
456 00:01:57.556228 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 00:01:57.556830 NOTICE: BL31: G12A normal boot!
458 00:01:57.582498 NOTICE: BL31: BL33 decompress pass
459 00:01:57.588086 ERROR: Error initializing runtime service opteed_fast
460 00:01:58.821080
461 00:01:58.821755
462 00:01:58.829524 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 00:01:58.830292
464 00:01:58.830833 Model: Libre Computer AML-A311D-CC Alta
465 00:01:59.038052 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 00:01:59.061239 DRAM: 2 GiB (effective 3.8 GiB)
467 00:01:59.204198 Core: 408 devices, 31 uclasses, devicetree: separate
468 00:01:59.210025 WDT: Not starting watchdog@f0d0
469 00:01:59.242408 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 00:01:59.254841 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 00:01:59.259806 ** Bad device specification mmc 0 **
472 00:01:59.270110 Card did not respond to voltage select! : -110
473 00:01:59.277937 ** Bad device specification mmc 0 **
474 00:01:59.278518 Couldn't find partition mmc 0
475 00:01:59.286121 Card did not respond to voltage select! : -110
476 00:01:59.291616 ** Bad device specification mmc 0 **
477 00:01:59.292256 Couldn't find partition mmc 0
478 00:01:59.296619 Error: could not access storage.
479 00:02:00.560331 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
480 00:02:00.560950 bl2_stage_init 0x81
481 00:02:00.565857 hw id: 0x0000 - pwm id 0x01
482 00:02:00.566381 bl2_stage_init 0xc1
483 00:02:00.566796 bl2_stage_init 0x02
484 00:02:00.567196
485 00:02:00.571370 L0:00000000
486 00:02:00.571900 L1:20000703
487 00:02:00.572359 L2:00008067
488 00:02:00.572760 L3:14000000
489 00:02:00.573151 B2:00402000
490 00:02:00.574243 B1:e0f83180
491 00:02:00.574688
492 00:02:00.575096 TE: 58150
493 00:02:00.575501
494 00:02:00.585320 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 00:02:00.585832
496 00:02:00.586241 Board ID = 1
497 00:02:00.586642 Set A53 clk to 24M
498 00:02:00.587035 Set A73 clk to 24M
499 00:02:00.590933 Set clk81 to 24M
500 00:02:00.591389 A53 clk: 1200 MHz
501 00:02:00.591786 A73 clk: 1200 MHz
502 00:02:00.596608 CLK81: 166.6M
503 00:02:00.597075 smccc: 00012aac
504 00:02:00.602204 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 00:02:00.602693 board id: 1
506 00:02:00.607806 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 00:02:00.621491 fw parse done
508 00:02:00.627433 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 00:02:00.669196 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 00:02:00.680988 PIEI prepare done
511 00:02:00.681568 fastboot data load
512 00:02:00.682009 fastboot data verify
513 00:02:00.686670 verify result: 266
514 00:02:00.692242 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 00:02:00.692813 LPDDR4 probe
516 00:02:00.693264 ddr clk to 1584MHz
517 00:02:00.699405 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 00:02:00.737210
519 00:02:00.737730 dmc_version 0001
520 00:02:00.743257 Check phy result
521 00:02:00.749983 INFO : End of CA training
522 00:02:00.750315 INFO : End of initialization
523 00:02:00.755716 INFO : Training has run successfully!
524 00:02:00.756082 Check phy result
525 00:02:00.761733 INFO : End of initialization
526 00:02:00.762158 INFO : End of read enable training
527 00:02:00.767255 INFO : End of fine write leveling
528 00:02:00.772586 INFO : End of Write leveling coarse delay
529 00:02:00.772997 INFO : Training has run successfully!
530 00:02:00.773318 Check phy result
531 00:02:00.778236 INFO : End of initialization
532 00:02:00.778669 INFO : End of read dq deskew training
533 00:02:00.784153 INFO : End of MPR read delay center optimization
534 00:02:00.789387 INFO : End of write delay center optimization
535 00:02:00.794997 INFO : End of read delay center optimization
536 00:02:00.795404 INFO : End of max read latency training
537 00:02:00.800601 INFO : Training has run successfully!
538 00:02:00.801012 1D training succeed
539 00:02:00.808885 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 00:02:00.856459 Check phy result
541 00:02:00.856955 INFO : End of initialization
542 00:02:00.878080 INFO : End of 2D read delay Voltage center optimization
543 00:02:00.899346 INFO : End of 2D read delay Voltage center optimization
544 00:02:00.950457 INFO : End of 2D write delay Voltage center optimization
545 00:02:01.000634 INFO : End of 2D write delay Voltage center optimization
546 00:02:01.006131 INFO : Training has run successfully!
547 00:02:01.006534
548 00:02:01.006781 channel==0
549 00:02:01.011782 RxClkDly_Margin_A0==88 ps 9
550 00:02:01.012219 TxDqDly_Margin_A0==98 ps 10
551 00:02:01.017417 RxClkDly_Margin_A1==88 ps 9
552 00:02:01.017843 TxDqDly_Margin_A1==98 ps 10
553 00:02:01.018093 TrainedVREFDQ_A0==74
554 00:02:01.022923 TrainedVREFDQ_A1==74
555 00:02:01.023349 VrefDac_Margin_A0==25
556 00:02:01.023598 DeviceVref_Margin_A0==40
557 00:02:01.028545 VrefDac_Margin_A1==23
558 00:02:01.028964 DeviceVref_Margin_A1==40
559 00:02:01.029207
560 00:02:01.029431
561 00:02:01.034174 channel==1
562 00:02:01.034580 RxClkDly_Margin_A0==98 ps 10
563 00:02:01.034803 TxDqDly_Margin_A0==98 ps 10
564 00:02:01.039968 RxClkDly_Margin_A1==98 ps 10
565 00:02:01.040420 TxDqDly_Margin_A1==88 ps 9
566 00:02:01.045429 TrainedVREFDQ_A0==77
567 00:02:01.046099 TrainedVREFDQ_A1==77
568 00:02:01.046626 VrefDac_Margin_A0==22
569 00:02:01.050984 DeviceVref_Margin_A0==37
570 00:02:01.051614 VrefDac_Margin_A1==22
571 00:02:01.056517 DeviceVref_Margin_A1==37
572 00:02:01.057049
573 00:02:01.057522 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 00:02:01.062140
575 00:02:01.090154 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
576 00:02:01.090801 2D training succeed
577 00:02:01.095742 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 00:02:01.101353 auto size-- 65535DDR cs0 size: 2048MB
579 00:02:01.102203 DDR cs1 size: 2048MB
580 00:02:01.106997 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 00:02:01.107548 cs0 DataBus test pass
582 00:02:01.112530 cs1 DataBus test pass
583 00:02:01.113114 cs0 AddrBus test pass
584 00:02:01.113577 cs1 AddrBus test pass
585 00:02:01.114032
586 00:02:01.118164 100bdlr_step_size ps== 420
587 00:02:01.118751 result report
588 00:02:01.124140 boot times 0Enable ddr reg access
589 00:02:01.129247 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 00:02:01.142743 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 00:02:01.716357 0.0;M3 CHK:0;cm4_sp_mode 0
592 00:02:01.717051 MVN_1=0x00000000
593 00:02:01.721786 MVN_2=0x00000000
594 00:02:01.727504 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 00:02:01.728097 OPS=0x10
596 00:02:01.728596 ring efuse init
597 00:02:01.729041 chipver efuse init
598 00:02:01.733175 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 00:02:01.738780 [0.018960 Inits done]
600 00:02:01.739374 secure task start!
601 00:02:01.739840 high task start!
602 00:02:01.743298 low task start!
603 00:02:01.743779 run into bl31
604 00:02:01.750015 NOTICE: BL31: v1.3(release):4fc40b1
605 00:02:01.757858 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 00:02:01.758421 NOTICE: BL31: G12A normal boot!
607 00:02:01.783255 NOTICE: BL31: BL33 decompress pass
608 00:02:01.788885 ERROR: Error initializing runtime service opteed_fast
609 00:02:03.022173
610 00:02:03.022853
611 00:02:03.030414 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 00:02:03.030927
613 00:02:03.031398 Model: Libre Computer AML-A311D-CC Alta
614 00:02:03.238949 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 00:02:03.262311 DRAM: 2 GiB (effective 3.8 GiB)
616 00:02:03.405296 Core: 408 devices, 31 uclasses, devicetree: separate
617 00:02:03.411075 WDT: Not starting watchdog@f0d0
618 00:02:03.443422 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 00:02:03.455741 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 00:02:03.460791 ** Bad device specification mmc 0 **
621 00:02:03.471066 Card did not respond to voltage select! : -110
622 00:02:03.478834 ** Bad device specification mmc 0 **
623 00:02:03.479371 Couldn't find partition mmc 0
624 00:02:03.487064 Card did not respond to voltage select! : -110
625 00:02:03.492494 ** Bad device specification mmc 0 **
626 00:02:03.492986 Couldn't find partition mmc 0
627 00:02:03.497581 Error: could not access storage.
628 00:02:03.841266 Net: eth0: ethernet@ff3f0000
629 00:02:03.841909 starting USB...
630 00:02:04.092926 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 00:02:04.093532 Starting the controller
632 00:02:04.099881 USB XHCI 1.10
633 00:02:05.811234 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
634 00:02:05.811874 bl2_stage_init 0x01
635 00:02:05.812391 bl2_stage_init 0x81
636 00:02:05.816631 hw id: 0x0000 - pwm id 0x01
637 00:02:05.817397 bl2_stage_init 0xc1
638 00:02:05.817875 bl2_stage_init 0x02
639 00:02:05.818312
640 00:02:05.822139 L0:00000000
641 00:02:05.822926 L1:20000703
642 00:02:05.823390 L2:00008067
643 00:02:05.823803 L3:14000000
644 00:02:05.827700 B2:00402000
645 00:02:05.828198 B1:e0f83180
646 00:02:05.828612
647 00:02:05.829019 TE: 58159
648 00:02:05.829424
649 00:02:05.833414 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 00:02:05.833861
651 00:02:05.834271 Board ID = 1
652 00:02:05.838859 Set A53 clk to 24M
653 00:02:05.839303 Set A73 clk to 24M
654 00:02:05.839712 Set clk81 to 24M
655 00:02:05.844495 A53 clk: 1200 MHz
656 00:02:05.844936 A73 clk: 1200 MHz
657 00:02:05.845334 CLK81: 166.6M
658 00:02:05.845730 smccc: 00012ab5
659 00:02:05.850043 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 00:02:05.855704 board id: 1
661 00:02:05.861621 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 00:02:05.872371 fw parse done
663 00:02:05.878270 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 00:02:05.920742 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 00:02:05.931606 PIEI prepare done
666 00:02:05.932130 fastboot data load
667 00:02:05.932555 fastboot data verify
668 00:02:05.937205 verify result: 266
669 00:02:05.942798 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 00:02:05.943251 LPDDR4 probe
671 00:02:05.943658 ddr clk to 1584MHz
672 00:02:05.950794 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 00:02:05.988088
674 00:02:05.988603 dmc_version 0001
675 00:02:05.994724 Check phy result
676 00:02:06.000592 INFO : End of CA training
677 00:02:06.001056 INFO : End of initialization
678 00:02:06.006206 INFO : Training has run successfully!
679 00:02:06.006685 Check phy result
680 00:02:06.011755 INFO : End of initialization
681 00:02:06.012244 INFO : End of read enable training
682 00:02:06.017405 INFO : End of fine write leveling
683 00:02:06.023005 INFO : End of Write leveling coarse delay
684 00:02:06.023532 INFO : Training has run successfully!
685 00:02:06.023956 Check phy result
686 00:02:06.028608 INFO : End of initialization
687 00:02:06.029337 INFO : End of read dq deskew training
688 00:02:06.034205 INFO : End of MPR read delay center optimization
689 00:02:06.039750 INFO : End of write delay center optimization
690 00:02:06.045358 INFO : End of read delay center optimization
691 00:02:06.045798 INFO : End of max read latency training
692 00:02:06.050945 INFO : Training has run successfully!
693 00:02:06.051383 1D training succeed
694 00:02:06.060293 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 00:02:06.107861 Check phy result
696 00:02:06.108502 INFO : End of initialization
697 00:02:06.130445 INFO : End of 2D read delay Voltage center optimization
698 00:02:06.150660 INFO : End of 2D read delay Voltage center optimization
699 00:02:06.202694 INFO : End of 2D write delay Voltage center optimization
700 00:02:06.252151 INFO : End of 2D write delay Voltage center optimization
701 00:02:06.257567 INFO : Training has run successfully!
702 00:02:06.258086
703 00:02:06.258521 channel==0
704 00:02:06.263290 RxClkDly_Margin_A0==88 ps 9
705 00:02:06.263828 TxDqDly_Margin_A0==98 ps 10
706 00:02:06.268765 RxClkDly_Margin_A1==78 ps 8
707 00:02:06.269285 TxDqDly_Margin_A1==88 ps 9
708 00:02:06.269695 TrainedVREFDQ_A0==74
709 00:02:06.274378 TrainedVREFDQ_A1==74
710 00:02:06.274869 VrefDac_Margin_A0==24
711 00:02:06.275265 DeviceVref_Margin_A0==40
712 00:02:06.280003 VrefDac_Margin_A1==26
713 00:02:06.280489 DeviceVref_Margin_A1==40
714 00:02:06.280891
715 00:02:06.281294
716 00:02:06.281687 channel==1
717 00:02:06.285544 RxClkDly_Margin_A0==88 ps 9
718 00:02:06.285985 TxDqDly_Margin_A0==88 ps 9
719 00:02:06.291254 RxClkDly_Margin_A1==98 ps 10
720 00:02:06.291773 TxDqDly_Margin_A1==88 ps 9
721 00:02:06.296780 TrainedVREFDQ_A0==77
722 00:02:06.297269 TrainedVREFDQ_A1==77
723 00:02:06.297670 VrefDac_Margin_A0==22
724 00:02:06.302431 DeviceVref_Margin_A0==37
725 00:02:06.302921 VrefDac_Margin_A1==22
726 00:02:06.308097 DeviceVref_Margin_A1==37
727 00:02:06.308609
728 00:02:06.309021 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 00:02:06.309421
730 00:02:06.341618 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
731 00:02:06.342213 2D training succeed
732 00:02:06.347323 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 00:02:06.352814 auto size-- 65535DDR cs0 size: 2048MB
734 00:02:06.353327 DDR cs1 size: 2048MB
735 00:02:06.358415 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 00:02:06.358915 cs0 DataBus test pass
737 00:02:06.364078 cs1 DataBus test pass
738 00:02:06.364570 cs0 AddrBus test pass
739 00:02:06.364973 cs1 AddrBus test pass
740 00:02:06.365361
741 00:02:06.369614 100bdlr_step_size ps== 420
742 00:02:06.370117 result report
743 00:02:06.375343 boot times 0Enable ddr reg access
744 00:02:06.380407 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 00:02:06.393887 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 00:02:06.967582 0.0;M3 CHK:0;cm4_sp_mode 0
747 00:02:06.968276 MVN_1=0x00000000
748 00:02:06.973160 MVN_2=0x00000000
749 00:02:06.978802 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 00:02:06.979170 OPS=0x10
751 00:02:06.979400 ring efuse init
752 00:02:06.979636 chipver efuse init
753 00:02:06.984453 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 00:02:06.990018 [0.018960 Inits done]
755 00:02:06.990541 secure task start!
756 00:02:06.990962 high task start!
757 00:02:06.994576 low task start!
758 00:02:06.995055 run into bl31
759 00:02:07.001364 NOTICE: BL31: v1.3(release):4fc40b1
760 00:02:07.009107 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 00:02:07.009656 NOTICE: BL31: G12A normal boot!
762 00:02:07.034489 NOTICE: BL31: BL33 decompress pass
763 00:02:07.040211 ERROR: Error initializing runtime service opteed_fast
764 00:02:08.273053
765 00:02:08.273688
766 00:02:08.281409 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 00:02:08.281890
768 00:02:08.282310 Model: Libre Computer AML-A311D-CC Alta
769 00:02:08.489835 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 00:02:08.513197 DRAM: 2 GiB (effective 3.8 GiB)
771 00:02:08.656281 Core: 408 devices, 31 uclasses, devicetree: separate
772 00:02:08.662057 WDT: Not starting watchdog@f0d0
773 00:02:08.694388 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 00:02:08.706892 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 00:02:08.711769 ** Bad device specification mmc 0 **
776 00:02:08.722179 Card did not respond to voltage select! : -110
777 00:02:08.729782 ** Bad device specification mmc 0 **
778 00:02:08.730319 Couldn't find partition mmc 0
779 00:02:08.738137 Card did not respond to voltage select! : -110
780 00:02:08.743633 ** Bad device specification mmc 0 **
781 00:02:08.744178 Couldn't find partition mmc 0
782 00:02:08.748637 Error: could not access storage.
783 00:02:09.092269 Net: eth0: ethernet@ff3f0000
784 00:02:09.092914 starting USB...
785 00:02:09.344064 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 00:02:09.344695 Starting the controller
787 00:02:09.350925 USB XHCI 1.10
788 00:02:11.509734 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 00:02:11.510373 bl2_stage_init 0x01
790 00:02:11.510821 bl2_stage_init 0x81
791 00:02:11.515259 hw id: 0x0000 - pwm id 0x01
792 00:02:11.515763 bl2_stage_init 0xc1
793 00:02:11.516247 bl2_stage_init 0x02
794 00:02:11.516670
795 00:02:11.520682 L0:00000000
796 00:02:11.521140 L1:20000703
797 00:02:11.521550 L2:00008067
798 00:02:11.521953 L3:14000000
799 00:02:11.523668 B2:00402000
800 00:02:11.524167 B1:e0f83180
801 00:02:11.524581
802 00:02:11.524986 TE: 58167
803 00:02:11.525389
804 00:02:11.534858 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 00:02:11.535328
806 00:02:11.535736 Board ID = 1
807 00:02:11.536177 Set A53 clk to 24M
808 00:02:11.536578 Set A73 clk to 24M
809 00:02:11.540434 Set clk81 to 24M
810 00:02:11.540918 A53 clk: 1200 MHz
811 00:02:11.541322 A73 clk: 1200 MHz
812 00:02:11.543947 CLK81: 166.6M
813 00:02:11.544443 smccc: 00012abe
814 00:02:11.549489 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 00:02:11.555119 board id: 1
816 00:02:11.560337 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 00:02:11.570772 fw parse done
818 00:02:11.576746 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 00:02:11.619385 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 00:02:11.630356 PIEI prepare done
821 00:02:11.630833 fastboot data load
822 00:02:11.631250 fastboot data verify
823 00:02:11.635919 verify result: 266
824 00:02:11.641546 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 00:02:11.642009 LPDDR4 probe
826 00:02:11.642422 ddr clk to 1584MHz
827 00:02:11.649544 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 00:02:11.686843
829 00:02:11.687333 dmc_version 0001
830 00:02:11.693527 Check phy result
831 00:02:11.699362 INFO : End of CA training
832 00:02:11.699808 INFO : End of initialization
833 00:02:11.704969 INFO : Training has run successfully!
834 00:02:11.705412 Check phy result
835 00:02:11.710593 INFO : End of initialization
836 00:02:11.711100 INFO : End of read enable training
837 00:02:11.716152 INFO : End of fine write leveling
838 00:02:11.721781 INFO : End of Write leveling coarse delay
839 00:02:11.722239 INFO : Training has run successfully!
840 00:02:11.722654 Check phy result
841 00:02:11.727386 INFO : End of initialization
842 00:02:11.727827 INFO : End of read dq deskew training
843 00:02:11.732953 INFO : End of MPR read delay center optimization
844 00:02:11.738587 INFO : End of write delay center optimization
845 00:02:11.744169 INFO : End of read delay center optimization
846 00:02:11.744628 INFO : End of max read latency training
847 00:02:11.749773 INFO : Training has run successfully!
848 00:02:11.750222 1D training succeed
849 00:02:11.759025 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 00:02:11.806551 Check phy result
851 00:02:11.807072 INFO : End of initialization
852 00:02:11.828324 INFO : End of 2D read delay Voltage center optimization
853 00:02:11.848557 INFO : End of 2D read delay Voltage center optimization
854 00:02:11.900725 INFO : End of 2D write delay Voltage center optimization
855 00:02:11.950035 INFO : End of 2D write delay Voltage center optimization
856 00:02:11.955547 INFO : Training has run successfully!
857 00:02:11.956041
858 00:02:11.956455 channel==0
859 00:02:11.961173 RxClkDly_Margin_A0==88 ps 9
860 00:02:11.961634 TxDqDly_Margin_A0==98 ps 10
861 00:02:11.964422 RxClkDly_Margin_A1==88 ps 9
862 00:02:11.964858 TxDqDly_Margin_A1==98 ps 10
863 00:02:11.969934 TrainedVREFDQ_A0==74
864 00:02:11.970382 TrainedVREFDQ_A1==75
865 00:02:11.975710 VrefDac_Margin_A0==25
866 00:02:11.976267 DeviceVref_Margin_A0==40
867 00:02:11.976688 VrefDac_Margin_A1==25
868 00:02:11.981205 DeviceVref_Margin_A1==39
869 00:02:11.981702
870 00:02:11.982096
871 00:02:11.982477 channel==1
872 00:02:11.982859 RxClkDly_Margin_A0==98 ps 10
873 00:02:11.984639 TxDqDly_Margin_A0==98 ps 10
874 00:02:11.990190 RxClkDly_Margin_A1==88 ps 9
875 00:02:11.990617 TxDqDly_Margin_A1==88 ps 9
876 00:02:11.991009 TrainedVREFDQ_A0==77
877 00:02:11.995771 TrainedVREFDQ_A1==77
878 00:02:11.996228 VrefDac_Margin_A0==22
879 00:02:12.001400 DeviceVref_Margin_A0==37
880 00:02:12.001822 VrefDac_Margin_A1==24
881 00:02:12.002211 DeviceVref_Margin_A1==37
882 00:02:12.002593
883 00:02:12.006961 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 00:02:12.007383
885 00:02:12.040546 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
886 00:02:12.041053 2D training succeed
887 00:02:12.046173 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 00:02:12.051732 auto size-- 65535DDR cs0 size: 2048MB
889 00:02:12.052200 DDR cs1 size: 2048MB
890 00:02:12.057344 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 00:02:12.057775 cs0 DataBus test pass
892 00:02:12.058166 cs1 DataBus test pass
893 00:02:12.063013 cs0 AddrBus test pass
894 00:02:12.063438 cs1 AddrBus test pass
895 00:02:12.063824
896 00:02:12.068551 100bdlr_step_size ps== 420
897 00:02:12.068991 result report
898 00:02:12.069373 boot times 0Enable ddr reg access
899 00:02:12.078446 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 00:02:12.092034 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 00:02:12.665037 0.0;M3 CHK:0;cm4_sp_mode 0
902 00:02:12.665661 MVN_1=0x00000000
903 00:02:12.670418 MVN_2=0x00000000
904 00:02:12.676205 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 00:02:12.676661 OPS=0x10
906 00:02:12.677069 ring efuse init
907 00:02:12.677466 chipver efuse init
908 00:02:12.681782 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 00:02:12.687377 [0.018960 Inits done]
910 00:02:12.687820 secure task start!
911 00:02:12.688276 high task start!
912 00:02:12.691970 low task start!
913 00:02:12.692450 run into bl31
914 00:02:12.698584 NOTICE: BL31: v1.3(release):4fc40b1
915 00:02:12.706389 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 00:02:12.706861 NOTICE: BL31: G12A normal boot!
917 00:02:12.731845 NOTICE: BL31: BL33 decompress pass
918 00:02:12.737506 ERROR: Error initializing runtime service opteed_fast
919 00:02:13.970455
920 00:02:13.970883
921 00:02:13.977947 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 00:02:13.978282
923 00:02:13.978504 Model: Libre Computer AML-A311D-CC Alta
924 00:02:14.187382 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 00:02:14.210692 DRAM: 2 GiB (effective 3.8 GiB)
926 00:02:14.353681 Core: 408 devices, 31 uclasses, devicetree: separate
927 00:02:14.359564 WDT: Not starting watchdog@f0d0
928 00:02:14.391790 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 00:02:14.404245 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 00:02:14.409403 ** Bad device specification mmc 0 **
931 00:02:14.419585 Card did not respond to voltage select! : -110
932 00:02:14.427259 ** Bad device specification mmc 0 **
933 00:02:14.427711 Couldn't find partition mmc 0
934 00:02:14.435574 Card did not respond to voltage select! : -110
935 00:02:14.441064 ** Bad device specification mmc 0 **
936 00:02:14.441386 Couldn't find partition mmc 0
937 00:02:14.446134 Error: could not access storage.
938 00:02:14.790172 Net: eth0: ethernet@ff3f0000
939 00:02:14.790607 starting USB...
940 00:02:15.041461 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 00:02:15.042082 Starting the controller
942 00:02:15.048419 USB XHCI 1.10
943 00:02:16.909401 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
944 00:02:16.910078 bl2_stage_init 0x01
945 00:02:16.910556 bl2_stage_init 0x81
946 00:02:16.914988 hw id: 0x0000 - pwm id 0x01
947 00:02:16.915526 bl2_stage_init 0xc1
948 00:02:16.916034 bl2_stage_init 0x02
949 00:02:16.916498
950 00:02:16.920613 L0:00000000
951 00:02:16.921138 L1:20000703
952 00:02:16.921599 L2:00008067
953 00:02:16.922048 L3:14000000
954 00:02:16.926205 B2:00402000
955 00:02:16.926729 B1:e0f83180
956 00:02:16.927183
957 00:02:16.927636 TE: 58124
958 00:02:16.928124
959 00:02:16.931800 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
960 00:02:16.932356
961 00:02:16.932817 Board ID = 1
962 00:02:16.937399 Set A53 clk to 24M
963 00:02:16.937932 Set A73 clk to 24M
964 00:02:16.938391 Set clk81 to 24M
965 00:02:16.942984 A53 clk: 1200 MHz
966 00:02:16.943509 A73 clk: 1200 MHz
967 00:02:16.943963 CLK81: 166.6M
968 00:02:16.944449 smccc: 00012a92
969 00:02:16.948622 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
970 00:02:16.954189 board id: 1
971 00:02:16.960068 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
972 00:02:16.970824 fw parse done
973 00:02:16.976735 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
974 00:02:17.019282 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
975 00:02:17.030228 PIEI prepare done
976 00:02:17.030758 fastboot data load
977 00:02:17.031197 fastboot data verify
978 00:02:17.035946 verify result: 266
979 00:02:17.041464 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
980 00:02:17.041983 LPDDR4 probe
981 00:02:17.042415 ddr clk to 1584MHz
982 00:02:17.049491 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
983 00:02:17.086802
984 00:02:17.087369 dmc_version 0001
985 00:02:17.093416 Check phy result
986 00:02:17.099287 INFO : End of CA training
987 00:02:17.099798 INFO : End of initialization
988 00:02:17.104919 INFO : Training has run successfully!
989 00:02:17.105443 Check phy result
990 00:02:17.110542 INFO : End of initialization
991 00:02:17.111092 INFO : End of read enable training
992 00:02:17.116304 INFO : End of fine write leveling
993 00:02:17.121834 INFO : End of Write leveling coarse delay
994 00:02:17.122370 INFO : Training has run successfully!
995 00:02:17.122825 Check phy result
996 00:02:17.127431 INFO : End of initialization
997 00:02:17.128017 INFO : End of read dq deskew training
998 00:02:17.133037 INFO : End of MPR read delay center optimization
999 00:02:17.138589 INFO : End of write delay center optimization
1000 00:02:17.144298 INFO : End of read delay center optimization
1001 00:02:17.144901 INFO : End of max read latency training
1002 00:02:17.149809 INFO : Training has run successfully!
1003 00:02:17.150346 1D training succeed
1004 00:02:17.159130 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 00:02:17.206713 Check phy result
1006 00:02:17.207377 INFO : End of initialization
1007 00:02:17.228375 INFO : End of 2D read delay Voltage center optimization
1008 00:02:17.248307 INFO : End of 2D read delay Voltage center optimization
1009 00:02:17.300248 INFO : End of 2D write delay Voltage center optimization
1010 00:02:17.349443 INFO : End of 2D write delay Voltage center optimization
1011 00:02:17.355141 INFO : Training has run successfully!
1012 00:02:17.355701
1013 00:02:17.356234 channel==0
1014 00:02:17.360628 RxClkDly_Margin_A0==88 ps 9
1015 00:02:17.361212 TxDqDly_Margin_A0==98 ps 10
1016 00:02:17.366199 RxClkDly_Margin_A1==88 ps 9
1017 00:02:17.366733 TxDqDly_Margin_A1==98 ps 10
1018 00:02:17.367193 TrainedVREFDQ_A0==74
1019 00:02:17.371804 TrainedVREFDQ_A1==74
1020 00:02:17.372383 VrefDac_Margin_A0==25
1021 00:02:17.372845 DeviceVref_Margin_A0==40
1022 00:02:17.377614 VrefDac_Margin_A1==25
1023 00:02:17.378217 DeviceVref_Margin_A1==40
1024 00:02:17.378692
1025 00:02:17.379140
1026 00:02:17.383125 channel==1
1027 00:02:17.383667 RxClkDly_Margin_A0==98 ps 10
1028 00:02:17.384161 TxDqDly_Margin_A0==98 ps 10
1029 00:02:17.388639 RxClkDly_Margin_A1==88 ps 9
1030 00:02:17.389212 TxDqDly_Margin_A1==88 ps 9
1031 00:02:17.394203 TrainedVREFDQ_A0==77
1032 00:02:17.394747 TrainedVREFDQ_A1==77
1033 00:02:17.395205 VrefDac_Margin_A0==22
1034 00:02:17.399890 DeviceVref_Margin_A0==37
1035 00:02:17.400493 VrefDac_Margin_A1==24
1036 00:02:17.405378 DeviceVref_Margin_A1==37
1037 00:02:17.405960
1038 00:02:17.406423 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1039 00:02:17.406870
1040 00:02:17.438960 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1041 00:02:17.439630 2D training succeed
1042 00:02:17.444508 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1043 00:02:17.450101 auto size-- 65535DDR cs0 size: 2048MB
1044 00:02:17.450684 DDR cs1 size: 2048MB
1045 00:02:17.455723 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1046 00:02:17.456337 cs0 DataBus test pass
1047 00:02:17.461293 cs1 DataBus test pass
1048 00:02:17.461852 cs0 AddrBus test pass
1049 00:02:17.462304 cs1 AddrBus test pass
1050 00:02:17.462745
1051 00:02:17.466999 100bdlr_step_size ps== 420
1052 00:02:17.467548 result report
1053 00:02:17.472464 boot times 0Enable ddr reg access
1054 00:02:17.476985 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1055 00:02:17.491279 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1056 00:02:18.063238 0.0;M3 CHK:0;cm4_sp_mode 0
1057 00:02:18.063911 MVN_1=0x00000000
1058 00:02:18.068755 MVN_2=0x00000000
1059 00:02:18.074516 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1060 00:02:18.075055 OPS=0x10
1061 00:02:18.075553 ring efuse init
1062 00:02:18.076078 chipver efuse init
1063 00:02:18.082673 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1064 00:02:18.083241 [0.018961 Inits done]
1065 00:02:18.090298 secure task start!
1066 00:02:18.090848 high task start!
1067 00:02:18.091299 low task start!
1068 00:02:18.091751 run into bl31
1069 00:02:18.096947 NOTICE: BL31: v1.3(release):4fc40b1
1070 00:02:18.104776 NOTICE: BL31: Built : 15:58:17, May 22 2019
1071 00:02:18.105344 NOTICE: BL31: G12A normal boot!
1072 00:02:18.130761 NOTICE: BL31: BL33 decompress pass
1073 00:02:18.135748 ERROR: Error initializing runtime service opteed_fast
1074 00:02:19.369144
1075 00:02:19.369590
1076 00:02:19.377554 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1077 00:02:19.377967
1078 00:02:19.378206 Model: Libre Computer AML-A311D-CC Alta
1079 00:02:19.584993 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1080 00:02:19.609428 DRAM: 2 GiB (effective 3.8 GiB)
1081 00:02:19.752366 Core: 408 devices, 31 uclasses, devicetree: separate
1082 00:02:19.758285 WDT: Not starting watchdog@f0d0
1083 00:02:19.790542 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1084 00:02:19.802950 Loading Environment from FAT... Card did not respond to voltage select! : -110
1085 00:02:19.808006 ** Bad device specification mmc 0 **
1086 00:02:19.818270 Card did not respond to voltage select! : -110
1087 00:02:19.825927 ** Bad device specification mmc 0 **
1088 00:02:19.826491 Couldn't find partition mmc 0
1089 00:02:19.834257 Card did not respond to voltage select! : -110
1090 00:02:19.839730 ** Bad device specification mmc 0 **
1091 00:02:19.840248 Couldn't find partition mmc 0
1092 00:02:19.844834 Error: could not access storage.
1093 00:02:20.186540 Net: eth0: ethernet@ff3f0000
1094 00:02:20.186955 starting USB...
1095 00:02:20.439079 Bus usb@ff500000: Register 3000140 NbrPorts 3
1096 00:02:20.439483 Starting the controller
1097 00:02:20.446017 USB XHCI 1.10
1098 00:02:22.002289 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1099 00:02:22.010669 scanning usb for storage devices... 0 Storage Device(s) found
1101 00:02:22.061814 Hit any key to stop autoboot: 1
1102 00:02:22.062550 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1103 00:02:22.062927 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1104 00:02:22.063199 Setting prompt string to ['=>']
1105 00:02:22.063465 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1106 00:02:22.068149 0
1107 00:02:22.068779 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1108 00:02:22.069069 Sending with 10 millisecond of delay
1110 00:02:23.203346 => setenv autoload no
1111 00:02:23.214090 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1112 00:02:23.216772 setenv autoload no
1113 00:02:23.217296 Sending with 10 millisecond of delay
1115 00:02:25.014091 => setenv initrd_high 0xffffffff
1116 00:02:25.024944 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1117 00:02:25.025945 setenv initrd_high 0xffffffff
1118 00:02:25.026712 Sending with 10 millisecond of delay
1120 00:02:26.644420 => setenv fdt_high 0xffffffff
1121 00:02:26.655304 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1122 00:02:26.656393 setenv fdt_high 0xffffffff
1123 00:02:26.657200 Sending with 10 millisecond of delay
1125 00:02:26.949380 => dhcp
1126 00:02:26.960265 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1127 00:02:26.961302 dhcp
1128 00:02:26.961780 Speed: 1000, full duplex
1129 00:02:26.962234 BOOTP broadcast 1
1130 00:02:26.969066 DHCP client bound to address 192.168.6.27 (9 ms)
1131 00:02:26.969970 Sending with 10 millisecond of delay
1133 00:02:28.648314 => setenv serverip 192.168.6.2
1134 00:02:28.659183 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1135 00:02:28.660240 setenv serverip 192.168.6.2
1136 00:02:28.661004 Sending with 10 millisecond of delay
1138 00:02:32.390966 => tftpboot 0x01080000 949255/tftp-deploy-7p3crbb3/kernel/uImage
1139 00:02:32.401875 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1140 00:02:32.402877 tftpboot 0x01080000 949255/tftp-deploy-7p3crbb3/kernel/uImage
1141 00:02:32.403408 Speed: 1000, full duplex
1142 00:02:32.403897 Using ethernet@ff3f0000 device
1143 00:02:32.404900 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1144 00:02:32.410544 Filename '949255/tftp-deploy-7p3crbb3/kernel/uImage'.
1145 00:02:32.414277 Load address: 0x1080000
1146 00:02:35.319573 Loading: *################################################## 43.6 MiB
1147 00:02:35.320305 15 MiB/s
1148 00:02:35.321073 done
1149 00:02:35.323755 Bytes transferred = 45713984 (2b98a40 hex)
1150 00:02:35.324635 Sending with 10 millisecond of delay
1152 00:02:40.014901 => tftpboot 0x08000000 949255/tftp-deploy-7p3crbb3/ramdisk/ramdisk.cpio.gz.uboot
1153 00:02:40.025528 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1154 00:02:40.026173 tftpboot 0x08000000 949255/tftp-deploy-7p3crbb3/ramdisk/ramdisk.cpio.gz.uboot
1155 00:02:40.026472 Speed: 1000, full duplex
1156 00:02:40.026752 Using ethernet@ff3f0000 device
1157 00:02:40.028200 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1158 00:02:40.036888 Filename '949255/tftp-deploy-7p3crbb3/ramdisk/ramdisk.cpio.gz.uboot'.
1159 00:02:40.037565 Load address: 0x8000000
1160 00:02:46.777044 Loading: *###################T ############################## UDP wrong checksum 00000005 0000e78d
1161 00:02:51.778325 T UDP wrong checksum 00000005 0000e78d
1162 00:02:57.523758 T UDP wrong checksum 000000ff 0000774b
1163 00:02:57.600117 UDP wrong checksum 000000ff 0000033e
1164 00:03:00.127676 UDP wrong checksum 000000ff 00001909
1165 00:03:00.167337 UDP wrong checksum 000000ff 0000a8fb
1166 00:03:01.780713 T UDP wrong checksum 00000005 0000e78d
1167 00:03:21.784123 T T T T UDP wrong checksum 00000005 0000e78d
1168 00:03:28.019921 T UDP wrong checksum 000000ff 000054ea
1169 00:03:28.059538 UDP wrong checksum 000000ff 0000eddc
1170 00:03:36.789468 T
1171 00:03:36.790142 Retry count exceeded; starting again
1173 00:03:36.791668 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1176 00:03:36.793718 end: 2.4 uboot-commands (duration 00:01:52) [common]
1178 00:03:36.795231 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1180 00:03:36.796429 end: 2 uboot-action (duration 00:01:52) [common]
1182 00:03:36.798114 Cleaning after the job
1183 00:03:36.798729 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/ramdisk
1184 00:03:36.800145 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/kernel
1185 00:03:36.830123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/dtb
1186 00:03:36.831469 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/nfsrootfs
1187 00:03:36.888645 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949255/tftp-deploy-7p3crbb3/modules
1188 00:03:36.895598 start: 4.1 power-off (timeout 00:00:30) [common]
1189 00:03:36.896249 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1190 00:03:36.931552 >> OK - accepted request
1191 00:03:36.933630 Returned 0 in 0 seconds
1192 00:03:37.034420 end: 4.1 power-off (duration 00:00:00) [common]
1194 00:03:37.035404 start: 4.2 read-feedback (timeout 00:10:00) [common]
1195 00:03:37.036071 Listened to connection for namespace 'common' for up to 1s
1196 00:03:38.036277 Finalising connection for namespace 'common'
1197 00:03:38.037076 Disconnecting from shell: Finalise
1198 00:03:38.037672 =>
1199 00:03:38.138795 end: 4.2 read-feedback (duration 00:00:01) [common]
1200 00:03:38.139563 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949255
1201 00:03:41.834351 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949255
1202 00:03:41.834970 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.