Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:44:19.506908 lava-dispatcher, installed at version: 2024.01
2 23:44:19.507672 start: 0 validate
3 23:44:19.508138 Start time: 2024-11-06 23:44:19.508108+00:00 (UTC)
4 23:44:19.508698 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:44:19.509250 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:44:19.553441 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:44:19.554044 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:44:19.593919 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:44:19.594737 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 23:44:19.630017 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:44:19.630624 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:44:19.669896 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 23:44:19.674992 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-102-gf43b156921299%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 23:44:19.715478 validate duration: 0.21
16 23:44:19.716425 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:44:19.716786 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:44:19.717124 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:44:19.717725 Not decompressing ramdisk as can be used compressed.
20 23:44:19.718203 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 23:44:19.718526 saving as /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/ramdisk/initrd.cpio.gz
22 23:44:19.718843 total size: 5628140 (5 MB)
23 23:44:19.759157 progress 0 % (0 MB)
24 23:44:19.764318 progress 5 % (0 MB)
25 23:44:19.769471 progress 10 % (0 MB)
26 23:44:19.773878 progress 15 % (0 MB)
27 23:44:19.783238 progress 20 % (1 MB)
28 23:44:19.787159 progress 25 % (1 MB)
29 23:44:19.791496 progress 30 % (1 MB)
30 23:44:19.795715 progress 35 % (1 MB)
31 23:44:19.799508 progress 40 % (2 MB)
32 23:44:19.803748 progress 45 % (2 MB)
33 23:44:19.807603 progress 50 % (2 MB)
34 23:44:19.811706 progress 55 % (2 MB)
35 23:44:19.815950 progress 60 % (3 MB)
36 23:44:19.819900 progress 65 % (3 MB)
37 23:44:19.824190 progress 70 % (3 MB)
38 23:44:19.828031 progress 75 % (4 MB)
39 23:44:19.832301 progress 80 % (4 MB)
40 23:44:19.836073 progress 85 % (4 MB)
41 23:44:19.840379 progress 90 % (4 MB)
42 23:44:19.844591 progress 95 % (5 MB)
43 23:44:19.848048 progress 100 % (5 MB)
44 23:44:19.848763 5 MB downloaded in 0.13 s (41.32 MB/s)
45 23:44:19.849352 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:44:19.850288 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:44:19.850603 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:44:19.850892 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:44:19.851371 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/kernel/Image
51 23:44:19.851646 saving as /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/kernel/Image
52 23:44:19.851879 total size: 45713920 (43 MB)
53 23:44:19.852135 No compression specified
54 23:44:19.894630 progress 0 % (0 MB)
55 23:44:19.927209 progress 5 % (2 MB)
56 23:44:19.957097 progress 10 % (4 MB)
57 23:44:19.985868 progress 15 % (6 MB)
58 23:44:20.015326 progress 20 % (8 MB)
59 23:44:20.043733 progress 25 % (10 MB)
60 23:44:20.073266 progress 30 % (13 MB)
61 23:44:20.102735 progress 35 % (15 MB)
62 23:44:20.132275 progress 40 % (17 MB)
63 23:44:20.160788 progress 45 % (19 MB)
64 23:44:20.189267 progress 50 % (21 MB)
65 23:44:20.221624 progress 55 % (24 MB)
66 23:44:20.253174 progress 60 % (26 MB)
67 23:44:20.285744 progress 65 % (28 MB)
68 23:44:20.316344 progress 70 % (30 MB)
69 23:44:20.346429 progress 75 % (32 MB)
70 23:44:20.377679 progress 80 % (34 MB)
71 23:44:20.406420 progress 85 % (37 MB)
72 23:44:20.436478 progress 90 % (39 MB)
73 23:44:20.465637 progress 95 % (41 MB)
74 23:44:20.493767 progress 100 % (43 MB)
75 23:44:20.494345 43 MB downloaded in 0.64 s (67.86 MB/s)
76 23:44:20.494823 end: 1.2.1 http-download (duration 00:00:01) [common]
78 23:44:20.495647 end: 1.2 download-retry (duration 00:00:01) [common]
79 23:44:20.495925 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:44:20.496230 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:44:20.496743 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 23:44:20.497021 saving as /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/dtb/meson-g12b-a311d-libretech-cc.dtb
83 23:44:20.497231 total size: 54703 (0 MB)
84 23:44:20.497441 No compression specified
85 23:44:20.542038 progress 59 % (0 MB)
86 23:44:20.542945 progress 100 % (0 MB)
87 23:44:20.543533 0 MB downloaded in 0.05 s (1.13 MB/s)
88 23:44:20.544085 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:44:20.544964 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:44:20.545249 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:44:20.545528 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:44:20.546002 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 23:44:20.546268 saving as /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/nfsrootfs/full.rootfs.tar
95 23:44:20.546479 total size: 474398908 (452 MB)
96 23:44:20.546695 Using unxz to decompress xz
97 23:44:20.584094 progress 0 % (0 MB)
98 23:44:21.745489 progress 5 % (22 MB)
99 23:44:23.299548 progress 10 % (45 MB)
100 23:44:23.787224 progress 15 % (67 MB)
101 23:44:24.598931 progress 20 % (90 MB)
102 23:44:25.148152 progress 25 % (113 MB)
103 23:44:25.511055 progress 30 % (135 MB)
104 23:44:26.118021 progress 35 % (158 MB)
105 23:44:27.053415 progress 40 % (181 MB)
106 23:44:27.938831 progress 45 % (203 MB)
107 23:44:28.655831 progress 50 % (226 MB)
108 23:44:29.310753 progress 55 % (248 MB)
109 23:44:30.616554 progress 60 % (271 MB)
110 23:44:32.183613 progress 65 % (294 MB)
111 23:44:33.846605 progress 70 % (316 MB)
112 23:44:36.926447 progress 75 % (339 MB)
113 23:44:39.383120 progress 80 % (361 MB)
114 23:44:42.350861 progress 85 % (384 MB)
115 23:44:45.541625 progress 90 % (407 MB)
116 23:44:48.734592 progress 95 % (429 MB)
117 23:44:51.892236 progress 100 % (452 MB)
118 23:44:51.905122 452 MB downloaded in 31.36 s (14.43 MB/s)
119 23:44:51.905837 end: 1.4.1 http-download (duration 00:00:31) [common]
121 23:44:51.907637 end: 1.4 download-retry (duration 00:00:31) [common]
122 23:44:51.908270 start: 1.5 download-retry (timeout 00:09:28) [common]
123 23:44:51.908855 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 23:44:51.909731 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-102-gf43b156921299/arm64/defconfig/gcc-12/modules.tar.xz
125 23:44:51.910238 saving as /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/modules/modules.tar
126 23:44:51.910696 total size: 11608172 (11 MB)
127 23:44:51.911160 Using unxz to decompress xz
128 23:44:51.956965 progress 0 % (0 MB)
129 23:44:52.036145 progress 5 % (0 MB)
130 23:44:52.122439 progress 10 % (1 MB)
131 23:44:52.232594 progress 15 % (1 MB)
132 23:44:52.324334 progress 20 % (2 MB)
133 23:44:52.402809 progress 25 % (2 MB)
134 23:44:52.477444 progress 30 % (3 MB)
135 23:44:52.550358 progress 35 % (3 MB)
136 23:44:52.626610 progress 40 % (4 MB)
137 23:44:52.702102 progress 45 % (5 MB)
138 23:44:52.785191 progress 50 % (5 MB)
139 23:44:52.861438 progress 55 % (6 MB)
140 23:44:52.945703 progress 60 % (6 MB)
141 23:44:53.025681 progress 65 % (7 MB)
142 23:44:53.101341 progress 70 % (7 MB)
143 23:44:53.182005 progress 75 % (8 MB)
144 23:44:53.264509 progress 80 % (8 MB)
145 23:44:53.343468 progress 85 % (9 MB)
146 23:44:53.421133 progress 90 % (9 MB)
147 23:44:53.497946 progress 95 % (10 MB)
148 23:44:53.575030 progress 100 % (11 MB)
149 23:44:53.586012 11 MB downloaded in 1.68 s (6.61 MB/s)
150 23:44:53.586860 end: 1.5.1 http-download (duration 00:00:02) [common]
152 23:44:53.588521 end: 1.5 download-retry (duration 00:00:02) [common]
153 23:44:53.589038 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 23:44:53.589552 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 23:45:09.088853 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/949226/extract-nfsrootfs-kczoe96f
156 23:45:09.089464 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 23:45:09.089754 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 23:45:09.090464 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc
159 23:45:09.090936 makedir: /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin
160 23:45:09.091277 makedir: /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/tests
161 23:45:09.091602 makedir: /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/results
162 23:45:09.091948 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-add-keys
163 23:45:09.092557 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-add-sources
164 23:45:09.093102 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-background-process-start
165 23:45:09.093645 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-background-process-stop
166 23:45:09.094216 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-common-functions
167 23:45:09.094797 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-echo-ipv4
168 23:45:09.095356 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-install-packages
169 23:45:09.095890 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-installed-packages
170 23:45:09.096468 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-os-build
171 23:45:09.096973 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-probe-channel
172 23:45:09.097470 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-probe-ip
173 23:45:09.097976 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-target-ip
174 23:45:09.098520 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-target-mac
175 23:45:09.099103 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-target-storage
176 23:45:09.099630 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-test-case
177 23:45:09.100176 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-test-event
178 23:45:09.100763 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-test-feedback
179 23:45:09.101304 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-test-raise
180 23:45:09.101804 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-test-reference
181 23:45:09.102303 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-test-runner
182 23:45:09.102815 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-test-set
183 23:45:09.103336 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-test-shell
184 23:45:09.103851 Updating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-install-packages (oe)
185 23:45:09.104477 Updating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/bin/lava-installed-packages (oe)
186 23:45:09.104967 Creating /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/environment
187 23:45:09.105388 LAVA metadata
188 23:45:09.105666 - LAVA_JOB_ID=949226
189 23:45:09.105888 - LAVA_DISPATCHER_IP=192.168.6.2
190 23:45:09.106287 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 23:45:09.107363 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 23:45:09.107744 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 23:45:09.107956 skipped lava-vland-overlay
194 23:45:09.108243 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 23:45:09.108502 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 23:45:09.108729 skipped lava-multinode-overlay
197 23:45:09.108973 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 23:45:09.109226 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 23:45:09.109493 Loading test definitions
200 23:45:09.109784 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 23:45:09.110008 Using /lava-949226 at stage 0
202 23:45:09.111263 uuid=949226_1.6.2.4.1 testdef=None
203 23:45:09.111588 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 23:45:09.111857 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 23:45:09.113856 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 23:45:09.114698 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 23:45:09.117142 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 23:45:09.118051 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 23:45:09.120344 runner path: /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 949226_1.6.2.4.1
212 23:45:09.121038 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 23:45:09.121853 Creating lava-test-runner.conf files
215 23:45:09.122058 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/949226/lava-overlay-cx9psnnc/lava-949226/0 for stage 0
216 23:45:09.122421 - 0_v4l2-decoder-conformance-vp9
217 23:45:09.122796 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 23:45:09.123089 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 23:45:09.145465 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 23:45:09.145929 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 23:45:09.146195 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 23:45:09.146465 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 23:45:09.146730 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 23:45:09.769606 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 23:45:09.770082 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 23:45:09.770335 extracting modules file /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949226/extract-nfsrootfs-kczoe96f
227 23:45:11.175397 extracting modules file /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/949226/extract-overlay-ramdisk-t75geu3q/ramdisk
228 23:45:12.832219 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 23:45:12.832719 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 23:45:12.833000 [common] Applying overlay to NFS
231 23:45:12.833219 [common] Applying overlay /var/lib/lava/dispatcher/tmp/949226/compress-overlay-jmhbidvu/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/949226/extract-nfsrootfs-kczoe96f
232 23:45:12.867332 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 23:45:12.867801 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 23:45:12.868157 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 23:45:12.868429 Converting downloaded kernel to a uImage
236 23:45:12.868782 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/kernel/Image /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/kernel/uImage
237 23:45:13.325957 output: Image Name:
238 23:45:13.326384 output: Created: Wed Nov 6 23:45:12 2024
239 23:45:13.326592 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 23:45:13.326797 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 23:45:13.327000 output: Load Address: 01080000
242 23:45:13.327200 output: Entry Point: 01080000
243 23:45:13.327396 output:
244 23:45:13.327730 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 23:45:13.328032 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 23:45:13.328313 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 23:45:13.328569 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 23:45:13.328829 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 23:45:13.329084 Building ramdisk /var/lib/lava/dispatcher/tmp/949226/extract-overlay-ramdisk-t75geu3q/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/949226/extract-overlay-ramdisk-t75geu3q/ramdisk
250 23:45:15.489163 >> 166825 blocks
251 23:45:23.203928 Adding RAMdisk u-boot header.
252 23:45:23.204668 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/949226/extract-overlay-ramdisk-t75geu3q/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/949226/extract-overlay-ramdisk-t75geu3q/ramdisk.cpio.gz.uboot
253 23:45:23.480422 output: Image Name:
254 23:45:23.481034 output: Created: Wed Nov 6 23:45:23 2024
255 23:45:23.481450 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 23:45:23.481853 output: Data Size: 23432042 Bytes = 22882.85 KiB = 22.35 MiB
257 23:45:23.482252 output: Load Address: 00000000
258 23:45:23.482643 output: Entry Point: 00000000
259 23:45:23.483036 output:
260 23:45:23.484122 rename /var/lib/lava/dispatcher/tmp/949226/extract-overlay-ramdisk-t75geu3q/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/ramdisk/ramdisk.cpio.gz.uboot
261 23:45:23.484856 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 23:45:23.485410 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 23:45:23.485932 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 23:45:23.486392 No LXC device requested
265 23:45:23.486893 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 23:45:23.487403 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 23:45:23.487894 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 23:45:23.488336 Checking files for TFTP limit of 4294967296 bytes.
269 23:45:23.490998 end: 1 tftp-deploy (duration 00:01:04) [common]
270 23:45:23.491578 start: 2 uboot-action (timeout 00:05:00) [common]
271 23:45:23.492123 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 23:45:23.492624 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 23:45:23.493123 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 23:45:23.493648 Using kernel file from prepare-kernel: 949226/tftp-deploy-neks0fjb/kernel/uImage
275 23:45:23.494274 substitutions:
276 23:45:23.494676 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 23:45:23.495073 - {DTB_ADDR}: 0x01070000
278 23:45:23.495469 - {DTB}: 949226/tftp-deploy-neks0fjb/dtb/meson-g12b-a311d-libretech-cc.dtb
279 23:45:23.495865 - {INITRD}: 949226/tftp-deploy-neks0fjb/ramdisk/ramdisk.cpio.gz.uboot
280 23:45:23.496291 - {KERNEL_ADDR}: 0x01080000
281 23:45:23.496683 - {KERNEL}: 949226/tftp-deploy-neks0fjb/kernel/uImage
282 23:45:23.497074 - {LAVA_MAC}: None
283 23:45:23.497501 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/949226/extract-nfsrootfs-kczoe96f
284 23:45:23.497898 - {NFS_SERVER_IP}: 192.168.6.2
285 23:45:23.498284 - {PRESEED_CONFIG}: None
286 23:45:23.498670 - {PRESEED_LOCAL}: None
287 23:45:23.499059 - {RAMDISK_ADDR}: 0x08000000
288 23:45:23.499442 - {RAMDISK}: 949226/tftp-deploy-neks0fjb/ramdisk/ramdisk.cpio.gz.uboot
289 23:45:23.499831 - {ROOT_PART}: None
290 23:45:23.500244 - {ROOT}: None
291 23:45:23.500632 - {SERVER_IP}: 192.168.6.2
292 23:45:23.501020 - {TEE_ADDR}: 0x83000000
293 23:45:23.501404 - {TEE}: None
294 23:45:23.501786 Parsed boot commands:
295 23:45:23.502161 - setenv autoload no
296 23:45:23.502543 - setenv initrd_high 0xffffffff
297 23:45:23.502923 - setenv fdt_high 0xffffffff
298 23:45:23.503306 - dhcp
299 23:45:23.503688 - setenv serverip 192.168.6.2
300 23:45:23.504091 - tftpboot 0x01080000 949226/tftp-deploy-neks0fjb/kernel/uImage
301 23:45:23.504478 - tftpboot 0x08000000 949226/tftp-deploy-neks0fjb/ramdisk/ramdisk.cpio.gz.uboot
302 23:45:23.504861 - tftpboot 0x01070000 949226/tftp-deploy-neks0fjb/dtb/meson-g12b-a311d-libretech-cc.dtb
303 23:45:23.505244 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/949226/extract-nfsrootfs-kczoe96f,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 23:45:23.505642 - bootm 0x01080000 0x08000000 0x01070000
305 23:45:23.506146 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 23:45:23.507618 start: 2.3 connect-device (timeout 00:05:00) [common]
308 23:45:23.508058 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 23:45:23.523034 Setting prompt string to ['lava-test: # ']
310 23:45:23.524603 end: 2.3 connect-device (duration 00:00:00) [common]
311 23:45:23.525199 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 23:45:23.525741 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 23:45:23.526264 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 23:45:23.527383 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 23:45:23.584122 >> OK - accepted request
316 23:45:23.586238 Returned 0 in 0 seconds
317 23:45:23.687133 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 23:45:23.688819 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 23:45:23.689372 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 23:45:23.689886 Setting prompt string to ['Hit any key to stop autoboot']
322 23:45:23.690338 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 23:45:23.691913 Trying 192.168.56.21...
324 23:45:23.692422 Connected to conserv1.
325 23:45:23.692831 Escape character is '^]'.
326 23:45:23.693242
327 23:45:23.693654 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 23:45:23.694065
329 23:45:34.972899 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 23:45:34.973512 bl2_stage_init 0x01
331 23:45:34.973917 bl2_stage_init 0x81
332 23:45:34.978559 hw id: 0x0000 - pwm id 0x01
333 23:45:34.979012 bl2_stage_init 0xc1
334 23:45:34.979409 bl2_stage_init 0x02
335 23:45:34.979799
336 23:45:34.983959 L0:00000000
337 23:45:34.984407 L1:20000703
338 23:45:34.984798 L2:00008067
339 23:45:34.985183 L3:14000000
340 23:45:34.989617 B2:00402000
341 23:45:34.990056 B1:e0f83180
342 23:45:34.990453
343 23:45:34.990839 TE: 58124
344 23:45:34.991229
345 23:45:34.995346 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 23:45:34.995769
347 23:45:34.996197 Board ID = 1
348 23:45:35.000816 Set A53 clk to 24M
349 23:45:35.001230 Set A73 clk to 24M
350 23:45:35.001615 Set clk81 to 24M
351 23:45:35.006630 A53 clk: 1200 MHz
352 23:45:35.007039 A73 clk: 1200 MHz
353 23:45:35.007425 CLK81: 166.6M
354 23:45:35.007806 smccc: 00012a92
355 23:45:35.012050 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 23:45:35.017631 board id: 1
357 23:45:35.023725 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 23:45:35.034036 fw parse done
359 23:45:35.040050 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 23:45:35.082780 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 23:45:35.093614 PIEI prepare done
362 23:45:35.094033 fastboot data load
363 23:45:35.094424 fastboot data verify
364 23:45:35.099270 verify result: 266
365 23:45:35.104795 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 23:45:35.105214 LPDDR4 probe
367 23:45:35.105598 ddr clk to 1584MHz
368 23:45:35.112592 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 23:45:35.150158
370 23:45:35.150586 dmc_version 0001
371 23:45:35.156800 Check phy result
372 23:45:35.162667 INFO : End of CA training
373 23:45:35.163086 INFO : End of initialization
374 23:45:35.168245 INFO : Training has run successfully!
375 23:45:35.168666 Check phy result
376 23:45:35.173836 INFO : End of initialization
377 23:45:35.174248 INFO : End of read enable training
378 23:45:35.179455 INFO : End of fine write leveling
379 23:45:35.185072 INFO : End of Write leveling coarse delay
380 23:45:35.185493 INFO : Training has run successfully!
381 23:45:35.185884 Check phy result
382 23:45:35.190633 INFO : End of initialization
383 23:45:35.191045 INFO : End of read dq deskew training
384 23:45:35.196277 INFO : End of MPR read delay center optimization
385 23:45:35.201832 INFO : End of write delay center optimization
386 23:45:35.207539 INFO : End of read delay center optimization
387 23:45:35.207956 INFO : End of max read latency training
388 23:45:35.213106 INFO : Training has run successfully!
389 23:45:35.213526 1D training succeed
390 23:45:35.221674 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 23:45:35.269846 Check phy result
392 23:45:35.270289 INFO : End of initialization
393 23:45:35.291489 INFO : End of 2D read delay Voltage center optimization
394 23:45:35.311599 INFO : End of 2D read delay Voltage center optimization
395 23:45:35.363458 INFO : End of 2D write delay Voltage center optimization
396 23:45:35.412756 INFO : End of 2D write delay Voltage center optimization
397 23:45:35.418264 INFO : Training has run successfully!
398 23:45:35.418682
399 23:45:35.419079 channel==0
400 23:45:35.423876 RxClkDly_Margin_A0==78 ps 8
401 23:45:35.424339 TxDqDly_Margin_A0==98 ps 10
402 23:45:35.427137 RxClkDly_Margin_A1==88 ps 9
403 23:45:35.427561 TxDqDly_Margin_A1==98 ps 10
404 23:45:35.432639 TrainedVREFDQ_A0==74
405 23:45:35.433055 TrainedVREFDQ_A1==74
406 23:45:35.438293 VrefDac_Margin_A0==25
407 23:45:35.438704 DeviceVref_Margin_A0==40
408 23:45:35.439091 VrefDac_Margin_A1==25
409 23:45:35.443890 DeviceVref_Margin_A1==40
410 23:45:35.444327
411 23:45:35.444717
412 23:45:35.445106 channel==1
413 23:45:35.445491 RxClkDly_Margin_A0==98 ps 10
414 23:45:35.449626 TxDqDly_Margin_A0==88 ps 9
415 23:45:35.450044 RxClkDly_Margin_A1==98 ps 10
416 23:45:35.455062 TxDqDly_Margin_A1==88 ps 9
417 23:45:35.455475 TrainedVREFDQ_A0==77
418 23:45:35.455866 TrainedVREFDQ_A1==77
419 23:45:35.460715 VrefDac_Margin_A0==22
420 23:45:35.461134 DeviceVref_Margin_A0==37
421 23:45:35.466195 VrefDac_Margin_A1==22
422 23:45:35.466606 DeviceVref_Margin_A1==37
423 23:45:35.466989
424 23:45:35.471807 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 23:45:35.472248
426 23:45:35.499791 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 23:45:35.505490 2D training succeed
428 23:45:35.511030 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 23:45:35.511448 auto size-- 65535DDR cs0 size: 2048MB
430 23:45:35.516621 DDR cs1 size: 2048MB
431 23:45:35.517040 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 23:45:35.522175 cs0 DataBus test pass
433 23:45:35.522585 cs1 DataBus test pass
434 23:45:35.522973 cs0 AddrBus test pass
435 23:45:35.527767 cs1 AddrBus test pass
436 23:45:35.528219
437 23:45:35.528612 100bdlr_step_size ps== 432
438 23:45:35.529010 result report
439 23:45:35.533482 boot times 0Enable ddr reg access
440 23:45:35.541101 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 23:45:35.554661 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 23:45:36.127936 0.0;M3 CHK:0;cm4_sp_mode 0
443 23:45:36.128573 MVN_1=0x00000000
444 23:45:36.132651 MVN_2=0x00000000
445 23:45:36.137913 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 23:45:36.138382 OPS=0x10
447 23:45:36.138791 ring efuse init
448 23:45:36.139181 chipver efuse init
449 23:45:36.143618 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 23:45:36.149118 [0.018961 Inits done]
451 23:45:36.149574 secure task start!
452 23:45:36.149971 high task start!
453 23:45:36.153716 low task start!
454 23:45:36.154188 run into bl31
455 23:45:36.160448 NOTICE: BL31: v1.3(release):4fc40b1
456 23:45:36.168339 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 23:45:36.168830 NOTICE: BL31: G12A normal boot!
458 23:45:36.193573 NOTICE: BL31: BL33 decompress pass
459 23:45:36.198278 ERROR: Error initializing runtime service opteed_fast
460 23:45:37.432121
461 23:45:37.432749
462 23:45:37.440445 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 23:45:37.440942
464 23:45:37.441361 Model: Libre Computer AML-A311D-CC Alta
465 23:45:37.649233 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 23:45:37.672344 DRAM: 2 GiB (effective 3.8 GiB)
467 23:45:37.815305 Core: 408 devices, 31 uclasses, devicetree: separate
468 23:45:37.821250 WDT: Not starting watchdog@f0d0
469 23:45:37.853451 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 23:45:37.865935 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 23:45:37.871008 ** Bad device specification mmc 0 **
472 23:45:37.881225 Card did not respond to voltage select! : -110
473 23:45:37.889016 ** Bad device specification mmc 0 **
474 23:45:37.889443 Couldn't find partition mmc 0
475 23:45:37.897329 Card did not respond to voltage select! : -110
476 23:45:37.902828 ** Bad device specification mmc 0 **
477 23:45:37.903276 Couldn't find partition mmc 0
478 23:45:37.907918 Error: could not access storage.
479 23:45:39.173573 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 23:45:39.174012 bl2_stage_init 0x01
481 23:45:39.174260 bl2_stage_init 0x81
482 23:45:39.179164 hw id: 0x0000 - pwm id 0x01
483 23:45:39.179661 bl2_stage_init 0xc1
484 23:45:39.180062 bl2_stage_init 0x02
485 23:45:39.180432
486 23:45:39.184795 L0:00000000
487 23:45:39.185134 L1:20000703
488 23:45:39.185377 L2:00008067
489 23:45:39.185629 L3:14000000
490 23:45:39.190415 B2:00402000
491 23:45:39.190916 B1:e0f83180
492 23:45:39.191254
493 23:45:39.191633 TE: 58167
494 23:45:39.191897
495 23:45:39.196074 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 23:45:39.196815
497 23:45:39.197483 Board ID = 1
498 23:45:39.201599 Set A53 clk to 24M
499 23:45:39.202184 Set A73 clk to 24M
500 23:45:39.202546 Set clk81 to 24M
501 23:45:39.206983 A53 clk: 1200 MHz
502 23:45:39.207562 A73 clk: 1200 MHz
503 23:45:39.208146 CLK81: 166.6M
504 23:45:39.208456 smccc: 00012abd
505 23:45:39.212570 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 23:45:39.218241 board id: 1
507 23:45:39.224064 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 23:45:39.234820 fw parse done
509 23:45:39.240718 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 23:45:39.283413 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 23:45:39.294286 PIEI prepare done
512 23:45:39.295028 fastboot data load
513 23:45:39.295593 fastboot data verify
514 23:45:39.299900 verify result: 266
515 23:45:39.305445 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 23:45:39.306138 LPDDR4 probe
517 23:45:39.306677 ddr clk to 1584MHz
518 23:45:39.313472 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 23:45:39.350765
520 23:45:39.351409 dmc_version 0001
521 23:45:39.357369 Check phy result
522 23:45:39.363203 INFO : End of CA training
523 23:45:39.363788 INFO : End of initialization
524 23:45:39.368785 INFO : Training has run successfully!
525 23:45:39.369352 Check phy result
526 23:45:39.374365 INFO : End of initialization
527 23:45:39.374935 INFO : End of read enable training
528 23:45:39.380018 INFO : End of fine write leveling
529 23:45:39.385559 INFO : End of Write leveling coarse delay
530 23:45:39.386135 INFO : Training has run successfully!
531 23:45:39.386658 Check phy result
532 23:45:39.391165 INFO : End of initialization
533 23:45:39.391752 INFO : End of read dq deskew training
534 23:45:39.396857 INFO : End of MPR read delay center optimization
535 23:45:39.402409 INFO : End of write delay center optimization
536 23:45:39.408081 INFO : End of read delay center optimization
537 23:45:39.408665 INFO : End of max read latency training
538 23:45:39.413636 INFO : Training has run successfully!
539 23:45:39.414214 1D training succeed
540 23:45:39.422783 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 23:45:39.470397 Check phy result
542 23:45:39.470997 INFO : End of initialization
543 23:45:39.493029 INFO : End of 2D read delay Voltage center optimization
544 23:45:39.513321 INFO : End of 2D read delay Voltage center optimization
545 23:45:39.565513 INFO : End of 2D write delay Voltage center optimization
546 23:45:39.614988 INFO : End of 2D write delay Voltage center optimization
547 23:45:39.620280 INFO : Training has run successfully!
548 23:45:39.620666
549 23:45:39.620887 channel==0
550 23:45:39.625782 RxClkDly_Margin_A0==88 ps 9
551 23:45:39.626069 TxDqDly_Margin_A0==98 ps 10
552 23:45:39.631333 RxClkDly_Margin_A1==88 ps 9
553 23:45:39.631593 TxDqDly_Margin_A1==98 ps 10
554 23:45:39.631802 TrainedVREFDQ_A0==74
555 23:45:39.637144 TrainedVREFDQ_A1==74
556 23:45:39.637628 VrefDac_Margin_A0==24
557 23:45:39.638027 DeviceVref_Margin_A0==40
558 23:45:39.642665 VrefDac_Margin_A1==25
559 23:45:39.643167 DeviceVref_Margin_A1==40
560 23:45:39.643565
561 23:45:39.643959
562 23:45:39.648293 channel==1
563 23:45:39.648811 RxClkDly_Margin_A0==98 ps 10
564 23:45:39.649217 TxDqDly_Margin_A0==98 ps 10
565 23:45:39.654057 RxClkDly_Margin_A1==98 ps 10
566 23:45:39.654516 TxDqDly_Margin_A1==88 ps 9
567 23:45:39.659388 TrainedVREFDQ_A0==77
568 23:45:39.659837 TrainedVREFDQ_A1==77
569 23:45:39.660270 VrefDac_Margin_A0==22
570 23:45:39.665095 DeviceVref_Margin_A0==37
571 23:45:39.665532 VrefDac_Margin_A1==24
572 23:45:39.670577 DeviceVref_Margin_A1==37
573 23:45:39.671064
574 23:45:39.671464 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 23:45:39.676281
576 23:45:39.704300 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 23:45:39.705061 2D training succeed
578 23:45:39.709864 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 23:45:39.715351 auto size-- 65535DDR cs0 size: 2048MB
580 23:45:39.716010 DDR cs1 size: 2048MB
581 23:45:39.721105 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 23:45:39.721794 cs0 DataBus test pass
583 23:45:39.726606 cs1 DataBus test pass
584 23:45:39.727261 cs0 AddrBus test pass
585 23:45:39.727831 cs1 AddrBus test pass
586 23:45:39.728447
587 23:45:39.732222 100bdlr_step_size ps== 420
588 23:45:39.732898 result report
589 23:45:39.737952 boot times 0Enable ddr reg access
590 23:45:39.743227 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 23:45:39.756689 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 23:45:40.330269 0.0;M3 CHK:0;cm4_sp_mode 0
593 23:45:40.330912 MVN_1=0x00000000
594 23:45:40.335773 MVN_2=0x00000000
595 23:45:40.341539 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 23:45:40.342069 OPS=0x10
597 23:45:40.342508 ring efuse init
598 23:45:40.342947 chipver efuse init
599 23:45:40.349734 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 23:45:40.350262 [0.018961 Inits done]
601 23:45:40.357301 secure task start!
602 23:45:40.357795 high task start!
603 23:45:40.358215 low task start!
604 23:45:40.358625 run into bl31
605 23:45:40.364165 NOTICE: BL31: v1.3(release):4fc40b1
606 23:45:40.370858 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 23:45:40.371580 NOTICE: BL31: G12A normal boot!
608 23:45:40.397206 NOTICE: BL31: BL33 decompress pass
609 23:45:40.402001 ERROR: Error initializing runtime service opteed_fast
610 23:45:41.635708
611 23:45:41.636146
612 23:45:41.644126 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 23:45:41.644456
614 23:45:41.644678 Model: Libre Computer AML-A311D-CC Alta
615 23:45:41.852663 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 23:45:41.876184 DRAM: 2 GiB (effective 3.8 GiB)
617 23:45:42.018906 Core: 408 devices, 31 uclasses, devicetree: separate
618 23:45:42.024735 WDT: Not starting watchdog@f0d0
619 23:45:42.057076 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 23:45:42.069465 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 23:45:42.074490 ** Bad device specification mmc 0 **
622 23:45:42.084789 Card did not respond to voltage select! : -110
623 23:45:42.092408 ** Bad device specification mmc 0 **
624 23:45:42.092706 Couldn't find partition mmc 0
625 23:45:42.100764 Card did not respond to voltage select! : -110
626 23:45:42.106239 ** Bad device specification mmc 0 **
627 23:45:42.106519 Couldn't find partition mmc 0
628 23:45:42.111315 Error: could not access storage.
629 23:45:42.453879 Net: eth0: ethernet@ff3f0000
630 23:45:42.454485 starting USB...
631 23:45:42.705720 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 23:45:42.706326 Starting the controller
633 23:45:42.712634 USB XHCI 1.10
634 23:45:44.423482 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 23:45:44.424074 bl2_stage_init 0x01
636 23:45:44.424365 bl2_stage_init 0x81
637 23:45:44.429022 hw id: 0x0000 - pwm id 0x01
638 23:45:44.429494 bl2_stage_init 0xc1
639 23:45:44.431032 bl2_stage_init 0x02
640 23:45:44.431332
641 23:45:44.434573 L0:00000000
642 23:45:44.435219 L1:20000703
643 23:45:44.435519 L2:00008067
644 23:45:44.435759 L3:14000000
645 23:45:44.440179 B2:00402000
646 23:45:44.441213 B1:e0f83180
647 23:45:44.441517
648 23:45:44.441801 TE: 58124
649 23:45:44.442065
650 23:45:44.445779 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 23:45:44.446227
652 23:45:44.446506 Board ID = 1
653 23:45:44.451388 Set A53 clk to 24M
654 23:45:44.451841 Set A73 clk to 24M
655 23:45:44.452174 Set clk81 to 24M
656 23:45:44.456974 A53 clk: 1200 MHz
657 23:45:44.457403 A73 clk: 1200 MHz
658 23:45:44.457665 CLK81: 166.6M
659 23:45:44.457917 smccc: 00012a91
660 23:45:44.462510 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 23:45:44.468142 board id: 1
662 23:45:44.474311 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 23:45:44.484722 fw parse done
664 23:45:44.490753 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 23:45:44.533300 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 23:45:44.544228 PIEI prepare done
667 23:45:44.544732 fastboot data load
668 23:45:44.545437 fastboot data verify
669 23:45:44.549767 verify result: 266
670 23:45:44.555357 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 23:45:44.555830 LPDDR4 probe
672 23:45:44.556166 ddr clk to 1584MHz
673 23:45:44.563328 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 23:45:44.600748
675 23:45:44.601269 dmc_version 0001
676 23:45:44.607337 Check phy result
677 23:45:44.613165 INFO : End of CA training
678 23:45:44.613659 INFO : End of initialization
679 23:45:44.618767 INFO : Training has run successfully!
680 23:45:44.619235 Check phy result
681 23:45:44.624366 INFO : End of initialization
682 23:45:44.624836 INFO : End of read enable training
683 23:45:44.629942 INFO : End of fine write leveling
684 23:45:44.635711 INFO : End of Write leveling coarse delay
685 23:45:44.636217 INFO : Training has run successfully!
686 23:45:44.636520 Check phy result
687 23:45:44.641191 INFO : End of initialization
688 23:45:44.641657 INFO : End of read dq deskew training
689 23:45:44.646800 INFO : End of MPR read delay center optimization
690 23:45:44.652367 INFO : End of write delay center optimization
691 23:45:44.658005 INFO : End of read delay center optimization
692 23:45:44.658485 INFO : End of max read latency training
693 23:45:44.663606 INFO : Training has run successfully!
694 23:45:44.664129 1D training succeed
695 23:45:44.671741 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 23:45:44.720593 Check phy result
697 23:45:44.721344 INFO : End of initialization
698 23:45:44.742339 INFO : End of 2D read delay Voltage center optimization
699 23:45:44.762555 INFO : End of 2D read delay Voltage center optimization
700 23:45:44.814672 INFO : End of 2D write delay Voltage center optimization
701 23:45:44.863907 INFO : End of 2D write delay Voltage center optimization
702 23:45:44.869439 INFO : Training has run successfully!
703 23:45:44.869847
704 23:45:44.870087 channel==0
705 23:45:44.875031 RxClkDly_Margin_A0==88 ps 9
706 23:45:44.875421 TxDqDly_Margin_A0==98 ps 10
707 23:45:44.878334 RxClkDly_Margin_A1==88 ps 9
708 23:45:44.878719 TxDqDly_Margin_A1==88 ps 9
709 23:45:44.883872 TrainedVREFDQ_A0==74
710 23:45:44.884292 TrainedVREFDQ_A1==74
711 23:45:44.884525 VrefDac_Margin_A0==25
712 23:45:44.889464 DeviceVref_Margin_A0==40
713 23:45:44.889861 VrefDac_Margin_A1==25
714 23:45:44.895242 DeviceVref_Margin_A1==40
715 23:45:44.896128
716 23:45:44.896608
717 23:45:44.897056 channel==1
718 23:45:44.897473 RxClkDly_Margin_A0==98 ps 10
719 23:45:44.898433 TxDqDly_Margin_A0==98 ps 10
720 23:45:44.904047 RxClkDly_Margin_A1==88 ps 9
721 23:45:44.904637 TxDqDly_Margin_A1==88 ps 9
722 23:45:44.905074 TrainedVREFDQ_A0==77
723 23:45:44.909620 TrainedVREFDQ_A1==77
724 23:45:44.910192 VrefDac_Margin_A0==22
725 23:45:44.915211 DeviceVref_Margin_A0==37
726 23:45:44.915774 VrefDac_Margin_A1==24
727 23:45:44.916372 DeviceVref_Margin_A1==37
728 23:45:44.916814
729 23:45:44.920793 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 23:45:44.921351
731 23:45:44.954493 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 23:45:44.955206 2D training succeed
733 23:45:44.960038 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 23:45:44.965610 auto size-- 65535DDR cs0 size: 2048MB
735 23:45:44.966296 DDR cs1 size: 2048MB
736 23:45:44.971220 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 23:45:44.971958 cs0 DataBus test pass
738 23:45:44.972660 cs1 DataBus test pass
739 23:45:44.976821 cs0 AddrBus test pass
740 23:45:44.977604 cs1 AddrBus test pass
741 23:45:44.978251
742 23:45:44.982360 100bdlr_step_size ps== 420
743 23:45:44.983145 result report
744 23:45:44.983830 boot times 0Enable ddr reg access
745 23:45:44.992224 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 23:45:45.005689 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 23:45:45.579326 0.0;M3 CHK:0;cm4_sp_mode 0
748 23:45:45.579780 MVN_1=0x00000000
749 23:45:45.584881 MVN_2=0x00000000
750 23:45:45.590622 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 23:45:45.591039 OPS=0x10
752 23:45:45.591282 ring efuse init
753 23:45:45.591506 chipver efuse init
754 23:45:45.598868 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 23:45:45.599293 [0.018961 Inits done]
756 23:45:45.606487 secure task start!
757 23:45:45.606883 high task start!
758 23:45:45.607115 low task start!
759 23:45:45.607328 run into bl31
760 23:45:45.613088 NOTICE: BL31: v1.3(release):4fc40b1
761 23:45:45.621046 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 23:45:45.621450 NOTICE: BL31: G12A normal boot!
763 23:45:45.646945 NOTICE: BL31: BL33 decompress pass
764 23:45:45.652553 ERROR: Error initializing runtime service opteed_fast
765 23:45:46.885289
766 23:45:46.885726
767 23:45:46.893696 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 23:45:46.894018
769 23:45:46.894250 Model: Libre Computer AML-A311D-CC Alta
770 23:45:47.102146 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 23:45:47.125549 DRAM: 2 GiB (effective 3.8 GiB)
772 23:45:47.268537 Core: 408 devices, 31 uclasses, devicetree: separate
773 23:45:47.274362 WDT: Not starting watchdog@f0d0
774 23:45:47.306661 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 23:45:47.319083 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 23:45:47.324134 ** Bad device specification mmc 0 **
777 23:45:47.334442 Card did not respond to voltage select! : -110
778 23:45:47.342136 ** Bad device specification mmc 0 **
779 23:45:47.342456 Couldn't find partition mmc 0
780 23:45:47.350410 Card did not respond to voltage select! : -110
781 23:45:47.356062 ** Bad device specification mmc 0 **
782 23:45:47.356358 Couldn't find partition mmc 0
783 23:45:47.360972 Error: could not access storage.
784 23:45:47.703463 Net: eth0: ethernet@ff3f0000
785 23:45:47.703880 starting USB...
786 23:45:47.955276 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 23:45:47.955700 Starting the controller
788 23:45:47.962215 USB XHCI 1.10
789 23:45:50.124841 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 23:45:50.125527 bl2_stage_init 0x01
791 23:45:50.126008 bl2_stage_init 0x81
792 23:45:50.130471 hw id: 0x0000 - pwm id 0x01
793 23:45:50.131123 bl2_stage_init 0xc1
794 23:45:50.131647 bl2_stage_init 0x02
795 23:45:50.132202
796 23:45:50.135911 L0:00000000
797 23:45:50.136799 L1:20000703
798 23:45:50.137436 L2:00008067
799 23:45:50.137973 L3:14000000
800 23:45:50.141541 B2:00402000
801 23:45:50.142124 B1:e0f83180
802 23:45:50.142648
803 23:45:50.143169 TE: 58124
804 23:45:50.143623
805 23:45:50.147158 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 23:45:50.147702
807 23:45:50.148221 Board ID = 1
808 23:45:50.152694 Set A53 clk to 24M
809 23:45:50.153220 Set A73 clk to 24M
810 23:45:50.154005 Set clk81 to 24M
811 23:45:50.158385 A53 clk: 1200 MHz
812 23:45:50.159248 A73 clk: 1200 MHz
813 23:45:50.159739 CLK81: 166.6M
814 23:45:50.160373 smccc: 00012a91
815 23:45:50.163884 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 23:45:50.169527 board id: 1
817 23:45:50.175622 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 23:45:50.186034 fw parse done
819 23:45:50.192036 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 23:45:50.234614 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 23:45:50.245560 PIEI prepare done
822 23:45:50.246121 fastboot data load
823 23:45:50.246639 fastboot data verify
824 23:45:50.251183 verify result: 266
825 23:45:50.256742 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 23:45:50.257308 LPDDR4 probe
827 23:45:50.257786 ddr clk to 1584MHz
828 23:45:50.264732 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 23:45:50.302034
830 23:45:50.302637 dmc_version 0001
831 23:45:50.308675 Check phy result
832 23:45:50.314604 INFO : End of CA training
833 23:45:50.315178 INFO : End of initialization
834 23:45:50.320302 INFO : Training has run successfully!
835 23:45:50.321014 Check phy result
836 23:45:50.325732 INFO : End of initialization
837 23:45:50.326404 INFO : End of read enable training
838 23:45:50.331478 INFO : End of fine write leveling
839 23:45:50.336939 INFO : End of Write leveling coarse delay
840 23:45:50.337610 INFO : Training has run successfully!
841 23:45:50.338139 Check phy result
842 23:45:50.342523 INFO : End of initialization
843 23:45:50.343152 INFO : End of read dq deskew training
844 23:45:50.348146 INFO : End of MPR read delay center optimization
845 23:45:50.353711 INFO : End of write delay center optimization
846 23:45:50.359421 INFO : End of read delay center optimization
847 23:45:50.360051 INFO : End of max read latency training
848 23:45:50.364961 INFO : Training has run successfully!
849 23:45:50.365802 1D training succeed
850 23:45:50.374143 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 23:45:50.421839 Check phy result
852 23:45:50.422661 INFO : End of initialization
853 23:45:50.443656 INFO : End of 2D read delay Voltage center optimization
854 23:45:50.463778 INFO : End of 2D read delay Voltage center optimization
855 23:45:50.515858 INFO : End of 2D write delay Voltage center optimization
856 23:45:50.565240 INFO : End of 2D write delay Voltage center optimization
857 23:45:50.570737 INFO : Training has run successfully!
858 23:45:50.571100
859 23:45:50.571339 channel==0
860 23:45:50.576391 RxClkDly_Margin_A0==88 ps 9
861 23:45:50.576722 TxDqDly_Margin_A0==98 ps 10
862 23:45:50.581913 RxClkDly_Margin_A1==88 ps 9
863 23:45:50.582249 TxDqDly_Margin_A1==98 ps 10
864 23:45:50.582477 TrainedVREFDQ_A0==74
865 23:45:50.587547 TrainedVREFDQ_A1==76
866 23:45:50.587885 VrefDac_Margin_A0==25
867 23:45:50.588159 DeviceVref_Margin_A0==40
868 23:45:50.593127 VrefDac_Margin_A1==26
869 23:45:50.593446 DeviceVref_Margin_A1==38
870 23:45:50.593667
871 23:45:50.593878
872 23:45:50.598729 channel==1
873 23:45:50.599039 RxClkDly_Margin_A0==98 ps 10
874 23:45:50.599260 TxDqDly_Margin_A0==98 ps 10
875 23:45:50.604366 RxClkDly_Margin_A1==88 ps 9
876 23:45:50.604685 TxDqDly_Margin_A1==88 ps 9
877 23:45:50.609915 TrainedVREFDQ_A0==77
878 23:45:50.610239 TrainedVREFDQ_A1==77
879 23:45:50.610457 VrefDac_Margin_A0==22
880 23:45:50.615534 DeviceVref_Margin_A0==37
881 23:45:50.615845 VrefDac_Margin_A1==24
882 23:45:50.621125 DeviceVref_Margin_A1==37
883 23:45:50.621447
884 23:45:50.621670 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 23:45:50.621877
886 23:45:50.654982 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
887 23:45:50.655350 2D training succeed
888 23:45:50.660547 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 23:45:50.666055 auto size-- 65535DDR cs0 size: 2048MB
890 23:45:50.666369 DDR cs1 size: 2048MB
891 23:45:50.671759 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 23:45:50.672130 cs0 DataBus test pass
893 23:45:50.677270 cs1 DataBus test pass
894 23:45:50.677595 cs0 AddrBus test pass
895 23:45:50.677820 cs1 AddrBus test pass
896 23:45:50.678026
897 23:45:50.682880 100bdlr_step_size ps== 420
898 23:45:50.683202 result report
899 23:45:50.688497 boot times 0Enable ddr reg access
900 23:45:50.693906 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 23:45:50.707297 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 23:45:51.280386 0.0;M3 CHK:0;cm4_sp_mode 0
903 23:45:51.280812 MVN_1=0x00000000
904 23:45:51.285876 MVN_2=0x00000000
905 23:45:51.291709 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 23:45:51.292057 OPS=0x10
907 23:45:51.292287 ring efuse init
908 23:45:51.292497 chipver efuse init
909 23:45:51.300024 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 23:45:51.300378 [0.018961 Inits done]
911 23:45:51.306683 secure task start!
912 23:45:51.306989 high task start!
913 23:45:51.307200 low task start!
914 23:45:51.307398 run into bl31
915 23:45:51.314082 NOTICE: BL31: v1.3(release):4fc40b1
916 23:45:51.321952 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 23:45:51.322286 NOTICE: BL31: G12A normal boot!
918 23:45:51.347341 NOTICE: BL31: BL33 decompress pass
919 23:45:51.352929 ERROR: Error initializing runtime service opteed_fast
920 23:45:52.585862
921 23:45:52.586282
922 23:45:52.594139 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 23:45:52.594479
924 23:45:52.594701 Model: Libre Computer AML-A311D-CC Alta
925 23:45:52.802700 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 23:45:52.826097 DRAM: 2 GiB (effective 3.8 GiB)
927 23:45:52.969123 Core: 408 devices, 31 uclasses, devicetree: separate
928 23:45:52.974941 WDT: Not starting watchdog@f0d0
929 23:45:53.007111 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 23:45:53.019606 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 23:45:53.024607 ** Bad device specification mmc 0 **
932 23:45:53.035053 Card did not respond to voltage select! : -110
933 23:45:53.042587 ** Bad device specification mmc 0 **
934 23:45:53.043033 Couldn't find partition mmc 0
935 23:45:53.050934 Card did not respond to voltage select! : -110
936 23:45:53.056401 ** Bad device specification mmc 0 **
937 23:45:53.056844 Couldn't find partition mmc 0
938 23:45:53.061508 Error: could not access storage.
939 23:45:53.405223 Net: eth0: ethernet@ff3f0000
940 23:45:53.405778 starting USB...
941 23:45:53.656778 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 23:45:53.657308 Starting the controller
943 23:45:53.663853 USB XHCI 1.10
944 23:45:55.525127 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 23:45:55.525778 bl2_stage_init 0x01
946 23:45:55.526251 bl2_stage_init 0x81
947 23:45:55.530852 hw id: 0x0000 - pwm id 0x01
948 23:45:55.531370 bl2_stage_init 0xc1
949 23:45:55.531828 bl2_stage_init 0x02
950 23:45:55.532355
951 23:45:55.536391 L0:00000000
952 23:45:55.536909 L1:20000703
953 23:45:55.537366 L2:00008067
954 23:45:55.537807 L3:14000000
955 23:45:55.541901 B2:00402000
956 23:45:55.542413 B1:e0f83180
957 23:45:55.542862
958 23:45:55.543309 TE: 58167
959 23:45:55.543755
960 23:45:55.547549 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 23:45:55.548094
962 23:45:55.548555 Board ID = 1
963 23:45:55.553091 Set A53 clk to 24M
964 23:45:55.553600 Set A73 clk to 24M
965 23:45:55.554050 Set clk81 to 24M
966 23:45:55.558762 A53 clk: 1200 MHz
967 23:45:55.559270 A73 clk: 1200 MHz
968 23:45:55.559718 CLK81: 166.6M
969 23:45:55.560191 smccc: 00012abd
970 23:45:55.564354 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 23:45:55.569727 board id: 1
972 23:45:55.575623 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 23:45:55.586326 fw parse done
974 23:45:55.592423 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 23:45:55.634958 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 23:45:55.645795 PIEI prepare done
977 23:45:55.646291 fastboot data load
978 23:45:55.646722 fastboot data verify
979 23:45:55.651359 verify result: 266
980 23:45:55.656991 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 23:45:55.657480 LPDDR4 probe
982 23:45:55.657904 ddr clk to 1584MHz
983 23:45:55.665048 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 23:45:55.702206
985 23:45:55.702694 dmc_version 0001
986 23:45:55.708916 Check phy result
987 23:45:55.714736 INFO : End of CA training
988 23:45:55.715226 INFO : End of initialization
989 23:45:55.720373 INFO : Training has run successfully!
990 23:45:55.720893 Check phy result
991 23:45:55.725957 INFO : End of initialization
992 23:45:55.726478 INFO : End of read enable training
993 23:45:55.729285 INFO : End of fine write leveling
994 23:45:55.734795 INFO : End of Write leveling coarse delay
995 23:45:55.740417 INFO : Training has run successfully!
996 23:45:55.740924 Check phy result
997 23:45:55.741370 INFO : End of initialization
998 23:45:55.745993 INFO : End of read dq deskew training
999 23:45:55.751618 INFO : End of MPR read delay center optimization
1000 23:45:55.752145 INFO : End of write delay center optimization
1001 23:45:55.757232 INFO : End of read delay center optimization
1002 23:45:55.762787 INFO : End of max read latency training
1003 23:45:55.763282 INFO : Training has run successfully!
1004 23:45:55.768395 1D training succeed
1005 23:45:55.774517 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 23:45:55.821979 Check phy result
1007 23:45:55.822503 INFO : End of initialization
1008 23:45:55.844502 INFO : End of 2D read delay Voltage center optimization
1009 23:45:55.864865 INFO : End of 2D read delay Voltage center optimization
1010 23:45:55.916856 INFO : End of 2D write delay Voltage center optimization
1011 23:45:55.966180 INFO : End of 2D write delay Voltage center optimization
1012 23:45:55.971730 INFO : Training has run successfully!
1013 23:45:55.972285
1014 23:45:55.972744 channel==0
1015 23:45:55.977509 RxClkDly_Margin_A0==88 ps 9
1016 23:45:55.978012 TxDqDly_Margin_A0==98 ps 10
1017 23:45:55.982930 RxClkDly_Margin_A1==88 ps 9
1018 23:45:55.983425 TxDqDly_Margin_A1==98 ps 10
1019 23:45:55.983878 TrainedVREFDQ_A0==74
1020 23:45:55.988622 TrainedVREFDQ_A1==74
1021 23:45:55.989131 VrefDac_Margin_A0==24
1022 23:45:55.989584 DeviceVref_Margin_A0==40
1023 23:45:55.994134 VrefDac_Margin_A1==24
1024 23:45:55.994633 DeviceVref_Margin_A1==40
1025 23:45:55.995078
1026 23:45:55.995523
1027 23:45:55.999757 channel==1
1028 23:45:56.000297 RxClkDly_Margin_A0==98 ps 10
1029 23:45:56.000747 TxDqDly_Margin_A0==88 ps 9
1030 23:45:56.005532 RxClkDly_Margin_A1==88 ps 9
1031 23:45:56.006035 TxDqDly_Margin_A1==88 ps 9
1032 23:45:56.011029 TrainedVREFDQ_A0==77
1033 23:45:56.011534 TrainedVREFDQ_A1==77
1034 23:45:56.012017 VrefDac_Margin_A0==22
1035 23:45:56.016622 DeviceVref_Margin_A0==37
1036 23:45:56.017118 VrefDac_Margin_A1==24
1037 23:45:56.022211 DeviceVref_Margin_A1==37
1038 23:45:56.022705
1039 23:45:56.023150 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 23:45:56.023588
1041 23:45:56.055728 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1042 23:45:56.056304 2D training succeed
1043 23:45:56.061490 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 23:45:56.067029 auto size-- 65535DDR cs0 size: 2048MB
1045 23:45:56.067529 DDR cs1 size: 2048MB
1046 23:45:56.072507 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 23:45:56.073010 cs0 DataBus test pass
1048 23:45:56.078085 cs1 DataBus test pass
1049 23:45:56.078582 cs0 AddrBus test pass
1050 23:45:56.079030 cs1 AddrBus test pass
1051 23:45:56.079470
1052 23:45:56.083659 100bdlr_step_size ps== 420
1053 23:45:56.084215 result report
1054 23:45:56.089382 boot times 0Enable ddr reg access
1055 23:45:56.094548 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 23:45:56.107971 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 23:45:56.681685 0.0;M3 CHK:0;cm4_sp_mode 0
1058 23:45:56.682254 MVN_1=0x00000000
1059 23:45:56.687188 MVN_2=0x00000000
1060 23:45:56.692994 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 23:45:56.693519 OPS=0x10
1062 23:45:56.693974 ring efuse init
1063 23:45:56.694412 chipver efuse init
1064 23:45:56.698563 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 23:45:56.704169 [0.018961 Inits done]
1066 23:45:56.704672 secure task start!
1067 23:45:56.705119 high task start!
1068 23:45:56.708705 low task start!
1069 23:45:56.709201 run into bl31
1070 23:45:56.715441 NOTICE: BL31: v1.3(release):4fc40b1
1071 23:45:56.723193 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 23:45:56.723698 NOTICE: BL31: G12A normal boot!
1073 23:45:56.748555 NOTICE: BL31: BL33 decompress pass
1074 23:45:56.754252 ERROR: Error initializing runtime service opteed_fast
1075 23:45:57.987079
1076 23:45:57.987700
1077 23:45:57.995513 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 23:45:57.996067
1079 23:45:57.996529 Model: Libre Computer AML-A311D-CC Alta
1080 23:45:58.203900 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 23:45:58.227286 DRAM: 2 GiB (effective 3.8 GiB)
1082 23:45:58.370274 Core: 408 devices, 31 uclasses, devicetree: separate
1083 23:45:58.376195 WDT: Not starting watchdog@f0d0
1084 23:45:58.408429 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 23:45:58.420845 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 23:45:58.425873 ** Bad device specification mmc 0 **
1087 23:45:58.436215 Card did not respond to voltage select! : -110
1088 23:45:58.443851 ** Bad device specification mmc 0 **
1089 23:45:58.444379 Couldn't find partition mmc 0
1090 23:45:58.452209 Card did not respond to voltage select! : -110
1091 23:45:58.457711 ** Bad device specification mmc 0 **
1092 23:45:58.458219 Couldn't find partition mmc 0
1093 23:45:58.462759 Error: could not access storage.
1094 23:45:58.805166 Net: eth0: ethernet@ff3f0000
1095 23:45:58.805707 starting USB...
1096 23:45:59.057075 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 23:45:59.057634 Starting the controller
1098 23:45:59.064064 USB XHCI 1.10
1099 23:46:00.619486 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 23:46:00.626981 scanning usb for storage devices... 0 Storage Device(s) found
1102 23:46:00.678765 Hit any key to stop autoboot: 1
1103 23:46:00.679638 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 23:46:00.680317 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 23:46:00.680820 Setting prompt string to ['=>']
1106 23:46:00.681327 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 23:46:00.694311 0
1108 23:46:00.695345 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 23:46:00.695896 Sending with 10 millisecond of delay
1111 23:46:01.831442 => setenv autoload no
1112 23:46:01.842439 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 23:46:01.847890 setenv autoload no
1114 23:46:01.848723 Sending with 10 millisecond of delay
1116 23:46:03.647521 => setenv initrd_high 0xffffffff
1117 23:46:03.658361 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 23:46:03.659261 setenv initrd_high 0xffffffff
1119 23:46:03.660043 Sending with 10 millisecond of delay
1121 23:46:05.276892 => setenv fdt_high 0xffffffff
1122 23:46:05.287668 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 23:46:05.288575 setenv fdt_high 0xffffffff
1124 23:46:05.289339 Sending with 10 millisecond of delay
1126 23:46:05.581308 => dhcp
1127 23:46:05.592095 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 23:46:05.593034 dhcp
1129 23:46:05.593483 Speed: 1000, full duplex
1130 23:46:05.593892 BOOTP broadcast 1
1131 23:46:05.600137 DHCP client bound to address 192.168.6.27 (8 ms)
1132 23:46:05.601000 Sending with 10 millisecond of delay
1134 23:46:07.278076 => setenv serverip 192.168.6.2
1135 23:46:07.288863 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 23:46:07.289753 setenv serverip 192.168.6.2
1137 23:46:07.290459 Sending with 10 millisecond of delay
1139 23:46:11.020551 => tftpboot 0x01080000 949226/tftp-deploy-neks0fjb/kernel/uImage
1140 23:46:11.031320 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 23:46:11.032216 tftpboot 0x01080000 949226/tftp-deploy-neks0fjb/kernel/uImage
1142 23:46:11.032667 Speed: 1000, full duplex
1143 23:46:11.033066 Using ethernet@ff3f0000 device
1144 23:46:11.033989 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 23:46:11.039571 Filename '949226/tftp-deploy-neks0fjb/kernel/uImage'.
1146 23:46:11.043523 Load address: 0x1080000
1147 23:46:13.905322 Loading: *################################################## 43.6 MiB
1148 23:46:13.905938 15.2 MiB/s
1149 23:46:13.906367 done
1150 23:46:13.909691 Bytes transferred = 45713984 (2b98a40 hex)
1151 23:46:13.910502 Sending with 10 millisecond of delay
1153 23:46:18.599152 => tftpboot 0x08000000 949226/tftp-deploy-neks0fjb/ramdisk/ramdisk.cpio.gz.uboot
1154 23:46:18.609927 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1155 23:46:18.610710 tftpboot 0x08000000 949226/tftp-deploy-neks0fjb/ramdisk/ramdisk.cpio .gz.uboot
1156 23:46:18.611149 Speed: 1000, full duplex
1157 23:46:18.611555 Using ethernet@ff3f0000 device
1158 23:46:18.612639 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 23:46:18.618156 Filename '949226/tftp-deploy-neks0fjb/ramdisk/ramdisk.cpi.gz.uboot'.
1160 23:46:18.623668 Load address: 0x8000000
1161 23:46:18.624182 Loading: *
1162 23:46:18.629105 TFTP error: 'File not found' (1)
1163 23:46:18.629549 Not retrying...
1165 23:46:18.630842 end: 2.4.3 bootloader-commands (duration 00:00:18) [common]
1168 23:46:18.632682 end: 2.4 uboot-commands (duration 00:00:55) [common]
1170 23:46:18.634049 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'File not found' (7)'
1172 23:46:18.635014 end: 2 uboot-action (duration 00:00:55) [common]
1174 23:46:18.636566 Cleaning after the job
1175 23:46:18.637115 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/ramdisk
1176 23:46:18.651733 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/kernel
1177 23:46:18.689019 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/dtb
1178 23:46:18.690034 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/nfsrootfs
1179 23:46:19.013055 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/949226/tftp-deploy-neks0fjb/modules
1180 23:46:19.035475 start: 4.1 power-off (timeout 00:00:30) [common]
1181 23:46:19.036209 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1182 23:46:19.070666 >> OK - accepted request
1183 23:46:19.072776 Returned 0 in 0 seconds
1184 23:46:19.173990 end: 4.1 power-off (duration 00:00:00) [common]
1186 23:46:19.175764 start: 4.2 read-feedback (timeout 00:10:00) [common]
1187 23:46:19.177149 Listened to connection for namespace 'common' for up to 1s
1188 23:46:20.177825 Finalising connection for namespace 'common'
1189 23:46:20.178367 Disconnecting from shell: Finalise
1190 23:46:20.178712 =>
1191 23:46:20.279461 end: 4.2 read-feedback (duration 00:00:01) [common]
1192 23:46:20.280067 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/949226
1193 23:46:23.348668 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/949226
1194 23:46:23.349290 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.