Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 00:40:54.205300 lava-dispatcher, installed at version: 2024.01
2 00:40:54.206123 start: 0 validate
3 00:40:54.206600 Start time: 2024-11-07 00:40:54.206570+00:00 (UTC)
4 00:40:54.207142 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 00:40:54.207693 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 00:40:54.239783 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 00:40:54.240471 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fkernel%2FzImage exists
8 00:40:54.265356 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 00:40:54.266009 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 00:40:54.290525 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 00:40:54.291195 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 00:40:54.314032 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 00:40:54.314544 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fmodules.tar.xz exists
14 00:40:54.344408 validate duration: 0.14
16 00:40:54.345357 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:40:54.345709 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:40:54.346055 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:40:54.346679 Not decompressing ramdisk as can be used compressed.
20 00:40:54.347134 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 00:40:54.347430 saving as /var/lib/lava/dispatcher/tmp/950205/tftp-deploy-duva7m5q/ramdisk/initrd.cpio.gz
22 00:40:54.347708 total size: 4775763 (4 MB)
23 00:40:54.374194 progress 0 % (0 MB)
24 00:40:54.377765 progress 5 % (0 MB)
25 00:40:54.381323 progress 10 % (0 MB)
26 00:40:54.384668 progress 15 % (0 MB)
27 00:40:54.388416 progress 20 % (0 MB)
28 00:40:54.391736 progress 25 % (1 MB)
29 00:40:54.395095 progress 30 % (1 MB)
30 00:40:54.398736 progress 35 % (1 MB)
31 00:40:54.402055 progress 40 % (1 MB)
32 00:40:54.405285 progress 45 % (2 MB)
33 00:40:54.408495 progress 50 % (2 MB)
34 00:40:54.412234 progress 55 % (2 MB)
35 00:40:54.415453 progress 60 % (2 MB)
36 00:40:54.418653 progress 65 % (2 MB)
37 00:40:54.422314 progress 70 % (3 MB)
38 00:40:54.425512 progress 75 % (3 MB)
39 00:40:54.428752 progress 80 % (3 MB)
40 00:40:54.431957 progress 85 % (3 MB)
41 00:40:54.435490 progress 90 % (4 MB)
42 00:40:54.438464 progress 95 % (4 MB)
43 00:40:54.441399 progress 100 % (4 MB)
44 00:40:54.442050 4 MB downloaded in 0.09 s (48.29 MB/s)
45 00:40:54.442621 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:40:54.443516 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:40:54.443830 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:40:54.444120 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:40:54.444694 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm/multi_v7_defconfig/clang-15/kernel/zImage
51 00:40:54.444968 saving as /var/lib/lava/dispatcher/tmp/950205/tftp-deploy-duva7m5q/kernel/zImage
52 00:40:54.445211 total size: 12050944 (11 MB)
53 00:40:54.445436 No compression specified
54 00:40:54.475371 progress 0 % (0 MB)
55 00:40:54.484951 progress 5 % (0 MB)
56 00:40:54.494426 progress 10 % (1 MB)
57 00:40:54.504460 progress 15 % (1 MB)
58 00:40:54.514049 progress 20 % (2 MB)
59 00:40:54.523465 progress 25 % (2 MB)
60 00:40:54.533482 progress 30 % (3 MB)
61 00:40:54.543898 progress 35 % (4 MB)
62 00:40:54.552951 progress 40 % (4 MB)
63 00:40:54.560569 progress 45 % (5 MB)
64 00:40:54.568229 progress 50 % (5 MB)
65 00:40:54.576239 progress 55 % (6 MB)
66 00:40:54.583896 progress 60 % (6 MB)
67 00:40:54.592034 progress 65 % (7 MB)
68 00:40:54.599693 progress 70 % (8 MB)
69 00:40:54.607354 progress 75 % (8 MB)
70 00:40:54.615413 progress 80 % (9 MB)
71 00:40:54.623301 progress 85 % (9 MB)
72 00:40:54.630963 progress 90 % (10 MB)
73 00:40:54.639052 progress 95 % (10 MB)
74 00:40:54.646220 progress 100 % (11 MB)
75 00:40:54.646881 11 MB downloaded in 0.20 s (56.99 MB/s)
76 00:40:54.647370 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:40:54.648198 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:40:54.648478 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:40:54.648743 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:40:54.649228 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
82 00:40:54.649545 saving as /var/lib/lava/dispatcher/tmp/950205/tftp-deploy-duva7m5q/dtb/am335x-boneblack.dtb
83 00:40:54.649757 total size: 70568 (0 MB)
84 00:40:54.649991 No compression specified
85 00:40:54.681312 progress 46 % (0 MB)
86 00:40:54.682188 progress 92 % (0 MB)
87 00:40:54.682900 progress 100 % (0 MB)
88 00:40:54.683293 0 MB downloaded in 0.03 s (2.01 MB/s)
89 00:40:54.683752 end: 1.3.1 http-download (duration 00:00:00) [common]
91 00:40:54.684560 end: 1.3 download-retry (duration 00:00:00) [common]
92 00:40:54.684826 start: 1.4 download-retry (timeout 00:10:00) [common]
93 00:40:54.685089 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 00:40:54.685577 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 00:40:54.685861 saving as /var/lib/lava/dispatcher/tmp/950205/tftp-deploy-duva7m5q/nfsrootfs/full.rootfs.tar
96 00:40:54.686087 total size: 117747780 (112 MB)
97 00:40:54.686306 Using unxz to decompress xz
98 00:40:54.714324 progress 0 % (0 MB)
99 00:40:55.429325 progress 5 % (5 MB)
100 00:40:56.193351 progress 10 % (11 MB)
101 00:40:56.997569 progress 15 % (16 MB)
102 00:40:57.734447 progress 20 % (22 MB)
103 00:40:58.308501 progress 25 % (28 MB)
104 00:40:59.104155 progress 30 % (33 MB)
105 00:40:59.898841 progress 35 % (39 MB)
106 00:41:00.224804 progress 40 % (44 MB)
107 00:41:00.610503 progress 45 % (50 MB)
108 00:41:01.259631 progress 50 % (56 MB)
109 00:41:02.057142 progress 55 % (61 MB)
110 00:41:02.774633 progress 60 % (67 MB)
111 00:41:03.479056 progress 65 % (73 MB)
112 00:41:04.228858 progress 70 % (78 MB)
113 00:41:04.973121 progress 75 % (84 MB)
114 00:41:05.690219 progress 80 % (89 MB)
115 00:41:06.384504 progress 85 % (95 MB)
116 00:41:07.156372 progress 90 % (101 MB)
117 00:41:07.903070 progress 95 % (106 MB)
118 00:41:08.705841 progress 100 % (112 MB)
119 00:41:08.718031 112 MB downloaded in 14.03 s (8.00 MB/s)
120 00:41:08.718584 end: 1.4.1 http-download (duration 00:00:14) [common]
122 00:41:08.719416 end: 1.4 download-retry (duration 00:00:14) [common]
123 00:41:08.719679 start: 1.5 download-retry (timeout 00:09:46) [common]
124 00:41:08.719939 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 00:41:08.720411 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm/multi_v7_defconfig/clang-15/modules.tar.xz
126 00:41:08.720651 saving as /var/lib/lava/dispatcher/tmp/950205/tftp-deploy-duva7m5q/modules/modules.tar
127 00:41:08.720856 total size: 6917716 (6 MB)
128 00:41:08.721064 Using unxz to decompress xz
129 00:41:08.756013 progress 0 % (0 MB)
130 00:41:08.796075 progress 5 % (0 MB)
131 00:41:08.849018 progress 10 % (0 MB)
132 00:41:08.894930 progress 15 % (1 MB)
133 00:41:08.944430 progress 20 % (1 MB)
134 00:41:08.989221 progress 25 % (1 MB)
135 00:41:09.037213 progress 30 % (2 MB)
136 00:41:09.080575 progress 35 % (2 MB)
137 00:41:09.128101 progress 40 % (2 MB)
138 00:41:09.175532 progress 45 % (3 MB)
139 00:41:09.218688 progress 50 % (3 MB)
140 00:41:09.265077 progress 55 % (3 MB)
141 00:41:09.310398 progress 60 % (3 MB)
142 00:41:09.355969 progress 65 % (4 MB)
143 00:41:09.400443 progress 70 % (4 MB)
144 00:41:09.450095 progress 75 % (4 MB)
145 00:41:09.492517 progress 80 % (5 MB)
146 00:41:09.540102 progress 85 % (5 MB)
147 00:41:09.587495 progress 90 % (5 MB)
148 00:41:09.630067 progress 95 % (6 MB)
149 00:41:09.677683 progress 100 % (6 MB)
150 00:41:09.688055 6 MB downloaded in 0.97 s (6.82 MB/s)
151 00:41:09.688899 end: 1.5.1 http-download (duration 00:00:01) [common]
153 00:41:09.690525 end: 1.5 download-retry (duration 00:00:01) [common]
154 00:41:09.691054 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 00:41:09.691569 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 00:41:26.131654 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/950205/extract-nfsrootfs-q0ttwdzb
157 00:41:26.132251 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 00:41:26.132538 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 00:41:26.133287 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj
160 00:41:26.133772 makedir: /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin
161 00:41:26.134181 makedir: /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/tests
162 00:41:26.134512 makedir: /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/results
163 00:41:26.134846 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-add-keys
164 00:41:26.135370 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-add-sources
165 00:41:26.135883 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-background-process-start
166 00:41:26.136413 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-background-process-stop
167 00:41:26.137052 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-common-functions
168 00:41:26.137582 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-echo-ipv4
169 00:41:26.138111 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-install-packages
170 00:41:26.138606 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-installed-packages
171 00:41:26.139087 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-os-build
172 00:41:26.139570 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-probe-channel
173 00:41:26.140072 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-probe-ip
174 00:41:26.140573 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-target-ip
175 00:41:26.141053 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-target-mac
176 00:41:26.141530 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-target-storage
177 00:41:26.142052 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-test-case
178 00:41:26.142578 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-test-event
179 00:41:26.143084 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-test-feedback
180 00:41:26.143569 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-test-raise
181 00:41:26.144047 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-test-reference
182 00:41:26.144526 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-test-runner
183 00:41:26.145038 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-test-set
184 00:41:26.145527 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-test-shell
185 00:41:26.146134 Updating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-add-keys (debian)
186 00:41:26.146703 Updating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-add-sources (debian)
187 00:41:26.147217 Updating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-install-packages (debian)
188 00:41:26.147734 Updating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-installed-packages (debian)
189 00:41:26.148236 Updating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/bin/lava-os-build (debian)
190 00:41:26.148679 Creating /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/environment
191 00:41:26.149064 LAVA metadata
192 00:41:26.149336 - LAVA_JOB_ID=950205
193 00:41:26.149553 - LAVA_DISPATCHER_IP=192.168.6.3
194 00:41:26.149937 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 00:41:26.150895 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 00:41:26.151206 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 00:41:26.151410 skipped lava-vland-overlay
198 00:41:26.151648 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 00:41:26.151900 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 00:41:26.152099 skipped lava-multinode-overlay
201 00:41:26.152335 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 00:41:26.152584 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 00:41:26.152827 Loading test definitions
204 00:41:26.153107 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 00:41:26.153363 Using /lava-950205 at stage 0
206 00:41:26.154498 uuid=950205_1.6.2.4.1 testdef=None
207 00:41:26.154803 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 00:41:26.155064 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 00:41:26.156615 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 00:41:26.157407 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 00:41:26.159419 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 00:41:26.160243 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 00:41:26.162081 runner path: /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/0/tests/0_timesync-off test_uuid 950205_1.6.2.4.1
216 00:41:26.162652 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 00:41:26.163462 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 00:41:26.163685 Using /lava-950205 at stage 0
220 00:41:26.164038 Fetching tests from https://github.com/kernelci/test-definitions.git
221 00:41:26.164328 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/0/tests/1_kselftest-dt'
222 00:41:29.785143 Running '/usr/bin/git checkout kernelci.org
223 00:41:30.232458 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 00:41:30.234992 uuid=950205_1.6.2.4.5 testdef=None
225 00:41:30.235597 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 00:41:30.237039 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 00:41:30.242421 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 00:41:30.243991 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 00:41:30.251204 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 00:41:30.252840 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 00:41:30.259854 runner path: /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/0/tests/1_kselftest-dt test_uuid 950205_1.6.2.4.5
235 00:41:30.260405 BOARD='beaglebone-black'
236 00:41:30.260816 BRANCH='mainline'
237 00:41:30.261207 SKIPFILE='/dev/null'
238 00:41:30.261596 SKIP_INSTALL='True'
239 00:41:30.262024 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
240 00:41:30.262428 TST_CASENAME=''
241 00:41:30.262812 TST_CMDFILES='dt'
242 00:41:30.263789 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 00:41:30.265305 Creating lava-test-runner.conf files
245 00:41:30.265701 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950205/lava-overlay-gv73l4kj/lava-950205/0 for stage 0
246 00:41:30.266373 - 0_timesync-off
247 00:41:30.266824 - 1_kselftest-dt
248 00:41:30.267441 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 00:41:30.267972 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 00:41:53.648092 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 00:41:53.648547 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 00:41:53.648847 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 00:41:53.649161 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 00:41:53.649457 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 00:41:54.066543 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 00:41:54.067306 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 00:41:54.067579 extracting modules file /var/lib/lava/dispatcher/tmp/950205/tftp-deploy-duva7m5q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950205/extract-nfsrootfs-q0ttwdzb
258 00:41:54.977916 extracting modules file /var/lib/lava/dispatcher/tmp/950205/tftp-deploy-duva7m5q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950205/extract-overlay-ramdisk-m9xbb5dd/ramdisk
259 00:41:55.933544 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 00:41:55.934057 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 00:41:55.934344 [common] Applying overlay to NFS
262 00:41:55.934564 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950205/compress-overlay-psq3vhcx/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950205/extract-nfsrootfs-q0ttwdzb
263 00:41:58.737155 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 00:41:58.737636 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 00:41:58.737942 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 00:41:58.738215 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 00:41:58.738462 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 00:41:58.738712 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 00:41:58.738953 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 00:41:58.739204 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 00:41:58.739423 Building ramdisk /var/lib/lava/dispatcher/tmp/950205/extract-overlay-ramdisk-m9xbb5dd/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950205/extract-overlay-ramdisk-m9xbb5dd/ramdisk
272 00:41:59.818266 >> 79012 blocks
273 00:42:04.913434 Adding RAMdisk u-boot header.
274 00:42:04.913982 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950205/extract-overlay-ramdisk-m9xbb5dd/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950205/extract-overlay-ramdisk-m9xbb5dd/ramdisk.cpio.gz.uboot
275 00:42:05.077215 output: Image Name:
276 00:42:05.077615 output: Created: Thu Nov 7 00:42:04 2024
277 00:42:05.077853 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 00:42:05.078306 output: Data Size: 15350309 Bytes = 14990.54 KiB = 14.64 MiB
279 00:42:05.078746 output: Load Address: 00000000
280 00:42:05.079179 output: Entry Point: 00000000
281 00:42:05.079609 output:
282 00:42:05.080804 rename /var/lib/lava/dispatcher/tmp/950205/extract-overlay-ramdisk-m9xbb5dd/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950205/tftp-deploy-duva7m5q/ramdisk/ramdisk.cpio.gz.uboot
283 00:42:05.081569 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 00:42:05.082194 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 00:42:05.082764 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 00:42:05.083258 No LXC device requested
287 00:42:05.083799 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 00:42:05.084343 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 00:42:05.084877 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 00:42:05.085322 Checking files for TFTP limit of 4294967296 bytes.
291 00:42:05.088225 end: 1 tftp-deploy (duration 00:01:11) [common]
292 00:42:05.088851 start: 2 uboot-action (timeout 00:05:00) [common]
293 00:42:05.089412 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 00:42:05.089978 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 00:42:05.090518 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 00:42:05.091463 substitutions:
297 00:42:05.091929 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 00:42:05.092407 - {DTB_ADDR}: 0x88000000
299 00:42:05.092844 - {DTB}: 950205/tftp-deploy-duva7m5q/dtb/am335x-boneblack.dtb
300 00:42:05.093274 - {INITRD}: 950205/tftp-deploy-duva7m5q/ramdisk/ramdisk.cpio.gz.uboot
301 00:42:05.093749 - {KERNEL_ADDR}: 0x82000000
302 00:42:05.094238 - {KERNEL}: 950205/tftp-deploy-duva7m5q/kernel/zImage
303 00:42:05.094677 - {LAVA_MAC}: None
304 00:42:05.095126 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/950205/extract-nfsrootfs-q0ttwdzb
305 00:42:05.095555 - {NFS_SERVER_IP}: 192.168.6.3
306 00:42:05.095980 - {PRESEED_CONFIG}: None
307 00:42:05.096404 - {PRESEED_LOCAL}: None
308 00:42:05.096826 - {RAMDISK_ADDR}: 0x83000000
309 00:42:05.097248 - {RAMDISK}: 950205/tftp-deploy-duva7m5q/ramdisk/ramdisk.cpio.gz.uboot
310 00:42:05.097677 - {ROOT_PART}: None
311 00:42:05.098126 - {ROOT}: None
312 00:42:05.098546 - {SERVER_IP}: 192.168.6.3
313 00:42:05.098963 - {TEE_ADDR}: 0x83000000
314 00:42:05.099378 - {TEE}: None
315 00:42:05.099794 Parsed boot commands:
316 00:42:05.100197 - setenv autoload no
317 00:42:05.100612 - setenv initrd_high 0xffffffff
318 00:42:05.101028 - setenv fdt_high 0xffffffff
319 00:42:05.101441 - dhcp
320 00:42:05.101874 - setenv serverip 192.168.6.3
321 00:42:05.102294 - tftp 0x82000000 950205/tftp-deploy-duva7m5q/kernel/zImage
322 00:42:05.102711 - tftp 0x83000000 950205/tftp-deploy-duva7m5q/ramdisk/ramdisk.cpio.gz.uboot
323 00:42:05.103132 - setenv initrd_size ${filesize}
324 00:42:05.103545 - tftp 0x88000000 950205/tftp-deploy-duva7m5q/dtb/am335x-boneblack.dtb
325 00:42:05.103960 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/950205/extract-nfsrootfs-q0ttwdzb,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 00:42:05.104389 - bootz 0x82000000 0x83000000 0x88000000
327 00:42:05.104929 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 00:42:05.106570 start: 2.3 connect-device (timeout 00:05:00) [common]
330 00:42:05.107022 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 00:42:05.121559 Setting prompt string to ['lava-test: # ']
332 00:42:05.123790 end: 2.3 connect-device (duration 00:00:00) [common]
333 00:42:05.124536 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 00:42:05.125154 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 00:42:05.125736 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 00:42:05.127226 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 00:42:05.169490 >> OK - accepted request
338 00:42:05.171741 Returned 0 in 0 seconds
339 00:42:05.272866 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 00:42:05.273890 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 00:42:05.274229 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 00:42:05.274543 Setting prompt string to ['Hit any key to stop autoboot']
344 00:42:05.274832 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 00:42:05.276032 Trying 192.168.56.22...
346 00:42:05.276363 Connected to conserv3.
347 00:42:05.276622 Escape character is '^]'.
348 00:42:05.276861
349 00:42:05.277095 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 00:42:05.277309
351 00:42:13.969506
352 00:42:13.975840 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 00:42:13.976406 Trying to boot from MMC1
354 00:42:18.032400
355 00:42:18.039275 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 00:42:18.039886 Trying to boot from MMC1
357 00:42:20.728569
358 00:42:20.735340 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 00:42:20.735609 Trying to boot from MMC1
360 00:42:21.319572
361 00:42:21.320248
362 00:42:21.325133 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 00:42:21.325684
364 00:42:21.326204 CPU : AM335X-GP rev 2.0
365 00:42:21.330319 Model: TI AM335x BeagleBone Black
366 00:42:21.330863 DRAM: 512 MiB
367 00:42:21.410178 Core: 160 devices, 18 uclasses, devicetree: separate
368 00:42:21.424058 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 00:42:21.824828 NAND: 0 MiB
370 00:42:21.835084 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 00:42:21.962780 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 00:42:21.984036 <ethaddr> not set. Validating first E-fuse MAC
373 00:42:22.014486 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 00:42:22.072937 Hit any key to stop autoboot: 2
376 00:42:22.073962 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
377 00:42:22.074340 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
378 00:42:22.074634 Setting prompt string to ['=>']
379 00:42:22.074899 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
380 00:42:22.082860 0
381 00:42:22.083566 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 00:42:22.083899 Sending with 10 millisecond of delay
384 00:42:23.222395 => setenv autoload no
385 00:42:23.233039 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
386 00:42:23.235926 setenv autoload no
387 00:42:23.236488 Sending with 10 millisecond of delay
389 00:42:25.033555 => setenv initrd_high 0xffffffff
390 00:42:25.044181 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
391 00:42:25.044741 setenv initrd_high 0xffffffff
392 00:42:25.045213 Sending with 10 millisecond of delay
394 00:42:26.662654 => setenv fdt_high 0xffffffff
395 00:42:26.673410 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
396 00:42:26.674405 setenv fdt_high 0xffffffff
397 00:42:26.675036 Sending with 10 millisecond of delay
399 00:42:26.966670 => dhcp
400 00:42:26.977249 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
401 00:42:26.977844 dhcp
402 00:42:26.979895 link up on port 0, speed 100, full duplex
403 00:42:26.980170 BOOTP broadcast 1
404 00:42:27.232086 BOOTP broadcast 2
405 00:42:27.734049 BOOTP broadcast 3
406 00:42:28.736144 BOOTP broadcast 4
407 00:42:30.737988 BOOTP broadcast 5
408 00:42:31.034970 DHCP client bound to address 192.168.6.8 (4052 ms)
409 00:42:31.035829 Sending with 10 millisecond of delay
411 00:42:32.714905 => setenv serverip 192.168.6.3
412 00:42:32.725548 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
413 00:42:32.726333 setenv serverip 192.168.6.3
414 00:42:32.726933 Sending with 10 millisecond of delay
416 00:42:36.209912 => tftp 0x82000000 950205/tftp-deploy-duva7m5q/kernel/zImage
417 00:42:36.220729 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
418 00:42:36.221635 tftp 0x82000000 950205/tftp-deploy-duva7m5q/kernel/zImage
419 00:42:36.222100 link up on port 0, speed 100, full duplex
420 00:42:36.225531 Using ethernet@4a100000 device
421 00:42:36.231962 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
422 00:42:36.232412 Filename '950205/tftp-deploy-duva7m5q/kernel/zImage'.
423 00:42:36.238396 Load address: 0x82000000
424 00:42:38.515697 Loading: *################################################## 11.5 MiB
425 00:42:38.516347 5 MiB/s
426 00:42:38.516820 done
427 00:42:38.519742 Bytes transferred = 12050944 (b7e200 hex)
428 00:42:38.520556 Sending with 10 millisecond of delay
430 00:42:42.966714 => tftp 0x83000000 950205/tftp-deploy-duva7m5q/ramdisk/ramdisk.cpio.gz.uboot
431 00:42:42.977546 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
432 00:42:42.978549 tftp 0x83000000 950205/tftp-deploy-duva7m5q/ramdisk/ramdisk.cpio.gz.uboot
433 00:42:42.979021 link up on port 0, speed 100, full duplex
434 00:42:42.982673 Using ethernet@4a100000 device
435 00:42:42.988244 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
436 00:42:42.991654 Filename '950205/tftp-deploy-duva7m5q/ramdisk/ramdisk.cpio.gz.uboot'.
437 00:42:42.996560 Load address: 0x83000000
438 00:42:45.909416 Loading: *################################################## 14.6 MiB
439 00:42:45.909886 5 MiB/s
440 00:42:45.910128 done
441 00:42:45.912669 Bytes transferred = 15350373 (ea3a65 hex)
442 00:42:45.913226 Sending with 10 millisecond of delay
444 00:42:47.770541 => setenv initrd_size ${filesize}
445 00:42:47.781344 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
446 00:42:47.782275 setenv initrd_size ${filesize}
447 00:42:47.783038 Sending with 10 millisecond of delay
449 00:42:51.930990 => tftp 0x88000000 950205/tftp-deploy-duva7m5q/dtb/am335x-boneblack.dtb
450 00:42:51.941786 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
451 00:42:51.942671 tftp 0x88000000 950205/tftp-deploy-duva7m5q/dtb/am335x-boneblack.dtb
452 00:42:51.943141 link up on port 0, speed 100, full duplex
453 00:42:51.946417 Using ethernet@4a100000 device
454 00:42:51.952143 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
455 00:42:51.962746 Filename '950205/tftp-deploy-duva7m5q/dtb/am335x-boneblack.dtb'.
456 00:42:51.963249 Load address: 0x88000000
457 00:42:51.972698 Loading: *################################################## 68.9 KiB
458 00:42:51.973232 4.8 MiB/s
459 00:42:51.981300 done
460 00:42:51.981869 Bytes transferred = 70568 (113a8 hex)
461 00:42:51.982659 Sending with 10 millisecond of delay
463 00:43:05.166915 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/950205/extract-nfsrootfs-q0ttwdzb,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
464 00:43:05.177693 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
465 00:43:05.178616 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/950205/extract-nfsrootfs-q0ttwdzb,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
466 00:43:05.179333 Sending with 10 millisecond of delay
468 00:43:07.518013 => bootz 0x82000000 0x83000000 0x88000000
469 00:43:07.528817 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
470 00:43:07.529367 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
471 00:43:07.530408 bootz 0x82000000 0x83000000 0x88000000
472 00:43:07.530887 Kernel image @ 0x82000000 [ 0x000000 - 0xb7e200 ]
473 00:43:07.531394 ## Loading init Ramdisk from Legacy Image at 83000000 ...
474 00:43:07.536342 Image Name:
475 00:43:07.536828 Created: 2024-11-07 0:42:04 UTC
476 00:43:07.541925 Image Type: ARM Linux RAMDisk Image (uncompressed)
477 00:43:07.547487 Data Size: 15350309 Bytes = 14.6 MiB
478 00:43:07.547948 Load Address: 00000000
479 00:43:07.553630 Entry Point: 00000000
480 00:43:07.728089 Verifying Checksum ... OK
481 00:43:07.728605 ## Flattened Device Tree blob at 88000000
482 00:43:07.734668 Booting using the fdt blob at 0x88000000
483 00:43:07.735136 Working FDT set to 88000000
484 00:43:07.740238 Using Device Tree in place at 88000000, end 880143a7
485 00:43:07.744624 Working FDT set to 88000000
486 00:43:07.758208
487 00:43:07.758689 Starting kernel ...
488 00:43:07.759100
489 00:43:07.759966 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
490 00:43:07.760537 start: 2.4.4 auto-login-action (timeout 00:03:57) [common]
491 00:43:07.761009 Setting prompt string to ['Linux version [0-9]']
492 00:43:07.761462 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
493 00:43:07.761965 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
494 00:43:08.649337 [ 0.000000] Booting Linux on physical CPU 0x0
495 00:43:08.655319 start: 2.4.4.1 login-action (timeout 00:03:56) [common]
496 00:43:08.655676 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
497 00:43:08.655934 Setting prompt string to []
498 00:43:08.656201 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
499 00:43:08.656446 Using line separator: #'\n'#
500 00:43:08.656656 No login prompt set.
501 00:43:08.656896 Parsing kernel messages
502 00:43:08.657106 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
503 00:43:08.657548 [login-action] Waiting for messages, (timeout 00:03:56)
504 00:43:08.657846 Waiting using forced prompt support (timeout 00:01:58)
505 00:43:08.666387 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j365863-arm-clang-15-multi-v7-defconfig-nwl9z) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Wed Nov 6 23:52:17 UTC 2024
506 00:43:08.672065 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
507 00:43:08.683530 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
508 00:43:08.689205 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
509 00:43:08.694938 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
510 00:43:08.700689 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
511 00:43:08.707475 [ 0.000000] Memory policy: Data cache writeback
512 00:43:08.707761 [ 0.000000] efi: UEFI not found.
513 00:43:08.715103 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
514 00:43:08.720792 [ 0.000000] Zone ranges:
515 00:43:08.726537 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
516 00:43:08.732298 [ 0.000000] Normal empty
517 00:43:08.732594 [ 0.000000] HighMem empty
518 00:43:08.737983 [ 0.000000] Movable zone start for each node
519 00:43:08.738373 [ 0.000000] Early memory node ranges
520 00:43:08.749486 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
521 00:43:08.754806 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
522 00:43:08.772998 [ 0.000000] CPU: All CPU(s) started in SVC mode.
523 00:43:08.777790 [ 0.000000] AM335X ES2.0 (sgx neon)
524 00:43:08.790612 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
525 00:43:08.808270 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/950205/extract-nfsrootfs-q0ttwdzb,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
526 00:43:08.819804 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
527 00:43:08.825559 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
528 00:43:08.831356 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
529 00:43:08.841366 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
530 00:43:08.870679 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
531 00:43:08.876659 <6>[ 0.000000] trace event string verifier disabled
532 00:43:08.877116 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
533 00:43:08.882481 <6>[ 0.000000] rcu: RCU event tracing is enabled.
534 00:43:08.893991 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
535 00:43:08.899664 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
536 00:43:08.906933 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
537 00:43:08.922246 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
538 00:43:08.940607 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
539 00:43:08.947285 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
540 00:43:09.050617 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
541 00:43:09.062084 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
542 00:43:09.068907 <6>[ 0.008339] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
543 00:43:09.082020 <6>[ 0.019248] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
544 00:43:09.089930 <6>[ 0.034617] Console: colour dummy device 80x30
545 00:43:09.096070 Matched prompt #6: WARNING:
546 00:43:09.096559 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
547 00:43:09.101420 <3>[ 0.039615] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
548 00:43:09.107197 <3>[ 0.046603] This ensures that you still see kernel messages. Please
549 00:43:09.110412 <3>[ 0.053329] update your kernel commandline.
550 00:43:09.150403 <6>[ 0.057945] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
551 00:43:09.156162 <6>[ 0.096262] CPU: Testing write buffer coherency: ok
552 00:43:09.158974 <6>[ 0.101634] CPU0: Spectre v2: using BPIALL workaround
553 00:43:09.164901 <6>[ 0.107102] pid_max: default: 32768 minimum: 301
554 00:43:09.170649 <6>[ 0.112300] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
555 00:43:09.183318 <6>[ 0.120124] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
556 00:43:09.190549 <6>[ 0.129564] CPU0: thread -1, cpu 0, socket -1, mpidr 0
557 00:43:09.199054 <6>[ 0.136533] Setting up static identity map for 0x80300000 - 0x803000ac
558 00:43:09.204851 <6>[ 0.146377] rcu: Hierarchical SRCU implementation.
559 00:43:09.209712 <6>[ 0.151662] rcu: Max phase no-delay instances is 1000.
560 00:43:09.218785 <6>[ 0.163337] EFI services will not be available.
561 00:43:09.224656 <6>[ 0.168630] smp: Bringing up secondary CPUs ...
562 00:43:09.230390 <6>[ 0.173693] smp: Brought up 1 node, 1 CPU
563 00:43:09.238589 <6>[ 0.178094] SMP: Total of 1 processors activated (996.14 BogoMIPS).
564 00:43:09.244576 <6>[ 0.184868] CPU: All CPU(s) started in SVC mode.
565 00:43:09.256784 <6>[ 0.190072] Memory: 404432K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50616K reserved, 65536K cma-reserved, 0K highmem)
566 00:43:09.262551 <6>[ 0.206353] devtmpfs: initialized
567 00:43:09.285782 <6>[ 0.224372] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
568 00:43:09.297277 <6>[ 0.233000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
569 00:43:09.303248 <6>[ 0.243459] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
570 00:43:09.314014 <6>[ 0.255769] pinctrl core: initialized pinctrl subsystem
571 00:43:09.323735 <6>[ 0.266845] DMI not present or invalid.
572 00:43:09.332168 <6>[ 0.272746] NET: Registered PF_NETLINK/PF_ROUTE protocol family
573 00:43:09.341670 <6>[ 0.281740] DMA: preallocated 256 KiB pool for atomic coherent allocations
574 00:43:09.357052 <6>[ 0.293491] thermal_sys: Registered thermal governor 'step_wise'
575 00:43:09.357591 <6>[ 0.293687] cpuidle: using governor menu
576 00:43:09.384676 <6>[ 0.329315] No ATAGs?
577 00:43:09.390906 <6>[ 0.332059] hw-breakpoint: debug architecture 0x4 unsupported.
578 00:43:09.401383 <6>[ 0.344351] Serial: AMBA PL011 UART driver
579 00:43:09.431364 <6>[ 0.375996] iommu: Default domain type: Translated
580 00:43:09.440501 <6>[ 0.381351] iommu: DMA domain TLB invalidation policy: strict mode
581 00:43:09.467193 <5>[ 0.410492] SCSI subsystem initialized
582 00:43:09.481031 <6>[ 0.420089] usbcore: registered new interface driver usbfs
583 00:43:09.488008 <6>[ 0.426056] usbcore: registered new interface driver hub
584 00:43:09.488542 <6>[ 0.431885] usbcore: registered new device driver usb
585 00:43:09.495510 <6>[ 0.438440] pps_core: LinuxPPS API ver. 1 registered
586 00:43:09.506988 <6>[ 0.443880] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
587 00:43:09.514193 <6>[ 0.453606] PTP clock support registered
588 00:43:09.514717 <6>[ 0.458060] EDAC MC: Ver: 3.0.0
589 00:43:09.568851 <6>[ 0.510603] scmi_core: SCMI protocol bus registered
590 00:43:09.573572 <6>[ 0.518800] vgaarb: loaded
591 00:43:09.586826 <6>[ 0.531544] clocksource: Switched to clocksource dmtimer
592 00:43:09.614510 <6>[ 0.558806] NET: Registered PF_INET protocol family
593 00:43:09.627241 <6>[ 0.564545] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
594 00:43:09.633111 <6>[ 0.573569] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
595 00:43:09.644488 <6>[ 0.582505] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
596 00:43:09.650347 <6>[ 0.590747] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
597 00:43:09.661896 <6>[ 0.599035] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
598 00:43:09.667788 <6>[ 0.606755] TCP: Hash tables configured (established 4096 bind 4096)
599 00:43:09.673510 <6>[ 0.613673] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
600 00:43:09.679427 <6>[ 0.620683] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
601 00:43:09.687004 <6>[ 0.628293] NET: Registered PF_UNIX/PF_LOCAL protocol family
602 00:43:09.779912 <6>[ 0.718905] RPC: Registered named UNIX socket transport module.
603 00:43:09.780433 <6>[ 0.725353] RPC: Registered udp transport module.
604 00:43:09.785855 <6>[ 0.730461] RPC: Registered tcp transport module.
605 00:43:09.791479 <6>[ 0.735590] RPC: Registered tcp-with-tls transport module.
606 00:43:09.804487 <6>[ 0.741515] RPC: Registered tcp NFSv4.1 backchannel transport module.
607 00:43:09.804996 <6>[ 0.748427] PCI: CLS 0 bytes, default 64
608 00:43:09.811269 <5>[ 0.754286] Initialise system trusted keyrings
609 00:43:09.833695 <6>[ 0.775330] Trying to unpack rootfs image as initramfs...
610 00:43:09.893514 <6>[ 0.831935] workingset: timestamp_bits=30 max_order=17 bucket_order=0
611 00:43:09.898397 <6>[ 0.839465] squashfs: version 4.0 (2009/01/31) Phillip Lougher
612 00:43:09.937710 <5>[ 0.882256] NFS: Registering the id_resolver key type
613 00:43:09.943606 <5>[ 0.887855] Key type id_resolver registered
614 00:43:09.949360 <5>[ 0.892546] Key type id_legacy registered
615 00:43:09.955137 <6>[ 0.896984] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
616 00:43:09.964697 <6>[ 0.904202] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
617 00:43:10.035724 <5>[ 0.980284] Key type asymmetric registered
618 00:43:10.041605 <5>[ 0.984861] Asymmetric key parser 'x509' registered
619 00:43:10.050074 <6>[ 0.990300] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
620 00:43:10.055823 <6>[ 0.998225] io scheduler mq-deadline registered
621 00:43:10.064552 <6>[ 1.003176] io scheduler kyber registered
622 00:43:10.065064 <6>[ 1.007631] io scheduler bfq registered
623 00:43:10.160923 <6>[ 1.101773] ledtrig-cpu: registered to indicate activity on CPUs
624 00:43:10.469092 <6>[ 1.409626] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
625 00:43:10.505693 <6>[ 1.449873] msm_serial: driver initialized
626 00:43:10.511604 <6>[ 1.454907] SuperH (H)SCI(F) driver initialized
627 00:43:10.517559 <6>[ 1.460044] STMicroelectronics ASC driver initialized
628 00:43:10.522860 <6>[ 1.465701] STM32 USART driver initialized
629 00:43:10.628438 <6>[ 1.572396] brd: module loaded
630 00:43:10.670768 <6>[ 1.614625] loop: module loaded
631 00:43:10.706153 <6>[ 1.649759] CAN device driver interface
632 00:43:10.712842 <6>[ 1.655075] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
633 00:43:10.718635 <6>[ 1.662175] e1000e: Intel(R) PRO/1000 Network Driver
634 00:43:10.724459 <6>[ 1.667565] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
635 00:43:10.730234 <6>[ 1.674048] igb: Intel(R) Gigabit Ethernet Network Driver
636 00:43:10.738518 <6>[ 1.679872] igb: Copyright (c) 2007-2014 Intel Corporation.
637 00:43:10.750182 <6>[ 1.689139] pegasus: Pegasus/Pegasus II USB Ethernet driver
638 00:43:10.756139 <6>[ 1.695308] usbcore: registered new interface driver pegasus
639 00:43:10.758920 <6>[ 1.701434] usbcore: registered new interface driver asix
640 00:43:10.764630 <6>[ 1.707325] usbcore: registered new interface driver ax88179_178a
641 00:43:10.770344 <6>[ 1.713918] usbcore: registered new interface driver cdc_ether
642 00:43:10.776145 <6>[ 1.720217] usbcore: registered new interface driver smsc75xx
643 00:43:10.784880 <6>[ 1.726458] usbcore: registered new interface driver smsc95xx
644 00:43:10.790611 <6>[ 1.732699] usbcore: registered new interface driver net1080
645 00:43:10.796391 <6>[ 1.738819] usbcore: registered new interface driver cdc_subset
646 00:43:10.802120 <6>[ 1.745242] usbcore: registered new interface driver zaurus
647 00:43:10.809931 <6>[ 1.751287] usbcore: registered new interface driver cdc_ncm
648 00:43:10.819692 <6>[ 1.760725] usbcore: registered new interface driver usb-storage
649 00:43:10.829083 <6>[ 1.771848] i2c_dev: i2c /dev entries driver
650 00:43:10.853154 <5>[ 1.789859] cpuidle: enable-method property 'ti,am3352' found operations
651 00:43:10.859083 <6>[ 1.799409] sdhci: Secure Digital Host Controller Interface driver
652 00:43:10.866592 <6>[ 1.806173] sdhci: Copyright(c) Pierre Ossman
653 00:43:10.873632 <6>[ 1.812701] Synopsys Designware Multimedia Card Interface Driver
654 00:43:10.879163 <6>[ 1.820474] sdhci-pltfm: SDHCI platform and OF driver helper
655 00:43:10.892879 <6>[ 1.830343] usbcore: registered new interface driver usbhid
656 00:43:10.893391 <6>[ 1.836461] usbhid: USB HID core driver
657 00:43:10.905999 <6>[ 1.847983] NET: Registered PF_INET6 protocol family
658 00:43:11.368195 <6>[ 2.312880] Segment Routing with IPv6
659 00:43:11.373891 <6>[ 2.317031] In-situ OAM (IOAM) with IPv6
660 00:43:11.380726 <6>[ 2.321428] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
661 00:43:11.386501 <6>[ 2.328896] NET: Registered PF_PACKET protocol family
662 00:43:11.392340 <6>[ 2.334485] can: controller area network core
663 00:43:11.398158 <6>[ 2.339315] NET: Registered PF_CAN protocol family
664 00:43:11.398477 <6>[ 2.344547] can: raw protocol
665 00:43:11.404023 <6>[ 2.347875] can: broadcast manager protocol
666 00:43:11.410386 <6>[ 2.352472] can: netlink gateway - max_hops=1
667 00:43:11.416619 <5>[ 2.357970] Key type dns_resolver registered
668 00:43:11.422862 <6>[ 2.363049] ThumbEE CPU extension supported.
669 00:43:11.423173 <5>[ 2.367755] Registering SWP/SWPB emulation handler
670 00:43:11.432599 <3>[ 2.373467] omap_voltage_late_init: Voltage driver support not added
671 00:43:11.646617 <5>[ 2.588918] Loading compiled-in X.509 certificates
672 00:43:11.789362 <6>[ 2.721123] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
673 00:43:11.796587 <6>[ 2.737852] pinctrl-single 44e10800.pinmux: 142 pins, size 568
674 00:43:11.823620 <3>[ 2.762314] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
675 00:43:12.013856 <3>[ 2.952540] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
676 00:43:12.219017 <6>[ 3.161997] OMAP GPIO hardware version 0.1
677 00:43:12.240089 <6>[ 3.181094] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
678 00:43:12.333044 <4>[ 3.273651] at24 2-0054: supply vcc not found, using dummy regulator
679 00:43:12.364672 <4>[ 3.305433] at24 2-0055: supply vcc not found, using dummy regulator
680 00:43:12.406282 <4>[ 3.346948] at24 2-0056: supply vcc not found, using dummy regulator
681 00:43:12.445773 <4>[ 3.386566] at24 2-0057: supply vcc not found, using dummy regulator
682 00:43:12.484035 <6>[ 3.425612] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
683 00:43:12.541345 <3>[ 3.478977] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
684 00:43:12.566478 <6>[ 3.500279] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
685 00:43:12.587957 <4>[ 3.527411] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
686 00:43:12.602618 <4>[ 3.542202] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
687 00:43:12.691258 <6>[ 3.632063] omap_rng 48310000.rng: Random Number Generator ver. 20
688 00:43:12.715582 <5>[ 3.659237] random: crng init done
689 00:43:12.760006 <6>[ 3.704618] Freeing initrd memory: 14992K
690 00:43:12.769885 <6>[ 3.709249] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
691 00:43:12.825566 <6>[ 3.764018] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
692 00:43:12.831450 <6>[ 3.774374] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
693 00:43:12.839554 <6>[ 3.781724] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
694 00:43:12.851082 <6>[ 3.789185] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
695 00:43:12.859520 <6>[ 3.797320] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
696 00:43:12.872683 <6>[ 3.808967] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
697 00:43:12.881193 <5>[ 3.818089] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
698 00:43:12.909659 <3>[ 3.848630] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
699 00:43:12.915468 <6>[ 3.857232] edma 49000000.dma: TI EDMA DMA engine driver
700 00:43:12.988737 <3>[ 3.927053] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
701 00:43:13.003853 <6>[ 3.941785] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
702 00:43:13.016977 <3>[ 3.959062] l3-aon-clkctrl:0000:0: failed to disable
703 00:43:13.071579 <6>[ 4.010451] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
704 00:43:13.077284 <6>[ 4.019974] printk: legacy console [ttyS0] enabled
705 00:43:13.083002 <6>[ 4.019974] printk: legacy console [ttyS0] enabled
706 00:43:13.088646 <6>[ 4.030322] printk: legacy bootconsole [omap8250] disabled
707 00:43:13.094541 <6>[ 4.030322] printk: legacy bootconsole [omap8250] disabled
708 00:43:13.124442 <4>[ 4.062374] tps65217-pmic: Failed to locate of_node [id: -1]
709 00:43:13.128071 <4>[ 4.069786] tps65217-bl: Failed to locate of_node [id: -1]
710 00:43:13.145090 <6>[ 4.090052] tps65217 0-0024: TPS65217 ID 0xe version 1.2
711 00:43:13.163581 <6>[ 4.097067] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
712 00:43:13.175341 <6>[ 4.110774] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
713 00:43:13.181080 <6>[ 4.122743] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
714 00:43:13.203762 <6>[ 4.143054] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
715 00:43:13.209674 <6>[ 4.152212] sdhci-omap 48060000.mmc: Got CD GPIO
716 00:43:13.217752 <4>[ 4.157359] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
717 00:43:13.232627 <4>[ 4.171210] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
718 00:43:13.239253 <4>[ 4.179931] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
719 00:43:13.248974 <4>[ 4.188668] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
720 00:43:13.323303 <6>[ 4.263582] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
721 00:43:13.369941 <6>[ 4.307942] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
722 00:43:13.376546 <6>[ 4.317356] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
723 00:43:13.385627 <6>[ 4.326354] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
724 00:43:13.448140 <6>[ 4.389900] mmc1: new high speed MMC card at address 0001
725 00:43:13.455980 <6>[ 4.398695] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
726 00:43:13.476709 <6>[ 4.413366] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
727 00:43:13.483661 <6>[ 4.426964] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
728 00:43:13.497904 <6>[ 4.441741] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
729 00:43:13.504901 <6>[ 4.447942] mmc0: new high speed SDHC card at address aaaa
730 00:43:13.511405 <6>[ 4.455183] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
731 00:43:13.521604 <6>[ 4.462917] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
732 00:43:13.542806 <6>[ 4.485526] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
733 00:43:15.573651 <6>[ 6.512620] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
734 00:43:15.686959 <5>[ 6.551550] Sending DHCP requests ., OK
735 00:43:15.698296 <6>[ 6.636113] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
736 00:43:15.698652 <6>[ 6.644193] IP-Config: Complete:
737 00:43:15.709634 <6>[ 6.647734] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
738 00:43:15.715299 <6>[ 6.658170] host=192.168.6.8, domain=, nis-domain=(none)
739 00:43:15.721053 <6>[ 6.664296] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
740 00:43:15.727723 <6>[ 6.664333] nameserver0=10.255.253.1
741 00:43:15.733844 <6>[ 6.676966] clk: Disabling unused clocks
742 00:43:15.739352 <6>[ 6.681704] PM: genpd: Disabling unused power domains
743 00:43:15.756848 <6>[ 6.698478] Freeing unused kernel image (initmem) memory: 2048K
744 00:43:15.764640 <6>[ 6.708361] Run /init as init process
745 00:43:15.791170 Loading, please wait...
746 00:43:15.869184 Starting systemd-udevd version 252.22-1~deb12u1
747 00:43:18.905316 <4>[ 9.843639] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 00:43:19.175279 <4>[ 10.113709] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 00:43:19.366104 <6>[ 10.311066] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
750 00:43:19.376986 <6>[ 10.316947] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
751 00:43:19.579072 <6>[ 10.522555] hub 1-0:1.0: USB hub found
752 00:43:19.658591 <6>[ 10.601800] hub 1-0:1.0: 1 port detected
753 00:43:19.722011 <6>[ 10.665071] tda998x 0-0070: found TDA19988
754 00:43:22.811792 Begin: Loading essential drivers ... done.
755 00:43:22.823054 Begin: Running /scripts/init-premount ... done.
756 00:43:22.834282 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
757 00:43:22.842378 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
758 00:43:22.846806 Device /sys/class/net/eth0 found
759 00:43:22.847296 done.
760 00:43:22.928670 Begin: Waiting up to 180 secs for any network device to become available ... done.
761 00:43:22.999604 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
762 00:43:23.092159 IP-Config: eth0 guessed broadcast address 192.168.6.255
763 00:43:23.097683 IP-Config: eth0 complete (dhcp from 192.168.6.1):
764 00:43:23.103271 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
765 00:43:23.112167 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
766 00:43:23.118079 rootserver: 192.168.6.1 rootpath:
767 00:43:23.118560 filename :
768 00:43:23.214172 done.
769 00:43:23.224229 Begin: Running /scripts/nfs-bottom ... done.
770 00:43:23.291600 Begin: Running /scripts/init-bottom ... done.
771 00:43:24.791660 <30>[ 15.733307] systemd[1]: System time before build time, advancing clock.
772 00:43:24.997771 <30>[ 15.912551] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
773 00:43:25.006550 <30>[ 15.949253] systemd[1]: Detected architecture arm.
774 00:43:25.019379
775 00:43:25.019851 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
776 00:43:25.020269
777 00:43:25.050497 <30>[ 15.992030] systemd[1]: Hostname set to <debian-bookworm-armhf>.
778 00:43:27.218087 <30>[ 18.158207] systemd[1]: Queued start job for default target graphical.target.
779 00:43:27.235044 <30>[ 18.173318] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
780 00:43:27.242666 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
781 00:43:27.266159 <30>[ 18.204631] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
782 00:43:27.273746 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
783 00:43:27.296638 <30>[ 18.235025] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
784 00:43:27.305062 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
785 00:43:27.324865 <30>[ 18.263626] systemd[1]: Created slice user.slice - User and Session Slice.
786 00:43:27.331554 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
787 00:43:27.359958 <30>[ 18.292956] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
788 00:43:27.365089 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
789 00:43:27.383946 <30>[ 18.322692] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
790 00:43:27.393941 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
791 00:43:27.421675 <30>[ 18.352515] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
792 00:43:27.433929 <30>[ 18.372927] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
793 00:43:27.438550 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
794 00:43:27.463018 <30>[ 18.402061] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
795 00:43:27.470483 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
796 00:43:27.493779 <30>[ 18.432474] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
797 00:43:27.501660 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
798 00:43:27.523610 <30>[ 18.462589] systemd[1]: Reached target paths.target - Path Units.
799 00:43:27.528706 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
800 00:43:27.553289 <30>[ 18.492220] systemd[1]: Reached target remote-fs.target - Remote File Systems.
801 00:43:27.559739 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
802 00:43:27.583225 <30>[ 18.522131] systemd[1]: Reached target slices.target - Slice Units.
803 00:43:27.587781 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
804 00:43:27.613298 <30>[ 18.552296] systemd[1]: Reached target swap.target - Swaps.
805 00:43:27.616438 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
806 00:43:27.643577 <30>[ 18.582358] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
807 00:43:27.652549 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
808 00:43:27.674417 <30>[ 18.613189] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
809 00:43:27.683037 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
810 00:43:27.763053 <30>[ 18.697001] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
811 00:43:27.775911 <30>[ 18.714729] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
812 00:43:27.784345 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
813 00:43:27.806597 <30>[ 18.744375] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
814 00:43:27.812966 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
815 00:43:27.836040 <30>[ 18.774767] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
816 00:43:27.843841 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
817 00:43:27.867727 <30>[ 18.806329] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
818 00:43:27.873400 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
819 00:43:27.905917 <30>[ 18.843328] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
820 00:43:27.913481 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
821 00:43:27.941295 <30>[ 18.875058] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
822 00:43:27.962964 <30>[ 18.895698] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
823 00:43:28.002040 <30>[ 18.942711] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
824 00:43:28.018979 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
825 00:43:28.050488 <30>[ 18.990935] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
826 00:43:28.074516 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
827 00:43:28.147784 <30>[ 19.087220] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
828 00:43:28.181075 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
829 00:43:28.233099 <30>[ 19.173248] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
830 00:43:28.252551 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
831 00:43:28.317199 <30>[ 19.256742] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
832 00:43:28.342611 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
833 00:43:28.395372 <30>[ 19.336390] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
834 00:43:28.422013 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
835 00:43:28.475235 <30>[ 19.415032] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
836 00:43:28.501291 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
837 00:43:28.553033 <30>[ 19.492893] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
838 00:43:28.581405 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
839 00:43:28.643602 <30>[ 19.582618] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
840 00:43:28.649919 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
841 00:43:28.687878 <28>[ 19.623100] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
842 00:43:28.700084 <28>[ 19.639003] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
843 00:43:28.743994 <30>[ 19.682787] systemd[1]: Starting systemd-journald.service - Journal Service...
844 00:43:28.749333 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
845 00:43:28.824182 <30>[ 19.764828] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
846 00:43:28.854762 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
847 00:43:28.906228 <30>[ 19.846109] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
848 00:43:28.963673 Starting [0;1;39msystemd-network-g… units from Kernel command line...
849 00:43:29.017926 <30>[ 19.957040] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
850 00:43:29.073076 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
851 00:43:29.133178 <30>[ 20.073194] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
852 00:43:29.183839 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
853 00:43:29.267330 <30>[ 20.207314] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
854 00:43:29.312991 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
855 00:43:29.335489 <30>[ 20.275207] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
856 00:43:29.370479 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
857 00:43:29.395640 <30>[ 20.334348] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
858 00:43:29.416500 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
859 00:43:29.586425 <30>[ 20.526906] systemd[1]: modprobe@configfs.service: Deactivated successfully.
860 00:43:29.623917 <30>[ 20.563263] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
861 00:43:29.653108 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
862 00:43:29.672862 <30>[ 20.614390] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
863 00:43:29.713093 <30>[ 20.652145] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
864 00:43:29.721512 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
865 00:43:29.744182 <30>[ 20.683332] systemd[1]: Started systemd-journald.service - Journal Service.
866 00:43:29.751034 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
867 00:43:29.784015 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
868 00:43:29.809073 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
869 00:43:29.845178 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
870 00:43:29.868930 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
871 00:43:29.903125 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
872 00:43:29.933163 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
873 00:43:29.963167 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
874 00:43:29.986822 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
875 00:43:30.052846 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
876 00:43:30.095792 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
877 00:43:30.168504 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
878 00:43:30.248170 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
879 00:43:30.337777 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
880 00:43:30.475356 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
881 00:43:30.513286 <46>[ 21.453409] systemd-journald[164]: Received client request to flush runtime journal.
882 00:43:30.606158 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
883 00:43:31.475185 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
884 00:43:31.652448 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
885 00:43:31.725291 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
886 00:43:32.226312 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
887 00:43:32.333190 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
888 00:43:32.355302 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
889 00:43:32.372876 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
890 00:43:32.461919 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
891 00:43:32.506474 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
892 00:43:33.499831 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
893 00:43:33.584394 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
894 00:43:33.718913 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
895 00:43:33.793331 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
896 00:43:33.836424 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
897 00:43:35.271338 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
898 00:43:36.422543 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
899 00:43:36.527048 <5>[ 27.467176] cfg80211: Loading compiled-in X.509 certificates for regulatory database
900 00:43:37.254672 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
901 00:43:37.682538 <5>[ 28.624508] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
902 00:43:37.752411 <5>[ 28.693018] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
903 00:43:37.764770 <4>[ 28.704554] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
904 00:43:37.770618 <6>[ 28.713738] cfg80211: failed to load regulatory.db
905 00:43:38.306741 <46>[ 29.237717] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
906 00:43:38.390674 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
907 00:43:38.501349 <46>[ 29.434495] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
908 00:43:38.864207 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
909 00:43:48.219432 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
910 00:43:48.243248 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
911 00:43:48.267926 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
912 00:43:48.296862 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
913 00:43:48.363121 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
914 00:43:48.414128 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
915 00:43:48.487270 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
916 00:43:48.531538 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
917 00:43:48.589400 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
918 00:43:48.620361 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
919 00:43:48.649152 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
920 00:43:48.689645 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
921 00:43:48.716724 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
922 00:43:48.773410 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
923 00:43:48.812953 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
924 00:43:48.835836 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
925 00:43:48.868336 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
926 00:43:48.899450 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
927 00:43:48.930192 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
928 00:43:48.953424 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
929 00:43:48.980660 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
930 00:43:49.003380 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
931 00:43:49.025936 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
932 00:43:49.103593 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
933 00:43:49.137545 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
934 00:43:49.232968 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
935 00:43:49.328900 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
936 00:43:49.378252 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
937 00:43:49.420061 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
938 00:43:49.435350 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
939 00:43:49.639809 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
940 00:43:49.724122 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
941 00:43:49.757389 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
942 00:43:49.771490 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
943 00:43:49.795391 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
944 00:43:50.064081 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
945 00:43:50.475664 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
946 00:43:50.535840 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
947 00:43:50.582307 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
948 00:43:50.646759 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
949 00:43:50.855177 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
950 00:43:51.020663
951 00:43:51.024160 Debian GNU/Linux 12 debworm-armhf login: root (automatic login)
952 00:43:51.024722
953 00:43:51.365960 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Wed Nov 6 23:52:17 UTC 2024 armv7l
954 00:43:51.366654
955 00:43:51.371548 The programs included with the Debian GNU/Linux system are free software;
956 00:43:51.377183 the exact distribution terms for each program are described in the
957 00:43:51.382760 individual files in /usr/share/doc/*/copyright.
958 00:43:51.383353
959 00:43:51.390797 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
960 00:43:51.391484 permitted by applicable law.
961 00:43:56.470256 Unable to match end of the kernel message
963 00:43:56.471220 Setting prompt string to ['/ #']
964 00:43:56.471528 end: 2.4.4.1 login-action (duration 00:00:48) [common]
966 00:43:56.472262 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
967 00:43:56.472550 start: 2.4.5 expect-shell-connection (timeout 00:03:09) [common]
968 00:43:56.472788 Setting prompt string to ['/ #']
969 00:43:56.473001 Forcing a shell prompt, looking for ['/ #']
971 00:43:56.523563 / #
972 00:43:56.524278 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
973 00:43:56.524724 Waiting using forced prompt support (timeout 00:02:30)
974 00:43:56.529288
975 00:43:56.537032 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
976 00:43:56.537678 start: 2.4.6 export-device-env (timeout 00:03:09) [common]
977 00:43:56.538296 Sending with 10 millisecond of delay
979 00:44:01.526063 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/950205/extract-nfsrootfs-q0ttwdzb'
980 00:44:01.537105 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/950205/extract-nfsrootfs-q0ttwdzb'
981 00:44:01.538304 Sending with 10 millisecond of delay
983 00:44:03.636208 / # export NFS_SERVER_IP='192.168.6.3'
984 00:44:03.647164 export NFS_SERVER_IP='192.168.6.3'
985 00:44:03.648827 end: 2.4.6 export-device-env (duration 00:00:07) [common]
986 00:44:03.649485 end: 2.4 uboot-commands (duration 00:01:59) [common]
987 00:44:03.650200 end: 2 uboot-action (duration 00:01:59) [common]
988 00:44:03.650825 start: 3 lava-test-retry (timeout 00:06:51) [common]
989 00:44:03.651481 start: 3.1 lava-test-shell (timeout 00:06:51) [common]
990 00:44:03.652022 Using namespace: common
992 00:44:03.753283 / # #
993 00:44:03.754214 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
994 00:44:03.758767 #
995 00:44:03.765296 Using /lava-950205
997 00:44:03.866566 / # export SHELL=/bin/bash
998 00:44:03.872207 export SHELL=/bin/bash
1000 00:44:03.979102 / # . /lava-950205/environment
1001 00:44:03.984248 . /lava-950205/environment
1003 00:44:04.100118 / # /lava-950205/bin/lava-test-runner /lava-950205/0
1004 00:44:04.100821 Test shell timeout: 10s (minimum of the action and connection timeout)
1005 00:44:04.104540 /lava-950205/bin/lava-test-runner /lava-950205/0
1006 00:44:04.509857 + export TESTRUN_ID=0_timesync-off
1007 00:44:04.516846 + TESTRUN_ID=0_timesync-off
1008 00:44:04.517369 + cd /lava-950205/0/tests/0_timesync-off
1009 00:44:04.517949 ++ cat uuid
1010 00:44:04.535341 + UUID=950205_1.6.2.4.1
1011 00:44:04.535898 + set +x
1012 00:44:04.542968 <LAVA_SIGNAL_STARTRUN 0_timesync-off 950205_1.6.2.4.1>
1013 00:44:04.543464 + systemctl stop systemd-timesyncd
1014 00:44:04.544350 Received signal: <STARTRUN> 0_timesync-off 950205_1.6.2.4.1
1015 00:44:04.544853 Starting test lava.0_timesync-off (950205_1.6.2.4.1)
1016 00:44:04.545528 Skipping test definition patterns.
1017 00:44:04.830398 + set +x
1018 00:44:04.830975 <LAVA_SIGNAL_ENDRUN 0_timesync-off 950205_1.6.2.4.1>
1019 00:44:04.831709 Received signal: <ENDRUN> 0_timesync-off 950205_1.6.2.4.1
1020 00:44:04.832249 Ending use of test pattern.
1021 00:44:04.832706 Ending test lava.0_timesync-off (950205_1.6.2.4.1), duration 0.29
1023 00:44:04.997708 + export TESTRUN_ID=1_kselftest-dt
1024 00:44:05.004659 + TESTRUN_ID=1_kselftest-dt
1025 00:44:05.005263 + cd /lava-950205/0/tests/1_kselftest-dt
1026 00:44:05.005743 ++ cat uuid
1027 00:44:05.022495 + UUID=950205_1.6.2.4.5
1028 00:44:05.023004 + set +x
1029 00:44:05.028150 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 950205_1.6.2.4.5>
1030 00:44:05.028705 + cd ./automated/linux/kselftest/
1031 00:44:05.029439 Received signal: <STARTRUN> 1_kselftest-dt 950205_1.6.2.4.5
1032 00:44:05.029945 Starting test lava.1_kselftest-dt (950205_1.6.2.4.5)
1033 00:44:05.030518 Skipping test definition patterns.
1034 00:44:05.055598 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1035 00:44:05.171655 INFO: install_deps skipped
1036 00:44:05.711823 --2024-11-07 00:44:05-- http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1037 00:44:05.981305 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1038 00:44:06.119258 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1039 00:44:06.257023 HTTP request sent, awaiting response... 200 OK
1040 00:44:06.257597 Length: 2541764 (2.4M) [application/octet-stream]
1041 00:44:06.262516 Saving to: 'kselftest_armhf.tar.gz'
1042 00:44:06.262996
1043 00:44:07.524636
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 47.54K 178KB/s
kselftest_armhf.tar 8%[> ] 216.29K 405KB/s
kselftest_armhf.tar 31%[=====> ] 791.01K 972KB/s
kselftest_armhf.tar 43%[=======> ] 1.05M 939KB/s
kselftest_armhf.tar 100%[===================>] 2.42M 1.92MB/s in 1.3s
1044 00:44:07.525280
1045 00:44:07.880164 2024-11-07 00:44:07 (1.92 MB/s) - 'kselftest_armhf.tar.gz' saved [2541764/2541764]
1046 00:44:07.880731
1047 00:44:21.236499 skiplist:
1048 00:44:21.236929 ========================================
1049 00:44:21.241407 ========================================
1050 00:44:21.349360 dt:test_unprobed_devices.sh
1051 00:44:21.399825 ============== Tests to run ===============
1052 00:44:21.409471 dt:test_unprobed_devices.sh
1053 00:44:21.413345 ===========End Tests to run ===============
1054 00:44:21.421187 shardfile-dt pass
1055 00:44:21.664156 <12>[ 72.609017] kselftest: Running tests in dt
1056 00:44:21.696416 TAP version 13
1057 00:44:21.720225 1..1
1058 00:44:21.775653 # timeout set to 45
1059 00:44:21.776176 # selftests: dt: test_unprobed_devices.sh
1060 00:44:22.671905 # TAP version 13
1061 00:44:48.274670 # 1..257
1062 00:44:48.467641 # ok 1 / # SKIP
1063 00:44:48.492663 # ok 2 /clk_mcasp0
1064 00:44:48.564425 # ok 3 /clk_mcasp0_fixed # SKIP
1065 00:44:48.637140 # ok 4 /cpus/cpu@0 # SKIP
1066 00:44:48.711485 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1067 00:44:48.733118 # ok 6 /fixedregulator0
1068 00:44:48.758913 # ok 7 /leds
1069 00:44:48.780980 # ok 8 /ocp
1070 00:44:48.800833 # ok 9 /ocp/interconnect@44c00000
1071 00:44:48.830432 # ok 10 /ocp/interconnect@44c00000/segment@0
1072 00:44:48.849001 # ok 11 /ocp/interconnect@44c00000/segment@100000
1073 00:44:48.877553 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1074 00:44:48.952637 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1075 00:44:48.968903 # ok 14 /ocp/interconnect@44c00000/segment@200000
1076 00:44:48.997165 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1077 00:44:49.104074 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1078 00:44:49.184918 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1079 00:44:49.258190 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1080 00:44:49.332499 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1081 00:44:49.408267 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1082 00:44:49.483796 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1083 00:44:49.557722 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1084 00:44:49.631680 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1085 00:44:49.706047 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1086 00:44:49.781226 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1087 00:44:49.855009 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1088 00:44:49.929805 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1089 00:44:50.004430 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1090 00:44:50.078560 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1091 00:44:50.151615 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1092 00:44:50.226402 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1093 00:44:50.304341 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1094 00:44:50.379455 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1095 00:44:50.449615 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1096 00:44:50.523927 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1097 00:44:50.597005 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1098 00:44:50.672109 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1099 00:44:50.757581 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1100 00:44:50.833299 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1101 00:44:50.908811 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1102 00:44:50.984480 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1103 00:44:51.060105 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1104 00:44:51.134826 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1105 00:44:51.213757 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1106 00:44:51.288060 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1107 00:44:51.363815 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1108 00:44:51.449607 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1109 00:44:51.524555 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1110 00:44:51.599397 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1111 00:44:51.673417 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1112 00:44:51.747352 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1113 00:44:51.822356 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1114 00:44:51.896865 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1115 00:44:51.972061 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1116 00:44:52.045054 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1117 00:44:52.126333 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1118 00:44:52.197197 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1119 00:44:52.271572 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1120 00:44:52.348413 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1121 00:44:52.424387 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1122 00:44:52.497486 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1123 00:44:52.572977 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1124 00:44:52.646190 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1125 00:44:52.722093 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1126 00:44:52.795918 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1127 00:44:52.873093 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1128 00:44:52.946028 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1129 00:44:53.021761 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1130 00:44:53.096493 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1131 00:44:53.177593 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1132 00:44:53.246549 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1133 00:44:53.321213 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1134 00:44:53.395294 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1135 00:44:53.472221 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1136 00:44:53.545603 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1137 00:44:53.621606 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1138 00:44:53.694541 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1139 00:44:53.767425 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1140 00:44:53.841944 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1141 00:44:53.914321 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1142 00:44:53.988727 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1143 00:44:54.067106 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1144 00:44:54.140048 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1145 00:44:54.210541 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1146 00:44:54.290408 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1147 00:44:54.363138 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1148 00:44:54.435659 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1149 00:44:54.509536 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1150 00:44:54.586521 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1151 00:44:54.660664 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1152 00:44:54.731266 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1153 00:44:54.806477 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1154 00:44:54.879113 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1155 00:44:54.953262 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1156 00:44:54.974785 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1157 00:44:55.001766 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1158 00:44:55.028530 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1159 00:44:55.048677 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1160 00:44:55.076943 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1161 00:44:55.098769 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1162 00:44:55.121454 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1163 00:44:55.147573 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1164 00:44:55.254317 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1165 00:44:55.288077 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1166 00:44:55.305070 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1167 00:44:55.330132 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1168 00:44:55.444017 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1169 00:44:55.517890 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1170 00:44:55.593273 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1171 00:44:55.667284 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1172 00:44:55.743733 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1173 00:44:55.816418 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1174 00:44:55.891822 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1175 00:44:55.964438 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1176 00:44:56.041103 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1177 00:44:56.117235 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1178 00:44:56.191429 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1179 00:44:56.270437 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1180 00:44:56.346825 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1181 00:44:56.419583 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1182 00:44:56.494799 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1183 00:44:56.568980 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1184 00:44:56.593453 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1185 00:44:56.667316 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1186 00:44:56.743975 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1187 00:44:56.819167 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1188 00:44:56.843474 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1189 00:44:56.918522 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1190 00:44:56.942756 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1191 00:44:57.016666 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1192 00:44:57.037505 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1193 00:44:57.060742 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1194 00:44:57.084047 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1195 00:44:57.114142 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1196 00:44:57.137600 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1197 00:44:57.158849 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1198 00:44:57.189907 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1199 00:44:57.264109 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1200 00:44:57.286078 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1201 00:44:57.314893 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1202 00:44:57.389562 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1203 00:44:57.458999 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1204 00:44:57.481004 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1205 00:44:57.585750 # not ok 144 /ocp/interconnect@47c00000
1206 00:44:57.660804 # not ok 145 /ocp/interconnect@47c00000/segment@0
1207 00:44:57.684509 # ok 146 /ocp/interconnect@48000000
1208 00:44:57.710276 # ok 147 /ocp/interconnect@48000000/segment@0
1209 00:44:57.733371 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1210 00:44:57.761538 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1211 00:44:57.781298 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1212 00:44:57.807431 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1213 00:44:57.829188 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1214 00:44:57.854549 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1215 00:44:57.877988 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1216 00:44:57.952559 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1217 00:44:58.028713 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1218 00:44:58.051081 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1219 00:44:58.074946 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1220 00:44:58.099061 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1221 00:44:58.127954 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1222 00:44:58.151642 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1223 00:44:58.172300 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1224 00:44:58.196264 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1225 00:44:58.220448 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1226 00:44:58.244485 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1227 00:44:58.270882 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1228 00:44:58.297199 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1229 00:44:58.318094 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1230 00:44:58.341647 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1231 00:44:58.366239 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1232 00:44:58.389633 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1233 00:44:58.414333 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1234 00:44:58.440086 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1235 00:44:58.462750 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1236 00:44:58.483642 # ok 175 /ocp/interconnect@48000000/segment@100000
1237 00:44:58.513772 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1238 00:44:58.538136 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1239 00:44:58.609476 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1240 00:44:58.684789 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1241 00:44:58.757287 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1242 00:44:58.833588 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1243 00:44:58.905930 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1244 00:44:58.982654 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1245 00:44:59.055480 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1246 00:44:59.137792 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1247 00:44:59.156663 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1248 00:44:59.183517 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1249 00:44:59.204137 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1250 00:44:59.232832 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1251 00:44:59.257075 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1252 00:44:59.277212 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1253 00:44:59.305595 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1254 00:44:59.328239 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1255 00:44:59.350015 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1256 00:44:59.373682 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1257 00:44:59.403600 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1258 00:44:59.423416 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1259 00:44:59.444328 # ok 198 /ocp/interconnect@48000000/segment@200000
1260 00:44:59.474945 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1261 00:44:59.547558 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1262 00:44:59.567841 # ok 201 /ocp/interconnect@48000000/segment@300000
1263 00:44:59.592877 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1264 00:44:59.621753 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1265 00:44:59.646703 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1266 00:44:59.667616 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1267 00:44:59.695271 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1268 00:44:59.717529 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1269 00:44:59.790859 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1270 00:44:59.809284 # ok 209 /ocp/interconnect@4a000000
1271 00:44:59.835603 # ok 210 /ocp/interconnect@4a000000/segment@0
1272 00:44:59.859344 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1273 00:44:59.884155 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1274 00:44:59.909932 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1275 00:44:59.935969 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1276 00:45:00.008477 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1277 00:45:00.117112 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1278 00:45:00.188606 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1279 00:45:00.295499 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1280 00:45:00.369164 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1281 00:45:00.446855 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1282 00:45:00.548559 # not ok 221 /ocp/interconnect@4b140000
1283 00:45:00.625218 # not ok 222 /ocp/interconnect@4b140000/segment@0
1284 00:45:00.699214 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1285 00:45:00.721751 # ok 224 /ocp/target-module@40300000
1286 00:45:00.744335 # ok 225 /ocp/target-module@40300000/sram@0
1287 00:45:00.822861 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1288 00:45:00.897413 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1289 00:45:00.913183 # ok 228 /ocp/target-module@47400000
1290 00:45:00.938930 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1291 00:45:00.964759 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1292 00:45:00.993281 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1293 00:45:01.008396 # ok 232 /ocp/target-module@47400000/usb@1400
1294 00:45:01.032059 # ok 233 /ocp/target-module@47400000/usb@1800
1295 00:45:01.054992 # ok 234 /ocp/target-module@47810000
1296 00:45:01.081994 # ok 235 /ocp/target-module@49000000
1297 00:45:01.104236 # ok 236 /ocp/target-module@49000000/dma@0
1298 00:45:01.125017 # ok 237 /ocp/target-module@49800000
1299 00:45:01.153226 # ok 238 /ocp/target-module@49800000/dma@0
1300 00:45:01.173629 # ok 239 /ocp/target-module@49900000
1301 00:45:01.200508 # ok 240 /ocp/target-module@49900000/dma@0
1302 00:45:01.223202 # ok 241 /ocp/target-module@49a00000
1303 00:45:01.244318 # ok 242 /ocp/target-module@49a00000/dma@0
1304 00:45:01.270766 # ok 243 /ocp/target-module@4c000000
1305 00:45:01.344751 # not ok 244 /ocp/target-module@4c000000/emif@0
1306 00:45:01.369730 # ok 245 /ocp/target-module@50000000
1307 00:45:01.392898 # ok 246 /ocp/target-module@53100000
1308 00:45:01.462325 # not ok 247 /ocp/target-module@53100000/sham@0
1309 00:45:01.483986 # ok 248 /ocp/target-module@53500000
1310 00:45:01.562968 # not ok 249 /ocp/target-module@53500000/aes@0
1311 00:45:01.580716 # ok 250 /ocp/target-module@56000000
1312 00:45:01.693385 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1313 00:45:01.759871 # ok 252 /opp-table # SKIP
1314 00:45:01.833188 # ok 253 /soc # SKIP
1315 00:45:01.859214 # ok 254 /sound
1316 00:45:01.878971 # ok 255 /target-module@4b000000
1317 00:45:01.906222 # ok 256 /target-module@4b000000/target-module@140000
1318 00:45:01.928240 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1319 00:45:01.936487 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1320 00:45:01.944293 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1321 00:45:04.187456 dt_test_unprobed_devices_sh_ skip
1322 00:45:04.192955 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1323 00:45:04.198532 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1324 00:45:04.198914 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1325 00:45:04.207350 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1326 00:45:04.207706 dt_test_unprobed_devices_sh_fixedregulator0 pass
1327 00:45:04.212945 dt_test_unprobed_devices_sh_leds pass
1328 00:45:04.218554 dt_test_unprobed_devices_sh_ocp pass
1329 00:45:04.224167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1330 00:45:04.229771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1331 00:45:04.235401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1332 00:45:04.241064 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1333 00:45:04.252389 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1334 00:45:04.258094 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1335 00:45:04.263481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1336 00:45:04.274846 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1337 00:45:04.286039 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1338 00:45:04.291632 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1339 00:45:04.302885 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1340 00:45:04.314088 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1341 00:45:04.325271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1342 00:45:04.336498 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1343 00:45:04.342118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1344 00:45:04.353274 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1345 00:45:04.364563 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1346 00:45:04.375742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1347 00:45:04.381336 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1348 00:45:04.392460 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1349 00:45:04.403758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1350 00:45:04.414895 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1351 00:45:04.426104 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1352 00:45:04.431649 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1353 00:45:04.442908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1354 00:45:04.454061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1355 00:45:04.465375 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1356 00:45:04.470832 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1357 00:45:04.482058 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1358 00:45:04.493198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1359 00:45:04.504443 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1360 00:45:04.515647 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1361 00:45:04.526859 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1362 00:45:04.538098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1363 00:45:04.549239 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1364 00:45:04.560498 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1365 00:45:04.571684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1366 00:45:04.582897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1367 00:45:04.594051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1368 00:45:04.605258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1369 00:45:04.616473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1370 00:45:04.627631 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1371 00:45:04.638898 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1372 00:45:04.650082 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1373 00:45:04.661297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1374 00:45:04.672530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1375 00:45:04.683668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1376 00:45:04.694892 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1377 00:45:04.706007 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1378 00:45:04.717209 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1379 00:45:04.722896 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1380 00:45:04.734061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1381 00:45:04.745255 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1382 00:45:04.756422 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1383 00:45:04.767731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1384 00:45:04.779150 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1385 00:45:04.793972 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1386 00:45:04.801276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1387 00:45:04.812593 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1388 00:45:04.823877 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1389 00:45:04.836884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1390 00:45:04.840556 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1391 00:45:04.851867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1392 00:45:04.865741 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1393 00:45:04.874224 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1394 00:45:04.885339 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1395 00:45:04.896540 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1396 00:45:04.911055 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1397 00:45:04.918917 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1398 00:45:04.930045 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1399 00:45:04.941266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1400 00:45:04.953522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1401 00:45:04.963630 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1402 00:45:04.974874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1403 00:45:04.986083 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1404 00:45:04.998282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1405 00:45:05.002921 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1406 00:45:05.014100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1407 00:45:05.025162 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1408 00:45:05.036322 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1409 00:45:05.047529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1410 00:45:05.058999 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1411 00:45:05.069882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1412 00:45:05.081201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1413 00:45:05.092410 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1414 00:45:05.103556 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1415 00:45:05.114773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1416 00:45:05.125986 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1417 00:45:05.131567 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1418 00:45:05.142768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1419 00:45:05.153942 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1420 00:45:05.159629 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1421 00:45:05.170793 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1422 00:45:05.176509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1423 00:45:05.188249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1424 00:45:05.198654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1425 00:45:05.204258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1426 00:45:05.215428 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1427 00:45:05.226660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1428 00:45:05.237943 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1429 00:45:05.249025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1430 00:45:05.260190 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1431 00:45:05.271438 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1432 00:45:05.288157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1433 00:45:05.299362 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1434 00:45:05.310607 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1435 00:45:05.321722 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1436 00:45:05.332960 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1437 00:45:05.344129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1438 00:45:05.355340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1439 00:45:05.372130 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1440 00:45:05.383336 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1441 00:45:05.394532 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1442 00:45:05.411321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1443 00:45:05.422487 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1444 00:45:05.428178 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1445 00:45:05.439346 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1446 00:45:05.444961 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1447 00:45:05.456167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1448 00:45:05.467299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1449 00:45:05.472930 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1450 00:45:05.484055 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1451 00:45:05.489668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1452 00:45:05.500888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1453 00:45:05.506472 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1454 00:45:05.517627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1455 00:45:05.523301 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1456 00:45:05.534471 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1457 00:45:05.545656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1458 00:45:05.556955 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1459 00:45:05.562499 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1460 00:45:05.573639 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1461 00:45:05.584941 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1462 00:45:05.596060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1463 00:45:05.601660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1464 00:45:05.607268 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1465 00:45:05.612856 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1466 00:45:05.618460 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1467 00:45:05.624053 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1468 00:45:05.635234 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1469 00:45:05.640847 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1470 00:45:05.652094 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1471 00:45:05.657735 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1472 00:45:05.663294 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1473 00:45:05.674483 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1474 00:45:05.680024 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1475 00:45:05.691252 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1476 00:45:05.696897 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1477 00:45:05.707990 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1478 00:45:05.713698 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1479 00:45:05.724909 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1480 00:45:05.730492 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1481 00:45:05.736061 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1482 00:45:05.747127 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1483 00:45:05.752764 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1484 00:45:05.763945 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1485 00:45:05.769570 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1486 00:45:05.780726 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1487 00:45:05.786353 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1488 00:45:05.797527 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1489 00:45:05.803128 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1490 00:45:05.814390 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1491 00:45:05.819904 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1492 00:45:05.833382 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1493 00:45:05.836655 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1494 00:45:05.847957 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1495 00:45:05.853438 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1496 00:45:05.859053 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1497 00:45:05.873993 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1498 00:45:05.881458 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1499 00:45:05.892633 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1500 00:45:05.903806 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1501 00:45:05.915101 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1502 00:45:05.920654 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1503 00:45:05.931807 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1504 00:45:05.942990 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1505 00:45:05.954414 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1506 00:45:05.965627 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1507 00:45:05.971096 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1508 00:45:05.982298 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1509 00:45:05.987746 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1510 00:45:05.999080 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1511 00:45:06.004647 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1512 00:45:06.015819 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1513 00:45:06.021476 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1514 00:45:06.032644 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1515 00:45:06.038193 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1516 00:45:06.049334 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1517 00:45:06.054939 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1518 00:45:06.066129 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1519 00:45:06.071731 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1520 00:45:06.082924 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1521 00:45:06.088518 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1522 00:45:06.094121 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1523 00:45:06.105305 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1524 00:45:06.110904 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1525 00:45:06.122093 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1526 00:45:06.127698 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1527 00:45:06.138937 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1528 00:45:06.144456 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1529 00:45:06.150083 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1530 00:45:06.155699 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1531 00:45:06.166917 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1532 00:45:06.172409 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1533 00:45:06.183606 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1534 00:45:06.189240 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1535 00:45:06.200377 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1536 00:45:06.211609 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1537 00:45:06.222783 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1538 00:45:06.228406 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1539 00:45:06.239626 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1540 00:45:06.250946 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1541 00:45:06.256614 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1542 00:45:06.262223 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1543 00:45:06.267843 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1544 00:45:06.273481 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1545 00:45:06.279116 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1546 00:45:06.285009 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1547 00:45:06.290222 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1548 00:45:06.295902 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1549 00:45:06.307025 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1550 00:45:06.312597 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1551 00:45:06.318181 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1552 00:45:06.323828 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1553 00:45:06.329387 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1554 00:45:06.335026 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1555 00:45:06.340632 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1556 00:45:06.346217 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1557 00:45:06.351866 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1558 00:45:06.357482 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1559 00:45:06.363120 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1560 00:45:06.368652 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1561 00:45:06.374313 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1562 00:45:06.379996 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1563 00:45:06.385573 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1564 00:45:06.391167 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1565 00:45:06.396789 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1566 00:45:06.402402 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1567 00:45:06.407977 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1568 00:45:06.413607 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1569 00:45:06.419245 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1570 00:45:06.424790 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1571 00:45:06.430439 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1572 00:45:06.436009 dt_test_unprobed_devices_sh_opp-table skip
1573 00:45:06.436445 dt_test_unprobed_devices_sh_soc skip
1574 00:45:06.441624 dt_test_unprobed_devices_sh_sound pass
1575 00:45:06.447209 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1576 00:45:06.452798 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1577 00:45:06.458429 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1578 00:45:06.464039 dt_test_unprobed_devices_sh fail
1579 00:45:06.469614 + ../../utils/send-to-lava.sh ./output/result.txt
1580 00:45:06.474278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1581 00:45:06.475045 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1583 00:45:06.503356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1584 00:45:06.504033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1586 00:45:06.602433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1587 00:45:06.603243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1589 00:45:06.691970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1590 00:45:06.692636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1592 00:45:06.793171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1593 00:45:06.793858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1595 00:45:06.891467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1596 00:45:06.892119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1598 00:45:06.985839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1599 00:45:06.986470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1601 00:45:07.079306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1602 00:45:07.079927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1604 00:45:07.172691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1605 00:45:07.173276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1607 00:45:07.268082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1608 00:45:07.268934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1610 00:45:07.361032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1611 00:45:07.361881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1613 00:45:07.455621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1614 00:45:07.456488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1616 00:45:07.551506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1617 00:45:07.552169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1619 00:45:07.647404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1620 00:45:07.648894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1622 00:45:07.740609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1623 00:45:07.741247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1625 00:45:07.837768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1626 00:45:07.838425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1628 00:45:07.936136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1629 00:45:07.936752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1631 00:45:08.033420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1632 00:45:08.035446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1634 00:45:08.145227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1635 00:45:08.146038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1637 00:45:08.246606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1638 00:45:08.247228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1640 00:45:08.340709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1641 00:45:08.341371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1643 00:45:08.441562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1644 00:45:08.442268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1646 00:45:08.540889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1647 00:45:08.541563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1649 00:45:08.637240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1650 00:45:08.637921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1652 00:45:08.736372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1653 00:45:08.737058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1655 00:45:08.830765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1656 00:45:08.831445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1658 00:45:08.926681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1659 00:45:08.927639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1661 00:45:09.020812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1662 00:45:09.022076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1664 00:45:09.117469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1665 00:45:09.118430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1667 00:45:09.217094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1668 00:45:09.217964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1670 00:45:09.309764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1671 00:45:09.310851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1673 00:45:09.406471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1674 00:45:09.407481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1676 00:45:09.500735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1677 00:45:09.501687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1679 00:45:09.595402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1680 00:45:09.596362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1682 00:45:09.691017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1683 00:45:09.691684 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1685 00:45:09.783918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1686 00:45:09.784569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1688 00:45:09.875031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1689 00:45:09.875669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1691 00:45:09.970757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1692 00:45:09.971392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1694 00:45:10.068674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1695 00:45:10.069560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1697 00:45:10.165618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1698 00:45:10.166472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1700 00:45:10.263201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1701 00:45:10.264040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1703 00:45:10.361091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1704 00:45:10.361937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1706 00:45:10.458884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1707 00:45:10.459689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1709 00:45:10.554800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1710 00:45:10.555486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1712 00:45:10.669959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1713 00:45:10.670790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1715 00:45:10.770438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1716 00:45:10.771409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1718 00:45:10.866726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1719 00:45:10.867699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1721 00:45:10.969101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1722 00:45:10.969981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1724 00:45:11.065206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1725 00:45:11.066140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1727 00:45:11.163368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1728 00:45:11.164709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1730 00:45:11.265234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1731 00:45:11.266058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1733 00:45:11.359672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1734 00:45:11.360315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1736 00:45:11.449681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1737 00:45:11.450668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1739 00:45:11.548220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1740 00:45:11.549086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1742 00:45:11.643568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1743 00:45:11.644529 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1745 00:45:11.737214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1746 00:45:11.738435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1748 00:45:11.832975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1749 00:45:11.834207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1751 00:45:11.931174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1752 00:45:11.932124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1754 00:45:12.026995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1755 00:45:12.027910 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1757 00:45:12.127463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1758 00:45:12.128133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1760 00:45:12.229081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1761 00:45:12.229739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1763 00:45:12.324795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1764 00:45:12.325453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1766 00:45:12.426926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1767 00:45:12.427577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1769 00:45:12.528204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1770 00:45:12.528852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1772 00:45:12.626441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1773 00:45:12.627351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1775 00:45:12.727279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1776 00:45:12.727908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1778 00:45:12.828112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1779 00:45:12.829118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1781 00:45:12.929921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1782 00:45:12.930754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1784 00:45:13.023193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1785 00:45:13.024041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1787 00:45:13.114860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1788 00:45:13.115690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1790 00:45:13.209364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1791 00:45:13.210186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1793 00:45:13.297753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1794 00:45:13.298566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1796 00:45:13.394483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1797 00:45:13.395273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1799 00:45:13.488707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1800 00:45:13.489477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1802 00:45:13.589518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1803 00:45:13.590323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1805 00:45:13.690820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1806 00:45:13.691531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1808 00:45:13.788795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1809 00:45:13.789488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1811 00:45:13.877919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1812 00:45:13.878578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1814 00:45:13.978846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1815 00:45:13.979482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1817 00:45:14.076629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1818 00:45:14.077287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1820 00:45:14.172724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1821 00:45:14.173665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1823 00:45:14.273888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1824 00:45:14.275471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1826 00:45:14.374120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1827 00:45:14.374849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1829 00:45:14.470538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1830 00:45:14.471223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1832 00:45:14.570813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1833 00:45:14.571513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1835 00:45:14.677508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1836 00:45:14.678230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1838 00:45:14.787270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1839 00:45:14.788180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1841 00:45:14.888229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1842 00:45:14.888882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1844 00:45:14.996187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1845 00:45:14.996869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1847 00:45:15.091305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1848 00:45:15.091978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1850 00:45:15.188323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1851 00:45:15.189022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1853 00:45:15.281573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1854 00:45:15.282286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1856 00:45:15.371069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1857 00:45:15.371773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1859 00:45:15.472161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1860 00:45:15.472856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1862 00:45:15.569191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1863 00:45:15.569885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1865 00:45:15.667996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1866 00:45:15.669001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1868 00:45:15.768840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1869 00:45:15.769482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1871 00:45:15.865997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1872 00:45:15.866672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1874 00:45:15.970647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1875 00:45:15.971323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1877 00:45:16.060216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1878 00:45:16.061016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1880 00:45:16.161636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1881 00:45:16.162323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1883 00:45:16.267161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1884 00:45:16.268230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1886 00:45:16.368304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1887 00:45:16.369213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1889 00:45:16.470319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1890 00:45:16.470944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1892 00:45:16.572514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1893 00:45:16.573341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1895 00:45:16.669585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1896 00:45:16.670618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1898 00:45:16.766194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1899 00:45:16.767043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1901 00:45:16.864637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1902 00:45:16.865429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1904 00:45:16.968274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1905 00:45:16.969242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1907 00:45:17.069864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1908 00:45:17.070691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1910 00:45:17.174428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1911 00:45:17.175404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1913 00:45:17.269366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1914 00:45:17.270053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1916 00:45:17.367466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1917 00:45:17.368317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1919 00:45:17.469290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1920 00:45:17.470739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1922 00:45:17.566885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1923 00:45:17.567875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1925 00:45:17.668497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1926 00:45:17.669140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1928 00:45:17.770119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1929 00:45:17.771029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1931 00:45:17.869977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1932 00:45:17.873369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1934 00:45:17.990007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1935 00:45:17.990673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1937 00:45:18.088325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1938 00:45:18.089388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1940 00:45:18.183913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1942 00:45:18.186950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1943 00:45:18.280925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1945 00:45:18.282962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1946 00:45:18.382089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1948 00:45:18.385112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1949 00:45:18.479485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1950 00:45:18.480148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1952 00:45:18.580191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1953 00:45:18.580824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1955 00:45:18.679884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1956 00:45:18.680510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1958 00:45:18.785132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1959 00:45:18.785884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1961 00:45:18.880791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1962 00:45:18.881452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1964 00:45:18.978070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1965 00:45:18.978702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1967 00:45:19.071164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1968 00:45:19.072263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1970 00:45:19.172315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1971 00:45:19.173201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1973 00:45:19.268862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1974 00:45:19.269804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1976 00:45:19.370183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1977 00:45:19.371799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1979 00:45:19.469334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1980 00:45:19.469968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1982 00:45:19.564012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1983 00:45:19.564650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1985 00:45:19.666143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1986 00:45:19.666783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1988 00:45:19.768409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1989 00:45:19.769045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1991 00:45:19.861107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1992 00:45:19.861754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1994 00:45:19.958823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1995 00:45:19.959452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
1997 00:45:20.056141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1998 00:45:20.056785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2000 00:45:20.150966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2001 00:45:20.151606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2003 00:45:20.248178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2004 00:45:20.248840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2006 00:45:20.343957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2007 00:45:20.344634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2009 00:45:20.436975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2010 00:45:20.437649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2012 00:45:20.530267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2013 00:45:20.530930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2015 00:45:20.628114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2016 00:45:20.628809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2018 00:45:20.722924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2019 00:45:20.723549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2021 00:45:20.816619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2022 00:45:20.817240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2024 00:45:20.914305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2025 00:45:20.914929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2027 00:45:21.010187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2028 00:45:21.010827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2030 00:45:21.106813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2031 00:45:21.107457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2033 00:45:21.198567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2034 00:45:21.199217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2036 00:45:21.294508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2037 00:45:21.295156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2039 00:45:21.388233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2040 00:45:21.388898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2042 00:45:21.480886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2043 00:45:21.481575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2045 00:45:21.578105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2046 00:45:21.578717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2048 00:45:21.675765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2049 00:45:21.676413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2051 00:45:21.768576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2052 00:45:21.769199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2054 00:45:21.864756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2055 00:45:21.865445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2057 00:45:21.957616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2058 00:45:21.958257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2060 00:45:22.051253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2061 00:45:22.051875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2063 00:45:22.146025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2064 00:45:22.146650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2066 00:45:22.238828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2067 00:45:22.239464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2069 00:45:22.332945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2070 00:45:22.333647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2072 00:45:22.427072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2073 00:45:22.427976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2075 00:45:22.519438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2076 00:45:22.520333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2078 00:45:22.608873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2079 00:45:22.609736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2081 00:45:22.701491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2082 00:45:22.702143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2084 00:45:22.794939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2085 00:45:22.795815 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2087 00:45:22.886109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2088 00:45:22.886739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2090 00:45:22.979978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2091 00:45:22.980696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2093 00:45:23.073768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2094 00:45:23.074517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2096 00:45:23.175502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2097 00:45:23.176260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2099 00:45:23.276106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2100 00:45:23.276866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2102 00:45:23.367786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2103 00:45:23.368513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2105 00:45:23.462298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2106 00:45:23.463046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2108 00:45:23.557558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2109 00:45:23.558434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2111 00:45:23.651387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2112 00:45:23.652153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2114 00:45:23.749202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2115 00:45:23.750198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2117 00:45:24.145447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2118 00:45:24.146235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2119 00:45:24.146689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2120 00:45:24.147381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2122 00:45:24.148740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2124 00:45:24.150107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2126 00:45:24.153155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2127 00:45:24.153975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2129 00:45:24.251607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2130 00:45:24.252467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2132 00:45:24.346275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2133 00:45:24.346978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2135 00:45:24.443590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2136 00:45:24.445222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2138 00:45:24.541696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2139 00:45:24.542334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2141 00:45:24.637024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2142 00:45:24.637651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2144 00:45:24.738205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2145 00:45:24.739094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2147 00:45:24.839245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2148 00:45:24.840159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2150 00:45:24.941776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2151 00:45:24.942827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2153 00:45:25.035564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2154 00:45:25.036652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2156 00:45:25.128233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2157 00:45:25.129100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2159 00:45:25.234731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2160 00:45:25.235591 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2162 00:45:25.335228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2163 00:45:25.335946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2165 00:45:25.436569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2166 00:45:25.437254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2168 00:45:25.533743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2169 00:45:25.534324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2171 00:45:25.635386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2172 00:45:25.636028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2174 00:45:25.734071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2175 00:45:25.734989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2177 00:45:25.837513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2178 00:45:25.838493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2180 00:45:25.939688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2181 00:45:25.940615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2183 00:45:26.039584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2184 00:45:26.040519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2186 00:45:26.141410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2187 00:45:26.142405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2189 00:45:26.245129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2190 00:45:26.246025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2192 00:45:26.345187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2193 00:45:26.346425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2195 00:45:26.439101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2196 00:45:26.439970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2198 00:45:26.539839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2199 00:45:26.542230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2201 00:45:26.635478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2202 00:45:26.636433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2204 00:45:26.737475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2205 00:45:26.738266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2207 00:45:26.832866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2208 00:45:26.835463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2210 00:45:26.926902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2211 00:45:26.927598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2213 00:45:27.031244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2214 00:45:27.032359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2216 00:45:27.134098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2217 00:45:27.134961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2219 00:45:27.235456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2220 00:45:27.236268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2222 00:45:27.335047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2223 00:45:27.335861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2225 00:45:27.428952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2226 00:45:27.429787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2228 00:45:27.532192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2229 00:45:27.533069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2231 00:45:27.634508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2232 00:45:27.635387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2234 00:45:27.727098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2235 00:45:27.728033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2237 00:45:27.823540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2238 00:45:27.824494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2240 00:45:27.925211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2241 00:45:27.926153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2243 00:45:28.021686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2244 00:45:28.022687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2246 00:45:28.131566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2247 00:45:28.132465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2249 00:45:28.233153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2250 00:45:28.234031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2252 00:45:28.339763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2253 00:45:28.340732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2255 00:45:28.436264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2256 00:45:28.437793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2258 00:45:28.537988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2259 00:45:28.538861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2261 00:45:28.638174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2263 00:45:28.641220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2264 00:45:28.734713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2265 00:45:28.735585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2267 00:45:28.830258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2268 00:45:28.831124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2270 00:45:28.931780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2271 00:45:28.932940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2273 00:45:29.031893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2274 00:45:29.032673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2276 00:45:29.133130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2277 00:45:29.134026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2279 00:45:29.234791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2280 00:45:29.235625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2282 00:45:29.334941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2283 00:45:29.335490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2285 00:45:29.436865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2286 00:45:29.437710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2288 00:45:29.533549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2289 00:45:29.534827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2291 00:45:29.622328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2292 00:45:29.623249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2294 00:45:29.724981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2295 00:45:29.725930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2297 00:45:29.826334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2298 00:45:29.827271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2300 00:45:29.928278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2301 00:45:29.929223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2303 00:45:30.021082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2304 00:45:30.021997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2306 00:45:30.122807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2307 00:45:30.123743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2309 00:45:30.223481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2310 00:45:30.224419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2312 00:45:30.321111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2313 00:45:30.321755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2315 00:45:30.420675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2316 00:45:30.421371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2318 00:45:30.522567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2319 00:45:30.523238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2321 00:45:30.623595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2322 00:45:30.624523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2324 00:45:30.725343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2325 00:45:30.726290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2327 00:45:30.821953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2328 00:45:30.822811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2330 00:45:30.923368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2331 00:45:30.924198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2333 00:45:31.025973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2334 00:45:31.027088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2336 00:45:31.117368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2337 00:45:31.118267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2339 00:45:31.211478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2340 00:45:31.212280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2342 00:45:31.300944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2343 00:45:31.301750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2345 00:45:31.403398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2346 00:45:31.404227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2348 00:45:31.506886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2349 00:45:31.507687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2351 00:45:31.609177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2352 00:45:31.609979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2354 00:45:31.706995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2355 00:45:31.707517 + set +x
2356 00:45:31.708193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2358 00:45:31.711336 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 950205_1.6.2.4.5>
2359 00:45:31.712064 Received signal: <ENDRUN> 1_kselftest-dt 950205_1.6.2.4.5
2360 00:45:31.712523 Ending use of test pattern.
2361 00:45:31.712935 Ending test lava.1_kselftest-dt (950205_1.6.2.4.5), duration 86.68
2363 00:45:31.718948 <LAVA_TEST_RUNNER EXIT>
2364 00:45:31.719669 ok: lava_test_shell seems to have completed
2365 00:45:31.732339 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2366 00:45:31.734309 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2367 00:45:31.734911 end: 3 lava-test-retry (duration 00:01:28) [common]
2368 00:45:31.735514 start: 4 finalize (timeout 00:05:23) [common]
2369 00:45:31.736104 start: 4.1 power-off (timeout 00:00:30) [common]
2370 00:45:31.737096 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2371 00:45:31.772491 >> OK - accepted request
2372 00:45:31.774493 Returned 0 in 0 seconds
2373 00:45:31.876200 end: 4.1 power-off (duration 00:00:00) [common]
2375 00:45:31.878424 start: 4.2 read-feedback (timeout 00:05:22) [common]
2376 00:45:31.879920 Listened to connection for namespace 'common' for up to 1s
2377 00:45:31.881386 Listened to connection for namespace 'common' for up to 1s
2378 00:45:32.879559 Finalising connection for namespace 'common'
2379 00:45:32.880332 Disconnecting from shell: Finalise
2380 00:45:32.880884 / #
2381 00:45:32.981942 end: 4.2 read-feedback (duration 00:00:01) [common]
2382 00:45:32.982737 end: 4 finalize (duration 00:00:01) [common]
2383 00:45:32.983423 Cleaning after the job
2384 00:45:32.984046 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950205/tftp-deploy-duva7m5q/ramdisk
2385 00:45:32.993345 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950205/tftp-deploy-duva7m5q/kernel
2386 00:45:32.995313 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950205/tftp-deploy-duva7m5q/dtb
2387 00:45:32.996475 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950205/tftp-deploy-duva7m5q/nfsrootfs
2388 00:45:33.028982 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950205/tftp-deploy-duva7m5q/modules
2389 00:45:33.035406 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950205
2390 00:45:35.920867 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950205
2391 00:45:35.921617 Job finished correctly