Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:00:22.356622 lava-dispatcher, installed at version: 2024.01
2 01:00:22.357416 start: 0 validate
3 01:00:22.357902 Start time: 2024-11-07 01:00:22.357872+00:00 (UTC)
4 01:00:22.358446 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:00:22.358986 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 01:00:22.400021 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:00:22.400608 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 01:00:22.427426 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:00:22.428069 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:00:23.474383 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:00:23.474928 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 01:00:23.509689 validate duration: 1.15
14 01:00:23.510562 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:00:23.510908 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:00:23.511224 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:00:23.511814 Not decompressing ramdisk as can be used compressed.
18 01:00:23.512293 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 01:00:23.512673 saving as /var/lib/lava/dispatcher/tmp/950535/tftp-deploy-ouvpyzq8/ramdisk/rootfs.cpio.gz
20 01:00:23.512975 total size: 8181887 (7 MB)
21 01:00:23.549901 progress 0 % (0 MB)
22 01:00:23.559764 progress 5 % (0 MB)
23 01:00:23.570029 progress 10 % (0 MB)
24 01:00:23.578708 progress 15 % (1 MB)
25 01:00:23.584073 progress 20 % (1 MB)
26 01:00:23.589802 progress 25 % (1 MB)
27 01:00:23.595049 progress 30 % (2 MB)
28 01:00:23.600889 progress 35 % (2 MB)
29 01:00:23.606190 progress 40 % (3 MB)
30 01:00:23.611806 progress 45 % (3 MB)
31 01:00:23.617076 progress 50 % (3 MB)
32 01:00:23.622685 progress 55 % (4 MB)
33 01:00:23.627943 progress 60 % (4 MB)
34 01:00:23.633532 progress 65 % (5 MB)
35 01:00:23.638708 progress 70 % (5 MB)
36 01:00:23.644369 progress 75 % (5 MB)
37 01:00:23.649500 progress 80 % (6 MB)
38 01:00:23.655012 progress 85 % (6 MB)
39 01:00:23.660281 progress 90 % (7 MB)
40 01:00:23.665885 progress 95 % (7 MB)
41 01:00:23.670817 progress 100 % (7 MB)
42 01:00:23.671476 7 MB downloaded in 0.16 s (49.24 MB/s)
43 01:00:23.672053 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:00:23.672962 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:00:23.673256 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:00:23.673524 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:00:23.674011 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig+debug/gcc-12/kernel/Image
49 01:00:23.674266 saving as /var/lib/lava/dispatcher/tmp/950535/tftp-deploy-ouvpyzq8/kernel/Image
50 01:00:23.674475 total size: 169943552 (162 MB)
51 01:00:23.674687 No compression specified
52 01:00:23.713586 progress 0 % (0 MB)
53 01:00:23.816532 progress 5 % (8 MB)
54 01:00:23.919066 progress 10 % (16 MB)
55 01:00:24.022378 progress 15 % (24 MB)
56 01:00:24.125753 progress 20 % (32 MB)
57 01:00:24.228470 progress 25 % (40 MB)
58 01:00:24.330896 progress 30 % (48 MB)
59 01:00:24.434052 progress 35 % (56 MB)
60 01:00:24.537165 progress 40 % (64 MB)
61 01:00:24.639271 progress 45 % (72 MB)
62 01:00:24.742421 progress 50 % (81 MB)
63 01:00:24.843738 progress 55 % (89 MB)
64 01:00:24.944650 progress 60 % (97 MB)
65 01:00:25.046264 progress 65 % (105 MB)
66 01:00:25.147330 progress 70 % (113 MB)
67 01:00:25.248426 progress 75 % (121 MB)
68 01:00:25.350073 progress 80 % (129 MB)
69 01:00:25.451776 progress 85 % (137 MB)
70 01:00:25.554111 progress 90 % (145 MB)
71 01:00:25.655661 progress 95 % (153 MB)
72 01:00:25.757164 progress 100 % (162 MB)
73 01:00:25.757759 162 MB downloaded in 2.08 s (77.80 MB/s)
74 01:00:25.758256 end: 1.2.1 http-download (duration 00:00:02) [common]
76 01:00:25.759104 end: 1.2 download-retry (duration 00:00:02) [common]
77 01:00:25.759399 start: 1.3 download-retry (timeout 00:09:58) [common]
78 01:00:25.759677 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 01:00:25.760161 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 01:00:25.760445 saving as /var/lib/lava/dispatcher/tmp/950535/tftp-deploy-ouvpyzq8/dtb/meson-g12b-a311d-libretech-cc.dtb
81 01:00:25.760665 total size: 54703 (0 MB)
82 01:00:25.760886 No compression specified
83 01:00:25.796524 progress 59 % (0 MB)
84 01:00:25.797376 progress 100 % (0 MB)
85 01:00:25.797937 0 MB downloaded in 0.04 s (1.40 MB/s)
86 01:00:25.798410 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:00:25.799252 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:00:25.799522 start: 1.4 download-retry (timeout 00:09:58) [common]
90 01:00:25.799796 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 01:00:25.800303 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 01:00:25.800560 saving as /var/lib/lava/dispatcher/tmp/950535/tftp-deploy-ouvpyzq8/modules/modules.tar
93 01:00:25.800776 total size: 27621356 (26 MB)
94 01:00:25.800994 Using unxz to decompress xz
95 01:00:25.833788 progress 0 % (0 MB)
96 01:00:26.020630 progress 5 % (1 MB)
97 01:00:26.219562 progress 10 % (2 MB)
98 01:00:26.448756 progress 15 % (3 MB)
99 01:00:26.685102 progress 20 % (5 MB)
100 01:00:26.883737 progress 25 % (6 MB)
101 01:00:27.123352 progress 30 % (7 MB)
102 01:00:27.333582 progress 35 % (9 MB)
103 01:00:27.531556 progress 40 % (10 MB)
104 01:00:27.725223 progress 45 % (11 MB)
105 01:00:27.934910 progress 50 % (13 MB)
106 01:00:28.135204 progress 55 % (14 MB)
107 01:00:28.352192 progress 60 % (15 MB)
108 01:00:28.561244 progress 65 % (17 MB)
109 01:00:28.767637 progress 70 % (18 MB)
110 01:00:28.978462 progress 75 % (19 MB)
111 01:00:29.179786 progress 80 % (21 MB)
112 01:00:29.388310 progress 85 % (22 MB)
113 01:00:29.594108 progress 90 % (23 MB)
114 01:00:29.789298 progress 95 % (25 MB)
115 01:00:29.987437 progress 100 % (26 MB)
116 01:00:30.001739 26 MB downloaded in 4.20 s (6.27 MB/s)
117 01:00:30.002347 end: 1.4.1 http-download (duration 00:00:04) [common]
119 01:00:30.003175 end: 1.4 download-retry (duration 00:00:04) [common]
120 01:00:30.003446 start: 1.5 prepare-tftp-overlay (timeout 00:09:54) [common]
121 01:00:30.003715 start: 1.5.1 extract-nfsrootfs (timeout 00:09:54) [common]
122 01:00:30.003961 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:00:30.004768 start: 1.5.2 lava-overlay (timeout 00:09:54) [common]
124 01:00:30.005823 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud
125 01:00:30.006682 makedir: /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin
126 01:00:30.007320 makedir: /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/tests
127 01:00:30.007934 makedir: /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/results
128 01:00:30.008601 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-add-keys
129 01:00:30.009560 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-add-sources
130 01:00:30.010488 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-background-process-start
131 01:00:30.011461 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-background-process-stop
132 01:00:30.012518 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-common-functions
133 01:00:30.013455 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-echo-ipv4
134 01:00:30.014349 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-install-packages
135 01:00:30.015234 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-installed-packages
136 01:00:30.016149 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-os-build
137 01:00:30.017050 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-probe-channel
138 01:00:30.017940 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-probe-ip
139 01:00:30.018871 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-target-ip
140 01:00:30.019834 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-target-mac
141 01:00:30.020811 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-target-storage
142 01:00:30.021742 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-test-case
143 01:00:30.022764 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-test-event
144 01:00:30.023695 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-test-feedback
145 01:00:30.024641 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-test-raise
146 01:00:30.025536 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-test-reference
147 01:00:30.026439 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-test-runner
148 01:00:30.027390 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-test-set
149 01:00:30.028367 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-test-shell
150 01:00:30.029294 Updating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-install-packages (oe)
151 01:00:30.030268 Updating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/bin/lava-installed-packages (oe)
152 01:00:30.031098 Creating /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/environment
153 01:00:30.031834 LAVA metadata
154 01:00:30.032379 - LAVA_JOB_ID=950535
155 01:00:30.032809 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:00:30.033486 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 01:00:30.035305 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:00:30.035931 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 01:00:30.036387 skipped lava-vland-overlay
160 01:00:30.036884 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:00:30.037397 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 01:00:30.037824 skipped lava-multinode-overlay
163 01:00:30.038313 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:00:30.038815 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 01:00:30.039296 Loading test definitions
166 01:00:30.039847 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 01:00:30.040243 Using /lava-950535 at stage 0
168 01:00:30.041685 uuid=950535_1.5.2.4.1 testdef=None
169 01:00:30.042054 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:00:30.042339 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 01:00:30.044230 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:00:30.045082 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 01:00:30.047427 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:00:30.048448 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 01:00:30.050749 runner path: /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/0/tests/0_dmesg test_uuid 950535_1.5.2.4.1
178 01:00:30.051378 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:00:30.052232 Creating lava-test-runner.conf files
181 01:00:30.052443 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950535/lava-overlay-zv1sjwud/lava-950535/0 for stage 0
182 01:00:30.052787 - 0_dmesg
183 01:00:30.053170 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:00:30.053467 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 01:00:30.077563 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:00:30.078011 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 01:00:30.078284 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:00:30.078556 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:00:30.078825 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 01:00:30.987910 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 01:00:30.988429 start: 1.5.4 extract-modules (timeout 00:09:53) [common]
192 01:00:30.988687 extracting modules file /var/lib/lava/dispatcher/tmp/950535/tftp-deploy-ouvpyzq8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950535/extract-overlay-ramdisk-2v7y4y4z/ramdisk
193 01:00:32.704042 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 01:00:32.704640 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
195 01:00:32.705013 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950535/compress-overlay-y5j5n_a9/overlay-1.5.2.5.tar.gz to ramdisk
196 01:00:32.705314 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950535/compress-overlay-y5j5n_a9/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950535/extract-overlay-ramdisk-2v7y4y4z/ramdisk
197 01:00:32.742136 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:00:32.742650 start: 1.5.6 prepare-kernel (timeout 00:09:51) [common]
199 01:00:32.742979 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:51) [common]
200 01:00:32.743258 Converting downloaded kernel to a uImage
201 01:00:32.743635 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/950535/tftp-deploy-ouvpyzq8/kernel/Image /var/lib/lava/dispatcher/tmp/950535/tftp-deploy-ouvpyzq8/kernel/uImage
202 01:00:34.454472 output: Image Name:
203 01:00:34.455009 output: Created: Thu Nov 7 01:00:32 2024
204 01:00:34.455292 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:00:34.455552 output: Data Size: 169943552 Bytes = 165960.50 KiB = 162.07 MiB
206 01:00:34.455814 output: Load Address: 01080000
207 01:00:34.456139 output: Entry Point: 01080000
208 01:00:34.456422 output:
209 01:00:34.456870 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 01:00:34.457246 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 01:00:34.457621 start: 1.5.7 configure-preseed-file (timeout 00:09:49) [common]
212 01:00:34.458015 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:00:34.458387 start: 1.5.8 compress-ramdisk (timeout 00:09:49) [common]
214 01:00:34.458736 Building ramdisk /var/lib/lava/dispatcher/tmp/950535/extract-overlay-ramdisk-2v7y4y4z/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950535/extract-overlay-ramdisk-2v7y4y4z/ramdisk
215 01:00:40.304336 >> 441545 blocks
216 01:00:59.528056 Adding RAMdisk u-boot header.
217 01:00:59.528723 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950535/extract-overlay-ramdisk-2v7y4y4z/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950535/extract-overlay-ramdisk-2v7y4y4z/ramdisk.cpio.gz.uboot
218 01:01:00.074295 output: Image Name:
219 01:01:00.074714 output: Created: Thu Nov 7 01:00:59 2024
220 01:01:00.074921 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:01:00.075127 output: Data Size: 53579729 Bytes = 52323.95 KiB = 51.10 MiB
222 01:01:00.075327 output: Load Address: 00000000
223 01:01:00.075525 output: Entry Point: 00000000
224 01:01:00.075722 output:
225 01:01:00.076694 rename /var/lib/lava/dispatcher/tmp/950535/extract-overlay-ramdisk-2v7y4y4z/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950535/tftp-deploy-ouvpyzq8/ramdisk/ramdisk.cpio.gz.uboot
226 01:01:00.077515 end: 1.5.8 compress-ramdisk (duration 00:00:26) [common]
227 01:01:00.078103 end: 1.5 prepare-tftp-overlay (duration 00:00:30) [common]
228 01:01:00.078679 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:23) [common]
229 01:01:00.079174 No LXC device requested
230 01:01:00.079716 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:01:00.080310 start: 1.7 deploy-device-env (timeout 00:09:23) [common]
232 01:01:00.080853 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:01:00.081302 Checking files for TFTP limit of 4294967296 bytes.
234 01:01:00.084226 end: 1 tftp-deploy (duration 00:00:37) [common]
235 01:01:00.084848 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:01:00.085418 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:01:00.085963 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:01:00.086508 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:01:00.087084 Using kernel file from prepare-kernel: 950535/tftp-deploy-ouvpyzq8/kernel/uImage
240 01:01:00.087761 substitutions:
241 01:01:00.088246 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:01:00.088689 - {DTB_ADDR}: 0x01070000
243 01:01:00.089128 - {DTB}: 950535/tftp-deploy-ouvpyzq8/dtb/meson-g12b-a311d-libretech-cc.dtb
244 01:01:00.089567 - {INITRD}: 950535/tftp-deploy-ouvpyzq8/ramdisk/ramdisk.cpio.gz.uboot
245 01:01:00.090004 - {KERNEL_ADDR}: 0x01080000
246 01:01:00.090437 - {KERNEL}: 950535/tftp-deploy-ouvpyzq8/kernel/uImage
247 01:01:00.090872 - {LAVA_MAC}: None
248 01:01:00.091347 - {PRESEED_CONFIG}: None
249 01:01:00.091781 - {PRESEED_LOCAL}: None
250 01:01:00.092239 - {RAMDISK_ADDR}: 0x08000000
251 01:01:00.092668 - {RAMDISK}: 950535/tftp-deploy-ouvpyzq8/ramdisk/ramdisk.cpio.gz.uboot
252 01:01:00.093102 - {ROOT_PART}: None
253 01:01:00.093534 - {ROOT}: None
254 01:01:00.093962 - {SERVER_IP}: 192.168.6.2
255 01:01:00.094394 - {TEE_ADDR}: 0x83000000
256 01:01:00.094825 - {TEE}: None
257 01:01:00.095253 Parsed boot commands:
258 01:01:00.095666 - setenv autoload no
259 01:01:00.096120 - setenv initrd_high 0xffffffff
260 01:01:00.096552 - setenv fdt_high 0xffffffff
261 01:01:00.096978 - dhcp
262 01:01:00.097406 - setenv serverip 192.168.6.2
263 01:01:00.097828 - tftpboot 0x01080000 950535/tftp-deploy-ouvpyzq8/kernel/uImage
264 01:01:00.098259 - tftpboot 0x08000000 950535/tftp-deploy-ouvpyzq8/ramdisk/ramdisk.cpio.gz.uboot
265 01:01:00.098686 - tftpboot 0x01070000 950535/tftp-deploy-ouvpyzq8/dtb/meson-g12b-a311d-libretech-cc.dtb
266 01:01:00.099109 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:01:00.099540 - bootm 0x01080000 0x08000000 0x01070000
268 01:01:00.100109 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:01:00.101734 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:01:00.102209 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 01:01:00.118709 Setting prompt string to ['lava-test: # ']
273 01:01:00.120372 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:01:00.121044 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:01:00.121636 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:01:00.122201 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:01:00.123437 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 01:01:00.165640 >> OK - accepted request
279 01:01:00.167836 Returned 0 in 0 seconds
280 01:01:00.269124 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:01:00.270877 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:01:00.271493 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:01:00.272107 Setting prompt string to ['Hit any key to stop autoboot']
285 01:01:00.272626 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:01:00.274423 Trying 192.168.56.21...
287 01:01:00.274953 Connected to conserv1.
288 01:01:00.275393 Escape character is '^]'.
289 01:01:00.275856
290 01:01:00.276363 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 01:01:00.276841
292 01:01:12.576239 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 01:01:12.576909 bl2_stage_init 0x01
294 01:01:12.577411 bl2_stage_init 0x81
295 01:01:12.581629 hw id: 0x0000 - pwm id 0x01
296 01:01:12.582204 bl2_stage_init 0xc1
297 01:01:12.582659 bl2_stage_init 0x02
298 01:01:12.583123
299 01:01:12.587099 L0:00000000
300 01:01:12.587616 L1:20000703
301 01:01:12.588102 L2:00008067
302 01:01:12.588547 L3:14000000
303 01:01:12.592736 B2:00402000
304 01:01:12.593236 B1:e0f83180
305 01:01:12.593670
306 01:01:12.594116 TE: 58124
307 01:01:12.594563
308 01:01:12.598294 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 01:01:12.598783
310 01:01:12.599212 Board ID = 1
311 01:01:12.604019 Set A53 clk to 24M
312 01:01:12.604521 Set A73 clk to 24M
313 01:01:12.604950 Set clk81 to 24M
314 01:01:12.609658 A53 clk: 1200 MHz
315 01:01:12.610153 A73 clk: 1200 MHz
316 01:01:12.610578 CLK81: 166.6M
317 01:01:12.611016 smccc: 00012a92
318 01:01:12.615129 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 01:01:12.620792 board id: 1
320 01:01:12.625637 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:01:12.637272 fw parse done
322 01:01:12.642405 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:01:12.684813 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:01:12.696706 PIEI prepare done
325 01:01:12.697263 fastboot data load
326 01:01:12.697702 fastboot data verify
327 01:01:12.702308 verify result: 266
328 01:01:12.707925 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 01:01:12.708509 LPDDR4 probe
330 01:01:12.708964 ddr clk to 1584MHz
331 01:01:12.714906 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:01:12.752305
333 01:01:12.752911 dmc_version 0001
334 01:01:12.758829 Check phy result
335 01:01:12.765723 INFO : End of CA training
336 01:01:12.766296 INFO : End of initialization
337 01:01:12.771234 INFO : Training has run successfully!
338 01:01:12.771778 Check phy result
339 01:01:12.776962 INFO : End of initialization
340 01:01:12.777517 INFO : End of read enable training
341 01:01:12.780202 INFO : End of fine write leveling
342 01:01:12.785694 INFO : End of Write leveling coarse delay
343 01:01:12.791315 INFO : Training has run successfully!
344 01:01:12.791840 Check phy result
345 01:01:12.792315 INFO : End of initialization
346 01:01:12.797139 INFO : End of read dq deskew training
347 01:01:12.802549 INFO : End of MPR read delay center optimization
348 01:01:12.803090 INFO : End of write delay center optimization
349 01:01:12.808270 INFO : End of read delay center optimization
350 01:01:12.813694 INFO : End of max read latency training
351 01:01:12.814223 INFO : Training has run successfully!
352 01:01:12.819283 1D training succeed
353 01:01:12.824363 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:01:12.872023 Check phy result
355 01:01:12.872731 INFO : End of initialization
356 01:01:12.893665 INFO : End of 2D read delay Voltage center optimization
357 01:01:12.913329 INFO : End of 2D read delay Voltage center optimization
358 01:01:12.966253 INFO : End of 2D write delay Voltage center optimization
359 01:01:13.015400 INFO : End of 2D write delay Voltage center optimization
360 01:01:13.020988 INFO : Training has run successfully!
361 01:01:13.021488
362 01:01:13.021934 channel==0
363 01:01:13.026600 RxClkDly_Margin_A0==88 ps 9
364 01:01:13.027085 TxDqDly_Margin_A0==98 ps 10
365 01:01:13.032205 RxClkDly_Margin_A1==88 ps 9
366 01:01:13.032691 TxDqDly_Margin_A1==98 ps 10
367 01:01:13.033130 TrainedVREFDQ_A0==74
368 01:01:13.037722 TrainedVREFDQ_A1==75
369 01:01:13.038187 VrefDac_Margin_A0==25
370 01:01:13.038614 DeviceVref_Margin_A0==40
371 01:01:13.043370 VrefDac_Margin_A1==25
372 01:01:13.043848 DeviceVref_Margin_A1==39
373 01:01:13.044343
374 01:01:13.044780
375 01:01:13.048985 channel==1
376 01:01:13.049461 RxClkDly_Margin_A0==88 ps 9
377 01:01:13.049897 TxDqDly_Margin_A0==98 ps 10
378 01:01:13.054585 RxClkDly_Margin_A1==88 ps 9
379 01:01:13.055056 TxDqDly_Margin_A1==88 ps 9
380 01:01:13.060134 TrainedVREFDQ_A0==77
381 01:01:13.060594 TrainedVREFDQ_A1==77
382 01:01:13.061027 VrefDac_Margin_A0==23
383 01:01:13.065762 DeviceVref_Margin_A0==37
384 01:01:13.066227 VrefDac_Margin_A1==24
385 01:01:13.071365 DeviceVref_Margin_A1==37
386 01:01:13.071835
387 01:01:13.072322 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:01:13.072761
389 01:01:13.105021 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 01:01:13.105600 2D training succeed
391 01:01:13.110548 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:01:13.116166 auto size-- 65535DDR cs0 size: 2048MB
393 01:01:13.116638 DDR cs1 size: 2048MB
394 01:01:13.121743 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:01:13.122231 cs0 DataBus test pass
396 01:01:13.127375 cs1 DataBus test pass
397 01:01:13.127851 cs0 AddrBus test pass
398 01:01:13.128317 cs1 AddrBus test pass
399 01:01:13.128742
400 01:01:13.133018 100bdlr_step_size ps== 420
401 01:01:13.133496 result report
402 01:01:13.138538 boot times 0Enable ddr reg access
403 01:01:13.143845 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:01:13.157326 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 01:01:13.731047 0.0;M3 CHK:0;cm4_sp_mode 0
406 01:01:13.731473 MVN_1=0x00000000
407 01:01:13.736378 MVN_2=0x00000000
408 01:01:13.742162 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 01:01:13.742680 OPS=0x10
410 01:01:13.743128 ring efuse init
411 01:01:13.743570 chipver efuse init
412 01:01:13.747724 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 01:01:13.753373 [0.018961 Inits done]
414 01:01:13.753952 secure task start!
415 01:01:13.754392 high task start!
416 01:01:13.758067 low task start!
417 01:01:13.758553 run into bl31
418 01:01:13.764731 NOTICE: BL31: v1.3(release):4fc40b1
419 01:01:13.771636 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 01:01:13.772227 NOTICE: BL31: G12A normal boot!
421 01:01:13.798013 NOTICE: BL31: BL33 decompress pass
422 01:01:13.803553 ERROR: Error initializing runtime service opteed_fast
423 01:01:15.036419
424 01:01:15.037050
425 01:01:15.044727 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 01:01:15.045235
427 01:01:15.045699 Model: Libre Computer AML-A311D-CC Alta
428 01:01:15.253210 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 01:01:15.276564 DRAM: 2 GiB (effective 3.8 GiB)
430 01:01:15.419600 Core: 408 devices, 31 uclasses, devicetree: separate
431 01:01:15.424419 WDT: Not starting watchdog@f0d0
432 01:01:15.457587 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 01:01:15.470073 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 01:01:15.475020 ** Bad device specification mmc 0 **
435 01:01:15.485414 Card did not respond to voltage select! : -110
436 01:01:15.492452 ** Bad device specification mmc 0 **
437 01:01:16.727657 Couldn't find partition G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
438 01:01:16.728483 bl2_stage_init 0x01
439 01:01:16.729108 bl2_stage_init 0x81
440 01:01:16.733138 hw id: 0x0000 - pwm id 0x01
441 01:01:16.733438 bl2_stage_init 0xc1
442 01:01:16.734030 bl2_stage_init 0x02
443 01:01:16.734413
444 01:01:16.738705 L0:00000000
445 01:01:16.739278 L1:20000703
446 01:01:16.739726 L2:00008067
447 01:01:16.740207 L3:14000000
448 01:01:16.744320 B2:00402000
449 01:01:16.744919 B1:e0f83180
450 01:01:16.745391
451 01:01:16.745833 TE: 58159
452 01:01:16.746271
453 01:01:16.749965 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
454 01:01:16.750518
455 01:01:16.750960 Board ID = 1
456 01:01:16.755587 Set A53 clk to 24M
457 01:01:16.755934 Set A73 clk to 24M
458 01:01:16.756164 Set clk81 to 24M
459 01:01:16.761215 A53 clk: 1200 MHz
460 01:01:16.761770 A73 clk: 1200 MHz
461 01:01:16.762213 CLK81: 166.6M
462 01:01:16.762647 smccc: 00012ab4
463 01:01:16.766724 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
464 01:01:16.772324 board id: 1
465 01:01:16.777357 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
466 01:01:16.788935 fw parse done
467 01:01:16.794873 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
468 01:01:16.837462 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
469 01:01:16.848320 PIEI prepare done
470 01:01:16.848663 fastboot data load
471 01:01:16.848881 fastboot data verify
472 01:01:16.854026 verify result: 266
473 01:01:16.859572 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
474 01:01:16.860237 LPDDR4 probe
475 01:01:16.860740 ddr clk to 1584MHz
476 01:01:16.866651 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
477 01:01:16.904897
478 01:01:16.905488 dmc_version 0001
479 01:01:16.911551 Check phy result
480 01:01:16.917409 INFO : End of CA training
481 01:01:16.917945 INFO : End of initialization
482 01:01:16.922965 INFO : Training has run successfully!
483 01:01:16.923274 Check phy result
484 01:01:16.928596 INFO : End of initialization
485 01:01:16.929132 INFO : End of read enable training
486 01:01:16.934236 INFO : End of fine write leveling
487 01:01:16.939800 INFO : End of Write leveling coarse delay
488 01:01:16.940363 INFO : Training has run successfully!
489 01:01:16.940804 Check phy result
490 01:01:16.945405 INFO : End of initialization
491 01:01:16.945930 INFO : End of read dq deskew training
492 01:01:16.951020 INFO : End of MPR read delay center optimization
493 01:01:16.956670 INFO : End of write delay center optimization
494 01:01:16.962175 INFO : End of read delay center optimization
495 01:01:16.962511 INFO : End of max read latency training
496 01:01:16.967667 INFO : Training has run successfully!
497 01:01:16.968016 1D training succeed
498 01:01:16.976832 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
499 01:01:17.024511 Check phy result
500 01:01:17.024904 INFO : End of initialization
501 01:01:17.046354 INFO : End of 2D read delay Voltage center optimization
502 01:01:17.066532 INFO : End of 2D read delay Voltage center optimization
503 01:01:17.118021 INFO : End of 2D write delay Voltage center optimization
504 01:01:17.167910 INFO : End of 2D write delay Voltage center optimization
505 01:01:17.173569 INFO : Training has run successfully!
506 01:01:17.173889
507 01:01:17.174108 channel==0
508 01:01:17.179062 RxClkDly_Margin_A0==88 ps 9
509 01:01:17.179383 TxDqDly_Margin_A0==98 ps 10
510 01:01:17.184839 RxClkDly_Margin_A1==88 ps 9
511 01:01:17.185158 TxDqDly_Margin_A1==98 ps 10
512 01:01:17.185370 TrainedVREFDQ_A0==74
513 01:01:17.190527 TrainedVREFDQ_A1==74
514 01:01:17.190897 VrefDac_Margin_A0==25
515 01:01:17.191120 DeviceVref_Margin_A0==40
516 01:01:17.195959 VrefDac_Margin_A1==25
517 01:01:17.196351 DeviceVref_Margin_A1==40
518 01:01:17.196560
519 01:01:17.196761
520 01:01:17.201573 channel==1
521 01:01:17.201922 RxClkDly_Margin_A0==98 ps 10
522 01:01:17.202137 TxDqDly_Margin_A0==88 ps 9
523 01:01:17.207697 RxClkDly_Margin_A1==88 ps 9
524 01:01:17.208420 TxDqDly_Margin_A1==98 ps 10
525 01:01:17.212760 TrainedVREFDQ_A0==76
526 01:01:17.213360 TrainedVREFDQ_A1==77
527 01:01:17.213835 VrefDac_Margin_A0==22
528 01:01:17.218411 DeviceVref_Margin_A0==38
529 01:01:17.219022 VrefDac_Margin_A1==24
530 01:01:17.224012 DeviceVref_Margin_A1==37
531 01:01:17.224622
532 01:01:17.225070 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
533 01:01:17.225509
534 01:01:17.257714 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
535 01:01:17.258353 2D training succeed
536 01:01:17.263182 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
537 01:01:17.268799 auto size-- 65535DDR cs0 size: 2048MB
538 01:01:17.269406 DDR cs1 size: 2048MB
539 01:01:17.274378 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
540 01:01:17.274974 cs0 DataBus test pass
541 01:01:17.279976 cs1 DataBus test pass
542 01:01:17.280584 cs0 AddrBus test pass
543 01:01:17.281045 cs1 AddrBus test pass
544 01:01:17.281513
545 01:01:17.285717 100bdlr_step_size ps== 420
546 01:01:17.286309 result report
547 01:01:17.291129 boot times 0Enable ddr reg access
548 01:01:17.296505 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
549 01:01:17.309934 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
550 01:01:17.883646 0.0;M3 CHK:0;cm4_sp_mode 0
551 01:01:17.884359 MVN_1=0x00000000
552 01:01:17.889175 MVN_2=0x00000000
553 01:01:17.894831 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
554 01:01:17.895325 OPS=0x10
555 01:01:17.895766 ring efuse init
556 01:01:17.896234 chipver efuse init
557 01:01:17.900512 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
558 01:01:17.906132 [0.018960 Inits done]
559 01:01:17.906647 secure task start!
560 01:01:17.907078 high task start!
561 01:01:17.910640 low task start!
562 01:01:17.911140 run into bl31
563 01:01:17.917431 NOTICE: BL31: v1.3(release):4fc40b1
564 01:01:17.925053 NOTICE: BL31: Built : 15:58:17, May 22 2019
565 01:01:17.925571 NOTICE: BL31: G12A normal boot!
566 01:01:17.950431 NOTICE: BL31: BL33 decompress pass
567 01:01:17.956210 ERROR: Error initializing runtime service opteed_fast
568 01:01:19.189028
569 01:01:19.189668
570 01:01:19.197410 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
571 01:01:19.197943
572 01:01:19.198404 Model: Libre Computer AML-A311D-CC Alta
573 01:01:19.405786 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
574 01:01:19.429317 DRAM: 2 GiB (effective 3.8 GiB)
575 01:01:19.572299 Core: 408 devices, 31 uclasses, devicetree: separate
576 01:01:19.577487 WDT: Not starting watchdog@f0d0
577 01:01:19.610378 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
578 01:01:19.622808 Loading Environment from FAT... Card did not respond to voltage select! : -110
579 01:01:19.627826 ** Bad device specification mmc 0 **
580 01:01:19.638097 Card did not respond to voltage select! : -110
581 01:01:19.645853 ** Bad device specification mmc 0 **
582 01:01:19.646370 Couldn't find partition mmc 0
583 01:01:19.654301 Card did not respond to voltage select! : -110
584 01:01:19.659602 ** Bad device specification mmc 0 **
585 01:01:19.660122 Couldn't find partition mmc 0
586 01:01:19.664619 Error: could not access storage.
587 01:01:20.007177 Net: eth0: ethernet@ff3f0000
588 01:01:20.007779 starting USB...
589 01:01:20.259066 Bus usb@ff500000: Register 3000140 NbrPorts 3
590 01:01:20.259661 Starting the controller
591 01:01:20.266089 USB XHCI 1.10
592 01:01:21.976347 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
593 01:01:21.976989 bl2_stage_init 0x01
594 01:01:21.977460 bl2_stage_init 0x81
595 01:01:21.981926 hw id: 0x0000 - pwm id 0x01
596 01:01:21.982439 bl2_stage_init 0xc1
597 01:01:21.982894 bl2_stage_init 0x02
598 01:01:21.983336
599 01:01:21.987483 L0:00000000
600 01:01:21.988023 L1:20000703
601 01:01:21.988483 L2:00008067
602 01:01:21.988926 L3:14000000
603 01:01:21.992982 B2:00402000
604 01:01:21.993491 B1:e0f83180
605 01:01:21.993940
606 01:01:21.994382 TE: 58124
607 01:01:21.994823
608 01:01:21.998680 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
609 01:01:21.999189
610 01:01:21.999636 Board ID = 1
611 01:01:22.004500 Set A53 clk to 24M
612 01:01:22.005011 Set A73 clk to 24M
613 01:01:22.005456 Set clk81 to 24M
614 01:01:22.009751 A53 clk: 1200 MHz
615 01:01:22.010255 A73 clk: 1200 MHz
616 01:01:22.010701 CLK81: 166.6M
617 01:01:22.011142 smccc: 00012a92
618 01:01:22.015446 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
619 01:01:22.021025 board id: 1
620 01:01:22.026896 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
621 01:01:22.037526 fw parse done
622 01:01:22.043443 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
623 01:01:22.086064 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
624 01:01:22.096998 PIEI prepare done
625 01:01:22.097519 fastboot data load
626 01:01:22.097973 fastboot data verify
627 01:01:22.102646 verify result: 266
628 01:01:22.108375 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
629 01:01:22.108882 LPDDR4 probe
630 01:01:22.109324 ddr clk to 1584MHz
631 01:01:22.116302 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
632 01:01:22.153564
633 01:01:22.154097 dmc_version 0001
634 01:01:22.160290 Check phy result
635 01:01:22.166028 INFO : End of CA training
636 01:01:22.166535 INFO : End of initialization
637 01:01:22.171700 INFO : Training has run successfully!
638 01:01:22.172242 Check phy result
639 01:01:22.177459 INFO : End of initialization
640 01:01:22.177964 INFO : End of read enable training
641 01:01:22.180608 INFO : End of fine write leveling
642 01:01:22.186131 INFO : End of Write leveling coarse delay
643 01:01:22.191701 INFO : Training has run successfully!
644 01:01:22.192235 Check phy result
645 01:01:22.192684 INFO : End of initialization
646 01:01:22.197389 INFO : End of read dq deskew training
647 01:01:22.203016 INFO : End of MPR read delay center optimization
648 01:01:22.203524 INFO : End of write delay center optimization
649 01:01:22.208544 INFO : End of read delay center optimization
650 01:01:22.214141 INFO : End of max read latency training
651 01:01:22.214641 INFO : Training has run successfully!
652 01:01:22.219778 1D training succeed
653 01:01:22.225793 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
654 01:01:22.273268 Check phy result
655 01:01:22.273830 INFO : End of initialization
656 01:01:22.295792 INFO : End of 2D read delay Voltage center optimization
657 01:01:22.316046 INFO : End of 2D read delay Voltage center optimization
658 01:01:22.367397 INFO : End of 2D write delay Voltage center optimization
659 01:01:22.417588 INFO : End of 2D write delay Voltage center optimization
660 01:01:22.423065 INFO : Training has run successfully!
661 01:01:22.423588
662 01:01:22.424091 channel==0
663 01:01:22.428717 RxClkDly_Margin_A0==88 ps 9
664 01:01:22.429236 TxDqDly_Margin_A0==98 ps 10
665 01:01:22.432135 RxClkDly_Margin_A1==88 ps 9
666 01:01:22.432649 TxDqDly_Margin_A1==98 ps 10
667 01:01:22.437672 TrainedVREFDQ_A0==74
668 01:01:22.438195 TrainedVREFDQ_A1==74
669 01:01:22.438650 VrefDac_Margin_A0==24
670 01:01:22.443159 DeviceVref_Margin_A0==40
671 01:01:22.443672 VrefDac_Margin_A1==24
672 01:01:22.449097 DeviceVref_Margin_A1==40
673 01:01:22.449630
674 01:01:22.450078
675 01:01:22.450521 channel==1
676 01:01:22.450956 RxClkDly_Margin_A0==98 ps 10
677 01:01:22.454526 TxDqDly_Margin_A0==98 ps 10
678 01:01:22.455040 RxClkDly_Margin_A1==98 ps 10
679 01:01:22.460100 TxDqDly_Margin_A1==88 ps 9
680 01:01:22.460614 TrainedVREFDQ_A0==77
681 01:01:22.461067 TrainedVREFDQ_A1==77
682 01:01:22.465553 VrefDac_Margin_A0==22
683 01:01:22.466065 DeviceVref_Margin_A0==37
684 01:01:22.471122 VrefDac_Margin_A1==22
685 01:01:22.471638 DeviceVref_Margin_A1==37
686 01:01:22.472116
687 01:01:22.476732 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
688 01:01:22.477250
689 01:01:22.504717 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
690 01:01:22.510463 2D training succeed
691 01:01:22.515952 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
692 01:01:22.516505 auto size-- 65535DDR cs0 size: 2048MB
693 01:01:22.521561 DDR cs1 size: 2048MB
694 01:01:22.522067 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
695 01:01:22.527155 cs0 DataBus test pass
696 01:01:22.527671 cs1 DataBus test pass
697 01:01:22.528173 cs0 AddrBus test pass
698 01:01:22.532767 cs1 AddrBus test pass
699 01:01:22.533279
700 01:01:22.533731 100bdlr_step_size ps== 420
701 01:01:22.534183 result report
702 01:01:22.538409 boot times 0Enable ddr reg access
703 01:01:22.546150 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
704 01:01:22.558677 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
705 01:01:23.133435 0.0;M3 CHK:0;cm4_sp_mode 0
706 01:01:23.134047 MVN_1=0x00000000
707 01:01:23.138845 MVN_2=0x00000000
708 01:01:23.144639 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
709 01:01:23.145208 OPS=0x10
710 01:01:23.145656 ring efuse init
711 01:01:23.146091 chipver efuse init
712 01:01:23.152813 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
713 01:01:23.153336 [0.018961 Inits done]
714 01:01:23.160285 secure task start!
715 01:01:23.160780 high task start!
716 01:01:23.161206 low task start!
717 01:01:23.161628 run into bl31
718 01:01:23.167002 NOTICE: BL31: v1.3(release):4fc40b1
719 01:01:23.174859 NOTICE: BL31: Built : 15:58:17, May 22 2019
720 01:01:23.175358 NOTICE: BL31: G12A normal boot!
721 01:01:23.200179 NOTICE: BL31: BL33 decompress pass
722 01:01:23.205823 ERROR: Error initializing runtime service opteed_fast
723 01:01:24.438537
724 01:01:24.438952
725 01:01:24.447213 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
726 01:01:24.447516
727 01:01:24.447736 Model: Libre Computer AML-A311D-CC Alta
728 01:01:24.862522 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
729 01:01:24.863070 DRAM: 2 GiB (effective 3.8 GiB)
730 01:01:24.863589 Core: 408 devices, 31 uclasses, devicetree: separate
731 01:01:24.863846 WDT: Not starting watchdog@f0d0
732 01:01:24.865423 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
733 01:01:24.872492 Loading Environment from FAT... Card did not respond to voltage select! : -110
734 01:01:24.877470 ** Bad device specification mmc 0 **
735 01:01:24.887804 Card did not respond to voltage select! : -110
736 01:01:24.895437 ** Bad device specification mmc 0 **
737 01:01:24.895754 Couldn't find partition mmc 0
738 01:01:24.903836 Card did not respond to voltage select! : -110
739 01:01:24.909261 ** Bad device specification mmc 0 **
740 01:01:24.909565 Couldn't find partition mmc 0
741 01:01:24.914309 Error: could not access storage.
742 01:01:25.256793 Net: eth0: ethernet@ff3f0000
743 01:01:25.257220 starting USB...
744 01:01:25.508528 Bus usb@ff500000: Register 3000140 NbrPorts 3
745 01:01:25.508941 Starting the controller
746 01:01:25.515536 USB XHCI 1.10
747 01:01:27.676665 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
748 01:01:27.677336 bl2_stage_init 0x01
749 01:01:27.677802 bl2_stage_init 0x81
750 01:01:27.682218 hw id: 0x0000 - pwm id 0x01
751 01:01:27.682759 bl2_stage_init 0xc1
752 01:01:27.683216 bl2_stage_init 0x02
753 01:01:27.683660
754 01:01:27.687853 L0:00000000
755 01:01:27.688397 L1:20000703
756 01:01:27.688851 L2:00008067
757 01:01:27.689293 L3:14000000
758 01:01:27.693533 B2:00402000
759 01:01:27.694045 B1:e0f83180
760 01:01:27.694493
761 01:01:27.694935 TE: 58150
762 01:01:27.695372
763 01:01:27.699234 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
764 01:01:27.699767
765 01:01:27.700276 Board ID = 1
766 01:01:27.704692 Set A53 clk to 24M
767 01:01:27.705210 Set A73 clk to 24M
768 01:01:27.705660 Set clk81 to 24M
769 01:01:27.710230 A53 clk: 1200 MHz
770 01:01:27.710739 A73 clk: 1200 MHz
771 01:01:27.711186 CLK81: 166.6M
772 01:01:27.711625 smccc: 00012aad
773 01:01:27.715783 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
774 01:01:27.721496 board id: 1
775 01:01:27.727150 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
776 01:01:27.737805 fw parse done
777 01:01:27.743875 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
778 01:01:27.786423 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
779 01:01:27.797367 PIEI prepare done
780 01:01:27.797885 fastboot data load
781 01:01:27.798340 fastboot data verify
782 01:01:27.803108 verify result: 266
783 01:01:27.808585 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
784 01:01:27.809096 LPDDR4 probe
785 01:01:27.809547 ddr clk to 1584MHz
786 01:01:27.816573 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
787 01:01:27.853775
788 01:01:27.854310 dmc_version 0001
789 01:01:27.860459 Check phy result
790 01:01:27.866339 INFO : End of CA training
791 01:01:27.866845 INFO : End of initialization
792 01:01:27.871866 INFO : Training has run successfully!
793 01:01:27.872414 Check phy result
794 01:01:27.877510 INFO : End of initialization
795 01:01:27.878016 INFO : End of read enable training
796 01:01:27.880858 INFO : End of fine write leveling
797 01:01:27.886461 INFO : End of Write leveling coarse delay
798 01:01:27.892102 INFO : Training has run successfully!
799 01:01:27.892612 Check phy result
800 01:01:27.893060 INFO : End of initialization
801 01:01:27.897672 INFO : End of read dq deskew training
802 01:01:27.903229 INFO : End of MPR read delay center optimization
803 01:01:27.903739 INFO : End of write delay center optimization
804 01:01:27.908841 INFO : End of read delay center optimization
805 01:01:27.914448 INFO : End of max read latency training
806 01:01:27.914947 INFO : Training has run successfully!
807 01:01:27.920093 1D training succeed
808 01:01:27.925954 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
809 01:01:27.973517 Check phy result
810 01:01:27.974068 INFO : End of initialization
811 01:01:27.995324 INFO : End of 2D read delay Voltage center optimization
812 01:01:28.015651 INFO : End of 2D read delay Voltage center optimization
813 01:01:28.067692 INFO : End of 2D write delay Voltage center optimization
814 01:01:28.117003 INFO : End of 2D write delay Voltage center optimization
815 01:01:28.122541 INFO : Training has run successfully!
816 01:01:28.123049
817 01:01:28.123499 channel==0
818 01:01:28.128196 RxClkDly_Margin_A0==88 ps 9
819 01:01:28.128706 TxDqDly_Margin_A0==98 ps 10
820 01:01:28.133749 RxClkDly_Margin_A1==88 ps 9
821 01:01:28.134252 TxDqDly_Margin_A1==98 ps 10
822 01:01:28.134715 TrainedVREFDQ_A0==74
823 01:01:28.139408 TrainedVREFDQ_A1==74
824 01:01:28.139941 VrefDac_Margin_A0==25
825 01:01:28.140464 DeviceVref_Margin_A0==40
826 01:01:28.144868 VrefDac_Margin_A1==24
827 01:01:28.145382 DeviceVref_Margin_A1==40
828 01:01:28.145810
829 01:01:28.146235
830 01:01:28.150533 channel==1
831 01:01:28.151028 RxClkDly_Margin_A0==98 ps 10
832 01:01:28.151456 TxDqDly_Margin_A0==98 ps 10
833 01:01:28.156107 RxClkDly_Margin_A1==88 ps 9
834 01:01:28.156599 TxDqDly_Margin_A1==88 ps 9
835 01:01:28.161689 TrainedVREFDQ_A0==77
836 01:01:28.162184 TrainedVREFDQ_A1==77
837 01:01:28.162615 VrefDac_Margin_A0==22
838 01:01:28.167337 DeviceVref_Margin_A0==37
839 01:01:28.167825 VrefDac_Margin_A1==24
840 01:01:28.172894 DeviceVref_Margin_A1==37
841 01:01:28.173390
842 01:01:28.173820 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
843 01:01:28.174244
844 01:01:28.206497 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
845 01:01:28.207073 2D training succeed
846 01:01:28.212121 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
847 01:01:28.217680 auto size-- 65535DDR cs0 size: 2048MB
848 01:01:28.218173 DDR cs1 size: 2048MB
849 01:01:28.223290 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
850 01:01:28.223781 cs0 DataBus test pass
851 01:01:28.228867 cs1 DataBus test pass
852 01:01:28.229362 cs0 AddrBus test pass
853 01:01:28.229789 cs1 AddrBus test pass
854 01:01:28.230206
855 01:01:28.234516 100bdlr_step_size ps== 420
856 01:01:28.235014 result report
857 01:01:28.240104 boot times 0Enable ddr reg access
858 01:01:28.245419 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
859 01:01:28.258757 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
860 01:01:28.832156 0.0;M3 CHK:0;cm4_sp_mode 0
861 01:01:28.832818 MVN_1=0x00000000
862 01:01:28.837583 MVN_2=0x00000000
863 01:01:28.843329 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
864 01:01:28.843898 OPS=0x10
865 01:01:28.844404 ring efuse init
866 01:01:28.844854 chipver efuse init
867 01:01:28.852255 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
868 01:01:28.852941 [0.018961 Inits done]
869 01:01:28.853399 secure task start!
870 01:01:28.859827 high task start!
871 01:01:28.860521 low task start!
872 01:01:28.860968 run into bl31
873 01:01:28.865780 NOTICE: BL31: v1.3(release):4fc40b1
874 01:01:28.873756 NOTICE: BL31: Built : 15:58:17, May 22 2019
875 01:01:28.874372 NOTICE: BL31: G12A normal boot!
876 01:01:28.899911 NOTICE: BL31: BL33 decompress pass
877 01:01:28.904924 ERROR: Error initializing runtime service opteed_fast
878 01:01:30.137445
879 01:01:30.138109
880 01:01:30.146025 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
881 01:01:30.146545
882 01:01:30.147005 Model: Libre Computer AML-A311D-CC Alta
883 01:01:30.354342 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
884 01:01:30.377674 DRAM: 2 GiB (effective 3.8 GiB)
885 01:01:30.520650 Core: 408 devices, 31 uclasses, devicetree: separate
886 01:01:30.526480 WDT: Not starting watchdog@f0d0
887 01:01:30.558792 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
888 01:01:30.571340 Loading Environment from FAT... Card did not respond to voltage select! : -110
889 01:01:30.576282 ** Bad device specification mmc 0 **
890 01:01:30.586567 Card did not respond to voltage select! : -110
891 01:01:30.594240 ** Bad device specification mmc 0 **
892 01:01:30.594739 Couldn't find partition mmc 0
893 01:01:30.602535 Card did not respond to voltage select! : -110
894 01:01:30.608131 ** Bad device specification mmc 0 **
895 01:01:30.608633 Couldn't find partition mmc 0
896 01:01:30.613166 Error: could not access storage.
897 01:01:30.955587 Net: eth0: ethernet@ff3f0000
898 01:01:30.956246 starting USB...
899 01:01:31.207469 Bus usb@ff500000: Register 3000140 NbrPorts 3
900 01:01:31.208057 Starting the controller
901 01:01:31.214354 USB XHCI 1.10
902 01:01:32.768223 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
903 01:01:32.776782 scanning usb for storage devices... 0 Storage Device(s) found
905 01:01:32.828363 Hit any key to stop autoboot: 1
906 01:01:32.829221 end: 2.4.2 bootloader-interrupt (duration 00:00:33) [common]
907 01:01:32.830008 start: 2.4.3 bootloader-commands (timeout 00:04:27) [common]
908 01:01:32.830535 Setting prompt string to ['=>']
909 01:01:32.831058 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:27)
910 01:01:32.844105 0
911 01:01:32.845049 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
912 01:01:32.845592 Sending with 10 millisecond of delay
914 01:01:33.980548 => setenv autoload no
915 01:01:33.991367 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
916 01:01:33.996773 setenv autoload no
917 01:01:33.997548 Sending with 10 millisecond of delay
919 01:01:35.794723 => setenv initrd_high 0xffffffff
920 01:01:35.805513 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
921 01:01:35.806417 setenv initrd_high 0xffffffff
922 01:01:35.807172 Sending with 10 millisecond of delay
924 01:01:37.424063 => setenv fdt_high 0xffffffff
925 01:01:37.434873 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
926 01:01:37.435753 setenv fdt_high 0xffffffff
927 01:01:37.436562 Sending with 10 millisecond of delay
929 01:01:37.728493 => dhcp
930 01:01:37.739221 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
931 01:01:37.740113 dhcp
932 01:01:37.740588 Speed: 1000, full duplex
933 01:01:37.741042 BOOTP broadcast 1
934 01:01:37.748308 DHCP client bound to address 192.168.6.27 (9 ms)
935 01:01:37.749069 Sending with 10 millisecond of delay
937 01:01:39.426157 => setenv serverip 192.168.6.2
938 01:01:39.437046 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
939 01:01:39.438119 setenv serverip 192.168.6.2
940 01:01:39.438873 Sending with 10 millisecond of delay
942 01:01:43.162755 => tftpboot 0x01080000 950535/tftp-deploy-ouvpyzq8/kernel/uImage
943 01:01:43.173321 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
944 01:01:43.173866 tftpboot 0x01080000 950535/tftp-deploy-ouvpyzq8/kernel/uImage
945 01:01:43.174143 Speed: 1000, full duplex
946 01:01:43.174376 Using ethernet@ff3f0000 device
947 01:01:43.176137 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
948 01:01:43.181620 Filename '950535/tftp-deploy-ouvpyzq8/kernel/uImage'.
949 01:01:43.185545 Load address: 0x1080000
950 01:01:47.493560 Loading: *###################
951 01:01:47.494227 TFTP error: trying to overwrite reserved memory...
953 01:01:47.495763 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
956 01:01:47.497779 end: 2.4 uboot-commands (duration 00:00:47) [common]
958 01:01:47.499224 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
960 01:01:47.500353 end: 2 uboot-action (duration 00:00:47) [common]
962 01:01:47.501981 Cleaning after the job
963 01:01:47.502570 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950535/tftp-deploy-ouvpyzq8/ramdisk
964 01:01:47.532624 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950535/tftp-deploy-ouvpyzq8/kernel
965 01:01:47.589790 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950535/tftp-deploy-ouvpyzq8/dtb
966 01:01:47.590687 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950535/tftp-deploy-ouvpyzq8/modules
967 01:01:47.648488 start: 4.1 power-off (timeout 00:00:30) [common]
968 01:01:47.649182 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
969 01:01:47.682687 >> OK - accepted request
970 01:01:47.684900 Returned 0 in 0 seconds
971 01:01:47.785947 end: 4.1 power-off (duration 00:00:00) [common]
973 01:01:47.786873 start: 4.2 read-feedback (timeout 00:10:00) [common]
974 01:01:47.787522 Listened to connection for namespace 'common' for up to 1s
975 01:01:48.787828 Finalising connection for namespace 'common'
976 01:01:48.788619 Disconnecting from shell: Finalise
977 01:01:48.789186 =>
978 01:01:48.890257 end: 4.2 read-feedback (duration 00:00:01) [common]
979 01:01:48.891017 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950535
980 01:01:49.235019 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950535
981 01:01:49.235635 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.