Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:21:23.197564 lava-dispatcher, installed at version: 2024.01
2 01:21:23.198322 start: 0 validate
3 01:21:23.198806 Start time: 2024-11-07 01:21:23.198777+00:00 (UTC)
4 01:21:23.199334 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:21:23.199862 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:21:23.244872 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:21:23.245398 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 01:21:23.277625 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:21:23.278246 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:21:23.312760 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:21:23.313246 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:21:23.346721 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:21:23.347194 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
14 01:21:23.390670 validate duration: 0.19
16 01:21:23.392186 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:21:23.392798 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:21:23.393393 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:21:23.394338 Not decompressing ramdisk as can be used compressed.
20 01:21:23.395086 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 01:21:23.395600 saving as /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/ramdisk/initrd.cpio.gz
22 01:21:23.396139 total size: 5628182 (5 MB)
23 01:21:23.439482 progress 0 % (0 MB)
24 01:21:23.447333 progress 5 % (0 MB)
25 01:21:23.455302 progress 10 % (0 MB)
26 01:21:23.462181 progress 15 % (0 MB)
27 01:21:23.470032 progress 20 % (1 MB)
28 01:21:23.476610 progress 25 % (1 MB)
29 01:21:23.480653 progress 30 % (1 MB)
30 01:21:23.484741 progress 35 % (1 MB)
31 01:21:23.488505 progress 40 % (2 MB)
32 01:21:23.492528 progress 45 % (2 MB)
33 01:21:23.496106 progress 50 % (2 MB)
34 01:21:23.500217 progress 55 % (2 MB)
35 01:21:23.504230 progress 60 % (3 MB)
36 01:21:23.507806 progress 65 % (3 MB)
37 01:21:23.511817 progress 70 % (3 MB)
38 01:21:23.515458 progress 75 % (4 MB)
39 01:21:23.519634 progress 80 % (4 MB)
40 01:21:23.523232 progress 85 % (4 MB)
41 01:21:23.527279 progress 90 % (4 MB)
42 01:21:23.531285 progress 95 % (5 MB)
43 01:21:23.534582 progress 100 % (5 MB)
44 01:21:23.535218 5 MB downloaded in 0.14 s (38.59 MB/s)
45 01:21:23.535777 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:21:23.536693 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:21:23.536982 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:21:23.537250 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:21:23.537790 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig+kselftest/gcc-12/kernel/Image
51 01:21:23.538043 saving as /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/kernel/Image
52 01:21:23.538253 total size: 66443776 (63 MB)
53 01:21:23.538463 No compression specified
54 01:21:23.577198 progress 0 % (0 MB)
55 01:21:23.618240 progress 5 % (3 MB)
56 01:21:23.659427 progress 10 % (6 MB)
57 01:21:23.700668 progress 15 % (9 MB)
58 01:21:23.741647 progress 20 % (12 MB)
59 01:21:23.781724 progress 25 % (15 MB)
60 01:21:23.822600 progress 30 % (19 MB)
61 01:21:23.862770 progress 35 % (22 MB)
62 01:21:23.902867 progress 40 % (25 MB)
63 01:21:23.943302 progress 45 % (28 MB)
64 01:21:23.983055 progress 50 % (31 MB)
65 01:21:24.023872 progress 55 % (34 MB)
66 01:21:24.063928 progress 60 % (38 MB)
67 01:21:24.104260 progress 65 % (41 MB)
68 01:21:24.144623 progress 70 % (44 MB)
69 01:21:24.184671 progress 75 % (47 MB)
70 01:21:24.225392 progress 80 % (50 MB)
71 01:21:24.265451 progress 85 % (53 MB)
72 01:21:24.305457 progress 90 % (57 MB)
73 01:21:24.346228 progress 95 % (60 MB)
74 01:21:24.385697 progress 100 % (63 MB)
75 01:21:24.386395 63 MB downloaded in 0.85 s (74.71 MB/s)
76 01:21:24.386877 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:21:24.387696 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:21:24.387969 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:21:24.388264 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:21:24.388736 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:21:24.389005 saving as /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:21:24.389211 total size: 54703 (0 MB)
84 01:21:24.389419 No compression specified
85 01:21:24.428424 progress 59 % (0 MB)
86 01:21:24.429262 progress 100 % (0 MB)
87 01:21:24.429795 0 MB downloaded in 0.04 s (1.29 MB/s)
88 01:21:24.430247 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:21:24.431059 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:21:24.431317 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:21:24.431576 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:21:24.432042 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 01:21:24.432291 saving as /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/nfsrootfs/full.rootfs.tar
95 01:21:24.432496 total size: 107552908 (102 MB)
96 01:21:24.432704 Using unxz to decompress xz
97 01:21:24.469361 progress 0 % (0 MB)
98 01:21:25.125913 progress 5 % (5 MB)
99 01:21:25.848992 progress 10 % (10 MB)
100 01:21:26.569625 progress 15 % (15 MB)
101 01:21:27.316968 progress 20 % (20 MB)
102 01:21:27.884875 progress 25 % (25 MB)
103 01:21:28.504251 progress 30 % (30 MB)
104 01:21:29.241353 progress 35 % (35 MB)
105 01:21:29.588170 progress 40 % (41 MB)
106 01:21:30.013790 progress 45 % (46 MB)
107 01:21:30.709701 progress 50 % (51 MB)
108 01:21:31.397557 progress 55 % (56 MB)
109 01:21:32.157686 progress 60 % (61 MB)
110 01:21:32.909244 progress 65 % (66 MB)
111 01:21:33.632834 progress 70 % (71 MB)
112 01:21:34.391911 progress 75 % (76 MB)
113 01:21:35.063002 progress 80 % (82 MB)
114 01:21:35.766082 progress 85 % (87 MB)
115 01:21:36.555944 progress 90 % (92 MB)
116 01:21:37.251375 progress 95 % (97 MB)
117 01:21:37.996205 progress 100 % (102 MB)
118 01:21:38.009092 102 MB downloaded in 13.58 s (7.55 MB/s)
119 01:21:38.009677 end: 1.4.1 http-download (duration 00:00:14) [common]
121 01:21:38.010509 end: 1.4 download-retry (duration 00:00:14) [common]
122 01:21:38.010772 start: 1.5 download-retry (timeout 00:09:45) [common]
123 01:21:38.011033 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 01:21:38.011495 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
125 01:21:38.011738 saving as /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/modules/modules.tar
126 01:21:38.011943 total size: 16128536 (15 MB)
127 01:21:38.012362 Using unxz to decompress xz
128 01:21:38.055757 progress 0 % (0 MB)
129 01:21:38.155429 progress 5 % (0 MB)
130 01:21:38.268087 progress 10 % (1 MB)
131 01:21:38.383507 progress 15 % (2 MB)
132 01:21:38.512319 progress 20 % (3 MB)
133 01:21:38.647138 progress 25 % (3 MB)
134 01:21:38.753183 progress 30 % (4 MB)
135 01:21:38.870566 progress 35 % (5 MB)
136 01:21:38.980680 progress 40 % (6 MB)
137 01:21:39.090282 progress 45 % (6 MB)
138 01:21:39.210889 progress 50 % (7 MB)
139 01:21:39.321972 progress 55 % (8 MB)
140 01:21:39.441648 progress 60 % (9 MB)
141 01:21:39.554770 progress 65 % (10 MB)
142 01:21:39.669122 progress 70 % (10 MB)
143 01:21:39.789075 progress 75 % (11 MB)
144 01:21:39.902472 progress 80 % (12 MB)
145 01:21:40.018523 progress 85 % (13 MB)
146 01:21:40.128952 progress 90 % (13 MB)
147 01:21:40.236576 progress 95 % (14 MB)
148 01:21:40.358430 progress 100 % (15 MB)
149 01:21:40.369127 15 MB downloaded in 2.36 s (6.53 MB/s)
150 01:21:40.369806 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:21:40.370654 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:21:40.370935 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 01:21:40.371207 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 01:21:50.070971 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/950721/extract-nfsrootfs-238myuxn
156 01:21:50.071574 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 01:21:50.071879 start: 1.6.2 lava-overlay (timeout 00:09:33) [common]
158 01:21:50.072522 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr
159 01:21:50.072959 makedir: /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin
160 01:21:50.073288 makedir: /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/tests
161 01:21:50.073601 makedir: /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/results
162 01:21:50.073940 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-add-keys
163 01:21:50.074474 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-add-sources
164 01:21:50.074977 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-background-process-start
165 01:21:50.075526 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-background-process-stop
166 01:21:50.076097 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-common-functions
167 01:21:50.076679 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-echo-ipv4
168 01:21:50.077239 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-install-packages
169 01:21:50.077794 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-installed-packages
170 01:21:50.078300 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-os-build
171 01:21:50.078788 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-probe-channel
172 01:21:50.079261 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-probe-ip
173 01:21:50.079757 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-target-ip
174 01:21:50.080305 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-target-mac
175 01:21:50.080849 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-target-storage
176 01:21:50.081351 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-test-case
177 01:21:50.081829 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-test-event
178 01:21:50.082308 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-test-feedback
179 01:21:50.082786 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-test-raise
180 01:21:50.083318 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-test-reference
181 01:21:50.083883 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-test-runner
182 01:21:50.084473 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-test-set
183 01:21:50.084993 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-test-shell
184 01:21:50.085498 Updating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-install-packages (oe)
185 01:21:50.086036 Updating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/bin/lava-installed-packages (oe)
186 01:21:50.086476 Creating /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/environment
187 01:21:50.086849 LAVA metadata
188 01:21:50.087114 - LAVA_JOB_ID=950721
189 01:21:50.087331 - LAVA_DISPATCHER_IP=192.168.6.2
190 01:21:50.087700 start: 1.6.2.1 ssh-authorize (timeout 00:09:33) [common]
191 01:21:50.088715 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 01:21:50.089040 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:33) [common]
193 01:21:50.089252 skipped lava-vland-overlay
194 01:21:50.089497 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 01:21:50.089752 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:33) [common]
196 01:21:50.089976 skipped lava-multinode-overlay
197 01:21:50.090225 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 01:21:50.090521 start: 1.6.2.4 test-definition (timeout 00:09:33) [common]
199 01:21:50.090795 Loading test definitions
200 01:21:50.091119 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:33) [common]
201 01:21:50.091381 Using /lava-950721 at stage 0
202 01:21:50.092764 uuid=950721_1.6.2.4.1 testdef=None
203 01:21:50.093099 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 01:21:50.093367 start: 1.6.2.4.2 test-overlay (timeout 00:09:33) [common]
205 01:21:50.095234 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 01:21:50.096044 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:33) [common]
208 01:21:50.098298 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 01:21:50.099130 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:33) [common]
211 01:21:50.101333 runner path: /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/0/tests/0_dmesg test_uuid 950721_1.6.2.4.1
212 01:21:50.101896 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 01:21:50.102661 Creating lava-test-runner.conf files
215 01:21:50.102865 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950721/lava-overlay-zupfcttr/lava-950721/0 for stage 0
216 01:21:50.103201 - 0_dmesg
217 01:21:50.103543 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 01:21:50.103822 start: 1.6.2.5 compress-overlay (timeout 00:09:33) [common]
219 01:21:50.125255 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 01:21:50.125646 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:33) [common]
221 01:21:50.125909 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 01:21:50.126175 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 01:21:50.126438 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
224 01:21:50.739846 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 01:21:50.740353 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 01:21:50.740627 extracting modules file /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950721/extract-nfsrootfs-238myuxn
227 01:21:52.305738 extracting modules file /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950721/extract-overlay-ramdisk-n8d08yuy/ramdisk
228 01:21:53.916105 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 01:21:53.916585 start: 1.6.5 apply-overlay-tftp (timeout 00:09:29) [common]
230 01:21:53.916864 [common] Applying overlay to NFS
231 01:21:53.917077 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950721/compress-overlay-tymvzswy/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950721/extract-nfsrootfs-238myuxn
232 01:21:53.946440 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 01:21:53.946863 start: 1.6.6 prepare-kernel (timeout 00:09:29) [common]
234 01:21:53.947133 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:29) [common]
235 01:21:53.947366 Converting downloaded kernel to a uImage
236 01:21:53.947674 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/kernel/Image /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/kernel/uImage
237 01:21:54.654546 output: Image Name:
238 01:21:54.654977 output: Created: Thu Nov 7 01:21:53 2024
239 01:21:54.655202 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 01:21:54.655415 output: Data Size: 66443776 Bytes = 64886.50 KiB = 63.37 MiB
241 01:21:54.655621 output: Load Address: 01080000
242 01:21:54.655825 output: Entry Point: 01080000
243 01:21:54.656065 output:
244 01:21:54.656417 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 01:21:54.656693 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 01:21:54.656969 start: 1.6.7 configure-preseed-file (timeout 00:09:29) [common]
247 01:21:54.657230 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 01:21:54.657494 start: 1.6.8 compress-ramdisk (timeout 00:09:29) [common]
249 01:21:54.657758 Building ramdisk /var/lib/lava/dispatcher/tmp/950721/extract-overlay-ramdisk-n8d08yuy/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950721/extract-overlay-ramdisk-n8d08yuy/ramdisk
250 01:21:57.677555 >> 239643 blocks
251 01:22:07.960317 Adding RAMdisk u-boot header.
252 01:22:07.960758 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950721/extract-overlay-ramdisk-n8d08yuy/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950721/extract-overlay-ramdisk-n8d08yuy/ramdisk.cpio.gz.uboot
253 01:22:08.321902 output: Image Name:
254 01:22:08.322321 output: Created: Thu Nov 7 01:22:07 2024
255 01:22:08.322533 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 01:22:08.322739 output: Data Size: 30953307 Bytes = 30227.84 KiB = 29.52 MiB
257 01:22:08.322941 output: Load Address: 00000000
258 01:22:08.323140 output: Entry Point: 00000000
259 01:22:08.323336 output:
260 01:22:08.324117 rename /var/lib/lava/dispatcher/tmp/950721/extract-overlay-ramdisk-n8d08yuy/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/ramdisk/ramdisk.cpio.gz.uboot
261 01:22:08.324849 end: 1.6.8 compress-ramdisk (duration 00:00:14) [common]
262 01:22:08.325396 end: 1.6 prepare-tftp-overlay (duration 00:00:28) [common]
263 01:22:08.325951 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:15) [common]
264 01:22:08.326405 No LXC device requested
265 01:22:08.326900 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 01:22:08.327404 start: 1.8 deploy-device-env (timeout 00:09:15) [common]
267 01:22:08.327890 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 01:22:08.328330 Checking files for TFTP limit of 4294967296 bytes.
269 01:22:08.330956 end: 1 tftp-deploy (duration 00:00:45) [common]
270 01:22:08.331528 start: 2 uboot-action (timeout 00:05:00) [common]
271 01:22:08.332073 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 01:22:08.332573 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 01:22:08.333071 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 01:22:08.333589 Using kernel file from prepare-kernel: 950721/tftp-deploy-06i4dh30/kernel/uImage
275 01:22:08.334206 substitutions:
276 01:22:08.334606 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 01:22:08.335003 - {DTB_ADDR}: 0x01070000
278 01:22:08.335396 - {DTB}: 950721/tftp-deploy-06i4dh30/dtb/meson-g12b-a311d-libretech-cc.dtb
279 01:22:08.335788 - {INITRD}: 950721/tftp-deploy-06i4dh30/ramdisk/ramdisk.cpio.gz.uboot
280 01:22:08.336211 - {KERNEL_ADDR}: 0x01080000
281 01:22:08.336604 - {KERNEL}: 950721/tftp-deploy-06i4dh30/kernel/uImage
282 01:22:08.336990 - {LAVA_MAC}: None
283 01:22:08.337418 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/950721/extract-nfsrootfs-238myuxn
284 01:22:08.337810 - {NFS_SERVER_IP}: 192.168.6.2
285 01:22:08.338197 - {PRESEED_CONFIG}: None
286 01:22:08.338581 - {PRESEED_LOCAL}: None
287 01:22:08.338965 - {RAMDISK_ADDR}: 0x08000000
288 01:22:08.339347 - {RAMDISK}: 950721/tftp-deploy-06i4dh30/ramdisk/ramdisk.cpio.gz.uboot
289 01:22:08.339730 - {ROOT_PART}: None
290 01:22:08.340149 - {ROOT}: None
291 01:22:08.340541 - {SERVER_IP}: 192.168.6.2
292 01:22:08.340927 - {TEE_ADDR}: 0x83000000
293 01:22:08.341308 - {TEE}: None
294 01:22:08.341694 Parsed boot commands:
295 01:22:08.342070 - setenv autoload no
296 01:22:08.342451 - setenv initrd_high 0xffffffff
297 01:22:08.342831 - setenv fdt_high 0xffffffff
298 01:22:08.343213 - dhcp
299 01:22:08.343593 - setenv serverip 192.168.6.2
300 01:22:08.343975 - tftpboot 0x01080000 950721/tftp-deploy-06i4dh30/kernel/uImage
301 01:22:08.344387 - tftpboot 0x08000000 950721/tftp-deploy-06i4dh30/ramdisk/ramdisk.cpio.gz.uboot
302 01:22:08.344772 - tftpboot 0x01070000 950721/tftp-deploy-06i4dh30/dtb/meson-g12b-a311d-libretech-cc.dtb
303 01:22:08.345157 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950721/extract-nfsrootfs-238myuxn,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 01:22:08.345551 - bootm 0x01080000 0x08000000 0x01070000
305 01:22:08.346046 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 01:22:08.347513 start: 2.3 connect-device (timeout 00:05:00) [common]
308 01:22:08.347929 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 01:22:08.362941 Setting prompt string to ['lava-test: # ']
310 01:22:08.364465 end: 2.3 connect-device (duration 00:00:00) [common]
311 01:22:08.365067 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 01:22:08.365614 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 01:22:08.366149 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 01:22:08.367272 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 01:22:08.404273 >> OK - accepted request
316 01:22:08.406703 Returned 0 in 0 seconds
317 01:22:08.507575 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 01:22:08.509208 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 01:22:08.509769 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 01:22:08.510286 Setting prompt string to ['Hit any key to stop autoboot']
322 01:22:08.510749 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 01:22:08.512323 Trying 192.168.56.21...
324 01:22:08.512795 Connected to conserv1.
325 01:22:08.513212 Escape character is '^]'.
326 01:22:08.513625
327 01:22:08.514038 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 01:22:08.514447
329 01:22:20.114043 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
330 01:22:20.114579 bl2_stage_init 0x81
331 01:22:20.119561 hw id: 0x0000 - pwm id 0x01
332 01:22:20.119943 bl2_stage_init 0xc1
333 01:22:20.120217 bl2_stage_init 0x02
334 01:22:20.120467
335 01:22:20.125040 L0:00000000
336 01:22:20.125386 L1:20000703
337 01:22:20.125657 L2:00008067
338 01:22:20.125891 L3:14000000
339 01:22:20.126136 B2:00402000
340 01:22:20.130643 B1:e0f83180
341 01:22:20.130987
342 01:22:20.131238 TE: 58150
343 01:22:20.131485
344 01:22:20.136342 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
345 01:22:20.136689
346 01:22:20.136950 Board ID = 1
347 01:22:20.141917 Set A53 clk to 24M
348 01:22:20.142249 Set A73 clk to 24M
349 01:22:20.142497 Set clk81 to 24M
350 01:22:20.147575 A53 clk: 1200 MHz
351 01:22:20.147924 A73 clk: 1200 MHz
352 01:22:20.148209 CLK81: 166.6M
353 01:22:20.148455 smccc: 00012aab
354 01:22:20.153090 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
355 01:22:20.158734 board id: 1
356 01:22:20.164800 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
357 01:22:20.175044 fw parse done
358 01:22:20.180990 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
359 01:22:20.224007 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
360 01:22:20.235467 PIEI prepare done
361 01:22:20.236802 fastboot data load
362 01:22:20.237794 fastboot data verify
363 01:22:20.240167 verify result: 266
364 01:22:20.245782 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
365 01:22:20.246110 LPDDR4 probe
366 01:22:20.246338 ddr clk to 1584MHz
367 01:22:20.253718 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
368 01:22:20.291963
369 01:22:20.292463 dmc_version 0001
370 01:22:20.297644 Check phy result
371 01:22:20.303519 INFO : End of CA training
372 01:22:20.303889 INFO : End of initialization
373 01:22:20.309134 INFO : Training has run successfully!
374 01:22:20.309756 Check phy result
375 01:22:20.314781 INFO : End of initialization
376 01:22:20.315380 INFO : End of read enable training
377 01:22:20.320313 INFO : End of fine write leveling
378 01:22:20.325948 INFO : End of Write leveling coarse delay
379 01:22:20.326538 INFO : Training has run successfully!
380 01:22:20.327055 Check phy result
381 01:22:20.331537 INFO : End of initialization
382 01:22:20.332151 INFO : End of read dq deskew training
383 01:22:20.337653 INFO : End of MPR read delay center optimization
384 01:22:20.342760 INFO : End of write delay center optimization
385 01:22:20.348351 INFO : End of read delay center optimization
386 01:22:20.348962 INFO : End of max read latency training
387 01:22:20.353948 INFO : Training has run successfully!
388 01:22:20.354509 1D training succeed
389 01:22:20.363101 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 01:22:20.410775 Check phy result
391 01:22:20.411232 INFO : End of initialization
392 01:22:20.433405 INFO : End of 2D read delay Voltage center optimization
393 01:22:20.453588 INFO : End of 2D read delay Voltage center optimization
394 01:22:20.505747 INFO : End of 2D write delay Voltage center optimization
395 01:22:20.555134 INFO : End of 2D write delay Voltage center optimization
396 01:22:20.560448 INFO : Training has run successfully!
397 01:22:20.561116
398 01:22:20.561656 channel==0
399 01:22:20.566043 RxClkDly_Margin_A0==88 ps 9
400 01:22:20.566621 TxDqDly_Margin_A0==98 ps 10
401 01:22:20.569464 RxClkDly_Margin_A1==88 ps 9
402 01:22:20.570018 TxDqDly_Margin_A1==88 ps 9
403 01:22:20.575023 TrainedVREFDQ_A0==74
404 01:22:20.575603 TrainedVREFDQ_A1==74
405 01:22:20.576178 VrefDac_Margin_A0==24
406 01:22:20.580638 DeviceVref_Margin_A0==40
407 01:22:20.581272 VrefDac_Margin_A1==24
408 01:22:20.586312 DeviceVref_Margin_A1==40
409 01:22:20.587017
410 01:22:20.587550
411 01:22:20.588106 channel==1
412 01:22:20.588649 RxClkDly_Margin_A0==88 ps 9
413 01:22:20.591930 TxDqDly_Margin_A0==98 ps 10
414 01:22:20.592681 RxClkDly_Margin_A1==88 ps 9
415 01:22:20.597512 TxDqDly_Margin_A1==88 ps 9
416 01:22:20.598142 TrainedVREFDQ_A0==77
417 01:22:20.598680 TrainedVREFDQ_A1==77
418 01:22:20.602980 VrefDac_Margin_A0==22
419 01:22:20.603579 DeviceVref_Margin_A0==37
420 01:22:20.608605 VrefDac_Margin_A1==24
421 01:22:20.608939 DeviceVref_Margin_A1==37
422 01:22:20.609202
423 01:22:20.614227 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
424 01:22:20.614888
425 01:22:20.643682 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
426 01:22:20.647949 2D training succeed
427 01:22:20.653582 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
428 01:22:20.654258 auto size-- 65535DDR cs0 size: 2048MB
429 01:22:20.659064 DDR cs1 size: 2048MB
430 01:22:20.659659 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
431 01:22:20.664648 cs0 DataBus test pass
432 01:22:20.665214 cs1 DataBus test pass
433 01:22:20.665729 cs0 AddrBus test pass
434 01:22:20.670281 cs1 AddrBus test pass
435 01:22:20.670837
436 01:22:20.671349 100bdlr_step_size ps== 420
437 01:22:20.671861 result report
438 01:22:20.675788 boot times 0Enable ddr reg access
439 01:22:20.683361 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
440 01:22:20.696784 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
441 01:22:21.270652 0.0;M3 CHK:0;cm4_sp_mode 0
442 01:22:21.271352 MVN_1=0x00000000
443 01:22:21.275921 MVN_2=0x00000000
444 01:22:21.281681 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
445 01:22:21.282194 OPS=0x10
446 01:22:21.282661 ring efuse init
447 01:22:21.283120 chipver efuse init
448 01:22:21.287317 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
449 01:22:21.292886 [0.018961 Inits done]
450 01:22:21.293392 secure task start!
451 01:22:21.293852 high task start!
452 01:22:21.297459 low task start!
453 01:22:21.297948 run into bl31
454 01:22:21.304112 NOTICE: BL31: v1.3(release):4fc40b1
455 01:22:21.311920 NOTICE: BL31: Built : 15:58:17, May 22 2019
456 01:22:21.312471 NOTICE: BL31: G12A normal boot!
457 01:22:21.337306 NOTICE: BL31: BL33 decompress pass
458 01:22:21.342977 ERROR: Error initializing runtime service opteed_fast
459 01:22:22.575935
460 01:22:22.576653
461 01:22:22.584316 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
462 01:22:22.584924
463 01:22:22.585447 Model: Libre Computer AML-A311D-CC Alta
464 01:22:22.792737 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
465 01:22:22.816103 DRAM: 2 GiB (effective 3.8 GiB)
466 01:22:22.959178 Core: 408 devices, 31 uclasses, devicetree: separate
467 01:22:22.964992 WDT: Not starting watchdog@f0d0
468 01:22:22.997193 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
469 01:22:23.009768 Loading Environment from FAT... Card did not respond to voltage select! : -110
470 01:22:23.014625 ** Bad device specification mmc 0 **
471 01:22:23.024944 Card did not respond to voltage select! : -110
472 01:22:23.032610 ** Bad device specification mmc 0 **
473 01:22:23.033099 Couldn't find partition mmc 0
474 01:22:23.040933 Card did not respond to voltage select! : -110
475 01:22:23.046453 ** Bad device specification mmc 0 **
476 01:22:23.046939 Couldn't find partition mmc 0
477 01:22:23.051515 Error: could not access storage.
478 01:22:24.314528 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
479 01:22:24.315212 bl2_stage_init 0x81
480 01:22:24.319955 hw id: 0x0000 - pwm id 0x01
481 01:22:24.320492 bl2_stage_init 0xc1
482 01:22:24.320956 bl2_stage_init 0x02
483 01:22:24.321407
484 01:22:24.325551 L0:00000000
485 01:22:24.326107 L1:20000703
486 01:22:24.326571 L2:00008067
487 01:22:24.327032 L3:14000000
488 01:22:24.327478 B2:00402000
489 01:22:24.331145 B1:e0f83180
490 01:22:24.331686
491 01:22:24.332198 TE: 58150
492 01:22:24.332663
493 01:22:24.336796 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
494 01:22:24.337340
495 01:22:24.337803 Board ID = 1
496 01:22:24.342340 Set A53 clk to 24M
497 01:22:24.342867 Set A73 clk to 24M
498 01:22:24.343320 Set clk81 to 24M
499 01:22:24.348037 A53 clk: 1200 MHz
500 01:22:24.348580 A73 clk: 1200 MHz
501 01:22:24.349040 CLK81: 166.6M
502 01:22:24.349481 smccc: 00012aac
503 01:22:24.353536 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
504 01:22:24.359132 board id: 1
505 01:22:24.365005 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
506 01:22:24.375599 fw parse done
507 01:22:24.381555 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
508 01:22:24.424222 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
509 01:22:24.435113 PIEI prepare done
510 01:22:24.435681 fastboot data load
511 01:22:24.436202 fastboot data verify
512 01:22:24.440759 verify result: 266
513 01:22:24.446338 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
514 01:22:24.446880 LPDDR4 probe
515 01:22:24.447350 ddr clk to 1584MHz
516 01:22:24.454334 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
517 01:22:24.491714
518 01:22:24.492394 dmc_version 0001
519 01:22:24.498240 Check phy result
520 01:22:24.504136 INFO : End of CA training
521 01:22:24.504655 INFO : End of initialization
522 01:22:24.509714 INFO : Training has run successfully!
523 01:22:24.510242 Check phy result
524 01:22:24.515311 INFO : End of initialization
525 01:22:24.515840 INFO : End of read enable training
526 01:22:24.520998 INFO : End of fine write leveling
527 01:22:24.526508 INFO : End of Write leveling coarse delay
528 01:22:24.527039 INFO : Training has run successfully!
529 01:22:24.527499 Check phy result
530 01:22:24.532163 INFO : End of initialization
531 01:22:24.532695 INFO : End of read dq deskew training
532 01:22:24.537724 INFO : End of MPR read delay center optimization
533 01:22:24.543351 INFO : End of write delay center optimization
534 01:22:24.549318 INFO : End of read delay center optimization
535 01:22:24.549870 INFO : End of max read latency training
536 01:22:24.554520 INFO : Training has run successfully!
537 01:22:24.555043 1D training succeed
538 01:22:24.563710 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 01:22:24.611413 Check phy result
540 01:22:24.612051 INFO : End of initialization
541 01:22:24.632941 INFO : End of 2D read delay Voltage center optimization
542 01:22:24.653132 INFO : End of 2D read delay Voltage center optimization
543 01:22:24.704946 INFO : End of 2D write delay Voltage center optimization
544 01:22:24.754160 INFO : End of 2D write delay Voltage center optimization
545 01:22:24.759689 INFO : Training has run successfully!
546 01:22:24.760260
547 01:22:24.760725 channel==0
548 01:22:24.765284 RxClkDly_Margin_A0==88 ps 9
549 01:22:24.765811 TxDqDly_Margin_A0==98 ps 10
550 01:22:24.770906 RxClkDly_Margin_A1==88 ps 9
551 01:22:24.771446 TxDqDly_Margin_A1==98 ps 10
552 01:22:24.771904 TrainedVREFDQ_A0==74
553 01:22:24.776506 TrainedVREFDQ_A1==75
554 01:22:24.777042 VrefDac_Margin_A0==25
555 01:22:24.777503 DeviceVref_Margin_A0==40
556 01:22:24.782078 VrefDac_Margin_A1==25
557 01:22:24.782597 DeviceVref_Margin_A1==39
558 01:22:24.783051
559 01:22:24.783500
560 01:22:24.787679 channel==1
561 01:22:24.788233 RxClkDly_Margin_A0==98 ps 10
562 01:22:24.788689 TxDqDly_Margin_A0==88 ps 9
563 01:22:24.793272 RxClkDly_Margin_A1==98 ps 10
564 01:22:24.793792 TxDqDly_Margin_A1==88 ps 9
565 01:22:24.798915 TrainedVREFDQ_A0==77
566 01:22:24.799448 TrainedVREFDQ_A1==77
567 01:22:24.799911 VrefDac_Margin_A0==22
568 01:22:24.804475 DeviceVref_Margin_A0==37
569 01:22:24.804957 VrefDac_Margin_A1==22
570 01:22:24.810059 DeviceVref_Margin_A1==37
571 01:22:24.810509
572 01:22:24.810937 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
573 01:22:24.811356
574 01:22:24.843740 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
575 01:22:24.844300 2D training succeed
576 01:22:24.849347 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
577 01:22:24.854974 auto size-- 65535DDR cs0 size: 2048MB
578 01:22:24.855445 DDR cs1 size: 2048MB
579 01:22:24.860580 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
580 01:22:24.861042 cs0 DataBus test pass
581 01:22:24.866126 cs1 DataBus test pass
582 01:22:24.866582 cs0 AddrBus test pass
583 01:22:24.867000 cs1 AddrBus test pass
584 01:22:24.867409
585 01:22:24.871691 100bdlr_step_size ps== 420
586 01:22:24.872197 result report
587 01:22:24.877330 boot times 0Enable ddr reg access
588 01:22:24.882677 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
589 01:22:24.896230 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
590 01:22:25.468680 0.0;M3 CHK:0;cm4_sp_mode 0
591 01:22:25.469378 MVN_1=0x00000000
592 01:22:25.473886 MVN_2=0x00000000
593 01:22:25.479677 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
594 01:22:25.480315 OPS=0x10
595 01:22:25.480797 ring efuse init
596 01:22:25.481306 chipver efuse init
597 01:22:25.485210 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
598 01:22:25.490772 [0.018961 Inits done]
599 01:22:25.491329 secure task start!
600 01:22:25.491770 high task start!
601 01:22:25.495485 low task start!
602 01:22:25.496064 run into bl31
603 01:22:25.502026 NOTICE: BL31: v1.3(release):4fc40b1
604 01:22:25.510002 NOTICE: BL31: Built : 15:58:17, May 22 2019
605 01:22:25.510543 NOTICE: BL31: G12A normal boot!
606 01:22:25.535527 NOTICE: BL31: BL33 decompress pass
607 01:22:25.541088 ERROR: Error initializing runtime service opteed_fast
608 01:22:26.774047
609 01:22:26.774723
610 01:22:26.782347 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
611 01:22:26.782926
612 01:22:26.783420 Model: Libre Computer AML-A311D-CC Alta
613 01:22:26.990820 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
614 01:22:27.014279 DRAM: 2 GiB (effective 3.8 GiB)
615 01:22:27.157171 Core: 408 devices, 31 uclasses, devicetree: separate
616 01:22:27.162994 WDT: Not starting watchdog@f0d0
617 01:22:27.195171 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
618 01:22:27.207752 Loading Environment from FAT... Card did not respond to voltage select! : -110
619 01:22:27.212815 ** Bad device specification mmc 0 **
620 01:22:27.223113 Card did not respond to voltage select! : -110
621 01:22:27.230791 ** Bad device specification mmc 0 **
622 01:22:27.231392 Couldn't find partition mmc 0
623 01:22:27.239005 Card did not respond to voltage select! : -110
624 01:22:27.244566 ** Bad device specification mmc 0 **
625 01:22:27.245111 Couldn't find partition mmc 0
626 01:22:27.249581 Error: could not access storage.
627 01:22:27.592042 Net: eth0: ethernet@ff3f0000
628 01:22:27.592703 starting USB...
629 01:22:27.843871 Bus usb@ff500000: Register 3000140 NbrPorts 3
630 01:22:27.844493 Starting the controller
631 01:22:27.850930 USB XHCI 1.10
632 01:22:29.565787 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
633 01:22:29.566228 bl2_stage_init 0x01
634 01:22:29.566455 bl2_stage_init 0x81
635 01:22:29.571297 hw id: 0x0000 - pwm id 0x01
636 01:22:29.571658 bl2_stage_init 0xc1
637 01:22:29.572017 bl2_stage_init 0x02
638 01:22:29.572281
639 01:22:29.576659 L0:00000000
640 01:22:29.577219 L1:20000703
641 01:22:29.577573 L2:00008067
642 01:22:29.577804 L3:14000000
643 01:22:29.579520 B2:00402000
644 01:22:29.580005 B1:e0f83180
645 01:22:29.580461
646 01:22:29.580924 TE: 58124
647 01:22:29.581388
648 01:22:29.590651 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
649 01:22:29.591181
650 01:22:29.591640 Board ID = 1
651 01:22:29.592093 Set A53 clk to 24M
652 01:22:29.592517 Set A73 clk to 24M
653 01:22:29.596266 Set clk81 to 24M
654 01:22:29.596767 A53 clk: 1200 MHz
655 01:22:29.597191 A73 clk: 1200 MHz
656 01:22:29.599777 CLK81: 166.6M
657 01:22:29.600279 smccc: 00012a92
658 01:22:29.605298 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
659 01:22:29.610861 board id: 1
660 01:22:29.616264 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
661 01:22:29.626546 fw parse done
662 01:22:29.632506 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
663 01:22:29.675146 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
664 01:22:29.686119 PIEI prepare done
665 01:22:29.686621 fastboot data load
666 01:22:29.687050 fastboot data verify
667 01:22:29.691740 verify result: 266
668 01:22:29.697300 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
669 01:22:29.697770 LPDDR4 probe
670 01:22:29.698188 ddr clk to 1584MHz
671 01:22:29.705271 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
672 01:22:29.742536
673 01:22:29.743021 dmc_version 0001
674 01:22:29.749212 Check phy result
675 01:22:29.755115 INFO : End of CA training
676 01:22:29.755666 INFO : End of initialization
677 01:22:29.760772 INFO : Training has run successfully!
678 01:22:29.761251 Check phy result
679 01:22:29.766281 INFO : End of initialization
680 01:22:29.766756 INFO : End of read enable training
681 01:22:29.769634 INFO : End of fine write leveling
682 01:22:29.775202 INFO : End of Write leveling coarse delay
683 01:22:29.780797 INFO : Training has run successfully!
684 01:22:29.781265 Check phy result
685 01:22:29.781687 INFO : End of initialization
686 01:22:29.786402 INFO : End of read dq deskew training
687 01:22:29.792008 INFO : End of MPR read delay center optimization
688 01:22:29.792486 INFO : End of write delay center optimization
689 01:22:29.797626 INFO : End of read delay center optimization
690 01:22:29.803182 INFO : End of max read latency training
691 01:22:29.803650 INFO : Training has run successfully!
692 01:22:29.808802 1D training succeed
693 01:22:29.814690 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 01:22:29.862307 Check phy result
695 01:22:29.862859 INFO : End of initialization
696 01:22:29.894008 INFO : End of 2D read delay Voltage center optimization
697 01:22:29.905091 INFO : End of 2D read delay Voltage center optimization
698 01:22:29.957308 INFO : End of 2D write delay Voltage center optimization
699 01:22:30.006481 INFO : End of 2D write delay Voltage center optimization
700 01:22:30.012067 INFO : Training has run successfully!
701 01:22:30.012527
702 01:22:30.012946 channel==0
703 01:22:30.017690 RxClkDly_Margin_A0==88 ps 9
704 01:22:30.018148 TxDqDly_Margin_A0==98 ps 10
705 01:22:30.023250 RxClkDly_Margin_A1==88 ps 9
706 01:22:30.023719 TxDqDly_Margin_A1==88 ps 9
707 01:22:30.024193 TrainedVREFDQ_A0==74
708 01:22:30.028856 TrainedVREFDQ_A1==74
709 01:22:30.029318 VrefDac_Margin_A0==24
710 01:22:30.029733 DeviceVref_Margin_A0==40
711 01:22:30.034460 VrefDac_Margin_A1==25
712 01:22:30.034918 DeviceVref_Margin_A1==40
713 01:22:30.035327
714 01:22:30.035728
715 01:22:30.036161 channel==1
716 01:22:30.040175 RxClkDly_Margin_A0==98 ps 10
717 01:22:30.040738 TxDqDly_Margin_A0==98 ps 10
718 01:22:30.045663 RxClkDly_Margin_A1==88 ps 9
719 01:22:30.046165 TxDqDly_Margin_A1==108 ps 11
720 01:22:30.051244 TrainedVREFDQ_A0==77
721 01:22:30.051727 TrainedVREFDQ_A1==77
722 01:22:30.052302 VrefDac_Margin_A0==22
723 01:22:30.056853 DeviceVref_Margin_A0==37
724 01:22:30.057318 VrefDac_Margin_A1==24
725 01:22:30.062449 DeviceVref_Margin_A1==37
726 01:22:30.062901
727 01:22:30.063317 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
728 01:22:30.068059
729 01:22:30.096101 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
730 01:22:30.096667 2D training succeed
731 01:22:30.101650 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
732 01:22:30.107238 auto size-- 65535DDR cs0 size: 2048MB
733 01:22:30.107696 DDR cs1 size: 2048MB
734 01:22:30.112854 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
735 01:22:30.113311 cs0 DataBus test pass
736 01:22:30.118459 cs1 DataBus test pass
737 01:22:30.118911 cs0 AddrBus test pass
738 01:22:30.119326 cs1 AddrBus test pass
739 01:22:30.119732
740 01:22:30.124051 100bdlr_step_size ps== 420
741 01:22:30.124520 result report
742 01:22:30.129652 boot times 0Enable ddr reg access
743 01:22:30.135105 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
744 01:22:30.148558 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
745 01:22:30.721771 0.0;M3 CHK:0;cm4_sp_mode 0
746 01:22:30.722390 MVN_1=0x00000000
747 01:22:30.727204 MVN_2=0x00000000
748 01:22:30.732976 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
749 01:22:30.733506 OPS=0x10
750 01:22:30.733905 ring efuse init
751 01:22:30.734293 chipver efuse init
752 01:22:30.738530 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
753 01:22:30.744173 [0.018961 Inits done]
754 01:22:30.744609 secure task start!
755 01:22:30.744997 high task start!
756 01:22:30.748718 low task start!
757 01:22:30.749150 run into bl31
758 01:22:30.755386 NOTICE: BL31: v1.3(release):4fc40b1
759 01:22:30.763352 NOTICE: BL31: Built : 15:58:17, May 22 2019
760 01:22:30.763866 NOTICE: BL31: G12A normal boot!
761 01:22:30.788560 NOTICE: BL31: BL33 decompress pass
762 01:22:30.794204 ERROR: Error initializing runtime service opteed_fast
763 01:22:32.027295
764 01:22:32.027913
765 01:22:32.035438 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
766 01:22:32.035909
767 01:22:32.036367 Model: Libre Computer AML-A311D-CC Alta
768 01:22:32.243946 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
769 01:22:32.267266 DRAM: 2 GiB (effective 3.8 GiB)
770 01:22:32.410242 Core: 408 devices, 31 uclasses, devicetree: separate
771 01:22:32.416192 WDT: Not starting watchdog@f0d0
772 01:22:32.448410 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
773 01:22:32.460927 Loading Environment from FAT... Card did not respond to voltage select! : -110
774 01:22:32.465843 ** Bad device specification mmc 0 **
775 01:22:32.476200 Card did not respond to voltage select! : -110
776 01:22:32.483827 ** Bad device specification mmc 0 **
777 01:22:32.484376 Couldn't find partition mmc 0
778 01:22:32.492185 Card did not respond to voltage select! : -110
779 01:22:32.497707 ** Bad device specification mmc 0 **
780 01:22:32.498205 Couldn't find partition mmc 0
781 01:22:32.502751 Error: could not access storage.
782 01:22:32.845217 Net: eth0: ethernet@ff3f0000
783 01:22:32.845825 starting USB...
784 01:22:33.097047 Bus usb@ff500000: Register 3000140 NbrPorts 3
785 01:22:33.097711 Starting the controller
786 01:22:33.104114 USB XHCI 1.10
787 01:22:35.264772 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
788 01:22:35.265241 bl2_stage_init 0x81
789 01:22:35.270244 hw id: 0x0000 - pwm id 0x01
790 01:22:35.270701 bl2_stage_init 0xc1
791 01:22:35.271103 bl2_stage_init 0x02
792 01:22:35.271496
793 01:22:35.275814 L0:00000000
794 01:22:35.276155 L1:20000703
795 01:22:35.276405 L2:00008067
796 01:22:35.276667 L3:14000000
797 01:22:35.276911 B2:00402000
798 01:22:35.281528 B1:e0f83180
799 01:22:35.281967
800 01:22:35.282370 TE: 58150
801 01:22:35.282768
802 01:22:35.286924 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
803 01:22:35.287364
804 01:22:35.287652 Board ID = 1
805 01:22:35.292702 Set A53 clk to 24M
806 01:22:35.293025 Set A73 clk to 24M
807 01:22:35.293276 Set clk81 to 24M
808 01:22:35.298306 A53 clk: 1200 MHz
809 01:22:35.298628 A73 clk: 1200 MHz
810 01:22:35.298878 CLK81: 166.6M
811 01:22:35.299116 smccc: 00012aab
812 01:22:35.303813 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
813 01:22:35.309511 board id: 1
814 01:22:35.315285 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
815 01:22:35.325776 fw parse done
816 01:22:35.331735 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
817 01:22:35.374369 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
818 01:22:35.385244 PIEI prepare done
819 01:22:35.385592 fastboot data load
820 01:22:35.385844 fastboot data verify
821 01:22:35.390954 verify result: 266
822 01:22:35.396571 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
823 01:22:35.397039 LPDDR4 probe
824 01:22:35.397454 ddr clk to 1584MHz
825 01:22:35.404541 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
826 01:22:35.441785
827 01:22:35.442175 dmc_version 0001
828 01:22:35.448433 Check phy result
829 01:22:35.454285 INFO : End of CA training
830 01:22:35.454621 INFO : End of initialization
831 01:22:35.459907 INFO : Training has run successfully!
832 01:22:35.460410 Check phy result
833 01:22:35.465649 INFO : End of initialization
834 01:22:35.466018 INFO : End of read enable training
835 01:22:35.471109 INFO : End of fine write leveling
836 01:22:35.476708 INFO : End of Write leveling coarse delay
837 01:22:35.477178 INFO : Training has run successfully!
838 01:22:35.477640 Check phy result
839 01:22:35.482271 INFO : End of initialization
840 01:22:35.482746 INFO : End of read dq deskew training
841 01:22:35.487885 INFO : End of MPR read delay center optimization
842 01:22:35.493582 INFO : End of write delay center optimization
843 01:22:35.499098 INFO : End of read delay center optimization
844 01:22:35.499415 INFO : End of max read latency training
845 01:22:35.504668 INFO : Training has run successfully!
846 01:22:35.505129 1D training succeed
847 01:22:35.513893 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
848 01:22:35.561479 Check phy result
849 01:22:35.561875 INFO : End of initialization
850 01:22:35.583234 INFO : End of 2D read delay Voltage center optimization
851 01:22:35.603897 INFO : End of 2D read delay Voltage center optimization
852 01:22:35.655713 INFO : End of 2D write delay Voltage center optimization
853 01:22:35.705118 INFO : End of 2D write delay Voltage center optimization
854 01:22:35.710520 INFO : Training has run successfully!
855 01:22:35.710900
856 01:22:35.711135 channel==0
857 01:22:35.716040 RxClkDly_Margin_A0==88 ps 9
858 01:22:35.716569 TxDqDly_Margin_A0==108 ps 11
859 01:22:35.719380 RxClkDly_Margin_A1==88 ps 9
860 01:22:35.719866 TxDqDly_Margin_A1==98 ps 10
861 01:22:35.724895 TrainedVREFDQ_A0==74
862 01:22:35.725261 TrainedVREFDQ_A1==75
863 01:22:35.730558 VrefDac_Margin_A0==25
864 01:22:35.730942 DeviceVref_Margin_A0==40
865 01:22:35.731168 VrefDac_Margin_A1==25
866 01:22:35.736135 DeviceVref_Margin_A1==39
867 01:22:35.736507
868 01:22:35.736740
869 01:22:35.736948 channel==1
870 01:22:35.737154 RxClkDly_Margin_A0==98 ps 10
871 01:22:35.741681 TxDqDly_Margin_A0==98 ps 10
872 01:22:35.742041 RxClkDly_Margin_A1==88 ps 9
873 01:22:35.747253 TxDqDly_Margin_A1==88 ps 9
874 01:22:35.747578 TrainedVREFDQ_A0==77
875 01:22:35.747802 TrainedVREFDQ_A1==77
876 01:22:35.753006 VrefDac_Margin_A0==22
877 01:22:35.753330 DeviceVref_Margin_A0==37
878 01:22:35.758569 VrefDac_Margin_A1==24
879 01:22:35.758874 DeviceVref_Margin_A1==37
880 01:22:35.759083
881 01:22:35.764181 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
882 01:22:35.764717
883 01:22:35.792152 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
884 01:22:35.797755 2D training succeed
885 01:22:35.803544 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
886 01:22:35.804043 auto size-- 65535DDR cs0 size: 2048MB
887 01:22:35.808968 DDR cs1 size: 2048MB
888 01:22:35.809423 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
889 01:22:35.814561 cs0 DataBus test pass
890 01:22:35.815013 cs1 DataBus test pass
891 01:22:35.815408 cs0 AddrBus test pass
892 01:22:35.820141 cs1 AddrBus test pass
893 01:22:35.820598
894 01:22:35.820999 100bdlr_step_size ps== 420
895 01:22:35.821398 result report
896 01:22:35.825712 boot times 0Enable ddr reg access
897 01:22:35.833409 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
898 01:22:35.846921 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
899 01:22:36.420753 0.0;M3 CHK:0;cm4_sp_mode 0
900 01:22:36.421447 MVN_1=0x00000000
901 01:22:36.426244 MVN_2=0x00000000
902 01:22:36.432026 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
903 01:22:36.432630 OPS=0x10
904 01:22:36.433114 ring efuse init
905 01:22:36.433578 chipver efuse init
906 01:22:36.440112 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
907 01:22:36.440745 [0.018961 Inits done]
908 01:22:36.447811 secure task start!
909 01:22:36.448440 high task start!
910 01:22:36.448926 low task start!
911 01:22:36.449389 run into bl31
912 01:22:36.454317 NOTICE: BL31: v1.3(release):4fc40b1
913 01:22:36.462114 NOTICE: BL31: Built : 15:58:17, May 22 2019
914 01:22:36.462715 NOTICE: BL31: G12A normal boot!
915 01:22:36.487513 NOTICE: BL31: BL33 decompress pass
916 01:22:36.493162 ERROR: Error initializing runtime service opteed_fast
917 01:22:37.725907
918 01:22:37.726328
919 01:22:37.733363 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
920 01:22:37.733865
921 01:22:37.734307 Model: Libre Computer AML-A311D-CC Alta
922 01:22:37.942741 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
923 01:22:37.966167 DRAM: 2 GiB (effective 3.8 GiB)
924 01:22:38.109105 Core: 408 devices, 31 uclasses, devicetree: separate
925 01:22:38.114957 WDT: Not starting watchdog@f0d0
926 01:22:38.147248 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
927 01:22:38.159692 Loading Environment from FAT... Card did not respond to voltage select! : -110
928 01:22:38.164750 ** Bad device specification mmc 0 **
929 01:22:38.175095 Card did not respond to voltage select! : -110
930 01:22:38.182720 ** Bad device specification mmc 0 **
931 01:22:38.183273 Couldn't find partition mmc 0
932 01:22:38.191072 Card did not respond to voltage select! : -110
933 01:22:38.196592 ** Bad device specification mmc 0 **
934 01:22:38.197136 Couldn't find partition mmc 0
935 01:22:38.201652 Error: could not access storage.
936 01:22:38.545133 Net: eth0: ethernet@ff3f0000
937 01:22:38.545763 starting USB...
938 01:22:38.796962 Bus usb@ff500000: Register 3000140 NbrPorts 3
939 01:22:38.797551 Starting the controller
940 01:22:38.804021 USB XHCI 1.10
941 01:22:40.357895 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
942 01:22:40.366332 scanning usb for storage devices... 0 Storage Device(s) found
944 01:22:40.418099 Hit any key to stop autoboot: 1
945 01:22:40.419231 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
946 01:22:40.419926 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
947 01:22:40.420523 Setting prompt string to ['=>']
948 01:22:40.421072 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
949 01:22:40.433662 0
950 01:22:40.434685 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
951 01:22:40.435304 Sending with 10 millisecond of delay
953 01:22:41.570166 => setenv autoload no
954 01:22:41.580997 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
955 01:22:41.586393 setenv autoload no
956 01:22:41.587163 Sending with 10 millisecond of delay
958 01:22:43.384118 => setenv initrd_high 0xffffffff
959 01:22:43.395156 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
960 01:22:43.395749 setenv initrd_high 0xffffffff
961 01:22:43.396278 Sending with 10 millisecond of delay
963 01:22:45.016322 => setenv fdt_high 0xffffffff
964 01:22:45.026991 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
965 01:22:45.027692 setenv fdt_high 0xffffffff
966 01:22:45.028248 Sending with 10 millisecond of delay
968 01:22:45.330612 => dhcp
969 01:22:45.341211 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
970 01:22:45.341855 dhcp
971 01:22:45.342098 Speed: 1000, full duplex
972 01:22:45.342311 BOOTP broadcast 1
973 01:22:45.352043 DHCP client bound to address 192.168.6.27 (11 ms)
974 01:22:45.352706 Sending with 10 millisecond of delay
976 01:22:47.029184 => setenv serverip 192.168.6.2
977 01:22:47.039770 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
978 01:22:47.040832 setenv serverip 192.168.6.2
979 01:22:47.041698 Sending with 10 millisecond of delay
981 01:22:50.767359 => tftpboot 0x01080000 950721/tftp-deploy-06i4dh30/kernel/uImage
982 01:22:50.778240 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
983 01:22:50.778919 tftpboot 0x01080000 950721/tftp-deploy-06i4dh30/kernel/uImage
984 01:22:50.779176 Speed: 1000, full duplex
985 01:22:50.779395 Using ethernet@ff3f0000 device
986 01:22:50.780897 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
987 01:22:50.786336 Filename '950721/tftp-deploy-06i4dh30/kernel/uImage'.
988 01:22:50.790259 Load address: 0x1080000
989 01:22:54.845059 Loading: *################################################## 63.4 MiB
990 01:22:54.846049 15.6 MiB/s
991 01:22:54.846359 done
992 01:22:54.849440 Bytes transferred = 66443840 (3f5da40 hex)
993 01:22:54.849989 Sending with 10 millisecond of delay
995 01:22:59.544927 => tftpboot 0x08000000 950721/tftp-deploy-06i4dh30/ramdisk/ramdisk.cpio.gz.uboot
996 01:22:59.555496 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
997 01:22:59.556325 tftpboot 0x08000000 950721/tftp-deploy-06i4dh30/ramdisk/ramdisk.cpio.gz.uboot
998 01:22:59.556762 Speed: 1000, full duplex
999 01:22:59.557165 Using ethernet@ff3f0000 device
1000 01:22:59.558313 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1001 01:22:59.570072 Filename '950721/tftp-deploy-06i4dh30/ramdisk/ramdisk.cpio.gz.uboot'.
1002 01:22:59.570625 Load address: 0x8000000
1003 01:23:01.566046 Loading: *################################################# UDP wrong checksum 00000007 0000efb8
1004 01:23:06.566947 T UDP wrong checksum 00000007 0000efb8
1005 01:23:16.570062 T T UDP wrong checksum 00000007 0000efb8
1006 01:23:36.573318 T T T UDP wrong checksum 00000007 0000efb8
1007 01:23:50.096319 T T T UDP wrong checksum 000000ff 00001747
1008 01:23:50.116276 UDP wrong checksum 000000ff 0000a039
1009 01:23:56.580173 T
1010 01:23:56.580852 Retry count exceeded; starting again
1012 01:23:56.582357 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1015 01:23:56.584429 end: 2.4 uboot-commands (duration 00:01:48) [common]
1017 01:23:56.585956 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1019 01:23:56.587119 end: 2 uboot-action (duration 00:01:48) [common]
1021 01:23:56.589127 Cleaning after the job
1022 01:23:56.589776 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/ramdisk
1023 01:23:56.591147 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/kernel
1024 01:23:56.602902 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/dtb
1025 01:23:56.604280 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/nfsrootfs
1026 01:23:56.659623 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950721/tftp-deploy-06i4dh30/modules
1027 01:23:56.668377 start: 4.1 power-off (timeout 00:00:30) [common]
1028 01:23:56.669013 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1029 01:23:56.702269 >> OK - accepted request
1030 01:23:56.704497 Returned 0 in 0 seconds
1031 01:23:56.805353 end: 4.1 power-off (duration 00:00:00) [common]
1033 01:23:56.806402 start: 4.2 read-feedback (timeout 00:10:00) [common]
1034 01:23:56.807095 Listened to connection for namespace 'common' for up to 1s
1035 01:23:57.808079 Finalising connection for namespace 'common'
1036 01:23:57.808635 Disconnecting from shell: Finalise
1037 01:23:57.808973 =>
1038 01:23:57.909789 end: 4.2 read-feedback (duration 00:00:01) [common]
1039 01:23:57.910832 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950721
1040 01:23:59.763498 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950721
1041 01:23:59.764145 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.