Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 5
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 03:24:07.722123 lava-dispatcher, installed at version: 2024.01
2 03:24:07.722892 start: 0 validate
3 03:24:07.723365 Start time: 2024-11-07 03:24:07.723336+00:00 (UTC)
4 03:24:07.723913 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:24:07.724483 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 03:24:07.770180 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:24:07.770732 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 03:24:07.804500 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:24:07.805119 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 03:24:07.840065 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:24:07.840550 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 03:24:07.875252 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 03:24:07.875971 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
14 03:24:07.920959 validate duration: 0.20
16 03:24:07.922455 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 03:24:07.923065 start: 1.1 download-retry (timeout 00:10:00) [common]
18 03:24:07.923672 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 03:24:07.924671 Not decompressing ramdisk as can be used compressed.
20 03:24:07.925439 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 03:24:07.925952 saving as /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/ramdisk/initrd.cpio.gz
22 03:24:07.926457 total size: 5628169 (5 MB)
23 03:24:07.970670 progress 0 % (0 MB)
24 03:24:07.979201 progress 5 % (0 MB)
25 03:24:07.988507 progress 10 % (0 MB)
26 03:24:07.996716 progress 15 % (0 MB)
27 03:24:08.004599 progress 20 % (1 MB)
28 03:24:08.008298 progress 25 % (1 MB)
29 03:24:08.012408 progress 30 % (1 MB)
30 03:24:08.016614 progress 35 % (1 MB)
31 03:24:08.020443 progress 40 % (2 MB)
32 03:24:08.024619 progress 45 % (2 MB)
33 03:24:08.028375 progress 50 % (2 MB)
34 03:24:08.032550 progress 55 % (2 MB)
35 03:24:08.036653 progress 60 % (3 MB)
36 03:24:08.040390 progress 65 % (3 MB)
37 03:24:08.044638 progress 70 % (3 MB)
38 03:24:08.048350 progress 75 % (4 MB)
39 03:24:08.052460 progress 80 % (4 MB)
40 03:24:08.056217 progress 85 % (4 MB)
41 03:24:08.060306 progress 90 % (4 MB)
42 03:24:08.064263 progress 95 % (5 MB)
43 03:24:08.067536 progress 100 % (5 MB)
44 03:24:08.068212 5 MB downloaded in 0.14 s (37.87 MB/s)
45 03:24:08.068766 end: 1.1.1 http-download (duration 00:00:00) [common]
47 03:24:08.069707 end: 1.1 download-retry (duration 00:00:00) [common]
48 03:24:08.070017 start: 1.2 download-retry (timeout 00:10:00) [common]
49 03:24:08.070303 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 03:24:08.070791 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/clang-15/kernel/Image
51 03:24:08.071053 saving as /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/kernel/Image
52 03:24:08.071273 total size: 37878272 (36 MB)
53 03:24:08.071494 No compression specified
54 03:24:08.112467 progress 0 % (0 MB)
55 03:24:08.136702 progress 5 % (1 MB)
56 03:24:08.160977 progress 10 % (3 MB)
57 03:24:08.185339 progress 15 % (5 MB)
58 03:24:08.209668 progress 20 % (7 MB)
59 03:24:08.233707 progress 25 % (9 MB)
60 03:24:08.257990 progress 30 % (10 MB)
61 03:24:08.282544 progress 35 % (12 MB)
62 03:24:08.307028 progress 40 % (14 MB)
63 03:24:08.331573 progress 45 % (16 MB)
64 03:24:08.355438 progress 50 % (18 MB)
65 03:24:08.379686 progress 55 % (19 MB)
66 03:24:08.403912 progress 60 % (21 MB)
67 03:24:08.428421 progress 65 % (23 MB)
68 03:24:08.453486 progress 70 % (25 MB)
69 03:24:08.477442 progress 75 % (27 MB)
70 03:24:08.501935 progress 80 % (28 MB)
71 03:24:08.526450 progress 85 % (30 MB)
72 03:24:08.551103 progress 90 % (32 MB)
73 03:24:08.575852 progress 95 % (34 MB)
74 03:24:08.599277 progress 100 % (36 MB)
75 03:24:08.600045 36 MB downloaded in 0.53 s (68.32 MB/s)
76 03:24:08.600525 end: 1.2.1 http-download (duration 00:00:01) [common]
78 03:24:08.601353 end: 1.2 download-retry (duration 00:00:01) [common]
79 03:24:08.601629 start: 1.3 download-retry (timeout 00:09:59) [common]
80 03:24:08.601897 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 03:24:08.602366 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 03:24:08.602638 saving as /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/dtb/meson-g12b-a311d-libretech-cc.dtb
83 03:24:08.602849 total size: 54703 (0 MB)
84 03:24:08.603058 No compression specified
85 03:24:08.649940 progress 59 % (0 MB)
86 03:24:08.650773 progress 100 % (0 MB)
87 03:24:08.651315 0 MB downloaded in 0.05 s (1.08 MB/s)
88 03:24:08.651798 end: 1.3.1 http-download (duration 00:00:00) [common]
90 03:24:08.652660 end: 1.3 download-retry (duration 00:00:00) [common]
91 03:24:08.652926 start: 1.4 download-retry (timeout 00:09:59) [common]
92 03:24:08.653191 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 03:24:08.653652 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 03:24:08.653896 saving as /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/nfsrootfs/full.rootfs.tar
95 03:24:08.654101 total size: 120894716 (115 MB)
96 03:24:08.654313 Using unxz to decompress xz
97 03:24:08.687525 progress 0 % (0 MB)
98 03:24:09.479347 progress 5 % (5 MB)
99 03:24:10.318913 progress 10 % (11 MB)
100 03:24:11.120506 progress 15 % (17 MB)
101 03:24:11.852661 progress 20 % (23 MB)
102 03:24:12.442895 progress 25 % (28 MB)
103 03:24:13.258107 progress 30 % (34 MB)
104 03:24:14.040953 progress 35 % (40 MB)
105 03:24:14.390336 progress 40 % (46 MB)
106 03:24:14.765264 progress 45 % (51 MB)
107 03:24:15.476508 progress 50 % (57 MB)
108 03:24:16.354438 progress 55 % (63 MB)
109 03:24:17.133043 progress 60 % (69 MB)
110 03:24:17.886276 progress 65 % (74 MB)
111 03:24:18.660936 progress 70 % (80 MB)
112 03:24:19.480887 progress 75 % (86 MB)
113 03:24:20.266270 progress 80 % (92 MB)
114 03:24:21.033903 progress 85 % (98 MB)
115 03:24:21.914863 progress 90 % (103 MB)
116 03:24:22.713922 progress 95 % (109 MB)
117 03:24:23.545675 progress 100 % (115 MB)
118 03:24:23.558300 115 MB downloaded in 14.90 s (7.74 MB/s)
119 03:24:23.559196 end: 1.4.1 http-download (duration 00:00:15) [common]
121 03:24:23.560885 end: 1.4 download-retry (duration 00:00:15) [common]
122 03:24:23.561428 start: 1.5 download-retry (timeout 00:09:44) [common]
123 03:24:23.561957 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 03:24:23.562759 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/clang-15/modules.tar.xz
125 03:24:23.563241 saving as /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/modules/modules.tar
126 03:24:23.563660 total size: 11778608 (11 MB)
127 03:24:23.564127 Using unxz to decompress xz
128 03:24:23.610997 progress 0 % (0 MB)
129 03:24:23.682152 progress 5 % (0 MB)
130 03:24:23.760269 progress 10 % (1 MB)
131 03:24:23.860048 progress 15 % (1 MB)
132 03:24:23.959328 progress 20 % (2 MB)
133 03:24:24.041354 progress 25 % (2 MB)
134 03:24:24.120158 progress 30 % (3 MB)
135 03:24:24.202861 progress 35 % (3 MB)
136 03:24:24.285261 progress 40 % (4 MB)
137 03:24:24.362914 progress 45 % (5 MB)
138 03:24:24.451150 progress 50 % (5 MB)
139 03:24:24.535870 progress 55 % (6 MB)
140 03:24:24.624244 progress 60 % (6 MB)
141 03:24:24.708487 progress 65 % (7 MB)
142 03:24:24.792718 progress 70 % (7 MB)
143 03:24:24.877242 progress 75 % (8 MB)
144 03:24:24.962315 progress 80 % (9 MB)
145 03:24:25.044498 progress 85 % (9 MB)
146 03:24:25.129614 progress 90 % (10 MB)
147 03:24:25.210726 progress 95 % (10 MB)
148 03:24:25.289578 progress 100 % (11 MB)
149 03:24:25.301956 11 MB downloaded in 1.74 s (6.46 MB/s)
150 03:24:25.302976 end: 1.5.1 http-download (duration 00:00:02) [common]
152 03:24:25.304044 end: 1.5 download-retry (duration 00:00:02) [common]
153 03:24:25.304547 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 03:24:25.305150 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 03:24:41.656986 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/950284/extract-nfsrootfs-jzmrvmu7
156 03:24:41.657587 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 03:24:41.657872 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 03:24:41.658483 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye
159 03:24:41.658908 makedir: /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin
160 03:24:41.659232 makedir: /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/tests
161 03:24:41.659538 makedir: /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/results
162 03:24:41.659870 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-add-keys
163 03:24:41.660431 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-add-sources
164 03:24:41.660955 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-background-process-start
165 03:24:41.661453 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-background-process-stop
166 03:24:41.661975 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-common-functions
167 03:24:41.662468 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-echo-ipv4
168 03:24:41.662948 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-install-packages
169 03:24:41.663417 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-installed-packages
170 03:24:41.663885 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-os-build
171 03:24:41.664386 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-probe-channel
172 03:24:41.664861 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-probe-ip
173 03:24:41.665333 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-target-ip
174 03:24:41.665802 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-target-mac
175 03:24:41.666269 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-target-storage
176 03:24:41.666831 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-test-case
177 03:24:41.667323 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-test-event
178 03:24:41.667791 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-test-feedback
179 03:24:41.668303 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-test-raise
180 03:24:41.668778 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-test-reference
181 03:24:41.669284 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-test-runner
182 03:24:41.669803 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-test-set
183 03:24:41.670275 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-test-shell
184 03:24:41.670759 Updating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-add-keys (debian)
185 03:24:41.671285 Updating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-add-sources (debian)
186 03:24:41.671781 Updating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-install-packages (debian)
187 03:24:41.672335 Updating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-installed-packages (debian)
188 03:24:41.672832 Updating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/bin/lava-os-build (debian)
189 03:24:41.673267 Creating /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/environment
190 03:24:41.673633 LAVA metadata
191 03:24:41.673893 - LAVA_JOB_ID=950284
192 03:24:41.674109 - LAVA_DISPATCHER_IP=192.168.6.2
193 03:24:41.674469 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 03:24:41.675410 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 03:24:41.675724 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 03:24:41.675932 skipped lava-vland-overlay
197 03:24:41.676199 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 03:24:41.676454 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 03:24:41.676669 skipped lava-multinode-overlay
200 03:24:41.676910 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 03:24:41.677158 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 03:24:41.677404 Loading test definitions
203 03:24:41.677677 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 03:24:41.677895 Using /lava-950284 at stage 0
205 03:24:41.678968 uuid=950284_1.6.2.4.1 testdef=None
206 03:24:41.679274 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 03:24:41.679537 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 03:24:41.681124 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 03:24:41.681915 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 03:24:41.683841 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 03:24:41.684746 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 03:24:41.686582 runner path: /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/0/tests/0_timesync-off test_uuid 950284_1.6.2.4.1
215 03:24:41.687122 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 03:24:41.687927 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 03:24:41.688180 Using /lava-950284 at stage 0
219 03:24:41.688534 Fetching tests from https://github.com/kernelci/test-definitions.git
220 03:24:41.688821 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/0/tests/1_kselftest-alsa'
221 03:24:45.294493 Running '/usr/bin/git checkout kernelci.org
222 03:24:45.574890 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 03:24:45.576815 uuid=950284_1.6.2.4.5 testdef=None
224 03:24:45.577506 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 03:24:45.579107 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 03:24:45.585039 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 03:24:45.586777 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 03:24:45.594619 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 03:24:45.596471 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 03:24:45.604132 runner path: /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/0/tests/1_kselftest-alsa test_uuid 950284_1.6.2.4.5
234 03:24:45.604707 BOARD='meson-g12b-a311d-libretech-cc'
235 03:24:45.605151 BRANCH='mainline'
236 03:24:45.605581 SKIPFILE='/dev/null'
237 03:24:45.606010 SKIP_INSTALL='True'
238 03:24:45.606436 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/clang-15/kselftest.tar.xz'
239 03:24:45.606876 TST_CASENAME=''
240 03:24:45.607304 TST_CMDFILES='alsa'
241 03:24:45.608382 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 03:24:45.610069 Creating lava-test-runner.conf files
244 03:24:45.610510 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950284/lava-overlay-dyjtcrye/lava-950284/0 for stage 0
245 03:24:45.611228 - 0_timesync-off
246 03:24:45.611726 - 1_kselftest-alsa
247 03:24:45.612487 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 03:24:45.613083 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 03:25:08.740898 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 03:25:08.741343 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 03:25:08.741610 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 03:25:08.741883 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 03:25:08.742149 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 03:25:09.354737 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 03:25:09.355221 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
256 03:25:09.355476 extracting modules file /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950284/extract-nfsrootfs-jzmrvmu7
257 03:25:11.022176 extracting modules file /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950284/extract-overlay-ramdisk-54u3p2i3/ramdisk
258 03:25:12.435599 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 03:25:12.436101 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 03:25:12.436390 [common] Applying overlay to NFS
261 03:25:12.436605 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950284/compress-overlay-nsnn_um0/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950284/extract-nfsrootfs-jzmrvmu7
262 03:25:15.156752 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 03:25:15.157244 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 03:25:15.157521 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 03:25:15.157754 Converting downloaded kernel to a uImage
266 03:25:15.158069 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/kernel/Image /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/kernel/uImage
267 03:25:15.537135 output: Image Name:
268 03:25:15.537557 output: Created: Thu Nov 7 03:25:15 2024
269 03:25:15.537770 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 03:25:15.537977 output: Data Size: 37878272 Bytes = 36990.50 KiB = 36.12 MiB
271 03:25:15.538178 output: Load Address: 01080000
272 03:25:15.538380 output: Entry Point: 01080000
273 03:25:15.538578 output:
274 03:25:15.538913 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 03:25:15.539182 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 03:25:15.539449 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 03:25:15.539705 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 03:25:15.539965 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 03:25:15.540275 Building ramdisk /var/lib/lava/dispatcher/tmp/950284/extract-overlay-ramdisk-54u3p2i3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950284/extract-overlay-ramdisk-54u3p2i3/ramdisk
280 03:25:17.750140 >> 173435 blocks
281 03:25:25.745265 Adding RAMdisk u-boot header.
282 03:25:25.745713 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950284/extract-overlay-ramdisk-54u3p2i3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950284/extract-overlay-ramdisk-54u3p2i3/ramdisk.cpio.gz.uboot
283 03:25:26.002485 output: Image Name:
284 03:25:26.002913 output: Created: Thu Nov 7 03:25:25 2024
285 03:25:26.003125 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 03:25:26.003331 output: Data Size: 24147244 Bytes = 23581.29 KiB = 23.03 MiB
287 03:25:26.003534 output: Load Address: 00000000
288 03:25:26.003734 output: Entry Point: 00000000
289 03:25:26.003935 output:
290 03:25:26.005299 rename /var/lib/lava/dispatcher/tmp/950284/extract-overlay-ramdisk-54u3p2i3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/ramdisk/ramdisk.cpio.gz.uboot
291 03:25:26.006085 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 03:25:26.006683 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 03:25:26.007264 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 03:25:26.007769 No LXC device requested
295 03:25:26.008364 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 03:25:26.008929 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 03:25:26.009476 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 03:25:26.009932 Checking files for TFTP limit of 4294967296 bytes.
299 03:25:26.012891 end: 1 tftp-deploy (duration 00:01:18) [common]
300 03:25:26.013523 start: 2 uboot-action (timeout 00:05:00) [common]
301 03:25:26.014096 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 03:25:26.014642 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 03:25:26.015195 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 03:25:26.015772 Using kernel file from prepare-kernel: 950284/tftp-deploy-2vebo3i3/kernel/uImage
305 03:25:26.016502 substitutions:
306 03:25:26.016959 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 03:25:26.017408 - {DTB_ADDR}: 0x01070000
308 03:25:26.017851 - {DTB}: 950284/tftp-deploy-2vebo3i3/dtb/meson-g12b-a311d-libretech-cc.dtb
309 03:25:26.018299 - {INITRD}: 950284/tftp-deploy-2vebo3i3/ramdisk/ramdisk.cpio.gz.uboot
310 03:25:26.018740 - {KERNEL_ADDR}: 0x01080000
311 03:25:26.019175 - {KERNEL}: 950284/tftp-deploy-2vebo3i3/kernel/uImage
312 03:25:26.019611 - {LAVA_MAC}: None
313 03:25:26.020111 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/950284/extract-nfsrootfs-jzmrvmu7
314 03:25:26.020561 - {NFS_SERVER_IP}: 192.168.6.2
315 03:25:26.020993 - {PRESEED_CONFIG}: None
316 03:25:26.021423 - {PRESEED_LOCAL}: None
317 03:25:26.021860 - {RAMDISK_ADDR}: 0x08000000
318 03:25:26.022289 - {RAMDISK}: 950284/tftp-deploy-2vebo3i3/ramdisk/ramdisk.cpio.gz.uboot
319 03:25:26.022723 - {ROOT_PART}: None
320 03:25:26.023151 - {ROOT}: None
321 03:25:26.023577 - {SERVER_IP}: 192.168.6.2
322 03:25:26.024053 - {TEE_ADDR}: 0x83000000
323 03:25:26.024497 - {TEE}: None
324 03:25:26.024925 Parsed boot commands:
325 03:25:26.025347 - setenv autoload no
326 03:25:26.025780 - setenv initrd_high 0xffffffff
327 03:25:26.026209 - setenv fdt_high 0xffffffff
328 03:25:26.026634 - dhcp
329 03:25:26.027063 - setenv serverip 192.168.6.2
330 03:25:26.027494 - tftpboot 0x01080000 950284/tftp-deploy-2vebo3i3/kernel/uImage
331 03:25:26.027925 - tftpboot 0x08000000 950284/tftp-deploy-2vebo3i3/ramdisk/ramdisk.cpio.gz.uboot
332 03:25:26.028390 - tftpboot 0x01070000 950284/tftp-deploy-2vebo3i3/dtb/meson-g12b-a311d-libretech-cc.dtb
333 03:25:26.028826 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950284/extract-nfsrootfs-jzmrvmu7,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 03:25:26.029272 - bootm 0x01080000 0x08000000 0x01070000
335 03:25:26.029833 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 03:25:26.031479 start: 2.3 connect-device (timeout 00:05:00) [common]
338 03:25:26.031944 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 03:25:26.046996 Setting prompt string to ['lava-test: # ']
340 03:25:26.048691 end: 2.3 connect-device (duration 00:00:00) [common]
341 03:25:26.049367 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 03:25:26.049996 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 03:25:26.050587 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 03:25:26.051808 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 03:25:26.089822 >> OK - accepted request
346 03:25:26.092132 Returned 0 in 0 seconds
347 03:25:26.193321 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 03:25:26.195110 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 03:25:26.195716 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 03:25:26.196330 Setting prompt string to ['Hit any key to stop autoboot']
352 03:25:26.196819 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 03:25:26.198521 Trying 192.168.56.21...
354 03:25:26.199039 Connected to conserv1.
355 03:25:26.199486 Escape character is '^]'.
356 03:25:26.199930
357 03:25:26.200426 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 03:25:26.200888
359 03:25:37.569662 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 03:25:37.570090 bl2_stage_init 0x01
361 03:25:37.570317 bl2_stage_init 0x81
362 03:25:37.575315 hw id: 0x0000 - pwm id 0x01
363 03:25:37.575648 bl2_stage_init 0xc1
364 03:25:37.575870 bl2_stage_init 0x02
365 03:25:37.576112
366 03:25:37.580325 L0:00000000
367 03:25:37.580617 L1:20000703
368 03:25:37.580832 L2:00008067
369 03:25:37.581037 L3:14000000
370 03:25:37.583331 B2:00402000
371 03:25:37.583605 B1:e0f83180
372 03:25:37.583818
373 03:25:37.584038 TE: 58159
374 03:25:37.584241
375 03:25:37.594627 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 03:25:37.594923
377 03:25:37.595127 Board ID = 1
378 03:25:37.595325 Set A53 clk to 24M
379 03:25:37.595520 Set A73 clk to 24M
380 03:25:37.600152 Set clk81 to 24M
381 03:25:37.600432 A53 clk: 1200 MHz
382 03:25:37.600634 A73 clk: 1200 MHz
383 03:25:37.603705 CLK81: 166.6M
384 03:25:37.604000 smccc: 00012ab5
385 03:25:37.609289 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 03:25:37.609567 board id: 1
387 03:25:37.619751 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 03:25:37.630377 fw parse done
389 03:25:37.636313 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 03:25:37.678966 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 03:25:37.689932 PIEI prepare done
392 03:25:37.690493 fastboot data load
393 03:25:37.690935 fastboot data verify
394 03:25:37.696426 verify result: 266
395 03:25:37.701154 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 03:25:37.701722 LPDDR4 probe
397 03:25:37.702186 ddr clk to 1584MHz
398 03:25:37.709076 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 03:25:37.746448
400 03:25:37.747049 dmc_version 0001
401 03:25:37.753087 Check phy result
402 03:25:37.758947 INFO : End of CA training
403 03:25:37.759484 INFO : End of initialization
404 03:25:37.764544 INFO : Training has run successfully!
405 03:25:37.765083 Check phy result
406 03:25:37.770098 INFO : End of initialization
407 03:25:37.770642 INFO : End of read enable training
408 03:25:37.773376 INFO : End of fine write leveling
409 03:25:37.778962 INFO : End of Write leveling coarse delay
410 03:25:37.784585 INFO : Training has run successfully!
411 03:25:37.785129 Check phy result
412 03:25:37.785643 INFO : End of initialization
413 03:25:37.790152 INFO : End of read dq deskew training
414 03:25:37.795748 INFO : End of MPR read delay center optimization
415 03:25:37.796336 INFO : End of write delay center optimization
416 03:25:37.801342 INFO : End of read delay center optimization
417 03:25:37.806921 INFO : End of max read latency training
418 03:25:37.807466 INFO : Training has run successfully!
419 03:25:37.812560 1D training succeed
420 03:25:37.818550 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 03:25:37.866145 Check phy result
422 03:25:37.866751 INFO : End of initialization
423 03:25:37.887681 INFO : End of 2D read delay Voltage center optimization
424 03:25:37.907807 INFO : End of 2D read delay Voltage center optimization
425 03:25:37.959793 INFO : End of 2D write delay Voltage center optimization
426 03:25:38.009074 INFO : End of 2D write delay Voltage center optimization
427 03:25:38.014555 INFO : Training has run successfully!
428 03:25:38.015095
429 03:25:38.015575 channel==0
430 03:25:38.020229 RxClkDly_Margin_A0==88 ps 9
431 03:25:38.020781 TxDqDly_Margin_A0==98 ps 10
432 03:25:38.025763 RxClkDly_Margin_A1==88 ps 9
433 03:25:38.026313 TxDqDly_Margin_A1==98 ps 10
434 03:25:38.026759 TrainedVREFDQ_A0==74
435 03:25:38.031412 TrainedVREFDQ_A1==74
436 03:25:38.032020 VrefDac_Margin_A0==25
437 03:25:38.032491 DeviceVref_Margin_A0==40
438 03:25:38.036930 VrefDac_Margin_A1==25
439 03:25:38.037458 DeviceVref_Margin_A1==40
440 03:25:38.037896
441 03:25:38.038336
442 03:25:38.042549 channel==1
443 03:25:38.043070 RxClkDly_Margin_A0==98 ps 10
444 03:25:38.043505 TxDqDly_Margin_A0==98 ps 10
445 03:25:38.048158 RxClkDly_Margin_A1==98 ps 10
446 03:25:38.048687 TxDqDly_Margin_A1==88 ps 9
447 03:25:38.053741 TrainedVREFDQ_A0==77
448 03:25:38.054291 TrainedVREFDQ_A1==77
449 03:25:38.054740 VrefDac_Margin_A0==22
450 03:25:38.059417 DeviceVref_Margin_A0==37
451 03:25:38.059957 VrefDac_Margin_A1==22
452 03:25:38.064867 DeviceVref_Margin_A1==37
453 03:25:38.065396
454 03:25:38.065843 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 03:25:38.070445
456 03:25:38.098475 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 03:25:38.099135 2D training succeed
458 03:25:38.104094 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 03:25:38.109677 auto size-- 65535DDR cs0 size: 2048MB
460 03:25:38.110211 DDR cs1 size: 2048MB
461 03:25:38.115308 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 03:25:38.115854 cs0 DataBus test pass
463 03:25:38.120867 cs1 DataBus test pass
464 03:25:38.121393 cs0 AddrBus test pass
465 03:25:38.121831 cs1 AddrBus test pass
466 03:25:38.122265
467 03:25:38.126461 100bdlr_step_size ps== 420
468 03:25:38.127009 result report
469 03:25:38.132083 boot times 0Enable ddr reg access
470 03:25:38.137527 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 03:25:38.150979 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 03:25:38.723104 0.0;M3 CHK:0;cm4_sp_mode 0
473 03:25:38.723541 MVN_1=0x00000000
474 03:25:38.728500 MVN_2=0x00000000
475 03:25:38.734297 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 03:25:38.734611 OPS=0x10
477 03:25:38.734833 ring efuse init
478 03:25:38.735039 chipver efuse init
479 03:25:38.742743 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 03:25:38.743456 [0.018961 Inits done]
481 03:25:38.744064 secure task start!
482 03:25:38.750173 high task start!
483 03:25:38.750771 low task start!
484 03:25:38.751318 run into bl31
485 03:25:38.756765 NOTICE: BL31: v1.3(release):4fc40b1
486 03:25:38.764620 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 03:25:38.765241 NOTICE: BL31: G12A normal boot!
488 03:25:38.789797 NOTICE: BL31: BL33 decompress pass
489 03:25:38.795613 ERROR: Error initializing runtime service opteed_fast
490 03:25:40.028487
491 03:25:40.028986
492 03:25:40.036982 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 03:25:40.037510
494 03:25:40.037942 Model: Libre Computer AML-A311D-CC Alta
495 03:25:40.245429 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 03:25:40.268932 DRAM: 2 GiB (effective 3.8 GiB)
497 03:25:40.411976 Core: 408 devices, 31 uclasses, devicetree: separate
498 03:25:40.417773 WDT: Not starting watchdog@f0d0
499 03:25:40.449831 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 03:25:40.462426 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 03:25:40.467335 ** Bad device specification mmc 0 **
502 03:25:40.477602 Card did not respond to voltage select! : -110
503 03:25:40.485352 ** Bad device specification mmc 0 **
504 03:25:40.485830 Couldn't find partition mmc 0
505 03:25:40.493636 Card did not respond to voltage select! : -110
506 03:25:40.499142 ** Bad device specification mmc 0 **
507 03:25:40.499627 Couldn't find partition mmc 0
508 03:25:40.504202 Error: could not access storage.
509 03:25:41.769688 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 03:25:41.770108 bl2_stage_init 0x01
511 03:25:41.770331 bl2_stage_init 0x81
512 03:25:41.775297 hw id: 0x0000 - pwm id 0x01
513 03:25:41.775687 bl2_stage_init 0xc1
514 03:25:41.776112 bl2_stage_init 0x02
515 03:25:41.776645
516 03:25:41.780914 L0:00000000
517 03:25:41.781357 L1:20000703
518 03:25:41.781770 L2:00008067
519 03:25:41.782177 L3:14000000
520 03:25:41.786571 B2:00402000
521 03:25:41.787011 B1:e0f83180
522 03:25:41.787419
523 03:25:41.787822 TE: 58124
524 03:25:41.788279
525 03:25:41.792092 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 03:25:41.792529
527 03:25:41.792936 Board ID = 1
528 03:25:41.797763 Set A53 clk to 24M
529 03:25:41.798194 Set A73 clk to 24M
530 03:25:41.798603 Set clk81 to 24M
531 03:25:41.803280 A53 clk: 1200 MHz
532 03:25:41.803711 A73 clk: 1200 MHz
533 03:25:41.804153 CLK81: 166.6M
534 03:25:41.804558 smccc: 00012a92
535 03:25:41.808813 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 03:25:41.814515 board id: 1
537 03:25:41.820488 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 03:25:41.830860 fw parse done
539 03:25:41.836828 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 03:25:41.879498 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 03:25:41.890422 PIEI prepare done
542 03:25:41.890890 fastboot data load
543 03:25:41.891308 fastboot data verify
544 03:25:41.896058 verify result: 266
545 03:25:41.901733 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 03:25:41.902179 LPDDR4 probe
547 03:25:41.902591 ddr clk to 1584MHz
548 03:25:41.909598 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 03:25:41.948405
550 03:25:41.948971 dmc_version 0001
551 03:25:41.953749 Check phy result
552 03:25:41.959905 INFO : End of CA training
553 03:25:41.960316 INFO : End of initialization
554 03:25:41.965148 INFO : Training has run successfully!
555 03:25:41.965548 Check phy result
556 03:25:41.970778 INFO : End of initialization
557 03:25:41.971262 INFO : End of read enable training
558 03:25:41.976495 INFO : End of fine write leveling
559 03:25:41.982317 INFO : End of Write leveling coarse delay
560 03:25:41.982717 INFO : Training has run successfully!
561 03:25:41.982948 Check phy result
562 03:25:41.989364 INFO : End of initialization
563 03:25:41.989988 INFO : End of read dq deskew training
564 03:25:41.993399 INFO : End of MPR read delay center optimization
565 03:25:41.999405 INFO : End of write delay center optimization
566 03:25:42.004408 INFO : End of read delay center optimization
567 03:25:42.004793 INFO : End of max read latency training
568 03:25:42.010214 INFO : Training has run successfully!
569 03:25:42.010751 1D training succeed
570 03:25:42.019683 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 03:25:42.071925 Check phy result
572 03:25:42.072380 INFO : End of initialization
573 03:25:42.088444 INFO : End of 2D read delay Voltage center optimization
574 03:25:42.108452 INFO : End of 2D read delay Voltage center optimization
575 03:25:42.161892 INFO : End of 2D write delay Voltage center optimization
576 03:25:42.210030 INFO : End of 2D write delay Voltage center optimization
577 03:25:42.215194 INFO : Training has run successfully!
578 03:25:42.215608
579 03:25:42.215840 channel==0
580 03:25:42.221398 RxClkDly_Margin_A0==88 ps 9
581 03:25:42.221946 TxDqDly_Margin_A0==98 ps 10
582 03:25:42.226356 RxClkDly_Margin_A1==88 ps 9
583 03:25:42.226912 TxDqDly_Margin_A1==88 ps 9
584 03:25:42.227180 TrainedVREFDQ_A0==74
585 03:25:42.231835 TrainedVREFDQ_A1==74
586 03:25:42.232238 VrefDac_Margin_A0==25
587 03:25:42.232460 DeviceVref_Margin_A0==40
588 03:25:42.237528 VrefDac_Margin_A1==25
589 03:25:42.238070 DeviceVref_Margin_A1==40
590 03:25:42.238426
591 03:25:42.238767
592 03:25:42.239104 channel==1
593 03:25:42.243017 RxClkDly_Margin_A0==98 ps 10
594 03:25:42.243401 TxDqDly_Margin_A0==98 ps 10
595 03:25:42.248656 RxClkDly_Margin_A1==98 ps 10
596 03:25:42.249173 TxDqDly_Margin_A1==88 ps 9
597 03:25:42.254199 TrainedVREFDQ_A0==77
598 03:25:42.254588 TrainedVREFDQ_A1==77
599 03:25:42.254813 VrefDac_Margin_A0==22
600 03:25:42.259977 DeviceVref_Margin_A0==37
601 03:25:42.260346 VrefDac_Margin_A1==22
602 03:25:42.265475 DeviceVref_Margin_A1==37
603 03:25:42.265807
604 03:25:42.266026 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 03:25:42.266239
606 03:25:42.299078 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
607 03:25:42.299720 2D training succeed
608 03:25:42.304740 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 03:25:42.310270 auto size-- 65535DDR cs0 size: 2048MB
610 03:25:42.310738 DDR cs1 size: 2048MB
611 03:25:42.315919 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 03:25:42.316409 cs0 DataBus test pass
613 03:25:42.321458 cs1 DataBus test pass
614 03:25:42.321940 cs0 AddrBus test pass
615 03:25:42.322351 cs1 AddrBus test pass
616 03:25:42.322747
617 03:25:42.327194 100bdlr_step_size ps== 420
618 03:25:42.327688 result report
619 03:25:42.332770 boot times 0Enable ddr reg access
620 03:25:42.338092 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 03:25:42.351890 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 03:25:42.923617 0.0;M3 CHK:0;cm4_sp_mode 0
623 03:25:42.924312 MVN_1=0x00000000
624 03:25:42.928902 MVN_2=0x00000000
625 03:25:42.934814 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 03:25:42.935404 OPS=0x10
627 03:25:42.935868 ring efuse init
628 03:25:42.936354 chipver efuse init
629 03:25:42.942918 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 03:25:42.943431 [0.018961 Inits done]
631 03:25:42.943826 secure task start!
632 03:25:42.950405 high task start!
633 03:25:42.950846 low task start!
634 03:25:42.951240 run into bl31
635 03:25:42.957061 NOTICE: BL31: v1.3(release):4fc40b1
636 03:25:42.964869 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 03:25:42.965304 NOTICE: BL31: G12A normal boot!
638 03:25:42.990254 NOTICE: BL31: BL33 decompress pass
639 03:25:42.996023 ERROR: Error initializing runtime service opteed_fast
640 03:25:44.228864
641 03:25:44.229475
642 03:25:44.237169 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 03:25:44.237628
644 03:25:44.238046 Model: Libre Computer AML-A311D-CC Alta
645 03:25:44.445684 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 03:25:44.468994 DRAM: 2 GiB (effective 3.8 GiB)
647 03:25:44.612111 Core: 408 devices, 31 uclasses, devicetree: separate
648 03:25:44.617825 WDT: Not starting watchdog@f0d0
649 03:25:44.650111 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 03:25:44.662551 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 03:25:44.667519 ** Bad device specification mmc 0 **
652 03:25:44.677928 Card did not respond to voltage select! : -110
653 03:25:44.685521 ** Bad device specification mmc 0 **
654 03:25:44.685978 Couldn't find partition mmc 0
655 03:25:44.693876 Card did not respond to voltage select! : -110
656 03:25:44.699386 ** Bad device specification mmc 0 **
657 03:25:44.699847 Couldn't find partition mmc 0
658 03:25:44.704417 Error: could not access storage.
659 03:25:45.048032 Net: eth0: ethernet@ff3f0000
660 03:25:45.048573 starting USB...
661 03:25:45.299819 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 03:25:45.300387 Starting the controller
663 03:25:45.306741 USB XHCI 1.10
664 03:25:47.021516 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
665 03:25:47.021961 bl2_stage_init 0x81
666 03:25:47.027554 hw id: 0x0000 - pwm id 0x01
667 03:25:47.027955 bl2_stage_init 0xc1
668 03:25:47.028327 bl2_stage_init 0x02
669 03:25:47.028638
670 03:25:47.032921 L0:00000000
671 03:25:47.033209 L1:20000703
672 03:25:47.033416 L2:00008067
673 03:25:47.033616 L3:14000000
674 03:25:47.033809 B2:00402000
675 03:25:47.035453 B1:e0f83180
676 03:25:47.035792
677 03:25:47.036121 TE: 58150
678 03:25:47.036420
679 03:25:47.046559 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 03:25:47.046915
681 03:25:47.047218 Board ID = 1
682 03:25:47.047510 Set A53 clk to 24M
683 03:25:47.047797 Set A73 clk to 24M
684 03:25:47.052175 Set clk81 to 24M
685 03:25:47.052515 A53 clk: 1200 MHz
686 03:25:47.052738 A73 clk: 1200 MHz
687 03:25:47.057648 CLK81: 166.6M
688 03:25:47.057926 smccc: 00012aac
689 03:25:47.063378 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 03:25:47.063655 board id: 1
691 03:25:47.072072 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 03:25:47.082447 fw parse done
693 03:25:47.088455 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 03:25:47.131075 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 03:25:47.141926 PIEI prepare done
696 03:25:47.142198 fastboot data load
697 03:25:47.142411 fastboot data verify
698 03:25:47.147592 verify result: 266
699 03:25:47.153191 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 03:25:47.153561 LPDDR4 probe
701 03:25:47.153877 ddr clk to 1584MHz
702 03:25:47.161162 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 03:25:47.198487
704 03:25:47.198769 dmc_version 0001
705 03:25:47.205177 Check phy result
706 03:25:47.211040 INFO : End of CA training
707 03:25:47.211296 INFO : End of initialization
708 03:25:47.216617 INFO : Training has run successfully!
709 03:25:47.216873 Check phy result
710 03:25:47.222208 INFO : End of initialization
711 03:25:47.222472 INFO : End of read enable training
712 03:25:47.225481 INFO : End of fine write leveling
713 03:25:47.231051 INFO : End of Write leveling coarse delay
714 03:25:47.236675 INFO : Training has run successfully!
715 03:25:47.236933 Check phy result
716 03:25:47.237137 INFO : End of initialization
717 03:25:47.242249 INFO : End of read dq deskew training
718 03:25:47.247858 INFO : End of MPR read delay center optimization
719 03:25:47.248167 INFO : End of write delay center optimization
720 03:25:47.253465 INFO : End of read delay center optimization
721 03:25:47.259033 INFO : End of max read latency training
722 03:25:47.259289 INFO : Training has run successfully!
723 03:25:47.264738 1D training succeed
724 03:25:47.270587 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 03:25:47.318211 Check phy result
726 03:25:47.318513 INFO : End of initialization
727 03:25:47.340670 INFO : End of 2D read delay Voltage center optimization
728 03:25:47.360725 INFO : End of 2D read delay Voltage center optimization
729 03:25:47.412809 INFO : End of 2D write delay Voltage center optimization
730 03:25:47.462738 INFO : End of 2D write delay Voltage center optimization
731 03:25:47.467581 INFO : Training has run successfully!
732 03:25:47.468020
733 03:25:47.468280 channel==0
734 03:25:47.473111 RxClkDly_Margin_A0==88 ps 9
735 03:25:47.473385 TxDqDly_Margin_A0==98 ps 10
736 03:25:47.478664 RxClkDly_Margin_A1==88 ps 9
737 03:25:47.479064 TxDqDly_Margin_A1==88 ps 9
738 03:25:47.479407 TrainedVREFDQ_A0==74
739 03:25:47.484297 TrainedVREFDQ_A1==74
740 03:25:47.484575 VrefDac_Margin_A0==25
741 03:25:47.485079 DeviceVref_Margin_A0==40
742 03:25:47.489931 VrefDac_Margin_A1==24
743 03:25:47.490209 DeviceVref_Margin_A1==40
744 03:25:47.490421
745 03:25:47.490628
746 03:25:47.490829 channel==1
747 03:25:47.495519 RxClkDly_Margin_A0==98 ps 10
748 03:25:47.495925 TxDqDly_Margin_A0==88 ps 9
749 03:25:47.501180 RxClkDly_Margin_A1==98 ps 10
750 03:25:47.501628 TxDqDly_Margin_A1==88 ps 9
751 03:25:47.506722 TrainedVREFDQ_A0==77
752 03:25:47.507146 TrainedVREFDQ_A1==77
753 03:25:47.507479 VrefDac_Margin_A0==22
754 03:25:47.512296 DeviceVref_Margin_A0==37
755 03:25:47.512588 VrefDac_Margin_A1==22
756 03:25:47.517818 DeviceVref_Margin_A1==37
757 03:25:47.518227
758 03:25:47.518558 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 03:25:47.518804
760 03:25:47.551477 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
761 03:25:47.551854 2D training succeed
762 03:25:47.557007 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 03:25:47.562641 auto size-- 65535DDR cs0 size: 2048MB
764 03:25:47.562934 DDR cs1 size: 2048MB
765 03:25:47.568238 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 03:25:47.568642 cs0 DataBus test pass
767 03:25:47.573791 cs1 DataBus test pass
768 03:25:47.574161 cs0 AddrBus test pass
769 03:25:47.574391 cs1 AddrBus test pass
770 03:25:47.574599
771 03:25:47.579473 100bdlr_step_size ps== 420
772 03:25:47.579871 result report
773 03:25:47.585024 boot times 0Enable ddr reg access
774 03:25:47.590279 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 03:25:47.603743 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 03:25:48.175805 0.0;M3 CHK:0;cm4_sp_mode 0
777 03:25:48.176270 MVN_1=0x00000000
778 03:25:48.181216 MVN_2=0x00000000
779 03:25:48.187009 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 03:25:48.187290 OPS=0x10
781 03:25:48.187508 ring efuse init
782 03:25:48.187717 chipver efuse init
783 03:25:48.192606 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 03:25:48.198187 [0.018961 Inits done]
785 03:25:48.198723 secure task start!
786 03:25:48.198958 high task start!
787 03:25:48.202884 low task start!
788 03:25:48.203437 run into bl31
789 03:25:48.209530 NOTICE: BL31: v1.3(release):4fc40b1
790 03:25:48.217246 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 03:25:48.217731 NOTICE: BL31: G12A normal boot!
792 03:25:48.242591 NOTICE: BL31: BL33 decompress pass
793 03:25:48.248282 ERROR: Error initializing runtime service opteed_fast
794 03:25:49.481283
795 03:25:49.481978
796 03:25:49.489586 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 03:25:49.490145
798 03:25:49.490613 Model: Libre Computer AML-A311D-CC Alta
799 03:25:49.698182 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 03:25:49.721388 DRAM: 2 GiB (effective 3.8 GiB)
801 03:25:49.864474 Core: 408 devices, 31 uclasses, devicetree: separate
802 03:25:49.870368 WDT: Not starting watchdog@f0d0
803 03:25:49.902600 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 03:25:49.915039 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 03:25:49.920074 ** Bad device specification mmc 0 **
806 03:25:49.930363 Card did not respond to voltage select! : -110
807 03:25:49.938046 ** Bad device specification mmc 0 **
808 03:25:49.938575 Couldn't find partition mmc 0
809 03:25:49.946377 Card did not respond to voltage select! : -110
810 03:25:49.951911 ** Bad device specification mmc 0 **
811 03:25:49.952470 Couldn't find partition mmc 0
812 03:25:49.956978 Error: could not access storage.
813 03:25:50.299402 Net: eth0: ethernet@ff3f0000
814 03:25:50.300085 starting USB...
815 03:25:50.551149 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 03:25:50.551580 Starting the controller
817 03:25:50.558128 USB XHCI 1.10
818 03:25:52.719865 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 03:25:52.720329 bl2_stage_init 0x01
820 03:25:52.720552 bl2_stage_init 0x81
821 03:25:52.725335 hw id: 0x0000 - pwm id 0x01
822 03:25:52.725816 bl2_stage_init 0xc1
823 03:25:52.726203 bl2_stage_init 0x02
824 03:25:52.726547
825 03:25:52.731004 L0:00000000
826 03:25:52.731339 L1:20000703
827 03:25:52.731562 L2:00008067
828 03:25:52.731768 L3:14000000
829 03:25:52.736582 B2:00402000
830 03:25:52.737038 B1:e0f83180
831 03:25:52.737378
832 03:25:52.737705 TE: 58124
833 03:25:52.738023
834 03:25:52.742248 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 03:25:52.742712
836 03:25:52.742976 Board ID = 1
837 03:25:52.747737 Set A53 clk to 24M
838 03:25:52.748249 Set A73 clk to 24M
839 03:25:52.748846 Set clk81 to 24M
840 03:25:52.753510 A53 clk: 1200 MHz
841 03:25:52.754037 A73 clk: 1200 MHz
842 03:25:52.754502 CLK81: 166.6M
843 03:25:52.754963 smccc: 00012a92
844 03:25:52.758935 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 03:25:52.764593 board id: 1
846 03:25:52.770484 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 03:25:52.781050 fw parse done
848 03:25:52.787066 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 03:25:52.829664 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 03:25:52.840514 PIEI prepare done
851 03:25:52.841034 fastboot data load
852 03:25:52.841500 fastboot data verify
853 03:25:52.846206 verify result: 266
854 03:25:52.851782 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 03:25:52.852352 LPDDR4 probe
856 03:25:52.852814 ddr clk to 1584MHz
857 03:25:52.859765 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 03:25:52.897024
859 03:25:52.897596 dmc_version 0001
860 03:25:52.903694 Check phy result
861 03:25:52.909540 INFO : End of CA training
862 03:25:52.910057 INFO : End of initialization
863 03:25:52.915205 INFO : Training has run successfully!
864 03:25:52.915712 Check phy result
865 03:25:52.920765 INFO : End of initialization
866 03:25:52.921293 INFO : End of read enable training
867 03:25:52.924095 INFO : End of fine write leveling
868 03:25:52.929608 INFO : End of Write leveling coarse delay
869 03:25:52.935209 INFO : Training has run successfully!
870 03:25:52.935713 Check phy result
871 03:25:52.936240 INFO : End of initialization
872 03:25:52.940833 INFO : End of read dq deskew training
873 03:25:52.946429 INFO : End of MPR read delay center optimization
874 03:25:52.946938 INFO : End of write delay center optimization
875 03:25:52.952083 INFO : End of read delay center optimization
876 03:25:52.957617 INFO : End of max read latency training
877 03:25:52.958129 INFO : Training has run successfully!
878 03:25:52.963241 1D training succeed
879 03:25:52.969220 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 03:25:53.016920 Check phy result
881 03:25:53.017451 INFO : End of initialization
882 03:25:53.039383 INFO : End of 2D read delay Voltage center optimization
883 03:25:53.059415 INFO : End of 2D read delay Voltage center optimization
884 03:25:53.111275 INFO : End of 2D write delay Voltage center optimization
885 03:25:53.160567 INFO : End of 2D write delay Voltage center optimization
886 03:25:53.166104 INFO : Training has run successfully!
887 03:25:53.166692
888 03:25:53.167185 channel==0
889 03:25:53.171684 RxClkDly_Margin_A0==88 ps 9
890 03:25:53.172259 TxDqDly_Margin_A0==98 ps 10
891 03:25:53.177298 RxClkDly_Margin_A1==88 ps 9
892 03:25:53.177802 TxDqDly_Margin_A1==98 ps 10
893 03:25:53.178283 TrainedVREFDQ_A0==74
894 03:25:53.182913 TrainedVREFDQ_A1==74
895 03:25:53.183471 VrefDac_Margin_A0==24
896 03:25:53.183930 DeviceVref_Margin_A0==40
897 03:25:53.188490 VrefDac_Margin_A1==25
898 03:25:53.189042 DeviceVref_Margin_A1==40
899 03:25:53.189479
900 03:25:53.189909
901 03:25:53.194123 channel==1
902 03:25:53.194617 RxClkDly_Margin_A0==98 ps 10
903 03:25:53.195048 TxDqDly_Margin_A0==98 ps 10
904 03:25:53.197566 RxClkDly_Margin_A1==88 ps 9
905 03:25:53.203133 TxDqDly_Margin_A1==88 ps 9
906 03:25:53.203618 TrainedVREFDQ_A0==77
907 03:25:53.204098 TrainedVREFDQ_A1==77
908 03:25:53.208704 VrefDac_Margin_A0==22
909 03:25:53.209249 DeviceVref_Margin_A0==37
910 03:25:53.214627 VrefDac_Margin_A1==24
911 03:25:53.215247 DeviceVref_Margin_A1==37
912 03:25:53.215682
913 03:25:53.217862 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 03:25:53.218369
915 03:25:53.249181 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
916 03:25:53.249816 2D training succeed
917 03:25:53.254851 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 03:25:53.260503 auto size-- 65535DDR cs0 size: 2048MB
919 03:25:53.261074 DDR cs1 size: 2048MB
920 03:25:53.266017 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 03:25:53.266556 cs0 DataBus test pass
922 03:25:53.271667 cs1 DataBus test pass
923 03:25:53.272268 cs0 AddrBus test pass
924 03:25:53.272673 cs1 AddrBus test pass
925 03:25:53.277226
926 03:25:53.277766 100bdlr_step_size ps== 420
927 03:25:53.278179 result report
928 03:25:53.282874 boot times 0Enable ddr reg access
929 03:25:53.289073 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 03:25:53.302490 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 03:25:53.874354 0.0;M3 CHK:0;cm4_sp_mode 0
932 03:25:53.874802 MVN_1=0x00000000
933 03:25:53.879861 MVN_2=0x00000000
934 03:25:53.885610 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 03:25:53.885953 OPS=0x10
936 03:25:53.886213 ring efuse init
937 03:25:53.886464 chipver efuse init
938 03:25:53.893889 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 03:25:53.894368 [0.018961 Inits done]
940 03:25:53.894788 secure task start!
941 03:25:53.901434 high task start!
942 03:25:53.901903 low task start!
943 03:25:53.902319 run into bl31
944 03:25:53.908057 NOTICE: BL31: v1.3(release):4fc40b1
945 03:25:53.915847 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 03:25:53.916205 NOTICE: BL31: G12A normal boot!
947 03:25:53.941270 NOTICE: BL31: BL33 decompress pass
948 03:25:53.946894 ERROR: Error initializing runtime service opteed_fast
949 03:25:55.179917
950 03:25:55.180593
951 03:25:55.188301 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 03:25:55.188817
953 03:25:55.189242 Model: Libre Computer AML-A311D-CC Alta
954 03:25:55.396722 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 03:25:55.420195 DRAM: 2 GiB (effective 3.8 GiB)
956 03:25:55.563056 Core: 408 devices, 31 uclasses, devicetree: separate
957 03:25:55.568928 WDT: Not starting watchdog@f0d0
958 03:25:55.601141 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 03:25:55.613648 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 03:25:55.618623 ** Bad device specification mmc 0 **
961 03:25:55.628909 Card did not respond to voltage select! : -110
962 03:25:55.636613 ** Bad device specification mmc 0 **
963 03:25:55.637092 Couldn't find partition mmc 0
964 03:25:55.644941 Card did not respond to voltage select! : -110
965 03:25:55.650434 ** Bad device specification mmc 0 **
966 03:25:55.650925 Couldn't find partition mmc 0
967 03:25:55.655518 Error: could not access storage.
968 03:25:55.998925 Net: eth0: ethernet@ff3f0000
969 03:25:55.999338 starting USB...
970 03:25:56.250876 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 03:25:56.251499 Starting the controller
972 03:25:56.257841 USB XHCI 1.10
973 03:25:58.119603 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
974 03:25:58.120265 bl2_stage_init 0x01
975 03:25:58.120696 bl2_stage_init 0x81
976 03:25:58.125198 hw id: 0x0000 - pwm id 0x01
977 03:25:58.125683 bl2_stage_init 0xc1
978 03:25:58.126102 bl2_stage_init 0x02
979 03:25:58.126505
980 03:25:58.130784 L0:00000000
981 03:25:58.131263 L1:20000703
982 03:25:58.131675 L2:00008067
983 03:25:58.132118 L3:14000000
984 03:25:58.136351 B2:00402000
985 03:25:58.136827 B1:e0f83180
986 03:25:58.137238
987 03:25:58.137646 TE: 58124
988 03:25:58.138047
989 03:25:58.142049 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 03:25:58.142532
991 03:25:58.142946 Board ID = 1
992 03:25:58.147569 Set A53 clk to 24M
993 03:25:58.148081 Set A73 clk to 24M
994 03:25:58.148492 Set clk81 to 24M
995 03:25:58.153154 A53 clk: 1200 MHz
996 03:25:58.153630 A73 clk: 1200 MHz
997 03:25:58.154039 CLK81: 166.6M
998 03:25:58.154437 smccc: 00012a92
999 03:25:58.158767 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 03:25:58.164328 board id: 1
1001 03:25:58.170236 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 03:25:58.180894 fw parse done
1003 03:25:58.187559 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 03:25:58.229463 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 03:25:58.240380 PIEI prepare done
1006 03:25:58.240858 fastboot data load
1007 03:25:58.241250 fastboot data verify
1008 03:25:58.246307 verify result: 266
1009 03:25:58.251808 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 03:25:58.252324 LPDDR4 probe
1011 03:25:58.252719 ddr clk to 1584MHz
1012 03:25:58.259719 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 03:25:58.297170
1014 03:25:58.297711 dmc_version 0001
1015 03:25:58.303710 Check phy result
1016 03:25:58.309601 INFO : End of CA training
1017 03:25:58.310068 INFO : End of initialization
1018 03:25:58.315297 INFO : Training has run successfully!
1019 03:25:58.315772 Check phy result
1020 03:25:58.320808 INFO : End of initialization
1021 03:25:58.321273 INFO : End of read enable training
1022 03:25:58.324374 INFO : End of fine write leveling
1023 03:25:58.329765 INFO : End of Write leveling coarse delay
1024 03:25:58.336138 INFO : Training has run successfully!
1025 03:25:58.336853 Check phy result
1026 03:25:58.337360 INFO : End of initialization
1027 03:25:58.341103 INFO : End of read dq deskew training
1028 03:25:58.345140 INFO : End of MPR read delay center optimization
1029 03:25:58.350660 INFO : End of write delay center optimization
1030 03:25:58.355455 INFO : End of read delay center optimization
1031 03:25:58.355922 INFO : End of max read latency training
1032 03:25:58.361139 INFO : Training has run successfully!
1033 03:25:58.361605 1D training succeed
1034 03:25:58.369185 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 03:25:58.416726 Check phy result
1036 03:25:58.417346 INFO : End of initialization
1037 03:25:58.438341 INFO : End of 2D read delay Voltage center optimization
1038 03:25:58.458699 INFO : End of 2D read delay Voltage center optimization
1039 03:25:58.510752 INFO : End of 2D write delay Voltage center optimization
1040 03:25:58.560122 INFO : End of 2D write delay Voltage center optimization
1041 03:25:58.565925 INFO : Training has run successfully!
1042 03:25:58.566413
1043 03:25:58.566842 channel==0
1044 03:25:58.571228 RxClkDly_Margin_A0==88 ps 9
1045 03:25:58.571678 TxDqDly_Margin_A0==98 ps 10
1046 03:25:58.576631 RxClkDly_Margin_A1==88 ps 9
1047 03:25:58.577082 TxDqDly_Margin_A1==98 ps 10
1048 03:25:58.577497 TrainedVREFDQ_A0==74
1049 03:25:58.582249 TrainedVREFDQ_A1==74
1050 03:25:58.582703 VrefDac_Margin_A0==25
1051 03:25:58.583111 DeviceVref_Margin_A0==40
1052 03:25:58.587905 VrefDac_Margin_A1==25
1053 03:25:58.588380 DeviceVref_Margin_A1==40
1054 03:25:58.588789
1055 03:25:58.589189
1056 03:25:58.593437 channel==1
1057 03:25:58.593876 RxClkDly_Margin_A0==98 ps 10
1058 03:25:58.594282 TxDqDly_Margin_A0==88 ps 9
1059 03:25:58.599173 RxClkDly_Margin_A1==98 ps 10
1060 03:25:58.599616 TxDqDly_Margin_A1==88 ps 9
1061 03:25:58.604731 TrainedVREFDQ_A0==77
1062 03:25:58.605184 TrainedVREFDQ_A1==77
1063 03:25:58.605592 VrefDac_Margin_A0==22
1064 03:25:58.610393 DeviceVref_Margin_A0==37
1065 03:25:58.610838 VrefDac_Margin_A1==24
1066 03:25:58.615900 DeviceVref_Margin_A1==37
1067 03:25:58.616371
1068 03:25:58.616780 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 03:25:58.617180
1070 03:25:58.649632 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1071 03:25:58.650146 2D training succeed
1072 03:25:58.655195 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 03:25:58.660653 auto size-- 65535DDR cs0 size: 2048MB
1074 03:25:58.661105 DDR cs1 size: 2048MB
1075 03:25:58.666251 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 03:25:58.666694 cs0 DataBus test pass
1077 03:25:58.671851 cs1 DataBus test pass
1078 03:25:58.672332 cs0 AddrBus test pass
1079 03:25:58.672740 cs1 AddrBus test pass
1080 03:25:58.673136
1081 03:25:58.677465 100bdlr_step_size ps== 420
1082 03:25:58.677921 result report
1083 03:25:58.683085 boot times 0Enable ddr reg access
1084 03:25:58.688375 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 03:25:58.701922 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 03:25:59.275734 0.0;M3 CHK:0;cm4_sp_mode 0
1087 03:25:59.276398 MVN_1=0x00000000
1088 03:25:59.281135 MVN_2=0x00000000
1089 03:25:59.286834 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 03:25:59.287284 OPS=0x10
1091 03:25:59.287699 ring efuse init
1092 03:25:59.288180 chipver efuse init
1093 03:25:59.295151 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 03:25:59.295613 [0.018961 Inits done]
1095 03:25:59.296056 secure task start!
1096 03:25:59.302638 high task start!
1097 03:25:59.303092 low task start!
1098 03:25:59.303503 run into bl31
1099 03:25:59.309238 NOTICE: BL31: v1.3(release):4fc40b1
1100 03:25:59.317063 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 03:25:59.317523 NOTICE: BL31: G12A normal boot!
1102 03:25:59.342436 NOTICE: BL31: BL33 decompress pass
1103 03:25:59.348203 ERROR: Error initializing runtime service opteed_fast
1104 03:26:00.580928
1105 03:26:00.581349
1106 03:26:00.589370 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 03:26:00.589674
1108 03:26:00.589896 Model: Libre Computer AML-A311D-CC Alta
1109 03:26:00.797784 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 03:26:00.821163 DRAM: 2 GiB (effective 3.8 GiB)
1111 03:26:00.964188 Core: 408 devices, 31 uclasses, devicetree: separate
1112 03:26:00.970004 WDT: Not starting watchdog@f0d0
1113 03:26:01.002335 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 03:26:01.014695 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 03:26:01.019700 ** Bad device specification mmc 0 **
1116 03:26:01.030133 Card did not respond to voltage select! : -110
1117 03:26:01.037763 ** Bad device specification mmc 0 **
1118 03:26:01.038294 Couldn't find partition mmc 0
1119 03:26:01.046064 Card did not respond to voltage select! : -110
1120 03:26:01.051534 ** Bad device specification mmc 0 **
1121 03:26:01.052047 Couldn't find partition mmc 0
1122 03:26:01.056652 Error: could not access storage.
1123 03:26:01.399105 Net: eth0: ethernet@ff3f0000
1124 03:26:01.399709 starting USB...
1125 03:26:01.650962 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 03:26:01.651584 Starting the controller
1127 03:26:01.657843 USB XHCI 1.10
1128 03:26:03.211949 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 03:26:03.220200 scanning usb for storage devices... 0 Storage Device(s) found
1131 03:26:03.271819 Hit any key to stop autoboot: 1
1132 03:26:03.272751 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1133 03:26:03.273382 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1134 03:26:03.273852 Setting prompt string to ['=>']
1135 03:26:03.274316 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1136 03:26:03.287732 0
1137 03:26:03.288644 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 03:26:03.289126 Sending with 10 millisecond of delay
1140 03:26:04.423967 => setenv autoload no
1141 03:26:04.434828 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1142 03:26:04.439768 setenv autoload no
1143 03:26:04.440526 Sending with 10 millisecond of delay
1145 03:26:06.237343 => setenv initrd_high 0xffffffff
1146 03:26:06.248146 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1147 03:26:06.248998 setenv initrd_high 0xffffffff
1148 03:26:06.249703 Sending with 10 millisecond of delay
1150 03:26:07.866204 => setenv fdt_high 0xffffffff
1151 03:26:07.876989 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1152 03:26:07.877801 setenv fdt_high 0xffffffff
1153 03:26:07.878504 Sending with 10 millisecond of delay
1155 03:26:08.170370 => dhcp
1156 03:26:08.181125 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1157 03:26:08.181926 dhcp
1158 03:26:08.182363 Speed: 1000, full duplex
1159 03:26:08.182778 BOOTP broadcast 1
1160 03:26:08.191738 DHCP client bound to address 192.168.6.27 (10 ms)
1161 03:26:08.192498 Sending with 10 millisecond of delay
1163 03:26:09.869296 => setenv serverip 192.168.6.2
1164 03:26:09.880096 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1165 03:26:09.881008 setenv serverip 192.168.6.2
1166 03:26:09.881695 Sending with 10 millisecond of delay
1168 03:26:13.605286 => tftpboot 0x01080000 950284/tftp-deploy-2vebo3i3/kernel/uImage
1169 03:26:13.616129 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1170 03:26:13.616961 tftpboot 0x01080000 950284/tftp-deploy-2vebo3i3/kernel/uImage
1171 03:26:13.617406 Speed: 1000, full duplex
1172 03:26:13.617818 Using ethernet@ff3f0000 device
1173 03:26:13.619010 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1174 03:26:13.624515 Filename '950284/tftp-deploy-2vebo3i3/kernel/uImage'.
1175 03:26:13.628500 Load address: 0x1080000
1176 03:26:16.701111 Loading: *################################################## 36.1 MiB
1177 03:26:16.701793 11.7 MiB/s
1178 03:26:16.702269 done
1179 03:26:16.705691 Bytes transferred = 37878336 (241fa40 hex)
1180 03:26:16.706526 Sending with 10 millisecond of delay
1182 03:26:21.394081 => tftpboot 0x08000000 950284/tftp-deploy-2vebo3i3/ramdisk/ramdisk.cpio.gz.uboot
1183 03:26:21.404933 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1184 03:26:21.405843 tftpboot 0x08000000 950284/tftp-deploy-2vebo3i3/ramdisk/ramdisk.cpio.gz.uboot
1185 03:26:21.406331 Speed: 1000, full duplex
1186 03:26:21.406784 Using ethernet@ff3f0000 device
1187 03:26:21.408253 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1188 03:26:21.416239 Filename '950284/tftp-deploy-2vebo3i3/ramdisk/ramdisk.cpio.gz.uboot'.
1189 03:26:21.416757 Load address: 0x8000000
1190 03:26:27.972480 Loading: *###############T ################################### 23 MiB
1191 03:26:27.973141 3.5 MiB/s
1192 03:26:27.973611 done
1193 03:26:27.976791 Bytes transferred = 24147308 (170756c hex)
1194 03:26:27.977566 Sending with 10 millisecond of delay
1196 03:26:33.146797 => tftpboot 0x01070000 950284/tftp-deploy-2vebo3i3/dtb/meson-g12b-a311d-libretech-cc.dtb
1197 03:26:33.157582 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:53)
1198 03:26:33.158083 tftpboot 0x01070000 950284/tftp-deploy-2vebo3i3/dtb/meson-g12b-a311d-libretech-cc.dtb
1199 03:26:33.158350 Speed: 1000, full duplex
1200 03:26:33.158585 Using ethernet@ff3f0000 device
1201 03:26:33.162386 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1202 03:26:33.174166 Filename '950284/tftp-deploy-2vebo3i3/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1203 03:26:33.174586 Load address: 0x1070000
1204 03:26:33.190168 Loading: *################################################## 53.4 KiB
1205 03:26:33.190570 3.1 MiB/s
1206 03:26:33.190922 done
1207 03:26:33.196573 Bytes transferred = 54703 (d5af hex)
1208 03:26:33.197205 Sending with 10 millisecond of delay
1210 03:26:46.494608 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950284/extract-nfsrootfs-jzmrvmu7,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1211 03:26:46.505475 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:40)
1212 03:26:46.506426 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950284/extract-nfsrootfs-jzmrvmu7,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1213 03:26:46.507190 Sending with 10 millisecond of delay
1215 03:26:48.845938 => bootm 0x01080000 0x08000000 0x01070000
1216 03:26:48.856773 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1217 03:26:48.857346 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:37)
1218 03:26:48.858427 bootm 0x01080000 0x08000000 0x01070000
1219 03:26:48.858912 ## Booting kernel from Legacy Image at 01080000 ...
1220 03:26:48.861563 Image Name:
1221 03:26:48.867127 Image Type: AArch64 Linux Kernel Image (uncompressed)
1222 03:26:48.867605 Data Size: 37878272 Bytes = 36.1 MiB
1223 03:26:48.869244 Load Address: 01080000
1224 03:26:48.875862 Entry Point: 01080000
1225 03:26:49.034940 Verifying Checksum ... OK
1226 03:26:49.035480 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1227 03:26:49.040330 Image Name:
1228 03:26:49.045815 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1229 03:26:49.046294 Data Size: 24147244 Bytes = 23 MiB
1230 03:26:49.051334 Load Address: 00000000
1231 03:26:49.051799 Entry Point: 00000000
1232 03:26:49.156372 Verifying Checksum ... OK
1233 03:26:49.156853 ## Flattened Device Tree blob at 01070000
1234 03:26:49.161815 Booting using the fdt blob at 0x1070000
1235 03:26:49.162287 Working FDT set to 1070000
1236 03:26:49.166395 Loading Kernel Image
1237 03:26:49.316116 Loading Ramdisk to 7e8f8000, end 7ffff52c ... OK
1238 03:26:49.324337 Loading Device Tree to 000000007e8e7000, end 000000007e8f75ae ... OK
1239 03:26:49.324821 Working FDT set to 7e8e7000
1240 03:26:49.325275
1241 03:26:49.326209 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1242 03:26:49.326836 start: 2.4.4 auto-login-action (timeout 00:03:37) [common]
1243 03:26:49.327346 Setting prompt string to ['Linux version [0-9]']
1244 03:26:49.327840 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1245 03:26:49.328390 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1246 03:26:49.329492 Starting kernel ...
1247 03:26:49.329975
1248 03:26:49.375203 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1249 03:26:49.376171 start: 2.4.4.1 login-action (timeout 00:03:37) [common]
1250 03:26:49.376737 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1251 03:26:49.377241 Setting prompt string to []
1252 03:26:49.377770 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1253 03:26:49.378265 Using line separator: #'\n'#
1254 03:26:49.378719 No login prompt set.
1255 03:26:49.379194 Parsing kernel messages
1256 03:26:49.379631 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1257 03:26:49.380509 [login-action] Waiting for messages, (timeout 00:03:37)
1258 03:26:49.381010 Waiting using forced prompt support (timeout 00:01:48)
1259 03:26:49.391729 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j365933-arm64-clang-15-defconfig-v68p4) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP PREEMPT Thu Nov 7 00:05:25 UTC 2024
1260 03:26:49.392301 [ 0.000000] KASLR disabled due to lack of seed
1261 03:26:49.397337 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1262 03:26:49.402774 [ 0.000000] efi: UEFI not found.
1263 03:26:49.408310 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1264 03:26:49.419355 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1265 03:26:49.424742 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1266 03:26:49.435779 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1267 03:26:49.446868 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1268 03:26:49.457850 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1269 03:26:49.463366 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1270 03:26:49.470294 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1271 03:26:49.475803 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1272 03:26:49.481327 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1273 03:26:49.486846 [ 0.000000] Zone ranges:
1274 03:26:49.492379 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1275 03:26:49.492852 [ 0.000000] DMA32 empty
1276 03:26:49.497958 [ 0.000000] Normal empty
1277 03:26:49.503406 [ 0.000000] Movable zone start for each node
1278 03:26:49.503883 [ 0.000000] Early memory node ranges
1279 03:26:49.508968 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1280 03:26:49.520082 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1281 03:26:49.525486 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1282 03:26:49.530800 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1283 03:26:49.554099 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1284 03:26:49.559543 [ 0.000000] psci: probing for conduit method from DT.
1285 03:26:49.560055 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1286 03:26:49.568582 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1287 03:26:49.569089 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1288 03:26:49.574107 [ 0.000000] psci: SMC Calling Convention v1.1
1289 03:26:49.579638 [ 0.000000] percpu: Embedded 25 pages/cpu s61528 r8192 d32680 u102400
1290 03:26:49.585129 [ 0.000000] Detected VIPT I-cache on CPU0
1291 03:26:49.590645 [ 0.000000] CPU features: detected: ARM erratum 845719
1292 03:26:49.596199 [ 0.000000] alternatives: applying boot alternatives
1293 03:26:49.618283 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950284/extract-nfsrootfs-jzmrvmu7,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1294 03:26:49.623786 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1295 03:26:49.634827 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1296 03:26:49.635319 <6>[ 0.000000] Fallback order for Node 0: 0
1297 03:26:49.645861 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1298 03:26:49.646340 <6>[ 0.000000] Policy zone: DMA
1299 03:26:49.651376 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1300 03:26:49.662447 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1301 03:26:49.662922 <6>[ 0.000000] software IO TLB: area num 8.
1302 03:26:49.673435 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1303 03:26:49.720494 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1304 03:26:49.726112 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1305 03:26:49.729552 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1306 03:26:49.735095 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1307 03:26:49.740614 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1308 03:26:49.746098 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1309 03:26:49.757127 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1310 03:26:49.762673 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1311 03:26:49.768199 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1312 03:26:49.779245 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1313 03:26:49.784738 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1314 03:26:49.790259 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1315 03:26:49.795776 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1316 03:26:49.802211 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1317 03:26:49.814505 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1318 03:26:49.825559 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1319 03:26:49.831110 <6>[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1320 03:26:49.836623 <6>[ 0.008776] Console: colour dummy device 80x25
1321 03:26:49.847659 <6>[ 0.012940] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1322 03:26:49.853161 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1323 03:26:49.858693 <6>[ 0.028188] LSM: initializing lsm=capability
1324 03:26:49.864228 <6>[ 0.032729] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1325 03:26:49.869750 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1326 03:26:49.875240 <6>[ 0.052300] rcu: Hierarchical SRCU implementation.
1327 03:26:49.880787 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1328 03:26:49.891796 <6>[ 0.058885] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1329 03:26:49.900273 <6>[ 0.071496] EFI services will not be available.
1330 03:26:49.900737 <6>[ 0.075151] smp: Bringing up secondary CPUs ...
1331 03:26:49.912405 <6>[ 0.077137] Detected VIPT I-cache on CPU1
1332 03:26:49.917996 <6>[ 0.077255] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1333 03:26:49.923471 <6>[ 0.078592] CPU features: detected: Spectre-v2
1334 03:26:49.932483 <6>[ 0.078606] CPU features: detected: Spectre-v4
1335 03:26:49.932951 <6>[ 0.078610] CPU features: detected: Spectre-BHB
1336 03:26:49.938109 <6>[ 0.078615] CPU features: detected: ARM erratum 858921
1337 03:26:49.943573 <6>[ 0.078623] Detected VIPT I-cache on CPU2
1338 03:26:49.949142 <6>[ 0.078695] arch_timer: Enabling local workaround for ARM erratum 858921
1339 03:26:49.954604 <6>[ 0.078712] arch_timer: CPU2: Trapping CNTVCT access
1340 03:26:49.965610 <6>[ 0.078722] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1341 03:26:49.966077 <6>[ 0.083501] Detected VIPT I-cache on CPU3
1342 03:26:49.976660 <6>[ 0.083547] arch_timer: Enabling local workaround for ARM erratum 858921
1343 03:26:49.977126 <6>[ 0.083556] arch_timer: CPU3: Trapping CNTVCT access
1344 03:26:49.987700 <6>[ 0.083563] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1345 03:26:49.988219 <6>[ 0.087533] Detected VIPT I-cache on CPU4
1346 03:26:49.998718 <6>[ 0.087579] arch_timer: Enabling local workaround for ARM erratum 858921
1347 03:26:50.004313 <6>[ 0.087588] arch_timer: CPU4: Trapping CNTVCT access
1348 03:26:50.009817 <6>[ 0.087595] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1349 03:26:50.015281 <6>[ 0.091542] Detected VIPT I-cache on CPU5
1350 03:26:50.020957 <6>[ 0.091589] arch_timer: Enabling local workaround for ARM erratum 858921
1351 03:26:50.026458 <6>[ 0.091598] arch_timer: CPU5: Trapping CNTVCT access
1352 03:26:50.032006 <6>[ 0.091605] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1353 03:26:50.037383 <6>[ 0.091719] smp: Brought up 1 node, 6 CPUs
1354 03:26:50.042927 <6>[ 0.212951] SMP: Total of 6 processors activated.
1355 03:26:50.043396 <6>[ 0.217856] CPU: All CPU(s) started at EL2
1356 03:26:50.048416 <6>[ 0.222207] CPU features: detected: 32-bit EL0 Support
1357 03:26:50.053911 <6>[ 0.227518] CPU features: detected: 32-bit EL1 Support
1358 03:26:50.059459 <6>[ 0.232864] CPU features: detected: CRC32 instructions
1359 03:26:50.065031 <6>[ 0.238267] alternatives: applying system-wide alternatives
1360 03:26:50.081563 <6>[ 0.245696] Memory: 3564416K/4012396K available (17792K kernel code, 4926K rwdata, 11684K rodata, 2432K init, 743K bss, 180816K reserved, 262144K cma-reserved)
1361 03:26:50.088732 <6>[ 0.259763] devtmpfs: initialized
1362 03:26:50.094235 <6>[ 0.269167] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1363 03:26:50.105300 <6>[ 0.273524] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1364 03:26:50.110809 <6>[ 0.284603] 23312 pages in range for non-PLT usage
1365 03:26:50.116301 <6>[ 0.284613] 514832 pages in range for PLT usage
1366 03:26:50.121857 <6>[ 0.285893] pinctrl core: initialized pinctrl subsystem
1367 03:26:50.122321 <6>[ 0.297920] DMI not present or invalid.
1368 03:26:50.127382 <6>[ 0.301757] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1369 03:26:50.138410 <6>[ 0.306992] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1370 03:26:50.143951 <6>[ 0.313770] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1371 03:26:50.155033 <6>[ 0.321863] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1372 03:26:50.160510 <6>[ 0.329356] audit: initializing netlink subsys (disabled)
1373 03:26:50.166028 <5>[ 0.335094] audit: type=2000 audit(0.256:1): state=initialized audit_enabled=0 res=1
1374 03:26:50.171511 <6>[ 0.336510] thermal_sys: Registered thermal governor 'step_wise'
1375 03:26:50.177157 <6>[ 0.342860] thermal_sys: Registered thermal governor 'power_allocator'
1376 03:26:50.182561 <6>[ 0.349121] cpuidle: using governor menu
1377 03:26:50.188186 <6>[ 0.360094] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1378 03:26:50.193575 <6>[ 0.367027] ASID allocator initialised with 65536 entries
1379 03:26:50.200703 <6>[ 0.374447] Serial: AMBA PL011 UART driver
1380 03:26:50.210417 <6>[ 0.383976] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1381 03:26:50.225665 <6>[ 0.399444] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1382 03:26:50.236690 <6>[ 0.402095] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1383 03:26:50.242199 <6>[ 0.415205] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1384 03:26:50.247677 <6>[ 0.418482] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1385 03:26:50.258823 <6>[ 0.426888] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1386 03:26:50.264308 <6>[ 0.434531] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1387 03:26:50.275308 <6>[ 0.447973] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1388 03:26:50.280867 <6>[ 0.450351] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1389 03:26:50.286383 <6>[ 0.456833] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1390 03:26:50.291881 <6>[ 0.463810] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1391 03:26:50.302941 <6>[ 0.470279] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1392 03:26:50.308462 <6>[ 0.477264] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1393 03:26:50.313956 <6>[ 0.483734] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1394 03:26:50.319468 <6>[ 0.490719] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1395 03:26:50.325080 <6>[ 0.498768] ACPI: Interpreter disabled.
1396 03:26:50.330525 <6>[ 0.504002] iommu: Default domain type: Translated
1397 03:26:50.336077 <6>[ 0.506256] iommu: DMA domain TLB invalidation policy: strict mode
1398 03:26:50.341591 <5>[ 0.512984] SCSI subsystem initialized
1399 03:26:50.347204 <6>[ 0.516881] usbcore: registered new interface driver usbfs
1400 03:26:50.352598 <6>[ 0.522311] usbcore: registered new interface driver hub
1401 03:26:50.358165 <6>[ 0.527827] usbcore: registered new device driver usb
1402 03:26:50.363635 <6>[ 0.534025] pps_core: LinuxPPS API ver. 1 registered
1403 03:26:50.369195 <6>[ 0.538245] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1404 03:26:50.374703 <6>[ 0.547566] PTP clock support registered
1405 03:26:50.380235 <6>[ 0.551800] EDAC MC: Ver: 3.0.0
1406 03:26:50.385740 <6>[ 0.555458] scmi_core: SCMI protocol bus registered
1407 03:26:50.386220 <6>[ 0.561072] FPGA manager framework
1408 03:26:50.391247 <6>[ 0.563829] Advanced Linux Sound Architecture Driver Initialized.
1409 03:26:50.396748 <6>[ 0.570742] vgaarb: loaded
1410 03:26:50.402269 <6>[ 0.573333] clocksource: Switched to clocksource arch_sys_counter
1411 03:26:50.407831 <5>[ 0.579477] VFS: Disk quotas dquot_6.6.0
1412 03:26:50.413387 <6>[ 0.583459] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1413 03:26:50.419009 <6>[ 0.590674] pnp: PnP ACPI: disabled
1414 03:26:50.424385 <6>[ 0.599102] NET: Registered PF_INET protocol family
1415 03:26:50.429876 <6>[ 0.599497] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1416 03:26:50.440911 <6>[ 0.609478] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1417 03:26:50.446493 <6>[ 0.615659] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1418 03:26:50.457497 <6>[ 0.623557] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1419 03:26:50.463084 <6>[ 0.631796] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1420 03:26:50.468528 <6>[ 0.639598] TCP: Hash tables configured (established 32768 bind 32768)
1421 03:26:50.474099 <6>[ 0.646065] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1422 03:26:50.485051 <6>[ 0.652914] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1423 03:26:50.490577 <6>[ 0.660333] NET: Registered PF_UNIX/PF_LOCAL protocol family
1424 03:26:50.496387 <6>[ 0.666451] RPC: Registered named UNIX socket transport module.
1425 03:26:50.501700 <6>[ 0.672204] RPC: Registered udp transport module.
1426 03:26:50.507263 <6>[ 0.677108] RPC: Registered tcp transport module.
1427 03:26:50.512727 <6>[ 0.682023] RPC: Registered tcp-with-tls transport module.
1428 03:26:50.518251 <6>[ 0.687716] RPC: Registered tcp NFSv4.1 backchannel transport module.
1429 03:26:50.523763 <6>[ 0.694365] PCI: CLS 0 bytes, default 64
1430 03:26:50.524278 <6>[ 0.698689] Unpacking initramfs...
1431 03:26:50.529299 <6>[ 0.704865] kvm [1]: nv: 554 coarse grained trap handlers
1432 03:26:50.534793 <6>[ 0.708040] kvm [1]: IPA Size Limit: 40 bits
1433 03:26:50.540324 <6>[ 0.713820] kvm [1]: vgic interrupt IRQ9
1434 03:26:50.545856 <6>[ 0.716376] kvm [1]: Hyp nVHE mode initialized successfully
1435 03:26:50.551364 <5>[ 0.723784] Initialise system trusted keyrings
1436 03:26:50.556875 <6>[ 0.727037] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1437 03:26:50.562404 <6>[ 0.733663] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1438 03:26:50.567931 <5>[ 0.739760] NFS: Registering the id_resolver key type
1439 03:26:50.573435 <5>[ 0.744760] Key type id_resolver registered
1440 03:26:50.578945 <5>[ 0.749129] Key type id_legacy registered
1441 03:26:50.584562 <6>[ 0.753367] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1442 03:26:50.590061 <6>[ 0.760255] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1443 03:26:50.597405 <6>[ 0.768068] 9p: Installing v9fs 9p2000 file system support
1444 03:26:50.626831 <5>[ 0.806086] Key type asymmetric registered
1445 03:26:50.632327 <5>[ 0.806124] Asymmetric key parser 'x509' registered
1446 03:26:50.641406 <6>[ 0.809991] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1447 03:26:50.646894 <6>[ 0.817507] io scheduler mq-deadline registered
1448 03:26:50.652412 <6>[ 0.822243] io scheduler kyber registered
1449 03:26:50.652884 <6>[ 0.826515] io scheduler bfq registered
1450 03:26:50.660826 <6>[ 0.834995] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1451 03:26:50.676602 <6>[ 0.852093] ledtrig-cpu: registered to indicate activity on CPUs
1452 03:26:50.707540 <6>[ 0.881852] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1453 03:26:50.726524 <6>[ 0.894592] Serial: 8250/16550 driver, 4 ports<6>[ 0.899183] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1454 03:26:50.732077 <6>[ 0.908805] printk: legacy console [ttyAML0] enabled
1455 03:26:50.737616 <6>[ 0.908805] printk: legacy console [ttyAML0] enabled
1456 03:26:50.743128 <6>[ 0.913602] printk: legacy bootconsole [meson0] disabled
1457 03:26:50.748678 <6>[ 0.913602] printk: legacy bootconsole [meson0] disabled
1458 03:26:50.754262 <6>[ 0.926055] msm_serial: driver initialized
1459 03:26:50.759783 <6>[ 0.929535] SuperH (H)SCI(F) driver initialized
1460 03:26:50.760282 <6>[ 0.934066] STM32 USART driver initialized
1461 03:26:50.765322 <5>[ 0.940265] random: crng init done
1462 03:26:50.772072 <6>[ 0.945996] loop: module loaded
1463 03:26:50.772550 <6>[ 0.947175] megasas: 07.727.03.00-rc1
1464 03:26:50.777570 <6>[ 0.955783] tun: Universal TUN/TAP device driver, 1.6
1465 03:26:50.783134 <6>[ 0.956877] thunder_xcv, ver 1.0
1466 03:26:50.788704 <6>[ 0.958978] thunder_bgx, ver 1.0
1467 03:26:50.789177 <6>[ 0.962426] nicpf, ver 1.0
1468 03:26:50.794298 <6>[ 0.966792] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1469 03:26:50.799738 <6>[ 0.972808] hns3: Copyright (c) 2017 Huawei Corporation.
1470 03:26:50.805349 <6>[ 0.978398] hclge is initializing
1471 03:26:50.810806 <6>[ 0.981934] e1000: Intel(R) PRO/1000 Network Driver
1472 03:26:50.816412 <6>[ 0.987017] e1000: Copyright (c) 1999-2006 Intel Corporation.
1473 03:26:50.821924 <6>[ 0.993045] e1000e: Intel(R) PRO/1000 Network Driver
1474 03:26:50.827481 <6>[ 0.998198] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1475 03:26:50.833050 <6>[ 1.004382] igb: Intel(R) Gigabit Ethernet Network Driver
1476 03:26:50.838586 <6>[ 1.009983] igb: Copyright (c) 2007-2014 Intel Corporation.
1477 03:26:50.844220 <6>[ 1.015822] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1478 03:26:50.849687 <6>[ 1.022292] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1479 03:26:50.855298 <6>[ 1.028974] sky2: driver version 1.30
1480 03:26:50.860781 <6>[ 1.034067] VFIO - User Level meta-driver version: 0.3
1481 03:26:50.866352 <6>[ 1.041274] usbcore: registered new interface driver usb-storage
1482 03:26:50.872366 <6>[ 1.047441] i2c_dev: i2c /dev entries driver
1483 03:26:50.884277 <6>[ 1.058012] sdhci: Secure Digital Host Controller Interface driver
1484 03:26:50.884748 <6>[ 1.058814] sdhci: Copyright(c) Pierre Ossman
1485 03:26:50.893319 <6>[ 1.064419] Synopsys Designware Multimedia Card Interface Driver
1486 03:26:50.898760 <6>[ 1.070989] sdhci-pltfm: SDHCI platform and OF driver helper
1487 03:26:50.904340 <6>[ 1.078455] meson-sm: secure-monitor enabled
1488 03:26:50.909847 <6>[ 1.081154] usbcore: registered new interface driver usbhid
1489 03:26:50.913798 <6>[ 1.085874] usbhid: USB HID core driver
1490 03:26:50.920415 <6>[ 1.099682] NET: Registered PF_PACKET protocol family
1491 03:26:50.925943 <6>[ 1.099781] 9pnet: Installing 9P2000 support
1492 03:26:50.933300 <5>[ 1.103940] Key type dns_resolver registered
1493 03:26:50.938747 <6>[ 1.115696] registered taskstats version 1
1494 03:26:50.944355 <5>[ 1.115848] Loading compiled-in X.509 certificates
1495 03:26:50.947921 <6>[ 1.124955] Demotion targets for Node 0: null
1496 03:26:50.988412 <6>[ 1.167636] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1497 03:26:50.993923 <6>[ 1.167682] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1498 03:26:51.005015 <4>[ 1.177868] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1499 03:26:51.010581 <4>[ 1.180421] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1500 03:26:51.016225 <6>[ 1.188030] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1501 03:26:51.021693 <6>[ 1.197323] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1502 03:26:51.032794 <6>[ 1.200700] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1503 03:26:51.043799 <6>[ 1.208721] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1504 03:26:51.049373 <6>[ 1.218243] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1505 03:26:51.054942 <6>[ 1.224471] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1506 03:26:51.060489 <6>[ 1.230086] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1507 03:26:51.066007 <6>[ 1.237969] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1508 03:26:51.071567 <6>[ 1.245253] hub 1-0:1.0: USB hub found
1509 03:26:51.077159 <6>[ 1.248742] hub 1-0:1.0: 2 ports detected
1510 03:26:51.082670 <6>[ 1.254803] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1511 03:26:51.088339 <6>[ 1.261755] hub 2-0:1.0: USB hub found
1512 03:26:51.093392 <6>[ 1.265274] hub 2-0:1.0: 1 port detected
1513 03:26:51.113953 <6>[ 1.290647] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1514 03:26:51.130137 <6>[ 1.306049] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1515 03:26:51.165545 <6>[ 1.341078] Trying to probe devices needed for running init ...
1516 03:26:51.322448 <6>[ 1.497363] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1517 03:26:51.471013 <6>[ 1.644688] mmc0: new ultra high speed SDR104 SDXC card at address e624
1518 03:26:51.477178 <6>[ 1.646483] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1519 03:26:51.477669 <6>[ 1.652216] mmcblk0: p1
1520 03:26:51.513957 <6>[ 1.693078] hub 1-1:1.0: USB hub found
1521 03:26:51.519425 <6>[ 1.693378] hub 1-1:1.0: 4 ports detected
1522 03:26:51.523857 <6>[ 1.700753] Freeing initrd memory: 23580K
1523 03:26:51.582535 <6>[ 1.757478] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1524 03:26:51.626574 <6>[ 1.805723] hub 2-1:1.0: USB hub found
1525 03:26:51.632245 <6>[ 1.806545] hub 2-1:1.0: 4 ports detected
1526 03:27:03.434545 <6>[ 13.613394] clk: Disabling unused clocks
1527 03:27:03.439903 <6>[ 13.613568] PM: genpd: Disabling unused power domains
1528 03:27:03.446128 <6>[ 13.617253] ALSA device list:
1529 03:27:03.446579 <6>[ 13.620458] No soundcards found.
1530 03:27:03.451528 <6>[ 13.630361] Freeing unused kernel memory: 2432K
1531 03:27:03.457355 <6>[ 13.630442] Run /init as init process
1532 03:27:03.463845 Loading, please wait...
1533 03:27:03.501405 Starting systemd-udevd version 252.22-1~deb12u1
1534 03:27:03.936834 <6>[ 14.113745] mc: Linux media interface: v0.10
1535 03:27:03.986240 <6>[ 14.159645] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1536 03:27:03.991692 <6>[ 14.160900] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1537 03:27:03.997182 <6>[ 14.167350] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1538 03:27:04.002662 <6>[ 14.173555] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1539 03:27:04.008176 <6>[ 14.181200] meson-vrtc ff8000a8.rtc: registered as rtc0
1540 03:27:04.013679 <6>[ 14.181241] videodev: Linux video capture interface: v2.00
1541 03:27:04.024833 <4>[ 14.181628] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1542 03:27:04.030343 <6>[ 14.184738] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1543 03:27:04.035890 <6>[ 14.184758] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1544 03:27:04.041458 <6>[ 14.184764] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1545 03:27:04.052542 <6>[ 14.184770] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1546 03:27:04.058070 <6>[ 14.184775] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1547 03:27:04.063812 <6>[ 14.184781] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1548 03:27:04.069260 <6>[ 14.184786] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1549 03:27:04.080312 <6>[ 14.185297] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1550 03:27:04.085974 <6>[ 14.209500] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1551 03:27:04.091521 <6>[ 14.261771] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1552 03:27:04.097502 <6>[ 14.267699] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1553 03:27:04.103077 <6>[ 14.282015] panfrost ffe40000.gpu: clock rate = 24000000
1554 03:27:04.114107 <3>[ 14.282127] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1555 03:27:04.125149 <3>[ 14.294294] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1556 03:27:04.130726 <6>[ 14.299239] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1557 03:27:04.136300 <6>[ 14.306901] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1558 03:27:04.152917 <6>[ 14.315284] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1559 03:27:04.158486 <6>[ 14.327391] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1560 03:27:04.169531 <4>[ 14.330389] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1561 03:27:04.173595 <6>[ 14.332433] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1562 03:27:04.187955 <6>[ 14.367131] Registered IR keymap rc-empty
1563 03:27:04.199046 <6>[ 14.368116] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1564 03:27:04.210078 <6>[ 14.380953] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1565 03:27:04.217839 <6>[ 14.385581] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1566 03:27:04.223390 <6>[ 14.399724] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1567 03:27:04.234442 <6>[ 14.403582] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1568 03:27:04.240102 <3>[ 14.411766] meson-drm ff900000.vpu: DSI transceiver device is disabled
1569 03:27:04.251118 <6>[ 14.418304] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1570 03:27:04.256682 <6>[ 14.418914] usbcore: registered new device driver onboard-usb-dev
1571 03:27:04.262215 <6>[ 14.419024] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1572 03:27:04.266236 <6>[ 14.436920] rc rc0: sw decoder init
1573 03:27:04.438374 <6>[ 14.442409] meson-ir ff808000.ir: receiver initialized
1574 03:27:04.449274 <6>[ 14.446777] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1575 03:27:04.454787 <6>[ 14.598108] Console: switching to colour frame buffer device 128x48
1576 03:27:04.460812 <6>[ 14.630103] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1577 03:27:04.472776 <6>[ 14.643551] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1578 03:27:04.697878 <6>[ 14.877078] hub 1-1:1.0: USB hub found
1579 03:27:04.703303 <6>[ 14.877406] hub 1-1:1.0: 4 ports detected
1580 03:27:04.708737 <6>[ 14.882108] usb 1-1: USB disconnect, device number 2
1581 03:27:05.078321 <6>[ 15.253362] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1582 03:27:05.273915 <6>[ 15.453154] hub 1-1:1.0: USB hub found
1583 03:27:05.279644 <6>[ 15.453477] hub 1-1:1.0: 4 ports detected
1584 03:27:05.286429 Begin: Loading essential drivers ... done.
1585 03:27:05.292025 Begin: Running /scripts/init-premount ... done.
1586 03:27:05.297522 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1587 03:27:05.311241 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1588 03:27:05.311773 Device /sys/class/net/end0 found
1589 03:27:05.312293 done.
1590 03:27:05.323222 Begin: Waiting up to 180 secs for any network device to become available ... done.
1591 03:27:05.389200 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.559739] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1592 03:27:05.389784
1593 03:27:05.471270 <6>[ 15.645042] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1594 03:27:05.485232 <6>[ 15.649439] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=32)
1595 03:27:05.490794 <6>[ 15.665342] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1596 03:27:05.496333 <6>[ 15.667533] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1597 03:27:05.506534 <6>[ 15.674903] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1598 03:27:05.726160 <6>[ 15.901009] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1599 03:27:06.266207 <4>[ 16.445342] rc rc0: two consecutive events of type space
1600 03:27:07.508025 IP-Config: no response after 2 secs - giving up
1601 03:27:07.573898 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1602 03:27:08.461622 <6>[ 18.634683] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1603 03:27:09.784302 IP-Config: end0 guessed broadcast address 192.168.6.255
1604 03:27:09.789799 IP-Config: end0 complete (dhcp from 192.168.6.1):
1605 03:27:09.795307 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1606 03:27:09.806448 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1607 03:27:09.806897 rootserver: 192.168.6.1 rootpath:
1608 03:27:09.809965 filename :
1609 03:27:09.916445 done.
1610 03:27:09.926607 Begin: Running /scripts/nfs-bottom ... done.
1611 03:27:09.942627 Begin: Running /scripts/init-bottom ... done.
1612 03:27:10.278066 <30>[ 20.452573] systemd[1]: System time before build time, advancing clock.
1613 03:27:10.327598 <6>[ 20.506588] NET: Registered PF_INET6 protocol family
1614 03:27:10.333125 <6>[ 20.508471] Segment Routing with IPv6
1615 03:27:10.338417 <6>[ 20.510109] In-situ OAM (IOAM) with IPv6
1616 03:27:10.413725 <30>[ 20.564918] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1617 03:27:10.419049 <30>[ 20.592309] systemd[1]: Detected architecture arm64.
1618 03:27:10.419485
1619 03:27:10.427588 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1620 03:27:10.428224
1621 03:27:10.435737 <30>[ 20.611027] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1622 03:27:11.128889 <30>[ 21.303894] systemd[1]: Queued start job for default target graphical.target.
1623 03:27:11.158078 <30>[ 21.331719] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1624 03:27:11.165706 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1625 03:27:11.176591 <30>[ 21.350340] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1626 03:27:11.185255 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1627 03:27:11.196741 <30>[ 21.370411] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1628 03:27:11.205830 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1629 03:27:11.216731 <30>[ 21.390097] systemd[1]: Created slice user.slice - User and Session Slice.
1630 03:27:11.223188 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1631 03:27:11.234350 <30>[ 21.405608] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1632 03:27:11.245792 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1633 03:27:11.256867 <30>[ 21.425550] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1634 03:27:11.263424 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1635 03:27:11.285711 <30>[ 21.445502] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1636 03:27:11.291184 <30>[ 21.459581] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1637 03:27:11.298863 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1638 03:27:11.309877 <30>[ 21.481424] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1639 03:27:11.315958 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1640 03:27:11.331722 <30>[ 21.505455] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1641 03:27:11.345462 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1642 03:27:11.351069 <30>[ 21.525470] systemd[1]: Reached target paths.target - Path Units.
1643 03:27:11.359449 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1644 03:27:11.365067 <30>[ 21.541442] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1645 03:27:11.376717 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1646 03:27:11.382338 <30>[ 21.557425] systemd[1]: Reached target slices.target - Slice Units.
1647 03:27:11.390408 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1648 03:27:11.395955 <30>[ 21.573436] systemd[1]: Reached target swap.target - Swaps.
1649 03:27:11.403803 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1650 03:27:11.415755 <30>[ 21.589456] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1651 03:27:11.424625 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1652 03:27:11.439898 <30>[ 21.613623] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1653 03:27:11.449161 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1654 03:27:11.462479 <30>[ 21.636221] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1655 03:27:11.471267 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1656 03:27:11.484631 <30>[ 21.658375] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1657 03:27:11.494068 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1658 03:27:11.508181 <30>[ 21.681771] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1659 03:27:11.515454 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1660 03:27:11.528756 <30>[ 21.702443] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1661 03:27:11.537927 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1662 03:27:11.549804 <30>[ 21.723454] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1663 03:27:11.555357 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1664 03:27:11.568208 <30>[ 21.741681] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1665 03:27:11.576550 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1666 03:27:11.616120 <30>[ 21.789537] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1667 03:27:11.622564 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1668 03:27:11.634322 <30>[ 21.808080] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1669 03:27:11.641833 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1670 03:27:11.653997 <30>[ 21.827832] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1671 03:27:11.662516 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1672 03:27:11.679490 <30>[ 21.846081] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1673 03:27:11.724401 <30>[ 21.898129] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1674 03:27:11.732964 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1675 03:27:11.748769 <30>[ 21.922490] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1676 03:27:11.756693 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1677 03:27:11.808340 <30>[ 21.982043] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1678 03:27:11.815927 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1679 03:27:11.834708 <6>[ 22.008462] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1680 03:27:11.845801 <30>[ 22.009023] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1681 03:27:11.850729 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1682 03:27:11.865021 <30>[ 22.038725] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1683 03:27:11.873285 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1684 03:27:11.888840 <30>[ 22.062568] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1685 03:27:11.896135 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1686 03:27:11.909349 <6>[ 22.088609] fuse: init (API version 7.41)
1687 03:27:11.920381 <30>[ 22.089288] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1688 03:27:11.924334 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1689 03:27:11.972302 <30>[ 22.146041] systemd[1]: Starting systemd-journald.service - Journal Service...
1690 03:27:11.978694 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1691 03:27:11.999459 <30>[ 22.172685] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1692 03:27:12.007087 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1693 03:27:12.021319 <30>[ 22.195079] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1694 03:27:12.030785 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1695 03:27:12.046034 <30>[ 22.219781] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1696 03:27:12.054885 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1697 03:27:12.069779 <30>[ 22.243520] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1698 03:27:12.077814 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1699 03:27:12.095150 <30>[ 22.268895] systemd[1]: Started systemd-journald.service - Journal Service.
1700 03:27:12.101961 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1701 03:27:12.113640 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1702 03:27:12.128460 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1703 03:27:12.140349 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1704 03:27:12.160714 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1705 03:27:12.176903 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1706 03:27:12.192893 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1707 03:27:12.204765 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1708 03:27:12.220921 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1709 03:27:12.236742 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1710 03:27:12.252773 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1711 03:27:12.264705 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1712 03:27:12.280608 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1713 03:27:12.296692 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1714 03:27:12.309023 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1715 03:27:12.371395 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1716 03:27:12.385852 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1717 03:27:12.397976 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1718 03:27:12.409729 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1719 03:27:12.429744 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1720 03:27:12.437071 <46>[ 22.609449] systemd-journald[233]: Received client request to flush runtime journal.
1721 03:27:12.454420 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1722 03:27:12.472362 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1723 03:27:12.480833 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1724 03:27:12.500528 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1725 03:27:12.521090 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1726 03:27:12.533042 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1727 03:27:12.582332 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1728 03:27:12.619424 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1729 03:27:12.704368 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1730 03:27:12.724800 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1731 03:27:12.740516 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1732 03:27:12.755399 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1733 03:27:12.803445 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1734 03:27:12.814161 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1735 03:27:12.979021 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1736 03:27:13.011845 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1737 03:27:13.046720 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1738 03:27:13.089315 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1739 03:27:13.128308 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1740 03:27:13.142772 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1741 03:27:13.182007 <5>[ 23.355817] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1742 03:27:13.217464 <5>[ 23.391194] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1743 03:27:13.222977 <5>[ 23.392062] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1744 03:27:13.234251 [[<4>[ 23.399972] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1745 03:27:13.234820 <6>[ 23.408313] cfg80211: failed to load regulatory.db
1746 03:27:13.244921 0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1747 03:27:13.308499 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1748 03:27:13.315082 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1749 03:27:13.332358 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1750 03:27:13.339312 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1751 03:27:13.356537 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1752 03:27:13.371755 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1753 03:27:13.398866 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1754 03:27:13.415481 <46>[ 23.576625] systemd-journald[233]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1755 03:27:13.431795 <46>[ 23.593130] systemd-journald[233]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1756 03:27:13.446192 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1757 03:27:13.459997 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1758 03:27:13.473955 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1759 03:27:13.486524 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1760 03:27:13.498822 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1761 03:27:13.561031 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1762 03:27:13.577539 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1763 03:27:13.583294 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1764 03:27:13.658825 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1765 03:27:13.708163 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1766 03:27:13.735600 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1767 03:27:13.745999 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1768 03:27:13.792827 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1769 03:27:13.806233 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1770 03:27:13.819378 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1771 03:27:13.835918 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1772 03:27:13.848161 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1773 03:27:13.891485 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1774 03:27:13.909111 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1775 03:27:13.932963 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1776 03:27:13.940158 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1777 03:27:13.952981 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1778 03:27:13.964408 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1779 03:27:13.985048 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1780 03:27:13.992551 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1781 03:27:14.003463 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1782 03:27:14.056464 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1783 03:27:14.113503 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1784 03:27:14.200498
1785 03:27:14.201044 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1786 03:27:14.201465
1787 03:27:14.207622 debian-bookworm-arm64 login: root (automatic login)
1788 03:27:14.208136
1789 03:27:14.366365 Linux debian-bookworm-arm64 6.12.0-rc6 #1 SMP PREEMPT Thu Nov 7 00:05:25 UTC 2024 aarch64
1790 03:27:14.366950
1791 03:27:14.371961 The programs included with the Debian GNU/Linux system are free software;
1792 03:27:14.377505 the exact distribution terms for each program are described in the
1793 03:27:14.383070 individual files in /usr/share/doc/*/copyright.
1794 03:27:14.383577
1795 03:27:14.388633 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1796 03:27:14.391742 permitted by applicable law.
1797 03:27:15.052877 Matched prompt #10: / #
1799 03:27:15.054402 Setting prompt string to ['/ #']
1800 03:27:15.054964 end: 2.4.4.1 login-action (duration 00:00:26) [common]
1802 03:27:15.056404 end: 2.4.4 auto-login-action (duration 00:00:26) [common]
1803 03:27:15.056967 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
1804 03:27:15.057416 Setting prompt string to ['/ #']
1805 03:27:15.057835 Forcing a shell prompt, looking for ['/ #']
1807 03:27:15.108791 / #
1808 03:27:15.109391 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1809 03:27:15.109852 Waiting using forced prompt support (timeout 00:02:30)
1810 03:27:15.115428
1811 03:27:15.116258 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1812 03:27:15.116838 start: 2.4.6 export-device-env (timeout 00:03:11) [common]
1813 03:27:15.117317 Sending with 10 millisecond of delay
1815 03:27:20.104330 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/950284/extract-nfsrootfs-jzmrvmu7'
1816 03:27:20.115278 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/950284/extract-nfsrootfs-jzmrvmu7'
1817 03:27:20.116086 Sending with 10 millisecond of delay
1819 03:27:22.214166 / # export NFS_SERVER_IP='192.168.6.2'
1820 03:27:22.225112 export NFS_SERVER_IP='192.168.6.2'
1821 03:27:22.225993 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1822 03:27:22.226585 end: 2.4 uboot-commands (duration 00:01:56) [common]
1823 03:27:22.227141 end: 2 uboot-action (duration 00:01:56) [common]
1824 03:27:22.227705 start: 3 lava-test-retry (timeout 00:06:46) [common]
1825 03:27:22.228319 start: 3.1 lava-test-shell (timeout 00:06:46) [common]
1826 03:27:22.228790 Using namespace: common
1828 03:27:22.329946 / # #
1829 03:27:22.330839 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1830 03:27:22.335846 #
1831 03:27:22.336672 Using /lava-950284
1833 03:27:22.437821 / # export SHELL=/bin/bash
1834 03:27:22.443581 export SHELL=/bin/bash
1836 03:27:22.545076 / # . /lava-950284/environment
1837 03:27:22.549098 . /lava-950284/environment
1839 03:27:22.655019 / # /lava-950284/bin/lava-test-runner /lava-950284/0
1840 03:27:22.655927 Test shell timeout: 10s (minimum of the action and connection timeout)
1841 03:27:22.660075 /lava-950284/bin/lava-test-runner /lava-950284/0
1842 03:27:22.843363 + export TESTRUN_ID=0_timesync-off
1843 03:27:22.851266 + TESTRUN_ID=0_timesync-off
1844 03:27:22.851748 + cd /lava-950284/0/tests/0_timesync-off
1845 03:27:22.852227 ++ cat uuid
1846 03:27:22.861970 + UUID=950284_1.6.2.4.1
1847 03:27:22.862452 + set +x
1848 03:27:22.870542 <LAVA_SIGNAL_STARTRUN 0_timesync-off 950284_1.6.2.4.1>
1849 03:27:22.871019 + systemctl stop systemd-timesyncd
1850 03:27:22.871727 Received signal: <STARTRUN> 0_timesync-off 950284_1.6.2.4.1
1851 03:27:22.872207 Starting test lava.0_timesync-off (950284_1.6.2.4.1)
1852 03:27:22.872735 Skipping test definition patterns.
1853 03:27:22.930104 + set +x
1854 03:27:22.930705 <LAVA_SIGNAL_ENDRUN 0_timesync-off 950284_1.6.2.4.1>
1855 03:27:22.931398 Received signal: <ENDRUN> 0_timesync-off 950284_1.6.2.4.1
1856 03:27:22.931912 Ending use of test pattern.
1857 03:27:22.932405 Ending test lava.0_timesync-off (950284_1.6.2.4.1), duration 0.06
1859 03:27:23.003027 + export TESTRUN_ID=1_kselftest-alsa
1860 03:27:23.011409 + TESTRUN_ID=1_kselftest-alsa
1861 03:27:23.011926 + cd /lava-950284/0/tests/1_kselftest-alsa
1862 03:27:23.012404 ++ cat uuid
1863 03:27:23.019683 + UUID=950284_1.6.2.4.5
1864 03:27:23.020275 + set +x
1865 03:27:23.025339 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 950284_1.6.2.4.5>
1866 03:27:23.025844 + cd ./automated/linux/kselftest/
1867 03:27:23.026520 Received signal: <STARTRUN> 1_kselftest-alsa 950284_1.6.2.4.5
1868 03:27:23.026981 Starting test lava.1_kselftest-alsa (950284_1.6.2.4.5)
1869 03:27:23.027496 Skipping test definition patterns.
1870 03:27:23.054287 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1871 03:27:23.091364 INFO: install_deps skipped
1872 03:27:23.226813 --2024-11-07 03:27:23-- http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/clang-15/kselftest.tar.xz
1873 03:27:23.251532 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1874 03:27:23.392313 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1875 03:27:23.537023 HTTP request sent, awaiting response... 200 OK
1876 03:27:23.537640 Length: 4438652 (4.2M) [application/octet-stream]
1877 03:27:23.542448 Saving to: 'kselftest_armhf.tar.gz'
1878 03:27:23.542926
1879 03:27:24.665229
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 180KB/s
kselftest_armhf.tar 5%[> ] 218.67K 393KB/s
kselftest_armhf.tar 20%[===> ] 893.67K 1.05MB/s
kselftest_armhf.tar 82%[===============> ] 3.51M 3.15MB/s
kselftest_armhf.tar 100%[===================>] 4.23M 3.77MB/s in 1.1s
1880 03:27:24.665859
1881 03:27:24.736729 2024-11-07 03:27:24 (3.77 MB/s) - 'kselftest_armhf.tar.gz' saved [4438652/4438652]
1882 03:27:24.737346
1883 03:27:33.007460 skiplist:
1884 03:27:33.008133 ========================================
1885 03:27:33.013068 ========================================
1886 03:27:33.051421 alsa:mixer-test
1887 03:27:33.051968 alsa:pcm-test
1888 03:27:33.052422 alsa:test-pcmtest-driver
1889 03:27:33.055539 alsa:utimer-test
1890 03:27:33.067415 ============== Tests to run ===============
1891 03:27:33.067943 alsa:mixer-test
1892 03:27:33.072929 alsa:pcm-test
1893 03:27:33.073410 alsa:test-pcmtest-driver
1894 03:27:33.073830 alsa:utimer-test
1895 03:27:33.080285 ===========End Tests to run ===============
1896 03:27:33.080775 shardfile-alsa pass
1897 03:27:33.192344 <12>[ 43.369315] kselftest: Running tests in alsa
1898 03:27:33.199644 TAP version 13
1899 03:27:33.209678 1..4
1900 03:27:33.232496 # timeout set to 45
1901 03:27:33.232987 # selftests: alsa: mixer-test
1902 03:27:33.393848 # TAP version 13
1903 03:27:33.394442 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1904 03:27:33.399337 # 1..427
1905 03:27:33.399812 # ok 1 get_value.LCALTA.60
1906 03:27:33.400274 # # LCALTA.60 TDMOUT_A SRC SEL
1907 03:27:33.404866 # ok 2 name.LCALTA.60
1908 03:27:33.405330 # ok 3 write_default.LCALTA.60
1909 03:27:33.408363 # ok 4 write_valid.LCALTA.60
1910 03:27:33.413864 # ok 5 write_invalid.LCALTA.60
1911 03:27:33.414346 # ok 6 event_missing.LCALTA.60
1912 03:27:33.419468 # ok 7 event_spurious.LCALTA.60
1913 03:27:33.419945 # ok 8 get_value.LCALTA.59
1914 03:27:33.425056 # # LCALTA.59 TDMOUT_B SRC SEL
1915 03:27:33.425530 # ok 9 name.LCALTA.59
1916 03:27:33.430612 # ok 10 write_default.LCALTA.59
1917 03:27:33.431081 # ok 11 write_valid.LCALTA.59
1918 03:27:33.436094 # ok 12 write_invalid.LCALTA.59
1919 03:27:33.436561 # ok 13 event_missing.LCALTA.59
1920 03:27:33.441676 # ok 14 event_spurious.LCALTA.59
1921 03:27:33.442138 # ok 15 get_value.LCALTA.58
1922 03:27:33.447278 # # LCALTA.58 TDMOUT_C SRC SEL
1923 03:27:33.447742 # ok 16 name.LCALTA.58
1924 03:27:33.448189 # ok 17 write_default.LCALTA.58
1925 03:27:33.452810 # ok 18 write_valid.LCALTA.58
1926 03:27:33.453279 # ok 19 write_invalid.LCALTA.58
1927 03:27:33.458284 # ok 20 event_missing.LCALTA.58
1928 03:27:33.458751 # ok 21 event_spurious.LCALTA.58
1929 03:27:33.463810 # ok 22 get_value.LCALTA.57
1930 03:27:33.464300 # # LCALTA.57 TDMIN_A SRC SEL
1931 03:27:33.469452 # ok 23 name.LCALTA.57
1932 03:27:33.469919 # ok 24 write_default.LCALTA.57
1933 03:27:33.474988 # ok 25 write_valid.LCALTA.57
1934 03:27:33.475454 # ok 26 write_invalid.LCALTA.57
1935 03:27:33.480521 # ok 27 event_missing.LCALTA.57
1936 03:27:33.480994 # ok 28 event_spurious.LCALTA.57
1937 03:27:33.486040 # ok 29 get_value.LCALTA.56
1938 03:27:33.486508 # # LCALTA.56 TDMIN_B SRC SEL
1939 03:27:33.491713 # ok 30 name.LCALTA.56
1940 03:27:33.492217 # ok 31 write_default.LCALTA.56
1941 03:27:33.508112 # ok 32 write_va<3>[ 43.672060] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1942 03:27:33.508653 lid.LCALTA.56
1943 03:27:33.509068 # ok 33 write_invalid.LCALTA.56
1944 03:27:33.513682 # ok 34 event_missing.LCALTA.56
1945 03:27:33.514158 # ok 35 event_spurious.LCALTA.56
1946 03:27:33.519213 # ok 36 get_value.LCALTA.55
1947 03:27:33.519688 # # LCALTA.55 TDMIN_C SRC SEL
1948 03:27:33.524752 # ok 37 name.LCALTA.55
1949 03:27:33.525227 # ok 38 write_default.LCALTA.55
1950 03:27:33.530300 # ok 39 write_valid.LCALTA.55
1951 03:27:33.530772 # ok 40 write_invalid.LCALTA.55
1952 03:27:33.535861 # ok 41 event_missing.LCALTA.55
1953 03:27:33.536372 # ok 42 event_spurious.LCALTA.55
1954 03:27:33.541406 # ok 43 get_value.LCALTA.54
1955 03:27:33.541887 # # LCALTA.54 ACODEC Left DAC Sel
1956 03:27:33.546919 # ok 44 name.LCALTA.54
1957 03:27:33.547386 # ok 45 write_default.LCALTA.54
1958 03:27:33.552447 # ok 46 write_valid.LCALTA.54
1959 03:27:33.552912 # ok 47 write_invalid.LCALTA.54
1960 03:27:33.558006 # ok 48 event_missing.LCALTA.54
1961 03:27:33.558479 # ok 49 event_spurious.LCALTA.54
1962 03:27:33.563590 # ok 50 get_value.LCALTA.53
1963 03:27:33.564101 # # LCALTA.53 ACODEC Right DAC Sel
1964 03:27:33.569140 # ok 51 name.LCALTA.53
1965 03:27:33.569623 # ok 52 write_default.LCALTA.53
1966 03:27:33.574682 # ok 53 write_valid.LCALTA.53
1967 03:27:33.575156 # ok 54 write_invalid.LCALTA.53
1968 03:27:33.580269 # ok 55 event_missing.LCALTA.53
1969 03:27:33.580734 # ok 56 event_spurious.LCALTA.53
1970 03:27:33.585770 # ok 57 get_value.LCALTA.52
1971 03:27:33.586235 # # LCALTA.52 TOACODEC OUT EN Switch
1972 03:27:33.591307 # ok 58 name.LCALTA.52
1973 03:27:33.591770 # ok 59 write_default.LCALTA.52
1974 03:27:33.596866 # ok 60 write_valid.LCALTA.52
1975 03:27:33.597330 # ok 61 write_invalid.LCALTA.52
1976 03:27:33.602407 # ok 62 event_missing.LCALTA.52
1977 03:27:33.602866 # ok 63 event_spurious.LCALTA.52
1978 03:27:33.607949 # ok 64 get_value.LCALTA.51
1979 03:27:33.608448 # # LCALTA.51 TOACODEC SRC
1980 03:27:33.608856 # ok 65 name.LCALTA.51
1981 03:27:33.613498 # ok 66 write_default.LCALTA.51
1982 03:27:33.613958 # ok 67 write_valid.LCALTA.51
1983 03:27:33.619039 # ok 68 write_invalid.LCALTA.51
1984 03:27:33.619498 # ok 69 event_missing.LCALTA.51
1985 03:27:33.624586 # ok 70 event_spurious.LCALTA.51
1986 03:27:33.625051 # ok 71 get_value.LCALTA.50
1987 03:27:33.630140 # # LCALTA.50 TOHDMITX SPDIF SRC
1988 03:27:33.630607 # ok 72 name.LCALTA.50
1989 03:27:33.635688 # ok 73 write_default.LCALTA.50
1990 03:27:33.636178 # ok 74 write_valid.LCALTA.50
1991 03:27:33.641235 # ok 75 write_invalid.LCALTA.50
1992 03:27:33.641694 # ok 76 event_missing.LCALTA.50
1993 03:27:33.646781 # ok 77 event_spurious.LCALTA.50
1994 03:27:33.647247 # ok 78 get_value.LCALTA.49
1995 03:27:33.652331 # # LCALTA.49 TOHDMITX Switch
1996 03:27:33.652803 # ok 79 name.LCALTA.49
1997 03:27:33.657895 # ok 80 write_default.LCALTA.49
1998 03:27:33.658356 # ok 81 write_valid.LCALTA.49
1999 03:27:33.663406 # ok 82 write_invalid.LCALTA.49
2000 03:27:33.663870 # ok 83 event_missing.LCALTA.49
2001 03:27:33.668971 # ok 84 event_spurious.LCALTA.49
2002 03:27:33.669435 # ok 85 get_value.LCALTA.48
2003 03:27:33.674520 # # LCALTA.48 TOHDMITX I2S SRC
2004 03:27:33.674983 # ok 86 name.LCALTA.48
2005 03:27:33.680075 # ok 87 write_default.LCALTA.48
2006 03:27:33.680537 # ok 88 write_valid.LCALTA.48
2007 03:27:33.685599 # ok 89 write_invalid.LCALTA.48
2008 03:27:33.686061 # ok 90 event_missing.LCALTA.48
2009 03:27:33.691146 # ok 91 event_spurious.LCALTA.48
2010 03:27:33.691616 # ok 92 get_value.LCALTA.47
2011 03:27:33.696700 # # LCALTA.47 TODDR_C SRC SEL
2012 03:27:33.697163 # ok 93 name.LCALTA.47
2013 03:27:33.697569 # ok 94 write_default.LCALTA.47
2014 03:27:33.702260 # ok 95 write_valid.LCALTA.47
2015 03:27:33.702720 # ok 96 write_invalid.LCALTA.47
2016 03:27:33.707776 # ok 97 event_missing.LCALTA.47
2017 03:27:33.713339 # ok 98 event_spurious.LCALTA.47
2018 03:27:33.713801 # ok 99 get_value.LCALTA.46
2019 03:27:33.714206 # # LCALTA.46 TODDR_B SRC SEL
2020 03:27:33.718866 # ok 100 name.LCALTA.46
2021 03:27:33.719323 # ok 101 write_default.LCALTA.46
2022 03:27:33.724415 # ok 102 write_valid.LCALTA.46
2023 03:27:33.724876 # ok 103 write_invalid.LCALTA.46
2024 03:27:33.729972 # ok 104 event_missing.LCALTA.46
2025 03:27:33.735505 # ok 105 event_spurious.LCALTA.46
2026 03:27:33.735966 # ok 106 get_value.LCALTA.45
2027 03:27:33.736408 # # LCALTA.45 TODDR_A SRC SEL
2028 03:27:33.741058 # ok 107 name.LCALTA.45
2029 03:27:33.741523 # ok 108 write_default.LCALTA.45
2030 03:27:33.746618 # ok 109 write_valid.LCALTA.45
2031 03:27:33.747085 # ok 110 write_invalid.LCALTA.45
2032 03:27:33.752242 # ok 111 event_missing.LCALTA.45
2033 03:27:33.752711 # ok 112 event_spurious.LCALTA.45
2034 03:27:33.757738 # ok 113 get_value.LCALTA.44
2035 03:27:33.758214 # # LCALTA.44 FRDDR_C SINK 3 SEL
2036 03:27:33.763279 # ok 114 name.LCALTA.44
2037 03:27:33.763750 # ok 115 write_default.LCALTA.44
2038 03:27:33.768816 # ok 116 write_valid.LCALTA.44
2039 03:27:33.769291 # ok 117 write_invalid.LCALTA.44
2040 03:27:33.774367 # ok 118 event_missing.LCALTA.44
2041 03:27:33.779892 # ok 119 event_spurious.LCALTA.44
2042 03:27:33.780387 # ok 120 get_value.LCALTA.43
2043 03:27:33.785446 # # LCALTA.43 FRDDR_C SINK 2 SEL
2044 03:27:33.785914 # ok 121 name.LCALTA.43
2045 03:27:33.786320 # ok 122 write_default.LCALTA.43
2046 03:27:33.791000 # ok 123 write_valid.LCALTA.43
2047 03:27:33.791465 # ok 124 write_invalid.LCALTA.43
2048 03:27:33.796509 # ok 125 event_missing.LCALTA.43
2049 03:27:33.802154 # ok 126 event_spurious.LCALTA.43
2050 03:27:33.802626 # ok 127 get_value.LCALTA.42
2051 03:27:33.807610 # # LCALTA.42 FRDDR_C SINK 1 SEL
2052 03:27:33.808128 # ok 128 name.LCALTA.42
2053 03:27:33.808538 # ok 129 write_default.LCALTA.42
2054 03:27:33.813209 # ok 130 write_valid.LCALTA.42
2055 03:27:33.818730 # ok 131 write_invalid.LCALTA.42
2056 03:27:33.819195 # ok 132 event_missing.LCALTA.42
2057 03:27:33.824291 # ok 133 event_spurious.LCALTA.42
2058 03:27:33.824762 # ok 134 get_value.LCALTA.41
2059 03:27:33.829813 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
2060 03:27:33.830276 # ok 135 name.LCALTA.41
2061 03:27:33.835362 # ok 136 write_default.LCALTA.41
2062 03:27:33.835823 # ok 137 write_valid.LCALTA.41
2063 03:27:33.840917 # ok 138 write_invalid.LCALTA.41
2064 03:27:33.841384 # ok 139 event_missing.LCALTA.41
2065 03:27:33.846450 # ok 140 event_spurious.LCALTA.41
2066 03:27:33.846912 # ok 141 get_value.LCALTA.40
2067 03:27:33.852019 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
2068 03:27:33.852486 # ok 142 name.LCALTA.40
2069 03:27:33.857540 # ok 143 write_default.LCALTA.40
2070 03:27:33.858006 # ok 144 write_valid.LCALTA.40
2071 03:27:33.863156 # ok 145 write_invalid.LCALTA.40
2072 03:27:33.863618 # ok 146 event_missing.LCALTA.40
2073 03:27:33.868632 # ok 147 event_spurious.LCALTA.40
2074 03:27:33.869088 # ok 148 get_value.LCALTA.39
2075 03:27:33.874199 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
2076 03:27:33.874660 # ok 149 name.LCALTA.39
2077 03:27:33.879710 # ok 150 write_default.LCALTA.39
2078 03:27:33.880200 # ok 151 write_valid.LCALTA.39
2079 03:27:33.885277 # ok 152 write_invalid.LCALTA.39
2080 03:27:33.885735 # ok 153 event_missing.LCALTA.39
2081 03:27:33.890808 # ok 154 event_spurious.LCALTA.39
2082 03:27:33.891287 # ok 155 get_value.LCALTA.38
2083 03:27:33.896364 # # LCALTA.38 FRDDR_B SINK 3 SEL
2084 03:27:33.896828 # ok 156 name.LCALTA.38
2085 03:27:33.901888 # ok 157 write_default.LCALTA.38
2086 03:27:33.902348 # ok 158 write_valid.LCALTA.38
2087 03:27:33.907440 # ok 159 write_invalid.LCALTA.38
2088 03:27:33.907900 # ok 160 event_missing.LCALTA.38
2089 03:27:33.913003 # ok 161 event_spurious.LCALTA.38
2090 03:27:33.913469 # ok 162 get_value.LCALTA.37
2091 03:27:33.918545 # # LCALTA.37 FRDDR_B SINK 2 SEL
2092 03:27:33.919007 # ok 163 name.LCALTA.37
2093 03:27:33.924224 # ok 164 write_default.LCALTA.37
2094 03:27:33.924698 # ok 165 write_valid.LCALTA.37
2095 03:27:33.929652 # ok 166 write_invalid.LCALTA.37
2096 03:27:33.930124 # ok 167 event_missing.LCALTA.37
2097 03:27:33.935242 # ok 168 event_spurious.LCALTA.37
2098 03:27:33.935703 # ok 169 get_value.LCALTA.36
2099 03:27:33.940747 # # LCALTA.36 FRDDR_B SINK 1 SEL
2100 03:27:33.941214 # ok 170 name.LCALTA.36
2101 03:27:33.946309 # ok 171 write_default.LCALTA.36
2102 03:27:33.946772 # ok 172 write_valid.LCALTA.36
2103 03:27:33.951825 # ok 173 write_invalid.LCALTA.36
2104 03:27:33.952314 # ok 174 event_missing.LCALTA.36
2105 03:27:33.957409 # ok 175 event_spurious.LCALTA.36
2106 03:27:33.957883 # ok 176 get_value.LCALTA.35
2107 03:27:33.962921 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
2108 03:27:33.963381 # ok 177 name.LCALTA.35
2109 03:27:33.968482 # ok 178 write_default.LCALTA.35
2110 03:27:33.974019 # ok 179 write_valid.LCALTA.35
2111 03:27:33.974481 # ok 180 write_invalid.LCALTA.35
2112 03:27:33.979562 # ok 181 event_missing.LCALTA.35
2113 03:27:33.980059 # ok 182 event_spurious.LCALTA.35
2114 03:27:33.985164 # ok 183 get_value.LCALTA.34
2115 03:27:33.985627 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
2116 03:27:33.990660 # ok 184 name.LCALTA.34
2117 03:27:33.991128 # ok 185 write_default.LCALTA.34
2118 03:27:33.996245 # ok 186 write_valid.LCALTA.34
2119 03:27:33.996717 # ok 187 write_invalid.LCALTA.34
2120 03:27:34.001827 # ok 188 event_missing.LCALTA.34
2121 03:27:34.002322 # ok 189 event_spurious.LCALTA.34
2122 03:27:34.007317 # ok 190 get_value.LCALTA.33
2123 03:27:34.007780 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
2124 03:27:34.012861 # ok 191 name.LCALTA.33
2125 03:27:34.013339 # ok 192 write_default.LCALTA.33
2126 03:27:34.018428 # ok 193 write_valid.LCALTA.33
2127 03:27:34.018907 # ok 194 write_invalid.LCALTA.33
2128 03:27:34.023964 # ok 195 event_missing.LCALTA.33
2129 03:27:34.024478 # ok 196 event_spurious.LCALTA.33
2130 03:27:34.029505 # ok 197 get_value.LCALTA.32
2131 03:27:34.029971 # # LCALTA.32 FRDDR_A SINK 3 SEL
2132 03:27:34.035048 # ok 198 name.LCALTA.32
2133 03:27:34.035507 # ok 199 write_default.LCALTA.32
2134 03:27:34.040569 # ok 200 write_valid.LCALTA.32
2135 03:27:34.041036 # ok 201 write_invalid.LCALTA.32
2136 03:27:34.046169 # ok 202 event_missing.LCALTA.32
2137 03:27:34.046626 # ok 203 event_spurious.LCALTA.32
2138 03:27:34.051655 # ok 204 get_value.LCALTA.31
2139 03:27:34.052138 # # LCALTA.31 FRDDR_A SINK 2 SEL
2140 03:27:34.057203 # ok 205 name.LCALTA.31
2141 03:27:34.057662 # ok 206 write_default.LCALTA.31
2142 03:27:34.062769 # ok 207 write_valid.LCALTA.31
2143 03:27:34.063234 # ok 208 write_invalid.LCALTA.31
2144 03:27:34.068357 # ok 209 event_missing.LCALTA.31
2145 03:27:34.068836 # ok 210 event_spurious.LCALTA.31
2146 03:27:34.073863 # ok 211 get_value.LCALTA.30
2147 03:27:34.074319 # # LCALTA.30 FRDDR_A SINK 1 SEL
2148 03:27:34.079411 # ok 212 name.LCALTA.30
2149 03:27:34.079868 # ok 213 write_default.LCALTA.30
2150 03:27:34.084964 # ok 214 write_valid.LCALTA.30
2151 03:27:34.085423 # ok 215 write_invalid.LCALTA.30
2152 03:27:34.090505 # ok 216 event_missing.LCALTA.30
2153 03:27:34.090969 # ok 217 event_spurious.LCALTA.30
2154 03:27:34.096112 # ok 218 get_value.LCALTA.29
2155 03:27:34.101543 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2156 03:27:34.101887 # ok 219 name.LCALTA.29
2157 03:27:34.102109 # ok 220 write_default.LCALTA.29
2158 03:27:34.107167 # ok 221 write_valid.LCALTA.29
2159 03:27:34.107663 # ok 222 write_invalid.LCALTA.29
2160 03:27:34.112688 # ok 223 event_missing.LCALTA.29
2161 03:27:34.118218 # ok 224 event_spurious.LCALTA.29
2162 03:27:34.118746 # ok 225 get_value.LCALTA.28
2163 03:27:34.123768 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2164 03:27:34.124186 # ok 226 name.LCALTA.28
2165 03:27:34.129290 # ok 227 write_default.LCALTA.28
2166 03:27:34.129770 # ok 228 write_valid.LCALTA.28
2167 03:27:34.134861 # ok 229 write_invalid.LCALTA.28
2168 03:27:34.135371 # ok 230 event_missing.LCALTA.28
2169 03:27:34.140385 # ok 231 event_spurious.LCALTA.28
2170 03:27:34.140758 # ok 232 get_value.LCALTA.27
2171 03:27:34.145943 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2172 03:27:34.146437 # ok 233 name.LCALTA.27
2173 03:27:34.151470 # ok 234 write_default.LCALTA.27
2174 03:27:34.151952 # ok 235 write_valid.LCALTA.27
2175 03:27:34.157031 # ok 236 write_invalid.LCALTA.27
2176 03:27:34.157380 # ok 237 event_missing.LCALTA.27
2177 03:27:34.162535 # ok 238 event_spurious.LCALTA.27
2178 03:27:34.162973 # ok 239 get_value.LCALTA.26
2179 03:27:34.168181 # # LCALTA.26 ELD
2180 03:27:34.168640 # ok 240 name.LCALTA.26
2181 03:27:34.168892 # # ELD is not writeable
2182 03:27:34.173651 # ok 241 # SKIP write_default.LCALTA.26
2183 03:27:34.174082 # # ELD is not writeable
2184 03:27:34.179228 # ok 242 # SKIP write_valid.LCALTA.26
2185 03:27:34.179738 # # ELD is not writeable
2186 03:27:34.184766 # ok 243 # SKIP write_invalid.LCALTA.26
2187 03:27:34.190288 # ok 244 event_missing.LCALTA.26
2188 03:27:34.190635 # ok 245 event_spurious.LCALTA.26
2189 03:27:34.195850 # ok 246 get_value.LCALTA.25
2190 03:27:34.196358 # # LCALTA.25 IEC958 Playback Default
2191 03:27:34.201368 # ok 247 name.LCALTA.25
2192 03:27:34.201726 # ok 248 write_default.LCALTA.25
2193 03:27:34.206931 # ok 249 # SKIP write_valid.LCALTA.25
2194 03:27:34.207399 # ok 250 # SKIP write_invalid.LCALTA.25
2195 03:27:34.212454 # ok 251 event_missing.LCALTA.25
2196 03:27:34.212786 # ok 252 event_spurious.LCALTA.25
2197 03:27:34.218017 # ok 253 get_value.LCALTA.24
2198 03:27:34.218469 # # LCALTA.24 IEC958 Playback Mask
2199 03:27:34.223538 # ok 254 name.LCALTA.24
2200 03:27:34.229092 # # IEC958 Playback Mask is not writeable
2201 03:27:34.229388 # ok 255 # SKIP write_default.LCALTA.24
2202 03:27:34.234604 # # IEC958 Playback Mask is not writeable
2203 03:27:34.234892 # ok 256 # SKIP write_valid.LCALTA.24
2204 03:27:34.240150 # # IEC958 Playback Mask is not writeable
2205 03:27:34.245676 # ok 257 # SKIP write_invalid.LCALTA.24
2206 03:27:34.245958 # ok 258 event_missing.LCALTA.24
2207 03:27:34.251223 # ok 259 event_spurious.LCALTA.24
2208 03:27:34.251500 # ok 260 get_value.LCALTA.23
2209 03:27:34.256769 # # LCALTA.23 Playback Channel Map
2210 03:27:34.257049 # ok 261 name.LCALTA.23
2211 03:27:34.262326 # # Playback Channel Map is not writeable
2212 03:27:34.267866 # ok 262 # SKIP write_default.LCALTA.23
2213 03:27:34.268166 # # Playback Channel Map is not writeable
2214 03:27:34.273416 # ok 263 # SKIP write_valid.LCALTA.23
2215 03:27:34.278957 # # Playback Channel Map is not writeable
2216 03:27:34.279239 # ok 264 # SKIP write_invalid.LCALTA.23
2217 03:27:34.284506 # ok 265 event_missing.LCALTA.23
2218 03:27:34.284890 # ok 266 event_spurious.LCALTA.23
2219 03:27:34.290097 # ok 267 get_value.LCALTA.22
2220 03:27:34.290375 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2221 03:27:34.295618 # ok 268 name.LCALTA.22
2222 03:27:34.295905 # ok 269 write_default.LCALTA.22
2223 03:27:34.301150 # ok 270 write_valid.LCALTA.22
2224 03:27:34.301442 # ok 271 write_invalid.LCALTA.22
2225 03:27:34.306702 # ok 272 event_missing.LCALTA.22
2226 03:27:34.306985 # ok 273 event_spurious.LCALTA.22
2227 03:27:34.312243 # ok 274 get_value.LCALTA.21
2228 03:27:34.312524 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2229 03:27:34.317778 # ok 275 name.LCALTA.21
2230 03:27:34.318061 # ok 276 write_default.LCALTA.21
2231 03:27:34.323324 # ok 277 write_valid.LCALTA.21
2232 03:27:34.323611 # ok 278 write_invalid.LCALTA.21
2233 03:27:34.328881 # ok 279 event_missing.LCALTA.21
2234 03:27:34.334420 # ok 280 event_spurious.LCALTA.21
2235 03:27:34.334802 # ok 281 get_value.LCALTA.20
2236 03:27:34.339976 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2237 03:27:34.340279 # ok 282 name.LCALTA.20
2238 03:27:34.340489 # ok 283 write_default.LCALTA.20
2239 03:27:34.345510 # ok 284 write_valid.LCALTA.20
2240 03:27:34.351105 # ok 285 write_invalid.LCALTA.20
2241 03:27:34.351484 # ok 286 event_missing.LCALTA.20
2242 03:27:34.356610 # ok 287 event_spurious.LCALTA.20
2243 03:27:34.356988 # ok 288 get_value.LCALTA.19
2244 03:27:34.362158 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2245 03:27:34.362438 # ok 289 name.LCALTA.19
2246 03:27:34.367704 # ok 290 write_default.LCALTA.19
2247 03:27:34.368002 # ok 291 write_valid.LCALTA.19
2248 03:27:34.377860 # ok 292 write_invalid.LCALTA.19
2249 03:27:34.378207 # ok 293 event_missing.LCALTA.19
2250 03:27:34.378820 # ok 294 event_spurious.LCALTA.19
2251 03:27:34.379199 # ok 295 get_value.LCALTA.18
2252 03:27:34.384372 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2253 03:27:34.384777 # ok 296 name.LCALTA.18
2254 03:27:34.389887 # ok 297 write_default.LCALTA.18
2255 03:27:34.390171 # ok 298 write_valid.LCALTA.18
2256 03:27:34.395465 # ok 299 write_invalid.LCALTA.18
2257 03:27:34.395899 # ok 300 event_missing.LCALTA.18
2258 03:27:34.401005 # ok 301 event_spurious.LCALTA.18
2259 03:27:34.401420 # ok 302 get_value.LCALTA.17
2260 03:27:34.406539 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2261 03:27:34.406819 # ok 303 name.LCALTA.17
2262 03:27:34.412177 # ok 304 write_default.LCALTA.17
2263 03:27:34.412630 # ok 305 write_valid.LCALTA.17
2264 03:27:34.417673 # ok 306 write_invalid.LCALTA.17
2265 03:27:34.418216 # ok 307 event_missing.LCALTA.17
2266 03:27:34.423184 # ok 308 event_spurious.LCALTA.17
2267 03:27:34.423469 # ok 309 get_value.LCALTA.16
2268 03:27:34.428733 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2269 03:27:34.429139 # ok 310 name.LCALTA.16
2270 03:27:34.434265 # ok 311 write_default.LCALTA.16
2271 03:27:34.434539 # ok 312 write_valid.LCALTA.16
2272 03:27:34.439819 # ok 313 write_invalid.LCALTA.16
2273 03:27:34.445509 # ok 314 event_missing.LCALTA.16
2274 03:27:34.446209 # ok 315 event_spurious.LCALTA.16
2275 03:27:34.451043 # ok 316 get_value.LCALTA.15
2276 03:27:34.451509 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2277 03:27:34.456582 # ok 317 name.LCALTA.15
2278 03:27:34.457045 # ok 318 write_default.LCALTA.15
2279 03:27:34.462136 # ok 319 write_valid.LCALTA.15
2280 03:27:34.462597 # ok 320 write_invalid.LCALTA.15
2281 03:27:34.467682 # ok 321 event_missing.LCALTA.15
2282 03:27:34.468181 # ok 322 event_spurious.LCALTA.15
2283 03:27:34.473244 # ok 323 get_value.LCALTA.14
2284 03:27:34.473705 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2285 03:27:34.478753 # ok 324 name.LCALTA.14
2286 03:27:34.479215 # ok 325 write_default.LCALTA.14
2287 03:27:34.484300 # ok 326 write_valid.LCALTA.14
2288 03:27:34.484763 # ok 327 write_invalid.LCALTA.14
2289 03:27:34.489859 # ok 328 event_missing.LCALTA.14
2290 03:27:34.490327 # ok 329 event_spurious.LCALTA.14
2291 03:27:34.495427 # ok 330 get_value.LCALTA.13
2292 03:27:34.495907 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2293 03:27:34.500985 # ok 331 name.LCALTA.13
2294 03:27:34.501466 # ok 332 write_default.LCALTA.13
2295 03:27:34.506510 # ok 333 write_valid.LCALTA.13
2296 03:27:34.506985 # ok 334 write_invalid.LCALTA.13
2297 03:27:34.512086 # ok 335 event_missing.LCALTA.13
2298 03:27:34.512558 # ok 336 event_spurious.LCALTA.13
2299 03:27:34.517622 # ok 337 get_value.LCALTA.12
2300 03:27:34.518086 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2301 03:27:34.523163 # ok 338 name.LCALTA.12
2302 03:27:34.523639 # ok 339 write_default.LCALTA.12
2303 03:27:34.528717 # ok 340 write_valid.LCALTA.12
2304 03:27:34.529191 # ok 341 write_invalid.LCALTA.12
2305 03:27:34.534298 # ok 342 event_missing.LCALTA.12
2306 03:27:34.539817 # ok 343 event_spurious.LCALTA.12
2307 03:27:34.540336 # ok 344 get_value.LCALTA.11
2308 03:27:34.545356 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2309 03:27:34.545838 # ok 345 name.LCALTA.11
2310 03:27:34.546251 # ok 346 write_default.LCALTA.11
2311 03:27:34.550866 # ok 347 write_valid.LCALTA.11
2312 03:27:34.556416 # ok 348 write_invalid.LCALTA.11
2313 03:27:34.556888 # ok 349 event_missing.LCALTA.11
2314 03:27:34.562007 # ok 350 event_spurious.LCALTA.11
2315 03:27:34.562485 # ok 351 get_value.LCALTA.10
2316 03:27:34.567562 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2317 03:27:34.568095 # ok 352 name.LCALTA.10
2318 03:27:34.573066 # ok 353 write_default.LCALTA.10
2319 03:27:34.573532 # ok 354 write_valid.LCALTA.10
2320 03:27:34.578686 # ok 355 write_invalid.LCALTA.10
2321 03:27:34.579217 # ok 356 event_missing.LCALTA.10
2322 03:27:34.584246 # ok 357 event_spurious.LCALTA.10
2323 03:27:34.584733 # ok 358 get_value.LCALTA.9
2324 03:27:34.589703 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2325 03:27:34.590166 # ok 359 name.LCALTA.9
2326 03:27:34.595307 # ok 360 write_default.LCALTA.9
2327 03:27:34.595780 # ok 361 write_valid.LCALTA.9
2328 03:27:34.600817 # ok 362 write_invalid.LCALTA.9
2329 03:27:34.601274 # ok 363 event_missing.LCALTA.9
2330 03:27:34.606350 # ok 364 event_spurious.LCALTA.9
2331 03:27:34.606806 # ok 365 get_value.LCALTA.8
2332 03:27:34.611902 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2333 03:27:34.612387 # ok 366 name.LCALTA.8
2334 03:27:34.617449 # ok 367 write_default.LCALTA.8
2335 03:27:34.617911 # ok 368 write_valid.LCALTA.8
2336 03:27:34.622988 # ok 369 write_invalid.LCALTA.8
2337 03:27:34.623447 # ok 370 event_missing.LCALTA.8
2338 03:27:34.628542 # ok 371 event_spurious.LCALTA.8
2339 03:27:34.629006 # ok 372 get_value.LCALTA.7
2340 03:27:34.634076 # # LCALTA.7 ACODEC Unmute Ramp Switch
2341 03:27:34.634534 # ok 373 name.LCALTA.7
2342 03:27:34.639635 # ok 374 write_default.LCALTA.7
2343 03:27:34.640121 # ok 375 write_valid.LCALTA.7
2344 03:27:34.645168 # ok 376 write_invalid.LCALTA.7
2345 03:27:34.645641 # ok 377 event_missing.LCALTA.7
2346 03:27:34.650737 # ok 378 event_spurious.LCALTA.7
2347 03:27:34.651200 # ok 379 get_value.LCALTA.6
2348 03:27:34.657455 # # LCALTA.6 ACODEC Mute Ramp Switch
2349 03:27:34.657917 # ok 380 name.LCALTA.6
2350 03:27:34.661807 # ok 381 write_default.LCALTA.6
2351 03:27:34.662267 # ok 382 write_valid.LCALTA.6
2352 03:27:34.667338 # ok 383 write_invalid.LCALTA.6
2353 03:27:34.667795 # ok 384 event_missing.LCALTA.6
2354 03:27:34.672884 # ok 385 event_spurious.LCALTA.6
2355 03:27:34.673343 # ok 386 get_value.LCALTA.5
2356 03:27:34.678410 # # LCALTA.5 ACODEC Volume Ramp Switch
2357 03:27:34.678865 # ok 387 name.LCALTA.5
2358 03:27:34.683955 # ok 388 write_default.LCALTA.5
2359 03:27:34.684437 # ok 389 write_valid.LCALTA.5
2360 03:27:34.689531 # ok 390 write_invalid.LCALTA.5
2361 03:27:34.689988 # ok 391 event_missing.LCALTA.5
2362 03:27:34.695130 # ok 392 event_spurious.LCALTA.5
2363 03:27:34.695637 # ok 393 get_value.LCALTA.4
2364 03:27:34.700635 # # LCALTA.4 ACODEC Ramp Rate
2365 03:27:34.701108 # ok 394 name.LCALTA.4
2366 03:27:34.701528 # ok 395 write_default.LCALTA.4
2367 03:27:34.706177 # ok 396 write_valid.LCALTA.4
2368 03:27:34.706642 # ok 397 write_invalid.LCALTA.4
2369 03:27:34.711722 # ok 398 event_missing.LCALTA.4
2370 03:27:34.717271 # ok 399 event_spurious.LCALTA.4
2371 03:27:34.717738 # ok 400 get_value.LCALTA.3
2372 03:27:34.722819 # # LCALTA.3 ACODEC Playback Volume
2373 03:27:34.723288 # ok 401 name.LCALTA.3
2374 03:27:34.723698 # ok 402 write_default.LCALTA.3
2375 03:27:34.728369 # ok 403 write_valid.LCALTA.3
2376 03:27:34.728835 # ok 404 write_invalid.LCALTA.3
2377 03:27:34.733916 # ok 405 event_missing.LCALTA.3
2378 03:27:34.734379 # ok 406 event_spurious.LCALTA.3
2379 03:27:34.739452 # ok 407 get_value.LCALTA.2
2380 03:27:34.745002 # # LCALTA.2 ACODEC Playback Switch
2381 03:27:34.745466 # ok 408 name.LCALTA.2
2382 03:27:34.745892 # ok 409 write_default.LCALTA.2
2383 03:27:34.750591 # ok 410 write_valid.LCALTA.2
2384 03:27:34.751073 # ok 411 write_invalid.LCALTA.2
2385 03:27:34.756143 # ok 412 event_missing.LCALTA.2
2386 03:27:34.756612 # ok 413 event_spurious.LCALTA.2
2387 03:27:34.761692 # ok 414 get_value.LCALTA.1
2388 03:27:34.767184 # # LCALTA.1 ACODEC Playback Channel Mode
2389 03:27:34.767667 # ok 415 name.LCALTA.1
2390 03:27:34.768106 # ok 416 write_default.LCALTA.1
2391 03:27:34.772733 # ok 417 write_valid.LCALTA.1
2392 03:27:34.773191 # ok 418 write_invalid.LCALTA.1
2393 03:27:34.778265 # ok 419 event_missing.LCALTA.1
2394 03:27:34.783806 # ok 420 event_spurious.LCALTA.1
2395 03:27:34.784291 # ok 421 get_value.LCALTA.0
2396 03:27:34.789352 # # LCALTA.0 TOACODEC Lane Select
2397 03:27:34.789797 # ok 422 name.LCALTA.0
2398 03:27:34.790185 # ok 423 write_default.LCALTA.0
2399 03:27:34.794896 # ok 424 write_valid.LCALTA.0
2400 03:27:34.795389 # ok 425 write_invalid.LCALTA.0
2401 03:27:34.800493 # ok 426 event_missing.LCALTA.0
2402 03:27:34.800951 # ok 427 event_spurious.LCALTA.0
2403 03:27:34.806012 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2404 03:27:34.811546 ok 1 selftests: alsa: mixer-test
2405 03:27:34.812020 # timeout set to 45
2406 03:27:34.817098 # selftests: alsa: pcm-test
2407 03:27:34.817555 # TAP version 13
2408 03:27:34.822685 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2409 03:27:34.823164 # # LCALTA.0 - fe.dai-link-0 (*)
2410 03:27:34.828278 # # LCALTA.0 - fe.dai-link-1 (*)
2411 03:27:34.828787 # # LCALTA.0 - fe.dai-link-2 (*)
2412 03:27:34.833812 # # LCALTA.0 - fe.dai-link-3 (*)
2413 03:27:34.834333 # # LCALTA.0 - fe.dai-link-4 (*)
2414 03:27:34.840249 # # LCALTA.0 - fe.dai-link-5 (*)
2415 03:27:34.840877 # 1..42
2416 03:27:34.844951 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2417 03:27:34.850446 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2418 03:27:34.850964 # # snd_pcm_hw_params: Invalid argument
2419 03:27:34.856215 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2420 03:27:34.861628 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2421 03:27:34.867149 # # snd_pcm_hw_params: Invalid argument
2422 03:27:34.872636 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2423 03:27:34.878246 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2424 03:27:34.878785 # # snd_pcm_hw_params: Invalid argument
2425 03:27:34.883749 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2426 03:27:34.889275 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2427 03:27:34.894797 # # snd_pcm_hw_params: Invalid argument
2428 03:27:34.900437 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2429 03:27:34.900974 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2430 03:27:34.905899 # # snd_pcm_hw_params: Invalid argument
2431 03:27:34.911441 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2432 03:27:34.916997 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2433 03:27:34.922496 # # snd_pcm_hw_params: Invalid argument
2434 03:27:34.928093 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2435 03:27:34.928592 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2436 03:27:34.933583 # # snd_pcm_hw_params: Invalid argument
2437 03:27:34.939149 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2438 03:27:34.944742 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2439 03:27:34.945222 # # snd_pcm_hw_params: Invalid argument
2440 03:27:34.950344 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2441 03:27:34.955790 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2442 03:27:34.961367 # # snd_pcm_hw_params: Invalid argument
2443 03:27:34.966879 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2444 03:27:34.972444 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2445 03:27:34.972897 # # snd_pcm_hw_params: Invalid argument
2446 03:27:34.977976 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2447 03:27:34.983501 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2448 03:27:34.989063 # # snd_pcm_hw_params: Invalid argument
2449 03:27:34.994620 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2450 03:27:35.000210 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2451 03:27:35.000708 # # snd_pcm_hw_params: Invalid argument
2452 03:27:35.005710 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2453 03:27:35.011347 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2454 03:27:35.016792 # # snd_pcm_hw_params: Invalid argument
2455 03:27:35.022387 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2456 03:27:35.027915 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2457 03:27:35.028454 # # snd_pcm_hw_params: Invalid argument
2458 03:27:35.033470 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2459 03:27:35.038987 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2460 03:27:35.044519 # # snd_pcm_hw_params: Invalid argument
2461 03:27:35.050042 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2462 03:27:35.050501 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2463 03:27:35.055583 # # snd_pcm_hw_params: Invalid argument
2464 03:27:35.061163 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2465 03:27:35.066733 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2466 03:27:35.072380 # # snd_pcm_hw_params: Invalid argument
2467 03:27:35.077822 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2468 03:27:35.078279 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2469 03:27:35.083365 # # snd_pcm_hw_params: Invalid argument
2470 03:27:35.088884 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2471 03:27:35.094447 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2472 03:27:35.094920 # # snd_pcm_hw_params: Invalid argument
2473 03:27:35.105494 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2474 03:27:35.105982 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2475 03:27:35.111113 # # snd_pcm_hw_params: Invalid argument
2476 03:27:35.116640 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2477 03:27:35.122189 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2478 03:27:35.122642 # # snd_pcm_hw_params: Invalid argument
2479 03:27:35.127750 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2480 03:27:35.133364 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2481 03:27:35.138825 # # snd_pcm_hw_params: Invalid argument
2482 03:27:35.144395 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2483 03:27:35.149919 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2484 03:27:35.150377 # # snd_pcm_hw_params: Invalid argument
2485 03:27:35.155472 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2486 03:27:35.161006 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2487 03:27:35.166512 # # snd_pcm_hw_params: Invalid argument
2488 03:27:35.172114 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2489 03:27:35.177659 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2490 03:27:35.178113 # # snd_pcm_hw_params: Invalid argument
2491 03:27:35.183196 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2492 03:27:35.188747 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2493 03:27:35.194361 # # snd_pcm_hw_params: Invalid argument
2494 03:27:35.199865 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2495 03:27:35.205342 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2496 03:27:35.205799 # # snd_pcm_hw_params: Invalid argument
2497 03:27:35.210942 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2498 03:27:35.216482 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2499 03:27:35.222023 # # snd_pcm_hw_params: Invalid argument
2500 03:27:35.227572 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2501 03:27:35.233110 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2502 03:27:35.233568 # # snd_pcm_hw_params: Invalid argument
2503 03:27:35.238678 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2504 03:27:35.244248 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2505 03:27:35.249744 # # snd_pcm_hw_params: Invalid argument
2506 03:27:35.255387 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2507 03:27:35.260862 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2508 03:27:35.261318 # # snd_pcm_hw_params: Invalid argument
2509 03:27:35.266410 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2510 03:27:35.271946 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2511 03:27:35.277479 # # snd_pcm_hw_params: Invalid argument
2512 03:27:35.283013 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2513 03:27:35.288554 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2514 03:27:35.289010 # # snd_pcm_hw_params: Invalid argument
2515 03:27:35.294132 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2516 03:27:35.299718 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2517 03:27:35.305235 # # snd_pcm_hw_params: Invalid argument
2518 03:27:35.310761 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2519 03:27:35.316369 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2520 03:27:35.316837 # # snd_pcm_hw_params: Invalid argument
2521 03:27:35.321844 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2522 03:27:35.327417 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2523 03:27:35.332959 # # snd_pcm_hw_params: Invalid argument
2524 03:27:35.338502 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2525 03:27:35.338957 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2526 03:27:35.344076 # # snd_pcm_hw_params: Invalid argument
2527 03:27:35.349611 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2528 03:27:35.355146 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2529 03:27:35.360688 # # snd_pcm_hw_params: Invalid argument
2530 03:27:35.366225 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2531 03:27:35.366678 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2532 03:27:35.371818 # # snd_pcm_hw_params: Invalid argument
2533 03:27:35.377423 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2534 03:27:35.382943 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2535 03:27:35.388446 # # snd_pcm_hw_params: Invalid argument
2536 03:27:35.393962 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2537 03:27:35.394424 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2538 03:27:35.399577 # # snd_pcm_hw_params: Invalid argument
2539 03:27:35.405105 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2540 03:27:35.410650 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2541 03:27:35.416274 # # snd_pcm_hw_params: Invalid argument
2542 03:27:35.421708 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2543 03:27:35.422178 ok 2 selftests: alsa: pcm-test
2544 03:27:35.422592 # timeout set to 45
2545 03:27:35.427263 # selftests: alsa: test-pcmtest-driver
2546 03:27:35.427746 # TAP version 13
2547 03:27:35.428197 # 1..5
2548 03:27:35.432802 # # Starting 5 tests from 1 test cases.
2549 03:27:35.438363 # # RUN pcmtest.playback ...
2550 03:27:35.443904 # # SKIP Can't read patterns. Probably, module isn't loaded
2551 03:27:35.444438 # # OK pcmtest.playback
2552 03:27:35.454949 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2553 03:27:35.455426 # # RUN pcmtest.capture ...
2554 03:27:35.460535 # # SKIP Can't read patterns. Probably, module isn't loaded
2555 03:27:35.466089 # # OK pcmtest.capture
2556 03:27:35.471635 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2557 03:27:35.477181 # # RUN pcmtest.ni_capture ...
2558 03:27:35.482733 # # SKIP Can't read patterns. Probably, module isn't loaded
2559 03:27:35.488272 # # OK pcmtest.ni_capture
2560 03:27:35.493804 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2561 03:27:35.499444 # # RUN pcmtest.ni_playback ...
2562 03:27:35.504932 # # SKIP Can't read patterns. Probably, module isn't loaded
2563 03:27:35.505453 # # OK pcmtest.ni_playback
2564 03:27:35.516044 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2565 03:27:35.516594 # # RUN pcmtest.reset_ioctl ...
2566 03:27:35.521528 # # SKIP Can't read patterns. Probably, module isn't loaded
2567 03:27:35.527102 # # OK pcmtest.reset_ioctl
2568 03:27:35.532630 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2569 03:27:35.538172 # # PASSED: 5 / 5 tests passed.
2570 03:27:35.543745 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2571 03:27:35.549292 ok 3 selftests: alsa: test-pcmtest-driver
2572 03:27:35.549774 # timeout set to 45
2573 03:27:35.550179 # selftests: alsa: utimer-test
2574 03:27:35.554816 # TAP version 13
2575 03:27:35.555287 # 1..2
2576 03:27:35.555690 # # Starting 2 tests from 2 test cases.
2577 03:27:35.560388 # # RUN global.wrong_timers_test ...
2578 03:27:35.565955 # # OK global.wrong_timers_test
2579 03:27:35.566448 # ok 1 global.wrong_timers_test
2580 03:27:35.571506 # # RUN timer_f.utimer ...
2581 03:27:35.582529 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2582 03:27:35.588098 # # utimer: Test terminated by assertion
2583 03:27:35.588571 # # FAIL timer_f.utimer
2584 03:27:35.588997 # not ok 2 timer_f.utimer
2585 03:27:35.593626 # # FAILED: 1 / 2 tests passed.
2586 03:27:35.599167 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2587 03:27:35.603127 not ok 4 selftests: alsa: utimer-test # exit=1
2588 03:27:36.098684 alsa_mixer-test_get_value_LCALTA_60 pass
2589 03:27:36.104174 alsa_mixer-test_name_LCALTA_60 pass
2590 03:27:36.104663 alsa_mixer-test_write_default_LCALTA_60 pass
2591 03:27:36.109658 alsa_mixer-test_write_valid_LCALTA_60 pass
2592 03:27:36.115182 alsa_mixer-test_write_invalid_LCALTA_60 pass
2593 03:27:36.120742 alsa_mixer-test_event_missing_LCALTA_60 pass
2594 03:27:36.121208 alsa_mixer-test_event_spurious_LCALTA_60 pass
2595 03:27:36.126270 alsa_mixer-test_get_value_LCALTA_59 pass
2596 03:27:36.131824 alsa_mixer-test_name_LCALTA_59 pass
2597 03:27:36.132309 alsa_mixer-test_write_default_LCALTA_59 pass
2598 03:27:36.137378 alsa_mixer-test_write_valid_LCALTA_59 pass
2599 03:27:36.142908 alsa_mixer-test_write_invalid_LCALTA_59 pass
2600 03:27:36.143363 alsa_mixer-test_event_missing_LCALTA_59 pass
2601 03:27:36.148463 alsa_mixer-test_event_spurious_LCALTA_59 pass
2602 03:27:36.154029 alsa_mixer-test_get_value_LCALTA_58 pass
2603 03:27:36.154491 alsa_mixer-test_name_LCALTA_58 pass
2604 03:27:36.159565 alsa_mixer-test_write_default_LCALTA_58 pass
2605 03:27:36.165090 alsa_mixer-test_write_valid_LCALTA_58 pass
2606 03:27:36.165545 alsa_mixer-test_write_invalid_LCALTA_58 pass
2607 03:27:36.170663 alsa_mixer-test_event_missing_LCALTA_58 pass
2608 03:27:36.176189 alsa_mixer-test_event_spurious_LCALTA_58 pass
2609 03:27:36.181724 alsa_mixer-test_get_value_LCALTA_57 pass
2610 03:27:36.182182 alsa_mixer-test_name_LCALTA_57 pass
2611 03:27:36.187381 alsa_mixer-test_write_default_LCALTA_57 pass
2612 03:27:36.192925 alsa_mixer-test_write_valid_LCALTA_57 pass
2613 03:27:36.193378 alsa_mixer-test_write_invalid_LCALTA_57 pass
2614 03:27:36.198482 alsa_mixer-test_event_missing_LCALTA_57 pass
2615 03:27:36.204068 alsa_mixer-test_event_spurious_LCALTA_57 pass
2616 03:27:36.204542 alsa_mixer-test_get_value_LCALTA_56 pass
2617 03:27:36.209558 alsa_mixer-test_name_LCALTA_56 pass
2618 03:27:36.215107 alsa_mixer-test_write_default_LCALTA_56 pass
2619 03:27:36.215569 alsa_mixer-test_write_valid_LCALTA_56 pass
2620 03:27:36.220663 alsa_mixer-test_write_invalid_LCALTA_56 pass
2621 03:27:36.226184 alsa_mixer-test_event_missing_LCALTA_56 pass
2622 03:27:36.231745 alsa_mixer-test_event_spurious_LCALTA_56 pass
2623 03:27:36.232227 alsa_mixer-test_get_value_LCALTA_55 pass
2624 03:27:36.237302 alsa_mixer-test_name_LCALTA_55 pass
2625 03:27:36.242845 alsa_mixer-test_write_default_LCALTA_55 pass
2626 03:27:36.243303 alsa_mixer-test_write_valid_LCALTA_55 pass
2627 03:27:36.248378 alsa_mixer-test_write_invalid_LCALTA_55 pass
2628 03:27:36.253937 alsa_mixer-test_event_missing_LCALTA_55 pass
2629 03:27:36.254394 alsa_mixer-test_event_spurious_LCALTA_55 pass
2630 03:27:36.259495 alsa_mixer-test_get_value_LCALTA_54 pass
2631 03:27:36.265020 alsa_mixer-test_name_LCALTA_54 pass
2632 03:27:36.265475 alsa_mixer-test_write_default_LCALTA_54 pass
2633 03:27:36.270567 alsa_mixer-test_write_valid_LCALTA_54 pass
2634 03:27:36.276112 alsa_mixer-test_write_invalid_LCALTA_54 pass
2635 03:27:36.276562 alsa_mixer-test_event_missing_LCALTA_54 pass
2636 03:27:36.281639 alsa_mixer-test_event_spurious_LCALTA_54 pass
2637 03:27:36.287176 alsa_mixer-test_get_value_LCALTA_53 pass
2638 03:27:36.287631 alsa_mixer-test_name_LCALTA_53 pass
2639 03:27:36.292726 alsa_mixer-test_write_default_LCALTA_53 pass
2640 03:27:36.298294 alsa_mixer-test_write_valid_LCALTA_53 pass
2641 03:27:36.303908 alsa_mixer-test_write_invalid_LCALTA_53 pass
2642 03:27:36.304401 alsa_mixer-test_event_missing_LCALTA_53 pass
2643 03:27:36.309399 alsa_mixer-test_event_spurious_LCALTA_53 pass
2644 03:27:36.314941 alsa_mixer-test_get_value_LCALTA_52 pass
2645 03:27:36.315399 alsa_mixer-test_name_LCALTA_52 pass
2646 03:27:36.320504 alsa_mixer-test_write_default_LCALTA_52 pass
2647 03:27:36.326045 alsa_mixer-test_write_valid_LCALTA_52 pass
2648 03:27:36.326497 alsa_mixer-test_write_invalid_LCALTA_52 pass
2649 03:27:36.331564 alsa_mixer-test_event_missing_LCALTA_52 pass
2650 03:27:36.337114 alsa_mixer-test_event_spurious_LCALTA_52 pass
2651 03:27:36.337560 alsa_mixer-test_get_value_LCALTA_51 pass
2652 03:27:36.342744 alsa_mixer-test_name_LCALTA_51 pass
2653 03:27:36.348267 alsa_mixer-test_write_default_LCALTA_51 pass
2654 03:27:36.348778 alsa_mixer-test_write_valid_LCALTA_51 pass
2655 03:27:36.353751 alsa_mixer-test_write_invalid_LCALTA_51 pass
2656 03:27:36.359275 alsa_mixer-test_event_missing_LCALTA_51 pass
2657 03:27:36.364845 alsa_mixer-test_event_spurious_LCALTA_51 pass
2658 03:27:36.365297 alsa_mixer-test_get_value_LCALTA_50 pass
2659 03:27:36.370596 alsa_mixer-test_name_LCALTA_50 pass
2660 03:27:36.376019 alsa_mixer-test_write_default_LCALTA_50 pass
2661 03:27:36.376730 alsa_mixer-test_write_valid_LCALTA_50 pass
2662 03:27:36.381567 alsa_mixer-test_write_invalid_LCALTA_50 pass
2663 03:27:36.387105 alsa_mixer-test_event_missing_LCALTA_50 pass
2664 03:27:36.387601 alsa_mixer-test_event_spurious_LCALTA_50 pass
2665 03:27:36.392596 alsa_mixer-test_get_value_LCALTA_49 pass
2666 03:27:36.398099 alsa_mixer-test_name_LCALTA_49 pass
2667 03:27:36.398564 alsa_mixer-test_write_default_LCALTA_49 pass
2668 03:27:36.403728 alsa_mixer-test_write_valid_LCALTA_49 pass
2669 03:27:36.409270 alsa_mixer-test_write_invalid_LCALTA_49 pass
2670 03:27:36.414827 alsa_mixer-test_event_missing_LCALTA_49 pass
2671 03:27:36.415322 alsa_mixer-test_event_spurious_LCALTA_49 pass
2672 03:27:36.420366 alsa_mixer-test_get_value_LCALTA_48 pass
2673 03:27:36.420841 alsa_mixer-test_name_LCALTA_48 pass
2674 03:27:36.425900 alsa_mixer-test_write_default_LCALTA_48 pass
2675 03:27:36.431417 alsa_mixer-test_write_valid_LCALTA_48 pass
2676 03:27:36.436976 alsa_mixer-test_write_invalid_LCALTA_48 pass
2677 03:27:36.437433 alsa_mixer-test_event_missing_LCALTA_48 pass
2678 03:27:36.442520 alsa_mixer-test_event_spurious_LCALTA_48 pass
2679 03:27:36.448084 alsa_mixer-test_get_value_LCALTA_47 pass
2680 03:27:36.448554 alsa_mixer-test_name_LCALTA_47 pass
2681 03:27:36.453683 alsa_mixer-test_write_default_LCALTA_47 pass
2682 03:27:36.459142 alsa_mixer-test_write_valid_LCALTA_47 pass
2683 03:27:36.459617 alsa_mixer-test_write_invalid_LCALTA_47 pass
2684 03:27:36.464700 alsa_mixer-test_event_missing_LCALTA_47 pass
2685 03:27:36.470246 alsa_mixer-test_event_spurious_LCALTA_47 pass
2686 03:27:36.475786 alsa_mixer-test_get_value_LCALTA_46 pass
2687 03:27:36.476283 alsa_mixer-test_name_LCALTA_46 pass
2688 03:27:36.481331 alsa_mixer-test_write_default_LCALTA_46 pass
2689 03:27:36.486875 alsa_mixer-test_write_valid_LCALTA_46 pass
2690 03:27:36.487333 alsa_mixer-test_write_invalid_LCALTA_46 pass
2691 03:27:36.492428 alsa_mixer-test_event_missing_LCALTA_46 pass
2692 03:27:36.498000 alsa_mixer-test_event_spurious_LCALTA_46 pass
2693 03:27:36.498484 alsa_mixer-test_get_value_LCALTA_45 pass
2694 03:27:36.503629 alsa_mixer-test_name_LCALTA_45 pass
2695 03:27:36.509119 alsa_mixer-test_write_default_LCALTA_45 pass
2696 03:27:36.509606 alsa_mixer-test_write_valid_LCALTA_45 pass
2697 03:27:36.514651 alsa_mixer-test_write_invalid_LCALTA_45 pass
2698 03:27:36.520235 alsa_mixer-test_event_missing_LCALTA_45 pass
2699 03:27:36.520707 alsa_mixer-test_event_spurious_LCALTA_45 pass
2700 03:27:36.525738 alsa_mixer-test_get_value_LCALTA_44 pass
2701 03:27:36.531301 alsa_mixer-test_name_LCALTA_44 pass
2702 03:27:36.531776 alsa_mixer-test_write_default_LCALTA_44 pass
2703 03:27:36.536845 alsa_mixer-test_write_valid_LCALTA_44 pass
2704 03:27:36.542390 alsa_mixer-test_write_invalid_LCALTA_44 pass
2705 03:27:36.547918 alsa_mixer-test_event_missing_LCALTA_44 pass
2706 03:27:36.548419 alsa_mixer-test_event_spurious_LCALTA_44 pass
2707 03:27:36.553552 alsa_mixer-test_get_value_LCALTA_43 pass
2708 03:27:36.558999 alsa_mixer-test_name_LCALTA_43 pass
2709 03:27:36.559463 alsa_mixer-test_write_default_LCALTA_43 pass
2710 03:27:36.564630 alsa_mixer-test_write_valid_LCALTA_43 pass
2711 03:27:36.570119 alsa_mixer-test_write_invalid_LCALTA_43 pass
2712 03:27:36.570591 alsa_mixer-test_event_missing_LCALTA_43 pass
2713 03:27:36.575657 alsa_mixer-test_event_spurious_LCALTA_43 pass
2714 03:27:36.581202 alsa_mixer-test_get_value_LCALTA_42 pass
2715 03:27:36.581665 alsa_mixer-test_name_LCALTA_42 pass
2716 03:27:36.586818 alsa_mixer-test_write_default_LCALTA_42 pass
2717 03:27:36.592294 alsa_mixer-test_write_valid_LCALTA_42 pass
2718 03:27:36.592754 alsa_mixer-test_write_invalid_LCALTA_42 pass
2719 03:27:36.597818 alsa_mixer-test_event_missing_LCALTA_42 pass
2720 03:27:36.603369 alsa_mixer-test_event_spurious_LCALTA_42 pass
2721 03:27:36.608958 alsa_mixer-test_get_value_LCALTA_41 pass
2722 03:27:36.609439 alsa_mixer-test_name_LCALTA_41 pass
2723 03:27:36.614560 alsa_mixer-test_write_default_LCALTA_41 pass
2724 03:27:36.620047 alsa_mixer-test_write_valid_LCALTA_41 pass
2725 03:27:36.620503 alsa_mixer-test_write_invalid_LCALTA_41 pass
2726 03:27:36.625587 alsa_mixer-test_event_missing_LCALTA_41 pass
2727 03:27:36.631117 alsa_mixer-test_event_spurious_LCALTA_41 pass
2728 03:27:36.631570 alsa_mixer-test_get_value_LCALTA_40 pass
2729 03:27:36.636672 alsa_mixer-test_name_LCALTA_40 pass
2730 03:27:36.642193 alsa_mixer-test_write_default_LCALTA_40 pass
2731 03:27:36.642644 alsa_mixer-test_write_valid_LCALTA_40 pass
2732 03:27:36.647735 alsa_mixer-test_write_invalid_LCALTA_40 pass
2733 03:27:36.653300 alsa_mixer-test_event_missing_LCALTA_40 pass
2734 03:27:36.658838 alsa_mixer-test_event_spurious_LCALTA_40 pass
2735 03:27:36.659284 alsa_mixer-test_get_value_LCALTA_39 pass
2736 03:27:36.664389 alsa_mixer-test_name_LCALTA_39 pass
2737 03:27:36.669931 alsa_mixer-test_write_default_LCALTA_39 pass
2738 03:27:36.670392 alsa_mixer-test_write_valid_LCALTA_39 pass
2739 03:27:36.675554 alsa_mixer-test_write_invalid_LCALTA_39 pass
2740 03:27:36.681010 alsa_mixer-test_event_missing_LCALTA_39 pass
2741 03:27:36.681463 alsa_mixer-test_event_spurious_LCALTA_39 pass
2742 03:27:36.686587 alsa_mixer-test_get_value_LCALTA_38 pass
2743 03:27:36.692128 alsa_mixer-test_name_LCALTA_38 pass
2744 03:27:36.692597 alsa_mixer-test_write_default_LCALTA_38 pass
2745 03:27:36.697656 alsa_mixer-test_write_valid_LCALTA_38 pass
2746 03:27:36.703182 alsa_mixer-test_write_invalid_LCALTA_38 pass
2747 03:27:36.703631 alsa_mixer-test_event_missing_LCALTA_38 pass
2748 03:27:36.708771 alsa_mixer-test_event_spurious_LCALTA_38 pass
2749 03:27:36.714296 alsa_mixer-test_get_value_LCALTA_37 pass
2750 03:27:36.714748 alsa_mixer-test_name_LCALTA_37 pass
2751 03:27:36.719835 alsa_mixer-test_write_default_LCALTA_37 pass
2752 03:27:36.725384 alsa_mixer-test_write_valid_LCALTA_37 pass
2753 03:27:36.730955 alsa_mixer-test_write_invalid_LCALTA_37 pass
2754 03:27:36.731410 alsa_mixer-test_event_missing_LCALTA_37 pass
2755 03:27:36.736587 alsa_mixer-test_event_spurious_LCALTA_37 pass
2756 03:27:36.742056 alsa_mixer-test_get_value_LCALTA_36 pass
2757 03:27:36.742506 alsa_mixer-test_name_LCALTA_36 pass
2758 03:27:36.747600 alsa_mixer-test_write_default_LCALTA_36 pass
2759 03:27:36.753136 alsa_mixer-test_write_valid_LCALTA_36 pass
2760 03:27:36.753584 alsa_mixer-test_write_invalid_LCALTA_36 pass
2761 03:27:36.758686 alsa_mixer-test_event_missing_LCALTA_36 pass
2762 03:27:36.764247 alsa_mixer-test_event_spurious_LCALTA_36 pass
2763 03:27:36.764698 alsa_mixer-test_get_value_LCALTA_35 pass
2764 03:27:36.769775 alsa_mixer-test_name_LCALTA_35 pass
2765 03:27:36.775325 alsa_mixer-test_write_default_LCALTA_35 pass
2766 03:27:36.775784 alsa_mixer-test_write_valid_LCALTA_35 pass
2767 03:27:36.780848 alsa_mixer-test_write_invalid_LCALTA_35 pass
2768 03:27:36.786414 alsa_mixer-test_event_missing_LCALTA_35 pass
2769 03:27:36.791951 alsa_mixer-test_event_spurious_LCALTA_35 pass
2770 03:27:36.792433 alsa_mixer-test_get_value_LCALTA_34 pass
2771 03:27:36.797574 alsa_mixer-test_name_LCALTA_34 pass
2772 03:27:36.803069 alsa_mixer-test_write_default_LCALTA_34 pass
2773 03:27:36.803520 alsa_mixer-test_write_valid_LCALTA_34 pass
2774 03:27:36.808656 alsa_mixer-test_write_invalid_LCALTA_34 pass
2775 03:27:36.814148 alsa_mixer-test_event_missing_LCALTA_34 pass
2776 03:27:36.814616 alsa_mixer-test_event_spurious_LCALTA_34 pass
2777 03:27:36.819686 alsa_mixer-test_get_value_LCALTA_33 pass
2778 03:27:36.825233 alsa_mixer-test_name_LCALTA_33 pass
2779 03:27:36.825690 alsa_mixer-test_write_default_LCALTA_33 pass
2780 03:27:36.830794 alsa_mixer-test_write_valid_LCALTA_33 pass
2781 03:27:36.836332 alsa_mixer-test_write_invalid_LCALTA_33 pass
2782 03:27:36.841888 alsa_mixer-test_event_missing_LCALTA_33 pass
2783 03:27:36.842336 alsa_mixer-test_event_spurious_LCALTA_33 pass
2784 03:27:36.847442 alsa_mixer-test_get_value_LCALTA_32 pass
2785 03:27:36.847891 alsa_mixer-test_name_LCALTA_32 pass
2786 03:27:36.852979 alsa_mixer-test_write_default_LCALTA_32 pass
2787 03:27:36.858593 alsa_mixer-test_write_valid_LCALTA_32 pass
2788 03:27:36.864087 alsa_mixer-test_write_invalid_LCALTA_32 pass
2789 03:27:36.864538 alsa_mixer-test_event_missing_LCALTA_32 pass
2790 03:27:36.869629 alsa_mixer-test_event_spurious_LCALTA_32 pass
2791 03:27:36.875164 alsa_mixer-test_get_value_LCALTA_31 pass
2792 03:27:36.875614 alsa_mixer-test_name_LCALTA_31 pass
2793 03:27:36.880688 alsa_mixer-test_write_default_LCALTA_31 pass
2794 03:27:36.886229 alsa_mixer-test_write_valid_LCALTA_31 pass
2795 03:27:36.886675 alsa_mixer-test_write_invalid_LCALTA_31 pass
2796 03:27:36.891803 alsa_mixer-test_event_missing_LCALTA_31 pass
2797 03:27:36.897345 alsa_mixer-test_event_spurious_LCALTA_31 pass
2798 03:27:36.902864 alsa_mixer-test_get_value_LCALTA_30 pass
2799 03:27:36.903311 alsa_mixer-test_name_LCALTA_30 pass
2800 03:27:36.908488 alsa_mixer-test_write_default_LCALTA_30 pass
2801 03:27:36.913978 alsa_mixer-test_write_valid_LCALTA_30 pass
2802 03:27:36.914429 alsa_mixer-test_write_invalid_LCALTA_30 pass
2803 03:27:36.919608 alsa_mixer-test_event_missing_LCALTA_30 pass
2804 03:27:36.925076 alsa_mixer-test_event_spurious_LCALTA_30 pass
2805 03:27:36.925533 alsa_mixer-test_get_value_LCALTA_29 pass
2806 03:27:36.930639 alsa_mixer-test_name_LCALTA_29 pass
2807 03:27:36.936209 alsa_mixer-test_write_default_LCALTA_29 pass
2808 03:27:36.936659 alsa_mixer-test_write_valid_LCALTA_29 pass
2809 03:27:36.941713 alsa_mixer-test_write_invalid_LCALTA_29 pass
2810 03:27:36.947247 alsa_mixer-test_event_missing_LCALTA_29 pass
2811 03:27:36.947700 alsa_mixer-test_event_spurious_LCALTA_29 pass
2812 03:27:36.952825 alsa_mixer-test_get_value_LCALTA_28 pass
2813 03:27:36.958360 alsa_mixer-test_name_LCALTA_28 pass
2814 03:27:36.958810 alsa_mixer-test_write_default_LCALTA_28 pass
2815 03:27:36.963903 alsa_mixer-test_write_valid_LCALTA_28 pass
2816 03:27:36.969467 alsa_mixer-test_write_invalid_LCALTA_28 pass
2817 03:27:36.975000 alsa_mixer-test_event_missing_LCALTA_28 pass
2818 03:27:36.975448 alsa_mixer-test_event_spurious_LCALTA_28 pass
2819 03:27:36.980581 alsa_mixer-test_get_value_LCALTA_27 pass
2820 03:27:36.986069 alsa_mixer-test_name_LCALTA_27 pass
2821 03:27:36.986520 alsa_mixer-test_write_default_LCALTA_27 pass
2822 03:27:36.991610 alsa_mixer-test_write_valid_LCALTA_27 pass
2823 03:27:36.997164 alsa_mixer-test_write_invalid_LCALTA_27 pass
2824 03:27:36.997630 alsa_mixer-test_event_missing_LCALTA_27 pass
2825 03:27:37.002778 alsa_mixer-test_event_spurious_LCALTA_27 pass
2826 03:27:37.008305 alsa_mixer-test_get_value_LCALTA_26 pass
2827 03:27:37.008770 alsa_mixer-test_name_LCALTA_26 pass
2828 03:27:37.013841 alsa_mixer-test_write_default_LCALTA_26 skip
2829 03:27:37.019392 alsa_mixer-test_write_valid_LCALTA_26 skip
2830 03:27:37.019853 alsa_mixer-test_write_invalid_LCALTA_26 skip
2831 03:27:37.024950 alsa_mixer-test_event_missing_LCALTA_26 pass
2832 03:27:37.030499 alsa_mixer-test_event_spurious_LCALTA_26 pass
2833 03:27:37.036044 alsa_mixer-test_get_value_LCALTA_25 pass
2834 03:27:37.036502 alsa_mixer-test_name_LCALTA_25 pass
2835 03:27:37.041586 alsa_mixer-test_write_default_LCALTA_25 pass
2836 03:27:37.047098 alsa_mixer-test_write_valid_LCALTA_25 skip
2837 03:27:37.047554 alsa_mixer-test_write_invalid_LCALTA_25 skip
2838 03:27:37.052625 alsa_mixer-test_event_missing_LCALTA_25 pass
2839 03:27:37.058175 alsa_mixer-test_event_spurious_LCALTA_25 pass
2840 03:27:37.058628 alsa_mixer-test_get_value_LCALTA_24 pass
2841 03:27:37.063732 alsa_mixer-test_name_LCALTA_24 pass
2842 03:27:37.069305 alsa_mixer-test_write_default_LCALTA_24 skip
2843 03:27:37.069776 alsa_mixer-test_write_valid_LCALTA_24 skip
2844 03:27:37.074868 alsa_mixer-test_write_invalid_LCALTA_24 skip
2845 03:27:37.080372 alsa_mixer-test_event_missing_LCALTA_24 pass
2846 03:27:37.085920 alsa_mixer-test_event_spurious_LCALTA_24 pass
2847 03:27:37.086372 alsa_mixer-test_get_value_LCALTA_23 pass
2848 03:27:37.091464 alsa_mixer-test_name_LCALTA_23 pass
2849 03:27:37.097011 alsa_mixer-test_write_default_LCALTA_23 skip
2850 03:27:37.097466 alsa_mixer-test_write_valid_LCALTA_23 skip
2851 03:27:37.102581 alsa_mixer-test_write_invalid_LCALTA_23 skip
2852 03:27:37.108191 alsa_mixer-test_event_missing_LCALTA_23 pass
2853 03:27:37.108657 alsa_mixer-test_event_spurious_LCALTA_23 pass
2854 03:27:37.113679 alsa_mixer-test_get_value_LCALTA_22 pass
2855 03:27:37.119213 alsa_mixer-test_name_LCALTA_22 pass
2856 03:27:37.119664 alsa_mixer-test_write_default_LCALTA_22 pass
2857 03:27:37.124763 alsa_mixer-test_write_valid_LCALTA_22 pass
2858 03:27:37.130302 alsa_mixer-test_write_invalid_LCALTA_22 pass
2859 03:27:37.130749 alsa_mixer-test_event_missing_LCALTA_22 pass
2860 03:27:37.135846 alsa_mixer-test_event_spurious_LCALTA_22 pass
2861 03:27:37.141400 alsa_mixer-test_get_value_LCALTA_21 pass
2862 03:27:37.141870 alsa_mixer-test_name_LCALTA_21 pass
2863 03:27:37.146932 alsa_mixer-test_write_default_LCALTA_21 pass
2864 03:27:37.152486 alsa_mixer-test_write_valid_LCALTA_21 pass
2865 03:27:37.158040 alsa_mixer-test_write_invalid_LCALTA_21 pass
2866 03:27:37.158491 alsa_mixer-test_event_missing_LCALTA_21 pass
2867 03:27:37.163611 alsa_mixer-test_event_spurious_LCALTA_21 pass
2868 03:27:37.169128 alsa_mixer-test_get_value_LCALTA_20 pass
2869 03:27:37.169578 alsa_mixer-test_name_LCALTA_20 pass
2870 03:27:37.174687 alsa_mixer-test_write_default_LCALTA_20 pass
2871 03:27:37.180238 alsa_mixer-test_write_valid_LCALTA_20 pass
2872 03:27:37.180703 alsa_mixer-test_write_invalid_LCALTA_20 pass
2873 03:27:37.185793 alsa_mixer-test_event_missing_LCALTA_20 pass
2874 03:27:37.191323 alsa_mixer-test_event_spurious_LCALTA_20 pass
2875 03:27:37.191774 alsa_mixer-test_get_value_LCALTA_19 pass
2876 03:27:37.196842 alsa_mixer-test_name_LCALTA_19 pass
2877 03:27:37.202389 alsa_mixer-test_write_default_LCALTA_19 pass
2878 03:27:37.202839 alsa_mixer-test_write_valid_LCALTA_19 pass
2879 03:27:37.208006 alsa_mixer-test_write_invalid_LCALTA_19 pass
2880 03:27:37.213501 alsa_mixer-test_event_missing_LCALTA_19 pass
2881 03:27:37.219048 alsa_mixer-test_event_spurious_LCALTA_19 pass
2882 03:27:37.219498 alsa_mixer-test_get_value_LCALTA_18 pass
2883 03:27:37.224611 alsa_mixer-test_name_LCALTA_18 pass
2884 03:27:37.230157 alsa_mixer-test_write_default_LCALTA_18 pass
2885 03:27:37.230634 alsa_mixer-test_write_valid_LCALTA_18 pass
2886 03:27:37.235690 alsa_mixer-test_write_invalid_LCALTA_18 pass
2887 03:27:37.241250 alsa_mixer-test_event_missing_LCALTA_18 pass
2888 03:27:37.241703 alsa_mixer-test_event_spurious_LCALTA_18 pass
2889 03:27:37.246783 alsa_mixer-test_get_value_LCALTA_17 pass
2890 03:27:37.252343 alsa_mixer-test_name_LCALTA_17 pass
2891 03:27:37.252806 alsa_mixer-test_write_default_LCALTA_17 pass
2892 03:27:37.257884 alsa_mixer-test_write_valid_LCALTA_17 pass
2893 03:27:37.263432 alsa_mixer-test_write_invalid_LCALTA_17 pass
2894 03:27:37.268983 alsa_mixer-test_event_missing_LCALTA_17 pass
2895 03:27:37.269435 alsa_mixer-test_event_spurious_LCALTA_17 pass
2896 03:27:37.274524 alsa_mixer-test_get_value_LCALTA_16 pass
2897 03:27:37.274978 alsa_mixer-test_name_LCALTA_16 pass
2898 03:27:37.280083 alsa_mixer-test_write_default_LCALTA_16 pass
2899 03:27:37.285632 alsa_mixer-test_write_valid_LCALTA_16 pass
2900 03:27:37.291141 alsa_mixer-test_write_invalid_LCALTA_16 pass
2901 03:27:37.291592 alsa_mixer-test_event_missing_LCALTA_16 pass
2902 03:27:37.296686 alsa_mixer-test_event_spurious_LCALTA_16 pass
2903 03:27:37.302245 alsa_mixer-test_get_value_LCALTA_15 pass
2904 03:27:37.302702 alsa_mixer-test_name_LCALTA_15 pass
2905 03:27:37.307811 alsa_mixer-test_write_default_LCALTA_15 pass
2906 03:27:37.313352 alsa_mixer-test_write_valid_LCALTA_15 pass
2907 03:27:37.313816 alsa_mixer-test_write_invalid_LCALTA_15 pass
2908 03:27:37.318903 alsa_mixer-test_event_missing_LCALTA_15 pass
2909 03:27:37.324424 alsa_mixer-test_event_spurious_LCALTA_15 pass
2910 03:27:37.329985 alsa_mixer-test_get_value_LCALTA_14 pass
2911 03:27:37.330437 alsa_mixer-test_name_LCALTA_14 pass
2912 03:27:37.335518 alsa_mixer-test_write_default_LCALTA_14 pass
2913 03:27:37.341089 alsa_mixer-test_write_valid_LCALTA_14 pass
2914 03:27:37.341542 alsa_mixer-test_write_invalid_LCALTA_14 pass
2915 03:27:37.346644 alsa_mixer-test_event_missing_LCALTA_14 pass
2916 03:27:37.352207 alsa_mixer-test_event_spurious_LCALTA_14 pass
2917 03:27:37.352656 alsa_mixer-test_get_value_LCALTA_13 pass
2918 03:27:37.357691 alsa_mixer-test_name_LCALTA_13 pass
2919 03:27:37.363226 alsa_mixer-test_write_default_LCALTA_13 pass
2920 03:27:37.363672 alsa_mixer-test_write_valid_LCALTA_13 pass
2921 03:27:37.368799 alsa_mixer-test_write_invalid_LCALTA_13 pass
2922 03:27:37.374401 alsa_mixer-test_event_missing_LCALTA_13 pass
2923 03:27:37.374898 alsa_mixer-test_event_spurious_LCALTA_13 pass
2924 03:27:37.379958 alsa_mixer-test_get_value_LCALTA_12 pass
2925 03:27:37.385487 alsa_mixer-test_name_LCALTA_12 pass
2926 03:27:37.385994 alsa_mixer-test_write_default_LCALTA_12 pass
2927 03:27:37.390914 alsa_mixer-test_write_valid_LCALTA_12 pass
2928 03:27:37.396453 alsa_mixer-test_write_invalid_LCALTA_12 pass
2929 03:27:37.402066 alsa_mixer-test_event_missing_LCALTA_12 pass
2930 03:27:37.402656 alsa_mixer-test_event_spurious_LCALTA_12 pass
2931 03:27:37.407566 alsa_mixer-test_get_value_LCALTA_11 pass
2932 03:27:37.413216 alsa_mixer-test_name_LCALTA_11 pass
2933 03:27:37.413741 alsa_mixer-test_write_default_LCALTA_11 pass
2934 03:27:37.418671 alsa_mixer-test_write_valid_LCALTA_11 pass
2935 03:27:37.424221 alsa_mixer-test_write_invalid_LCALTA_11 pass
2936 03:27:37.424721 alsa_mixer-test_event_missing_LCALTA_11 pass
2937 03:27:37.429739 alsa_mixer-test_event_spurious_LCALTA_11 pass
2938 03:27:37.435283 alsa_mixer-test_get_value_LCALTA_10 pass
2939 03:27:37.435774 alsa_mixer-test_name_LCALTA_10 pass
2940 03:27:37.440814 alsa_mixer-test_write_default_LCALTA_10 pass
2941 03:27:37.446365 alsa_mixer-test_write_valid_LCALTA_10 pass
2942 03:27:37.446856 alsa_mixer-test_write_invalid_LCALTA_10 pass
2943 03:27:37.451941 alsa_mixer-test_event_missing_LCALTA_10 pass
2944 03:27:37.457455 alsa_mixer-test_event_spurious_LCALTA_10 pass
2945 03:27:37.463020 alsa_mixer-test_get_value_LCALTA_9 pass
2946 03:27:37.463516 alsa_mixer-test_name_LCALTA_9 pass
2947 03:27:37.468572 alsa_mixer-test_write_default_LCALTA_9 pass
2948 03:27:37.474121 alsa_mixer-test_write_valid_LCALTA_9 pass
2949 03:27:37.474621 alsa_mixer-test_write_invalid_LCALTA_9 pass
2950 03:27:37.479656 alsa_mixer-test_event_missing_LCALTA_9 pass
2951 03:27:37.485195 alsa_mixer-test_event_spurious_LCALTA_9 pass
2952 03:27:37.485684 alsa_mixer-test_get_value_LCALTA_8 pass
2953 03:27:37.490734 alsa_mixer-test_name_LCALTA_8 pass
2954 03:27:37.496387 alsa_mixer-test_write_default_LCALTA_8 pass
2955 03:27:37.496874 alsa_mixer-test_write_valid_LCALTA_8 pass
2956 03:27:37.501927 alsa_mixer-test_write_invalid_LCALTA_8 pass
2957 03:27:37.507404 alsa_mixer-test_event_missing_LCALTA_8 pass
2958 03:27:37.507911 alsa_mixer-test_event_spurious_LCALTA_8 pass
2959 03:27:37.513012 alsa_mixer-test_get_value_LCALTA_7 pass
2960 03:27:37.518514 alsa_mixer-test_name_LCALTA_7 pass
2961 03:27:37.519008 alsa_mixer-test_write_default_LCALTA_7 pass
2962 03:27:37.524068 alsa_mixer-test_write_valid_LCALTA_7 pass
2963 03:27:37.529596 alsa_mixer-test_write_invalid_LCALTA_7 pass
2964 03:27:37.530094 alsa_mixer-test_event_missing_LCALTA_7 pass
2965 03:27:37.535144 alsa_mixer-test_event_spurious_LCALTA_7 pass
2966 03:27:37.540699 alsa_mixer-test_get_value_LCALTA_6 pass
2967 03:27:37.541204 alsa_mixer-test_name_LCALTA_6 pass
2968 03:27:37.546224 alsa_mixer-test_write_default_LCALTA_6 pass
2969 03:27:37.551764 alsa_mixer-test_write_valid_LCALTA_6 pass
2970 03:27:37.552297 alsa_mixer-test_write_invalid_LCALTA_6 pass
2971 03:27:37.557306 alsa_mixer-test_event_missing_LCALTA_6 pass
2972 03:27:37.562885 alsa_mixer-test_event_spurious_LCALTA_6 pass
2973 03:27:37.563384 alsa_mixer-test_get_value_LCALTA_5 pass
2974 03:27:37.568429 alsa_mixer-test_name_LCALTA_5 pass
2975 03:27:37.573942 alsa_mixer-test_write_default_LCALTA_5 pass
2976 03:27:37.574440 alsa_mixer-test_write_valid_LCALTA_5 pass
2977 03:27:37.579506 alsa_mixer-test_write_invalid_LCALTA_5 pass
2978 03:27:37.585045 alsa_mixer-test_event_missing_LCALTA_5 pass
2979 03:27:37.585544 alsa_mixer-test_event_spurious_LCALTA_5 pass
2980 03:27:37.590597 alsa_mixer-test_get_value_LCALTA_4 pass
2981 03:27:37.596161 alsa_mixer-test_name_LCALTA_4 pass
2982 03:27:37.596666 alsa_mixer-test_write_default_LCALTA_4 pass
2983 03:27:37.601715 alsa_mixer-test_write_valid_LCALTA_4 pass
2984 03:27:37.607224 alsa_mixer-test_write_invalid_LCALTA_4 pass
2985 03:27:37.607722 alsa_mixer-test_event_missing_LCALTA_4 pass
2986 03:27:37.612847 alsa_mixer-test_event_spurious_LCALTA_4 pass
2987 03:27:37.618345 alsa_mixer-test_get_value_LCALTA_3 pass
2988 03:27:37.618834 alsa_mixer-test_name_LCALTA_3 pass
2989 03:27:37.623878 alsa_mixer-test_write_default_LCALTA_3 pass
2990 03:27:37.629436 alsa_mixer-test_write_valid_LCALTA_3 pass
2991 03:27:37.629928 alsa_mixer-test_write_invalid_LCALTA_3 pass
2992 03:27:37.634969 alsa_mixer-test_event_missing_LCALTA_3 pass
2993 03:27:37.640508 alsa_mixer-test_event_spurious_LCALTA_3 pass
2994 03:27:37.640993 alsa_mixer-test_get_value_LCALTA_2 pass
2995 03:27:37.646067 alsa_mixer-test_name_LCALTA_2 pass
2996 03:27:37.651662 alsa_mixer-test_write_default_LCALTA_2 pass
2997 03:27:37.652185 alsa_mixer-test_write_valid_LCALTA_2 pass
2998 03:27:37.657153 alsa_mixer-test_write_invalid_LCALTA_2 pass
2999 03:27:37.664067 alsa_mixer-test_event_missing_LCALTA_2 pass
3000 03:27:37.668230 alsa_mixer-test_event_spurious_LCALTA_2 pass
3001 03:27:37.668716 alsa_mixer-test_get_value_LCALTA_1 pass
3002 03:27:37.673800 alsa_mixer-test_name_LCALTA_1 pass
3003 03:27:37.674287 alsa_mixer-test_write_default_LCALTA_1 pass
3004 03:27:37.679354 alsa_mixer-test_write_valid_LCALTA_1 pass
3005 03:27:37.684894 alsa_mixer-test_write_invalid_LCALTA_1 pass
3006 03:27:37.690443 alsa_mixer-test_event_missing_LCALTA_1 pass
3007 03:27:37.690934 alsa_mixer-test_event_spurious_LCALTA_1 pass
3008 03:27:37.696034 alsa_mixer-test_get_value_LCALTA_0 pass
3009 03:27:37.696548 alsa_mixer-test_name_LCALTA_0 pass
3010 03:27:37.701628 alsa_mixer-test_write_default_LCALTA_0 pass
3011 03:27:37.707058 alsa_mixer-test_write_valid_LCALTA_0 pass
3012 03:27:37.712716 alsa_mixer-test_write_invalid_LCALTA_0 pass
3013 03:27:37.713198 alsa_mixer-test_event_missing_LCALTA_0 pass
3014 03:27:37.718185 alsa_mixer-test_event_spurious_LCALTA_0 pass
3015 03:27:37.718670 alsa_mixer-test pass
3016 03:27:37.723741 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
3017 03:27:37.729267 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
3018 03:27:37.734814 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
3019 03:27:37.740365 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
3020 03:27:37.740858 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
3021 03:27:37.745910 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
3022 03:27:37.751448 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
3023 03:27:37.756993 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
3024 03:27:37.762613 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
3025 03:27:37.768090 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
3026 03:27:37.768584 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
3027 03:27:37.773671 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
3028 03:27:37.779178 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
3029 03:27:37.784749 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
3030 03:27:37.790281 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
3031 03:27:37.795830 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
3032 03:27:37.796365 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
3033 03:27:37.801350 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
3034 03:27:37.806920 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
3035 03:27:37.812513 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
3036 03:27:37.818015 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
3037 03:27:37.823652 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
3038 03:27:37.824172 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
3039 03:27:37.829119 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
3040 03:27:37.834690 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
3041 03:27:37.840227 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
3042 03:27:37.845755 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
3043 03:27:37.851301 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
3044 03:27:37.851794 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
3045 03:27:37.856835 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
3046 03:27:37.862364 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
3047 03:27:37.867913 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
3048 03:27:37.873504 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
3049 03:27:37.879026 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
3050 03:27:37.884636 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
3051 03:27:37.885123 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
3052 03:27:37.890112 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
3053 03:27:37.895695 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
3054 03:27:37.901212 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
3055 03:27:37.906762 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
3056 03:27:37.912356 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
3057 03:27:37.912842 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
3058 03:27:37.917861 alsa_pcm-test pass
3059 03:27:37.923404 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3060 03:27:37.934505 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3061 03:27:37.940063 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3062 03:27:37.951133 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3063 03:27:37.956683 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3064 03:27:37.962207 alsa_test-pcmtest-driver pass
3065 03:27:37.967748 alsa_utimer-test_global_wrong_timers_test pass
3066 03:27:37.968271 alsa_utimer-test_timer_f_utimer fail
3067 03:27:37.973323 alsa_utimer-test fail
3068 03:27:37.973817 + ../../utils/send-to-lava.sh ./output/result.txt
3069 03:27:37.978870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
3070 03:27:37.979826 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
3072 03:27:37.989943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
3073 03:27:37.990719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
3075 03:27:37.995500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
3076 03:27:37.996299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
3078 03:27:38.003484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
3079 03:27:38.004287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
3081 03:27:38.047616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
3082 03:27:38.048424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
3084 03:27:38.093484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
3085 03:27:38.094307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
3087 03:27:38.152357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
3088 03:27:38.153135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
3090 03:27:38.202532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
3091 03:27:38.203290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
3093 03:27:38.252224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
3094 03:27:38.252994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
3096 03:27:38.301415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
3097 03:27:38.302233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
3099 03:27:38.354482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
3100 03:27:38.355244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
3102 03:27:38.415263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
3103 03:27:38.416151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
3105 03:27:38.467633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
3106 03:27:38.468499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
3108 03:27:38.517399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
3109 03:27:38.518199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
3111 03:27:38.565556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
3112 03:27:38.566376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
3114 03:27:38.616596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
3115 03:27:38.617400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
3117 03:27:38.664843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
3118 03:27:38.665609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
3120 03:27:38.709715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
3121 03:27:38.710484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
3123 03:27:38.767426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
3124 03:27:38.768214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
3126 03:27:38.826790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
3127 03:27:38.827559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
3129 03:27:38.883383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
3130 03:27:38.884139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
3132 03:27:38.940211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
3133 03:27:38.940968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
3135 03:27:38.998337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
3136 03:27:38.999101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
3138 03:27:39.048850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
3139 03:27:39.049661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
3141 03:27:39.100849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
3142 03:27:39.101676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
3144 03:27:39.150390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3145 03:27:39.151148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3147 03:27:39.202497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3148 03:27:39.203266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3150 03:27:39.251057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3151 03:27:39.251815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3153 03:27:39.306032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3154 03:27:39.306834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3156 03:27:39.364402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3157 03:27:39.365185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3159 03:27:39.417632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3160 03:27:39.418539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3162 03:27:39.462570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3163 03:27:39.463389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3165 03:27:39.524078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3166 03:27:39.524889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3168 03:27:39.573731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3169 03:27:39.574575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3171 03:27:39.619806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3172 03:27:39.620638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3174 03:27:39.673151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3175 03:27:39.673922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3177 03:27:39.722054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3178 03:27:39.722819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3180 03:27:39.765462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3181 03:27:39.766264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3183 03:27:39.812085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3184 03:27:39.812938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3186 03:27:39.861647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3187 03:27:39.862397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3189 03:27:39.917854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3190 03:27:39.918593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3192 03:27:39.971678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3193 03:27:39.972481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3195 03:27:40.031331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3196 03:27:40.032078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3198 03:27:40.083532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3199 03:27:40.084430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3201 03:27:40.135152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3202 03:27:40.135956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3204 03:27:40.183508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3205 03:27:40.184371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3207 03:27:40.234396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3208 03:27:40.235193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3210 03:27:40.293044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3211 03:27:40.293872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3213 03:27:40.342722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3214 03:27:40.343571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3216 03:27:40.397215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3217 03:27:40.398005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3219 03:27:40.449519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3220 03:27:40.450425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3222 03:27:40.500420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3223 03:27:40.501237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3225 03:27:40.557202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3226 03:27:40.558001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3228 03:27:40.598541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3229 03:27:40.599338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3231 03:27:40.644379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3232 03:27:40.645181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3234 03:27:40.702693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3235 03:27:40.703493 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3237 03:27:40.752942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3238 03:27:40.753741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3240 03:27:40.801262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3241 03:27:40.802029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3243 03:27:40.846012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3244 03:27:40.846791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3246 03:27:40.909297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3247 03:27:40.910095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3249 03:27:40.962512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3250 03:27:40.963310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3252 03:27:41.013496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3253 03:27:41.014283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3255 03:27:41.070722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3256 03:27:41.071573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3258 03:27:41.124316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3259 03:27:41.125117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3261 03:27:41.170658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3262 03:27:41.171449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3264 03:27:41.216669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3265 03:27:41.217450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3267 03:27:41.266960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3268 03:27:41.267746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3270 03:27:41.313247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3271 03:27:41.314099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3273 03:27:41.357656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3274 03:27:41.358448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3276 03:27:41.416262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3277 03:27:41.417144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3279 03:27:41.463375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3280 03:27:41.464148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3282 03:27:41.514562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3283 03:27:41.515364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3285 03:27:41.561703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3286 03:27:41.562514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3288 03:27:41.616464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3289 03:27:41.617283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3291 03:27:41.664185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3292 03:27:41.664971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3294 03:27:41.713360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3295 03:27:41.714137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3297 03:27:41.765123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3298 03:27:41.765952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3300 03:27:41.816265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3301 03:27:41.817086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3303 03:27:41.866208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3304 03:27:41.866987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3306 03:27:41.915776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3307 03:27:41.916591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3309 03:27:41.980063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3310 03:27:41.980848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3312 03:27:42.024960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3313 03:27:42.025724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3315 03:27:42.083355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3316 03:27:42.084200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3318 03:27:42.139913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3319 03:27:42.140767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3321 03:27:42.193437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3322 03:27:42.194209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3324 03:27:42.237114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3325 03:27:42.237880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3327 03:27:42.283457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3328 03:27:42.284307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3330 03:27:42.337698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3331 03:27:42.338552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3333 03:27:42.383066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3334 03:27:42.383857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3336 03:27:42.435233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3337 03:27:42.436124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3339 03:27:42.493685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3340 03:27:42.494482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3342 03:27:42.537990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3343 03:27:42.538802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3345 03:27:42.595206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3346 03:27:42.596049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3348 03:27:42.648442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3349 03:27:42.649221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3351 03:27:42.708091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3352 03:27:42.708865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3354 03:27:42.768092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3355 03:27:42.768890 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3357 03:27:42.829016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3358 03:27:42.829783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3360 03:27:42.887694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3361 03:27:42.888511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3363 03:27:42.939363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3364 03:27:42.940151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3366 03:27:42.982662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3367 03:27:42.983425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3369 03:27:43.027227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3370 03:27:43.028034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3372 03:27:43.089327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3373 03:27:43.090145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3375 03:27:43.134949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3376 03:27:43.135737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3378 03:27:43.177860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3379 03:27:43.178622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3381 03:27:43.222223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3382 03:27:43.222975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3384 03:27:43.266513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3385 03:27:43.267361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3387 03:27:43.307880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3388 03:27:43.308735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3390 03:27:43.349770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3391 03:27:43.350561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3393 03:27:43.402352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3394 03:27:43.403217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3396 03:27:43.457621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3397 03:27:43.458424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3399 03:27:43.509108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3400 03:27:43.509933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3402 03:27:43.560956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3403 03:27:43.561752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3405 03:27:43.610279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3406 03:27:43.611087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3408 03:27:43.657021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3409 03:27:43.657818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3411 03:27:43.710065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3412 03:27:43.710866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3414 03:27:43.753243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3415 03:27:43.754023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3417 03:27:43.809622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3418 03:27:43.810420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3420 03:27:43.854812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3421 03:27:43.855591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3423 03:27:43.909316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3424 03:27:43.910099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3426 03:27:43.965222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3427 03:27:43.966001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3429 03:27:44.016714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3430 03:27:44.017480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3432 03:27:44.067081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3433 03:27:44.067923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3435 03:27:44.120982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3436 03:27:44.121878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3438 03:27:44.164369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3439 03:27:44.165304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3441 03:27:44.219052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3442 03:27:44.219870 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3444 03:27:44.269778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3445 03:27:44.270621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3447 03:27:44.329785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3448 03:27:44.330656 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3450 03:27:44.383598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3451 03:27:44.384467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3453 03:27:44.428042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3454 03:27:44.428968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3456 03:27:44.472484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3457 03:27:44.473297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3459 03:27:44.516107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3460 03:27:44.516970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3462 03:27:44.562557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3463 03:27:44.563381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3465 03:27:44.619328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3466 03:27:44.620143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3468 03:27:44.671877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3469 03:27:44.672734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3471 03:27:44.725426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3472 03:27:44.726263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3474 03:27:44.777420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3475 03:27:44.778226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3477 03:27:44.836896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3478 03:27:44.837806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3480 03:27:44.889149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3481 03:27:44.889946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3483 03:27:44.934016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3484 03:27:44.934796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3486 03:27:44.986024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3487 03:27:44.986785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3489 03:27:45.045974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3490 03:27:45.046760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3492 03:27:45.098258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3493 03:27:45.099169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3495 03:27:45.141860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3496 03:27:45.142682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3498 03:27:45.196972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3499 03:27:45.197776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3501 03:27:45.248492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3502 03:27:45.249286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3504 03:27:45.291548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3505 03:27:45.292388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3507 03:27:45.337454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3508 03:27:45.338252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3510 03:27:45.392346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3511 03:27:45.393112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3513 03:27:45.441064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3514 03:27:45.441932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3516 03:27:45.497312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3517 03:27:45.498109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3519 03:27:45.542524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3520 03:27:45.543306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3522 03:27:45.592192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3523 03:27:45.593046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3525 03:27:45.644960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3526 03:27:45.645735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3528 03:27:45.695202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3529 03:27:45.695971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3531 03:27:45.744401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3532 03:27:45.745147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3534 03:27:45.787737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3535 03:27:45.788526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3537 03:27:45.840913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3538 03:27:45.841704 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3540 03:27:45.896030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3541 03:27:45.896809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3543 03:27:45.947891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3544 03:27:45.948687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3546 03:27:45.995480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3547 03:27:45.996274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3549 03:27:46.039209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3550 03:27:46.040005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3552 03:27:46.096879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3553 03:27:46.097703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3555 03:27:46.142694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3556 03:27:46.143482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3558 03:27:46.196216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3559 03:27:46.196991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3561 03:27:46.249990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3562 03:27:46.250762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3564 03:27:46.292705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3565 03:27:46.293510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3567 03:27:46.344804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3568 03:27:46.345628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3570 03:27:46.395714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3571 03:27:46.396556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3573 03:27:46.454286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3574 03:27:46.455176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3576 03:27:46.503174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3577 03:27:46.504046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3579 03:27:46.580442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3580 03:27:46.581233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3582 03:27:46.632611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3583 03:27:46.633385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3585 03:27:46.684872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3586 03:27:46.685683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3588 03:27:46.743238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3589 03:27:46.744051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3591 03:27:46.787633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3592 03:27:46.788458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3594 03:27:46.837977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3595 03:27:46.838762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3597 03:27:46.882725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3598 03:27:46.883612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3600 03:27:46.928297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3601 03:27:46.929087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3603 03:27:46.987658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3604 03:27:46.988481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3606 03:27:47.038856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3607 03:27:47.039641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3609 03:27:47.086696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3610 03:27:47.087534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3612 03:27:47.144884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3613 03:27:47.145680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3615 03:27:47.197763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3616 03:27:47.198533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3618 03:27:47.239814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3619 03:27:47.240655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3621 03:27:47.290131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3622 03:27:47.290935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3624 03:27:47.337430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3625 03:27:47.338232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3627 03:27:47.381543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3628 03:27:47.382300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3630 03:27:47.428974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3631 03:27:47.429848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3633 03:27:47.484847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3634 03:27:47.485672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3636 03:27:47.527725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3637 03:27:47.528586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3639 03:27:47.579449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3640 03:27:47.580269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3642 03:27:47.623763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3643 03:27:47.624595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3645 03:27:47.670030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3646 03:27:47.670830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3648 03:27:47.714653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3649 03:27:47.715434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3651 03:27:47.760250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3652 03:27:47.761040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3654 03:27:47.806751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3655 03:27:47.807509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3657 03:27:47.851407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3658 03:27:47.852179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3660 03:27:47.901316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3661 03:27:47.902093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3663 03:27:47.948548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3664 03:27:47.949340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3666 03:27:48.002500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3667 03:27:48.003287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3669 03:27:48.045583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3670 03:27:48.046345 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3672 03:27:48.097111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3673 03:27:48.097911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3675 03:27:48.148572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3676 03:27:48.149328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3678 03:27:48.191789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3679 03:27:48.192618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3681 03:27:48.244361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3682 03:27:48.245153 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3684 03:27:48.286818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3685 03:27:48.287655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3687 03:27:48.348778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3688 03:27:48.349628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3690 03:27:48.390978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3691 03:27:48.391784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3693 03:27:48.440215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3694 03:27:48.441090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3696 03:27:48.485253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3697 03:27:48.486061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3699 03:27:48.532072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3700 03:27:48.532949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3702 03:27:48.576312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3703 03:27:48.577187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3705 03:27:48.631666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3706 03:27:48.632611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3708 03:27:48.683034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3709 03:27:48.683904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3711 03:27:48.739794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3712 03:27:48.740661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3714 03:27:48.786545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3715 03:27:48.787361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3717 03:27:48.837741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3718 03:27:48.838523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3720 03:27:48.892559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3721 03:27:48.893310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3723 03:27:48.947834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3724 03:27:48.948620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3726 03:27:49.000346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3727 03:27:49.001113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3729 03:27:49.048556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3730 03:27:49.049314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3732 03:27:49.099128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3733 03:27:49.099884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3735 03:27:49.145203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3736 03:27:49.145986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3738 03:27:49.197365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3739 03:27:49.198153 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3741 03:27:49.241699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3742 03:27:49.242457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3744 03:27:49.291194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3745 03:27:49.292060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3747 03:27:49.343849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3748 03:27:49.344708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3750 03:27:49.397198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3751 03:27:49.397975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3753 03:27:49.447211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3754 03:27:49.448008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3756 03:27:49.494432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3757 03:27:49.495239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3759 03:27:49.548107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3760 03:27:49.548932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3762 03:27:49.598728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3763 03:27:49.599508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3765 03:27:49.650523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3766 03:27:49.651317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3768 03:27:49.699531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3769 03:27:49.700320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3771 03:27:49.752617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3772 03:27:49.753378 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3774 03:27:49.808328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3775 03:27:49.809141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3777 03:27:49.860605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3778 03:27:49.861436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3780 03:27:49.917428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3781 03:27:49.918182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3783 03:27:49.966283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3784 03:27:49.967047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3786 03:27:50.025696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3787 03:27:50.026537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3789 03:27:50.077613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3790 03:27:50.078420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3792 03:27:50.130517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3793 03:27:50.131328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3795 03:27:50.175494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3796 03:27:50.176317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3798 03:27:50.229397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3799 03:27:50.230192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3801 03:27:50.282666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3802 03:27:50.283467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3804 03:27:50.338019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3805 03:27:50.338817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3807 03:27:50.392468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3808 03:27:50.393257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3810 03:27:50.445438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3811 03:27:50.446239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3813 03:27:50.502517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3814 03:27:50.503330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3816 03:27:50.547699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3817 03:27:50.548520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3819 03:27:50.596504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3820 03:27:50.597273 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3822 03:27:50.640827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3823 03:27:50.641576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3825 03:27:50.693876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3826 03:27:50.694628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3828 03:27:50.752494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3829 03:27:50.753253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3831 03:27:50.796807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3832 03:27:50.797551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3834 03:27:50.850144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3835 03:27:50.850902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3837 03:27:50.900073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3838 03:27:50.900822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3840 03:27:50.950682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3841 03:27:50.951425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3843 03:27:51.001942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3844 03:27:51.002715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3846 03:27:51.047235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3847 03:27:51.048032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3849 03:27:51.090729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3850 03:27:51.091504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3852 03:27:51.133978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3853 03:27:51.134713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3855 03:27:51.199642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3856 03:27:51.200426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3858 03:27:51.248891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3859 03:27:51.249636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3861 03:27:51.297274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3862 03:27:51.298022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3864 03:27:51.356590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3865 03:27:51.357344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3867 03:27:51.401030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3868 03:27:51.401791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3870 03:27:51.451826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3871 03:27:51.452625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3873 03:27:51.510540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3874 03:27:51.511331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3876 03:27:51.562077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3877 03:27:51.562893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3879 03:27:51.609390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3880 03:27:51.610181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3882 03:27:51.660191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3883 03:27:51.660970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3885 03:27:51.708796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3886 03:27:51.709567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3888 03:27:51.765837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3889 03:27:51.766594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3891 03:27:51.812027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3892 03:27:51.812778 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3894 03:27:51.868915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3895 03:27:51.869714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3897 03:27:51.919830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3898 03:27:51.920674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3900 03:27:51.970227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3901 03:27:51.971020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3903 03:27:52.022344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3904 03:27:52.023181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3906 03:27:52.069573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3907 03:27:52.070390 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3909 03:27:52.129008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3910 03:27:52.129853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3912 03:27:52.173289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3913 03:27:52.174095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3915 03:27:52.215667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3916 03:27:52.216514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3918 03:27:52.271627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3919 03:27:52.272505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3921 03:27:52.326349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3922 03:27:52.327151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3924 03:27:52.375194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3925 03:27:52.376027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3927 03:27:52.427968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3928 03:27:52.428799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3930 03:27:52.480323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3931 03:27:52.481148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3933 03:27:52.530202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3934 03:27:52.531009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3936 03:27:52.573864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3937 03:27:52.574674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3939 03:27:52.625218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3940 03:27:52.626014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3942 03:27:52.681245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3943 03:27:52.682003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3945 03:27:52.743751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3946 03:27:52.744583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3948 03:27:52.787923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3949 03:27:52.788738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3951 03:27:52.839257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3952 03:27:52.840030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3954 03:27:52.891590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3955 03:27:52.892373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3957 03:27:52.944970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3958 03:27:52.945712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3960 03:27:52.996243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3961 03:27:52.996991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3963 03:27:53.047674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3964 03:27:53.048497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3966 03:27:53.115187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3967 03:27:53.115945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3969 03:27:53.164568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3970 03:27:53.165363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3972 03:27:53.219385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3973 03:27:53.220152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3975 03:27:53.266894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3976 03:27:53.267687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3978 03:27:53.310471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3979 03:27:53.311236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3981 03:27:53.366070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3982 03:27:53.366809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3984 03:27:53.423404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3985 03:27:53.424172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3987 03:27:53.469304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3988 03:27:53.470036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3990 03:27:53.521874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3991 03:27:53.522651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3993 03:27:53.572847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3994 03:27:53.573625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3996 03:27:53.617091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3997 03:27:53.617840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3999 03:27:53.669078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
4000 03:27:53.669827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
4002 03:27:53.732977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
4003 03:27:53.733742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
4005 03:27:53.784690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
4006 03:27:53.785440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
4008 03:27:53.837651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
4009 03:27:53.838402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
4011 03:27:53.882688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
4012 03:27:53.883439 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
4014 03:27:53.934119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
4015 03:27:53.934882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
4017 03:27:53.979963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
4018 03:27:53.980743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
4020 03:27:54.031532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
4021 03:27:54.032387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
4023 03:27:54.084774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
4024 03:27:54.085552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
4026 03:27:54.134819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
4027 03:27:54.135589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
4029 03:27:54.178948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
4030 03:27:54.179691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
4032 03:27:54.240682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
4033 03:27:54.241453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
4035 03:27:54.292081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
4036 03:27:54.292841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
4038 03:27:54.339160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
4039 03:27:54.339892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
4041 03:27:54.392363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
4042 03:27:54.393127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
4044 03:27:54.441581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
4045 03:27:54.442355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
4047 03:27:54.488137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
4048 03:27:54.488971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
4050 03:27:54.539727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
4051 03:27:54.540575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
4053 03:27:54.597476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
4054 03:27:54.598306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
4056 03:27:54.642252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
4057 03:27:54.643043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
4059 03:27:54.697551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
4060 03:27:54.698361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
4062 03:27:54.745513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
4063 03:27:54.746285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
4065 03:27:54.791567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
4066 03:27:54.792384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
4068 03:27:54.845989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
4069 03:27:54.846757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
4071 03:27:54.897737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
4072 03:27:54.898503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
4074 03:27:54.943700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
4075 03:27:54.944482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
4077 03:27:54.992675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
4078 03:27:54.993402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
4080 03:27:55.037305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
4081 03:27:55.038083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
4083 03:27:55.081288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
4084 03:27:55.082007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
4086 03:27:55.132251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
4087 03:27:55.133000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
4089 03:27:55.178167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
4090 03:27:55.178922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
4092 03:27:55.227768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
4093 03:27:55.228639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
4095 03:27:55.271909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
4096 03:27:55.272683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
4098 03:27:55.330715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
4099 03:27:55.331478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
4101 03:27:55.373220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
4102 03:27:55.373975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
4104 03:27:55.425443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
4105 03:27:55.426208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
4107 03:27:55.477664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
4108 03:27:55.478406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
4110 03:27:55.530378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
4111 03:27:55.531175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
4113 03:27:55.577902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
4114 03:27:55.578682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
4116 03:27:55.623946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
4117 03:27:55.624732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
4119 03:27:55.677856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
4120 03:27:55.678598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
4122 03:27:55.722400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
4123 03:27:55.723152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
4125 03:27:55.769031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
4126 03:27:55.769779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
4128 03:27:55.828241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
4129 03:27:55.828997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
4131 03:27:55.884511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
4132 03:27:55.885272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
4134 03:27:55.931966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
4135 03:27:55.932749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
4137 03:27:55.984907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
4138 03:27:55.985685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
4140 03:27:56.032025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
4141 03:27:56.032841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
4143 03:27:56.084721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
4144 03:27:56.085508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4146 03:27:56.136225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4147 03:27:56.137022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4149 03:27:56.188893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4150 03:27:56.189633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4152 03:27:56.234071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4153 03:27:56.234795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4155 03:27:56.282818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4156 03:27:56.283562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4158 03:27:56.339676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4159 03:27:56.340457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4161 03:27:56.384947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4162 03:27:56.385698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4164 03:27:56.445343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4165 03:27:56.446109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4167 03:27:56.495703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4168 03:27:56.496481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4170 03:27:56.542939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4171 03:27:56.543720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4173 03:27:56.595422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4174 03:27:56.596194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4176 03:27:56.643337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4177 03:27:56.644094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4179 03:27:56.687138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4180 03:27:56.687886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4182 03:27:56.740765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4183 03:27:56.741531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4185 03:27:56.793881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4186 03:27:56.794640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4188 03:27:56.848008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4189 03:27:56.848779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4191 03:27:56.902987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4192 03:27:56.903755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4194 03:27:56.954025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4195 03:27:56.954801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4197 03:27:57.005074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4198 03:27:57.005866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4200 03:27:57.052621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4201 03:27:57.053389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4203 03:27:57.107541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4204 03:27:57.108378 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4206 03:27:57.163564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4207 03:27:57.164372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4209 03:27:57.214543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4210 03:27:57.215314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4212 03:27:57.268280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4213 03:27:57.269048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4215 03:27:57.322686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4216 03:27:57.323453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4218 03:27:57.391074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4219 03:27:57.391854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4221 03:27:57.445073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4222 03:27:57.445845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4224 03:27:57.500820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4225 03:27:57.501612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4227 03:27:57.550286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4228 03:27:57.551085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4230 03:27:57.596411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4231 03:27:57.597196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4233 03:27:57.647222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4234 03:27:57.648019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4236 03:27:57.701258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4237 03:27:57.702035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4239 03:27:57.747755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4240 03:27:57.748566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4242 03:27:57.802011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4243 03:27:57.802765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4245 03:27:57.848297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4246 03:27:57.849044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4248 03:27:57.907494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4249 03:27:57.908271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4251 03:27:57.952449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4252 03:27:57.953203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4254 03:27:58.004014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4255 03:27:58.004774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4257 03:27:58.058218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4258 03:27:58.058976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4260 03:27:58.105714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4261 03:27:58.106483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4263 03:27:58.150255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4264 03:27:58.151001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4266 03:27:58.201326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4267 03:27:58.202073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4269 03:27:58.259501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4270 03:27:58.260364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4272 03:27:58.308710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4273 03:27:58.309456 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4275 03:27:58.355580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4276 03:27:58.356350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4278 03:27:58.403035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4279 03:27:58.403791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4281 03:27:58.450429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4282 03:27:58.451189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4284 03:27:58.513919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4285 03:27:58.514770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4287 03:27:58.557813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4288 03:27:58.558600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4290 03:27:58.609042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4291 03:27:58.609813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4293 03:27:58.663302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4294 03:27:58.664067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4296 03:27:58.710436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4297 03:27:58.711187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4299 03:27:58.766885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4300 03:27:58.767629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4302 03:27:58.818907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4303 03:27:58.819649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4305 03:27:58.865183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4306 03:27:58.865958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4308 03:27:58.912462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4309 03:27:58.913241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4311 03:27:58.963347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4312 03:27:58.964271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4314 03:27:59.021143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4315 03:27:59.021957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4317 03:27:59.074791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4318 03:27:59.075586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4320 03:27:59.128855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4321 03:27:59.129648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4323 03:27:59.181099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4324 03:27:59.182026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4326 03:27:59.230826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4327 03:27:59.231618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4329 03:27:59.275616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4330 03:27:59.276469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4332 03:27:59.320817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4333 03:27:59.321596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4335 03:27:59.374062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4336 03:27:59.374840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4338 03:27:59.430890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4339 03:27:59.431677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4341 03:27:59.484883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4342 03:27:59.485768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4344 03:27:59.540650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4345 03:27:59.541297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4347 03:27:59.586364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4348 03:27:59.586966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4350 03:27:59.650236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4351 03:27:59.650997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4353 03:27:59.698834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4355 03:27:59.701888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4356 03:27:59.755422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4357 03:27:59.756309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4359 03:27:59.808900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4360 03:27:59.809658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4362 03:27:59.860243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4363 03:27:59.860994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4365 03:27:59.916263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4366 03:27:59.917072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4368 03:27:59.973498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4369 03:27:59.974243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4371 03:28:00.027591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4372 03:28:00.028420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4374 03:28:00.078938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4375 03:28:00.079667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4377 03:28:00.124791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4378 03:28:00.125534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4380 03:28:00.176936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4381 03:28:00.177653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4383 03:28:00.223541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4384 03:28:00.224435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4386 03:28:00.282742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4387 03:28:00.283561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4389 03:28:00.336535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4390 03:28:00.337349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4392 03:28:00.381559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4393 03:28:00.382371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4395 03:28:00.432998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4396 03:28:00.433813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4398 03:28:00.477888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4399 03:28:00.478667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4401 03:28:00.528476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4402 03:28:00.529101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4404 03:28:00.589022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4405 03:28:00.589618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4407 03:28:00.640813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4408 03:28:00.641589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4410 03:28:00.698238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4411 03:28:00.698987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4413 03:28:00.749401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4414 03:28:00.750146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4416 03:28:00.805291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4417 03:28:00.806024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4419 03:28:00.851148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4420 03:28:00.851883 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4422 03:28:00.903035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4423 03:28:00.903768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4425 03:28:00.957043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4426 03:28:00.957787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4428 03:28:01.011549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4429 03:28:01.012354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4431 03:28:01.072731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4432 03:28:01.073561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4434 03:28:01.118220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4435 03:28:01.118810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4437 03:28:01.165644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4438 03:28:01.166254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4440 03:28:01.216603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4441 03:28:01.217209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4443 03:28:01.264797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4444 03:28:01.265374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4446 03:28:01.311322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4447 03:28:01.311921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4449 03:28:01.366920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4450 03:28:01.367502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4452 03:28:01.423440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4453 03:28:01.424081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4455 03:28:01.469051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4456 03:28:01.469654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4458 03:28:01.522510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4459 03:28:01.523451 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4461 03:28:01.566010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4462 03:28:01.566833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4464 03:28:01.610711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4465 03:28:01.611487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4467 03:28:01.662039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4468 03:28:01.662803 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4470 03:28:01.712550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4471 03:28:01.713309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4473 03:28:01.757420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4474 03:28:01.758184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4476 03:28:01.811233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4477 03:28:01.812014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4479 03:28:01.862194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4480 03:28:01.862963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4482 03:28:01.911891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4483 03:28:01.912677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4485 03:28:01.970919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4486 03:28:01.971677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4488 03:28:02.028465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4489 03:28:02.029290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4491 03:28:02.087869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4492 03:28:02.088716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4494 03:28:02.131554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4495 03:28:02.132355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4497 03:28:02.182853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4498 03:28:02.183634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4500 03:28:02.223188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4501 03:28:02.223941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4503 03:28:02.274018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4504 03:28:02.274771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4506 03:28:02.327922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4507 03:28:02.328723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4509 03:28:02.377931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4511 03:28:02.383227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4512 03:28:02.383709 + set +x
4513 03:28:02.389121 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 950284_1.6.2.4.5>
4514 03:28:02.389594 <LAVA_TEST_RUNNER EXIT>
4515 03:28:02.390254 Received signal: <ENDRUN> 1_kselftest-alsa 950284_1.6.2.4.5
4516 03:28:02.390704 Ending use of test pattern.
4517 03:28:02.391105 Ending test lava.1_kselftest-alsa (950284_1.6.2.4.5), duration 39.36
4519 03:28:02.392637 ok: lava_test_shell seems to have completed
4520 03:28:02.415210 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4521 03:28:02.416991 end: 3.1 lava-test-shell (duration 00:00:40) [common]
4522 03:28:02.417583 end: 3 lava-test-retry (duration 00:00:40) [common]
4523 03:28:02.418141 start: 4 finalize (timeout 00:06:06) [common]
4524 03:28:02.418707 start: 4.1 power-off (timeout 00:00:30) [common]
4525 03:28:02.419662 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4526 03:28:02.455132 >> OK - accepted request
4527 03:28:02.457365 Returned 0 in 0 seconds
4528 03:28:02.558510 end: 4.1 power-off (duration 00:00:00) [common]
4530 03:28:02.560238 start: 4.2 read-feedback (timeout 00:06:05) [common]
4531 03:28:02.561337 Listened to connection for namespace 'common' for up to 1s
4532 03:28:03.562148 Finalising connection for namespace 'common'
4533 03:28:03.562907 Disconnecting from shell: Finalise
4534 03:28:03.563436 / #
4535 03:28:03.664523 end: 4.2 read-feedback (duration 00:00:01) [common]
4536 03:28:03.665225 end: 4 finalize (duration 00:00:01) [common]
4537 03:28:03.665905 Cleaning after the job
4538 03:28:03.666516 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/ramdisk
4539 03:28:03.680463 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/kernel
4540 03:28:03.718338 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/dtb
4541 03:28:03.719133 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/nfsrootfs
4542 03:28:03.880432 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950284/tftp-deploy-2vebo3i3/modules
4543 03:28:03.902434 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950284
4544 03:28:07.254166 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950284
4545 03:28:07.254742 Job finished correctly