Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 03:10:07.206934 lava-dispatcher, installed at version: 2024.01
2 03:10:07.207737 start: 0 validate
3 03:10:07.208244 Start time: 2024-11-07 03:10:07.208214+00:00 (UTC)
4 03:10:07.208786 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:10:07.209329 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 03:10:07.250075 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:10:07.250615 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 03:10:07.280119 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:10:07.280735 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 03:10:07.311375 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:10:07.311892 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 03:10:07.343062 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 03:10:07.343918 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
14 03:10:07.380349 validate duration: 0.17
16 03:10:07.381205 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 03:10:07.381522 start: 1.1 download-retry (timeout 00:10:00) [common]
18 03:10:07.381830 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 03:10:07.382476 Not decompressing ramdisk as can be used compressed.
20 03:10:07.382949 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 03:10:07.383228 saving as /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/ramdisk/initrd.cpio.gz
22 03:10:07.383491 total size: 5628140 (5 MB)
23 03:10:07.419455 progress 0 % (0 MB)
24 03:10:07.423727 progress 5 % (0 MB)
25 03:10:07.428100 progress 10 % (0 MB)
26 03:10:07.431823 progress 15 % (0 MB)
27 03:10:07.435943 progress 20 % (1 MB)
28 03:10:07.439603 progress 25 % (1 MB)
29 03:10:07.443730 progress 30 % (1 MB)
30 03:10:07.447864 progress 35 % (1 MB)
31 03:10:07.451477 progress 40 % (2 MB)
32 03:10:07.455574 progress 45 % (2 MB)
33 03:10:07.459288 progress 50 % (2 MB)
34 03:10:07.463349 progress 55 % (2 MB)
35 03:10:07.467483 progress 60 % (3 MB)
36 03:10:07.471080 progress 65 % (3 MB)
37 03:10:07.475111 progress 70 % (3 MB)
38 03:10:07.478727 progress 75 % (4 MB)
39 03:10:07.482746 progress 80 % (4 MB)
40 03:10:07.486340 progress 85 % (4 MB)
41 03:10:07.490295 progress 90 % (4 MB)
42 03:10:07.494221 progress 95 % (5 MB)
43 03:10:07.497539 progress 100 % (5 MB)
44 03:10:07.498217 5 MB downloaded in 0.11 s (46.79 MB/s)
45 03:10:07.498776 end: 1.1.1 http-download (duration 00:00:00) [common]
47 03:10:07.499674 end: 1.1 download-retry (duration 00:00:00) [common]
48 03:10:07.499974 start: 1.2 download-retry (timeout 00:10:00) [common]
49 03:10:07.500282 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 03:10:07.500766 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/clang-15/kernel/Image
51 03:10:07.501025 saving as /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/kernel/Image
52 03:10:07.501240 total size: 37878272 (36 MB)
53 03:10:07.501454 No compression specified
54 03:10:07.533926 progress 0 % (0 MB)
55 03:10:07.557309 progress 5 % (1 MB)
56 03:10:07.580559 progress 10 % (3 MB)
57 03:10:07.604025 progress 15 % (5 MB)
58 03:10:07.627115 progress 20 % (7 MB)
59 03:10:07.649886 progress 25 % (9 MB)
60 03:10:07.672991 progress 30 % (10 MB)
61 03:10:07.696409 progress 35 % (12 MB)
62 03:10:07.719674 progress 40 % (14 MB)
63 03:10:07.742750 progress 45 % (16 MB)
64 03:10:07.765375 progress 50 % (18 MB)
65 03:10:07.788730 progress 55 % (19 MB)
66 03:10:07.811658 progress 60 % (21 MB)
67 03:10:07.834603 progress 65 % (23 MB)
68 03:10:07.857645 progress 70 % (25 MB)
69 03:10:07.880234 progress 75 % (27 MB)
70 03:10:07.903602 progress 80 % (28 MB)
71 03:10:07.926577 progress 85 % (30 MB)
72 03:10:07.949645 progress 90 % (32 MB)
73 03:10:07.972486 progress 95 % (34 MB)
74 03:10:07.994830 progress 100 % (36 MB)
75 03:10:07.995580 36 MB downloaded in 0.49 s (73.08 MB/s)
76 03:10:07.996096 end: 1.2.1 http-download (duration 00:00:00) [common]
78 03:10:07.996939 end: 1.2 download-retry (duration 00:00:00) [common]
79 03:10:07.997216 start: 1.3 download-retry (timeout 00:09:59) [common]
80 03:10:07.997485 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 03:10:07.997951 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 03:10:07.998229 saving as /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/dtb/meson-g12b-a311d-libretech-cc.dtb
83 03:10:07.998443 total size: 54703 (0 MB)
84 03:10:07.998655 No compression specified
85 03:10:08.038063 progress 59 % (0 MB)
86 03:10:08.038919 progress 100 % (0 MB)
87 03:10:08.039474 0 MB downloaded in 0.04 s (1.27 MB/s)
88 03:10:08.039963 end: 1.3.1 http-download (duration 00:00:00) [common]
90 03:10:08.040826 end: 1.3 download-retry (duration 00:00:00) [common]
91 03:10:08.041092 start: 1.4 download-retry (timeout 00:09:59) [common]
92 03:10:08.041357 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 03:10:08.041820 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 03:10:08.042085 saving as /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/nfsrootfs/full.rootfs.tar
95 03:10:08.042294 total size: 474398908 (452 MB)
96 03:10:08.042508 Using unxz to decompress xz
97 03:10:08.074784 progress 0 % (0 MB)
98 03:10:09.163584 progress 5 % (22 MB)
99 03:10:10.611482 progress 10 % (45 MB)
100 03:10:11.055445 progress 15 % (67 MB)
101 03:10:11.856824 progress 20 % (90 MB)
102 03:10:12.402643 progress 25 % (113 MB)
103 03:10:12.761026 progress 30 % (135 MB)
104 03:10:13.381295 progress 35 % (158 MB)
105 03:10:14.256842 progress 40 % (181 MB)
106 03:10:15.095046 progress 45 % (203 MB)
107 03:10:15.723441 progress 50 % (226 MB)
108 03:10:16.366862 progress 55 % (248 MB)
109 03:10:17.592245 progress 60 % (271 MB)
110 03:10:19.061648 progress 65 % (294 MB)
111 03:10:20.737445 progress 70 % (316 MB)
112 03:10:23.983013 progress 75 % (339 MB)
113 03:10:26.447532 progress 80 % (361 MB)
114 03:10:29.503155 progress 85 % (384 MB)
115 03:10:32.692053 progress 90 % (407 MB)
116 03:10:35.940661 progress 95 % (429 MB)
117 03:10:39.090282 progress 100 % (452 MB)
118 03:10:39.103171 452 MB downloaded in 31.06 s (14.57 MB/s)
119 03:10:39.104166 end: 1.4.1 http-download (duration 00:00:31) [common]
121 03:10:39.105955 end: 1.4 download-retry (duration 00:00:31) [common]
122 03:10:39.106524 start: 1.5 download-retry (timeout 00:09:28) [common]
123 03:10:39.107097 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 03:10:39.108392 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/clang-15/modules.tar.xz
125 03:10:39.108936 saving as /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/modules/modules.tar
126 03:10:39.109391 total size: 11778608 (11 MB)
127 03:10:39.109853 Using unxz to decompress xz
128 03:10:39.163065 progress 0 % (0 MB)
129 03:10:39.232118 progress 5 % (0 MB)
130 03:10:39.306923 progress 10 % (1 MB)
131 03:10:39.401891 progress 15 % (1 MB)
132 03:10:39.497859 progress 20 % (2 MB)
133 03:10:39.577845 progress 25 % (2 MB)
134 03:10:39.654239 progress 30 % (3 MB)
135 03:10:39.734243 progress 35 % (3 MB)
136 03:10:39.813761 progress 40 % (4 MB)
137 03:10:39.890221 progress 45 % (5 MB)
138 03:10:39.975186 progress 50 % (5 MB)
139 03:10:40.058847 progress 55 % (6 MB)
140 03:10:40.144108 progress 60 % (6 MB)
141 03:10:40.226784 progress 65 % (7 MB)
142 03:10:40.309070 progress 70 % (7 MB)
143 03:10:40.392747 progress 75 % (8 MB)
144 03:10:40.477285 progress 80 % (9 MB)
145 03:10:40.558492 progress 85 % (9 MB)
146 03:10:40.642385 progress 90 % (10 MB)
147 03:10:40.721620 progress 95 % (10 MB)
148 03:10:40.798892 progress 100 % (11 MB)
149 03:10:40.810860 11 MB downloaded in 1.70 s (6.60 MB/s)
150 03:10:40.811480 end: 1.5.1 http-download (duration 00:00:02) [common]
152 03:10:40.812707 end: 1.5 download-retry (duration 00:00:02) [common]
153 03:10:40.813240 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 03:10:40.813760 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 03:10:56.787082 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/950252/extract-nfsrootfs-gw_j8b5f
156 03:10:56.787665 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 03:10:56.787956 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 03:10:56.788585 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v
159 03:10:56.789015 makedir: /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin
160 03:10:56.789349 makedir: /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/tests
161 03:10:56.789684 makedir: /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/results
162 03:10:56.790032 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-add-keys
163 03:10:56.790564 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-add-sources
164 03:10:56.791090 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-background-process-start
165 03:10:56.791613 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-background-process-stop
166 03:10:56.792302 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-common-functions
167 03:10:56.792903 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-echo-ipv4
168 03:10:56.793561 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-install-packages
169 03:10:56.794120 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-installed-packages
170 03:10:56.794626 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-os-build
171 03:10:56.795115 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-probe-channel
172 03:10:56.795604 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-probe-ip
173 03:10:56.796112 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-target-ip
174 03:10:56.796610 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-target-mac
175 03:10:56.797102 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-target-storage
176 03:10:56.797599 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-test-case
177 03:10:56.798116 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-test-event
178 03:10:56.798605 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-test-feedback
179 03:10:56.799107 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-test-raise
180 03:10:56.799590 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-test-reference
181 03:10:56.800115 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-test-runner
182 03:10:56.800638 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-test-set
183 03:10:56.801126 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-test-shell
184 03:10:56.801616 Updating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-install-packages (oe)
185 03:10:56.802160 Updating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/bin/lava-installed-packages (oe)
186 03:10:56.802609 Creating /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/environment
187 03:10:56.802997 LAVA metadata
188 03:10:56.803260 - LAVA_JOB_ID=950252
189 03:10:56.803477 - LAVA_DISPATCHER_IP=192.168.6.2
190 03:10:56.803877 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 03:10:56.804894 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 03:10:56.805215 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 03:10:56.805425 skipped lava-vland-overlay
194 03:10:56.805670 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 03:10:56.805926 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 03:10:56.806147 skipped lava-multinode-overlay
197 03:10:56.806393 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 03:10:56.806643 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 03:10:56.806891 Loading test definitions
200 03:10:56.807172 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 03:10:56.807397 Using /lava-950252 at stage 0
202 03:10:56.808817 uuid=950252_1.6.2.4.1 testdef=None
203 03:10:56.809144 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 03:10:56.809411 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 03:10:56.811194 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 03:10:56.812029 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 03:10:56.814333 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 03:10:56.815191 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 03:10:56.817442 runner path: /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 950252_1.6.2.4.1
212 03:10:56.818042 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 03:10:56.818813 Creating lava-test-runner.conf files
215 03:10:56.819019 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950252/lava-overlay-ajiqdx5v/lava-950252/0 for stage 0
216 03:10:56.819360 - 0_v4l2-decoder-conformance-h265
217 03:10:56.819709 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 03:10:56.820014 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 03:10:56.841912 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 03:10:56.842343 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 03:10:56.842612 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 03:10:56.842909 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 03:10:56.843212 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 03:10:57.505666 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 03:10:57.506146 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 03:10:57.506397 extracting modules file /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950252/extract-nfsrootfs-gw_j8b5f
227 03:10:58.897644 extracting modules file /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950252/extract-overlay-ramdisk-9l1d7ixf/ramdisk
228 03:11:00.306414 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 03:11:00.306904 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 03:11:00.307180 [common] Applying overlay to NFS
231 03:11:00.307395 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950252/compress-overlay-yd20t4xf/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950252/extract-nfsrootfs-gw_j8b5f
232 03:11:00.336499 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 03:11:00.336916 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 03:11:00.337187 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 03:11:00.337417 Converting downloaded kernel to a uImage
236 03:11:00.337742 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/kernel/Image /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/kernel/uImage
237 03:11:00.843657 output: Image Name:
238 03:11:00.844118 output: Created: Thu Nov 7 03:11:00 2024
239 03:11:00.844340 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 03:11:00.844549 output: Data Size: 37878272 Bytes = 36990.50 KiB = 36.12 MiB
241 03:11:00.844754 output: Load Address: 01080000
242 03:11:00.844957 output: Entry Point: 01080000
243 03:11:00.845172 output:
244 03:11:00.845529 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 03:11:00.845805 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 03:11:00.846074 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 03:11:00.846336 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 03:11:00.846627 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 03:11:00.846898 Building ramdisk /var/lib/lava/dispatcher/tmp/950252/extract-overlay-ramdisk-9l1d7ixf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950252/extract-overlay-ramdisk-9l1d7ixf/ramdisk
250 03:11:03.390285 >> 173435 blocks
251 03:11:11.045620 Adding RAMdisk u-boot header.
252 03:11:11.046292 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950252/extract-overlay-ramdisk-9l1d7ixf/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950252/extract-overlay-ramdisk-9l1d7ixf/ramdisk.cpio.gz.uboot
253 03:11:11.304739 output: Image Name:
254 03:11:11.305167 output: Created: Thu Nov 7 03:11:11 2024
255 03:11:11.305384 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 03:11:11.305595 output: Data Size: 24147163 Bytes = 23581.21 KiB = 23.03 MiB
257 03:11:11.305799 output: Load Address: 00000000
258 03:11:11.305999 output: Entry Point: 00000000
259 03:11:11.306201 output:
260 03:11:11.306788 rename /var/lib/lava/dispatcher/tmp/950252/extract-overlay-ramdisk-9l1d7ixf/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/ramdisk/ramdisk.cpio.gz.uboot
261 03:11:11.307206 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 03:11:11.307497 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 03:11:11.307797 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 03:11:11.308174 No LXC device requested
265 03:11:11.308712 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 03:11:11.309229 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 03:11:11.309727 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 03:11:11.310143 Checking files for TFTP limit of 4294967296 bytes.
269 03:11:11.312847 end: 1 tftp-deploy (duration 00:01:04) [common]
270 03:11:11.313422 start: 2 uboot-action (timeout 00:05:00) [common]
271 03:11:11.313945 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 03:11:11.314440 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 03:11:11.314939 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 03:11:11.315465 Using kernel file from prepare-kernel: 950252/tftp-deploy-s17t03ab/kernel/uImage
275 03:11:11.316121 substitutions:
276 03:11:11.316544 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 03:11:11.316948 - {DTB_ADDR}: 0x01070000
278 03:11:11.317349 - {DTB}: 950252/tftp-deploy-s17t03ab/dtb/meson-g12b-a311d-libretech-cc.dtb
279 03:11:11.317748 - {INITRD}: 950252/tftp-deploy-s17t03ab/ramdisk/ramdisk.cpio.gz.uboot
280 03:11:11.318143 - {KERNEL_ADDR}: 0x01080000
281 03:11:11.318534 - {KERNEL}: 950252/tftp-deploy-s17t03ab/kernel/uImage
282 03:11:11.318924 - {LAVA_MAC}: None
283 03:11:11.319354 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/950252/extract-nfsrootfs-gw_j8b5f
284 03:11:11.319753 - {NFS_SERVER_IP}: 192.168.6.2
285 03:11:11.320174 - {PRESEED_CONFIG}: None
286 03:11:11.320567 - {PRESEED_LOCAL}: None
287 03:11:11.320957 - {RAMDISK_ADDR}: 0x08000000
288 03:11:11.321344 - {RAMDISK}: 950252/tftp-deploy-s17t03ab/ramdisk/ramdisk.cpio.gz.uboot
289 03:11:11.321735 - {ROOT_PART}: None
290 03:11:11.322122 - {ROOT}: None
291 03:11:11.322509 - {SERVER_IP}: 192.168.6.2
292 03:11:11.322896 - {TEE_ADDR}: 0x83000000
293 03:11:11.323282 - {TEE}: None
294 03:11:11.323793 Parsed boot commands:
295 03:11:11.324211 - setenv autoload no
296 03:11:11.324608 - setenv initrd_high 0xffffffff
297 03:11:11.325000 - setenv fdt_high 0xffffffff
298 03:11:11.325389 - dhcp
299 03:11:11.325775 - setenv serverip 192.168.6.2
300 03:11:11.326162 - tftpboot 0x01080000 950252/tftp-deploy-s17t03ab/kernel/uImage
301 03:11:11.326555 - tftpboot 0x08000000 950252/tftp-deploy-s17t03ab/ramdisk/ramdisk.cpio.gz.uboot
302 03:11:11.326941 - tftpboot 0x01070000 950252/tftp-deploy-s17t03ab/dtb/meson-g12b-a311d-libretech-cc.dtb
303 03:11:11.327331 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950252/extract-nfsrootfs-gw_j8b5f,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 03:11:11.327733 - bootm 0x01080000 0x08000000 0x01070000
305 03:11:11.328299 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 03:11:11.329800 start: 2.3 connect-device (timeout 00:05:00) [common]
308 03:11:11.330219 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 03:11:11.344914 Setting prompt string to ['lava-test: # ']
310 03:11:11.346388 end: 2.3 connect-device (duration 00:00:00) [common]
311 03:11:11.346972 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 03:11:11.347522 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 03:11:11.348204 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 03:11:11.349363 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 03:11:11.386771 >> OK - accepted request
316 03:11:11.388875 Returned 0 in 0 seconds
317 03:11:11.489995 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 03:11:11.491655 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 03:11:11.492261 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 03:11:11.492775 Setting prompt string to ['Hit any key to stop autoboot']
322 03:11:11.493234 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 03:11:11.494801 Trying 192.168.56.21...
324 03:11:11.495276 Connected to conserv1.
325 03:11:11.495697 Escape character is '^]'.
326 03:11:11.496147
327 03:11:11.496573 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 03:11:11.496994
329 03:11:22.565675 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 03:11:22.566336 bl2_stage_init 0x01
331 03:11:22.566752 bl2_stage_init 0x81
332 03:11:22.570669 hw id: 0x0000 - pwm id 0x01
333 03:11:22.571137 bl2_stage_init 0xc1
334 03:11:22.571536 bl2_stage_init 0x02
335 03:11:22.571931
336 03:11:22.576053 L0:00000000
337 03:11:22.576628 L1:20000703
338 03:11:22.577049 L2:00008067
339 03:11:22.577438 L3:14000000
340 03:11:22.581314 B2:00402000
341 03:11:22.581688 B1:e0f83180
342 03:11:22.581929
343 03:11:22.582136 TE: 58167
344 03:11:22.582335
345 03:11:22.586600 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 03:11:22.587131
347 03:11:22.587529 Board ID = 1
348 03:11:22.592000 Set A53 clk to 24M
349 03:11:22.592459 Set A73 clk to 24M
350 03:11:22.592855 Set clk81 to 24M
351 03:11:22.598000 A53 clk: 1200 MHz
352 03:11:22.598464 A73 clk: 1200 MHz
353 03:11:22.598860 CLK81: 166.6M
354 03:11:22.599246 smccc: 00012abe
355 03:11:22.603407 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 03:11:22.608977 board id: 1
357 03:11:22.614770 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 03:11:22.625303 fw parse done
359 03:11:22.631292 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 03:11:22.673999 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 03:11:22.684776 PIEI prepare done
362 03:11:22.685096 fastboot data load
363 03:11:22.685306 fastboot data verify
364 03:11:22.690208 verify result: 266
365 03:11:22.695811 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 03:11:22.696106 LPDDR4 probe
367 03:11:22.696315 ddr clk to 1584MHz
368 03:11:22.703736 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 03:11:22.741270
370 03:11:22.741908 dmc_version 0001
371 03:11:22.747929 Check phy result
372 03:11:22.755181 INFO : End of CA training
373 03:11:22.755861 INFO : End of initialization
374 03:11:22.759594 INFO : Training has run successfully!
375 03:11:22.760143 Check phy result
376 03:11:22.766392 INFO : End of initialization
377 03:11:22.766903 INFO : End of read enable training
378 03:11:22.771770 INFO : End of fine write leveling
379 03:11:22.777500 INFO : End of Write leveling coarse delay
380 03:11:22.778197 INFO : Training has run successfully!
381 03:11:22.778669 Check phy result
382 03:11:22.783738 INFO : End of initialization
383 03:11:22.784419 INFO : End of read dq deskew training
384 03:11:22.787563 INFO : End of MPR read delay center optimization
385 03:11:22.796072 INFO : End of write delay center optimization
386 03:11:22.798674 INFO : End of read delay center optimization
387 03:11:22.799289 INFO : End of max read latency training
388 03:11:22.804286 INFO : Training has run successfully!
389 03:11:22.804886 1D training succeed
390 03:11:22.813360 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 03:11:22.861012 Check phy result
392 03:11:22.861713 INFO : End of initialization
393 03:11:22.882815 INFO : End of 2D read delay Voltage center optimization
394 03:11:22.903013 INFO : End of 2D read delay Voltage center optimization
395 03:11:22.955124 INFO : End of 2D write delay Voltage center optimization
396 03:11:23.004435 INFO : End of 2D write delay Voltage center optimization
397 03:11:23.009949 INFO : Training has run successfully!
398 03:11:23.010521
399 03:11:23.010984 channel==0
400 03:11:23.015505 RxClkDly_Margin_A0==88 ps 9
401 03:11:23.016135 TxDqDly_Margin_A0==98 ps 10
402 03:11:23.021108 RxClkDly_Margin_A1==88 ps 9
403 03:11:23.021687 TxDqDly_Margin_A1==98 ps 10
404 03:11:23.022155 TrainedVREFDQ_A0==74
405 03:11:23.026722 TrainedVREFDQ_A1==74
406 03:11:23.027311 VrefDac_Margin_A0==25
407 03:11:23.027772 DeviceVref_Margin_A0==40
408 03:11:23.032472 VrefDac_Margin_A1==23
409 03:11:23.032901 DeviceVref_Margin_A1==40
410 03:11:23.033150
411 03:11:23.033393
412 03:11:23.037890 channel==1
413 03:11:23.038473 RxClkDly_Margin_A0==98 ps 10
414 03:11:23.038850 TxDqDly_Margin_A0==98 ps 10
415 03:11:23.043414 RxClkDly_Margin_A1==88 ps 9
416 03:11:23.043926 TxDqDly_Margin_A1==88 ps 9
417 03:11:23.049027 TrainedVREFDQ_A0==77
418 03:11:23.049463 TrainedVREFDQ_A1==77
419 03:11:23.049761 VrefDac_Margin_A0==22
420 03:11:23.054634 DeviceVref_Margin_A0==37
421 03:11:23.055044 VrefDac_Margin_A1==24
422 03:11:23.060403 DeviceVref_Margin_A1==37
423 03:11:23.060973
424 03:11:23.061370 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 03:11:23.061749
426 03:11:23.093981 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000019 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 03:11:23.094704 2D training succeed
428 03:11:23.099590 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 03:11:23.105110 auto size-- 65535DDR cs0 size: 2048MB
430 03:11:23.105528 DDR cs1 size: 2048MB
431 03:11:23.110809 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 03:11:23.111393 cs0 DataBus test pass
433 03:11:23.116379 cs1 DataBus test pass
434 03:11:23.116937 cs0 AddrBus test pass
435 03:11:23.117361 cs1 AddrBus test pass
436 03:11:23.117773
437 03:11:23.121881 100bdlr_step_size ps== 420
438 03:11:23.122405 result report
439 03:11:23.127553 boot times 0Enable ddr reg access
440 03:11:23.132790 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 03:11:23.146386 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 03:11:23.719883 0.0;M3 CHK:0;cm4_sp_mode 0
443 03:11:23.720512 MVN_1=0x00000000
444 03:11:23.725307 MVN_2=0x00000000
445 03:11:23.731017 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 03:11:23.731297 OPS=0x10
447 03:11:23.731545 ring efuse init
448 03:11:23.731782 chipver efuse init
449 03:11:23.736606 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 03:11:23.742240 [0.018960 Inits done]
451 03:11:23.742516 secure task start!
452 03:11:23.742763 high task start!
453 03:11:23.746805 low task start!
454 03:11:23.747074 run into bl31
455 03:11:23.753432 NOTICE: BL31: v1.3(release):4fc40b1
456 03:11:23.761294 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 03:11:23.761585 NOTICE: BL31: G12A normal boot!
458 03:11:23.786663 NOTICE: BL31: BL33 decompress pass
459 03:11:23.792322 ERROR: Error initializing runtime service opteed_fast
460 03:11:25.025412
461 03:11:25.026103
462 03:11:25.033607 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 03:11:25.033958
464 03:11:25.034217 Model: Libre Computer AML-A311D-CC Alta
465 03:11:25.242002 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 03:11:25.265381 DRAM: 2 GiB (effective 3.8 GiB)
467 03:11:25.408379 Core: 408 devices, 31 uclasses, devicetree: separate
468 03:11:25.414253 WDT: Not starting watchdog@f0d0
469 03:11:25.446508 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 03:11:25.458931 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 03:11:25.463934 ** Bad device specification mmc 0 **
472 03:11:25.474259 Card did not respond to voltage select! : -110
473 03:11:25.481907 ** Bad device specification mmc 0 **
474 03:11:25.482183 Couldn't find partition mmc 0
475 03:11:25.490275 Card did not respond to voltage select! : -110
476 03:11:25.495850 ** Bad device specification mmc 0 **
477 03:11:25.496311 Couldn't find partition mmc 0
478 03:11:25.500915 Error: could not access storage.
479 03:11:26.764268 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 03:11:26.764718 bl2_stage_init 0x01
481 03:11:26.764950 bl2_stage_init 0x81
482 03:11:26.769825 hw id: 0x0000 - pwm id 0x01
483 03:11:26.770129 bl2_stage_init 0xc1
484 03:11:26.770352 bl2_stage_init 0x02
485 03:11:26.770564
486 03:11:26.775567 L0:00000000
487 03:11:26.776162 L1:20000703
488 03:11:26.776632 L2:00008067
489 03:11:26.777079 L3:14000000
490 03:11:26.781140 B2:00402000
491 03:11:26.781654 B1:e0f83180
492 03:11:26.782107
493 03:11:26.782551 TE: 58167
494 03:11:26.782994
495 03:11:26.786805 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 03:11:26.787325
497 03:11:26.787779 Board ID = 1
498 03:11:26.792403 Set A53 clk to 24M
499 03:11:26.792921 Set A73 clk to 24M
500 03:11:26.793374 Set clk81 to 24M
501 03:11:26.797937 A53 clk: 1200 MHz
502 03:11:26.798447 A73 clk: 1200 MHz
503 03:11:26.798905 CLK81: 166.6M
504 03:11:26.799353 smccc: 00012abd
505 03:11:26.803518 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 03:11:26.809110 board id: 1
507 03:11:26.814976 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 03:11:26.825673 fw parse done
509 03:11:26.831603 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 03:11:26.874219 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 03:11:26.885151 PIEI prepare done
512 03:11:26.885668 fastboot data load
513 03:11:26.886126 fastboot data verify
514 03:11:26.890952 verify result: 266
515 03:11:26.896435 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 03:11:26.896949 LPDDR4 probe
517 03:11:26.897402 ddr clk to 1584MHz
518 03:11:26.904431 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 03:11:26.941652
520 03:11:26.942181 dmc_version 0001
521 03:11:26.948353 Check phy result
522 03:11:26.954204 INFO : End of CA training
523 03:11:26.954716 INFO : End of initialization
524 03:11:26.959895 INFO : Training has run successfully!
525 03:11:26.960443 Check phy result
526 03:11:26.965434 INFO : End of initialization
527 03:11:26.965944 INFO : End of read enable training
528 03:11:26.971018 INFO : End of fine write leveling
529 03:11:26.976628 INFO : End of Write leveling coarse delay
530 03:11:26.977143 INFO : Training has run successfully!
531 03:11:26.977595 Check phy result
532 03:11:26.982227 INFO : End of initialization
533 03:11:26.982729 INFO : End of read dq deskew training
534 03:11:26.987923 INFO : End of MPR read delay center optimization
535 03:11:26.993418 INFO : End of write delay center optimization
536 03:11:26.999022 INFO : End of read delay center optimization
537 03:11:26.999544 INFO : End of max read latency training
538 03:11:27.004620 INFO : Training has run successfully!
539 03:11:27.005127 1D training succeed
540 03:11:27.013775 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 03:11:27.061414 Check phy result
542 03:11:27.061993 INFO : End of initialization
543 03:11:27.083010 INFO : End of 2D read delay Voltage center optimization
544 03:11:27.103121 INFO : End of 2D read delay Voltage center optimization
545 03:11:27.155064 INFO : End of 2D write delay Voltage center optimization
546 03:11:27.204409 INFO : End of 2D write delay Voltage center optimization
547 03:11:27.209887 INFO : Training has run successfully!
548 03:11:27.210483
549 03:11:27.210967 channel==0
550 03:11:27.215505 RxClkDly_Margin_A0==88 ps 9
551 03:11:27.216134 TxDqDly_Margin_A0==98 ps 10
552 03:11:27.221108 RxClkDly_Margin_A1==88 ps 9
553 03:11:27.221686 TxDqDly_Margin_A1==98 ps 10
554 03:11:27.222151 TrainedVREFDQ_A0==74
555 03:11:27.226699 TrainedVREFDQ_A1==74
556 03:11:27.227270 VrefDac_Margin_A0==25
557 03:11:27.227728 DeviceVref_Margin_A0==40
558 03:11:27.232313 VrefDac_Margin_A1==25
559 03:11:27.232870 DeviceVref_Margin_A1==40
560 03:11:27.233326
561 03:11:27.233779
562 03:11:27.237871 channel==1
563 03:11:27.238396 RxClkDly_Margin_A0==98 ps 10
564 03:11:27.238846 TxDqDly_Margin_A0==88 ps 9
565 03:11:27.243492 RxClkDly_Margin_A1==88 ps 9
566 03:11:27.244078 TxDqDly_Margin_A1==88 ps 9
567 03:11:27.249044 TrainedVREFDQ_A0==77
568 03:11:27.249593 TrainedVREFDQ_A1==77
569 03:11:27.250052 VrefDac_Margin_A0==22
570 03:11:27.254707 DeviceVref_Margin_A0==37
571 03:11:27.255296 VrefDac_Margin_A1==24
572 03:11:27.260322 DeviceVref_Margin_A1==37
573 03:11:27.260883
574 03:11:27.261343 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 03:11:27.261793
576 03:11:27.293838 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 03:11:27.294497 2D training succeed
578 03:11:27.299494 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 03:11:27.305053 auto size-- 65535DDR cs0 size: 2048MB
580 03:11:27.305585 DDR cs1 size: 2048MB
581 03:11:27.310636 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 03:11:27.311154 cs0 DataBus test pass
583 03:11:27.316288 cs1 DataBus test pass
584 03:11:27.316812 cs0 AddrBus test pass
585 03:11:27.317267 cs1 AddrBus test pass
586 03:11:27.317709
587 03:11:27.321838 100bdlr_step_size ps== 420
588 03:11:27.322370 result report
589 03:11:27.327428 boot times 0Enable ddr reg access
590 03:11:27.332691 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 03:11:27.346075 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 03:11:27.918851 0.0;M3 CHK:0;cm4_sp_mode 0
593 03:11:27.919513 MVN_1=0x00000000
594 03:11:27.924360 MVN_2=0x00000000
595 03:11:27.929922 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 03:11:27.930469 OPS=0x10
597 03:11:27.930932 ring efuse init
598 03:11:27.931405 chipver efuse init
599 03:11:27.935470 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 03:11:27.940829 [0.018961 Inits done]
601 03:11:27.941345 secure task start!
602 03:11:27.941781 high task start!
603 03:11:27.945289 low task start!
604 03:11:27.945786 run into bl31
605 03:11:27.952180 NOTICE: BL31: v1.3(release):4fc40b1
606 03:11:27.959705 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 03:11:27.960247 NOTICE: BL31: G12A normal boot!
608 03:11:27.985430 NOTICE: BL31: BL33 decompress pass
609 03:11:27.991134 ERROR: Error initializing runtime service opteed_fast
610 03:11:29.224355
611 03:11:29.225044
612 03:11:29.232619 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 03:11:29.233166
614 03:11:29.233634 Model: Libre Computer AML-A311D-CC Alta
615 03:11:29.440948 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 03:11:29.464469 DRAM: 2 GiB (effective 3.8 GiB)
617 03:11:29.607464 Core: 408 devices, 31 uclasses, devicetree: separate
618 03:11:29.613194 WDT: Not starting watchdog@f0d0
619 03:11:29.645500 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 03:11:29.657905 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 03:11:29.662903 ** Bad device specification mmc 0 **
622 03:11:29.673246 Card did not respond to voltage select! : -110
623 03:11:29.680894 ** Bad device specification mmc 0 **
624 03:11:29.681423 Couldn't find partition mmc 0
625 03:11:29.689244 Card did not respond to voltage select! : -110
626 03:11:29.694666 ** Bad device specification mmc 0 **
627 03:11:29.695192 Couldn't find partition mmc 0
628 03:11:29.699799 Error: could not access storage.
629 03:11:30.043427 Net: eth0: ethernet@ff3f0000
630 03:11:30.044127 starting USB...
631 03:11:30.295127 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 03:11:30.295750 Starting the controller
633 03:11:30.302127 USB XHCI 1.10
634 03:11:32.016083 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 03:11:32.016732 bl2_stage_init 0x01
636 03:11:32.017201 bl2_stage_init 0x81
637 03:11:32.021804 hw id: 0x0000 - pwm id 0x01
638 03:11:32.022342 bl2_stage_init 0xc1
639 03:11:32.022804 bl2_stage_init 0x02
640 03:11:32.023258
641 03:11:32.027290 L0:00000000
642 03:11:32.027820 L1:20000703
643 03:11:32.028320 L2:00008067
644 03:11:32.028783 L3:14000000
645 03:11:32.032869 B2:00402000
646 03:11:32.033391 B1:e0f83180
647 03:11:32.033847
648 03:11:32.034298 TE: 58167
649 03:11:32.034738
650 03:11:32.038478 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 03:11:32.038995
652 03:11:32.039455 Board ID = 1
653 03:11:32.044077 Set A53 clk to 24M
654 03:11:32.044590 Set A73 clk to 24M
655 03:11:32.045045 Set clk81 to 24M
656 03:11:32.049577 A53 clk: 1200 MHz
657 03:11:32.050083 A73 clk: 1200 MHz
658 03:11:32.050538 CLK81: 166.6M
659 03:11:32.050983 smccc: 00012abe
660 03:11:32.055243 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 03:11:32.060865 board id: 1
662 03:11:32.066795 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 03:11:32.077353 fw parse done
664 03:11:32.083308 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 03:11:32.125860 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 03:11:32.136764 PIEI prepare done
667 03:11:32.137271 fastboot data load
668 03:11:32.137728 fastboot data verify
669 03:11:32.142430 verify result: 266
670 03:11:32.148065 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 03:11:32.148582 LPDDR4 probe
672 03:11:32.149043 ddr clk to 1584MHz
673 03:11:32.156093 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 03:11:32.193311
675 03:11:32.193824 dmc_version 0001
676 03:11:32.200026 Check phy result
677 03:11:32.205828 INFO : End of CA training
678 03:11:32.206332 INFO : End of initialization
679 03:11:32.211445 INFO : Training has run successfully!
680 03:11:32.211948 Check phy result
681 03:11:32.217099 INFO : End of initialization
682 03:11:32.217602 INFO : End of read enable training
683 03:11:32.220373 INFO : End of fine write leveling
684 03:11:32.225932 INFO : End of Write leveling coarse delay
685 03:11:32.231486 INFO : Training has run successfully!
686 03:11:32.232021 Check phy result
687 03:11:32.232484 INFO : End of initialization
688 03:11:32.237089 INFO : End of read dq deskew training
689 03:11:32.240520 INFO : End of MPR read delay center optimization
690 03:11:32.246066 INFO : End of write delay center optimization
691 03:11:32.251686 INFO : End of read delay center optimization
692 03:11:32.252237 INFO : End of max read latency training
693 03:11:32.257218 INFO : Training has run successfully!
694 03:11:32.257725 1D training succeed
695 03:11:32.265507 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 03:11:32.313128 Check phy result
697 03:11:32.313701 INFO : End of initialization
698 03:11:32.335671 INFO : End of 2D read delay Voltage center optimization
699 03:11:32.355911 INFO : End of 2D read delay Voltage center optimization
700 03:11:32.407951 INFO : End of 2D write delay Voltage center optimization
701 03:11:32.457394 INFO : End of 2D write delay Voltage center optimization
702 03:11:32.462902 INFO : Training has run successfully!
703 03:11:32.463410
704 03:11:32.463872 channel==0
705 03:11:32.468586 RxClkDly_Margin_A0==88 ps 9
706 03:11:32.469098 TxDqDly_Margin_A0==98 ps 10
707 03:11:32.471852 RxClkDly_Margin_A1==88 ps 9
708 03:11:32.472395 TxDqDly_Margin_A1==98 ps 10
709 03:11:32.477422 TrainedVREFDQ_A0==74
710 03:11:32.477934 TrainedVREFDQ_A1==74
711 03:11:32.482999 VrefDac_Margin_A0==24
712 03:11:32.483501 DeviceVref_Margin_A0==40
713 03:11:32.483956 VrefDac_Margin_A1==25
714 03:11:32.488609 DeviceVref_Margin_A1==40
715 03:11:32.489116
716 03:11:32.489570
717 03:11:32.490046 channel==1
718 03:11:32.490494 RxClkDly_Margin_A0==98 ps 10
719 03:11:32.492104 TxDqDly_Margin_A0==88 ps 9
720 03:11:32.497729 RxClkDly_Margin_A1==88 ps 9
721 03:11:32.498247 TxDqDly_Margin_A1==88 ps 9
722 03:11:32.498704 TrainedVREFDQ_A0==77
723 03:11:32.503351 TrainedVREFDQ_A1==77
724 03:11:32.503876 VrefDac_Margin_A0==22
725 03:11:32.508911 DeviceVref_Margin_A0==37
726 03:11:32.509430 VrefDac_Margin_A1==24
727 03:11:32.509884 DeviceVref_Margin_A1==37
728 03:11:32.510330
729 03:11:32.514451 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 03:11:32.514968
731 03:11:32.548104 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
732 03:11:32.548735 2D training succeed
733 03:11:32.553676 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 03:11:32.559186 auto size-- 65535DDR cs0 size: 2048MB
735 03:11:32.559708 DDR cs1 size: 2048MB
736 03:11:32.564827 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 03:11:32.565355 cs0 DataBus test pass
738 03:11:32.565814 cs1 DataBus test pass
739 03:11:32.570397 cs0 AddrBus test pass
740 03:11:32.570925 cs1 AddrBus test pass
741 03:11:32.571379
742 03:11:32.575954 100bdlr_step_size ps== 420
743 03:11:32.576520 result report
744 03:11:32.576979 boot times 0Enable ddr reg access
745 03:11:32.585700 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 03:11:32.599140 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 03:11:33.172808 0.0;M3 CHK:0;cm4_sp_mode 0
748 03:11:33.173508 MVN_1=0x00000000
749 03:11:33.178323 MVN_2=0x00000000
750 03:11:33.184175 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 03:11:33.184849 OPS=0x10
752 03:11:33.185386 ring efuse init
753 03:11:33.185898 chipver efuse init
754 03:11:33.190751 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 03:11:33.195259 [0.018961 Inits done]
756 03:11:33.195814 secure task start!
757 03:11:33.196386 high task start!
758 03:11:33.199825 low task start!
759 03:11:33.200407 run into bl31
760 03:11:33.206460 NOTICE: BL31: v1.3(release):4fc40b1
761 03:11:33.214190 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 03:11:33.214766 NOTICE: BL31: G12A normal boot!
763 03:11:33.239728 NOTICE: BL31: BL33 decompress pass
764 03:11:33.245304 ERROR: Error initializing runtime service opteed_fast
765 03:11:34.478321
766 03:11:34.479138
767 03:11:34.486567 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 03:11:34.487237
769 03:11:34.487828 Model: Libre Computer AML-A311D-CC Alta
770 03:11:34.695029 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 03:11:34.717408 DRAM: 2 GiB (effective 3.8 GiB)
772 03:11:34.861445 Core: 408 devices, 31 uclasses, devicetree: separate
773 03:11:34.867266 WDT: Not starting watchdog@f0d0
774 03:11:34.899509 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 03:11:34.912104 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 03:11:34.916084 ** Bad device specification mmc 0 **
777 03:11:34.927317 Card did not respond to voltage select! : -110
778 03:11:34.934035 ** Bad device specification mmc 0 **
779 03:11:34.934637 Couldn't find partition mmc 0
780 03:11:34.943331 Card did not respond to voltage select! : -110
781 03:11:34.948786 ** Bad device specification mmc 0 **
782 03:11:34.949399 Couldn't find partition mmc 0
783 03:11:34.952892 Error: could not access storage.
784 03:11:35.295376 Net: eth0: ethernet@ff3f0000
785 03:11:35.296166 starting USB...
786 03:11:35.548293 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 03:11:35.549089 Starting the controller
788 03:11:35.555051 USB XHCI 1.10
789 03:11:37.735866 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 03:11:37.736690 bl2_stage_init 0x01
791 03:11:37.737271 bl2_stage_init 0x81
792 03:11:37.741549 hw id: 0x0000 - pwm id 0x01
793 03:11:37.742144 bl2_stage_init 0xc1
794 03:11:37.742688 bl2_stage_init 0x02
795 03:11:37.743221
796 03:11:37.747201 L0:00000000
797 03:11:37.747784 L1:20000703
798 03:11:37.748358 L2:00008067
799 03:11:37.748894 L3:14000000
800 03:11:37.752659 B2:00402000
801 03:11:37.753292 B1:e0f83180
802 03:11:37.753837
803 03:11:37.754361 TE: 58124
804 03:11:37.754881
805 03:11:37.758572 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 03:11:37.759158
807 03:11:37.759689 Board ID = 1
808 03:11:37.763902 Set A53 clk to 24M
809 03:11:37.764498 Set A73 clk to 24M
810 03:11:37.765038 Set clk81 to 24M
811 03:11:37.769432 A53 clk: 1200 MHz
812 03:11:37.770009 A73 clk: 1200 MHz
813 03:11:37.770544 CLK81: 166.6M
814 03:11:37.771058 smccc: 00012a92
815 03:11:37.775025 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 03:11:37.780633 board id: 1
817 03:11:37.786627 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 03:11:37.797330 fw parse done
819 03:11:37.803214 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 03:11:37.845702 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 03:11:37.856633 PIEI prepare done
822 03:11:37.857268 fastboot data load
823 03:11:37.857818 fastboot data verify
824 03:11:37.862339 verify result: 266
825 03:11:37.867850 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 03:11:37.868482 LPDDR4 probe
827 03:11:37.869014 ddr clk to 1584MHz
828 03:11:37.875824 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 03:11:37.913076
830 03:11:37.913683 dmc_version 0001
831 03:11:37.919759 Check phy result
832 03:11:37.925629 INFO : End of CA training
833 03:11:37.926208 INFO : End of initialization
834 03:11:37.931313 INFO : Training has run successfully!
835 03:11:37.931885 Check phy result
836 03:11:37.936840 INFO : End of initialization
837 03:11:37.937400 INFO : End of read enable training
838 03:11:37.942446 INFO : End of fine write leveling
839 03:11:37.948069 INFO : End of Write leveling coarse delay
840 03:11:37.948655 INFO : Training has run successfully!
841 03:11:37.949193 Check phy result
842 03:11:37.953692 INFO : End of initialization
843 03:11:37.954329 INFO : End of read dq deskew training
844 03:11:37.959229 INFO : End of MPR read delay center optimization
845 03:11:37.964826 INFO : End of write delay center optimization
846 03:11:37.970447 INFO : End of read delay center optimization
847 03:11:37.971017 INFO : End of max read latency training
848 03:11:37.976113 INFO : Training has run successfully!
849 03:11:37.976676 1D training succeed
850 03:11:37.985237 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 03:11:38.032862 Check phy result
852 03:11:38.033551 INFO : End of initialization
853 03:11:38.055293 INFO : End of 2D read delay Voltage center optimization
854 03:11:38.075330 INFO : End of 2D read delay Voltage center optimization
855 03:11:38.127307 INFO : End of 2D write delay Voltage center optimization
856 03:11:38.176514 INFO : End of 2D write delay Voltage center optimization
857 03:11:38.182139 INFO : Training has run successfully!
858 03:11:38.182788
859 03:11:38.183385 channel==0
860 03:11:38.187658 RxClkDly_Margin_A0==88 ps 9
861 03:11:38.188301 TxDqDly_Margin_A0==98 ps 10
862 03:11:38.193236 RxClkDly_Margin_A1==88 ps 9
863 03:11:38.193784 TxDqDly_Margin_A1==98 ps 10
864 03:11:38.194301 TrainedVREFDQ_A0==74
865 03:11:38.198839 TrainedVREFDQ_A1==74
866 03:11:38.199398 VrefDac_Margin_A0==24
867 03:11:38.199903 DeviceVref_Margin_A0==40
868 03:11:38.204426 VrefDac_Margin_A1==25
869 03:11:38.204986 DeviceVref_Margin_A1==40
870 03:11:38.205497
871 03:11:38.206005
872 03:11:38.210021 channel==1
873 03:11:38.210569 RxClkDly_Margin_A0==88 ps 9
874 03:11:38.211082 TxDqDly_Margin_A0==88 ps 9
875 03:11:38.215663 RxClkDly_Margin_A1==98 ps 10
876 03:11:38.216227 TxDqDly_Margin_A1==88 ps 9
877 03:11:38.221252 TrainedVREFDQ_A0==77
878 03:11:38.221808 TrainedVREFDQ_A1==77
879 03:11:38.222318 VrefDac_Margin_A0==22
880 03:11:38.226856 DeviceVref_Margin_A0==37
881 03:11:38.227395 VrefDac_Margin_A1==22
882 03:11:38.232428 DeviceVref_Margin_A1==37
883 03:11:38.232966
884 03:11:38.233471 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 03:11:38.233970
886 03:11:38.266068 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
887 03:11:38.266750 2D training succeed
888 03:11:38.271633 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 03:11:38.277233 auto size-- 65535DDR cs0 size: 2048MB
890 03:11:38.277783 DDR cs1 size: 2048MB
891 03:11:38.282833 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 03:11:38.283382 cs0 DataBus test pass
893 03:11:38.288427 cs1 DataBus test pass
894 03:11:38.288970 cs0 AddrBus test pass
895 03:11:38.289472 cs1 AddrBus test pass
896 03:11:38.289970
897 03:11:38.294023 100bdlr_step_size ps== 420
898 03:11:38.294578 result report
899 03:11:38.299643 boot times 0Enable ddr reg access
900 03:11:38.304949 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 03:11:38.318439 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 03:11:38.890505 0.0;M3 CHK:0;cm4_sp_mode 0
903 03:11:38.891287 MVN_1=0x00000000
904 03:11:38.895875 MVN_2=0x00000000
905 03:11:38.901709 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 03:11:38.902296 OPS=0x10
907 03:11:38.902840 ring efuse init
908 03:11:38.903360 chipver efuse init
909 03:11:38.909898 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 03:11:38.910507 [0.018961 Inits done]
911 03:11:38.917511 secure task start!
912 03:11:38.918076 high task start!
913 03:11:38.918608 low task start!
914 03:11:38.919127 run into bl31
915 03:11:38.924069 NOTICE: BL31: v1.3(release):4fc40b1
916 03:11:38.931851 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 03:11:38.932480 NOTICE: BL31: G12A normal boot!
918 03:11:38.957295 NOTICE: BL31: BL33 decompress pass
919 03:11:38.961950 ERROR: Error initializing runtime service opteed_fast
920 03:11:40.195816
921 03:11:40.196473
922 03:11:40.204187 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 03:11:40.204666
924 03:11:40.205092 Model: Libre Computer AML-A311D-CC Alta
925 03:11:40.412666 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 03:11:40.435941 DRAM: 2 GiB (effective 3.8 GiB)
927 03:11:40.579026 Core: 408 devices, 31 uclasses, devicetree: separate
928 03:11:40.584832 WDT: Not starting watchdog@f0d0
929 03:11:40.617084 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 03:11:40.629606 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 03:11:40.634512 ** Bad device specification mmc 0 **
932 03:11:40.644842 Card did not respond to voltage select! : -110
933 03:11:40.652491 ** Bad device specification mmc 0 **
934 03:11:40.652945 Couldn't find partition mmc 0
935 03:11:40.660832 Card did not respond to voltage select! : -110
936 03:11:40.666396 ** Bad device specification mmc 0 **
937 03:11:40.666897 Couldn't find partition mmc 0
938 03:11:40.671425 Error: could not access storage.
939 03:11:41.014967 Net: eth0: ethernet@ff3f0000
940 03:11:41.015526 starting USB...
941 03:11:41.266892 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 03:11:41.267439 Starting the controller
943 03:11:41.273831 USB XHCI 1.10
944 03:11:42.827845 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 03:11:42.836138 scanning usb for storage devices... 0 Storage Device(s) found
947 03:11:42.887636 Hit any key to stop autoboot: 1
948 03:11:42.888494 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
949 03:11:42.889090 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
950 03:11:42.889571 Setting prompt string to ['=>']
951 03:11:42.890064 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
952 03:11:42.903749 0
953 03:11:42.904634 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 03:11:42.905143 Sending with 10 millisecond of delay
956 03:11:44.039775 => setenv autoload no
957 03:11:44.050610 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
958 03:11:44.055497 setenv autoload no
959 03:11:44.056260 Sending with 10 millisecond of delay
961 03:11:45.853726 => setenv initrd_high 0xffffffff
962 03:11:45.864711 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
963 03:11:45.865826 setenv initrd_high 0xffffffff
964 03:11:45.866693 Sending with 10 millisecond of delay
966 03:11:47.483649 => setenv fdt_high 0xffffffff
967 03:11:47.494705 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
968 03:11:47.495748 setenv fdt_high 0xffffffff
969 03:11:47.496681 Sending with 10 millisecond of delay
971 03:11:47.788931 => dhcp
972 03:11:47.799861 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
973 03:11:47.800937 dhcp
974 03:11:47.801505 Speed: 1000, full duplex
975 03:11:47.802045 BOOTP broadcast 1
976 03:11:47.856123 DHCP client bound to address 192.168.6.27 (56 ms)
977 03:11:47.856984 Sending with 10 millisecond of delay
979 03:11:49.534020 => setenv serverip 192.168.6.2
980 03:11:49.545068 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
981 03:11:49.546258 setenv serverip 192.168.6.2
982 03:11:49.547113 Sending with 10 millisecond of delay
984 03:11:53.272434 => tftpboot 0x01080000 950252/tftp-deploy-s17t03ab/kernel/uImage
985 03:11:53.282971 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
986 03:11:53.283448 tftpboot 0x01080000 950252/tftp-deploy-s17t03ab/kernel/uImage
987 03:11:53.283676 Speed: 1000, full duplex
988 03:11:53.283899 Using ethernet@ff3f0000 device
989 03:11:53.285576 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
990 03:11:53.291008 Filename '950252/tftp-deploy-s17t03ab/kernel/uImage'.
991 03:11:53.295159 Load address: 0x1080000
992 03:11:53.452338 Loading: *### UDP wrong checksum 000000ff 000032b4
993 03:11:53.465478 UDP wrong checksum 000000ff 0000bba6
994 03:11:55.767098 ############################################### 36.1 MiB
995 03:11:55.767756 14.6 MiB/s
996 03:11:55.768302 done
997 03:11:55.771611 Bytes transferred = 37878336 (241fa40 hex)
998 03:11:55.772452 Sending with 10 millisecond of delay
1000 03:12:00.461026 => tftpboot 0x08000000 950252/tftp-deploy-s17t03ab/ramdisk/ramdisk.cpio.gz.uboot
1001 03:12:00.471842 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1002 03:12:00.472764 tftpboot 0x08000000 950252/tftp-deploy-s17t03ab/ramdisk/ramdisk.cpio.gz.uboot
1003 03:12:00.473244 Speed: 1000, full duplex
1004 03:12:00.473696 Using ethernet@ff3f0000 device
1005 03:12:00.474868 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1006 03:12:00.486554 Filename '950252/tftp-deploy-s17t03ab/ramdisk/ramdisk.cpio.gz.uboot'.
1007 03:12:00.487087 Load address: 0x8000000
1008 03:12:07.349243 Loading: *###############################T ################## UDP wrong checksum 00000005 0000f0a5
1009 03:12:12.350117 T UDP wrong checksum 00000005 0000f0a5
1010 03:12:22.351838 T T UDP wrong checksum 00000005 0000f0a5
1011 03:12:31.543522 T UDP wrong checksum 000000ff 00003884
1012 03:12:31.560224 UDP wrong checksum 000000ff 0000ce76
1013 03:12:42.356052 T T T UDP wrong checksum 00000005 0000f0a5
1014 03:12:50.375223 T UDP wrong checksum 000000ff 000073e7
1015 03:12:50.415492 UDP wrong checksum 000000ff 0000fdd9
1016 03:12:57.360180 T
1017 03:12:57.360875 Retry count exceeded; starting again
1019 03:12:57.362392 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1022 03:12:57.364496 end: 2.4 uboot-commands (duration 00:01:46) [common]
1024 03:12:57.365989 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1026 03:12:57.367148 end: 2 uboot-action (duration 00:01:46) [common]
1028 03:12:57.368888 Cleaning after the job
1029 03:12:57.369512 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/ramdisk
1030 03:12:57.370928 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/kernel
1031 03:12:57.414982 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/dtb
1032 03:12:57.416193 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/nfsrootfs
1033 03:12:57.720387 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950252/tftp-deploy-s17t03ab/modules
1034 03:12:57.740733 start: 4.1 power-off (timeout 00:00:30) [common]
1035 03:12:57.741392 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1036 03:12:57.778998 >> OK - accepted request
1037 03:12:57.780745 Returned 0 in 0 seconds
1038 03:12:57.881508 end: 4.1 power-off (duration 00:00:00) [common]
1040 03:12:57.882516 start: 4.2 read-feedback (timeout 00:10:00) [common]
1041 03:12:57.883164 Listened to connection for namespace 'common' for up to 1s
1042 03:12:58.883140 Finalising connection for namespace 'common'
1043 03:12:58.883627 Disconnecting from shell: Finalise
1044 03:12:58.883906 =>
1045 03:12:58.984674 end: 4.2 read-feedback (duration 00:00:01) [common]
1046 03:12:58.985127 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950252
1047 03:13:01.922789 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950252
1048 03:13:01.923404 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.