Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:11:02.775002 lava-dispatcher, installed at version: 2024.01
2 01:11:02.775763 start: 0 validate
3 01:11:02.776292 Start time: 2024-11-07 01:11:02.776261+00:00 (UTC)
4 01:11:02.776832 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:11:02.777381 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 01:11:02.819837 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:11:02.820428 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:11:02.853762 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:11:02.854412 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:11:03.903151 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:11:03.903689 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 01:11:03.950800 validate duration: 1.17
14 01:11:03.952474 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:11:03.952857 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:11:03.953298 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:11:03.954290 Not decompressing ramdisk as can be used compressed.
18 01:11:03.955024 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 01:11:03.955482 saving as /var/lib/lava/dispatcher/tmp/950786/tftp-deploy-4dxw_qhd/ramdisk/rootfs.cpio.gz
20 01:11:03.955964 total size: 8181887 (7 MB)
21 01:11:03.991657 progress 0 % (0 MB)
22 01:11:04.004391 progress 5 % (0 MB)
23 01:11:04.016047 progress 10 % (0 MB)
24 01:11:04.028194 progress 15 % (1 MB)
25 01:11:04.033764 progress 20 % (1 MB)
26 01:11:04.039558 progress 25 % (1 MB)
27 01:11:04.045073 progress 30 % (2 MB)
28 01:11:04.050943 progress 35 % (2 MB)
29 01:11:04.056449 progress 40 % (3 MB)
30 01:11:04.062226 progress 45 % (3 MB)
31 01:11:04.067705 progress 50 % (3 MB)
32 01:11:04.073611 progress 55 % (4 MB)
33 01:11:04.079066 progress 60 % (4 MB)
34 01:11:04.084873 progress 65 % (5 MB)
35 01:11:04.090277 progress 70 % (5 MB)
36 01:11:04.096110 progress 75 % (5 MB)
37 01:11:04.101431 progress 80 % (6 MB)
38 01:11:04.107196 progress 85 % (6 MB)
39 01:11:04.112527 progress 90 % (7 MB)
40 01:11:04.118337 progress 95 % (7 MB)
41 01:11:04.123359 progress 100 % (7 MB)
42 01:11:04.124036 7 MB downloaded in 0.17 s (46.43 MB/s)
43 01:11:04.124611 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:11:04.125544 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:11:04.125861 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:11:04.126146 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:11:04.126674 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/kernel/Image
49 01:11:04.126935 saving as /var/lib/lava/dispatcher/tmp/950786/tftp-deploy-4dxw_qhd/kernel/Image
50 01:11:04.127162 total size: 45713920 (43 MB)
51 01:11:04.127390 No compression specified
52 01:11:04.161541 progress 0 % (0 MB)
53 01:11:04.189791 progress 5 % (2 MB)
54 01:11:04.218370 progress 10 % (4 MB)
55 01:11:04.247114 progress 15 % (6 MB)
56 01:11:04.275815 progress 20 % (8 MB)
57 01:11:04.304413 progress 25 % (10 MB)
58 01:11:04.332690 progress 30 % (13 MB)
59 01:11:04.361452 progress 35 % (15 MB)
60 01:11:04.390050 progress 40 % (17 MB)
61 01:11:04.417870 progress 45 % (19 MB)
62 01:11:04.446110 progress 50 % (21 MB)
63 01:11:04.473916 progress 55 % (24 MB)
64 01:11:04.501948 progress 60 % (26 MB)
65 01:11:04.529289 progress 65 % (28 MB)
66 01:11:04.556934 progress 70 % (30 MB)
67 01:11:04.584543 progress 75 % (32 MB)
68 01:11:04.612669 progress 80 % (34 MB)
69 01:11:04.639977 progress 85 % (37 MB)
70 01:11:04.667652 progress 90 % (39 MB)
71 01:11:04.695443 progress 95 % (41 MB)
72 01:11:04.722748 progress 100 % (43 MB)
73 01:11:04.723265 43 MB downloaded in 0.60 s (73.14 MB/s)
74 01:11:04.723752 end: 1.2.1 http-download (duration 00:00:01) [common]
76 01:11:04.724614 end: 1.2 download-retry (duration 00:00:01) [common]
77 01:11:04.724888 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:11:04.725151 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:11:04.725710 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 01:11:04.725998 saving as /var/lib/lava/dispatcher/tmp/950786/tftp-deploy-4dxw_qhd/dtb/meson-g12b-a311d-libretech-cc.dtb
81 01:11:04.726209 total size: 54703 (0 MB)
82 01:11:04.726421 No compression specified
83 01:11:04.760890 progress 59 % (0 MB)
84 01:11:04.761732 progress 100 % (0 MB)
85 01:11:04.762278 0 MB downloaded in 0.04 s (1.45 MB/s)
86 01:11:04.762772 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:11:04.763592 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:11:04.763854 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:11:04.764157 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:11:04.764640 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/modules.tar.xz
92 01:11:04.764919 saving as /var/lib/lava/dispatcher/tmp/950786/tftp-deploy-4dxw_qhd/modules/modules.tar
93 01:11:04.765135 total size: 11618152 (11 MB)
94 01:11:04.765348 Using unxz to decompress xz
95 01:11:04.800742 progress 0 % (0 MB)
96 01:11:04.877825 progress 5 % (0 MB)
97 01:11:04.964587 progress 10 % (1 MB)
98 01:11:05.077048 progress 15 % (1 MB)
99 01:11:05.185558 progress 20 % (2 MB)
100 01:11:05.279001 progress 25 % (2 MB)
101 01:11:05.354807 progress 30 % (3 MB)
102 01:11:05.432454 progress 35 % (3 MB)
103 01:11:05.505323 progress 40 % (4 MB)
104 01:11:05.579837 progress 45 % (5 MB)
105 01:11:05.664118 progress 50 % (5 MB)
106 01:11:05.744868 progress 55 % (6 MB)
107 01:11:05.825865 progress 60 % (6 MB)
108 01:11:05.907411 progress 65 % (7 MB)
109 01:11:05.987036 progress 70 % (7 MB)
110 01:11:06.064515 progress 75 % (8 MB)
111 01:11:06.147221 progress 80 % (8 MB)
112 01:11:06.229669 progress 85 % (9 MB)
113 01:11:06.313093 progress 90 % (10 MB)
114 01:11:06.386460 progress 95 % (10 MB)
115 01:11:06.463499 progress 100 % (11 MB)
116 01:11:06.475993 11 MB downloaded in 1.71 s (6.48 MB/s)
117 01:11:06.477052 end: 1.4.1 http-download (duration 00:00:02) [common]
119 01:11:06.478819 end: 1.4 download-retry (duration 00:00:02) [common]
120 01:11:06.479397 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 01:11:06.479974 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 01:11:06.480560 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:11:06.481121 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 01:11:06.482305 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08
125 01:11:06.483222 makedir: /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin
126 01:11:06.483916 makedir: /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/tests
127 01:11:06.484652 makedir: /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/results
128 01:11:06.485332 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-add-keys
129 01:11:06.486401 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-add-sources
130 01:11:06.487463 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-background-process-start
131 01:11:06.488555 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-background-process-stop
132 01:11:06.489653 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-common-functions
133 01:11:06.490654 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-echo-ipv4
134 01:11:06.491636 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-install-packages
135 01:11:06.492667 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-installed-packages
136 01:11:06.493645 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-os-build
137 01:11:06.494620 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-probe-channel
138 01:11:06.495587 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-probe-ip
139 01:11:06.496627 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-target-ip
140 01:11:06.497613 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-target-mac
141 01:11:06.498584 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-target-storage
142 01:11:06.499578 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-test-case
143 01:11:06.500653 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-test-event
144 01:11:06.501684 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-test-feedback
145 01:11:06.502715 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-test-raise
146 01:11:06.503691 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-test-reference
147 01:11:06.504738 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-test-runner
148 01:11:06.505734 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-test-set
149 01:11:06.506719 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-test-shell
150 01:11:06.507753 Updating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-install-packages (oe)
151 01:11:06.508913 Updating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/bin/lava-installed-packages (oe)
152 01:11:06.509859 Creating /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/environment
153 01:11:06.510656 LAVA metadata
154 01:11:06.511200 - LAVA_JOB_ID=950786
155 01:11:06.511680 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:11:06.512487 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 01:11:06.514469 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:11:06.515149 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 01:11:06.515617 skipped lava-vland-overlay
160 01:11:06.516249 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:11:06.516781 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 01:11:06.517235 skipped lava-multinode-overlay
163 01:11:06.517725 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:11:06.518235 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 01:11:06.518725 Loading test definitions
166 01:11:06.519281 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 01:11:06.519727 Using /lava-950786 at stage 0
168 01:11:06.521217 uuid=950786_1.5.2.4.1 testdef=None
169 01:11:06.521564 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:11:06.521845 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 01:11:06.523758 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:11:06.524634 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 01:11:06.526969 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:11:06.527846 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 01:11:06.530171 runner path: /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/0/tests/0_dmesg test_uuid 950786_1.5.2.4.1
178 01:11:06.530786 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:11:06.531597 Creating lava-test-runner.conf files
181 01:11:06.531804 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950786/lava-overlay-0xvp5i08/lava-950786/0 for stage 0
182 01:11:06.532196 - 0_dmesg
183 01:11:06.532585 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:11:06.532882 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 01:11:06.557157 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:11:06.557603 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 01:11:06.557871 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:11:06.558144 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:11:06.558411 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 01:11:07.485882 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 01:11:07.486357 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 01:11:07.486605 extracting modules file /var/lib/lava/dispatcher/tmp/950786/tftp-deploy-4dxw_qhd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950786/extract-overlay-ramdisk-gb687mu8/ramdisk
193 01:11:08.790141 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 01:11:08.790607 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 01:11:08.790881 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950786/compress-overlay-7a4huoh8/overlay-1.5.2.5.tar.gz to ramdisk
196 01:11:08.791098 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950786/compress-overlay-7a4huoh8/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950786/extract-overlay-ramdisk-gb687mu8/ramdisk
197 01:11:08.821372 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:11:08.821786 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 01:11:08.822060 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 01:11:08.822290 Converting downloaded kernel to a uImage
201 01:11:08.822598 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/950786/tftp-deploy-4dxw_qhd/kernel/Image /var/lib/lava/dispatcher/tmp/950786/tftp-deploy-4dxw_qhd/kernel/uImage
202 01:11:09.293653 output: Image Name:
203 01:11:09.294078 output: Created: Thu Nov 7 01:11:08 2024
204 01:11:09.294289 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:11:09.294496 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 01:11:09.294697 output: Load Address: 01080000
207 01:11:09.294895 output: Entry Point: 01080000
208 01:11:09.295093 output:
209 01:11:09.295428 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 01:11:09.295699 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 01:11:09.295973 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 01:11:09.296279 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:11:09.296543 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 01:11:09.296800 Building ramdisk /var/lib/lava/dispatcher/tmp/950786/extract-overlay-ramdisk-gb687mu8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950786/extract-overlay-ramdisk-gb687mu8/ramdisk
215 01:11:11.611481 >> 181608 blocks
216 01:11:20.055010 Adding RAMdisk u-boot header.
217 01:11:20.055458 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950786/extract-overlay-ramdisk-gb687mu8/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950786/extract-overlay-ramdisk-gb687mu8/ramdisk.cpio.gz.uboot
218 01:11:20.343385 output: Image Name:
219 01:11:20.343791 output: Created: Thu Nov 7 01:11:20 2024
220 01:11:20.344053 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:11:20.344469 output: Data Size: 26061731 Bytes = 25450.91 KiB = 24.85 MiB
222 01:11:20.344880 output: Load Address: 00000000
223 01:11:20.345293 output: Entry Point: 00000000
224 01:11:20.345692 output:
225 01:11:20.346666 rename /var/lib/lava/dispatcher/tmp/950786/extract-overlay-ramdisk-gb687mu8/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950786/tftp-deploy-4dxw_qhd/ramdisk/ramdisk.cpio.gz.uboot
226 01:11:20.347370 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 01:11:20.347913 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 01:11:20.348485 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 01:11:20.348938 No LXC device requested
230 01:11:20.349435 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:11:20.349938 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 01:11:20.350422 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:11:20.350831 Checking files for TFTP limit of 4294967296 bytes.
234 01:11:20.353512 end: 1 tftp-deploy (duration 00:00:16) [common]
235 01:11:20.354085 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:11:20.354599 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:11:20.355087 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:11:20.355599 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:11:20.356144 Using kernel file from prepare-kernel: 950786/tftp-deploy-4dxw_qhd/kernel/uImage
240 01:11:20.356751 substitutions:
241 01:11:20.357156 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:11:20.357557 - {DTB_ADDR}: 0x01070000
243 01:11:20.357954 - {DTB}: 950786/tftp-deploy-4dxw_qhd/dtb/meson-g12b-a311d-libretech-cc.dtb
244 01:11:20.358352 - {INITRD}: 950786/tftp-deploy-4dxw_qhd/ramdisk/ramdisk.cpio.gz.uboot
245 01:11:20.358746 - {KERNEL_ADDR}: 0x01080000
246 01:11:20.359139 - {KERNEL}: 950786/tftp-deploy-4dxw_qhd/kernel/uImage
247 01:11:20.359530 - {LAVA_MAC}: None
248 01:11:20.359957 - {PRESEED_CONFIG}: None
249 01:11:20.360386 - {PRESEED_LOCAL}: None
250 01:11:20.360776 - {RAMDISK_ADDR}: 0x08000000
251 01:11:20.361164 - {RAMDISK}: 950786/tftp-deploy-4dxw_qhd/ramdisk/ramdisk.cpio.gz.uboot
252 01:11:20.361556 - {ROOT_PART}: None
253 01:11:20.361946 - {ROOT}: None
254 01:11:20.362336 - {SERVER_IP}: 192.168.6.2
255 01:11:20.362727 - {TEE_ADDR}: 0x83000000
256 01:11:20.363115 - {TEE}: None
257 01:11:20.363500 Parsed boot commands:
258 01:11:20.363874 - setenv autoload no
259 01:11:20.364290 - setenv initrd_high 0xffffffff
260 01:11:20.364675 - setenv fdt_high 0xffffffff
261 01:11:20.365060 - dhcp
262 01:11:20.365444 - setenv serverip 192.168.6.2
263 01:11:20.365825 - tftpboot 0x01080000 950786/tftp-deploy-4dxw_qhd/kernel/uImage
264 01:11:20.366210 - tftpboot 0x08000000 950786/tftp-deploy-4dxw_qhd/ramdisk/ramdisk.cpio.gz.uboot
265 01:11:20.366592 - tftpboot 0x01070000 950786/tftp-deploy-4dxw_qhd/dtb/meson-g12b-a311d-libretech-cc.dtb
266 01:11:20.366980 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:11:20.367370 - bootm 0x01080000 0x08000000 0x01070000
268 01:11:20.367861 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:11:20.369364 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:11:20.369802 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 01:11:20.384439 Setting prompt string to ['lava-test: # ']
273 01:11:20.385927 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:11:20.386520 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:11:20.387076 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:11:20.387668 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:11:20.388894 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 01:11:20.425522 >> OK - accepted request
279 01:11:20.427354 Returned 0 in 0 seconds
280 01:11:20.528487 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:11:20.530038 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:11:20.530599 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:11:20.531100 Setting prompt string to ['Hit any key to stop autoboot']
285 01:11:20.531547 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:11:20.533155 Trying 192.168.56.21...
287 01:11:20.533651 Connected to conserv1.
288 01:11:20.534068 Escape character is '^]'.
289 01:11:20.534474
290 01:11:20.534894 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 01:11:20.535314
292 01:11:32.291736 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 01:11:32.292454 bl2_stage_init 0x01
294 01:11:32.292915 bl2_stage_init 0x81
295 01:11:32.296894 hw id: 0x0000 - pwm id 0x01
296 01:11:32.297413 bl2_stage_init 0xc1
297 01:11:32.297878 bl2_stage_init 0x02
298 01:11:32.298303
299 01:11:32.302411 L0:00000000
300 01:11:32.302862 L1:20000703
301 01:11:32.303272 L2:00008067
302 01:11:32.303676 L3:14000000
303 01:11:32.308013 B2:00402000
304 01:11:32.308442 B1:e0f83180
305 01:11:32.308847
306 01:11:32.309253 TE: 58159
307 01:11:32.309647
308 01:11:32.313602 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 01:11:32.314024
310 01:11:32.314419 Board ID = 1
311 01:11:32.319227 Set A53 clk to 24M
312 01:11:32.319646 Set A73 clk to 24M
313 01:11:32.320068 Set clk81 to 24M
314 01:11:32.324825 A53 clk: 1200 MHz
315 01:11:32.325241 A73 clk: 1200 MHz
316 01:11:32.325632 CLK81: 166.6M
317 01:11:32.326023 smccc: 00012ab5
318 01:11:32.330372 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 01:11:32.336030 board id: 1
320 01:11:32.341914 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:11:32.352515 fw parse done
322 01:11:32.358444 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:11:32.400997 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:11:32.411947 PIEI prepare done
325 01:11:32.412403 fastboot data load
326 01:11:32.412800 fastboot data verify
327 01:11:32.417565 verify result: 266
328 01:11:32.423183 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 01:11:32.423646 LPDDR4 probe
330 01:11:32.424091 ddr clk to 1584MHz
331 01:11:32.431139 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:11:32.468417
333 01:11:32.468852 dmc_version 0001
334 01:11:32.475074 Check phy result
335 01:11:32.480914 INFO : End of CA training
336 01:11:32.481342 INFO : End of initialization
337 01:11:32.486553 INFO : Training has run successfully!
338 01:11:32.486979 Check phy result
339 01:11:32.492239 INFO : End of initialization
340 01:11:32.492665 INFO : End of read enable training
341 01:11:32.495451 INFO : End of fine write leveling
342 01:11:32.500992 INFO : End of Write leveling coarse delay
343 01:11:32.506573 INFO : Training has run successfully!
344 01:11:32.506997 Check phy result
345 01:11:32.507404 INFO : End of initialization
346 01:11:32.512330 INFO : End of read dq deskew training
347 01:11:32.515560 INFO : End of MPR read delay center optimization
348 01:11:32.521100 INFO : End of write delay center optimization
349 01:11:32.526726 INFO : End of read delay center optimization
350 01:11:32.527163 INFO : End of max read latency training
351 01:11:32.532313 INFO : Training has run successfully!
352 01:11:32.532737 1D training succeed
353 01:11:32.540558 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:11:32.588182 Check phy result
355 01:11:32.588627 INFO : End of initialization
356 01:11:32.609752 INFO : End of 2D read delay Voltage center optimization
357 01:11:32.629876 INFO : End of 2D read delay Voltage center optimization
358 01:11:32.681789 INFO : End of 2D write delay Voltage center optimization
359 01:11:32.731028 INFO : End of 2D write delay Voltage center optimization
360 01:11:32.736529 INFO : Training has run successfully!
361 01:11:32.736983
362 01:11:32.737403 channel==0
363 01:11:32.742141 RxClkDly_Margin_A0==88 ps 9
364 01:11:32.742589 TxDqDly_Margin_A0==98 ps 10
365 01:11:32.747708 RxClkDly_Margin_A1==88 ps 9
366 01:11:32.748199 TxDqDly_Margin_A1==98 ps 10
367 01:11:32.748622 TrainedVREFDQ_A0==74
368 01:11:32.753346 TrainedVREFDQ_A1==76
369 01:11:32.753797 VrefDac_Margin_A0==25
370 01:11:32.754204 DeviceVref_Margin_A0==40
371 01:11:32.758975 VrefDac_Margin_A1==25
372 01:11:32.759444 DeviceVref_Margin_A1==38
373 01:11:32.759867
374 01:11:32.760307
375 01:11:32.764532 channel==1
376 01:11:32.764979 RxClkDly_Margin_A0==98 ps 10
377 01:11:32.765388 TxDqDly_Margin_A0==98 ps 10
378 01:11:32.770106 RxClkDly_Margin_A1==98 ps 10
379 01:11:32.770550 TxDqDly_Margin_A1==88 ps 9
380 01:11:32.775698 TrainedVREFDQ_A0==77
381 01:11:32.776163 TrainedVREFDQ_A1==77
382 01:11:32.776575 VrefDac_Margin_A0==22
383 01:11:32.781413 DeviceVref_Margin_A0==37
384 01:11:32.781860 VrefDac_Margin_A1==22
385 01:11:32.786955 DeviceVref_Margin_A1==37
386 01:11:32.787407
387 01:11:32.787829 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:11:32.793555
389 01:11:32.820525 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 01:11:32.821162 2D training succeed
391 01:11:32.826194 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:11:32.831815 auto size-- 65535DDR cs0 size: 2048MB
393 01:11:32.832333 DDR cs1 size: 2048MB
394 01:11:32.837387 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:11:32.837845 cs0 DataBus test pass
396 01:11:32.842982 cs1 DataBus test pass
397 01:11:32.843429 cs0 AddrBus test pass
398 01:11:32.843836 cs1 AddrBus test pass
399 01:11:32.844271
400 01:11:32.848498 100bdlr_step_size ps== 420
401 01:11:32.848978 result report
402 01:11:32.854137 boot times 0Enable ddr reg access
403 01:11:32.858630 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:11:32.873075 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 01:11:33.445044 0.0;M3 CHK:0;cm4_sp_mode 0
406 01:11:33.445603 MVN_1=0x00000000
407 01:11:33.450626 MVN_2=0x00000000
408 01:11:33.456401 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 01:11:33.456845 OPS=0x10
410 01:11:33.457260 ring efuse init
411 01:11:33.457664 chipver efuse init
412 01:11:33.461879 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 01:11:33.467478 [0.018961 Inits done]
414 01:11:33.467912 secure task start!
415 01:11:33.468382 high task start!
416 01:11:33.471548 low task start!
417 01:11:33.472009 run into bl31
418 01:11:33.478721 NOTICE: BL31: v1.3(release):4fc40b1
419 01:11:33.485801 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 01:11:33.486242 NOTICE: BL31: G12A normal boot!
421 01:11:33.511904 NOTICE: BL31: BL33 decompress pass
422 01:11:33.517012 ERROR: Error initializing runtime service opteed_fast
423 01:11:34.750517
424 01:11:34.751121
425 01:11:34.758924 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 01:11:34.759478
427 01:11:34.759911 Model: Libre Computer AML-A311D-CC Alta
428 01:11:34.966524 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 01:11:34.990558 DRAM: 2 GiB (effective 3.8 GiB)
430 01:11:35.133769 Core: 408 devices, 31 uclasses, devicetree: separate
431 01:11:35.139699 WDT: Not starting watchdog@f0d0
432 01:11:35.171878 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 01:11:35.184429 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 01:11:35.188501 ** Bad device specification mmc 0 **
435 01:11:35.199636 Card did not respond to voltage select! : -110
436 01:11:35.206779 ** Bad device specification mmc 0 **
437 01:11:35.207299 Couldn't find partition mmc 0
438 01:11:35.215712 Card did not respond to voltage select! : -110
439 01:11:35.221192 ** Bad device specification mmc 0 **
440 01:11:35.221790 Couldn't find partition mmc 0
441 01:11:35.225416 Error: could not access storage.
442 01:11:36.491807 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 01:11:36.492429 bl2_stage_init 0x01
444 01:11:36.492847 bl2_stage_init 0x81
445 01:11:36.497243 hw id: 0x0000 - pwm id 0x01
446 01:11:36.497790 bl2_stage_init 0xc1
447 01:11:36.498199 bl2_stage_init 0x02
448 01:11:36.498596
449 01:11:36.502862 L0:00000000
450 01:11:36.503329 L1:20000703
451 01:11:36.503754 L2:00008067
452 01:11:36.504238 L3:14000000
453 01:11:36.508465 B2:00402000
454 01:11:36.508925 B1:e0f83180
455 01:11:36.509319
456 01:11:36.509713 TE: 58167
457 01:11:36.510107
458 01:11:36.513981 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 01:11:36.514437
460 01:11:36.514865 Board ID = 1
461 01:11:36.519580 Set A53 clk to 24M
462 01:11:36.520091 Set A73 clk to 24M
463 01:11:36.520513 Set clk81 to 24M
464 01:11:36.525190 A53 clk: 1200 MHz
465 01:11:36.525698 A73 clk: 1200 MHz
466 01:11:36.526117 CLK81: 166.6M
467 01:11:36.526527 smccc: 00012abe
468 01:11:36.530845 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 01:11:36.536510 board id: 1
470 01:11:36.541324 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 01:11:36.552952 fw parse done
472 01:11:36.558369 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 01:11:36.601584 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 01:11:36.612484 PIEI prepare done
475 01:11:36.612952 fastboot data load
476 01:11:36.613362 fastboot data verify
477 01:11:36.618095 verify result: 266
478 01:11:36.623755 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 01:11:36.624259 LPDDR4 probe
480 01:11:36.624667 ddr clk to 1584MHz
481 01:11:36.630892 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 01:11:36.668447
483 01:11:36.669152 dmc_version 0001
484 01:11:36.674945 Check phy result
485 01:11:36.681683 INFO : End of CA training
486 01:11:36.682402 INFO : End of initialization
487 01:11:36.687232 INFO : Training has run successfully!
488 01:11:36.687791 Check phy result
489 01:11:36.692878 INFO : End of initialization
490 01:11:36.693588 INFO : End of read enable training
491 01:11:36.698479 INFO : End of fine write leveling
492 01:11:36.704085 INFO : End of Write leveling coarse delay
493 01:11:36.704746 INFO : Training has run successfully!
494 01:11:36.705386 Check phy result
495 01:11:36.709746 INFO : End of initialization
496 01:11:36.710394 INFO : End of read dq deskew training
497 01:11:36.715241 INFO : End of MPR read delay center optimization
498 01:11:36.720814 INFO : End of write delay center optimization
499 01:11:36.726385 INFO : End of read delay center optimization
500 01:11:36.727171 INFO : End of max read latency training
501 01:11:36.732097 INFO : Training has run successfully!
502 01:11:36.732653 1D training succeed
503 01:11:36.740225 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 01:11:36.788248 Check phy result
505 01:11:36.788819 INFO : End of initialization
506 01:11:36.810130 INFO : End of 2D read delay Voltage center optimization
507 01:11:36.829008 INFO : End of 2D read delay Voltage center optimization
508 01:11:36.881735 INFO : End of 2D write delay Voltage center optimization
509 01:11:36.931341 INFO : End of 2D write delay Voltage center optimization
510 01:11:36.936896 INFO : Training has run successfully!
511 01:11:36.937611
512 01:11:36.938253 channel==0
513 01:11:36.942612 RxClkDly_Margin_A0==88 ps 9
514 01:11:36.943262 TxDqDly_Margin_A0==98 ps 10
515 01:11:36.945821 RxClkDly_Margin_A1==88 ps 9
516 01:11:36.946450 TxDqDly_Margin_A1==98 ps 10
517 01:11:36.951416 TrainedVREFDQ_A0==74
518 01:11:36.952141 TrainedVREFDQ_A1==74
519 01:11:36.957123 VrefDac_Margin_A0==25
520 01:11:36.957778 DeviceVref_Margin_A0==40
521 01:11:36.958357 VrefDac_Margin_A1==25
522 01:11:36.962593 DeviceVref_Margin_A1==40
523 01:11:36.963241
524 01:11:36.963816
525 01:11:36.964425 channel==1
526 01:11:36.965047 RxClkDly_Margin_A0==88 ps 9
527 01:11:36.968155 TxDqDly_Margin_A0==98 ps 10
528 01:11:36.968853 RxClkDly_Margin_A1==88 ps 9
529 01:11:36.973765 TxDqDly_Margin_A1==88 ps 9
530 01:11:36.974403 TrainedVREFDQ_A0==77
531 01:11:36.974981 TrainedVREFDQ_A1==77
532 01:11:36.979406 VrefDac_Margin_A0==23
533 01:11:36.980141 DeviceVref_Margin_A0==37
534 01:11:36.984951 VrefDac_Margin_A1==24
535 01:11:36.985597 DeviceVref_Margin_A1==37
536 01:11:36.986166
537 01:11:36.990630 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 01:11:36.991329
539 01:11:37.018549 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 01:11:37.024270 2D training succeed
541 01:11:37.029840 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 01:11:37.030494 auto size-- 65535DDR cs0 size: 2048MB
543 01:11:37.035350 DDR cs1 size: 2048MB
544 01:11:37.036030 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 01:11:37.040993 cs0 DataBus test pass
546 01:11:37.041683 cs1 DataBus test pass
547 01:11:37.042280 cs0 AddrBus test pass
548 01:11:37.046540 cs1 AddrBus test pass
549 01:11:37.047186
550 01:11:37.047831 100bdlr_step_size ps== 420
551 01:11:37.048509 result report
552 01:11:37.052234 boot times 0Enable ddr reg access
553 01:11:37.058889 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 01:11:37.072640 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 01:11:37.646936 0.0;M3 CHK:0;cm4_sp_mode 0
556 01:11:37.647547 MVN_1=0x00000000
557 01:11:37.652480 MVN_2=0x00000000
558 01:11:37.658171 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 01:11:37.658850 OPS=0x10
560 01:11:37.659336 ring efuse init
561 01:11:37.659962 chipver efuse init
562 01:11:37.663805 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 01:11:37.669490 [0.018961 Inits done]
564 01:11:37.670095 secure task start!
565 01:11:37.670621 high task start!
566 01:11:37.673835 low task start!
567 01:11:37.674489 run into bl31
568 01:11:37.680826 NOTICE: BL31: v1.3(release):4fc40b1
569 01:11:37.687810 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 01:11:37.688483 NOTICE: BL31: G12A normal boot!
571 01:11:37.713971 NOTICE: BL31: BL33 decompress pass
572 01:11:37.718652 ERROR: Error initializing runtime service opteed_fast
573 01:11:38.952614
574 01:11:38.953018
575 01:11:38.959834 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 01:11:38.960200
577 01:11:38.960464 Model: Libre Computer AML-A311D-CC Alta
578 01:11:39.169276 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 01:11:39.191951 DRAM: 2 GiB (effective 3.8 GiB)
580 01:11:39.335760 Core: 408 devices, 31 uclasses, devicetree: separate
581 01:11:39.341493 WDT: Not starting watchdog@f0d0
582 01:11:39.373795 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 01:11:39.386173 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 01:11:39.391173 ** Bad device specification mmc 0 **
585 01:11:39.401494 Card did not respond to voltage select! : -110
586 01:11:39.408379 ** Bad device specification mmc 0 **
587 01:11:39.409018 Couldn't find partition mmc 0
588 01:11:39.417451 Card did not respond to voltage select! : -110
589 01:11:39.423094 ** Bad device specification mmc 0 **
590 01:11:39.423656 Couldn't find partition mmc 0
591 01:11:39.427099 Error: could not access storage.
592 01:11:39.770629 Net: eth0: ethernet@ff3f0000
593 01:11:39.771374 starting USB...
594 01:11:40.022416 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 01:11:40.023179 Starting the controller
596 01:11:40.029427 USB XHCI 1.10
597 01:11:41.740603 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
598 01:11:41.741422 bl2_stage_init 0x81
599 01:11:41.746129 hw id: 0x0000 - pwm id 0x01
600 01:11:41.746732 bl2_stage_init 0xc1
601 01:11:41.747264 bl2_stage_init 0x02
602 01:11:41.747792
603 01:11:41.751769 L0:00000000
604 01:11:41.752409 L1:20000703
605 01:11:41.752934 L2:00008067
606 01:11:41.753452 L3:14000000
607 01:11:41.753957 B2:00402000
608 01:11:41.758822 B1:e0f83180
609 01:11:41.759411
610 01:11:41.759846 TE: 58150
611 01:11:41.760302
612 01:11:41.763016 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 01:11:41.763470
614 01:11:41.763870 Board ID = 1
615 01:11:41.768778 Set A53 clk to 24M
616 01:11:41.769272 Set A73 clk to 24M
617 01:11:41.769675 Set clk81 to 24M
618 01:11:41.774101 A53 clk: 1200 MHz
619 01:11:41.774551 A73 clk: 1200 MHz
620 01:11:41.775083 CLK81: 166.6M
621 01:11:41.775489 smccc: 00012aac
622 01:11:41.784529 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 01:11:41.785028 board id: 1
624 01:11:41.791262 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 01:11:41.801872 fw parse done
626 01:11:41.807870 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 01:11:41.850337 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 01:11:41.861265 PIEI prepare done
629 01:11:41.861756 fastboot data load
630 01:11:41.862160 fastboot data verify
631 01:11:41.866801 verify result: 266
632 01:11:41.872424 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 01:11:41.872904 LPDDR4 probe
634 01:11:41.873307 ddr clk to 1584MHz
635 01:11:41.880411 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 01:11:41.917810
637 01:11:41.918325 dmc_version 0001
638 01:11:41.924373 Check phy result
639 01:11:41.930178 INFO : End of CA training
640 01:11:41.930630 INFO : End of initialization
641 01:11:41.935786 INFO : Training has run successfully!
642 01:11:41.936283 Check phy result
643 01:11:41.941410 INFO : End of initialization
644 01:11:41.941916 INFO : End of read enable training
645 01:11:41.946971 INFO : End of fine write leveling
646 01:11:41.952635 INFO : End of Write leveling coarse delay
647 01:11:41.953100 INFO : Training has run successfully!
648 01:11:41.953502 Check phy result
649 01:11:41.958187 INFO : End of initialization
650 01:11:41.958781 INFO : End of read dq deskew training
651 01:11:41.963778 INFO : End of MPR read delay center optimization
652 01:11:41.969363 INFO : End of write delay center optimization
653 01:11:41.974964 INFO : End of read delay center optimization
654 01:11:41.975417 INFO : End of max read latency training
655 01:11:41.980611 INFO : Training has run successfully!
656 01:11:41.981058 1D training succeed
657 01:11:41.989752 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 01:11:42.036460 Check phy result
659 01:11:42.036959 INFO : End of initialization
660 01:11:42.059904 INFO : End of 2D read delay Voltage center optimization
661 01:11:42.079153 INFO : End of 2D read delay Voltage center optimization
662 01:11:42.132230 INFO : End of 2D write delay Voltage center optimization
663 01:11:42.181582 INFO : End of 2D write delay Voltage center optimization
664 01:11:42.187112 INFO : Training has run successfully!
665 01:11:42.187590
666 01:11:42.188026 channel==0
667 01:11:42.192780 RxClkDly_Margin_A0==88 ps 9
668 01:11:42.193250 TxDqDly_Margin_A0==98 ps 10
669 01:11:42.198293 RxClkDly_Margin_A1==88 ps 9
670 01:11:42.198742 TxDqDly_Margin_A1==98 ps 10
671 01:11:42.199142 TrainedVREFDQ_A0==74
672 01:11:42.203921 TrainedVREFDQ_A1==74
673 01:11:42.204400 VrefDac_Margin_A0==24
674 01:11:42.204795 DeviceVref_Margin_A0==40
675 01:11:42.209499 VrefDac_Margin_A1==24
676 01:11:42.209943 DeviceVref_Margin_A1==40
677 01:11:42.210334
678 01:11:42.210903
679 01:11:42.215094 channel==1
680 01:11:42.215545 RxClkDly_Margin_A0==98 ps 10
681 01:11:42.215942 TxDqDly_Margin_A0==98 ps 10
682 01:11:42.220735 RxClkDly_Margin_A1==88 ps 9
683 01:11:42.221205 TxDqDly_Margin_A1==98 ps 10
684 01:11:42.226286 TrainedVREFDQ_A0==77
685 01:11:42.226737 TrainedVREFDQ_A1==78
686 01:11:42.227134 VrefDac_Margin_A0==22
687 01:11:42.231888 DeviceVref_Margin_A0==37
688 01:11:42.232367 VrefDac_Margin_A1==24
689 01:11:42.237511 DeviceVref_Margin_A1==36
690 01:11:42.238000
691 01:11:42.238397 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 01:11:42.243114
693 01:11:42.271096 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000018 00000019 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
694 01:11:42.271613 2D training succeed
695 01:11:42.276712 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 01:11:42.282305 auto size-- 65535DDR cs0 size: 2048MB
697 01:11:42.282781 DDR cs1 size: 2048MB
698 01:11:42.287921 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 01:11:42.288415 cs0 DataBus test pass
700 01:11:42.293506 cs1 DataBus test pass
701 01:11:42.293962 cs0 AddrBus test pass
702 01:11:42.294359 cs1 AddrBus test pass
703 01:11:42.294748
704 01:11:42.299190 100bdlr_step_size ps== 420
705 01:11:42.299700 result report
706 01:11:42.304777 boot times 0Enable ddr reg access
707 01:11:42.310154 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 01:11:42.322841 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 01:11:42.896788 0.0;M3 CHK:0;cm4_sp_mode 0
710 01:11:42.897375 MVN_1=0x00000000
711 01:11:42.902253 MVN_2=0x00000000
712 01:11:42.908054 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 01:11:42.908571 OPS=0x10
714 01:11:42.908975 ring efuse init
715 01:11:42.909363 chipver efuse init
716 01:11:42.916396 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 01:11:42.916866 [0.018960 Inits done]
718 01:11:42.917261 secure task start!
719 01:11:42.923881 high task start!
720 01:11:42.924363 low task start!
721 01:11:42.924754 run into bl31
722 01:11:42.930477 NOTICE: BL31: v1.3(release):4fc40b1
723 01:11:42.938268 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 01:11:42.938759 NOTICE: BL31: G12A normal boot!
725 01:11:42.963651 NOTICE: BL31: BL33 decompress pass
726 01:11:42.969324 ERROR: Error initializing runtime service opteed_fast
727 01:11:44.202169
728 01:11:44.202775
729 01:11:44.210127 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 01:11:44.210591
731 01:11:44.210998 Model: Libre Computer AML-A311D-CC Alta
732 01:11:44.418961 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 01:11:44.441468 DRAM: 2 GiB (effective 3.8 GiB)
734 01:11:44.585328 Core: 408 devices, 31 uclasses, devicetree: separate
735 01:11:44.590337 WDT: Not starting watchdog@f0d0
736 01:11:44.623446 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 01:11:44.636013 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 01:11:44.640279 ** Bad device specification mmc 0 **
739 01:11:44.651243 Card did not respond to voltage select! : -110
740 01:11:44.657970 ** Bad device specification mmc 0 **
741 01:11:44.658417 Couldn't find partition mmc 0
742 01:11:44.667242 Card did not respond to voltage select! : -110
743 01:11:44.672751 ** Bad device specification mmc 0 **
744 01:11:44.673196 Couldn't find partition mmc 0
745 01:11:44.677534 Error: could not access storage.
746 01:11:45.019345 Net: eth0: ethernet@ff3f0000
747 01:11:45.019895 starting USB...
748 01:11:45.272288 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 01:11:45.272973 Starting the controller
750 01:11:45.278280 USB XHCI 1.10
751 01:11:47.440530 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 01:11:47.441118 bl2_stage_init 0x01
753 01:11:47.441550 bl2_stage_init 0x81
754 01:11:47.446064 hw id: 0x0000 - pwm id 0x01
755 01:11:47.446559 bl2_stage_init 0xc1
756 01:11:47.446984 bl2_stage_init 0x02
757 01:11:47.447390
758 01:11:47.451598 L0:00000000
759 01:11:47.452110 L1:20000703
760 01:11:47.452536 L2:00008067
761 01:11:47.452934 L3:14000000
762 01:11:47.454534 B2:00402000
763 01:11:47.454974 B1:e0f83180
764 01:11:47.455378
765 01:11:47.455950 TE: 58159
766 01:11:47.456426
767 01:11:47.465649 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 01:11:47.466138
769 01:11:47.466557 Board ID = 1
770 01:11:47.467090 Set A53 clk to 24M
771 01:11:47.467542 Set A73 clk to 24M
772 01:11:47.471184 Set clk81 to 24M
773 01:11:47.471656 A53 clk: 1200 MHz
774 01:11:47.472111 A73 clk: 1200 MHz
775 01:11:47.474664 CLK81: 166.6M
776 01:11:47.475098 smccc: 00012ab5
777 01:11:47.480298 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 01:11:47.485828 board id: 1
779 01:11:47.490541 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 01:11:47.501778 fw parse done
781 01:11:47.507117 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 01:11:47.550518 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 01:11:47.561336 PIEI prepare done
784 01:11:47.561805 fastboot data load
785 01:11:47.562225 fastboot data verify
786 01:11:47.566905 verify result: 266
787 01:11:47.572526 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 01:11:47.573098 LPDDR4 probe
789 01:11:47.573530 ddr clk to 1584MHz
790 01:11:47.579814 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 01:11:47.617330
792 01:11:47.617806 dmc_version 0001
793 01:11:47.624200 Check phy result
794 01:11:47.630292 INFO : End of CA training
795 01:11:47.630740 INFO : End of initialization
796 01:11:47.635921 INFO : Training has run successfully!
797 01:11:47.636395 Check phy result
798 01:11:47.641459 INFO : End of initialization
799 01:11:47.641906 INFO : End of read enable training
800 01:11:47.647101 INFO : End of fine write leveling
801 01:11:47.652715 INFO : End of Write leveling coarse delay
802 01:11:47.653174 INFO : Training has run successfully!
803 01:11:47.653582 Check phy result
804 01:11:47.658313 INFO : End of initialization
805 01:11:47.658757 INFO : End of read dq deskew training
806 01:11:47.663900 INFO : End of MPR read delay center optimization
807 01:11:47.669515 INFO : End of write delay center optimization
808 01:11:47.675104 INFO : End of read delay center optimization
809 01:11:47.675548 INFO : End of max read latency training
810 01:11:47.680733 INFO : Training has run successfully!
811 01:11:47.681174 1D training succeed
812 01:11:47.688966 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 01:11:47.736871 Check phy result
814 01:11:47.737339 INFO : End of initialization
815 01:11:47.758562 INFO : End of 2D read delay Voltage center optimization
816 01:11:47.779290 INFO : End of 2D read delay Voltage center optimization
817 01:11:47.830569 INFO : End of 2D write delay Voltage center optimization
818 01:11:47.880868 INFO : End of 2D write delay Voltage center optimization
819 01:11:47.886531 INFO : Training has run successfully!
820 01:11:47.886995
821 01:11:47.887409 channel==0
822 01:11:47.892071 RxClkDly_Margin_A0==88 ps 9
823 01:11:47.892524 TxDqDly_Margin_A0==98 ps 10
824 01:11:47.897597 RxClkDly_Margin_A1==88 ps 9
825 01:11:47.898052 TxDqDly_Margin_A1==88 ps 9
826 01:11:47.898473 TrainedVREFDQ_A0==74
827 01:11:47.903232 TrainedVREFDQ_A1==74
828 01:11:47.903719 VrefDac_Margin_A0==25
829 01:11:47.904171 DeviceVref_Margin_A0==40
830 01:11:47.908855 VrefDac_Margin_A1==25
831 01:11:47.909342 DeviceVref_Margin_A1==40
832 01:11:47.909732
833 01:11:47.910120
834 01:11:47.910506 channel==1
835 01:11:47.914519 RxClkDly_Margin_A0==98 ps 10
836 01:11:47.914954 TxDqDly_Margin_A0==88 ps 9
837 01:11:47.920045 RxClkDly_Margin_A1==88 ps 9
838 01:11:47.920524 TxDqDly_Margin_A1==98 ps 10
839 01:11:47.925617 TrainedVREFDQ_A0==75
840 01:11:47.926124 TrainedVREFDQ_A1==77
841 01:11:47.926522 VrefDac_Margin_A0==22
842 01:11:47.931210 DeviceVref_Margin_A0==39
843 01:11:47.931651 VrefDac_Margin_A1==24
844 01:11:47.936790 DeviceVref_Margin_A1==37
845 01:11:47.937219
846 01:11:47.937615 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 01:11:47.938007
848 01:11:47.970532 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
849 01:11:47.971020 2D training succeed
850 01:11:47.976052 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 01:11:47.981653 auto size-- 65535DDR cs0 size: 2048MB
852 01:11:47.982088 DDR cs1 size: 2048MB
853 01:11:47.987205 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 01:11:47.987633 cs0 DataBus test pass
855 01:11:47.992824 cs1 DataBus test pass
856 01:11:47.993263 cs0 AddrBus test pass
857 01:11:47.993653 cs1 AddrBus test pass
858 01:11:47.994037
859 01:11:47.998567 100bdlr_step_size ps== 420
860 01:11:47.999003 result report
861 01:11:48.004032 boot times 0Enable ddr reg access
862 01:11:48.008383 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 01:11:48.022072 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 01:11:48.596541 0.0;M3 CHK:0;cm4_sp_mode 0
865 01:11:48.597136 MVN_1=0x00000000
866 01:11:48.602000 MVN_2=0x00000000
867 01:11:48.607743 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 01:11:48.608234 OPS=0x10
869 01:11:48.608657 ring efuse init
870 01:11:48.609062 chipver efuse init
871 01:11:48.615943 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 01:11:48.616430 [0.018960 Inits done]
873 01:11:48.623043 secure task start!
874 01:11:48.623481 high task start!
875 01:11:48.623883 low task start!
876 01:11:48.624320 run into bl31
877 01:11:48.630189 NOTICE: BL31: v1.3(release):4fc40b1
878 01:11:48.637141 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 01:11:48.637592 NOTICE: BL31: G12A normal boot!
880 01:11:48.663450 NOTICE: BL31: BL33 decompress pass
881 01:11:48.668392 ERROR: Error initializing runtime service opteed_fast
882 01:11:49.901921
883 01:11:49.902504
884 01:11:49.909328 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 01:11:49.909809
886 01:11:49.910228 Model: Libre Computer AML-A311D-CC Alta
887 01:11:50.118144 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 01:11:50.141557 DRAM: 2 GiB (effective 3.8 GiB)
889 01:11:50.285118 Core: 408 devices, 31 uclasses, devicetree: separate
890 01:11:50.291005 WDT: Not starting watchdog@f0d0
891 01:11:50.323196 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 01:11:50.335835 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 01:11:50.339759 ** Bad device specification mmc 0 **
894 01:11:50.351095 Card did not respond to voltage select! : -110
895 01:11:50.357807 ** Bad device specification mmc 0 **
896 01:11:50.358251 Couldn't find partition mmc 0
897 01:11:50.367093 Card did not respond to voltage select! : -110
898 01:11:50.372523 ** Bad device specification mmc 0 **
899 01:11:50.372994 Couldn't find partition mmc 0
900 01:11:50.376970 Error: could not access storage.
901 01:11:50.719084 Net: eth0: ethernet@ff3f0000
902 01:11:50.719618 starting USB...
903 01:11:50.972017 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 01:11:50.972526 Starting the controller
905 01:11:50.977839 USB XHCI 1.10
906 01:11:52.840517 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 01:11:52.841115 bl2_stage_init 0x01
908 01:11:52.841541 bl2_stage_init 0x81
909 01:11:52.845916 hw id: 0x0000 - pwm id 0x01
910 01:11:52.846390 bl2_stage_init 0xc1
911 01:11:52.846809 bl2_stage_init 0x02
912 01:11:52.847217
913 01:11:52.851502 L0:00000000
914 01:11:52.851974 L1:20000703
915 01:11:52.852428 L2:00008067
916 01:11:52.852838 L3:14000000
917 01:11:52.857148 B2:00402000
918 01:11:52.857588 B1:e0f83180
919 01:11:52.858000
920 01:11:52.858403 TE: 58159
921 01:11:52.858806
922 01:11:52.862791 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 01:11:52.863236
924 01:11:52.863652 Board ID = 1
925 01:11:52.868303 Set A53 clk to 24M
926 01:11:52.868742 Set A73 clk to 24M
927 01:11:52.869148 Set clk81 to 24M
928 01:11:52.873914 A53 clk: 1200 MHz
929 01:11:52.874350 A73 clk: 1200 MHz
930 01:11:52.874750 CLK81: 166.6M
931 01:11:52.875145 smccc: 00012ab5
932 01:11:52.879500 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 01:11:52.885162 board id: 1
934 01:11:52.890051 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 01:11:52.901695 fw parse done
936 01:11:52.906699 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 01:11:52.949347 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 01:11:52.961135 PIEI prepare done
939 01:11:52.961591 fastboot data load
940 01:11:52.961987 fastboot data verify
941 01:11:52.966901 verify result: 266
942 01:11:52.972427 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 01:11:52.972864 LPDDR4 probe
944 01:11:52.973251 ddr clk to 1584MHz
945 01:11:52.979516 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 01:11:53.016809
947 01:11:53.017311 dmc_version 0001
948 01:11:53.023354 Check phy result
949 01:11:53.030242 INFO : End of CA training
950 01:11:53.030709 INFO : End of initialization
951 01:11:53.035867 INFO : Training has run successfully!
952 01:11:53.036340 Check phy result
953 01:11:53.041425 INFO : End of initialization
954 01:11:53.041908 INFO : End of read enable training
955 01:11:53.046987 INFO : End of fine write leveling
956 01:11:53.052575 INFO : End of Write leveling coarse delay
957 01:11:53.053028 INFO : Training has run successfully!
958 01:11:53.053436 Check phy result
959 01:11:53.058245 INFO : End of initialization
960 01:11:53.058689 INFO : End of read dq deskew training
961 01:11:53.063829 INFO : End of MPR read delay center optimization
962 01:11:53.069394 INFO : End of write delay center optimization
963 01:11:53.074965 INFO : End of read delay center optimization
964 01:11:53.075403 INFO : End of max read latency training
965 01:11:53.080615 INFO : Training has run successfully!
966 01:11:53.081069 1D training succeed
967 01:11:53.088888 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 01:11:53.136476 Check phy result
969 01:11:53.137029 INFO : End of initialization
970 01:11:53.158178 INFO : End of 2D read delay Voltage center optimization
971 01:11:53.178413 INFO : End of 2D read delay Voltage center optimization
972 01:11:53.230508 INFO : End of 2D write delay Voltage center optimization
973 01:11:53.280767 INFO : End of 2D write delay Voltage center optimization
974 01:11:53.286395 INFO : Training has run successfully!
975 01:11:53.286984
976 01:11:53.287569 channel==0
977 01:11:53.291908 RxClkDly_Margin_A0==88 ps 9
978 01:11:53.292508 TxDqDly_Margin_A0==98 ps 10
979 01:11:53.297595 RxClkDly_Margin_A1==88 ps 9
980 01:11:53.298295 TxDqDly_Margin_A1==98 ps 10
981 01:11:53.298878 TrainedVREFDQ_A0==74
982 01:11:53.303102 TrainedVREFDQ_A1==75
983 01:11:53.303776 VrefDac_Margin_A0==25
984 01:11:53.304370 DeviceVref_Margin_A0==40
985 01:11:53.308638 VrefDac_Margin_A1==25
986 01:11:53.309231 DeviceVref_Margin_A1==39
987 01:11:53.309764
988 01:11:53.310298
989 01:11:53.314306 channel==1
990 01:11:53.314912 RxClkDly_Margin_A0==98 ps 10
991 01:11:53.315443 TxDqDly_Margin_A0==88 ps 9
992 01:11:53.319870 RxClkDly_Margin_A1==98 ps 10
993 01:11:53.320501 TxDqDly_Margin_A1==88 ps 9
994 01:11:53.325487 TrainedVREFDQ_A0==76
995 01:11:53.326109 TrainedVREFDQ_A1==77
996 01:11:53.326661 VrefDac_Margin_A0==22
997 01:11:53.331090 DeviceVref_Margin_A0==38
998 01:11:53.331712 VrefDac_Margin_A1==22
999 01:11:53.336792 DeviceVref_Margin_A1==37
1000 01:11:53.337409
1001 01:11:53.337942 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 01:11:53.339023
1003 01:11:53.370345 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1004 01:11:53.371142 2D training succeed
1005 01:11:53.375877 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 01:11:53.381459 auto size-- 65535DDR cs0 size: 2048MB
1007 01:11:53.382051 DDR cs1 size: 2048MB
1008 01:11:53.387210 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 01:11:53.387837 cs0 DataBus test pass
1010 01:11:53.392653 cs1 DataBus test pass
1011 01:11:53.393157 cs0 AddrBus test pass
1012 01:11:53.393587 cs1 AddrBus test pass
1013 01:11:53.393996
1014 01:11:53.398261 100bdlr_step_size ps== 420
1015 01:11:53.398877 result report
1016 01:11:53.403899 boot times 0Enable ddr reg access
1017 01:11:53.409364 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 01:11:53.422693 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 01:11:53.996460 0.0;M3 CHK:0;cm4_sp_mode 0
1020 01:11:53.997054 MVN_1=0x00000000
1021 01:11:54.001899 MVN_2=0x00000000
1022 01:11:54.007757 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 01:11:54.008398 OPS=0x10
1024 01:11:54.008851 ring efuse init
1025 01:11:54.009255 chipver efuse init
1026 01:11:54.015906 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 01:11:54.016417 [0.018961 Inits done]
1028 01:11:54.022543 secure task start!
1029 01:11:54.023016 high task start!
1030 01:11:54.023410 low task start!
1031 01:11:54.023807 run into bl31
1032 01:11:54.030108 NOTICE: BL31: v1.3(release):4fc40b1
1033 01:11:54.036966 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 01:11:54.037410 NOTICE: BL31: G12A normal boot!
1035 01:11:54.063317 NOTICE: BL31: BL33 decompress pass
1036 01:11:54.068199 ERROR: Error initializing runtime service opteed_fast
1037 01:11:55.301832
1038 01:11:55.302445
1039 01:11:55.310265 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 01:11:55.310732
1041 01:11:55.311148 Model: Libre Computer AML-A311D-CC Alta
1042 01:11:55.518667 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 01:11:55.542072 DRAM: 2 GiB (effective 3.8 GiB)
1044 01:11:55.685106 Core: 408 devices, 31 uclasses, devicetree: separate
1045 01:11:55.690866 WDT: Not starting watchdog@f0d0
1046 01:11:55.723276 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 01:11:55.735566 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 01:11:55.740612 ** Bad device specification mmc 0 **
1049 01:11:55.750910 Card did not respond to voltage select! : -110
1050 01:11:55.758605 ** Bad device specification mmc 0 **
1051 01:11:55.759174 Couldn't find partition mmc 0
1052 01:11:55.766861 Card did not respond to voltage select! : -110
1053 01:11:55.772530 ** Bad device specification mmc 0 **
1054 01:11:55.773108 Couldn't find partition mmc 0
1055 01:11:55.777479 Error: could not access storage.
1056 01:11:56.120070 Net: eth0: ethernet@ff3f0000
1057 01:11:56.120803 starting USB...
1058 01:11:56.371858 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 01:11:56.372651 Starting the controller
1060 01:11:56.378688 USB XHCI 1.10
1061 01:11:57.932887 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 01:11:57.941228 scanning usb for storage devices... 0 Storage Device(s) found
1064 01:11:57.993155 Hit any key to stop autoboot: 1
1065 01:11:57.994147 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1066 01:11:57.994864 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1067 01:11:57.995449 Setting prompt string to ['=>']
1068 01:11:57.996101 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1069 01:11:58.008658 0
1070 01:11:58.009761 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 01:11:58.010386 Sending with 10 millisecond of delay
1073 01:11:59.145559 => setenv autoload no
1074 01:11:59.156337 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1075 01:11:59.161210 setenv autoload no
1076 01:11:59.161943 Sending with 10 millisecond of delay
1078 01:12:00.959075 => setenv initrd_high 0xffffffff
1079 01:12:00.969845 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1080 01:12:00.970704 setenv initrd_high 0xffffffff
1081 01:12:00.971414 Sending with 10 millisecond of delay
1083 01:12:02.589837 => setenv fdt_high 0xffffffff
1084 01:12:02.600870 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1085 01:12:02.601938 setenv fdt_high 0xffffffff
1086 01:12:02.602857 Sending with 10 millisecond of delay
1088 01:12:02.895205 => dhcp
1089 01:12:02.905980 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1090 01:12:02.906588 dhcp
1091 01:12:02.906828 Speed: 1000, full duplex
1092 01:12:02.907046 BOOTP broadcast 1
1093 01:12:02.920812 DHCP client bound to address 192.168.6.27 (16 ms)
1094 01:12:02.921313 Sending with 10 millisecond of delay
1096 01:12:04.598791 => setenv serverip 192.168.6.2
1097 01:12:04.609775 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1098 01:12:04.610923 setenv serverip 192.168.6.2
1099 01:12:04.611766 Sending with 10 millisecond of delay
1101 01:12:08.335188 => tftpboot 0x01080000 950786/tftp-deploy-4dxw_qhd/kernel/uImage
1102 01:12:08.345977 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1103 01:12:08.346789 tftpboot 0x01080000 950786/tftp-deploy-4dxw_qhd/kernel/uImage
1104 01:12:08.347235 Speed: 1000, full duplex
1105 01:12:08.347648 Using ethernet@ff3f0000 device
1106 01:12:08.348717 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1107 01:12:08.354208 Filename '950786/tftp-deploy-4dxw_qhd/kernel/uImage'.
1108 01:12:08.358242 Load address: 0x1080000
1109 01:12:11.195226 Loading: *################################################## 43.6 MiB
1110 01:12:11.195881 15.4 MiB/s
1111 01:12:11.196372 done
1112 01:12:11.199737 Bytes transferred = 45713984 (2b98a40 hex)
1113 01:12:11.200664 Sending with 10 millisecond of delay
1115 01:12:15.888346 => tftpboot 0x08000000 950786/tftp-deploy-4dxw_qhd/ramdisk/ramdisk.cpio.gz.uboot
1116 01:12:15.899153 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1117 01:12:15.900073 tftpboot 0x08000000 950786/tftp-deploy-4dxw_qhd/ramdisk/ramdisk.cpio.gz.uboot
1118 01:12:15.900563 Speed: 1000, full duplex
1119 01:12:15.901008 Using ethernet@ff3f0000 device
1120 01:12:15.902089 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1121 01:12:15.910604 Filename '950786/tftp-deploy-4dxw_qhd/ramdisk/ramdisk.cpio.gz.uboot'.
1122 01:12:15.911104 Load address: 0x8000000
1123 01:12:22.712215 Loading: *####################T ############################# UDP wrong checksum 00000005 00007d8d
1124 01:12:24.268818 UDP wrong checksum 000000ff 00008f38
1125 01:12:24.319707 UDP wrong checksum 000000ff 0000292b
1126 01:12:27.714029 T UDP wrong checksum 00000005 00007d8d
1127 01:12:37.715918 T T UDP wrong checksum 00000005 00007d8d
1128 01:12:57.720046 T T T T UDP wrong checksum 00000005 00007d8d
1129 01:13:11.560168 T T UDP wrong checksum 000000ff 00005b0d
1130 01:13:11.610249 UDP wrong checksum 000000ff 0000f5ff
1131 01:13:12.724226
1132 01:13:12.725004 Retry count exceeded; starting again
1134 01:13:12.726763 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1137 01:13:12.729184 end: 2.4 uboot-commands (duration 00:01:52) [common]
1139 01:13:12.730945 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1141 01:13:12.732305 end: 2 uboot-action (duration 00:01:52) [common]
1143 01:13:12.734307 Cleaning after the job
1144 01:13:12.735025 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950786/tftp-deploy-4dxw_qhd/ramdisk
1145 01:13:12.736805 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950786/tftp-deploy-4dxw_qhd/kernel
1146 01:13:12.784030 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950786/tftp-deploy-4dxw_qhd/dtb
1147 01:13:12.785112 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950786/tftp-deploy-4dxw_qhd/modules
1148 01:13:12.807520 start: 4.1 power-off (timeout 00:00:30) [common]
1149 01:13:12.808329 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1150 01:13:12.842021 >> OK - accepted request
1151 01:13:12.844142 Returned 0 in 0 seconds
1152 01:13:12.945055 end: 4.1 power-off (duration 00:00:00) [common]
1154 01:13:12.946254 start: 4.2 read-feedback (timeout 00:10:00) [common]
1155 01:13:12.947042 Listened to connection for namespace 'common' for up to 1s
1156 01:13:13.947535 Finalising connection for namespace 'common'
1157 01:13:13.948546 Disconnecting from shell: Finalise
1158 01:13:13.949197 =>
1159 01:13:14.050408 end: 4.2 read-feedback (duration 00:00:01) [common]
1160 01:13:14.051228 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950786
1161 01:13:14.396831 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950786
1162 01:13:14.397564 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.