Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 8
- Errors: 0
- Boot result: PASS
- Kernel Errors: 6
1 04:22:49.971705 lava-dispatcher, installed at version: 2024.01
2 04:22:49.972615 start: 0 validate
3 04:22:49.973124 Start time: 2024-11-07 04:22:49.973091+00:00 (UTC)
4 04:22:49.973715 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:22:49.974287 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 04:22:50.020980 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:22:50.021566 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 04:22:50.054081 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:22:50.054763 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:22:50.090443 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:22:50.090983 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:22:50.124348 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 04:22:50.124886 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 04:22:50.172797 validate duration: 0.20
16 04:22:50.173864 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:22:50.174314 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:22:50.174730 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:22:50.175450 Not decompressing ramdisk as can be used compressed.
20 04:22:50.176057 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 04:22:50.176444 saving as /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/ramdisk/initrd.cpio.gz
22 04:22:50.176780 total size: 5628169 (5 MB)
23 04:22:50.218784 progress 0 % (0 MB)
24 04:22:50.223242 progress 5 % (0 MB)
25 04:22:50.231227 progress 10 % (0 MB)
26 04:22:50.237593 progress 15 % (0 MB)
27 04:22:50.242160 progress 20 % (1 MB)
28 04:22:50.246023 progress 25 % (1 MB)
29 04:22:50.250309 progress 30 % (1 MB)
30 04:22:50.254734 progress 35 % (1 MB)
31 04:22:50.258679 progress 40 % (2 MB)
32 04:22:50.263194 progress 45 % (2 MB)
33 04:22:50.267180 progress 50 % (2 MB)
34 04:22:50.271430 progress 55 % (2 MB)
35 04:22:50.275683 progress 60 % (3 MB)
36 04:22:50.279538 progress 65 % (3 MB)
37 04:22:50.283809 progress 70 % (3 MB)
38 04:22:50.287667 progress 75 % (4 MB)
39 04:22:50.291897 progress 80 % (4 MB)
40 04:22:50.295873 progress 85 % (4 MB)
41 04:22:50.300173 progress 90 % (4 MB)
42 04:22:50.304314 progress 95 % (5 MB)
43 04:22:50.307713 progress 100 % (5 MB)
44 04:22:50.308494 5 MB downloaded in 0.13 s (40.76 MB/s)
45 04:22:50.309083 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:22:50.310056 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:22:50.310382 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:22:50.310678 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:22:50.311192 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/kernel/Image
51 04:22:50.311468 saving as /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/kernel/Image
52 04:22:50.311698 total size: 45713920 (43 MB)
53 04:22:50.311927 No compression specified
54 04:22:50.352637 progress 0 % (0 MB)
55 04:22:50.381772 progress 5 % (2 MB)
56 04:22:50.410570 progress 10 % (4 MB)
57 04:22:50.439645 progress 15 % (6 MB)
58 04:22:50.470872 progress 20 % (8 MB)
59 04:22:50.499889 progress 25 % (10 MB)
60 04:22:50.529150 progress 30 % (13 MB)
61 04:22:50.558802 progress 35 % (15 MB)
62 04:22:50.589416 progress 40 % (17 MB)
63 04:22:50.617080 progress 45 % (19 MB)
64 04:22:50.645607 progress 50 % (21 MB)
65 04:22:50.673972 progress 55 % (24 MB)
66 04:22:50.702142 progress 60 % (26 MB)
67 04:22:50.730208 progress 65 % (28 MB)
68 04:22:50.758272 progress 70 % (30 MB)
69 04:22:50.786463 progress 75 % (32 MB)
70 04:22:50.814507 progress 80 % (34 MB)
71 04:22:50.842328 progress 85 % (37 MB)
72 04:22:50.870425 progress 90 % (39 MB)
73 04:22:50.898631 progress 95 % (41 MB)
74 04:22:50.926593 progress 100 % (43 MB)
75 04:22:50.927144 43 MB downloaded in 0.62 s (70.84 MB/s)
76 04:22:50.927626 end: 1.2.1 http-download (duration 00:00:01) [common]
78 04:22:50.928515 end: 1.2 download-retry (duration 00:00:01) [common]
79 04:22:50.928799 start: 1.3 download-retry (timeout 00:09:59) [common]
80 04:22:50.929073 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 04:22:50.929554 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 04:22:50.929832 saving as /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/dtb/meson-g12b-a311d-libretech-cc.dtb
83 04:22:50.930047 total size: 54703 (0 MB)
84 04:22:50.930262 No compression specified
85 04:22:50.970711 progress 59 % (0 MB)
86 04:22:50.971571 progress 100 % (0 MB)
87 04:22:50.972159 0 MB downloaded in 0.04 s (1.24 MB/s)
88 04:22:50.972669 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:22:50.973528 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:22:50.973805 start: 1.4 download-retry (timeout 00:09:59) [common]
92 04:22:50.974078 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 04:22:50.974568 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 04:22:50.974822 saving as /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/nfsrootfs/full.rootfs.tar
95 04:22:50.975033 total size: 120894716 (115 MB)
96 04:22:50.975250 Using unxz to decompress xz
97 04:22:51.010481 progress 0 % (0 MB)
98 04:22:51.800496 progress 5 % (5 MB)
99 04:22:52.664713 progress 10 % (11 MB)
100 04:22:53.455944 progress 15 % (17 MB)
101 04:22:54.196419 progress 20 % (23 MB)
102 04:22:54.785519 progress 25 % (28 MB)
103 04:22:55.611027 progress 30 % (34 MB)
104 04:22:56.405173 progress 35 % (40 MB)
105 04:22:56.754421 progress 40 % (46 MB)
106 04:22:57.127974 progress 45 % (51 MB)
107 04:22:57.853121 progress 50 % (57 MB)
108 04:22:58.769200 progress 55 % (63 MB)
109 04:22:59.561752 progress 60 % (69 MB)
110 04:23:00.317960 progress 65 % (74 MB)
111 04:23:01.103428 progress 70 % (80 MB)
112 04:23:01.929623 progress 75 % (86 MB)
113 04:23:02.754713 progress 80 % (92 MB)
114 04:23:03.562943 progress 85 % (98 MB)
115 04:23:04.426218 progress 90 % (103 MB)
116 04:23:05.200234 progress 95 % (109 MB)
117 04:23:06.033308 progress 100 % (115 MB)
118 04:23:06.045854 115 MB downloaded in 15.07 s (7.65 MB/s)
119 04:23:06.046511 end: 1.4.1 http-download (duration 00:00:15) [common]
121 04:23:06.047436 end: 1.4 download-retry (duration 00:00:15) [common]
122 04:23:06.047758 start: 1.5 download-retry (timeout 00:09:44) [common]
123 04:23:06.048102 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 04:23:06.048570 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/modules.tar.xz
125 04:23:06.048825 saving as /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/modules/modules.tar
126 04:23:06.049054 total size: 11618152 (11 MB)
127 04:23:06.049292 Using unxz to decompress xz
128 04:23:06.094310 progress 0 % (0 MB)
129 04:23:06.160867 progress 5 % (0 MB)
130 04:23:06.234974 progress 10 % (1 MB)
131 04:23:06.333072 progress 15 % (1 MB)
132 04:23:06.426717 progress 20 % (2 MB)
133 04:23:06.506529 progress 25 % (2 MB)
134 04:23:06.582423 progress 30 % (3 MB)
135 04:23:06.661181 progress 35 % (3 MB)
136 04:23:06.733536 progress 40 % (4 MB)
137 04:23:06.808866 progress 45 % (5 MB)
138 04:23:06.894592 progress 50 % (5 MB)
139 04:23:06.977811 progress 55 % (6 MB)
140 04:23:07.058850 progress 60 % (6 MB)
141 04:23:07.140145 progress 65 % (7 MB)
142 04:23:07.221064 progress 70 % (7 MB)
143 04:23:07.300703 progress 75 % (8 MB)
144 04:23:07.385235 progress 80 % (8 MB)
145 04:23:07.471210 progress 85 % (9 MB)
146 04:23:07.556938 progress 90 % (10 MB)
147 04:23:07.630833 progress 95 % (10 MB)
148 04:23:07.708627 progress 100 % (11 MB)
149 04:23:07.721124 11 MB downloaded in 1.67 s (6.63 MB/s)
150 04:23:07.721703 end: 1.5.1 http-download (duration 00:00:02) [common]
152 04:23:07.722585 end: 1.5 download-retry (duration 00:00:02) [common]
153 04:23:07.722865 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 04:23:07.723137 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 04:23:24.934275 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/950796/extract-nfsrootfs-7h5f4j8z
156 04:23:24.934914 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 04:23:24.935205 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 04:23:24.935837 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j
159 04:23:24.936340 makedir: /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin
160 04:23:24.936670 makedir: /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/tests
161 04:23:24.937003 makedir: /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/results
162 04:23:24.937404 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-add-keys
163 04:23:24.937993 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-add-sources
164 04:23:24.938515 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-background-process-start
165 04:23:24.939047 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-background-process-stop
166 04:23:24.939605 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-common-functions
167 04:23:24.940220 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-echo-ipv4
168 04:23:24.940758 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-install-packages
169 04:23:24.941263 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-installed-packages
170 04:23:24.941795 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-os-build
171 04:23:24.942348 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-probe-channel
172 04:23:24.942865 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-probe-ip
173 04:23:24.943384 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-target-ip
174 04:23:24.943874 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-target-mac
175 04:23:24.944446 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-target-storage
176 04:23:24.944955 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-test-case
177 04:23:24.945449 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-test-event
178 04:23:24.946007 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-test-feedback
179 04:23:24.946580 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-test-raise
180 04:23:24.947084 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-test-reference
181 04:23:24.947581 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-test-runner
182 04:23:24.948133 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-test-set
183 04:23:24.948660 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-test-shell
184 04:23:24.949163 Updating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-add-keys (debian)
185 04:23:24.949736 Updating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-add-sources (debian)
186 04:23:24.950273 Updating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-install-packages (debian)
187 04:23:24.950806 Updating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-installed-packages (debian)
188 04:23:24.951330 Updating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/bin/lava-os-build (debian)
189 04:23:24.951874 Creating /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/environment
190 04:23:24.952380 LAVA metadata
191 04:23:24.952658 - LAVA_JOB_ID=950796
192 04:23:24.952877 - LAVA_DISPATCHER_IP=192.168.6.2
193 04:23:24.953281 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 04:23:24.954348 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 04:23:24.954726 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 04:23:24.954937 skipped lava-vland-overlay
197 04:23:24.955179 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 04:23:24.955437 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 04:23:24.955665 skipped lava-multinode-overlay
200 04:23:24.955912 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 04:23:24.956219 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 04:23:24.956488 Loading test definitions
203 04:23:24.956777 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 04:23:24.957002 Using /lava-950796 at stage 0
205 04:23:24.958176 uuid=950796_1.6.2.4.1 testdef=None
206 04:23:24.958526 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 04:23:24.958796 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 04:23:24.960486 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 04:23:24.961304 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 04:23:24.963469 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 04:23:24.964396 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 04:23:24.966386 runner path: /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/0/tests/0_timesync-off test_uuid 950796_1.6.2.4.1
215 04:23:24.967034 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 04:23:24.967880 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 04:23:24.968145 Using /lava-950796 at stage 0
219 04:23:24.968532 Fetching tests from https://github.com/kernelci/test-definitions.git
220 04:23:24.968840 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/0/tests/1_kselftest-alsa'
221 04:23:28.470104 Running '/usr/bin/git checkout kernelci.org
222 04:23:28.843326 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 04:23:28.844787 uuid=950796_1.6.2.4.5 testdef=None
224 04:23:28.845134 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 04:23:28.845880 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 04:23:28.848700 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 04:23:28.849509 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 04:23:28.853194 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 04:23:28.854057 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 04:23:28.857620 runner path: /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/0/tests/1_kselftest-alsa test_uuid 950796_1.6.2.4.5
234 04:23:28.857905 BOARD='meson-g12b-a311d-libretech-cc'
235 04:23:28.858113 BRANCH='mainline'
236 04:23:28.858310 SKIPFILE='/dev/null'
237 04:23:28.858507 SKIP_INSTALL='True'
238 04:23:28.858700 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 04:23:28.858900 TST_CASENAME=''
240 04:23:28.859095 TST_CMDFILES='alsa'
241 04:23:28.859621 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 04:23:28.860428 Creating lava-test-runner.conf files
244 04:23:28.860636 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950796/lava-overlay-ezrmxx7j/lava-950796/0 for stage 0
245 04:23:28.860994 - 0_timesync-off
246 04:23:28.861240 - 1_kselftest-alsa
247 04:23:28.861572 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 04:23:28.861851 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 04:23:52.413613 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 04:23:52.414110 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 04:23:52.414434 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 04:23:52.414758 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 04:23:52.415084 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 04:23:53.048100 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 04:23:53.048588 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 04:23:53.048840 extracting modules file /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950796/extract-nfsrootfs-7h5f4j8z
257 04:23:54.426751 extracting modules file /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950796/extract-overlay-ramdisk-h48ulsvp/ramdisk
258 04:23:55.835127 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 04:23:55.835637 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 04:23:55.835919 [common] Applying overlay to NFS
261 04:23:55.836181 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950796/compress-overlay-4voo8mqj/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950796/extract-nfsrootfs-7h5f4j8z
262 04:23:58.650396 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 04:23:58.650867 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 04:23:58.651144 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 04:23:58.651377 Converting downloaded kernel to a uImage
266 04:23:58.651692 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/kernel/Image /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/kernel/uImage
267 04:23:59.112254 output: Image Name:
268 04:23:59.112689 output: Created: Thu Nov 7 04:23:58 2024
269 04:23:59.112929 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 04:23:59.113146 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 04:23:59.113364 output: Load Address: 01080000
272 04:23:59.113579 output: Entry Point: 01080000
273 04:23:59.113786 output:
274 04:23:59.114140 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 04:23:59.114424 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 04:23:59.114706 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 04:23:59.115022 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 04:23:59.115331 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 04:23:59.115634 Building ramdisk /var/lib/lava/dispatcher/tmp/950796/extract-overlay-ramdisk-h48ulsvp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950796/extract-overlay-ramdisk-h48ulsvp/ramdisk
280 04:24:01.307091 >> 166825 blocks
281 04:24:09.044867 Adding RAMdisk u-boot header.
282 04:24:09.045312 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950796/extract-overlay-ramdisk-h48ulsvp/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950796/extract-overlay-ramdisk-h48ulsvp/ramdisk.cpio.gz.uboot
283 04:24:09.297380 output: Image Name:
284 04:24:09.297813 output: Created: Thu Nov 7 04:24:09 2024
285 04:24:09.298025 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 04:24:09.298231 output: Data Size: 23431956 Bytes = 22882.77 KiB = 22.35 MiB
287 04:24:09.298435 output: Load Address: 00000000
288 04:24:09.298635 output: Entry Point: 00000000
289 04:24:09.298835 output:
290 04:24:09.299430 rename /var/lib/lava/dispatcher/tmp/950796/extract-overlay-ramdisk-h48ulsvp/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/ramdisk/ramdisk.cpio.gz.uboot
291 04:24:09.299842 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 04:24:09.300349 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 04:24:09.300938 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 04:24:09.301436 No LXC device requested
295 04:24:09.301987 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 04:24:09.302549 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 04:24:09.303093 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 04:24:09.303547 Checking files for TFTP limit of 4294967296 bytes.
299 04:24:09.306489 end: 1 tftp-deploy (duration 00:01:19) [common]
300 04:24:09.307123 start: 2 uboot-action (timeout 00:05:00) [common]
301 04:24:09.307697 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 04:24:09.308288 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 04:24:09.308847 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 04:24:09.309428 Using kernel file from prepare-kernel: 950796/tftp-deploy-xbqxmg97/kernel/uImage
305 04:24:09.310120 substitutions:
306 04:24:09.310573 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 04:24:09.311020 - {DTB_ADDR}: 0x01070000
308 04:24:09.311464 - {DTB}: 950796/tftp-deploy-xbqxmg97/dtb/meson-g12b-a311d-libretech-cc.dtb
309 04:24:09.311913 - {INITRD}: 950796/tftp-deploy-xbqxmg97/ramdisk/ramdisk.cpio.gz.uboot
310 04:24:09.312391 - {KERNEL_ADDR}: 0x01080000
311 04:24:09.312829 - {KERNEL}: 950796/tftp-deploy-xbqxmg97/kernel/uImage
312 04:24:09.313265 - {LAVA_MAC}: None
313 04:24:09.313737 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/950796/extract-nfsrootfs-7h5f4j8z
314 04:24:09.314176 - {NFS_SERVER_IP}: 192.168.6.2
315 04:24:09.314607 - {PRESEED_CONFIG}: None
316 04:24:09.315037 - {PRESEED_LOCAL}: None
317 04:24:09.315469 - {RAMDISK_ADDR}: 0x08000000
318 04:24:09.315898 - {RAMDISK}: 950796/tftp-deploy-xbqxmg97/ramdisk/ramdisk.cpio.gz.uboot
319 04:24:09.316364 - {ROOT_PART}: None
320 04:24:09.316796 - {ROOT}: None
321 04:24:09.317224 - {SERVER_IP}: 192.168.6.2
322 04:24:09.317647 - {TEE_ADDR}: 0x83000000
323 04:24:09.318070 - {TEE}: None
324 04:24:09.318494 Parsed boot commands:
325 04:24:09.318909 - setenv autoload no
326 04:24:09.319333 - setenv initrd_high 0xffffffff
327 04:24:09.319752 - setenv fdt_high 0xffffffff
328 04:24:09.320216 - dhcp
329 04:24:09.320643 - setenv serverip 192.168.6.2
330 04:24:09.321076 - tftpboot 0x01080000 950796/tftp-deploy-xbqxmg97/kernel/uImage
331 04:24:09.321508 - tftpboot 0x08000000 950796/tftp-deploy-xbqxmg97/ramdisk/ramdisk.cpio.gz.uboot
332 04:24:09.321973 - tftpboot 0x01070000 950796/tftp-deploy-xbqxmg97/dtb/meson-g12b-a311d-libretech-cc.dtb
333 04:24:09.322437 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950796/extract-nfsrootfs-7h5f4j8z,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 04:24:09.322883 - bootm 0x01080000 0x08000000 0x01070000
335 04:24:09.323445 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 04:24:09.325129 start: 2.3 connect-device (timeout 00:05:00) [common]
338 04:24:09.325599 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 04:24:09.341393 Setting prompt string to ['lava-test: # ']
340 04:24:09.343065 end: 2.3 connect-device (duration 00:00:00) [common]
341 04:24:09.343742 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 04:24:09.344405 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 04:24:09.344990 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 04:24:09.346207 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 04:24:09.387482 >> OK - accepted request
346 04:24:09.389759 Returned 0 in 0 seconds
347 04:24:09.490948 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 04:24:09.492819 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 04:24:09.493432 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 04:24:09.493989 Setting prompt string to ['Hit any key to stop autoboot']
352 04:24:09.494483 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 04:24:09.496210 Trying 192.168.56.21...
354 04:24:09.496740 Connected to conserv1.
355 04:24:09.497172 Escape character is '^]'.
356 04:24:09.497426
357 04:24:09.497674 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 04:24:09.497912
359 04:24:20.810720 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 04:24:20.811379 bl2_stage_init 0x01
361 04:24:20.811845 bl2_stage_init 0x81
362 04:24:20.816307 hw id: 0x0000 - pwm id 0x01
363 04:24:20.816876 bl2_stage_init 0xc1
364 04:24:20.817338 bl2_stage_init 0x02
365 04:24:20.817788
366 04:24:20.821863 L0:00000000
367 04:24:20.822367 L1:20000703
368 04:24:20.822826 L2:00008067
369 04:24:20.823275 L3:14000000
370 04:24:20.827438 B2:00402000
371 04:24:20.827910 B1:e0f83180
372 04:24:20.828386
373 04:24:20.828821 TE: 58124
374 04:24:20.829254
375 04:24:20.833084 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 04:24:20.833561
377 04:24:20.833995 Board ID = 1
378 04:24:20.838665 Set A53 clk to 24M
379 04:24:20.839125 Set A73 clk to 24M
380 04:24:20.839558 Set clk81 to 24M
381 04:24:20.844289 A53 clk: 1200 MHz
382 04:24:20.844759 A73 clk: 1200 MHz
383 04:24:20.845190 CLK81: 166.6M
384 04:24:20.845615 smccc: 00012a92
385 04:24:20.849886 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 04:24:20.855459 board id: 1
387 04:24:20.861312 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 04:24:20.872018 fw parse done
389 04:24:20.877917 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 04:24:20.920571 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 04:24:20.931433 PIEI prepare done
392 04:24:20.931910 fastboot data load
393 04:24:20.932395 fastboot data verify
394 04:24:20.937152 verify result: 266
395 04:24:20.942817 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 04:24:20.943332 LPDDR4 probe
397 04:24:20.943796 ddr clk to 1584MHz
398 04:24:20.949682 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 04:24:20.988064
400 04:24:20.988571 dmc_version 0001
401 04:24:20.994627 Check phy result
402 04:24:21.000495 INFO : End of CA training
403 04:24:21.000972 INFO : End of initialization
404 04:24:21.006221 INFO : Training has run successfully!
405 04:24:21.006695 Check phy result
406 04:24:21.011695 INFO : End of initialization
407 04:24:21.012197 INFO : End of read enable training
408 04:24:21.015057 INFO : End of fine write leveling
409 04:24:21.020615 INFO : End of Write leveling coarse delay
410 04:24:21.026222 INFO : Training has run successfully!
411 04:24:21.026717 Check phy result
412 04:24:21.027178 INFO : End of initialization
413 04:24:21.031849 INFO : End of read dq deskew training
414 04:24:21.037506 INFO : End of MPR read delay center optimization
415 04:24:21.037998 INFO : End of write delay center optimization
416 04:24:21.043035 INFO : End of read delay center optimization
417 04:24:21.048587 INFO : End of max read latency training
418 04:24:21.049056 INFO : Training has run successfully!
419 04:24:21.054210 1D training succeed
420 04:24:21.060062 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 04:24:21.107656 Check phy result
422 04:24:21.108193 INFO : End of initialization
423 04:24:21.129276 INFO : End of 2D read delay Voltage center optimization
424 04:24:21.150281 INFO : End of 2D read delay Voltage center optimization
425 04:24:21.202145 INFO : End of 2D write delay Voltage center optimization
426 04:24:21.251387 INFO : End of 2D write delay Voltage center optimization
427 04:24:21.257085 INFO : Training has run successfully!
428 04:24:21.257569
429 04:24:21.258026 channel==0
430 04:24:21.262583 RxClkDly_Margin_A0==88 ps 9
431 04:24:21.263058 TxDqDly_Margin_A0==98 ps 10
432 04:24:21.268239 RxClkDly_Margin_A1==88 ps 9
433 04:24:21.268708 TxDqDly_Margin_A1==98 ps 10
434 04:24:21.269161 TrainedVREFDQ_A0==74
435 04:24:21.273771 TrainedVREFDQ_A1==74
436 04:24:21.274249 VrefDac_Margin_A0==25
437 04:24:21.274695 DeviceVref_Margin_A0==40
438 04:24:21.279365 VrefDac_Margin_A1==25
439 04:24:21.279834 DeviceVref_Margin_A1==40
440 04:24:21.280327
441 04:24:21.280773
442 04:24:21.285088 channel==1
443 04:24:21.285564 RxClkDly_Margin_A0==98 ps 10
444 04:24:21.286010 TxDqDly_Margin_A0==88 ps 9
445 04:24:21.290614 RxClkDly_Margin_A1==98 ps 10
446 04:24:21.291085 TxDqDly_Margin_A1==88 ps 9
447 04:24:21.296206 TrainedVREFDQ_A0==77
448 04:24:21.296680 TrainedVREFDQ_A1==77
449 04:24:21.297125 VrefDac_Margin_A0==22
450 04:24:21.301755 DeviceVref_Margin_A0==37
451 04:24:21.302229 VrefDac_Margin_A1==22
452 04:24:21.307379 DeviceVref_Margin_A1==37
453 04:24:21.307863
454 04:24:21.308356 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 04:24:21.308804
456 04:24:21.340971 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 04:24:21.341563 2D training succeed
458 04:24:21.346567 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 04:24:21.352217 auto size-- 65535DDR cs0 size: 2048MB
460 04:24:21.352696 DDR cs1 size: 2048MB
461 04:24:21.357786 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 04:24:21.358255 cs0 DataBus test pass
463 04:24:21.363366 cs1 DataBus test pass
464 04:24:21.363830 cs0 AddrBus test pass
465 04:24:21.364316 cs1 AddrBus test pass
466 04:24:21.364759
467 04:24:21.368968 100bdlr_step_size ps== 420
468 04:24:21.369449 result report
469 04:24:21.374569 boot times 0Enable ddr reg access
470 04:24:21.379935 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 04:24:21.393367 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 04:24:21.965387 0.0;M3 CHK:0;cm4_sp_mode 0
473 04:24:21.966093 MVN_1=0x00000000
474 04:24:21.970844 MVN_2=0x00000000
475 04:24:21.976609 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 04:24:21.977131 OPS=0x10
477 04:24:21.977589 ring efuse init
478 04:24:21.978036 chipver efuse init
479 04:24:21.982194 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 04:24:21.987797 [0.018961 Inits done]
481 04:24:21.988328 secure task start!
482 04:24:21.988786 high task start!
483 04:24:21.991473 low task start!
484 04:24:21.991945 run into bl31
485 04:24:21.999130 NOTICE: BL31: v1.3(release):4fc40b1
486 04:24:22.006862 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 04:24:22.007340 NOTICE: BL31: G12A normal boot!
488 04:24:22.032810 NOTICE: BL31: BL33 decompress pass
489 04:24:22.038399 ERROR: Error initializing runtime service opteed_fast
490 04:24:23.271443
491 04:24:23.272174
492 04:24:23.278812 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 04:24:23.279332
494 04:24:23.279796 Model: Libre Computer AML-A311D-CC Alta
495 04:24:23.488271 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 04:24:23.510577 DRAM: 2 GiB (effective 3.8 GiB)
497 04:24:23.654649 Core: 408 devices, 31 uclasses, devicetree: separate
498 04:24:23.660437 WDT: Not starting watchdog@f0d0
499 04:24:23.692704 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 04:24:23.705155 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 04:24:23.710126 ** Bad device specification mmc 0 **
502 04:24:23.720455 Card did not respond to voltage select! : -110
503 04:24:23.728103 ** Bad device specification mmc 0 **
504 04:24:23.728596 Couldn't find partition mmc 0
505 04:24:23.736440 Card did not respond to voltage select! : -110
506 04:24:23.741981 ** Bad device specification mmc 0 **
507 04:24:23.742487 Couldn't find partition mmc 0
508 04:24:23.746041 Error: could not access storage.
509 04:24:25.011183 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 04:24:25.011827 bl2_stage_init 0x01
511 04:24:25.012367 bl2_stage_init 0x81
512 04:24:25.016785 hw id: 0x0000 - pwm id 0x01
513 04:24:25.017272 bl2_stage_init 0xc1
514 04:24:25.017729 bl2_stage_init 0x02
515 04:24:25.018178
516 04:24:25.022364 L0:00000000
517 04:24:25.022848 L1:20000703
518 04:24:25.023297 L2:00008067
519 04:24:25.023744 L3:14000000
520 04:24:25.025206 B2:00402000
521 04:24:25.025687 B1:e0f83180
522 04:24:25.026137
523 04:24:25.026583 TE: 58167
524 04:24:25.027026
525 04:24:25.036431 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 04:24:25.036930
527 04:24:25.037382 Board ID = 1
528 04:24:25.037821 Set A53 clk to 24M
529 04:24:25.038258 Set A73 clk to 24M
530 04:24:25.041946 Set clk81 to 24M
531 04:24:25.042421 A53 clk: 1200 MHz
532 04:24:25.042866 A73 clk: 1200 MHz
533 04:24:25.045358 CLK81: 166.6M
534 04:24:25.045828 smccc: 00012abe
535 04:24:25.050953 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 04:24:25.056798 board id: 1
537 04:24:25.061086 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 04:24:25.072485 fw parse done
539 04:24:25.078473 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 04:24:25.120077 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 04:24:25.131920 PIEI prepare done
542 04:24:25.132430 fastboot data load
543 04:24:25.132890 fastboot data verify
544 04:24:25.137602 verify result: 266
545 04:24:25.143134 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 04:24:25.143609 LPDDR4 probe
547 04:24:25.144132 ddr clk to 1584MHz
548 04:24:25.151121 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 04:24:25.188347
550 04:24:25.188836 dmc_version 0001
551 04:24:25.195052 Check phy result
552 04:24:25.200898 INFO : End of CA training
553 04:24:25.201367 INFO : End of initialization
554 04:24:25.206590 INFO : Training has run successfully!
555 04:24:25.207067 Check phy result
556 04:24:25.212075 INFO : End of initialization
557 04:24:25.212545 INFO : End of read enable training
558 04:24:25.217694 INFO : End of fine write leveling
559 04:24:25.223325 INFO : End of Write leveling coarse delay
560 04:24:25.223800 INFO : Training has run successfully!
561 04:24:25.224291 Check phy result
562 04:24:25.228976 INFO : End of initialization
563 04:24:25.229457 INFO : End of read dq deskew training
564 04:24:25.234596 INFO : End of MPR read delay center optimization
565 04:24:25.240149 INFO : End of write delay center optimization
566 04:24:25.245697 INFO : End of read delay center optimization
567 04:24:25.246167 INFO : End of max read latency training
568 04:24:25.251276 INFO : Training has run successfully!
569 04:24:25.251746 1D training succeed
570 04:24:25.260547 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 04:24:25.308107 Check phy result
572 04:24:25.308586 INFO : End of initialization
573 04:24:25.329872 INFO : End of 2D read delay Voltage center optimization
574 04:24:25.349165 INFO : End of 2D read delay Voltage center optimization
575 04:24:25.402143 INFO : End of 2D write delay Voltage center optimization
576 04:24:25.451646 INFO : End of 2D write delay Voltage center optimization
577 04:24:25.457085 INFO : Training has run successfully!
578 04:24:25.457580
579 04:24:25.458044 channel==0
580 04:24:25.462697 RxClkDly_Margin_A0==88 ps 9
581 04:24:25.463177 TxDqDly_Margin_A0==98 ps 10
582 04:24:25.468312 RxClkDly_Margin_A1==88 ps 9
583 04:24:25.468791 TxDqDly_Margin_A1==98 ps 10
584 04:24:25.469246 TrainedVREFDQ_A0==74
585 04:24:25.473901 TrainedVREFDQ_A1==75
586 04:24:25.474385 VrefDac_Margin_A0==25
587 04:24:25.474833 DeviceVref_Margin_A0==40
588 04:24:25.479508 VrefDac_Margin_A1==25
589 04:24:25.479977 DeviceVref_Margin_A1==39
590 04:24:25.480462
591 04:24:25.480908
592 04:24:25.485076 channel==1
593 04:24:25.485546 RxClkDly_Margin_A0==88 ps 9
594 04:24:25.485992 TxDqDly_Margin_A0==88 ps 9
595 04:24:25.490689 RxClkDly_Margin_A1==88 ps 9
596 04:24:25.491158 TxDqDly_Margin_A1==88 ps 9
597 04:24:25.496299 TrainedVREFDQ_A0==76
598 04:24:25.496784 TrainedVREFDQ_A1==77
599 04:24:25.497210 VrefDac_Margin_A0==22
600 04:24:25.501894 DeviceVref_Margin_A0==38
601 04:24:25.502199 VrefDac_Margin_A1==24
602 04:24:25.507516 DeviceVref_Margin_A1==37
603 04:24:25.507819
604 04:24:25.508072 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 04:24:25.508305
606 04:24:25.541103 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 04:24:25.541489 2D training succeed
608 04:24:25.546710 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 04:24:25.552274 auto size-- 65535DDR cs0 size: 2048MB
610 04:24:25.552726 DDR cs1 size: 2048MB
611 04:24:25.557879 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 04:24:25.558178 cs0 DataBus test pass
613 04:24:25.563541 cs1 DataBus test pass
614 04:24:25.563969 cs0 AddrBus test pass
615 04:24:25.564628 cs1 AddrBus test pass
616 04:24:25.565129
617 04:24:25.569113 100bdlr_step_size ps== 420
618 04:24:25.569711 result report
619 04:24:25.574778 boot times 0Enable ddr reg access
620 04:24:25.579870 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 04:24:25.592410 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 04:24:26.166410 0.0;M3 CHK:0;cm4_sp_mode 0
623 04:24:26.167091 MVN_1=0x00000000
624 04:24:26.171896 MVN_2=0x00000000
625 04:24:26.177749 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 04:24:26.178354 OPS=0x10
627 04:24:26.178857 ring efuse init
628 04:24:26.179353 chipver efuse init
629 04:24:26.185723 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 04:24:26.186300 [0.018961 Inits done]
631 04:24:26.193421 secure task start!
632 04:24:26.193918 high task start!
633 04:24:26.194364 low task start!
634 04:24:26.194799 run into bl31
635 04:24:26.200093 NOTICE: BL31: v1.3(release):4fc40b1
636 04:24:26.207885 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 04:24:26.208434 NOTICE: BL31: G12A normal boot!
638 04:24:26.233241 NOTICE: BL31: BL33 decompress pass
639 04:24:26.238902 ERROR: Error initializing runtime service opteed_fast
640 04:24:27.583025
641 04:24:27.583687
642 04:24:27.585947 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 04:24:27.586463
644 04:24:27.586925 Model: Libre Computer AML-A311D-CC Alta
645 04:24:27.688539 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 04:24:27.711946 DRAM: 2 GiB (effective 3.8 GiB)
647 04:24:27.854910 Core: 408 devices, 31 uclasses, devicetree: separate
648 04:24:27.860779 WDT: Not starting watchdog@f0d0
649 04:24:27.893049 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 04:24:27.905517 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 04:24:27.910468 ** Bad device specification mmc 0 **
652 04:24:27.920803 Card did not respond to voltage select! : -110
653 04:24:27.928452 ** Bad device specification mmc 0 **
654 04:24:27.928782 Couldn't find partition mmc 0
655 04:24:27.936805 Card did not respond to voltage select! : -110
656 04:24:27.942295 ** Bad device specification mmc 0 **
657 04:24:27.942727 Couldn't find partition mmc 0
658 04:24:27.947355 Error: could not access storage.
659 04:24:28.289854 Net: eth0: ethernet@ff3f0000
660 04:24:28.290285 starting USB...
661 04:24:28.541761 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 04:24:28.542546 Starting the controller
663 04:24:28.548615 USB XHCI 1.10
664 04:24:30.261353 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 04:24:30.262008 bl2_stage_init 0x01
666 04:24:30.262454 bl2_stage_init 0x81
667 04:24:30.266979 hw id: 0x0000 - pwm id 0x01
668 04:24:30.267465 bl2_stage_init 0xc1
669 04:24:30.267885 bl2_stage_init 0x02
670 04:24:30.268459
671 04:24:30.272546 L0:00000000
672 04:24:30.273027 L1:20000703
673 04:24:30.273446 L2:00008067
674 04:24:30.273848 L3:14000000
675 04:24:30.275403 B2:00402000
676 04:24:30.275868 B1:e0f83180
677 04:24:30.276322
678 04:24:30.276733 TE: 58124
679 04:24:30.277137
680 04:24:30.286416 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 04:24:30.286911
682 04:24:30.287327 Board ID = 1
683 04:24:30.287728 Set A53 clk to 24M
684 04:24:30.288163 Set A73 clk to 24M
685 04:24:30.292083 Set clk81 to 24M
686 04:24:30.292551 A53 clk: 1200 MHz
687 04:24:30.292964 A73 clk: 1200 MHz
688 04:24:30.297677 CLK81: 166.6M
689 04:24:30.298155 smccc: 00012a92
690 04:24:30.303212 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 04:24:30.303696 board id: 1
692 04:24:30.312216 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 04:24:30.322573 fw parse done
694 04:24:30.328577 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 04:24:30.371144 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 04:24:30.382186 PIEI prepare done
697 04:24:30.382705 fastboot data load
698 04:24:30.383125 fastboot data verify
699 04:24:30.387764 verify result: 266
700 04:24:30.393340 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 04:24:30.393828 LPDDR4 probe
702 04:24:30.394242 ddr clk to 1584MHz
703 04:24:30.401357 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 04:24:30.438798
705 04:24:30.439412 dmc_version 0001
706 04:24:30.445395 Check phy result
707 04:24:30.451236 INFO : End of CA training
708 04:24:30.451747 INFO : End of initialization
709 04:24:30.456835 INFO : Training has run successfully!
710 04:24:30.457343 Check phy result
711 04:24:30.462446 INFO : End of initialization
712 04:24:30.462957 INFO : End of read enable training
713 04:24:30.465713 INFO : End of fine write leveling
714 04:24:30.471291 INFO : End of Write leveling coarse delay
715 04:24:30.476851 INFO : Training has run successfully!
716 04:24:30.477363 Check phy result
717 04:24:30.477782 INFO : End of initialization
718 04:24:30.482452 INFO : End of read dq deskew training
719 04:24:30.488102 INFO : End of MPR read delay center optimization
720 04:24:30.488633 INFO : End of write delay center optimization
721 04:24:30.493645 INFO : End of read delay center optimization
722 04:24:30.499247 INFO : End of max read latency training
723 04:24:30.499769 INFO : Training has run successfully!
724 04:24:30.504847 1D training succeed
725 04:24:30.510894 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 04:24:30.558336 Check phy result
727 04:24:30.558863 INFO : End of initialization
728 04:24:30.580791 INFO : End of 2D read delay Voltage center optimization
729 04:24:30.600898 INFO : End of 2D read delay Voltage center optimization
730 04:24:30.652858 INFO : End of 2D write delay Voltage center optimization
731 04:24:30.702083 INFO : End of 2D write delay Voltage center optimization
732 04:24:30.707656 INFO : Training has run successfully!
733 04:24:30.708191
734 04:24:30.708614 channel==0
735 04:24:30.713263 RxClkDly_Margin_A0==88 ps 9
736 04:24:30.713764 TxDqDly_Margin_A0==98 ps 10
737 04:24:30.716511 RxClkDly_Margin_A1==88 ps 9
738 04:24:30.716991 TxDqDly_Margin_A1==98 ps 10
739 04:24:30.722182 TrainedVREFDQ_A0==74
740 04:24:30.722659 TrainedVREFDQ_A1==75
741 04:24:30.723072 VrefDac_Margin_A0==24
742 04:24:30.727688 DeviceVref_Margin_A0==40
743 04:24:30.728196 VrefDac_Margin_A1==24
744 04:24:30.733361 DeviceVref_Margin_A1==39
745 04:24:30.733849
746 04:24:30.734265
747 04:24:30.734671 channel==1
748 04:24:30.735068 RxClkDly_Margin_A0==88 ps 9
749 04:24:30.736734 TxDqDly_Margin_A0==98 ps 10
750 04:24:30.742294 RxClkDly_Margin_A1==98 ps 10
751 04:24:30.742774 TxDqDly_Margin_A1==88 ps 9
752 04:24:30.743188 TrainedVREFDQ_A0==77
753 04:24:30.747821 TrainedVREFDQ_A1==77
754 04:24:30.748330 VrefDac_Margin_A0==22
755 04:24:30.753478 DeviceVref_Margin_A0==37
756 04:24:30.753951 VrefDac_Margin_A1==22
757 04:24:30.754366 DeviceVref_Margin_A1==37
758 04:24:30.754767
759 04:24:30.758998 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 04:24:30.759476
761 04:24:30.792530 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
762 04:24:30.793095 2D training succeed
763 04:24:30.798235 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 04:24:30.803830 auto size-- 65535DDR cs0 size: 2048MB
765 04:24:30.804361 DDR cs1 size: 2048MB
766 04:24:30.809430 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 04:24:30.809921 cs0 DataBus test pass
768 04:24:30.810338 cs1 DataBus test pass
769 04:24:30.815018 cs0 AddrBus test pass
770 04:24:30.815515 cs1 AddrBus test pass
771 04:24:30.815929
772 04:24:30.820613 100bdlr_step_size ps== 420
773 04:24:30.821122 result report
774 04:24:30.821533 boot times 0Enable ddr reg access
775 04:24:30.830444 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 04:24:30.843938 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 04:24:31.416036 0.0;M3 CHK:0;cm4_sp_mode 0
778 04:24:31.416679 MVN_1=0x00000000
779 04:24:31.421459 MVN_2=0x00000000
780 04:24:31.427180 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 04:24:31.427746 OPS=0x10
782 04:24:31.428192 ring efuse init
783 04:24:31.428586 chipver efuse init
784 04:24:31.432748 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 04:24:31.438406 [0.018961 Inits done]
786 04:24:31.438914 secure task start!
787 04:24:31.439310 high task start!
788 04:24:31.442921 low task start!
789 04:24:31.443426 run into bl31
790 04:24:31.449581 NOTICE: BL31: v1.3(release):4fc40b1
791 04:24:31.457385 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 04:24:31.457892 NOTICE: BL31: G12A normal boot!
793 04:24:31.482768 NOTICE: BL31: BL33 decompress pass
794 04:24:31.488465 ERROR: Error initializing runtime service opteed_fast
795 04:24:32.721334
796 04:24:32.721944
797 04:24:32.729708 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 04:24:32.730183
799 04:24:32.730600 Model: Libre Computer AML-A311D-CC Alta
800 04:24:32.938098 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 04:24:32.961496 DRAM: 2 GiB (effective 3.8 GiB)
802 04:24:33.104474 Core: 408 devices, 31 uclasses, devicetree: separate
803 04:24:33.110352 WDT: Not starting watchdog@f0d0
804 04:24:33.142616 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 04:24:33.155050 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 04:24:33.160109 ** Bad device specification mmc 0 **
807 04:24:33.170378 Card did not respond to voltage select! : -110
808 04:24:33.178034 ** Bad device specification mmc 0 **
809 04:24:33.178507 Couldn't find partition mmc 0
810 04:24:33.186371 Card did not respond to voltage select! : -110
811 04:24:33.191884 ** Bad device specification mmc 0 **
812 04:24:33.192372 Couldn't find partition mmc 0
813 04:24:33.196946 Error: could not access storage.
814 04:24:33.539376 Net: eth0: ethernet@ff3f0000
815 04:24:33.539975 starting USB...
816 04:24:33.791214 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 04:24:33.791758 Starting the controller
818 04:24:33.798183 USB XHCI 1.10
819 04:24:35.962972 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 04:24:35.963573 bl2_stage_init 0x01
821 04:24:35.964031 bl2_stage_init 0x81
822 04:24:35.968415 hw id: 0x0000 - pwm id 0x01
823 04:24:35.968892 bl2_stage_init 0xc1
824 04:24:35.969311 bl2_stage_init 0x02
825 04:24:35.969715
826 04:24:35.974011 L0:00000000
827 04:24:35.974474 L1:20000703
828 04:24:35.974878 L2:00008067
829 04:24:35.975277 L3:14000000
830 04:24:35.979682 B2:00402000
831 04:24:35.980164 B1:e0f83180
832 04:24:35.980573
833 04:24:35.980975 TE: 58124
834 04:24:35.981379
835 04:24:35.985217 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 04:24:35.985676
837 04:24:35.986080 Board ID = 1
838 04:24:35.990893 Set A53 clk to 24M
839 04:24:35.991346 Set A73 clk to 24M
840 04:24:35.991747 Set clk81 to 24M
841 04:24:35.996481 A53 clk: 1200 MHz
842 04:24:35.996934 A73 clk: 1200 MHz
843 04:24:35.997340 CLK81: 166.6M
844 04:24:35.997735 smccc: 00012a91
845 04:24:36.002093 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 04:24:36.007629 board id: 1
847 04:24:36.013697 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 04:24:36.024114 fw parse done
849 04:24:36.030147 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 04:24:36.072681 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 04:24:36.083698 PIEI prepare done
852 04:24:36.084210 fastboot data load
853 04:24:36.084623 fastboot data verify
854 04:24:36.089286 verify result: 266
855 04:24:36.094885 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 04:24:36.095351 LPDDR4 probe
857 04:24:36.095755 ddr clk to 1584MHz
858 04:24:36.102828 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 04:24:36.140269
860 04:24:36.140781 dmc_version 0001
861 04:24:36.146868 Check phy result
862 04:24:36.152630 INFO : End of CA training
863 04:24:36.153090 INFO : End of initialization
864 04:24:36.158298 INFO : Training has run successfully!
865 04:24:36.158764 Check phy result
866 04:24:36.163924 INFO : End of initialization
867 04:24:36.164416 INFO : End of read enable training
868 04:24:36.167203 INFO : End of fine write leveling
869 04:24:36.172879 INFO : End of Write leveling coarse delay
870 04:24:36.178456 INFO : Training has run successfully!
871 04:24:36.178930 Check phy result
872 04:24:36.179338 INFO : End of initialization
873 04:24:36.184053 INFO : End of read dq deskew training
874 04:24:36.189655 INFO : End of MPR read delay center optimization
875 04:24:36.190122 INFO : End of write delay center optimization
876 04:24:36.195183 INFO : End of read delay center optimization
877 04:24:36.200858 INFO : End of max read latency training
878 04:24:36.201326 INFO : Training has run successfully!
879 04:24:36.206469 1D training succeed
880 04:24:36.212285 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 04:24:36.259852 Check phy result
882 04:24:36.260376 INFO : End of initialization
883 04:24:36.281507 INFO : End of 2D read delay Voltage center optimization
884 04:24:36.301627 INFO : End of 2D read delay Voltage center optimization
885 04:24:36.353576 INFO : End of 2D write delay Voltage center optimization
886 04:24:36.402831 INFO : End of 2D write delay Voltage center optimization
887 04:24:36.408378 INFO : Training has run successfully!
888 04:24:36.408839
889 04:24:36.409248 channel==0
890 04:24:36.413965 RxClkDly_Margin_A0==88 ps 9
891 04:24:36.414499 TxDqDly_Margin_A0==98 ps 10
892 04:24:36.417420 RxClkDly_Margin_A1==88 ps 9
893 04:24:36.417929 TxDqDly_Margin_A1==98 ps 10
894 04:24:36.422951 TrainedVREFDQ_A0==74
895 04:24:36.423433 TrainedVREFDQ_A1==74
896 04:24:36.423840 VrefDac_Margin_A0==25
897 04:24:36.428465 DeviceVref_Margin_A0==40
898 04:24:36.428931 VrefDac_Margin_A1==25
899 04:24:36.434112 DeviceVref_Margin_A1==40
900 04:24:36.434554
901 04:24:36.434942
902 04:24:36.435323 channel==1
903 04:24:36.435700 RxClkDly_Margin_A0==88 ps 9
904 04:24:36.437516 TxDqDly_Margin_A0==98 ps 10
905 04:24:36.443047 RxClkDly_Margin_A1==88 ps 9
906 04:24:36.443492 TxDqDly_Margin_A1==88 ps 9
907 04:24:36.443880 TrainedVREFDQ_A0==77
908 04:24:36.448701 TrainedVREFDQ_A1==77
909 04:24:36.449148 VrefDac_Margin_A0==22
910 04:24:36.454213 DeviceVref_Margin_A0==37
911 04:24:36.454667 VrefDac_Margin_A1==24
912 04:24:36.455050 DeviceVref_Margin_A1==37
913 04:24:36.455430
914 04:24:36.459809 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 04:24:36.460283
916 04:24:36.493366 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 04:24:36.493892 2D training succeed
918 04:24:36.499031 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 04:24:36.504647 auto size-- 65535DDR cs0 size: 2048MB
920 04:24:36.505128 DDR cs1 size: 2048MB
921 04:24:36.510217 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 04:24:36.510680 cs0 DataBus test pass
923 04:24:36.511063 cs1 DataBus test pass
924 04:24:36.515853 cs0 AddrBus test pass
925 04:24:36.516350 cs1 AddrBus test pass
926 04:24:36.516737
927 04:24:36.521445 100bdlr_step_size ps== 420
928 04:24:36.521917 result report
929 04:24:36.522304 boot times 0Enable ddr reg access
930 04:24:36.531110 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 04:24:36.544591 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 04:24:37.116586 0.0;M3 CHK:0;cm4_sp_mode 0
933 04:24:37.117193 MVN_1=0x00000000
934 04:24:37.122047 MVN_2=0x00000000
935 04:24:37.127780 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 04:24:37.128284 OPS=0x10
937 04:24:37.128693 ring efuse init
938 04:24:37.129087 chipver efuse init
939 04:24:37.133382 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 04:24:37.138971 [0.018961 Inits done]
941 04:24:37.139427 secure task start!
942 04:24:37.139829 high task start!
943 04:24:37.143553 low task start!
944 04:24:37.144028 run into bl31
945 04:24:37.150226 NOTICE: BL31: v1.3(release):4fc40b1
946 04:24:37.158043 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 04:24:37.158507 NOTICE: BL31: G12A normal boot!
948 04:24:37.183913 NOTICE: BL31: BL33 decompress pass
949 04:24:37.189599 ERROR: Error initializing runtime service opteed_fast
950 04:24:38.422570
951 04:24:38.423174
952 04:24:38.430879 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 04:24:38.431348
954 04:24:38.431759 Model: Libre Computer AML-A311D-CC Alta
955 04:24:38.639302 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 04:24:38.662662 DRAM: 2 GiB (effective 3.8 GiB)
957 04:24:38.805661 Core: 408 devices, 31 uclasses, devicetree: separate
958 04:24:38.811512 WDT: Not starting watchdog@f0d0
959 04:24:38.843810 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 04:24:38.856232 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 04:24:38.861244 ** Bad device specification mmc 0 **
962 04:24:38.871583 Card did not respond to voltage select! : -110
963 04:24:38.879230 ** Bad device specification mmc 0 **
964 04:24:38.879707 Couldn't find partition mmc 0
965 04:24:38.887578 Card did not respond to voltage select! : -110
966 04:24:38.893082 ** Bad device specification mmc 0 **
967 04:24:38.893551 Couldn't find partition mmc 0
968 04:24:38.898157 Error: could not access storage.
969 04:24:39.240512 Net: eth0: ethernet@ff3f0000
970 04:24:39.241091 starting USB...
971 04:24:39.492508 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 04:24:39.493097 Starting the controller
973 04:24:39.499415 USB XHCI 1.10
974 04:24:41.362805 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 04:24:41.363415 bl2_stage_init 0x01
976 04:24:41.363835 bl2_stage_init 0x81
977 04:24:41.368387 hw id: 0x0000 - pwm id 0x01
978 04:24:41.368856 bl2_stage_init 0xc1
979 04:24:41.369268 bl2_stage_init 0x02
980 04:24:41.369667
981 04:24:41.373970 L0:00000000
982 04:24:41.374436 L1:20000703
983 04:24:41.374844 L2:00008067
984 04:24:41.375242 L3:14000000
985 04:24:41.379569 B2:00402000
986 04:24:41.380066 B1:e0f83180
987 04:24:41.380482
988 04:24:41.380887 TE: 58159
989 04:24:41.381284
990 04:24:41.385176 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 04:24:41.385648
992 04:24:41.386058 Board ID = 1
993 04:24:41.390808 Set A53 clk to 24M
994 04:24:41.391267 Set A73 clk to 24M
995 04:24:41.391666 Set clk81 to 24M
996 04:24:41.396359 A53 clk: 1200 MHz
997 04:24:41.396853 A73 clk: 1200 MHz
998 04:24:41.397295 CLK81: 166.6M
999 04:24:41.397724 smccc: 00012ab5
1000 04:24:41.402014 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 04:24:41.407629 board id: 1
1002 04:24:41.416267 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 04:24:41.424183 fw parse done
1004 04:24:41.430063 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 04:24:41.472662 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 04:24:41.483513 PIEI prepare done
1007 04:24:41.483957 fastboot data load
1008 04:24:41.484420 fastboot data verify
1009 04:24:41.489105 verify result: 266
1010 04:24:41.494742 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 04:24:41.495173 LPDDR4 probe
1012 04:24:41.495568 ddr clk to 1584MHz
1013 04:24:41.502796 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 04:24:41.540023
1015 04:24:41.540507 dmc_version 0001
1016 04:24:41.546640 Check phy result
1017 04:24:41.552474 INFO : End of CA training
1018 04:24:41.552908 INFO : End of initialization
1019 04:24:41.558292 INFO : Training has run successfully!
1020 04:24:41.558793 Check phy result
1021 04:24:41.563931 INFO : End of initialization
1022 04:24:41.564432 INFO : End of read enable training
1023 04:24:41.567046 INFO : End of fine write leveling
1024 04:24:41.572644 INFO : End of Write leveling coarse delay
1025 04:24:41.578186 INFO : Training has run successfully!
1026 04:24:41.578634 Check phy result
1027 04:24:41.579039 INFO : End of initialization
1028 04:24:41.583910 INFO : End of read dq deskew training
1029 04:24:41.589428 INFO : End of MPR read delay center optimization
1030 04:24:41.589873 INFO : End of write delay center optimization
1031 04:24:41.594902 INFO : End of read delay center optimization
1032 04:24:41.600616 INFO : End of max read latency training
1033 04:24:41.601058 INFO : Training has run successfully!
1034 04:24:41.606183 1D training succeed
1035 04:24:41.612325 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 04:24:41.659921 Check phy result
1037 04:24:41.660441 INFO : End of initialization
1038 04:24:41.681588 INFO : End of 2D read delay Voltage center optimization
1039 04:24:41.700978 INFO : End of 2D read delay Voltage center optimization
1040 04:24:41.752986 INFO : End of 2D write delay Voltage center optimization
1041 04:24:41.802444 INFO : End of 2D write delay Voltage center optimization
1042 04:24:41.808079 INFO : Training has run successfully!
1043 04:24:41.808542
1044 04:24:41.808955 channel==0
1045 04:24:41.813472 RxClkDly_Margin_A0==88 ps 9
1046 04:24:41.813916 TxDqDly_Margin_A0==98 ps 10
1047 04:24:41.819179 RxClkDly_Margin_A1==88 ps 9
1048 04:24:41.819612 TxDqDly_Margin_A1==98 ps 10
1049 04:24:41.820061 TrainedVREFDQ_A0==74
1050 04:24:41.824848 TrainedVREFDQ_A1==74
1051 04:24:41.825285 VrefDac_Margin_A0==25
1052 04:24:41.825688 DeviceVref_Margin_A0==40
1053 04:24:41.830294 VrefDac_Margin_A1==25
1054 04:24:41.830732 DeviceVref_Margin_A1==40
1055 04:24:41.831128
1056 04:24:41.831521
1057 04:24:41.835893 channel==1
1058 04:24:41.836364 RxClkDly_Margin_A0==78 ps 8
1059 04:24:41.836768 TxDqDly_Margin_A0==98 ps 10
1060 04:24:41.841566 RxClkDly_Margin_A1==88 ps 9
1061 04:24:41.842002 TxDqDly_Margin_A1==88 ps 9
1062 04:24:41.847162 TrainedVREFDQ_A0==77
1063 04:24:41.847597 TrainedVREFDQ_A1==77
1064 04:24:41.848054 VrefDac_Margin_A0==23
1065 04:24:41.852690 DeviceVref_Margin_A0==37
1066 04:24:41.853122 VrefDac_Margin_A1==24
1067 04:24:41.858339 DeviceVref_Margin_A1==37
1068 04:24:41.858774
1069 04:24:41.859176 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 04:24:41.859574
1071 04:24:41.892034 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000019 00000019 00000019 00000018 00000017 00000019 00000017 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 04:24:41.892511 2D training succeed
1073 04:24:41.897440 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 04:24:41.902966 auto size-- 65535DDR cs0 size: 2048MB
1075 04:24:41.903392 DDR cs1 size: 2048MB
1076 04:24:41.908600 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 04:24:41.909039 cs0 DataBus test pass
1078 04:24:41.914227 cs1 DataBus test pass
1079 04:24:41.914660 cs0 AddrBus test pass
1080 04:24:41.915059 cs1 AddrBus test pass
1081 04:24:41.915456
1082 04:24:41.919790 100bdlr_step_size ps== 420
1083 04:24:41.920279 result report
1084 04:24:41.925379 boot times 0Enable ddr reg access
1085 04:24:41.930665 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 04:24:41.944132 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 04:24:42.517417 0.0;M3 CHK:0;cm4_sp_mode 0
1088 04:24:42.518052 MVN_1=0x00000000
1089 04:24:42.522792 MVN_2=0x00000000
1090 04:24:42.528551 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 04:24:42.529031 OPS=0x10
1092 04:24:42.529448 ring efuse init
1093 04:24:42.529853 chipver efuse init
1094 04:24:42.534090 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 04:24:42.539715 [0.018961 Inits done]
1096 04:24:42.540219 secure task start!
1097 04:24:42.540630 high task start!
1098 04:24:42.544263 low task start!
1099 04:24:42.544711 run into bl31
1100 04:24:42.550947 NOTICE: BL31: v1.3(release):4fc40b1
1101 04:24:42.558734 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 04:24:42.559181 NOTICE: BL31: G12A normal boot!
1103 04:24:42.584178 NOTICE: BL31: BL33 decompress pass
1104 04:24:42.589953 ERROR: Error initializing runtime service opteed_fast
1105 04:24:43.822734
1106 04:24:43.823335
1107 04:24:43.831116 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 04:24:43.831588
1109 04:24:43.832037 Model: Libre Computer AML-A311D-CC Alta
1110 04:24:44.039489 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 04:24:44.062882 DRAM: 2 GiB (effective 3.8 GiB)
1112 04:24:44.205974 Core: 408 devices, 31 uclasses, devicetree: separate
1113 04:24:44.211721 WDT: Not starting watchdog@f0d0
1114 04:24:44.244040 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 04:24:44.256447 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 04:24:44.261409 ** Bad device specification mmc 0 **
1117 04:24:44.271750 Card did not respond to voltage select! : -110
1118 04:24:44.279409 ** Bad device specification mmc 0 **
1119 04:24:44.279857 Couldn't find partition mmc 0
1120 04:24:44.287740 Card did not respond to voltage select! : -110
1121 04:24:44.293254 ** Bad device specification mmc 0 **
1122 04:24:44.293691 Couldn't find partition mmc 0
1123 04:24:44.298320 Error: could not access storage.
1124 04:24:44.641940 Net: eth0: ethernet@ff3f0000
1125 04:24:44.642366 starting USB...
1126 04:24:44.893735 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 04:24:44.894314 Starting the controller
1128 04:24:44.900652 USB XHCI 1.10
1129 04:24:46.454881 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 04:24:46.463173 scanning usb for storage devices... 0 Storage Device(s) found
1132 04:24:46.515128 Hit any key to stop autoboot: 1
1133 04:24:46.516232 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 04:24:46.516997 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 04:24:46.517590 Setting prompt string to ['=>']
1136 04:24:46.518203 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 04:24:46.530620 0
1138 04:24:46.531690 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 04:24:46.532399 Sending with 10 millisecond of delay
1141 04:24:47.667620 => setenv autoload no
1142 04:24:47.678692 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 04:24:47.684909 setenv autoload no
1144 04:24:47.685834 Sending with 10 millisecond of delay
1146 04:24:49.483673 => setenv initrd_high 0xffffffff
1147 04:24:49.494713 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 04:24:49.495841 setenv initrd_high 0xffffffff
1149 04:24:49.496780 Sending with 10 millisecond of delay
1151 04:24:51.112977 => setenv fdt_high 0xffffffff
1152 04:24:51.123682 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 04:24:51.124219 setenv fdt_high 0xffffffff
1154 04:24:51.124708 Sending with 10 millisecond of delay
1156 04:24:51.416064 => dhcp
1157 04:24:51.426902 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 04:24:51.428015 dhcp
1159 04:24:51.428582 Speed: 1000, full duplex
1160 04:24:51.429115 BOOTP broadcast 1
1161 04:24:51.435687 DHCP client bound to address 192.168.6.27 (9 ms)
1162 04:24:51.436551 Sending with 10 millisecond of delay
1164 04:24:53.113257 => setenv serverip 192.168.6.2
1165 04:24:53.124075 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 04:24:53.124942 setenv serverip 192.168.6.2
1167 04:24:53.125632 Sending with 10 millisecond of delay
1169 04:24:56.851153 => tftpboot 0x01080000 950796/tftp-deploy-xbqxmg97/kernel/uImage
1170 04:24:56.861956 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 04:24:56.862795 tftpboot 0x01080000 950796/tftp-deploy-xbqxmg97/kernel/uImage
1172 04:24:56.863239 Speed: 1000, full duplex
1173 04:24:56.863647 Using ethernet@ff3f0000 device
1174 04:24:56.864713 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 04:24:56.870192 Filename '950796/tftp-deploy-xbqxmg97/kernel/uImage'.
1176 04:24:56.874197 Load address: 0x1080000
1177 04:24:59.734949 Loading: *################################################## 43.6 MiB
1178 04:24:59.735558 15.2 MiB/s
1179 04:24:59.736026 done
1180 04:24:59.739305 Bytes transferred = 45713984 (2b98a40 hex)
1181 04:24:59.740118 Sending with 10 millisecond of delay
1183 04:25:04.425802 => tftpboot 0x08000000 950796/tftp-deploy-xbqxmg97/ramdisk/ramdisk.cpio.gz.uboot
1184 04:25:04.436585 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 04:25:04.437178 tftpboot 0x08000000 950796/tftp-deploy-xbqxmg97/ramdisk/ramdisk.cpio.gz.uboot
1186 04:25:04.437442 Speed: 1000, full duplex
1187 04:25:04.437670 Using ethernet@ff3f0000 device
1188 04:25:04.438997 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 04:25:04.450789 Filename '950796/tftp-deploy-xbqxmg97/ramdisk/ramdisk.cpio.gz.uboot'.
1190 04:25:04.451109 Load address: 0x8000000
1191 04:25:11.066537 Loading: *#################T ################################# 22.3 MiB
1192 04:25:11.067157 3.4 MiB/s
1193 04:25:11.067588 done
1194 04:25:11.070938 Bytes transferred = 23432020 (1658b54 hex)
1195 04:25:11.071736 Sending with 10 millisecond of delay
1197 04:25:16.242199 => tftpboot 0x01070000 950796/tftp-deploy-xbqxmg97/dtb/meson-g12b-a311d-libretech-cc.dtb
1198 04:25:16.253053 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:53)
1199 04:25:16.253920 tftpboot 0x01070000 950796/tftp-deploy-xbqxmg97/dtb/meson-g12b-a311d-libretech-cc.dtb
1200 04:25:16.254442 Speed: 1000, full duplex
1201 04:25:16.254898 Using ethernet@ff3f0000 device
1202 04:25:16.258100 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1203 04:25:16.265564 Filename '950796/tftp-deploy-xbqxmg97/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1204 04:25:16.277585 Load address: 0x1070000
1205 04:25:16.289635 Loading: *################################################## 53.4 KiB
1206 04:25:16.290196 2.9 MiB/s
1207 04:25:16.290658 done
1208 04:25:16.294169 Bytes transferred = 54703 (d5af hex)
1209 04:25:16.294929 Sending with 10 millisecond of delay
1211 04:25:29.603207 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950796/extract-nfsrootfs-7h5f4j8z,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1212 04:25:29.614030 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:40)
1213 04:25:29.614917 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950796/extract-nfsrootfs-7h5f4j8z,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1214 04:25:29.615623 Sending with 10 millisecond of delay
1216 04:25:31.957752 => bootm 0x01080000 0x08000000 0x01070000
1217 04:25:31.968633 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1218 04:25:31.969251 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:37)
1219 04:25:31.970342 bootm 0x01080000 0x08000000 0x01070000
1220 04:25:31.970827 ## Booting kernel from Legacy Image at 01080000 ...
1221 04:25:31.973848 Image Name:
1222 04:25:31.979861 Image Type: AArch64 Linux Kernel Image (uncompressed)
1223 04:25:31.980387 Data Size: 45713920 Bytes = 43.6 MiB
1224 04:25:31.981563 Load Address: 01080000
1225 04:25:31.987918 Entry Point: 01080000
1226 04:25:32.180714 Verifying Checksum ... OK
1227 04:25:32.181347 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1228 04:25:32.185745 Image Name:
1229 04:25:32.191461 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1230 04:25:32.192019 Data Size: 23431956 Bytes = 22.3 MiB
1231 04:25:32.193560 Load Address: 00000000
1232 04:25:32.200407 Entry Point: 00000000
1233 04:25:32.298681 Verifying Checksum ... OK
1234 04:25:32.299251 ## Flattened Device Tree blob at 01070000
1235 04:25:32.304076 Booting using the fdt blob at 0x1070000
1236 04:25:32.304566 Working FDT set to 1070000
1237 04:25:32.308467 Loading Kernel Image
1238 04:25:32.459658 Loading Ramdisk to 7e9a7000, end 7ffffb14 ... OK
1239 04:25:32.467829 Loading Device Tree to 000000007e996000, end 000000007e9a65ae ... OK
1240 04:25:32.468432 Working FDT set to 7e996000
1241 04:25:32.468896
1242 04:25:32.469871 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1243 04:25:32.470560 start: 2.4.4 auto-login-action (timeout 00:03:37) [common]
1244 04:25:32.471096 Setting prompt string to ['Linux version [0-9]']
1245 04:25:32.471605 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1246 04:25:32.472192 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1247 04:25:32.473352 Starting kernel ...
1248 04:25:32.473893
1249 04:25:32.508059 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1250 04:25:32.509207 start: 2.4.4.1 login-action (timeout 00:03:37) [common]
1251 04:25:32.509800 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1252 04:25:32.510332 Setting prompt string to []
1253 04:25:32.510880 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1254 04:25:32.511411 Using line separator: #'\n'#
1255 04:25:32.511871 No login prompt set.
1256 04:25:32.512402 Parsing kernel messages
1257 04:25:32.512850 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1258 04:25:32.513744 [login-action] Waiting for messages, (timeout 00:03:37)
1259 04:25:32.514249 Waiting using forced prompt support (timeout 00:01:48)
1260 04:25:32.528108 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j365965-arm64-gcc-12-defconfig-lbnql) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Nov 7 00:22:50 UTC 2024
1261 04:25:32.528756 [ 0.000000] KASLR disabled due to lack of seed
1262 04:25:32.533634 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1263 04:25:32.539160 [ 0.000000] efi: UEFI not found.
1264 04:25:32.544687 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1265 04:25:32.555673 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1266 04:25:32.561247 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1267 04:25:32.572269 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1268 04:25:32.584179 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1269 04:25:32.589667 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1270 04:25:32.600714 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1271 04:25:32.606253 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1272 04:25:32.611874 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1273 04:25:32.617253 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1274 04:25:32.617807 [ 0.000000] Zone ranges:
1275 04:25:32.628207 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1276 04:25:32.628518 [ 0.000000] DMA32 empty
1277 04:25:32.633642 [ 0.000000] Normal empty
1278 04:25:32.634183 [ 0.000000] Movable zone start for each node
1279 04:25:32.639199 [ 0.000000] Early memory node ranges
1280 04:25:32.644908 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1281 04:25:32.650295 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1282 04:25:32.655761 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1283 04:25:32.665418 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1284 04:25:32.689664 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1285 04:25:32.695231 [ 0.000000] psci: probing for conduit method from DT.
1286 04:25:32.695723 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1287 04:25:32.704352 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1288 04:25:32.704919 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1289 04:25:32.709841 [ 0.000000] psci: SMC Calling Convention v1.1
1290 04:25:32.715436 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1291 04:25:32.720858 [ 0.000000] Detected VIPT I-cache on CPU0
1292 04:25:32.726412 [ 0.000000] CPU features: detected: ARM erratum 845719
1293 04:25:32.731921 [ 0.000000] alternatives: applying boot alternatives
1294 04:25:32.754033 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950796/extract-nfsrootfs-7h5f4j8z,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1295 04:25:32.759558 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1296 04:25:32.770493 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1297 04:25:32.771094 <6>[ 0.000000] Fallback order for Node 0: 0
1298 04:25:32.781598 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1299 04:25:32.782160 <6>[ 0.000000] Policy zone: DMA
1300 04:25:32.787109 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1301 04:25:32.798165 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1302 04:25:32.798709 <6>[ 0.000000] software IO TLB: area num 8.
1303 04:25:32.809187 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1304 04:25:32.855756 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1305 04:25:32.861240 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1306 04:25:32.866874 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1307 04:25:32.872454 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1308 04:25:32.877866 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1309 04:25:32.884779 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1310 04:25:32.888887 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1311 04:25:32.894491 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1312 04:25:32.905590 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1313 04:25:32.917030 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1314 04:25:32.922148 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1315 04:25:32.927537 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1316 04:25:32.928259 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1317 04:25:32.937681 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1318 04:25:32.950398 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1319 04:25:32.961052 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1320 04:25:32.966645 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1321 04:25:32.972244 <6>[ 0.008799] Console: colour dummy device 80x25
1322 04:25:32.983156 <6>[ 0.012940] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1323 04:25:32.988743 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1324 04:25:32.994365 <6>[ 0.028190] LSM: initializing lsm=capability
1325 04:25:32.999859 <6>[ 0.032731] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1326 04:25:33.005316 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1327 04:25:33.010861 <6>[ 0.052298] rcu: Hierarchical SRCU implementation.
1328 04:25:33.016396 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1329 04:25:33.027380 <6>[ 0.058883] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1330 04:25:33.035866 <6>[ 0.071607] EFI services will not be available.
1331 04:25:33.036490 <6>[ 0.075249] smp: Bringing up secondary CPUs ...
1332 04:25:33.048145 <6>[ 0.077131] Detected VIPT I-cache on CPU1
1333 04:25:33.055608 <6>[ 0.077252] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1334 04:25:33.059172 <6>[ 0.078599] CPU features: detected: Spectre-v2
1335 04:25:33.068433 <6>[ 0.078614] CPU features: detected: Spectre-v4
1336 04:25:33.069062 <6>[ 0.078619] CPU features: detected: Spectre-BHB
1337 04:25:33.073779 <6>[ 0.078624] CPU features: detected: ARM erratum 858921
1338 04:25:33.079141 <6>[ 0.078632] Detected VIPT I-cache on CPU2
1339 04:25:33.084750 <6>[ 0.078705] arch_timer: Enabling local workaround for ARM erratum 858921
1340 04:25:33.090254 <6>[ 0.078722] arch_timer: CPU2: Trapping CNTVCT access
1341 04:25:33.101279 <6>[ 0.078733] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1342 04:25:33.101937 <6>[ 0.079691] Detected VIPT I-cache on CPU3
1343 04:25:33.112365 <6>[ 0.079737] arch_timer: Enabling local workaround for ARM erratum 858921
1344 04:25:33.112982 <6>[ 0.079746] arch_timer: CPU3: Trapping CNTVCT access
1345 04:25:33.123395 <6>[ 0.079754] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1346 04:25:33.124037 <6>[ 0.083606] Detected VIPT I-cache on CPU4
1347 04:25:33.134357 <6>[ 0.083653] arch_timer: Enabling local workaround for ARM erratum 858921
1348 04:25:33.140099 <6>[ 0.083663] arch_timer: CPU4: Trapping CNTVCT access
1349 04:25:33.145509 <6>[ 0.083670] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1350 04:25:33.150991 <6>[ 0.091642] Detected VIPT I-cache on CPU5
1351 04:25:33.156541 <6>[ 0.091689] arch_timer: Enabling local workaround for ARM erratum 858921
1352 04:25:33.162090 <6>[ 0.091699] arch_timer: CPU5: Trapping CNTVCT access
1353 04:25:33.167653 <6>[ 0.091706] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1354 04:25:33.173011 <6>[ 0.091828] smp: Brought up 1 node, 6 CPUs
1355 04:25:33.178544 <6>[ 0.213054] SMP: Total of 6 processors activated.
1356 04:25:33.179148 <6>[ 0.217960] CPU: All CPU(s) started at EL2
1357 04:25:33.184174 <6>[ 0.222309] CPU features: detected: 32-bit EL0 Support
1358 04:25:33.189615 <6>[ 0.227621] CPU features: detected: 32-bit EL1 Support
1359 04:25:33.195040 <6>[ 0.232967] CPU features: detected: CRC32 instructions
1360 04:25:33.200644 <6>[ 0.238371] alternatives: applying system-wide alternatives
1361 04:25:33.217177 <6>[ 0.245554] Memory: 3557436K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187796K reserved, 262144K cma-reserved)
1362 04:25:33.224141 <6>[ 0.259909] devtmpfs: initialized
1363 04:25:33.235136 <6>[ 0.269047] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1364 04:25:33.240683 <6>[ 0.273402] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1365 04:25:33.246231 <6>[ 0.284203] 21392 pages in range for non-PLT usage
1366 04:25:33.251738 <6>[ 0.284213] 512912 pages in range for PLT usage
1367 04:25:33.257258 <6>[ 0.285762] pinctrl core: initialized pinctrl subsystem
1368 04:25:33.257806 <6>[ 0.297813] DMI not present or invalid.
1369 04:25:33.262784 <6>[ 0.302152] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1370 04:25:33.273753 <6>[ 0.306882] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1371 04:25:33.279325 <6>[ 0.313654] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1372 04:25:33.290380 <6>[ 0.321753] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1373 04:25:33.295824 <6>[ 0.329233] audit: initializing netlink subsys (disabled)
1374 04:25:33.301362 <5>[ 0.334975] audit: type=2000 audit(0.256:1): state=initialized audit_enabled=0 res=1
1375 04:25:33.306814 <6>[ 0.336396] thermal_sys: Registered thermal governor 'step_wise'
1376 04:25:33.312474 <6>[ 0.342740] thermal_sys: Registered thermal governor 'power_allocator'
1377 04:25:33.318115 <6>[ 0.349001] cpuidle: using governor menu
1378 04:25:33.323435 <6>[ 0.360047] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1379 04:25:33.328898 <6>[ 0.366919] ASID allocator initialised with 65536 entries
1380 04:25:33.337245 <6>[ 0.374464] Serial: AMBA PL011 UART driver
1381 04:25:33.346996 <6>[ 0.385026] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1382 04:25:33.362119 <6>[ 0.400422] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1383 04:25:33.371274 <6>[ 0.403087] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1384 04:25:33.376730 <6>[ 0.416199] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1385 04:25:33.388064 <6>[ 0.419465] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1386 04:25:33.393329 <6>[ 0.427895] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1387 04:25:33.404282 <6>[ 0.435516] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1388 04:25:33.409834 <6>[ 0.449080] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1389 04:25:33.415464 <6>[ 0.451334] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1390 04:25:33.426354 <6>[ 0.457816] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1391 04:25:33.431950 <6>[ 0.464793] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1392 04:25:33.437406 <6>[ 0.471262] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1393 04:25:33.442943 <6>[ 0.478248] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1394 04:25:33.448436 <6>[ 0.484717] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1395 04:25:33.459557 <6>[ 0.491702] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1396 04:25:33.460135 <6>[ 0.499703] ACPI: Interpreter disabled.
1397 04:25:33.465155 <6>[ 0.505133] iommu: Default domain type: Translated
1398 04:25:33.470572 <6>[ 0.507235] iommu: DMA domain TLB invalidation policy: strict mode
1399 04:25:33.476101 <5>[ 0.513921] SCSI subsystem initialized
1400 04:25:33.481659 <6>[ 0.517842] usbcore: registered new interface driver usbfs
1401 04:25:33.487123 <6>[ 0.523292] usbcore: registered new interface driver hub
1402 04:25:33.492577 <6>[ 0.528811] usbcore: registered new device driver usb
1403 04:25:33.498323 <6>[ 0.535085] pps_core: LinuxPPS API ver. 1 registered
1404 04:25:33.511059 <6>[ 0.539229] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1405 04:25:33.511710 <6>[ 0.548549] PTP clock support registered
1406 04:25:33.514688 <6>[ 0.552789] EDAC MC: Ver: 3.0.0
1407 04:25:33.520567 <6>[ 0.556442] scmi_core: SCMI protocol bus registered
1408 04:25:33.525779 <6>[ 0.562099] FPGA manager framework
1409 04:25:33.531307 <6>[ 0.564813] Advanced Linux Sound Architecture Driver Initialized.
1410 04:25:33.531859 <6>[ 0.571747] vgaarb: loaded
1411 04:25:33.536866 <6>[ 0.574314] clocksource: Switched to clocksource arch_sys_counter
1412 04:25:33.543131 <5>[ 0.580465] VFS: Disk quotas dquot_6.6.0
1413 04:25:33.547892 <6>[ 0.584445] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1414 04:25:33.553495 <6>[ 0.591651] pnp: PnP ACPI: disabled
1415 04:25:33.559301 <6>[ 0.600080] NET: Registered PF_INET protocol family
1416 04:25:33.564350 <6>[ 0.600471] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1417 04:25:33.575382 <6>[ 0.610649] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1418 04:25:33.580944 <6>[ 0.616645] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1419 04:25:33.592032 <6>[ 0.624541] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1420 04:25:33.597525 <6>[ 0.632778] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1421 04:25:33.608581 <6>[ 0.640578] TCP: Hash tables configured (established 32768 bind 32768)
1422 04:25:33.614135 <6>[ 0.647048] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1423 04:25:33.619577 <6>[ 0.653896] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1424 04:25:33.625068 <6>[ 0.661323] NET: Registered PF_UNIX/PF_LOCAL protocol family
1425 04:25:33.630674 <6>[ 0.667421] RPC: Registered named UNIX socket transport module.
1426 04:25:33.636155 <6>[ 0.673183] RPC: Registered udp transport module.
1427 04:25:33.641645 <6>[ 0.678092] RPC: Registered tcp transport module.
1428 04:25:33.647086 <6>[ 0.683006] RPC: Registered tcp-with-tls transport module.
1429 04:25:33.652621 <6>[ 0.688699] RPC: Registered tcp NFSv4.1 backchannel transport module.
1430 04:25:33.658144 <6>[ 0.695347] PCI: CLS 0 bytes, default 64
1431 04:25:33.663654 <6>[ 0.699661] Unpacking initramfs...
1432 04:25:33.669193 <6>[ 0.705710] kvm [1]: nv: 554 coarse grained trap handlers
1433 04:25:33.674679 <6>[ 0.709014] kvm [1]: IPA Size Limit: 40 bits
1434 04:25:33.674973 <6>[ 0.714664] kvm [1]: vgic interrupt IRQ9
1435 04:25:33.680200 <6>[ 0.717356] kvm [1]: Hyp nVHE mode initialized successfully
1436 04:25:33.685734 <5>[ 0.724362] Initialise system trusted keyrings
1437 04:25:33.691262 <6>[ 0.728155] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1438 04:25:33.696775 <6>[ 0.734685] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1439 04:25:33.702285 <5>[ 0.740734] NFS: Registering the id_resolver key type
1440 04:25:33.707824 <5>[ 0.745742] Key type id_resolver registered
1441 04:25:33.713348 <5>[ 0.750112] Key type id_legacy registered
1442 04:25:33.718909 <6>[ 0.754367] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1443 04:25:33.729910 <6>[ 0.761237] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1444 04:25:33.733737 <6>[ 0.769015] 9p: Installing v9fs 9p2000 file system support
1445 04:25:33.771879 <5>[ 0.815672] Key type asymmetric registered
1446 04:25:33.777294 <5>[ 0.815718] Asymmetric key parser 'x509' registered
1447 04:25:33.788332 <6>[ 0.819571] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1448 04:25:33.788656 <6>[ 0.827095] io scheduler mq-deadline registered
1449 04:25:33.793931 <6>[ 0.831834] io scheduler kyber registered
1450 04:25:33.799363 <6>[ 0.836100] io scheduler bfq registered
1451 04:25:33.805822 <6>[ 0.841983] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1452 04:25:33.822062 <6>[ 0.862224] ledtrig-cpu: registered to indicate activity on CPUs
1453 04:25:33.854400 <6>[ 0.893326] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1454 04:25:33.874110 <6>[ 0.906835] Serial: 8250/16550 driver, 4 port�<6>[ 0.911397] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1455 04:25:33.879656 <6>[ 0.921025] printk: legacy console [ttyAML0] enabled
1456 04:25:33.885188 <6>[ 0.921025] printk: legacy console [ttyAML0] enabled
1457 04:25:33.890744 <6>[ 0.925830] printk: legacy bootconsole [meson0] disabled
1458 04:25:33.896305 <6>[ 0.925830] printk: legacy bootconsole [meson0] disabled
1459 04:25:33.901937 <6>[ 0.939099] msm_serial: driver initialized
1460 04:25:33.907406 <6>[ 0.941754] SuperH (H)SCI(F) driver initialized
1461 04:25:33.907702 <6>[ 0.946297] STM32 USART driver initialized
1462 04:25:33.912977 <5>[ 0.952456] random: crng init done
1463 04:25:33.920077 <6>[ 0.958128] loop: module loaded
1464 04:25:33.920389 <6>[ 0.959445] megasas: 07.727.03.00-rc1
1465 04:25:33.925599 <6>[ 0.968428] tun: Universal TUN/TAP device driver, 1.6
1466 04:25:33.931151 <6>[ 0.969621] thunder_xcv, ver 1.0
1467 04:25:33.936703 <6>[ 0.971620] thunder_bgx, ver 1.0
1468 04:25:33.937008 <6>[ 0.975068] nicpf, ver 1.0
1469 04:25:33.942259 <6>[ 0.979678] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1470 04:25:33.947787 <6>[ 0.985455] hns3: Copyright (c) 2017 Huawei Corporation.
1471 04:25:33.953332 <6>[ 0.991046] hclge is initializing
1472 04:25:33.958956 <6>[ 0.994584] e1000: Intel(R) PRO/1000 Network Driver
1473 04:25:33.964417 <6>[ 0.999665] e1000: Copyright (c) 1999-2006 Intel Corporation.
1474 04:25:33.969975 <6>[ 1.005684] e1000e: Intel(R) PRO/1000 Network Driver
1475 04:25:33.975480 <6>[ 1.010844] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1476 04:25:33.981046 <6>[ 1.017026] igb: Intel(R) Gigabit Ethernet Network Driver
1477 04:25:33.986590 <6>[ 1.022628] igb: Copyright (c) 2007-2014 Intel Corporation.
1478 04:25:33.992153 <6>[ 1.028468] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1479 04:25:33.997670 <6>[ 1.034937] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1480 04:25:34.003245 <6>[ 1.041707] sky2: driver version 1.30
1481 04:25:34.008796 <6>[ 1.046839] VFIO - User Level meta-driver version: 0.3
1482 04:25:34.014331 <6>[ 1.054233] usbcore: registered new interface driver usb-storage
1483 04:25:34.020396 <6>[ 1.060351] i2c_dev: i2c /dev entries driver
1484 04:25:34.033192 <6>[ 1.071500] sdhci: Secure Digital Host Controller Interface driver
1485 04:25:34.033555 <6>[ 1.072301] sdhci: Copyright(c) Pierre Ossman
1486 04:25:34.044252 <6>[ 1.078011] Synopsys Designware Multimedia Card Interface Driver
1487 04:25:34.049792 <6>[ 1.084537] sdhci-pltfm: SDHCI platform and OF driver helper
1488 04:25:34.050092 <6>[ 1.092227] meson-sm: secure-monitor enabled
1489 04:25:34.062713 <6>[ 1.094726] usbcore: registered new interface driver usbhid
1490 04:25:34.063056 <6>[ 1.099351] usbhid: USB HID core driver
1491 04:25:34.070277 <6>[ 1.114146] NET: Registered PF_PACKET protocol family
1492 04:25:34.075787 <6>[ 1.114235] 9pnet: Installing 9P2000 support
1493 04:25:34.082839 <5>[ 1.118397] Key type dns_resolver registered
1494 04:25:34.088427 <6>[ 1.129929] registered taskstats version 1
1495 04:25:34.093932 <5>[ 1.130089] Loading compiled-in X.509 certificates
1496 04:25:34.097492 <6>[ 1.138738] Demotion targets for Node 0: null
1497 04:25:34.137634 <6>[ 1.181400] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1498 04:25:34.143102 <6>[ 1.181444] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1499 04:25:34.152086 <4>[ 1.191609] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1500 04:25:34.157630 <4>[ 1.194190] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1501 04:25:34.168729 <6>[ 1.201809] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1502 04:25:34.172245 <6>[ 1.211082] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1503 04:25:34.183278 <6>[ 1.214480] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1504 04:25:34.188846 <6>[ 1.222475] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1505 04:25:34.197847 <6>[ 1.232001] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1506 04:25:34.203376 <6>[ 1.238229] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1507 04:25:34.208969 <6>[ 1.243850] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1508 04:25:34.220082 <6>[ 1.251741] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1509 04:25:34.220422 <6>[ 1.259013] hub 1-0:1.0: USB hub found
1510 04:25:34.225655 <6>[ 1.262498] hub 1-0:1.0: 2 ports detected
1511 04:25:34.236658 <6>[ 1.268529] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1512 04:25:34.237010 <6>[ 1.275469] hub 2-0:1.0: USB hub found
1513 04:25:34.242388 <6>[ 1.279050] hub 2-0:1.0: 1 port detected
1514 04:25:34.268740 <6>[ 1.309898] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1515 04:25:34.280648 <6>[ 1.321137] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1516 04:25:34.312983 <6>[ 1.353160] Trying to probe devices needed for running init ...
1517 04:25:34.478933 <6>[ 1.518351] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1518 04:25:34.616108 <6>[ 1.659693] Freeing initrd memory: 22880K
1519 04:25:34.621460 <6>[ 1.661685] mmc0: new ultra high speed SDR104 SDXC card at address e624
1520 04:25:34.627021 <6>[ 1.666125] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1521 04:25:34.630859 <6>[ 1.672120] mmcblk0: p1
1522 04:25:34.663151 <6>[ 1.706820] hub 1-1:1.0: USB hub found
1523 04:25:34.668856 <6>[ 1.707145] hub 1-1:1.0: 4 ports detected
1524 04:25:34.734937 <6>[ 1.774449] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1525 04:25:34.775752 <6>[ 1.819479] hub 2-1:1.0: USB hub found
1526 04:25:34.781432 <6>[ 1.820308] hub 2-1:1.0: 4 ports detected
1527 04:25:46.602922 <6>[ 13.646376] clk: Disabling unused clocks
1528 04:25:46.608193 <6>[ 13.646544] PM: genpd: Disabling unused power domains
1529 04:25:46.616654 <6>[ 13.650232] ALSA device list:
1530 04:25:46.617170 <6>[ 13.653429] No soundcards found.
1531 04:25:46.622219 <6>[ 13.665597] Freeing unused kernel memory: 10432K
1532 04:25:46.628188 <6>[ 13.665705] Run /init as init process
1533 04:25:46.634289 Loading, please wait...
1534 04:25:46.670800 Starting systemd-udevd version 252.22-1~deb12u1
1535 04:25:47.157269 <6>[ 14.198627] mc: Linux media interface: v0.10
1536 04:25:47.175235 <6>[ 14.213442] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1537 04:25:47.180718 <6>[ 14.214822] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1538 04:25:47.186345 <6>[ 14.222793] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1539 04:25:47.191874 <6>[ 14.227388] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1540 04:25:47.197419 <6>[ 14.237094] meson-vrtc ff8000a8.rtc: registered as rtc0
1541 04:25:47.208607 <6>[ 14.239974] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1542 04:25:47.213934 <6>[ 14.247895] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1543 04:25:47.219477 <6>[ 14.254765] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1544 04:25:47.225039 <6>[ 14.260204] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1545 04:25:47.236149 <6>[ 14.267905] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1546 04:25:47.241680 <6>[ 14.272664] videodev: Linux video capture interface: v2.00
1547 04:25:47.247224 <6>[ 14.275616] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1548 04:25:47.252842 <6>[ 14.275621] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1549 04:25:47.258824 <6>[ 14.294097] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1550 04:25:47.270249 <4>[ 14.306817] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1551 04:25:47.275842 <6>[ 14.315608] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1552 04:25:47.281332 <6>[ 14.316156] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1553 04:25:47.289811 <6>[ 14.322281] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1554 04:25:47.301354 <6>[ 14.341813] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1555 04:25:47.313320 <3>[ 14.351726] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1556 04:25:47.329332 <6>[ 14.373171] Registered IR keymap rc-empty
1557 04:25:47.340424 <6>[ 14.374433] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1558 04:25:47.351508 <6>[ 14.378488] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1559 04:25:47.357056 <6>[ 14.390946] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1560 04:25:47.368182 <4>[ 14.400258] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1561 04:25:47.373771 <6>[ 14.402677] panfrost ffe40000.gpu: clock rate = 24000000
1562 04:25:47.379362 <6>[ 14.405175] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1563 04:25:47.390383 <6>[ 14.405888] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1564 04:25:47.395969 <3>[ 14.406008] meson-drm ff900000.vpu: DSI transceiver device is disabled
1565 04:25:47.401520 <6>[ 14.406631] rc rc0: sw decoder init
1566 04:25:47.407055 <6>[ 14.406674] meson-ir ff808000.ir: receiver initialized
1567 04:25:47.412630 <6>[ 14.409107] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 0
1568 04:25:47.423667 <3>[ 14.413611] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1569 04:25:47.429267 <6>[ 14.428156] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1570 04:25:47.434791 <6>[ 14.445082] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1571 04:25:47.440347 <6>[ 14.447573] usbcore: registered new device driver onboard-usb-dev
1572 04:25:47.451419 <6>[ 14.453834] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1573 04:25:47.463413 <6>[ 14.453847] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1574 04:25:47.643792 <6>[ 14.504077] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1575 04:25:47.649401 <6>[ 14.510559] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 1
1576 04:25:47.654972 <6>[ 14.663124] Console: switching to colour frame buffer device 128x48
1577 04:25:47.660498 <6>[ 14.696480] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1578 04:25:47.674095 <6>[ 14.698628] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1579 04:25:47.911034 <6>[ 14.954825] hub 1-1:1.0: USB hub found
1580 04:25:47.916755 <6>[ 14.955124] hub 1-1:1.0: 4 ports detected
1581 04:25:48.060058 <4>[ 15.098347] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1582 04:25:48.065626 <3>[ 15.100740] onboard-usb-dev 1-1: Failed to suspend device, error -32
1583 04:25:48.072594 <3>[ 15.107158] onboard-usb-dev 1-1: can't set config #1, error -71
1584 04:25:48.088079 <4>[ 15.126369] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1585 04:25:48.093635 <6>[ 15.128700] onboard-usb-dev 1-1: USB disconnect, device number 2
1586 04:25:48.100689 <3>[ 15.134875] onboard-usb-dev 1-1: Failed to suspend device, error -32
1587 04:25:48.219391 <6>[ 15.258784] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1588 04:25:48.354794 <6>[ 15.394376] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1589 04:25:48.551227 <6>[ 15.594902] hub 1-1:1.0: USB hub found
1590 04:25:48.556860 <6>[ 15.595259] hub 1-1:1.0: 4 ports detected
1591 04:25:48.563973 Begin: Loading essential drivers ... done.
1592 04:25:48.569513 Begin: Running /scripts/init-premount ... done.
1593 04:25:48.575116 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1594 04:25:48.588928 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1595 04:25:48.589468 Device /sys/class/net/end0 found
1596 04:25:48.589899 done.
1597 04:25:48.598830 Begin: Waiting up to 180 secs for any network device to become available ... done.
1598 04:25:48.653665 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.687580] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1599 04:25:48.654188
1600 04:25:48.742824 <6>[ 15.778431] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=27)
1601 04:25:48.756081 <6>[ 15.794322] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1602 04:25:48.761662 <6>[ 15.796512] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1603 04:25:48.770929 <6>[ 15.803884] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1604 04:25:50.030634 <4>[ 17.074323] rc rc0: two consecutive events of type space
1605 04:25:50.698191 IP-Config: no response after 2 secs - giving up
1606 04:25:50.737713 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1607 04:25:51.724499 <6>[ 18.762157] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1608 04:25:52.948787 IP-Config: end0 guessed broadcast address 192.168.6.255
1609 04:25:52.954165 IP-Config: end0 complete (dhcp from 192.168.6.1):
1610 04:25:52.959642 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1611 04:25:52.968736 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1612 04:25:52.974258 rootserver: 192.168.6.1 rootpath:
1613 04:25:52.974752 filename :
1614 04:25:53.110454 done.
1615 04:25:53.120455 Begin: Running /scripts/nfs-bottom ... done.
1616 04:25:53.131814 Begin: Running /scripts/init-bottom ... done.
1617 04:25:53.480545 <30>[ 20.519736] systemd[1]: System time before build time, advancing clock.
1618 04:25:53.541941 <6>[ 20.585449] NET: Registered PF_INET6 protocol family
1619 04:25:53.547331 <6>[ 20.586274] Segment Routing with IPv6
1620 04:25:53.552582 <6>[ 20.588981] In-situ OAM (IOAM) with IPv6
1621 04:25:53.629382 <30>[ 20.645397] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1622 04:25:53.634914 <30>[ 20.672818] systemd[1]: Detected architecture arm64.
1623 04:25:53.635401
1624 04:25:53.642402 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1625 04:25:53.642878
1626 04:25:53.652113 <30>[ 20.692026] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1627 04:25:54.341216 <30>[ 21.379916] systemd[1]: Queued start job for default target graphical.target.
1628 04:25:54.378495 <30>[ 21.416659] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1629 04:25:54.386260 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1630 04:25:54.397082 <30>[ 21.435316] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1631 04:25:54.405566 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1632 04:25:54.417265 <30>[ 21.455333] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1633 04:25:54.426134 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1634 04:25:54.437164 <30>[ 21.475061] systemd[1]: Created slice user.slice - User and Session Slice.
1635 04:25:54.443850 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1636 04:25:54.457461 <30>[ 21.490589] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1637 04:25:54.463475 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1638 04:25:54.472121 <30>[ 21.510521] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1639 04:25:54.484243 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1640 04:25:54.500784 <30>[ 21.530495] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1641 04:25:54.511901 <30>[ 21.544561] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1642 04:25:54.519626 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1643 04:25:54.525135 <30>[ 21.566407] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1644 04:25:54.536374 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1645 04:25:54.552230 <30>[ 21.590435] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1646 04:25:54.565912 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1647 04:25:54.571539 <30>[ 21.610458] systemd[1]: Reached target paths.target - Path Units.
1648 04:25:54.580015 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1649 04:25:54.585498 <30>[ 21.626423] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1650 04:25:54.597153 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1651 04:25:54.602766 <30>[ 21.642405] systemd[1]: Reached target slices.target - Slice Units.
1652 04:25:54.611000 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1653 04:25:54.616452 <30>[ 21.658434] systemd[1]: Reached target swap.target - Swaps.
1654 04:25:54.624327 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1655 04:25:54.636226 <30>[ 21.674432] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1656 04:25:54.645089 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1657 04:25:54.660357 <30>[ 21.698606] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1658 04:25:54.669614 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1659 04:25:54.682292 <30>[ 21.720535] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1660 04:25:54.691320 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1661 04:25:54.702373 <30>[ 21.739404] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1662 04:25:54.710000 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1663 04:25:54.720947 <30>[ 21.758755] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1664 04:25:54.727970 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1665 04:25:54.738970 <30>[ 21.775455] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1666 04:25:54.746439 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1667 04:25:54.758160 <30>[ 21.796411] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1668 04:25:54.763811 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1669 04:25:54.776429 <30>[ 21.814639] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1670 04:25:54.784944 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1671 04:25:54.816277 <30>[ 21.854506] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1672 04:25:54.823058 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1673 04:25:54.834883 <30>[ 21.873035] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1674 04:25:54.842397 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1675 04:25:54.854577 <30>[ 21.892779] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1676 04:25:54.862602 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1677 04:25:54.880231 <30>[ 21.910632] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1678 04:25:54.885813 <30>[ 21.923026] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1679 04:25:54.896109 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1680 04:25:54.915115 <30>[ 21.953243] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1681 04:25:54.923096 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1682 04:25:54.935080 <30>[ 21.973303] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1683 04:25:54.942746 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1684 04:25:54.954700 <30>[ 21.992967] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1685 04:25:54.965799 <6>[ 21.997295] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1686 04:25:54.970778 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1687 04:25:54.983037 <30>[ 22.021287] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1688 04:25:54.991404 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1689 04:25:55.002783 <30>[ 22.041041] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1690 04:25:55.010126 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1691 04:25:55.019475 <6>[ 22.063210] fuse: init (API version 7.41)
1692 04:25:55.030506 <30>[ 22.064970] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1693 04:25:55.034526 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1694 04:25:55.052941 <30>[ 22.091198] systemd[1]: Starting systemd-journald.service - Journal Service...
1695 04:25:55.059388 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1696 04:25:55.075335 <30>[ 22.113533] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1697 04:25:55.082855 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1698 04:25:55.094208 <30>[ 22.132387] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1699 04:25:55.103495 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1700 04:25:55.123950 <30>[ 22.162136] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1701 04:25:55.132837 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1702 04:25:55.148763 <30>[ 22.186679] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1703 04:25:55.156720 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1704 04:25:55.171634 <30>[ 22.209890] systemd[1]: Started systemd-journald.service - Journal Service.
1705 04:25:55.178334 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1706 04:25:55.192973 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1707 04:25:55.199885 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1708 04:25:55.216728 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1709 04:25:55.233079 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1710 04:25:55.249497 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1711 04:25:55.261456 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1712 04:25:55.273046 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1713 04:25:55.289311 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1714 04:25:55.305194 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1715 04:25:55.321280 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1716 04:25:55.333076 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1717 04:25:55.349028 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1718 04:25:55.365289 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1719 04:25:55.381488 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1720 04:25:55.418823 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1721 04:25:55.425259 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1722 04:25:55.437508 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1723 04:25:55.449893 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1724 04:25:55.468531 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1725 04:25:55.474880 <46>[ 22.514020] systemd-journald[232]: Received client request to flush runtime journal.
1726 04:25:55.491017 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1727 04:25:55.510828 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1728 04:25:55.529069 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1729 04:25:55.545098 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1730 04:25:55.565212 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1731 04:25:55.606621 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1732 04:25:55.667415 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1733 04:25:55.708145 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1734 04:25:55.746203 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1735 04:25:55.788293 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1736 04:25:55.796671 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1737 04:25:55.811809 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1738 04:25:55.879869 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1739 04:25:55.894338 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1740 04:25:56.124879 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1741 04:25:56.142489 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1742 04:25:56.191879 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1743 04:25:56.211258 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1744 04:25:56.217829 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1745 04:25:56.281493 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1746 04:25:56.293182 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1747 04:25:56.350839 <5>[ 23.389244] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1748 04:25:56.388460 <5>[ 23.426710] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1749 04:25:56.393978 <5>[ 23.427397] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1750 04:25:56.399548 <4>[ 23.435669] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1751 04:25:56.405091 [<6>[ 23.444094] cfg80211: failed to load regulatory.db
1752 04:25:56.417833 [0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1753 04:25:56.425296 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1754 04:25:56.436989 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1755 04:25:56.452650 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1756 04:25:56.473264 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1757 04:25:56.487348 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1758 04:25:56.498612 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1759 04:25:56.512607 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1760 04:25:56.532377 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1761 04:25:56.551439 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1762 04:25:56.564499 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1763 04:25:56.576267 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1764 04:25:56.592916 <46>[ 23.619178] systemd-journald[232]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1765 04:25:56.608251 <46>[ 23.634069] systemd-journald[232]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1766 04:25:56.619213 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1767 04:25:56.743365 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1768 04:25:56.815997 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1769 04:25:56.877102 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1770 04:25:56.889625 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1771 04:25:56.930465 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1772 04:25:56.941461 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1773 04:25:56.954845 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1774 04:25:56.968178 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1775 04:25:56.975626 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1776 04:25:57.031964 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1777 04:25:57.044721 Starting [0;1;39mdpkg-db-backup.se…ly dpkg database backup service...
1778 04:25:57.060673 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1779 04:25:57.077631 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1780 04:25:57.084738 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1781 04:25:57.095800 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1782 04:25:57.108474 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1783 04:25:57.148012 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1784 04:25:57.160604 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1785 04:25:57.167117 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1786 04:25:57.176299 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1787 04:25:57.196431 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1788 04:25:57.248503 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1789 04:25:57.310703 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1790 04:25:57.869003 [[0;32m OK [0m] Finished [0;1;39mdpkg-db-backup.se…aily dpkg database backup service.
1791 04:25:57.965816
1792 04:25:57.966330 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1793 04:25:57.966755
1794 04:25:57.973007 debian-bookworm-arm64 login: root (automatic login)
1795 04:25:57.973474
1796 04:25:58.114375 Linux debian-bookworm-arm64 6.12.0-rc6 #1 SMP PREEMPT Thu Nov 7 00:22:50 UTC 2024 aarch64
1797 04:25:58.115001
1798 04:25:58.119727 The programs included with the Debian GNU/Linux system are free software;
1799 04:25:58.128817 the exact distribution terms for each program are described in the
1800 04:25:58.129443 individual files in /usr/share/doc/*/copyright.
1801 04:25:58.129897
1802 04:25:58.134306 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1803 04:25:58.139523 permitted by applicable law.
1804 04:25:58.918872 Matched prompt #10: / #
1806 04:25:58.920482 Setting prompt string to ['/ #']
1807 04:25:58.921055 end: 2.4.4.1 login-action (duration 00:00:26) [common]
1809 04:25:58.922450 end: 2.4.4 auto-login-action (duration 00:00:26) [common]
1810 04:25:58.922996 start: 2.4.5 expect-shell-connection (timeout 00:03:10) [common]
1811 04:25:58.923448 Setting prompt string to ['/ #']
1812 04:25:58.923868 Forcing a shell prompt, looking for ['/ #']
1814 04:25:58.974858 / #
1815 04:25:58.975739 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1816 04:25:58.976282 Waiting using forced prompt support (timeout 00:02:30)
1817 04:25:58.980982
1818 04:25:58.981796 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1819 04:25:58.982354 start: 2.4.6 export-device-env (timeout 00:03:10) [common]
1820 04:25:58.982839 Sending with 10 millisecond of delay
1822 04:26:03.969868 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/950796/extract-nfsrootfs-7h5f4j8z'
1823 04:26:03.980846 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/950796/extract-nfsrootfs-7h5f4j8z'
1824 04:26:03.981634 Sending with 10 millisecond of delay
1826 04:26:06.080105 / # export NFS_SERVER_IP='192.168.6.2'
1827 04:26:06.091037 export NFS_SERVER_IP='192.168.6.2'
1828 04:26:06.091911 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1829 04:26:06.092553 end: 2.4 uboot-commands (duration 00:01:57) [common]
1830 04:26:06.093116 end: 2 uboot-action (duration 00:01:57) [common]
1831 04:26:06.093672 start: 3 lava-test-retry (timeout 00:06:44) [common]
1832 04:26:06.094239 start: 3.1 lava-test-shell (timeout 00:06:44) [common]
1833 04:26:06.094700 Using namespace: common
1835 04:26:06.195834 / # #
1836 04:26:06.196702 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1837 04:26:06.201625 #
1838 04:26:06.202376 Using /lava-950796
1840 04:26:06.303468 / # export SHELL=/bin/bash
1841 04:26:06.309434 export SHELL=/bin/bash
1843 04:26:06.410832 / # . /lava-950796/environment
1844 04:26:06.415020 . /lava-950796/environment
1846 04:26:06.520651 / # /lava-950796/bin/lava-test-runner /lava-950796/0
1847 04:26:06.521292 Test shell timeout: 10s (minimum of the action and connection timeout)
1848 04:26:06.525570 /lava-950796/bin/lava-test-runner /lava-950796/0
1849 04:26:06.698206 + export TESTRUN_ID=0_timesync-off
1850 04:26:06.706019 + TESTRUN_ID=0_timesync-off
1851 04:26:06.706495 + cd /lava-950796/0/tests/0_timesync-off
1852 04:26:06.706748 ++ cat uuid
1853 04:26:06.712655 + UUID=950796_1.6.2.4.1
1854 04:26:06.712988 + set +x
1855 04:26:06.721223 <LAVA_SIGNAL_STARTRUN 0_timesync-off 950796_1.6.2.4.1>
1856 04:26:06.721566 + systemctl stop systemd-timesyncd
1857 04:26:06.722049 Received signal: <STARTRUN> 0_timesync-off 950796_1.6.2.4.1
1858 04:26:06.722305 Starting test lava.0_timesync-off (950796_1.6.2.4.1)
1859 04:26:06.722620 Skipping test definition patterns.
1860 04:26:06.778316 + set +x
1861 04:26:06.778897 <LAVA_SIGNAL_ENDRUN 0_timesync-off 950796_1.6.2.4.1>
1862 04:26:06.779595 Received signal: <ENDRUN> 0_timesync-off 950796_1.6.2.4.1
1863 04:26:06.780118 Ending use of test pattern.
1864 04:26:06.780529 Ending test lava.0_timesync-off (950796_1.6.2.4.1), duration 0.06
1866 04:26:06.862718 + export TESTRUN_ID=1_kselftest-alsa
1867 04:26:06.871022 + TESTRUN_ID=1_kselftest-alsa
1868 04:26:06.871478 + cd /lava-950796/0/tests/1_kselftest-alsa
1869 04:26:06.871888 ++ cat uuid
1870 04:26:06.878661 + UUID=950796_1.6.2.4.5
1871 04:26:06.879092 + set +x
1872 04:26:06.884077 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 950796_1.6.2.4.5>
1873 04:26:06.884507 + cd ./automated/linux/kselftest/
1874 04:26:06.885167 Received signal: <STARTRUN> 1_kselftest-alsa 950796_1.6.2.4.5
1875 04:26:06.885584 Starting test lava.1_kselftest-alsa (950796_1.6.2.4.5)
1876 04:26:06.886053 Skipping test definition patterns.
1877 04:26:06.913019 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1878 04:26:06.952093 INFO: install_deps skipped
1879 04:26:07.071213 --2024-11-07 04:26:07-- http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/kselftest.tar.xz
1880 04:26:07.345614 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1881 04:26:07.486042 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1882 04:26:07.624159 HTTP request sent, awaiting response... 200 OK
1883 04:26:07.624609 Length: 6927060 (6.6M) [application/octet-stream]
1884 04:26:07.629375 Saving to: 'kselftest_armhf.tar.gz'
1885 04:26:07.629788
1886 04:26:09.029373
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 49.92K 181KB/s
kselftest_armhf.tar 3%[ ] 218.67K 396KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.05MB/s
kselftest_armhf.tar 53%[=========> ] 3.51M 3.18MB/s
kselftest_armhf.tar 97%[==================> ] 6.46M 4.64MB/s
kselftest_armhf.tar 100%[===================>] 6.61M 4.74MB/s in 1.4s
1887 04:26:09.030074
1888 04:26:09.119452 2024-11-07 04:26:09 (4.74 MB/s) - 'kselftest_armhf.tar.gz' saved [6927060/6927060]
1889 04:26:09.120115
1890 04:26:18.489500 skiplist:
1891 04:26:18.490136 ========================================
1892 04:26:18.495004 ========================================
1893 04:26:18.525852 alsa:mixer-test
1894 04:26:18.526345 alsa:pcm-test
1895 04:26:18.526766 alsa:test-pcmtest-driver
1896 04:26:18.529946 alsa:utimer-test
1897 04:26:18.541737 ============== Tests to run ===============
1898 04:26:18.542196 alsa:mixer-test
1899 04:26:18.547388 alsa:pcm-test
1900 04:26:18.547826 alsa:test-pcmtest-driver
1901 04:26:18.548328 alsa:utimer-test
1902 04:26:18.555589 ===========End Tests to run ===============
1903 04:26:18.556061 shardfile-alsa pass
1904 04:26:18.652917 <12>[ 45.694470] kselftest: Running tests in alsa
1905 04:26:18.661247 TAP version 13
1906 04:26:18.672250 1..4
1907 04:26:18.693227 # timeout set to 45
1908 04:26:18.693659 # selftests: alsa: mixer-test
1909 04:26:18.861388 # TAP version 13
1910 04:26:18.861976 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1911 04:26:18.866558 # 1..427
1912 04:26:18.866999 # ok 1 get_value.LCALTA.60
1913 04:26:18.867406 # # LCALTA.60 TDMOUT_A SRC SEL
1914 04:26:18.872064 # ok 2 name.LCALTA.60
1915 04:26:18.872498 # ok 3 write_default.LCALTA.60
1916 04:26:18.877597 # ok 4 write_valid.LCALTA.60
1917 04:26:18.878031 # ok 5 write_invalid.LCALTA.60
1918 04:26:18.883130 # ok 6 event_missing.LCALTA.60
1919 04:26:18.883556 # ok 7 event_spurious.LCALTA.60
1920 04:26:18.888771 # ok 8 get_value.LCALTA.59
1921 04:26:18.889197 # # LCALTA.59 TDMOUT_B SRC SEL
1922 04:26:18.894257 # ok 9 name.LCALTA.59
1923 04:26:18.894682 # ok 10 write_default.LCALTA.59
1924 04:26:18.899737 # ok 11 write_valid.LCALTA.59
1925 04:26:18.900189 # ok 12 write_invalid.LCALTA.59
1926 04:26:18.905401 # ok 13 event_missing.LCALTA.59
1927 04:26:18.905829 # ok 14 event_spurious.LCALTA.59
1928 04:26:18.910958 # ok 15 get_value.LCALTA.58
1929 04:26:18.911384 # # LCALTA.58 TDMOUT_C SRC SEL
1930 04:26:18.916453 # ok 16 name.LCALTA.58
1931 04:26:18.916877 # ok 17 write_default.LCALTA.58
1932 04:26:18.922016 # ok 18 write_valid.LCALTA.58
1933 04:26:18.922438 # ok 19 write_invalid.LCALTA.58
1934 04:26:18.927555 # ok 20 event_missing.LCALTA.58
1935 04:26:18.927976 # ok 21 event_spurious.LCALTA.58
1936 04:26:18.933188 # ok 22 get_value.LCALTA.57
1937 04:26:18.933617 # # LCALTA.57 TDMIN_A SRC SEL
1938 04:26:18.934022 # ok 23 name.LCALTA.57
1939 04:26:18.938680 # ok 24 write_default.LCALTA.57
1940 04:26:18.939109 # ok 25 write_valid.LCALTA.57
1941 04:26:18.944235 # ok 26 write_invalid.LCALTA.57
1942 04:26:18.944656 # ok 27 event_missing.LCALTA.57
1943 04:26:18.949629 # ok 28 event_spurious.LCALTA.57
1944 04:26:18.950051 # ok 29 get_value.LCALTA.56
1945 04:26:18.955243 # # LCALTA.56 TDMIN_B SRC SEL
1946 04:26:18.955669 # ok 30 name.LCALTA.56
1947 04:26:18.960708 # ok 31 write_default.LCALTA.56
1948 04:26:18.961135 # ok 32 write_valid.LCALTA.56
1949 04:26:18.977446 # ok 33 write_<3>[ 46.007158] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1950 04:26:18.977885 invalid.LCALTA.56
1951 04:26:18.978286 # ok 34 event_missing.LCALTA.56
1952 04:26:18.982950 # ok 35 event_spurious.LCALTA.56
1953 04:26:18.983374 # ok 36 get_value.LCALTA.55
1954 04:26:18.988465 # # LCALTA.55 TDMIN_C SRC SEL
1955 04:26:18.988894 # ok 37 name.LCALTA.55
1956 04:26:18.994002 # ok 38 write_default.LCALTA.55
1957 04:26:18.994427 # ok 39 write_valid.LCALTA.55
1958 04:26:18.999556 # ok 40 write_invalid.LCALTA.55
1959 04:26:18.999976 # ok 41 event_missing.LCALTA.55
1960 04:26:19.005166 # ok 42 event_spurious.LCALTA.55
1961 04:26:19.005589 # ok 43 get_value.LCALTA.54
1962 04:26:19.010625 # # LCALTA.54 ACODEC Left DAC Sel
1963 04:26:19.011051 # ok 44 name.LCALTA.54
1964 04:26:19.016210 # ok 45 write_default.LCALTA.54
1965 04:26:19.016631 # ok 46 write_valid.LCALTA.54
1966 04:26:19.021738 # ok 47 write_invalid.LCALTA.54
1967 04:26:19.022160 # ok 48 event_missing.LCALTA.54
1968 04:26:19.027333 # ok 49 event_spurious.LCALTA.54
1969 04:26:19.027832 # ok 50 get_value.LCALTA.53
1970 04:26:19.032937 # # LCALTA.53 ACODEC Right DAC Sel
1971 04:26:19.033438 # ok 51 name.LCALTA.53
1972 04:26:19.038423 # ok 52 write_default.LCALTA.53
1973 04:26:19.038901 # ok 53 write_valid.LCALTA.53
1974 04:26:19.043926 # ok 54 write_invalid.LCALTA.53
1975 04:26:19.044386 # ok 55 event_missing.LCALTA.53
1976 04:26:19.049462 # ok 56 event_spurious.LCALTA.53
1977 04:26:19.049887 # ok 57 get_value.LCALTA.52
1978 04:26:19.055069 # # LCALTA.52 TOACODEC OUT EN Switch
1979 04:26:19.055498 # ok 58 name.LCALTA.52
1980 04:26:19.060568 # ok 59 write_default.LCALTA.52
1981 04:26:19.060994 # ok 60 write_valid.LCALTA.52
1982 04:26:19.066172 # ok 61 write_invalid.LCALTA.52
1983 04:26:19.066604 # ok 62 event_missing.LCALTA.52
1984 04:26:19.071669 # ok 63 event_spurious.LCALTA.52
1985 04:26:19.072132 # ok 64 get_value.LCALTA.51
1986 04:26:19.077222 # # LCALTA.51 TOACODEC SRC
1987 04:26:19.077649 # ok 65 name.LCALTA.51
1988 04:26:19.082761 # ok 66 write_default.LCALTA.51
1989 04:26:19.083187 # ok 67 write_valid.LCALTA.51
1990 04:26:19.088292 # ok 68 write_invalid.LCALTA.51
1991 04:26:19.088712 # ok 69 event_missing.LCALTA.51
1992 04:26:19.093850 # ok 70 event_spurious.LCALTA.51
1993 04:26:19.094275 # ok 71 get_value.LCALTA.50
1994 04:26:19.099396 # # LCALTA.50 TOHDMITX SPDIF SRC
1995 04:26:19.099823 # ok 72 name.LCALTA.50
1996 04:26:19.100258 # ok 73 write_default.LCALTA.50
1997 04:26:19.104940 # ok 74 write_valid.LCALTA.50
1998 04:26:19.105361 # ok 75 write_invalid.LCALTA.50
1999 04:26:19.110499 # ok 76 event_missing.LCALTA.50
2000 04:26:19.116067 # ok 77 event_spurious.LCALTA.50
2001 04:26:19.116493 # ok 78 get_value.LCALTA.49
2002 04:26:19.116897 # # LCALTA.49 TOHDMITX Switch
2003 04:26:19.121567 # ok 79 name.LCALTA.49
2004 04:26:19.121986 # ok 80 write_default.LCALTA.49
2005 04:26:19.127181 # ok 81 write_valid.LCALTA.49
2006 04:26:19.127607 # ok 82 write_invalid.LCALTA.49
2007 04:26:19.132713 # ok 83 event_missing.LCALTA.49
2008 04:26:19.133138 # ok 84 event_spurious.LCALTA.49
2009 04:26:19.138249 # ok 85 get_value.LCALTA.48
2010 04:26:19.138718 # # LCALTA.48 TOHDMITX I2S SRC
2011 04:26:19.143767 # ok 86 name.LCALTA.48
2012 04:26:19.144253 # ok 87 write_default.LCALTA.48
2013 04:26:19.149298 # ok 88 write_valid.LCALTA.48
2014 04:26:19.149712 # ok 89 write_invalid.LCALTA.48
2015 04:26:19.154882 # ok 90 event_missing.LCALTA.48
2016 04:26:19.155292 # ok 91 event_spurious.LCALTA.48
2017 04:26:19.160388 # ok 92 get_value.LCALTA.47
2018 04:26:19.160802 # # LCALTA.47 TODDR_C SRC SEL
2019 04:26:19.165940 # ok 93 name.LCALTA.47
2020 04:26:19.166350 # ok 94 write_default.LCALTA.47
2021 04:26:19.171474 # ok 95 write_valid.LCALTA.47
2022 04:26:19.171882 # ok 96 write_invalid.LCALTA.47
2023 04:26:19.177038 # ok 97 event_missing.LCALTA.47
2024 04:26:19.177447 # ok 98 event_spurious.LCALTA.47
2025 04:26:19.182576 # ok 99 get_value.LCALTA.46
2026 04:26:19.182981 # # LCALTA.46 TODDR_B SRC SEL
2027 04:26:19.183366 # ok 100 name.LCALTA.46
2028 04:26:19.188220 # ok 101 write_default.LCALTA.46
2029 04:26:19.193707 # ok 102 write_valid.LCALTA.46
2030 04:26:19.194112 # ok 103 write_invalid.LCALTA.46
2031 04:26:19.199227 # ok 104 event_missing.LCALTA.46
2032 04:26:19.199633 # ok 105 event_spurious.LCALTA.46
2033 04:26:19.204775 # ok 106 get_value.LCALTA.45
2034 04:26:19.205187 # # LCALTA.45 TODDR_A SRC SEL
2035 04:26:19.205574 # ok 107 name.LCALTA.45
2036 04:26:19.210301 # ok 108 write_default.LCALTA.45
2037 04:26:19.215871 # ok 109 write_valid.LCALTA.45
2038 04:26:19.216302 # ok 110 write_invalid.LCALTA.45
2039 04:26:19.221416 # ok 111 event_missing.LCALTA.45
2040 04:26:19.221820 # ok 112 event_spurious.LCALTA.45
2041 04:26:19.226942 # ok 113 get_value.LCALTA.44
2042 04:26:19.227351 # # LCALTA.44 FRDDR_C SINK 3 SEL
2043 04:26:19.232521 # ok 114 name.LCALTA.44
2044 04:26:19.232951 # ok 115 write_default.LCALTA.44
2045 04:26:19.238079 # ok 116 write_valid.LCALTA.44
2046 04:26:19.238503 # ok 117 write_invalid.LCALTA.44
2047 04:26:19.243604 # ok 118 event_missing.LCALTA.44
2048 04:26:19.244034 # ok 119 event_spurious.LCALTA.44
2049 04:26:19.249205 # ok 120 get_value.LCALTA.43
2050 04:26:19.249633 # # LCALTA.43 FRDDR_C SINK 2 SEL
2051 04:26:19.254696 # ok 121 name.LCALTA.43
2052 04:26:19.255103 # ok 122 write_default.LCALTA.43
2053 04:26:19.260248 # ok 123 write_valid.LCALTA.43
2054 04:26:19.260652 # ok 124 write_invalid.LCALTA.43
2055 04:26:19.265808 # ok 125 event_missing.LCALTA.43
2056 04:26:19.266262 # ok 126 event_spurious.LCALTA.43
2057 04:26:19.271346 # ok 127 get_value.LCALTA.42
2058 04:26:19.271789 # # LCALTA.42 FRDDR_C SINK 1 SEL
2059 04:26:19.276863 # ok 128 name.LCALTA.42
2060 04:26:19.277286 # ok 129 write_default.LCALTA.42
2061 04:26:19.282441 # ok 130 write_valid.LCALTA.42
2062 04:26:19.282865 # ok 131 write_invalid.LCALTA.42
2063 04:26:19.288110 # ok 132 event_missing.LCALTA.42
2064 04:26:19.288739 # ok 133 event_spurious.LCALTA.42
2065 04:26:19.293645 # ok 134 get_value.LCALTA.41
2066 04:26:19.294534 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
2067 04:26:19.299206 # ok 135 name.LCALTA.41
2068 04:26:19.299848 # ok 136 write_default.LCALTA.41
2069 04:26:19.304760 # ok 137 write_valid.LCALTA.41
2070 04:26:19.305630 # ok 138 write_invalid.LCALTA.41
2071 04:26:19.310287 # ok 139 event_missing.LCALTA.41
2072 04:26:19.311038 # ok 140 event_spurious.LCALTA.41
2073 04:26:19.315809 # ok 141 get_value.LCALTA.40
2074 04:26:19.316455 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
2075 04:26:19.321327 # ok 142 name.LCALTA.40
2076 04:26:19.322109 # ok 143 write_default.LCALTA.40
2077 04:26:19.326881 # ok 144 write_valid.LCALTA.40
2078 04:26:19.327455 # ok 145 write_invalid.LCALTA.40
2079 04:26:19.332541 # ok 146 event_missing.LCALTA.40
2080 04:26:19.333078 # ok 147 event_spurious.LCALTA.40
2081 04:26:19.338097 # ok 148 get_value.LCALTA.39
2082 04:26:19.343514 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
2083 04:26:19.343879 # ok 149 name.LCALTA.39
2084 04:26:19.344370 # ok 150 write_default.LCALTA.39
2085 04:26:19.348991 # ok 151 write_valid.LCALTA.39
2086 04:26:19.349420 # ok 152 write_invalid.LCALTA.39
2087 04:26:19.354524 # ok 153 event_missing.LCALTA.39
2088 04:26:19.360095 # ok 154 event_spurious.LCALTA.39
2089 04:26:19.360517 # ok 155 get_value.LCALTA.38
2090 04:26:19.365636 # # LCALTA.38 FRDDR_B SINK 3 SEL
2091 04:26:19.366062 # ok 156 name.LCALTA.38
2092 04:26:19.366467 # ok 157 write_default.LCALTA.38
2093 04:26:19.371235 # ok 158 write_valid.LCALTA.38
2094 04:26:19.371662 # ok 159 write_invalid.LCALTA.38
2095 04:26:19.376753 # ok 160 event_missing.LCALTA.38
2096 04:26:19.382273 # ok 161 event_spurious.LCALTA.38
2097 04:26:19.382702 # ok 162 get_value.LCALTA.37
2098 04:26:19.387844 # # LCALTA.37 FRDDR_B SINK 2 SEL
2099 04:26:19.388289 # ok 163 name.LCALTA.37
2100 04:26:19.388695 # ok 164 write_default.LCALTA.37
2101 04:26:19.393370 # ok 165 write_valid.LCALTA.37
2102 04:26:19.398912 # ok 166 write_invalid.LCALTA.37
2103 04:26:19.399329 # ok 167 event_missing.LCALTA.37
2104 04:26:19.404474 # ok 168 event_spurious.LCALTA.37
2105 04:26:19.404902 # ok 169 get_value.LCALTA.36
2106 04:26:19.410000 # # LCALTA.36 FRDDR_B SINK 1 SEL
2107 04:26:19.410430 # ok 170 name.LCALTA.36
2108 04:26:19.415737 # ok 171 write_default.LCALTA.36
2109 04:26:19.416212 # ok 172 write_valid.LCALTA.36
2110 04:26:19.421181 # ok 173 write_invalid.LCALTA.36
2111 04:26:19.421610 # ok 174 event_missing.LCALTA.36
2112 04:26:19.426637 # ok 175 event_spurious.LCALTA.36
2113 04:26:19.427063 # ok 176 get_value.LCALTA.35
2114 04:26:19.432292 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
2115 04:26:19.432733 # ok 177 name.LCALTA.35
2116 04:26:19.437756 # ok 178 write_default.LCALTA.35
2117 04:26:19.438187 # ok 179 write_valid.LCALTA.35
2118 04:26:19.443280 # ok 180 write_invalid.LCALTA.35
2119 04:26:19.443737 # ok 181 event_missing.LCALTA.35
2120 04:26:19.448849 # ok 182 event_spurious.LCALTA.35
2121 04:26:19.449277 # ok 183 get_value.LCALTA.34
2122 04:26:19.454394 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
2123 04:26:19.454822 # ok 184 name.LCALTA.34
2124 04:26:19.459901 # ok 185 write_default.LCALTA.34
2125 04:26:19.460352 # ok 186 write_valid.LCALTA.34
2126 04:26:19.465488 # ok 187 write_invalid.LCALTA.34
2127 04:26:19.465916 # ok 188 event_missing.LCALTA.34
2128 04:26:19.471027 # ok 189 event_spurious.LCALTA.34
2129 04:26:19.471452 # ok 190 get_value.LCALTA.33
2130 04:26:19.476565 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
2131 04:26:19.476993 # ok 191 name.LCALTA.33
2132 04:26:19.482123 # ok 192 write_default.LCALTA.33
2133 04:26:19.482547 # ok 193 write_valid.LCALTA.33
2134 04:26:19.487668 # ok 194 write_invalid.LCALTA.33
2135 04:26:19.488123 # ok 195 event_missing.LCALTA.33
2136 04:26:19.493257 # ok 196 event_spurious.LCALTA.33
2137 04:26:19.493683 # ok 197 get_value.LCALTA.32
2138 04:26:19.498753 # # LCALTA.32 FRDDR_A SINK 3 SEL
2139 04:26:19.499181 # ok 198 name.LCALTA.32
2140 04:26:19.504296 # ok 199 write_default.LCALTA.32
2141 04:26:19.504735 # ok 200 write_valid.LCALTA.32
2142 04:26:19.509863 # ok 201 write_invalid.LCALTA.32
2143 04:26:19.510299 # ok 202 event_missing.LCALTA.32
2144 04:26:19.515379 # ok 203 event_spurious.LCALTA.32
2145 04:26:19.515812 # ok 204 get_value.LCALTA.31
2146 04:26:19.520937 # # LCALTA.31 FRDDR_A SINK 2 SEL
2147 04:26:19.521366 # ok 205 name.LCALTA.31
2148 04:26:19.526488 # ok 206 write_default.LCALTA.31
2149 04:26:19.526916 # ok 207 write_valid.LCALTA.31
2150 04:26:19.532044 # ok 208 write_invalid.LCALTA.31
2151 04:26:19.532480 # ok 209 event_missing.LCALTA.31
2152 04:26:19.537645 # ok 210 event_spurious.LCALTA.31
2153 04:26:19.538086 # ok 211 get_value.LCALTA.30
2154 04:26:19.543102 # # LCALTA.30 FRDDR_A SINK 1 SEL
2155 04:26:19.543544 # ok 212 name.LCALTA.30
2156 04:26:19.548687 # ok 213 write_default.LCALTA.30
2157 04:26:19.549151 # ok 214 write_valid.LCALTA.30
2158 04:26:19.554327 # ok 215 write_invalid.LCALTA.30
2159 04:26:19.559906 # ok 216 event_missing.LCALTA.30
2160 04:26:19.560379 # ok 217 event_spurious.LCALTA.30
2161 04:26:19.565383 # ok 218 get_value.LCALTA.29
2162 04:26:19.565835 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2163 04:26:19.570880 # ok 219 name.LCALTA.29
2164 04:26:19.571318 # ok 220 write_default.LCALTA.29
2165 04:26:19.576433 # ok 221 write_valid.LCALTA.29
2166 04:26:19.576861 # ok 222 write_invalid.LCALTA.29
2167 04:26:19.581971 # ok 223 event_missing.LCALTA.29
2168 04:26:19.582397 # ok 224 event_spurious.LCALTA.29
2169 04:26:19.587509 # ok 225 get_value.LCALTA.28
2170 04:26:19.587931 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2171 04:26:19.593051 # ok 226 name.LCALTA.28
2172 04:26:19.593477 # ok 227 write_default.LCALTA.28
2173 04:26:19.598602 # ok 228 write_valid.LCALTA.28
2174 04:26:19.599029 # ok 229 write_invalid.LCALTA.28
2175 04:26:19.604171 # ok 230 event_missing.LCALTA.28
2176 04:26:19.604597 # ok 231 event_spurious.LCALTA.28
2177 04:26:19.609694 # ok 232 get_value.LCALTA.27
2178 04:26:19.610120 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2179 04:26:19.615267 # ok 233 name.LCALTA.27
2180 04:26:19.615690 # ok 234 write_default.LCALTA.27
2181 04:26:19.620789 # ok 235 write_valid.LCALTA.27
2182 04:26:19.621217 # ok 236 write_invalid.LCALTA.27
2183 04:26:19.626330 # ok 237 event_missing.LCALTA.27
2184 04:26:19.626754 # ok 238 event_spurious.LCALTA.27
2185 04:26:19.631866 # ok 239 get_value.LCALTA.26
2186 04:26:19.632319 # # LCALTA.26 ELD
2187 04:26:19.637496 # ok 240 name.LCALTA.26
2188 04:26:19.637923 # # ELD is not writeable
2189 04:26:19.642976 # ok 241 # SKIP write_default.LCALTA.26
2190 04:26:19.643402 # # ELD is not writeable
2191 04:26:19.648526 # ok 242 # SKIP write_valid.LCALTA.26
2192 04:26:19.648952 # # ELD is not writeable
2193 04:26:19.654069 # ok 243 # SKIP write_invalid.LCALTA.26
2194 04:26:19.654492 # ok 244 event_missing.LCALTA.26
2195 04:26:19.659627 # ok 245 event_spurious.LCALTA.26
2196 04:26:19.660076 # ok 246 get_value.LCALTA.25
2197 04:26:19.665164 # # LCALTA.25 IEC958 Playback Default
2198 04:26:19.665586 # ok 247 name.LCALTA.25
2199 04:26:19.670707 # ok 248 write_default.LCALTA.25
2200 04:26:19.671133 # ok 249 # SKIP write_valid.LCALTA.25
2201 04:26:19.676258 # ok 250 # SKIP write_invalid.LCALTA.25
2202 04:26:19.681794 # ok 251 event_missing.LCALTA.25
2203 04:26:19.682214 # ok 252 event_spurious.LCALTA.25
2204 04:26:19.687336 # ok 253 get_value.LCALTA.24
2205 04:26:19.687757 # # LCALTA.24 IEC958 Playback Mask
2206 04:26:19.688204 # ok 254 name.LCALTA.24
2207 04:26:19.692910 # # IEC958 Playback Mask is not writeable
2208 04:26:19.698429 # ok 255 # SKIP write_default.LCALTA.24
2209 04:26:19.698860 # # IEC958 Playback Mask is not writeable
2210 04:26:19.703999 # ok 256 # SKIP write_valid.LCALTA.24
2211 04:26:19.709539 # # IEC958 Playback Mask is not writeable
2212 04:26:19.709965 # ok 257 # SKIP write_invalid.LCALTA.24
2213 04:26:19.715079 # ok 258 event_missing.LCALTA.24
2214 04:26:19.715503 # ok 259 event_spurious.LCALTA.24
2215 04:26:19.720606 # ok 260 get_value.LCALTA.23
2216 04:26:19.721031 # # LCALTA.23 Playback Channel Map
2217 04:26:19.726168 # ok 261 name.LCALTA.23
2218 04:26:19.731698 # # Playback Channel Map is not writeable
2219 04:26:19.732158 # ok 262 # SKIP write_default.LCALTA.23
2220 04:26:19.737327 # # Playback Channel Map is not writeable
2221 04:26:19.737754 # ok 263 # SKIP write_valid.LCALTA.23
2222 04:26:19.742819 # # Playback Channel Map is not writeable
2223 04:26:19.748358 # ok 264 # SKIP write_invalid.LCALTA.23
2224 04:26:19.748783 # ok 265 event_missing.LCALTA.23
2225 04:26:19.753912 # ok 266 event_spurious.LCALTA.23
2226 04:26:19.754340 # ok 267 get_value.LCALTA.22
2227 04:26:19.759458 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2228 04:26:19.759880 # ok 268 name.LCALTA.22
2229 04:26:19.765010 # ok 269 write_default.LCALTA.22
2230 04:26:19.765433 # ok 270 write_valid.LCALTA.22
2231 04:26:19.770552 # ok 271 write_invalid.LCALTA.22
2232 04:26:19.770976 # ok 272 event_missing.LCALTA.22
2233 04:26:19.776101 # ok 273 event_spurious.LCALTA.22
2234 04:26:19.781658 # ok 274 get_value.LCALTA.21
2235 04:26:19.782083 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2236 04:26:19.782484 # ok 275 name.LCALTA.21
2237 04:26:19.787188 # ok 276 write_default.LCALTA.21
2238 04:26:19.792728 # ok 277 write_valid.LCALTA.21
2239 04:26:19.793151 # ok 278 write_invalid.LCALTA.21
2240 04:26:19.798287 # ok 279 event_missing.LCALTA.21
2241 04:26:19.798709 # ok 280 event_spurious.LCALTA.21
2242 04:26:19.803825 # ok 281 get_value.LCALTA.20
2243 04:26:19.804288 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2244 04:26:19.809370 # ok 282 name.LCALTA.20
2245 04:26:19.809789 # ok 283 write_default.LCALTA.20
2246 04:26:19.814933 # ok 284 write_valid.LCALTA.20
2247 04:26:19.815352 # ok 285 write_invalid.LCALTA.20
2248 04:26:19.820467 # ok 286 event_missing.LCALTA.20
2249 04:26:19.820892 # ok 287 event_spurious.LCALTA.20
2250 04:26:19.826006 # ok 288 get_value.LCALTA.19
2251 04:26:19.826427 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2252 04:26:19.831555 # ok 289 name.LCALTA.19
2253 04:26:19.832005 # ok 290 write_default.LCALTA.19
2254 04:26:19.837152 # ok 291 write_valid.LCALTA.19
2255 04:26:19.837574 # ok 292 write_invalid.LCALTA.19
2256 04:26:19.842673 # ok 293 event_missing.LCALTA.19
2257 04:26:19.843101 # ok 294 event_spurious.LCALTA.19
2258 04:26:19.848202 # ok 295 get_value.LCALTA.18
2259 04:26:19.848625 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2260 04:26:19.853750 # ok 296 name.LCALTA.18
2261 04:26:19.854173 # ok 297 write_default.LCALTA.18
2262 04:26:19.859293 # ok 298 write_valid.LCALTA.18
2263 04:26:19.859714 # ok 299 write_invalid.LCALTA.18
2264 04:26:19.864839 # ok 300 event_missing.LCALTA.18
2265 04:26:19.865270 # ok 301 event_spurious.LCALTA.18
2266 04:26:19.870385 # ok 302 get_value.LCALTA.17
2267 04:26:19.875934 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2268 04:26:19.876381 # ok 303 name.LCALTA.17
2269 04:26:19.876780 # ok 304 write_default.LCALTA.17
2270 04:26:19.881473 # ok 305 write_valid.LCALTA.17
2271 04:26:19.887014 # ok 306 write_invalid.LCALTA.17
2272 04:26:19.887438 # ok 307 event_missing.LCALTA.17
2273 04:26:19.892579 # ok 308 event_spurious.LCALTA.17
2274 04:26:19.893006 # ok 309 get_value.LCALTA.16
2275 04:26:19.898124 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2276 04:26:19.898554 # ok 310 name.LCALTA.16
2277 04:26:19.903675 # ok 311 write_default.LCALTA.16
2278 04:26:19.904133 # ok 312 write_valid.LCALTA.16
2279 04:26:19.909211 # ok 313 write_invalid.LCALTA.16
2280 04:26:19.909639 # ok 314 event_missing.LCALTA.16
2281 04:26:19.914763 # ok 315 event_spurious.LCALTA.16
2282 04:26:19.915190 # ok 316 get_value.LCALTA.15
2283 04:26:19.920302 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2284 04:26:19.920724 # ok 317 name.LCALTA.15
2285 04:26:19.925837 # ok 318 write_default.LCALTA.15
2286 04:26:19.926264 # ok 319 write_valid.LCALTA.15
2287 04:26:19.931394 # ok 320 write_invalid.LCALTA.15
2288 04:26:19.931820 # ok 321 event_missing.LCALTA.15
2289 04:26:19.937002 # ok 322 event_spurious.LCALTA.15
2290 04:26:19.937430 # ok 323 get_value.LCALTA.14
2291 04:26:19.942487 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2292 04:26:19.942914 # ok 324 name.LCALTA.14
2293 04:26:19.948061 # ok 325 write_default.LCALTA.14
2294 04:26:19.948485 # ok 326 write_valid.LCALTA.14
2295 04:26:19.953595 # ok 327 write_invalid.LCALTA.14
2296 04:26:19.954017 # ok 328 event_missing.LCALTA.14
2297 04:26:19.959112 # ok 329 event_spurious.LCALTA.14
2298 04:26:19.959539 # ok 330 get_value.LCALTA.13
2299 04:26:19.964686 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2300 04:26:19.965117 # ok 331 name.LCALTA.13
2301 04:26:19.970241 # ok 332 write_default.LCALTA.13
2302 04:26:19.970666 # ok 333 write_valid.LCALTA.13
2303 04:26:19.975778 # ok 334 write_invalid.LCALTA.13
2304 04:26:19.976228 # ok 335 event_missing.LCALTA.13
2305 04:26:19.981322 # ok 336 event_spurious.LCALTA.13
2306 04:26:19.981743 # ok 337 get_value.LCALTA.12
2307 04:26:19.986861 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2308 04:26:19.987285 # ok 338 name.LCALTA.12
2309 04:26:19.992421 # ok 339 write_default.LCALTA.12
2310 04:26:19.997970 # ok 340 write_valid.LCALTA.12
2311 04:26:19.998395 # ok 341 write_invalid.LCALTA.12
2312 04:26:20.003514 # ok 342 event_missing.LCALTA.12
2313 04:26:20.003938 # ok 343 event_spurious.LCALTA.12
2314 04:26:20.009066 # ok 344 get_value.LCALTA.11
2315 04:26:20.009494 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2316 04:26:20.014595 # ok 345 name.LCALTA.11
2317 04:26:20.015018 # ok 346 write_default.LCALTA.11
2318 04:26:20.020191 # ok 347 write_valid.LCALTA.11
2319 04:26:20.020665 # ok 348 write_invalid.LCALTA.11
2320 04:26:20.025696 # ok 349 event_missing.LCALTA.11
2321 04:26:20.026175 # ok 350 event_spurious.LCALTA.11
2322 04:26:20.031285 # ok 351 get_value.LCALTA.10
2323 04:26:20.031783 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2324 04:26:20.036895 # ok 352 name.LCALTA.10
2325 04:26:20.037373 # ok 353 write_default.LCALTA.10
2326 04:26:20.042382 # ok 354 write_valid.LCALTA.10
2327 04:26:20.042812 # ok 355 write_invalid.LCALTA.10
2328 04:26:20.047881 # ok 356 event_missing.LCALTA.10
2329 04:26:20.048336 # ok 357 event_spurious.LCALTA.10
2330 04:26:20.053446 # ok 358 get_value.LCALTA.9
2331 04:26:20.053878 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2332 04:26:20.058980 # ok 359 name.LCALTA.9
2333 04:26:20.059408 # ok 360 write_default.LCALTA.9
2334 04:26:20.064532 # ok 361 write_valid.LCALTA.9
2335 04:26:20.064963 # ok 362 write_invalid.LCALTA.9
2336 04:26:20.070071 # ok 363 event_missing.LCALTA.9
2337 04:26:20.070498 # ok 364 event_spurious.LCALTA.9
2338 04:26:20.075621 # ok 365 get_value.LCALTA.8
2339 04:26:20.076076 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2340 04:26:20.081157 # ok 366 name.LCALTA.8
2341 04:26:20.081585 # ok 367 write_default.LCALTA.8
2342 04:26:20.086677 # ok 368 write_valid.LCALTA.8
2343 04:26:20.087110 # ok 369 write_invalid.LCALTA.8
2344 04:26:20.092330 # ok 370 event_missing.LCALTA.8
2345 04:26:20.092754 # ok 371 event_spurious.LCALTA.8
2346 04:26:20.097811 # ok 372 get_value.LCALTA.7
2347 04:26:20.098247 # # LCALTA.7 ACODEC Unmute Ramp Switch
2348 04:26:20.103373 # ok 373 name.LCALTA.7
2349 04:26:20.103796 # ok 374 write_default.LCALTA.7
2350 04:26:20.108905 # ok 375 write_valid.LCALTA.7
2351 04:26:20.109334 # ok 376 write_invalid.LCALTA.7
2352 04:26:20.114467 # ok 377 event_missing.LCALTA.7
2353 04:26:20.114892 # ok 378 event_spurious.LCALTA.7
2354 04:26:20.120003 # ok 379 get_value.LCALTA.6
2355 04:26:20.120434 # # LCALTA.6 ACODEC Mute Ramp Switch
2356 04:26:20.125517 # ok 380 name.LCALTA.6
2357 04:26:20.125937 # ok 381 write_default.LCALTA.6
2358 04:26:20.131085 # ok 382 write_valid.LCALTA.6
2359 04:26:20.131513 # ok 383 write_invalid.LCALTA.6
2360 04:26:20.136676 # ok 384 event_missing.LCALTA.6
2361 04:26:20.137107 # ok 385 event_spurious.LCALTA.6
2362 04:26:20.142182 # ok 386 get_value.LCALTA.5
2363 04:26:20.142609 # # LCALTA.5 ACODEC Volume Ramp Switch
2364 04:26:20.147720 # ok 387 name.LCALTA.5
2365 04:26:20.148170 # ok 388 write_default.LCALTA.5
2366 04:26:20.153340 # ok 389 write_valid.LCALTA.5
2367 04:26:20.153765 # ok 390 write_invalid.LCALTA.5
2368 04:26:20.158822 # ok 391 event_missing.LCALTA.5
2369 04:26:20.159247 # ok 392 event_spurious.LCALTA.5
2370 04:26:20.164382 # ok 393 get_value.LCALTA.4
2371 04:26:20.164805 # # LCALTA.4 ACODEC Ramp Rate
2372 04:26:20.169905 # ok 394 name.LCALTA.4
2373 04:26:20.170329 # ok 395 write_default.LCALTA.4
2374 04:26:20.175454 # ok 396 write_valid.LCALTA.4
2375 04:26:20.175875 # ok 397 write_invalid.LCALTA.4
2376 04:26:20.180973 # ok 398 event_missing.LCALTA.4
2377 04:26:20.181399 # ok 399 event_spurious.LCALTA.4
2378 04:26:20.186509 # ok 400 get_value.LCALTA.3
2379 04:26:20.186931 # # LCALTA.3 ACODEC Playback Volume
2380 04:26:20.192093 # ok 401 name.LCALTA.3
2381 04:26:20.192516 # ok 402 write_default.LCALTA.3
2382 04:26:20.197654 # ok 403 write_valid.LCALTA.3
2383 04:26:20.198081 # ok 404 write_invalid.LCALTA.3
2384 04:26:20.203188 # ok 405 event_missing.LCALTA.3
2385 04:26:20.203610 # ok 406 event_spurious.LCALTA.3
2386 04:26:20.208729 # ok 407 get_value.LCALTA.2
2387 04:26:20.209157 # # LCALTA.2 ACODEC Playback Switch
2388 04:26:20.214347 # ok 408 name.LCALTA.2
2389 04:26:20.214772 # ok 409 write_default.LCALTA.2
2390 04:26:20.219831 # ok 410 write_valid.LCALTA.2
2391 04:26:20.220277 # ok 411 write_invalid.LCALTA.2
2392 04:26:20.225359 # ok 412 event_missing.LCALTA.2
2393 04:26:20.225783 # ok 413 event_spurious.LCALTA.2
2394 04:26:20.230879 # ok 414 get_value.LCALTA.1
2395 04:26:20.231304 # # LCALTA.1 ACODEC Playback Channel Mode
2396 04:26:20.236528 # ok 415 name.LCALTA.1
2397 04:26:20.236962 # ok 416 write_default.LCALTA.1
2398 04:26:20.242021 # ok 417 write_valid.LCALTA.1
2399 04:26:20.242444 # ok 418 write_invalid.LCALTA.1
2400 04:26:20.247560 # ok 419 event_missing.LCALTA.1
2401 04:26:20.248014 # ok 420 event_spurious.LCALTA.1
2402 04:26:20.253116 # ok 421 get_value.LCALTA.0
2403 04:26:20.253539 # # LCALTA.0 TOACODEC Lane Select
2404 04:26:20.258651 # ok 422 name.LCALTA.0
2405 04:26:20.259072 # ok 423 write_default.LCALTA.0
2406 04:26:20.264217 # ok 424 write_valid.LCALTA.0
2407 04:26:20.264640 # ok 425 write_invalid.LCALTA.0
2408 04:26:20.269741 # ok 426 event_missing.LCALTA.0
2409 04:26:20.270165 # ok 427 event_spurious.LCALTA.0
2410 04:26:20.275371 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2411 04:26:20.280855 ok 1 selftests: alsa: mixer-test
2412 04:26:20.281290 # timeout set to 45
2413 04:26:20.281689 # selftests: alsa: pcm-test
2414 04:26:20.286390 # TAP version 13
2415 04:26:20.286837 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2416 04:26:20.291928 # # LCALTA.0 - fe.dai-link-0 (*)
2417 04:26:20.292415 # # LCALTA.0 - fe.dai-link-1 (*)
2418 04:26:20.297484 # # LCALTA.0 - fe.dai-link-2 (*)
2419 04:26:20.297924 # # LCALTA.0 - fe.dai-link-3 (*)
2420 04:26:20.303026 # # LCALTA.0 - fe.dai-link-4 (*)
2421 04:26:20.303452 # # LCALTA.0 - fe.dai-link-5 (*)
2422 04:26:20.308580 # 1..42
2423 04:26:20.314132 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2424 04:26:20.314556 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2425 04:26:20.319675 # # snd_pcm_hw_params: Invalid argument
2426 04:26:20.325237 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2427 04:26:20.330767 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2428 04:26:20.331195 # # snd_pcm_hw_params: Invalid argument
2429 04:26:20.336445 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2430 04:26:20.342063 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2431 04:26:20.347416 # # snd_pcm_hw_params: Invalid argument
2432 04:26:20.352977 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2433 04:26:20.358629 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2434 04:26:20.359097 # # snd_pcm_hw_params: Invalid argument
2435 04:26:20.364055 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2436 04:26:20.369655 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2437 04:26:20.375260 # # snd_pcm_hw_params: Invalid argument
2438 04:26:20.380806 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2439 04:26:20.386353 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2440 04:26:20.386845 # # snd_pcm_hw_params: Invalid argument
2441 04:26:20.391880 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2442 04:26:20.397485 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2443 04:26:20.402954 # # snd_pcm_hw_params: Invalid argument
2444 04:26:20.408495 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2445 04:26:20.408985 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2446 04:26:20.414153 # # snd_pcm_hw_params: Invalid argument
2447 04:26:20.419692 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2448 04:26:20.425157 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2449 04:26:20.425651 # # snd_pcm_hw_params: Invalid argument
2450 04:26:20.436215 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2451 04:26:20.436725 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2452 04:26:20.441803 # # snd_pcm_hw_params: Invalid argument
2453 04:26:20.447381 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2454 04:26:20.452883 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2455 04:26:20.453387 # # snd_pcm_hw_params: Invalid argument
2456 04:26:20.458482 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2457 04:26:20.464045 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2458 04:26:20.469547 # # snd_pcm_hw_params: Invalid argument
2459 04:26:20.475093 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2460 04:26:20.480637 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2461 04:26:20.481143 # # snd_pcm_hw_params: Invalid argument
2462 04:26:20.486168 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2463 04:26:20.491697 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2464 04:26:20.497265 # # snd_pcm_hw_params: Invalid argument
2465 04:26:20.502838 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2466 04:26:20.508397 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2467 04:26:20.508911 # # snd_pcm_hw_params: Invalid argument
2468 04:26:20.513921 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2469 04:26:20.519552 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2470 04:26:20.525026 # # snd_pcm_hw_params: Invalid argument
2471 04:26:20.530604 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2472 04:26:20.531132 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2473 04:26:20.536141 # # snd_pcm_hw_params: Invalid argument
2474 04:26:20.541758 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2475 04:26:20.547207 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2476 04:26:20.552823 # # snd_pcm_hw_params: Invalid argument
2477 04:26:20.558296 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2478 04:26:20.558831 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2479 04:26:20.563888 # # snd_pcm_hw_params: Invalid argument
2480 04:26:20.569461 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2481 04:26:20.574913 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2482 04:26:20.580534 # # snd_pcm_hw_params: Invalid argument
2483 04:26:20.586034 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2484 04:26:20.586555 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2485 04:26:20.591572 # # snd_pcm_hw_params: Invalid argument
2486 04:26:20.597122 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2487 04:26:20.602653 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2488 04:26:20.603161 # # snd_pcm_hw_params: Invalid argument
2489 04:26:20.608240 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2490 04:26:20.613754 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2491 04:26:20.619291 # # snd_pcm_hw_params: Invalid argument
2492 04:26:20.624845 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2493 04:26:20.630372 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2494 04:26:20.630877 # # snd_pcm_hw_params: Invalid argument
2495 04:26:20.635950 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2496 04:26:20.641572 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2497 04:26:20.647025 # # snd_pcm_hw_params: Invalid argument
2498 04:26:20.652561 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2499 04:26:20.658117 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2500 04:26:20.658617 # # snd_pcm_hw_params: Invalid argument
2501 04:26:20.663665 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2502 04:26:20.669207 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2503 04:26:20.674744 # # snd_pcm_hw_params: Invalid argument
2504 04:26:20.680335 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2505 04:26:20.685861 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2506 04:26:20.686373 # # snd_pcm_hw_params: Invalid argument
2507 04:26:20.691426 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2508 04:26:20.696947 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2509 04:26:20.702521 # # snd_pcm_hw_params: Invalid argument
2510 04:26:20.708071 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2511 04:26:20.713590 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2512 04:26:20.714092 # # snd_pcm_hw_params: Invalid argument
2513 04:26:20.719143 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2514 04:26:20.724691 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2515 04:26:20.730230 # # snd_pcm_hw_params: Invalid argument
2516 04:26:20.735766 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2517 04:26:20.741403 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2518 04:26:20.741929 # # snd_pcm_hw_params: Invalid argument
2519 04:26:20.746885 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2520 04:26:20.752416 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2521 04:26:20.757981 # # snd_pcm_hw_params: Invalid argument
2522 04:26:20.763523 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2523 04:26:20.769047 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2524 04:26:20.769548 # # snd_pcm_hw_params: Invalid argument
2525 04:26:20.774609 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2526 04:26:20.780202 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2527 04:26:20.785694 # # snd_pcm_hw_params: Invalid argument
2528 04:26:20.791251 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2529 04:26:20.796807 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2530 04:26:20.797314 # # snd_pcm_hw_params: Invalid argument
2531 04:26:20.802323 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2532 04:26:20.807889 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2533 04:26:20.813428 # # snd_pcm_hw_params: Invalid argument
2534 04:26:20.819023 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2535 04:26:20.824607 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2536 04:26:20.825137 # # snd_pcm_hw_params: Invalid argument
2537 04:26:20.830068 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2538 04:26:20.835639 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2539 04:26:20.841288 # # snd_pcm_hw_params: Invalid argument
2540 04:26:20.846777 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2541 04:26:20.852290 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2542 04:26:20.852810 # # snd_pcm_hw_params: Invalid argument
2543 04:26:20.857822 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2544 04:26:20.863366 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2545 04:26:20.868894 # # snd_pcm_hw_params: Invalid argument
2546 04:26:20.874480 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2547 04:26:20.880060 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2548 04:26:20.880589 # # snd_pcm_hw_params: Invalid argument
2549 04:26:20.885586 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2550 04:26:20.891091 ok 2 selftests: alsa: pcm-test
2551 04:26:20.891614 # timeout set to 45
2552 04:26:20.896648 # selftests: alsa: test-pcmtest-driver
2553 04:26:20.897172 # TAP version 13
2554 04:26:20.897604 # 1..5
2555 04:26:20.902190 # # Starting 5 tests from 1 test cases.
2556 04:26:20.902710 # # RUN pcmtest.playback ...
2557 04:26:20.907768 # # SKIP Can't read patterns. Probably, module isn't loaded
2558 04:26:20.913354 # # OK pcmtest.playback
2559 04:26:20.918802 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2560 04:26:20.924342 # # RUN pcmtest.capture ...
2561 04:26:20.929898 # # SKIP Can't read patterns. Probably, module isn't loaded
2562 04:26:20.935444 # # OK pcmtest.capture
2563 04:26:20.941056 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2564 04:26:20.946560 # # RUN pcmtest.ni_capture ...
2565 04:26:20.952113 # # SKIP Can't read patterns. Probably, module isn't loaded
2566 04:26:20.952660 # # OK pcmtest.ni_capture
2567 04:26:20.963128 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2568 04:26:20.963679 # # RUN pcmtest.ni_playback ...
2569 04:26:20.968739 # # SKIP Can't read patterns. Probably, module isn't loaded
2570 04:26:20.974298 # # OK pcmtest.ni_playback
2571 04:26:20.979815 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2572 04:26:20.985356 # # RUN pcmtest.reset_ioctl ...
2573 04:26:20.990914 # # SKIP Can't read patterns. Probably, module isn't loaded
2574 04:26:20.996454 # # OK pcmtest.reset_ioctl
2575 04:26:21.002011 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2576 04:26:21.007549 # # PASSED: 5 / 5 tests passed.
2577 04:26:21.013104 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2578 04:26:21.013606 ok 3 selftests: alsa: test-pcmtest-driver
2579 04:26:21.018662 # timeout set to 45
2580 04:26:21.019181 # selftests: alsa: utimer-test
2581 04:26:21.019606 # TAP version 13
2582 04:26:21.020050 # 1..2
2583 04:26:21.024269 # # Starting 2 tests from 2 test cases.
2584 04:26:21.029748 # # RUN global.wrong_timers_test ...
2585 04:26:21.035291 # # OK global.wrong_timers_test
2586 04:26:21.035791 # ok 1 global.wrong_timers_test
2587 04:26:21.040894 # # RUN timer_f.utimer ...
2588 04:26:21.046384 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2589 04:26:21.051942 # # utimer: Test terminated by assertion
2590 04:26:21.057483 # # FAIL timer_f.utimer
2591 04:26:21.057976 # not ok 2 timer_f.utimer
2592 04:26:21.063040 # # FAILED: 1 / 2 tests passed.
2593 04:26:21.070428 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2594 04:26:21.070913 not ok 4 selftests: alsa: utimer-test # exit=1
2595 04:26:21.642098 alsa_mixer-test_get_value_LCALTA_60 pass
2596 04:26:21.647599 alsa_mixer-test_name_LCALTA_60 pass
2597 04:26:21.648143 alsa_mixer-test_write_default_LCALTA_60 pass
2598 04:26:21.653072 alsa_mixer-test_write_valid_LCALTA_60 pass
2599 04:26:21.658610 alsa_mixer-test_write_invalid_LCALTA_60 pass
2600 04:26:21.664188 alsa_mixer-test_event_missing_LCALTA_60 pass
2601 04:26:21.664689 alsa_mixer-test_event_spurious_LCALTA_60 pass
2602 04:26:21.669716 alsa_mixer-test_get_value_LCALTA_59 pass
2603 04:26:21.675264 alsa_mixer-test_name_LCALTA_59 pass
2604 04:26:21.675737 alsa_mixer-test_write_default_LCALTA_59 pass
2605 04:26:21.680802 alsa_mixer-test_write_valid_LCALTA_59 pass
2606 04:26:21.686327 alsa_mixer-test_write_invalid_LCALTA_59 pass
2607 04:26:21.686793 alsa_mixer-test_event_missing_LCALTA_59 pass
2608 04:26:21.691907 alsa_mixer-test_event_spurious_LCALTA_59 pass
2609 04:26:21.697465 alsa_mixer-test_get_value_LCALTA_58 pass
2610 04:26:21.697932 alsa_mixer-test_name_LCALTA_58 pass
2611 04:26:21.702991 alsa_mixer-test_write_default_LCALTA_58 pass
2612 04:26:21.708540 alsa_mixer-test_write_valid_LCALTA_58 pass
2613 04:26:21.709018 alsa_mixer-test_write_invalid_LCALTA_58 pass
2614 04:26:21.714068 alsa_mixer-test_event_missing_LCALTA_58 pass
2615 04:26:21.719623 alsa_mixer-test_event_spurious_LCALTA_58 pass
2616 04:26:21.725160 alsa_mixer-test_get_value_LCALTA_57 pass
2617 04:26:21.725621 alsa_mixer-test_name_LCALTA_57 pass
2618 04:26:21.730797 alsa_mixer-test_write_default_LCALTA_57 pass
2619 04:26:21.736331 alsa_mixer-test_write_valid_LCALTA_57 pass
2620 04:26:21.736800 alsa_mixer-test_write_invalid_LCALTA_57 pass
2621 04:26:21.741888 alsa_mixer-test_event_missing_LCALTA_57 pass
2622 04:26:21.747477 alsa_mixer-test_event_spurious_LCALTA_57 pass
2623 04:26:21.747964 alsa_mixer-test_get_value_LCALTA_56 pass
2624 04:26:21.753017 alsa_mixer-test_name_LCALTA_56 pass
2625 04:26:21.758538 alsa_mixer-test_write_default_LCALTA_56 pass
2626 04:26:21.759012 alsa_mixer-test_write_valid_LCALTA_56 pass
2627 04:26:21.764087 alsa_mixer-test_write_invalid_LCALTA_56 pass
2628 04:26:21.769643 alsa_mixer-test_event_missing_LCALTA_56 pass
2629 04:26:21.775176 alsa_mixer-test_event_spurious_LCALTA_56 pass
2630 04:26:21.775640 alsa_mixer-test_get_value_LCALTA_55 pass
2631 04:26:21.780704 alsa_mixer-test_name_LCALTA_55 pass
2632 04:26:21.786281 alsa_mixer-test_write_default_LCALTA_55 pass
2633 04:26:21.786750 alsa_mixer-test_write_valid_LCALTA_55 pass
2634 04:26:21.791807 alsa_mixer-test_write_invalid_LCALTA_55 pass
2635 04:26:21.797356 alsa_mixer-test_event_missing_LCALTA_55 pass
2636 04:26:21.797823 alsa_mixer-test_event_spurious_LCALTA_55 pass
2637 04:26:21.802914 alsa_mixer-test_get_value_LCALTA_54 pass
2638 04:26:21.808449 alsa_mixer-test_name_LCALTA_54 pass
2639 04:26:21.808914 alsa_mixer-test_write_default_LCALTA_54 pass
2640 04:26:21.813989 alsa_mixer-test_write_valid_LCALTA_54 pass
2641 04:26:21.819559 alsa_mixer-test_write_invalid_LCALTA_54 pass
2642 04:26:21.820053 alsa_mixer-test_event_missing_LCALTA_54 pass
2643 04:26:21.825087 alsa_mixer-test_event_spurious_LCALTA_54 pass
2644 04:26:21.830636 alsa_mixer-test_get_value_LCALTA_53 pass
2645 04:26:21.831102 alsa_mixer-test_name_LCALTA_53 pass
2646 04:26:21.836214 alsa_mixer-test_write_default_LCALTA_53 pass
2647 04:26:21.841717 alsa_mixer-test_write_valid_LCALTA_53 pass
2648 04:26:21.847333 alsa_mixer-test_write_invalid_LCALTA_53 pass
2649 04:26:21.847818 alsa_mixer-test_event_missing_LCALTA_53 pass
2650 04:26:21.852864 alsa_mixer-test_event_spurious_LCALTA_53 pass
2651 04:26:21.858378 alsa_mixer-test_get_value_LCALTA_52 pass
2652 04:26:21.858852 alsa_mixer-test_name_LCALTA_52 pass
2653 04:26:21.863920 alsa_mixer-test_write_default_LCALTA_52 pass
2654 04:26:21.869471 alsa_mixer-test_write_valid_LCALTA_52 pass
2655 04:26:21.869937 alsa_mixer-test_write_invalid_LCALTA_52 pass
2656 04:26:21.875039 alsa_mixer-test_event_missing_LCALTA_52 pass
2657 04:26:21.880548 alsa_mixer-test_event_spurious_LCALTA_52 pass
2658 04:26:21.881014 alsa_mixer-test_get_value_LCALTA_51 pass
2659 04:26:21.886106 alsa_mixer-test_name_LCALTA_51 pass
2660 04:26:21.891667 alsa_mixer-test_write_default_LCALTA_51 pass
2661 04:26:21.892160 alsa_mixer-test_write_valid_LCALTA_51 pass
2662 04:26:21.897197 alsa_mixer-test_write_invalid_LCALTA_51 pass
2663 04:26:21.902741 alsa_mixer-test_event_missing_LCALTA_51 pass
2664 04:26:21.908277 alsa_mixer-test_event_spurious_LCALTA_51 pass
2665 04:26:21.908738 alsa_mixer-test_get_value_LCALTA_50 pass
2666 04:26:21.913853 alsa_mixer-test_name_LCALTA_50 pass
2667 04:26:21.919410 alsa_mixer-test_write_default_LCALTA_50 pass
2668 04:26:21.919879 alsa_mixer-test_write_valid_LCALTA_50 pass
2669 04:26:21.924936 alsa_mixer-test_write_invalid_LCALTA_50 pass
2670 04:26:21.930475 alsa_mixer-test_event_missing_LCALTA_50 pass
2671 04:26:21.930940 alsa_mixer-test_event_spurious_LCALTA_50 pass
2672 04:26:21.936051 alsa_mixer-test_get_value_LCALTA_49 pass
2673 04:26:21.941574 alsa_mixer-test_name_LCALTA_49 pass
2674 04:26:21.942041 alsa_mixer-test_write_default_LCALTA_49 pass
2675 04:26:21.947156 alsa_mixer-test_write_valid_LCALTA_49 pass
2676 04:26:21.952668 alsa_mixer-test_write_invalid_LCALTA_49 pass
2677 04:26:21.958201 alsa_mixer-test_event_missing_LCALTA_49 pass
2678 04:26:21.958671 alsa_mixer-test_event_spurious_LCALTA_49 pass
2679 04:26:21.963757 alsa_mixer-test_get_value_LCALTA_48 pass
2680 04:26:21.964255 alsa_mixer-test_name_LCALTA_48 pass
2681 04:26:21.969330 alsa_mixer-test_write_default_LCALTA_48 pass
2682 04:26:21.974868 alsa_mixer-test_write_valid_LCALTA_48 pass
2683 04:26:21.980421 alsa_mixer-test_write_invalid_LCALTA_48 pass
2684 04:26:21.980890 alsa_mixer-test_event_missing_LCALTA_48 pass
2685 04:26:21.985958 alsa_mixer-test_event_spurious_LCALTA_48 pass
2686 04:26:21.991502 alsa_mixer-test_get_value_LCALTA_47 pass
2687 04:26:21.991964 alsa_mixer-test_name_LCALTA_47 pass
2688 04:26:21.997063 alsa_mixer-test_write_default_LCALTA_47 pass
2689 04:26:22.002584 alsa_mixer-test_write_valid_LCALTA_47 pass
2690 04:26:22.003051 alsa_mixer-test_write_invalid_LCALTA_47 pass
2691 04:26:22.008191 alsa_mixer-test_event_missing_LCALTA_47 pass
2692 04:26:22.013676 alsa_mixer-test_event_spurious_LCALTA_47 pass
2693 04:26:22.019242 alsa_mixer-test_get_value_LCALTA_46 pass
2694 04:26:22.019736 alsa_mixer-test_name_LCALTA_46 pass
2695 04:26:22.024805 alsa_mixer-test_write_default_LCALTA_46 pass
2696 04:26:22.030351 alsa_mixer-test_write_valid_LCALTA_46 pass
2697 04:26:22.030847 alsa_mixer-test_write_invalid_LCALTA_46 pass
2698 04:26:22.035876 alsa_mixer-test_event_missing_LCALTA_46 pass
2699 04:26:22.041424 alsa_mixer-test_event_spurious_LCALTA_46 pass
2700 04:26:22.041892 alsa_mixer-test_get_value_LCALTA_45 pass
2701 04:26:22.047018 alsa_mixer-test_name_LCALTA_45 pass
2702 04:26:22.052530 alsa_mixer-test_write_default_LCALTA_45 pass
2703 04:26:22.053002 alsa_mixer-test_write_valid_LCALTA_45 pass
2704 04:26:22.058081 alsa_mixer-test_write_invalid_LCALTA_45 pass
2705 04:26:22.063615 alsa_mixer-test_event_missing_LCALTA_45 pass
2706 04:26:22.064122 alsa_mixer-test_event_spurious_LCALTA_45 pass
2707 04:26:22.069151 alsa_mixer-test_get_value_LCALTA_44 pass
2708 04:26:22.074701 alsa_mixer-test_name_LCALTA_44 pass
2709 04:26:22.075173 alsa_mixer-test_write_default_LCALTA_44 pass
2710 04:26:22.080270 alsa_mixer-test_write_valid_LCALTA_44 pass
2711 04:26:22.085790 alsa_mixer-test_write_invalid_LCALTA_44 pass
2712 04:26:22.091340 alsa_mixer-test_event_missing_LCALTA_44 pass
2713 04:26:22.091804 alsa_mixer-test_event_spurious_LCALTA_44 pass
2714 04:26:22.096900 alsa_mixer-test_get_value_LCALTA_43 pass
2715 04:26:22.102431 alsa_mixer-test_name_LCALTA_43 pass
2716 04:26:22.102895 alsa_mixer-test_write_default_LCALTA_43 pass
2717 04:26:22.108003 alsa_mixer-test_write_valid_LCALTA_43 pass
2718 04:26:22.113512 alsa_mixer-test_write_invalid_LCALTA_43 pass
2719 04:26:22.113978 alsa_mixer-test_event_missing_LCALTA_43 pass
2720 04:26:22.119071 alsa_mixer-test_event_spurious_LCALTA_43 pass
2721 04:26:22.124614 alsa_mixer-test_get_value_LCALTA_42 pass
2722 04:26:22.125083 alsa_mixer-test_name_LCALTA_42 pass
2723 04:26:22.130142 alsa_mixer-test_write_default_LCALTA_42 pass
2724 04:26:22.135741 alsa_mixer-test_write_valid_LCALTA_42 pass
2725 04:26:22.136235 alsa_mixer-test_write_invalid_LCALTA_42 pass
2726 04:26:22.141247 alsa_mixer-test_event_missing_LCALTA_42 pass
2727 04:26:22.146853 alsa_mixer-test_event_spurious_LCALTA_42 pass
2728 04:26:22.152359 alsa_mixer-test_get_value_LCALTA_41 pass
2729 04:26:22.152828 alsa_mixer-test_name_LCALTA_41 pass
2730 04:26:22.157906 alsa_mixer-test_write_default_LCALTA_41 pass
2731 04:26:22.163462 alsa_mixer-test_write_valid_LCALTA_41 pass
2732 04:26:22.163931 alsa_mixer-test_write_invalid_LCALTA_41 pass
2733 04:26:22.169008 alsa_mixer-test_event_missing_LCALTA_41 pass
2734 04:26:22.174525 alsa_mixer-test_event_spurious_LCALTA_41 pass
2735 04:26:22.175000 alsa_mixer-test_get_value_LCALTA_40 pass
2736 04:26:22.180107 alsa_mixer-test_name_LCALTA_40 pass
2737 04:26:22.185634 alsa_mixer-test_write_default_LCALTA_40 pass
2738 04:26:22.186106 alsa_mixer-test_write_valid_LCALTA_40 pass
2739 04:26:22.191172 alsa_mixer-test_write_invalid_LCALTA_40 pass
2740 04:26:22.196747 alsa_mixer-test_event_missing_LCALTA_40 pass
2741 04:26:22.202276 alsa_mixer-test_event_spurious_LCALTA_40 pass
2742 04:26:22.202746 alsa_mixer-test_get_value_LCALTA_39 pass
2743 04:26:22.207852 alsa_mixer-test_name_LCALTA_39 pass
2744 04:26:22.213352 alsa_mixer-test_write_default_LCALTA_39 pass
2745 04:26:22.213822 alsa_mixer-test_write_valid_LCALTA_39 pass
2746 04:26:22.218920 alsa_mixer-test_write_invalid_LCALTA_39 pass
2747 04:26:22.224450 alsa_mixer-test_event_missing_LCALTA_39 pass
2748 04:26:22.224917 alsa_mixer-test_event_spurious_LCALTA_39 pass
2749 04:26:22.229998 alsa_mixer-test_get_value_LCALTA_38 pass
2750 04:26:22.235547 alsa_mixer-test_name_LCALTA_38 pass
2751 04:26:22.236045 alsa_mixer-test_write_default_LCALTA_38 pass
2752 04:26:22.241089 alsa_mixer-test_write_valid_LCALTA_38 pass
2753 04:26:22.246786 alsa_mixer-test_write_invalid_LCALTA_38 pass
2754 04:26:22.247279 alsa_mixer-test_event_missing_LCALTA_38 pass
2755 04:26:22.252241 alsa_mixer-test_event_spurious_LCALTA_38 pass
2756 04:26:22.257780 alsa_mixer-test_get_value_LCALTA_37 pass
2757 04:26:22.258255 alsa_mixer-test_name_LCALTA_37 pass
2758 04:26:22.263299 alsa_mixer-test_write_default_LCALTA_37 pass
2759 04:26:22.268846 alsa_mixer-test_write_valid_LCALTA_37 pass
2760 04:26:22.274380 alsa_mixer-test_write_invalid_LCALTA_37 pass
2761 04:26:22.274844 alsa_mixer-test_event_missing_LCALTA_37 pass
2762 04:26:22.279914 alsa_mixer-test_event_spurious_LCALTA_37 pass
2763 04:26:22.285470 alsa_mixer-test_get_value_LCALTA_36 pass
2764 04:26:22.285937 alsa_mixer-test_name_LCALTA_36 pass
2765 04:26:22.291012 alsa_mixer-test_write_default_LCALTA_36 pass
2766 04:26:22.296599 alsa_mixer-test_write_valid_LCALTA_36 pass
2767 04:26:22.297067 alsa_mixer-test_write_invalid_LCALTA_36 pass
2768 04:26:22.302111 alsa_mixer-test_event_missing_LCALTA_36 pass
2769 04:26:22.307740 alsa_mixer-test_event_spurious_LCALTA_36 pass
2770 04:26:22.308236 alsa_mixer-test_get_value_LCALTA_35 pass
2771 04:26:22.313205 alsa_mixer-test_name_LCALTA_35 pass
2772 04:26:22.318778 alsa_mixer-test_write_default_LCALTA_35 pass
2773 04:26:22.319249 alsa_mixer-test_write_valid_LCALTA_35 pass
2774 04:26:22.324293 alsa_mixer-test_write_invalid_LCALTA_35 pass
2775 04:26:22.329833 alsa_mixer-test_event_missing_LCALTA_35 pass
2776 04:26:22.335380 alsa_mixer-test_event_spurious_LCALTA_35 pass
2777 04:26:22.335846 alsa_mixer-test_get_value_LCALTA_34 pass
2778 04:26:22.340937 alsa_mixer-test_name_LCALTA_34 pass
2779 04:26:22.346568 alsa_mixer-test_write_default_LCALTA_34 pass
2780 04:26:22.347119 alsa_mixer-test_write_valid_LCALTA_34 pass
2781 04:26:22.352083 alsa_mixer-test_write_invalid_LCALTA_34 pass
2782 04:26:22.357603 alsa_mixer-test_event_missing_LCALTA_34 pass
2783 04:26:22.358088 alsa_mixer-test_event_spurious_LCALTA_34 pass
2784 04:26:22.363114 alsa_mixer-test_get_value_LCALTA_33 pass
2785 04:26:22.368721 alsa_mixer-test_name_LCALTA_33 pass
2786 04:26:22.369197 alsa_mixer-test_write_default_LCALTA_33 pass
2787 04:26:22.374255 alsa_mixer-test_write_valid_LCALTA_33 pass
2788 04:26:22.379812 alsa_mixer-test_write_invalid_LCALTA_33 pass
2789 04:26:22.385405 alsa_mixer-test_event_missing_LCALTA_33 pass
2790 04:26:22.385900 alsa_mixer-test_event_spurious_LCALTA_33 pass
2791 04:26:22.390958 alsa_mixer-test_get_value_LCALTA_32 pass
2792 04:26:22.391436 alsa_mixer-test_name_LCALTA_32 pass
2793 04:26:22.396726 alsa_mixer-test_write_default_LCALTA_32 pass
2794 04:26:22.402002 alsa_mixer-test_write_valid_LCALTA_32 pass
2795 04:26:22.407522 alsa_mixer-test_write_invalid_LCALTA_32 pass
2796 04:26:22.408024 alsa_mixer-test_event_missing_LCALTA_32 pass
2797 04:26:22.413063 alsa_mixer-test_event_spurious_LCALTA_32 pass
2798 04:26:22.418708 alsa_mixer-test_get_value_LCALTA_31 pass
2799 04:26:22.419243 alsa_mixer-test_name_LCALTA_31 pass
2800 04:26:22.424186 alsa_mixer-test_write_default_LCALTA_31 pass
2801 04:26:22.429737 alsa_mixer-test_write_valid_LCALTA_31 pass
2802 04:26:22.430211 alsa_mixer-test_write_invalid_LCALTA_31 pass
2803 04:26:22.435220 alsa_mixer-test_event_missing_LCALTA_31 pass
2804 04:26:22.440767 alsa_mixer-test_event_spurious_LCALTA_31 pass
2805 04:26:22.446351 alsa_mixer-test_get_value_LCALTA_30 pass
2806 04:26:22.446834 alsa_mixer-test_name_LCALTA_30 pass
2807 04:26:22.451918 alsa_mixer-test_write_default_LCALTA_30 pass
2808 04:26:22.457439 alsa_mixer-test_write_valid_LCALTA_30 pass
2809 04:26:22.457913 alsa_mixer-test_write_invalid_LCALTA_30 pass
2810 04:26:22.462985 alsa_mixer-test_event_missing_LCALTA_30 pass
2811 04:26:22.468518 alsa_mixer-test_event_spurious_LCALTA_30 pass
2812 04:26:22.468992 alsa_mixer-test_get_value_LCALTA_29 pass
2813 04:26:22.474069 alsa_mixer-test_name_LCALTA_29 pass
2814 04:26:22.479609 alsa_mixer-test_write_default_LCALTA_29 pass
2815 04:26:22.480116 alsa_mixer-test_write_valid_LCALTA_29 pass
2816 04:26:22.485132 alsa_mixer-test_write_invalid_LCALTA_29 pass
2817 04:26:22.490736 alsa_mixer-test_event_missing_LCALTA_29 pass
2818 04:26:22.491204 alsa_mixer-test_event_spurious_LCALTA_29 pass
2819 04:26:22.496305 alsa_mixer-test_get_value_LCALTA_28 pass
2820 04:26:22.501827 alsa_mixer-test_name_LCALTA_28 pass
2821 04:26:22.502307 alsa_mixer-test_write_default_LCALTA_28 pass
2822 04:26:22.507355 alsa_mixer-test_write_valid_LCALTA_28 pass
2823 04:26:22.512902 alsa_mixer-test_write_invalid_LCALTA_28 pass
2824 04:26:22.518451 alsa_mixer-test_event_missing_LCALTA_28 pass
2825 04:26:22.518952 alsa_mixer-test_event_spurious_LCALTA_28 pass
2826 04:26:22.524031 alsa_mixer-test_get_value_LCALTA_27 pass
2827 04:26:22.529540 alsa_mixer-test_name_LCALTA_27 pass
2828 04:26:22.530032 alsa_mixer-test_write_default_LCALTA_27 pass
2829 04:26:22.535096 alsa_mixer-test_write_valid_LCALTA_27 pass
2830 04:26:22.540649 alsa_mixer-test_write_invalid_LCALTA_27 pass
2831 04:26:22.541140 alsa_mixer-test_event_missing_LCALTA_27 pass
2832 04:26:22.546179 alsa_mixer-test_event_spurious_LCALTA_27 pass
2833 04:26:22.551872 alsa_mixer-test_get_value_LCALTA_26 pass
2834 04:26:22.552434 alsa_mixer-test_name_LCALTA_26 pass
2835 04:26:22.557303 alsa_mixer-test_write_default_LCALTA_26 skip
2836 04:26:22.562845 alsa_mixer-test_write_valid_LCALTA_26 skip
2837 04:26:22.563338 alsa_mixer-test_write_invalid_LCALTA_26 skip
2838 04:26:22.568414 alsa_mixer-test_event_missing_LCALTA_26 pass
2839 04:26:22.573903 alsa_mixer-test_event_spurious_LCALTA_26 pass
2840 04:26:22.579460 alsa_mixer-test_get_value_LCALTA_25 pass
2841 04:26:22.579922 alsa_mixer-test_name_LCALTA_25 pass
2842 04:26:22.585029 alsa_mixer-test_write_default_LCALTA_25 pass
2843 04:26:22.590558 alsa_mixer-test_write_valid_LCALTA_25 skip
2844 04:26:22.591035 alsa_mixer-test_write_invalid_LCALTA_25 skip
2845 04:26:22.596095 alsa_mixer-test_event_missing_LCALTA_25 pass
2846 04:26:22.601636 alsa_mixer-test_event_spurious_LCALTA_25 pass
2847 04:26:22.602104 alsa_mixer-test_get_value_LCALTA_24 pass
2848 04:26:22.607191 alsa_mixer-test_name_LCALTA_24 pass
2849 04:26:22.612795 alsa_mixer-test_write_default_LCALTA_24 skip
2850 04:26:22.613281 alsa_mixer-test_write_valid_LCALTA_24 skip
2851 04:26:22.618290 alsa_mixer-test_write_invalid_LCALTA_24 skip
2852 04:26:22.623836 alsa_mixer-test_event_missing_LCALTA_24 pass
2853 04:26:22.629386 alsa_mixer-test_event_spurious_LCALTA_24 pass
2854 04:26:22.629868 alsa_mixer-test_get_value_LCALTA_23 pass
2855 04:26:22.634916 alsa_mixer-test_name_LCALTA_23 pass
2856 04:26:22.640466 alsa_mixer-test_write_default_LCALTA_23 skip
2857 04:26:22.640954 alsa_mixer-test_write_valid_LCALTA_23 skip
2858 04:26:22.646033 alsa_mixer-test_write_invalid_LCALTA_23 skip
2859 04:26:22.651655 alsa_mixer-test_event_missing_LCALTA_23 pass
2860 04:26:22.652227 alsa_mixer-test_event_spurious_LCALTA_23 pass
2861 04:26:22.657156 alsa_mixer-test_get_value_LCALTA_22 pass
2862 04:26:22.662699 alsa_mixer-test_name_LCALTA_22 pass
2863 04:26:22.663192 alsa_mixer-test_write_default_LCALTA_22 pass
2864 04:26:22.668249 alsa_mixer-test_write_valid_LCALTA_22 pass
2865 04:26:22.673794 alsa_mixer-test_write_invalid_LCALTA_22 pass
2866 04:26:22.674291 alsa_mixer-test_event_missing_LCALTA_22 pass
2867 04:26:22.679318 alsa_mixer-test_event_spurious_LCALTA_22 pass
2868 04:26:22.684856 alsa_mixer-test_get_value_LCALTA_21 pass
2869 04:26:22.685353 alsa_mixer-test_name_LCALTA_21 pass
2870 04:26:22.690411 alsa_mixer-test_write_default_LCALTA_21 pass
2871 04:26:22.695971 alsa_mixer-test_write_valid_LCALTA_21 pass
2872 04:26:22.701525 alsa_mixer-test_write_invalid_LCALTA_21 pass
2873 04:26:22.702023 alsa_mixer-test_event_missing_LCALTA_21 pass
2874 04:26:22.707079 alsa_mixer-test_event_spurious_LCALTA_21 pass
2875 04:26:22.712586 alsa_mixer-test_get_value_LCALTA_20 pass
2876 04:26:22.713082 alsa_mixer-test_name_LCALTA_20 pass
2877 04:26:22.718156 alsa_mixer-test_write_default_LCALTA_20 pass
2878 04:26:22.723689 alsa_mixer-test_write_valid_LCALTA_20 pass
2879 04:26:22.724204 alsa_mixer-test_write_invalid_LCALTA_20 pass
2880 04:26:22.729202 alsa_mixer-test_event_missing_LCALTA_20 pass
2881 04:26:22.734784 alsa_mixer-test_event_spurious_LCALTA_20 pass
2882 04:26:22.735269 alsa_mixer-test_get_value_LCALTA_19 pass
2883 04:26:22.740349 alsa_mixer-test_name_LCALTA_19 pass
2884 04:26:22.745851 alsa_mixer-test_write_default_LCALTA_19 pass
2885 04:26:22.746331 alsa_mixer-test_write_valid_LCALTA_19 pass
2886 04:26:22.751454 alsa_mixer-test_write_invalid_LCALTA_19 pass
2887 04:26:22.756921 alsa_mixer-test_event_missing_LCALTA_19 pass
2888 04:26:22.762496 alsa_mixer-test_event_spurious_LCALTA_19 pass
2889 04:26:22.762964 alsa_mixer-test_get_value_LCALTA_18 pass
2890 04:26:22.768127 alsa_mixer-test_name_LCALTA_18 pass
2891 04:26:22.773585 alsa_mixer-test_write_default_LCALTA_18 pass
2892 04:26:22.774052 alsa_mixer-test_write_valid_LCALTA_18 pass
2893 04:26:22.779130 alsa_mixer-test_write_invalid_LCALTA_18 pass
2894 04:26:22.784673 alsa_mixer-test_event_missing_LCALTA_18 pass
2895 04:26:22.785136 alsa_mixer-test_event_spurious_LCALTA_18 pass
2896 04:26:22.790224 alsa_mixer-test_get_value_LCALTA_17 pass
2897 04:26:22.795792 alsa_mixer-test_name_LCALTA_17 pass
2898 04:26:22.796291 alsa_mixer-test_write_default_LCALTA_17 pass
2899 04:26:22.801307 alsa_mixer-test_write_valid_LCALTA_17 pass
2900 04:26:22.806846 alsa_mixer-test_write_invalid_LCALTA_17 pass
2901 04:26:22.812401 alsa_mixer-test_event_missing_LCALTA_17 pass
2902 04:26:22.812861 alsa_mixer-test_event_spurious_LCALTA_17 pass
2903 04:26:22.817927 alsa_mixer-test_get_value_LCALTA_16 pass
2904 04:26:22.818390 alsa_mixer-test_name_LCALTA_16 pass
2905 04:26:22.823493 alsa_mixer-test_write_default_LCALTA_16 pass
2906 04:26:22.829050 alsa_mixer-test_write_valid_LCALTA_16 pass
2907 04:26:22.834563 alsa_mixer-test_write_invalid_LCALTA_16 pass
2908 04:26:22.835027 alsa_mixer-test_event_missing_LCALTA_16 pass
2909 04:26:22.840147 alsa_mixer-test_event_spurious_LCALTA_16 pass
2910 04:26:22.845671 alsa_mixer-test_get_value_LCALTA_15 pass
2911 04:26:22.846137 alsa_mixer-test_name_LCALTA_15 pass
2912 04:26:22.851266 alsa_mixer-test_write_default_LCALTA_15 pass
2913 04:26:22.856811 alsa_mixer-test_write_valid_LCALTA_15 pass
2914 04:26:22.857272 alsa_mixer-test_write_invalid_LCALTA_15 pass
2915 04:26:22.862328 alsa_mixer-test_event_missing_LCALTA_15 pass
2916 04:26:22.867862 alsa_mixer-test_event_spurious_LCALTA_15 pass
2917 04:26:22.873418 alsa_mixer-test_get_value_LCALTA_14 pass
2918 04:26:22.873884 alsa_mixer-test_name_LCALTA_14 pass
2919 04:26:22.878963 alsa_mixer-test_write_default_LCALTA_14 pass
2920 04:26:22.884597 alsa_mixer-test_write_valid_LCALTA_14 pass
2921 04:26:22.885057 alsa_mixer-test_write_invalid_LCALTA_14 pass
2922 04:26:22.890066 alsa_mixer-test_event_missing_LCALTA_14 pass
2923 04:26:22.895610 alsa_mixer-test_event_spurious_LCALTA_14 pass
2924 04:26:22.896115 alsa_mixer-test_get_value_LCALTA_13 pass
2925 04:26:22.901150 alsa_mixer-test_name_LCALTA_13 pass
2926 04:26:22.906682 alsa_mixer-test_write_default_LCALTA_13 pass
2927 04:26:22.907146 alsa_mixer-test_write_valid_LCALTA_13 pass
2928 04:26:22.912257 alsa_mixer-test_write_invalid_LCALTA_13 pass
2929 04:26:22.917800 alsa_mixer-test_event_missing_LCALTA_13 pass
2930 04:26:22.918265 alsa_mixer-test_event_spurious_LCALTA_13 pass
2931 04:26:22.923331 alsa_mixer-test_get_value_LCALTA_12 pass
2932 04:26:22.928863 alsa_mixer-test_name_LCALTA_12 pass
2933 04:26:22.929329 alsa_mixer-test_write_default_LCALTA_12 pass
2934 04:26:22.934418 alsa_mixer-test_write_valid_LCALTA_12 pass
2935 04:26:22.939958 alsa_mixer-test_write_invalid_LCALTA_12 pass
2936 04:26:22.945502 alsa_mixer-test_event_missing_LCALTA_12 pass
2937 04:26:22.945973 alsa_mixer-test_event_spurious_LCALTA_12 pass
2938 04:26:22.951097 alsa_mixer-test_get_value_LCALTA_11 pass
2939 04:26:22.956601 alsa_mixer-test_name_LCALTA_11 pass
2940 04:26:22.957070 alsa_mixer-test_write_default_LCALTA_11 pass
2941 04:26:22.962137 alsa_mixer-test_write_valid_LCALTA_11 pass
2942 04:26:22.967693 alsa_mixer-test_write_invalid_LCALTA_11 pass
2943 04:26:22.968200 alsa_mixer-test_event_missing_LCALTA_11 pass
2944 04:26:22.973281 alsa_mixer-test_event_spurious_LCALTA_11 pass
2945 04:26:22.978837 alsa_mixer-test_get_value_LCALTA_10 pass
2946 04:26:22.979325 alsa_mixer-test_name_LCALTA_10 pass
2947 04:26:22.984355 alsa_mixer-test_write_default_LCALTA_10 pass
2948 04:26:22.989884 alsa_mixer-test_write_valid_LCALTA_10 pass
2949 04:26:22.990348 alsa_mixer-test_write_invalid_LCALTA_10 pass
2950 04:26:22.995440 alsa_mixer-test_event_missing_LCALTA_10 pass
2951 04:26:23.000989 alsa_mixer-test_event_spurious_LCALTA_10 pass
2952 04:26:23.006545 alsa_mixer-test_get_value_LCALTA_9 pass
2953 04:26:23.007008 alsa_mixer-test_name_LCALTA_9 pass
2954 04:26:23.012083 alsa_mixer-test_write_default_LCALTA_9 pass
2955 04:26:23.017629 alsa_mixer-test_write_valid_LCALTA_9 pass
2956 04:26:23.018096 alsa_mixer-test_write_invalid_LCALTA_9 pass
2957 04:26:23.023192 alsa_mixer-test_event_missing_LCALTA_9 pass
2958 04:26:23.028740 alsa_mixer-test_event_spurious_LCALTA_9 pass
2959 04:26:23.029230 alsa_mixer-test_get_value_LCALTA_8 pass
2960 04:26:23.034272 alsa_mixer-test_name_LCALTA_8 pass
2961 04:26:23.039813 alsa_mixer-test_write_default_LCALTA_8 pass
2962 04:26:23.040304 alsa_mixer-test_write_valid_LCALTA_8 pass
2963 04:26:23.045354 alsa_mixer-test_write_invalid_LCALTA_8 pass
2964 04:26:23.050952 alsa_mixer-test_event_missing_LCALTA_8 pass
2965 04:26:23.051442 alsa_mixer-test_event_spurious_LCALTA_8 pass
2966 04:26:23.056469 alsa_mixer-test_get_value_LCALTA_7 pass
2967 04:26:23.062013 alsa_mixer-test_name_LCALTA_7 pass
2968 04:26:23.062485 alsa_mixer-test_write_default_LCALTA_7 pass
2969 04:26:23.067563 alsa_mixer-test_write_valid_LCALTA_7 pass
2970 04:26:23.073117 alsa_mixer-test_write_invalid_LCALTA_7 pass
2971 04:26:23.073585 alsa_mixer-test_event_missing_LCALTA_7 pass
2972 04:26:23.078653 alsa_mixer-test_event_spurious_LCALTA_7 pass
2973 04:26:23.084240 alsa_mixer-test_get_value_LCALTA_6 pass
2974 04:26:23.084708 alsa_mixer-test_name_LCALTA_6 pass
2975 04:26:23.089748 alsa_mixer-test_write_default_LCALTA_6 pass
2976 04:26:23.095287 alsa_mixer-test_write_valid_LCALTA_6 pass
2977 04:26:23.095751 alsa_mixer-test_write_invalid_LCALTA_6 pass
2978 04:26:23.100833 alsa_mixer-test_event_missing_LCALTA_6 pass
2979 04:26:23.106375 alsa_mixer-test_event_spurious_LCALTA_6 pass
2980 04:26:23.106840 alsa_mixer-test_get_value_LCALTA_5 pass
2981 04:26:23.111916 alsa_mixer-test_name_LCALTA_5 pass
2982 04:26:23.117478 alsa_mixer-test_write_default_LCALTA_5 pass
2983 04:26:23.117963 alsa_mixer-test_write_valid_LCALTA_5 pass
2984 04:26:23.123016 alsa_mixer-test_write_invalid_LCALTA_5 pass
2985 04:26:23.128567 alsa_mixer-test_event_missing_LCALTA_5 pass
2986 04:26:23.129056 alsa_mixer-test_event_spurious_LCALTA_5 pass
2987 04:26:23.134116 alsa_mixer-test_get_value_LCALTA_4 pass
2988 04:26:23.139694 alsa_mixer-test_name_LCALTA_4 pass
2989 04:26:23.140185 alsa_mixer-test_write_default_LCALTA_4 pass
2990 04:26:23.145203 alsa_mixer-test_write_valid_LCALTA_4 pass
2991 04:26:23.150817 alsa_mixer-test_write_invalid_LCALTA_4 pass
2992 04:26:23.151319 alsa_mixer-test_event_missing_LCALTA_4 pass
2993 04:26:23.156326 alsa_mixer-test_event_spurious_LCALTA_4 pass
2994 04:26:23.161841 alsa_mixer-test_get_value_LCALTA_3 pass
2995 04:26:23.162319 alsa_mixer-test_name_LCALTA_3 pass
2996 04:26:23.167384 alsa_mixer-test_write_default_LCALTA_3 pass
2997 04:26:23.172937 alsa_mixer-test_write_valid_LCALTA_3 pass
2998 04:26:23.173407 alsa_mixer-test_write_invalid_LCALTA_3 pass
2999 04:26:23.178481 alsa_mixer-test_event_missing_LCALTA_3 pass
3000 04:26:23.184022 alsa_mixer-test_event_spurious_LCALTA_3 pass
3001 04:26:23.184494 alsa_mixer-test_get_value_LCALTA_2 pass
3002 04:26:23.189573 alsa_mixer-test_name_LCALTA_2 pass
3003 04:26:23.195141 alsa_mixer-test_write_default_LCALTA_2 pass
3004 04:26:23.195623 alsa_mixer-test_write_valid_LCALTA_2 pass
3005 04:26:23.200674 alsa_mixer-test_write_invalid_LCALTA_2 pass
3006 04:26:23.206233 alsa_mixer-test_event_missing_LCALTA_2 pass
3007 04:26:23.211760 alsa_mixer-test_event_spurious_LCALTA_2 pass
3008 04:26:23.212274 alsa_mixer-test_get_value_LCALTA_1 pass
3009 04:26:23.217346 alsa_mixer-test_name_LCALTA_1 pass
3010 04:26:23.217839 alsa_mixer-test_write_default_LCALTA_1 pass
3011 04:26:23.222870 alsa_mixer-test_write_valid_LCALTA_1 pass
3012 04:26:23.228400 alsa_mixer-test_write_invalid_LCALTA_1 pass
3013 04:26:23.233951 alsa_mixer-test_event_missing_LCALTA_1 pass
3014 04:26:23.234434 alsa_mixer-test_event_spurious_LCALTA_1 pass
3015 04:26:23.239546 alsa_mixer-test_get_value_LCALTA_0 pass
3016 04:26:23.240083 alsa_mixer-test_name_LCALTA_0 pass
3017 04:26:23.245093 alsa_mixer-test_write_default_LCALTA_0 pass
3018 04:26:23.250644 alsa_mixer-test_write_valid_LCALTA_0 pass
3019 04:26:23.256226 alsa_mixer-test_write_invalid_LCALTA_0 pass
3020 04:26:23.256706 alsa_mixer-test_event_missing_LCALTA_0 pass
3021 04:26:23.261645 alsa_mixer-test_event_spurious_LCALTA_0 pass
3022 04:26:23.262105 alsa_mixer-test pass
3023 04:26:23.267186 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
3024 04:26:23.272747 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
3025 04:26:23.278278 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
3026 04:26:23.283818 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
3027 04:26:23.284302 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
3028 04:26:23.289408 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
3029 04:26:23.294969 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
3030 04:26:23.300488 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
3031 04:26:23.306032 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
3032 04:26:23.311595 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
3033 04:26:23.312084 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
3034 04:26:23.317150 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
3035 04:26:23.322671 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
3036 04:26:23.328249 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
3037 04:26:23.333766 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
3038 04:26:23.339297 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
3039 04:26:23.339746 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
3040 04:26:23.344867 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
3041 04:26:23.350405 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
3042 04:26:23.356049 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
3043 04:26:23.361499 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
3044 04:26:23.367028 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
3045 04:26:23.367482 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
3046 04:26:23.372634 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
3047 04:26:23.378144 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
3048 04:26:23.383714 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
3049 04:26:23.389260 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
3050 04:26:23.394871 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
3051 04:26:23.395333 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
3052 04:26:23.400333 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
3053 04:26:23.405894 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
3054 04:26:23.411425 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
3055 04:26:23.417103 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
3056 04:26:23.422528 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
3057 04:26:23.428112 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
3058 04:26:23.428587 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
3059 04:26:23.433599 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
3060 04:26:23.439122 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
3061 04:26:23.444728 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
3062 04:26:23.450253 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
3063 04:26:23.455910 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
3064 04:26:23.456422 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
3065 04:26:23.461346 alsa_pcm-test pass
3066 04:26:23.466902 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3067 04:26:23.477960 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3068 04:26:23.483537 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3069 04:26:23.494601 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3070 04:26:23.500242 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3071 04:26:23.505842 alsa_test-pcmtest-driver pass
3072 04:26:23.511333 alsa_utimer-test_global_wrong_timers_test pass
3073 04:26:23.511818 alsa_utimer-test_timer_f_utimer fail
3074 04:26:23.516934 alsa_utimer-test fail
3075 04:26:23.517416 + ../../utils/send-to-lava.sh ./output/result.txt
3076 04:26:23.522416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
3077 04:26:23.523343 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
3079 04:26:23.533419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
3080 04:26:23.534230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
3082 04:26:23.539273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
3083 04:26:23.540085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
3085 04:26:23.552530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
3086 04:26:23.553393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
3088 04:26:23.605213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
3089 04:26:23.606084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
3091 04:26:23.648220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
3092 04:26:23.649002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
3094 04:26:23.700241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
3095 04:26:23.701021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
3097 04:26:23.757211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
3098 04:26:23.757982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
3100 04:26:23.806672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
3101 04:26:23.807423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
3103 04:26:23.859613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
3104 04:26:23.860408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
3106 04:26:23.910742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
3107 04:26:23.911483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
3109 04:26:23.961501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
3110 04:26:23.962254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
3112 04:26:24.012817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
3113 04:26:24.013559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
3115 04:26:24.056329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
3116 04:26:24.057116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
3118 04:26:24.106347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
3119 04:26:24.107090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
3121 04:26:24.157812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
3122 04:26:24.158675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
3124 04:26:24.210477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
3125 04:26:24.211085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
3127 04:26:24.265702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
3128 04:26:24.266570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
3130 04:26:24.315774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
3131 04:26:24.316593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
3133 04:26:24.361314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
3134 04:26:24.362103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
3136 04:26:24.411473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
3137 04:26:24.412289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
3139 04:26:24.462585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
3140 04:26:24.463391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
3142 04:26:24.506378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
3143 04:26:24.507137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
3145 04:26:24.550415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
3146 04:26:24.551199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
3148 04:26:24.596108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
3149 04:26:24.596892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
3151 04:26:24.650138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3152 04:26:24.650874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3154 04:26:24.697372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3155 04:26:24.698147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3157 04:26:24.740349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3158 04:26:24.741117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3160 04:26:24.786084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3161 04:26:24.786984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3163 04:26:24.837159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3164 04:26:24.837972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3166 04:26:24.889128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3167 04:26:24.889899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3169 04:26:24.941172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3170 04:26:24.941935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3172 04:26:24.990400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3173 04:26:24.991141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3175 04:26:25.042437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3176 04:26:25.043244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3178 04:26:25.088156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3179 04:26:25.088887 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3181 04:26:25.140975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3182 04:26:25.141703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3184 04:26:25.193939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3185 04:26:25.194643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3187 04:26:25.247243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3188 04:26:25.247968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3190 04:26:25.291526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3191 04:26:25.292310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3193 04:26:25.341755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3194 04:26:25.342461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3196 04:26:25.396247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3197 04:26:25.396955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3199 04:26:25.441058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3200 04:26:25.441817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3202 04:26:25.484705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3203 04:26:25.485413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3205 04:26:25.528207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3206 04:26:25.528935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3208 04:26:25.571847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3209 04:26:25.572633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3211 04:26:25.617514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3212 04:26:25.618232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3214 04:26:25.663267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3215 04:26:25.663969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3217 04:26:25.711940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3218 04:26:25.712675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3220 04:26:25.756649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3221 04:26:25.757365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3223 04:26:25.801512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3224 04:26:25.802228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3226 04:26:25.847663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3227 04:26:25.848426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3229 04:26:25.892930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3230 04:26:25.893630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3232 04:26:25.939536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3233 04:26:25.940272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3235 04:26:25.983385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3236 04:26:25.984084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3238 04:26:26.035321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3239 04:26:26.036147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3241 04:26:26.080802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3242 04:26:26.081535 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3244 04:26:26.132146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3245 04:26:26.132856 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3247 04:26:26.181674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3248 04:26:26.182372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3250 04:26:26.231730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3251 04:26:26.232483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3253 04:26:26.289035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3254 04:26:26.289754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3256 04:26:26.347255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3257 04:26:26.347972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3259 04:26:26.400702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3260 04:26:26.401429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3262 04:26:26.451794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3263 04:26:26.452562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3265 04:26:26.507071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3266 04:26:26.507839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3268 04:26:26.561576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3269 04:26:26.562318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3271 04:26:26.606009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3272 04:26:26.606792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3274 04:26:26.659196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3275 04:26:26.660012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3277 04:26:26.731714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3278 04:26:26.732535 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3280 04:26:26.787546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3281 04:26:26.788442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3283 04:26:26.847839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3284 04:26:26.848516 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3286 04:26:26.904900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3287 04:26:26.905539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3289 04:26:26.960781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3290 04:26:26.961439 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3292 04:26:27.020954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3293 04:26:27.021620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3295 04:26:27.077052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3296 04:26:27.078016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3298 04:26:27.138073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3299 04:26:27.138944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3301 04:26:27.187658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3302 04:26:27.188573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3304 04:26:27.348373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3305 04:26:27.349250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3307 04:26:27.397525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3308 04:26:27.398320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3310 04:26:27.444070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3311 04:26:27.444872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3313 04:26:27.499836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3314 04:26:27.500642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3316 04:26:27.544892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3317 04:26:27.545787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3319 04:26:27.596997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3320 04:26:27.597928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3322 04:26:27.650169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3323 04:26:27.651054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3325 04:26:27.696535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3326 04:26:27.697385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3328 04:26:27.741692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3329 04:26:27.742533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3331 04:26:27.789223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3332 04:26:27.790099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3334 04:26:27.836252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3335 04:26:27.837062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3337 04:26:27.882443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3338 04:26:27.883288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3340 04:26:27.929316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3341 04:26:27.930154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3343 04:26:27.973490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3344 04:26:27.974355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3346 04:26:28.025454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3347 04:26:28.026382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3349 04:26:28.079697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3350 04:26:28.080593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3352 04:26:28.130408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3353 04:26:28.131251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3355 04:26:28.184014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3356 04:26:28.184851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3358 04:26:28.245018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3359 04:26:28.245860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3361 04:26:28.295153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3362 04:26:28.296053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3364 04:26:28.343542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3365 04:26:28.344416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3367 04:26:28.388278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3368 04:26:28.389157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3370 04:26:28.436512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3371 04:26:28.437398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3373 04:26:28.485947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3374 04:26:28.486794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3376 04:26:28.532543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3377 04:26:28.533439 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3379 04:26:28.580579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3380 04:26:28.581516 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3382 04:26:28.640383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3383 04:26:28.641209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3385 04:26:28.685964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3386 04:26:28.686804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3388 04:26:28.733442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3389 04:26:28.734265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3391 04:26:28.784906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3392 04:26:28.785864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3394 04:26:28.832100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3395 04:26:28.832959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3397 04:26:28.883941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3398 04:26:28.884796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3400 04:26:28.932557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3401 04:26:28.933400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3403 04:26:28.987883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3404 04:26:28.988787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3406 04:26:29.041428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3407 04:26:29.042319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3409 04:26:29.087676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3410 04:26:29.088669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3412 04:26:29.142900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3413 04:26:29.143753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3415 04:26:29.187780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3416 04:26:29.188633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3418 04:26:29.239790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3419 04:26:29.240589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3421 04:26:29.288571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3422 04:26:29.289377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3424 04:26:29.333508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3425 04:26:29.334259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3427 04:26:29.387004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3428 04:26:29.387859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3430 04:26:29.435242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3431 04:26:29.436106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3433 04:26:29.480642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3434 04:26:29.481407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3436 04:26:29.526398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3437 04:26:29.527252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3439 04:26:29.582167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3440 04:26:29.583137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3442 04:26:29.641940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3443 04:26:29.642784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3445 04:26:29.692960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3446 04:26:29.693779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3448 04:26:29.748230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3449 04:26:29.749050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3451 04:26:29.802794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3452 04:26:29.803633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3454 04:26:29.866581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3455 04:26:29.867401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3457 04:26:29.917190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3458 04:26:29.918075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3460 04:26:29.971762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3461 04:26:29.972665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3463 04:26:30.028973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3464 04:26:30.029871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3466 04:26:30.083796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3467 04:26:30.084705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3469 04:26:30.137409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3470 04:26:30.138239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3472 04:26:30.193436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3473 04:26:30.194267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3475 04:26:30.252160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3476 04:26:30.252992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3478 04:26:30.309541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3479 04:26:30.310379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3481 04:26:30.363137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3482 04:26:30.364083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3484 04:26:30.412990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3485 04:26:30.414002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3487 04:26:30.464528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3488 04:26:30.465387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3490 04:26:30.509779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3491 04:26:30.510657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3493 04:26:30.555789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3494 04:26:30.556743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3496 04:26:30.608246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3497 04:26:30.609113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3499 04:26:30.653100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3500 04:26:30.653901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3502 04:26:30.698397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3503 04:26:30.699190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3505 04:26:30.748746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3506 04:26:30.749497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3508 04:26:30.803902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3509 04:26:30.804741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3511 04:26:30.861332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3512 04:26:30.862078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3514 04:26:30.906171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3515 04:26:30.906958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3517 04:26:30.951748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3518 04:26:30.952533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3520 04:26:31.002249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3521 04:26:31.003046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3523 04:26:31.056080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3524 04:26:31.056854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3526 04:26:31.105733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3527 04:26:31.106533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3529 04:26:31.161234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3530 04:26:31.161994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3532 04:26:31.213333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3533 04:26:31.214128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3535 04:26:31.257935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3536 04:26:31.258683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3538 04:26:31.304884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3539 04:26:31.305678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3541 04:26:31.352477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3542 04:26:31.353222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3544 04:26:31.404036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3545 04:26:31.404872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3547 04:26:31.461367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3548 04:26:31.462235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3550 04:26:31.518943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3551 04:26:31.519783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3553 04:26:31.577107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3554 04:26:31.577897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3556 04:26:31.638137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3557 04:26:31.638980 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3559 04:26:31.689519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3560 04:26:31.690277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3562 04:26:31.738624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3563 04:26:31.739424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3565 04:26:31.792929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3566 04:26:31.793689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3568 04:26:31.842496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3569 04:26:31.843285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3571 04:26:31.890930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3572 04:26:31.891676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3574 04:26:31.938544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3575 04:26:31.939325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3577 04:26:31.991243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3578 04:26:31.992018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3580 04:26:32.041202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3581 04:26:32.042041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3583 04:26:32.088673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3584 04:26:32.089421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3586 04:26:32.134291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3587 04:26:32.135082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3589 04:26:32.184506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3590 04:26:32.185253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3592 04:26:32.236278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3593 04:26:32.237074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3595 04:26:32.286938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3596 04:26:32.287695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3598 04:26:32.345392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3599 04:26:32.346183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3601 04:26:32.392768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3602 04:26:32.393557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3604 04:26:32.440587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3605 04:26:32.441469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3607 04:26:32.484789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3608 04:26:32.485532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3610 04:26:32.555293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3611 04:26:32.556252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3613 04:26:32.613971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3614 04:26:32.614932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3616 04:26:32.662658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3617 04:26:32.663611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3619 04:26:32.716835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3620 04:26:32.717565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3622 04:26:32.788715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3623 04:26:32.789395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3625 04:26:32.842569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3626 04:26:32.843218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3628 04:26:32.894104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3629 04:26:32.894628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3631 04:26:32.945035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3632 04:26:32.945561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3634 04:26:32.990901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3635 04:26:32.991423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3637 04:26:33.055525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3638 04:26:33.056133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3640 04:26:33.110132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3641 04:26:33.110643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3643 04:26:33.167491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3644 04:26:33.168034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3646 04:26:33.217901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3647 04:26:33.218433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3649 04:26:33.270275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3650 04:26:33.271581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3652 04:26:33.324703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3653 04:26:33.325540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3655 04:26:33.379248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3656 04:26:33.380116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3658 04:26:33.425408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3659 04:26:33.426298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3661 04:26:33.470970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3662 04:26:33.471824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3664 04:26:33.522833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3665 04:26:33.523700 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3667 04:26:33.569859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3668 04:26:33.570918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3670 04:26:33.632564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3671 04:26:33.633473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3673 04:26:33.678188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3674 04:26:33.679183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3676 04:26:33.731660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3677 04:26:33.732570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3679 04:26:33.787682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3680 04:26:33.788592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3682 04:26:33.845079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3683 04:26:33.846119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3685 04:26:33.897209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3686 04:26:33.898087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3688 04:26:33.942403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3689 04:26:33.943313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3691 04:26:34.001055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3692 04:26:34.001894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3694 04:26:34.054877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3695 04:26:34.055702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3697 04:26:34.110009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3698 04:26:34.110819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3700 04:26:34.157066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3701 04:26:34.157862 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3703 04:26:34.209102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3704 04:26:34.209948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3706 04:26:34.262667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3707 04:26:34.263457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3709 04:26:34.318264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3710 04:26:34.319073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3712 04:26:34.370201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3713 04:26:34.370997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3715 04:26:34.426252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3716 04:26:34.427096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3718 04:26:34.476997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3719 04:26:34.477797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3721 04:26:34.527129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3722 04:26:34.528034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3724 04:26:34.572207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3725 04:26:34.573011 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3727 04:26:34.625394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3728 04:26:34.626241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3730 04:26:34.674898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3731 04:26:34.675685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3733 04:26:34.729470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3734 04:26:34.730305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3736 04:26:34.773845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3737 04:26:34.774670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3739 04:26:34.818782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3740 04:26:34.819608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3742 04:26:34.862519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3743 04:26:34.863314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3745 04:26:34.915688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3746 04:26:34.916535 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3748 04:26:34.972206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3749 04:26:34.972999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3751 04:26:35.017135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3752 04:26:35.017917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3754 04:26:35.071752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3755 04:26:35.072631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3757 04:26:35.136342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3758 04:26:35.137134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3760 04:26:35.183357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3761 04:26:35.184105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3763 04:26:35.230554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3764 04:26:35.231359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3766 04:26:35.288875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3767 04:26:35.289652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3769 04:26:35.341587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3770 04:26:35.342368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3772 04:26:35.396566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3773 04:26:35.397332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3775 04:26:35.451307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3776 04:26:35.452091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3778 04:26:35.505008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3779 04:26:35.505782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3781 04:26:35.551801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3782 04:26:35.552637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3784 04:26:35.600547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3785 04:26:35.601148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3787 04:26:35.653124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3788 04:26:35.653910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3790 04:26:35.708826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3791 04:26:35.709595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3793 04:26:35.763402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3794 04:26:35.764165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3796 04:26:35.813456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3797 04:26:35.814262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3799 04:26:35.861251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3800 04:26:35.862087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3802 04:26:35.917897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3803 04:26:35.918684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3805 04:26:35.968603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3806 04:26:35.969393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3808 04:26:36.018500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3809 04:26:36.019289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3811 04:26:36.065296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3812 04:26:36.066088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3814 04:26:36.115253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3815 04:26:36.116061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3817 04:26:36.159864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3818 04:26:36.160718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3820 04:26:36.206883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3821 04:26:36.207680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3823 04:26:36.255929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3824 04:26:36.256772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3826 04:26:36.306354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3827 04:26:36.307164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3829 04:26:36.357722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3830 04:26:36.358516 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3832 04:26:36.415033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3833 04:26:36.415849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3835 04:26:36.464528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3836 04:26:36.465308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3838 04:26:36.517633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3839 04:26:36.518261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3841 04:26:36.566689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3842 04:26:36.567346 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3844 04:26:36.612101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3845 04:26:36.612871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3847 04:26:36.658137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3848 04:26:36.658911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3850 04:26:36.708864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3851 04:26:36.709651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3853 04:26:36.760863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3854 04:26:36.761644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3856 04:26:36.811572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3857 04:26:36.812430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3859 04:26:36.856830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3860 04:26:36.857622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3862 04:26:36.903091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3863 04:26:36.903906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3865 04:26:36.960771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3866 04:26:36.961556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3868 04:26:37.020806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3869 04:26:37.021587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3871 04:26:37.080253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3872 04:26:37.081061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3874 04:26:37.125115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3875 04:26:37.125882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3877 04:26:37.176655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3878 04:26:37.177434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3880 04:26:37.221593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3881 04:26:37.222392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3883 04:26:37.269187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3884 04:26:37.269963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3886 04:26:37.315790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3887 04:26:37.316628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3889 04:26:37.367056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3890 04:26:37.367810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3892 04:26:37.415627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3893 04:26:37.416454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3895 04:26:37.462856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3896 04:26:37.463626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3898 04:26:37.513956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3899 04:26:37.514561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3901 04:26:37.567219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3902 04:26:37.567846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3904 04:26:37.622887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3905 04:26:37.623668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3907 04:26:37.677740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3908 04:26:37.678500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3910 04:26:37.730583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3911 04:26:37.731346 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3913 04:26:37.781978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3914 04:26:37.782791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3916 04:26:37.829861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3917 04:26:37.830408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3919 04:26:37.882979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3920 04:26:37.883774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3922 04:26:37.944735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3923 04:26:37.945588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3925 04:26:38.007819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3926 04:26:38.008666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3928 04:26:38.057253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3929 04:26:38.058021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3931 04:26:38.110505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3932 04:26:38.111249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3934 04:26:38.165973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3935 04:26:38.166718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3937 04:26:38.217888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3938 04:26:38.218679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3940 04:26:38.263125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3941 04:26:38.263874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3943 04:26:38.315546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3944 04:26:38.316334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3946 04:26:38.372351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3947 04:26:38.373159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3949 04:26:38.417284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3950 04:26:38.418041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3952 04:26:38.463705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3953 04:26:38.464484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3955 04:26:38.520009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3956 04:26:38.520596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3958 04:26:38.578230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3959 04:26:38.579092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3961 04:26:38.629907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3962 04:26:38.630715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3964 04:26:38.675429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3965 04:26:38.676213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3967 04:26:38.734476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3968 04:26:38.735237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3970 04:26:38.784541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3971 04:26:38.785312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3973 04:26:38.837149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3974 04:26:38.837900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3976 04:26:38.887933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3977 04:26:38.888711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3979 04:26:38.939077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3980 04:26:38.939818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3982 04:26:38.987389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3983 04:26:38.988136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3985 04:26:39.043564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3986 04:26:39.044429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3988 04:26:39.089658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3989 04:26:39.090396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3991 04:26:39.142271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3992 04:26:39.143005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3994 04:26:39.198140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3995 04:26:39.198957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3997 04:26:39.249552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3998 04:26:39.250368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
4000 04:26:39.296312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
4001 04:26:39.297116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
4003 04:26:39.348541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
4004 04:26:39.349391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
4006 04:26:39.394637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
4007 04:26:39.395548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
4009 04:26:39.452243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
4010 04:26:39.453243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
4012 04:26:39.502638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
4013 04:26:39.503479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
4015 04:26:39.548466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
4016 04:26:39.549346 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
4018 04:26:39.596076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
4019 04:26:39.597106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
4021 04:26:39.653605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
4022 04:26:39.654435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
4024 04:26:39.705602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
4025 04:26:39.706412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
4027 04:26:39.759687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
4028 04:26:39.760549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
4030 04:26:39.813265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
4031 04:26:39.814088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
4033 04:26:39.864046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
4034 04:26:39.864878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
4036 04:26:39.909350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
4037 04:26:39.910220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
4039 04:26:39.965820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
4040 04:26:39.966740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
4042 04:26:40.019103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
4043 04:26:40.019903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
4045 04:26:40.071285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
4046 04:26:40.072148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
4048 04:26:40.122251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
4049 04:26:40.123055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
4051 04:26:40.180811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
4052 04:26:40.181621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
4054 04:26:40.231427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
4055 04:26:40.232427 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
4057 04:26:40.276165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
4058 04:26:40.277027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
4060 04:26:40.323281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
4061 04:26:40.324095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
4063 04:26:40.377433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
4064 04:26:40.378201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
4066 04:26:40.421263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
4067 04:26:40.422035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
4069 04:26:40.480138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
4070 04:26:40.480886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
4072 04:26:40.541579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
4073 04:26:40.542375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
4075 04:26:40.587684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
4076 04:26:40.588513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
4078 04:26:40.641370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
4079 04:26:40.642119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
4081 04:26:40.685881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
4082 04:26:40.686620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
4084 04:26:40.741767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
4085 04:26:40.742540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
4087 04:26:40.793315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
4088 04:26:40.794088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
4090 04:26:40.837915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
4091 04:26:40.838655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
4093 04:26:40.901817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
4094 04:26:40.902601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
4096 04:26:40.956569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
4097 04:26:40.957319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
4099 04:26:41.006539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
4100 04:26:41.007277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
4102 04:26:41.063352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
4103 04:26:41.064141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
4105 04:26:41.106616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
4106 04:26:41.107352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
4108 04:26:41.158829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
4109 04:26:41.159568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
4111 04:26:41.218575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
4112 04:26:41.219338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
4114 04:26:41.270713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
4115 04:26:41.271467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
4117 04:26:41.320259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
4118 04:26:41.321020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
4120 04:26:41.370686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
4121 04:26:41.371428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
4123 04:26:41.417517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
4124 04:26:41.418298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
4126 04:26:41.473423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
4127 04:26:41.474168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
4129 04:26:41.527029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
4130 04:26:41.527793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
4132 04:26:41.571933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
4133 04:26:41.572755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
4135 04:26:41.625804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
4136 04:26:41.626553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
4138 04:26:41.670075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
4139 04:26:41.670813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
4141 04:26:41.716075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
4142 04:26:41.716824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
4144 04:26:41.775173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
4145 04:26:41.775912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
4147 04:26:41.825068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
4148 04:26:41.825844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
4150 04:26:41.871411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
4151 04:26:41.872152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4153 04:26:41.916834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4154 04:26:41.917560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4156 04:26:41.970005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4157 04:26:41.970736 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4159 04:26:42.026945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4160 04:26:42.027698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4162 04:26:42.072011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4163 04:26:42.072784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4165 04:26:42.132455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4166 04:26:42.133199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4168 04:26:42.188958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4169 04:26:42.189699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4171 04:26:42.233724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4172 04:26:42.234492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4174 04:26:42.288082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4175 04:26:42.288822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4177 04:26:42.333816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4178 04:26:42.334565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4180 04:26:42.386781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4181 04:26:42.387547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4183 04:26:42.434756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4184 04:26:42.435506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4186 04:26:42.480998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4187 04:26:42.481739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4189 04:26:42.526855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4190 04:26:42.527633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4192 04:26:42.582024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4193 04:26:42.582809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4195 04:26:42.631776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4196 04:26:42.632567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4198 04:26:42.677561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4199 04:26:42.678303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4201 04:26:42.728586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4202 04:26:42.729333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4204 04:26:42.779682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4205 04:26:42.780472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4207 04:26:42.824656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4208 04:26:42.825433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4210 04:26:42.876548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4211 04:26:42.877288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4213 04:26:42.927559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4214 04:26:42.928336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4216 04:26:42.982400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4217 04:26:42.983128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4219 04:26:43.027286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4220 04:26:43.028074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4222 04:26:43.085459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4223 04:26:43.086220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4225 04:26:43.131666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4226 04:26:43.132450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4228 04:26:43.177332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4229 04:26:43.178058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4231 04:26:43.224523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4232 04:26:43.225282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4234 04:26:43.268665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4235 04:26:43.269410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4237 04:26:43.326651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4238 04:26:43.327492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4240 04:26:43.384427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4241 04:26:43.385260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4243 04:26:43.431687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4244 04:26:43.432469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4246 04:26:43.489641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4247 04:26:43.490366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4249 04:26:43.536632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4250 04:26:43.537379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4252 04:26:43.600322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4253 04:26:43.601082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4255 04:26:43.651784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4256 04:26:43.652629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4258 04:26:43.709568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4259 04:26:43.710325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4261 04:26:43.762121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4262 04:26:43.762865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4264 04:26:43.810264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4265 04:26:43.811058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4267 04:26:43.863825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4268 04:26:43.864630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4270 04:26:43.919854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4271 04:26:43.920634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4273 04:26:43.973283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4274 04:26:43.974028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4276 04:26:44.019252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4277 04:26:44.020023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4279 04:26:44.064467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4280 04:26:44.065236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4282 04:26:44.117986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4283 04:26:44.118529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4285 04:26:44.168836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4286 04:26:44.169371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4288 04:26:44.229538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4289 04:26:44.230076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4291 04:26:44.274730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4292 04:26:44.275257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4294 04:26:44.322739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4295 04:26:44.323261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4297 04:26:44.365921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4298 04:26:44.366432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4300 04:26:44.410177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4301 04:26:44.410745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4303 04:26:44.458130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4304 04:26:44.458711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4306 04:26:44.512476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4307 04:26:44.513077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4309 04:26:44.566493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4310 04:26:44.567142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4312 04:26:44.612143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4313 04:26:44.612696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4315 04:26:44.658238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4316 04:26:44.659038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4318 04:26:44.703298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4319 04:26:44.704071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4321 04:26:44.747775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4322 04:26:44.748578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4324 04:26:44.792455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4325 04:26:44.793241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4327 04:26:44.844046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4328 04:26:44.844828 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4330 04:26:44.895592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4331 04:26:44.896401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4333 04:26:44.944715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4334 04:26:44.945499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4336 04:26:44.995297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4337 04:26:44.996084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4339 04:26:45.041044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4340 04:26:45.041850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4342 04:26:45.087146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4343 04:26:45.087941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4345 04:26:45.147344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4346 04:26:45.148133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4348 04:26:45.193492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4349 04:26:45.194279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4351 04:26:45.240419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4352 04:26:45.241203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4354 04:26:45.288232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4355 04:26:45.289020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4357 04:26:45.337266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4358 04:26:45.338046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4360 04:26:45.377762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4362 04:26:45.380749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4363 04:26:45.426795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4364 04:26:45.427630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4366 04:26:45.474006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4367 04:26:45.474819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4369 04:26:45.521155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4370 04:26:45.521979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4372 04:26:45.568286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4373 04:26:45.569143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4375 04:26:45.617430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4376 04:26:45.618233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4378 04:26:45.667510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4379 04:26:45.668340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4381 04:26:45.713477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4382 04:26:45.714262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4384 04:26:45.759922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4385 04:26:45.760743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4387 04:26:45.815702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4388 04:26:45.816576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4390 04:26:45.861164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4391 04:26:45.861970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4393 04:26:45.909113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4394 04:26:45.909901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4396 04:26:45.956369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4397 04:26:45.957177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4399 04:26:46.005783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4400 04:26:46.006578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4402 04:26:46.052445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4403 04:26:46.053250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4405 04:26:46.098185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4406 04:26:46.098966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4408 04:26:46.144925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4409 04:26:46.145710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4411 04:26:46.193973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4412 04:26:46.194747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4414 04:26:46.242010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4415 04:26:46.242780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4417 04:26:46.288267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4418 04:26:46.289036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4420 04:26:46.334410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4421 04:26:46.335269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4423 04:26:46.381459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4424 04:26:46.382284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4426 04:26:46.427683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4427 04:26:46.428539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4429 04:26:46.477881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4430 04:26:46.478653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4432 04:26:46.524961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4433 04:26:46.525806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4435 04:26:46.569506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4436 04:26:46.570307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4438 04:26:46.621978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4439 04:26:46.622752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4441 04:26:46.669051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4442 04:26:46.669839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4444 04:26:46.714681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4445 04:26:46.715451 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4447 04:26:46.761198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4448 04:26:46.761961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4450 04:26:46.811808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4451 04:26:46.812682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4453 04:26:46.858948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4454 04:26:46.859722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4456 04:26:46.906868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4457 04:26:46.907635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4459 04:26:46.953788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4460 04:26:46.954602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4462 04:26:47.000454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4463 04:26:47.001227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4465 04:26:47.046739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4466 04:26:47.047549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4468 04:26:47.093150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4469 04:26:47.093921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4471 04:26:47.141913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4472 04:26:47.142681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4474 04:26:47.190213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4475 04:26:47.191008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4477 04:26:47.236827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4478 04:26:47.237609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4480 04:26:47.289518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4481 04:26:47.290331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4483 04:26:47.340990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4484 04:26:47.341798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4486 04:26:47.388768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4487 04:26:47.389601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4489 04:26:47.433126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4490 04:26:47.433900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4492 04:26:47.488354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4493 04:26:47.489134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4495 04:26:47.540216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4496 04:26:47.541010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4498 04:26:47.590309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4499 04:26:47.591094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4501 04:26:47.636320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4502 04:26:47.637099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4504 04:26:47.687574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4505 04:26:47.688395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4507 04:26:47.729301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4508 04:26:47.730111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4510 04:26:47.776759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4511 04:26:47.777565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4513 04:26:47.822753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4514 04:26:47.823576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4516 04:26:47.867582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4518 04:26:47.872901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4519 04:26:47.873408 + set +x
4520 04:26:47.878893 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 950796_1.6.2.4.5>
4521 04:26:47.879386 <LAVA_TEST_RUNNER EXIT>
4522 04:26:47.880095 Received signal: <ENDRUN> 1_kselftest-alsa 950796_1.6.2.4.5
4523 04:26:47.880595 Ending use of test pattern.
4524 04:26:47.881054 Ending test lava.1_kselftest-alsa (950796_1.6.2.4.5), duration 41.00
4526 04:26:47.882746 ok: lava_test_shell seems to have completed
4527 04:26:47.907271 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4528 04:26:47.909198 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4529 04:26:47.909859 end: 3 lava-test-retry (duration 00:00:42) [common]
4530 04:26:47.910505 start: 4 finalize (timeout 00:06:02) [common]
4531 04:26:47.911140 start: 4.1 power-off (timeout 00:00:30) [common]
4532 04:26:47.912225 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4533 04:26:47.947952 >> OK - accepted request
4534 04:26:47.950025 Returned 0 in 0 seconds
4535 04:26:48.051248 end: 4.1 power-off (duration 00:00:00) [common]
4537 04:26:48.053129 start: 4.2 read-feedback (timeout 00:06:02) [common]
4538 04:26:48.054363 Listened to connection for namespace 'common' for up to 1s
4539 04:26:49.055160 Finalising connection for namespace 'common'
4540 04:26:49.055931 Disconnecting from shell: Finalise
4541 04:26:49.056617 / #
4542 04:26:49.157750 end: 4.2 read-feedback (duration 00:00:01) [common]
4543 04:26:49.158529 end: 4 finalize (duration 00:00:01) [common]
4544 04:26:49.159237 Cleaning after the job
4545 04:26:49.159872 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/ramdisk
4546 04:26:49.174643 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/kernel
4547 04:26:49.216771 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/dtb
4548 04:26:49.217541 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/nfsrootfs
4549 04:26:49.362600 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950796/tftp-deploy-xbqxmg97/modules
4550 04:26:49.370892 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950796
4551 04:26:52.451280 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950796
4552 04:26:52.451863 Job finished correctly