Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:27:30.142782 lava-dispatcher, installed at version: 2024.01
2 04:27:30.143565 start: 0 validate
3 04:27:30.144083 Start time: 2024-11-07 04:27:30.144052+00:00 (UTC)
4 04:27:30.144639 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:27:30.145181 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 04:27:30.190944 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:27:30.191504 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 04:27:30.224748 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:27:30.225387 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:27:30.258479 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:27:30.258994 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:27:30.291706 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 04:27:30.292224 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 04:27:30.338927 validate duration: 0.20
16 04:27:30.340913 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:27:30.341735 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:27:30.342547 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:27:30.343756 Not decompressing ramdisk as can be used compressed.
20 04:27:30.344793 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 04:27:30.345472 saving as /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/ramdisk/initrd.cpio.gz
22 04:27:30.346142 total size: 5628169 (5 MB)
23 04:27:30.390125 progress 0 % (0 MB)
24 04:27:30.397634 progress 5 % (0 MB)
25 04:27:30.405450 progress 10 % (0 MB)
26 04:27:30.412439 progress 15 % (0 MB)
27 04:27:30.420436 progress 20 % (1 MB)
28 04:27:30.425821 progress 25 % (1 MB)
29 04:27:30.429912 progress 30 % (1 MB)
30 04:27:30.433903 progress 35 % (1 MB)
31 04:27:30.437482 progress 40 % (2 MB)
32 04:27:30.441425 progress 45 % (2 MB)
33 04:27:30.445161 progress 50 % (2 MB)
34 04:27:30.449112 progress 55 % (2 MB)
35 04:27:30.453054 progress 60 % (3 MB)
36 04:27:30.456599 progress 65 % (3 MB)
37 04:27:30.460522 progress 70 % (3 MB)
38 04:27:30.464037 progress 75 % (4 MB)
39 04:27:30.468004 progress 80 % (4 MB)
40 04:27:30.471524 progress 85 % (4 MB)
41 04:27:30.475614 progress 90 % (4 MB)
42 04:27:30.479387 progress 95 % (5 MB)
43 04:27:30.482705 progress 100 % (5 MB)
44 04:27:30.483373 5 MB downloaded in 0.14 s (39.11 MB/s)
45 04:27:30.483910 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:27:30.484840 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:27:30.485137 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:27:30.485410 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:27:30.485865 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/kernel/Image
51 04:27:30.486131 saving as /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/kernel/Image
52 04:27:30.486345 total size: 45713920 (43 MB)
53 04:27:30.486556 No compression specified
54 04:27:30.525953 progress 0 % (0 MB)
55 04:27:30.554770 progress 5 % (2 MB)
56 04:27:30.583869 progress 10 % (4 MB)
57 04:27:30.613172 progress 15 % (6 MB)
58 04:27:30.641873 progress 20 % (8 MB)
59 04:27:30.670554 progress 25 % (10 MB)
60 04:27:30.699367 progress 30 % (13 MB)
61 04:27:30.728065 progress 35 % (15 MB)
62 04:27:30.757153 progress 40 % (17 MB)
63 04:27:30.785821 progress 45 % (19 MB)
64 04:27:30.814890 progress 50 % (21 MB)
65 04:27:30.844008 progress 55 % (24 MB)
66 04:27:30.872944 progress 60 % (26 MB)
67 04:27:30.902031 progress 65 % (28 MB)
68 04:27:30.930881 progress 70 % (30 MB)
69 04:27:30.959959 progress 75 % (32 MB)
70 04:27:30.989041 progress 80 % (34 MB)
71 04:27:31.017476 progress 85 % (37 MB)
72 04:27:31.046800 progress 90 % (39 MB)
73 04:27:31.075746 progress 95 % (41 MB)
74 04:27:31.104690 progress 100 % (43 MB)
75 04:27:31.105223 43 MB downloaded in 0.62 s (70.45 MB/s)
76 04:27:31.105699 end: 1.2.1 http-download (duration 00:00:01) [common]
78 04:27:31.106529 end: 1.2 download-retry (duration 00:00:01) [common]
79 04:27:31.106804 start: 1.3 download-retry (timeout 00:09:59) [common]
80 04:27:31.107072 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 04:27:31.107553 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 04:27:31.107828 saving as /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/dtb/meson-g12b-a311d-libretech-cc.dtb
83 04:27:31.108063 total size: 54703 (0 MB)
84 04:27:31.108281 No compression specified
85 04:27:31.152977 progress 59 % (0 MB)
86 04:27:31.153818 progress 100 % (0 MB)
87 04:27:31.154370 0 MB downloaded in 0.05 s (1.13 MB/s)
88 04:27:31.154854 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:27:31.155677 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:27:31.155937 start: 1.4 download-retry (timeout 00:09:59) [common]
92 04:27:31.156253 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 04:27:31.156718 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 04:27:31.156967 saving as /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/nfsrootfs/full.rootfs.tar
95 04:27:31.157172 total size: 120894716 (115 MB)
96 04:27:31.157381 Using unxz to decompress xz
97 04:27:31.200059 progress 0 % (0 MB)
98 04:27:31.987899 progress 5 % (5 MB)
99 04:27:32.825710 progress 10 % (11 MB)
100 04:27:33.616665 progress 15 % (17 MB)
101 04:27:34.358024 progress 20 % (23 MB)
102 04:27:35.057979 progress 25 % (28 MB)
103 04:27:35.980224 progress 30 % (34 MB)
104 04:27:36.782445 progress 35 % (40 MB)
105 04:27:37.126239 progress 40 % (46 MB)
106 04:27:37.507609 progress 45 % (51 MB)
107 04:27:38.226040 progress 50 % (57 MB)
108 04:27:39.105778 progress 55 % (63 MB)
109 04:27:39.889827 progress 60 % (69 MB)
110 04:27:40.646027 progress 65 % (74 MB)
111 04:27:41.422447 progress 70 % (80 MB)
112 04:27:42.248808 progress 75 % (86 MB)
113 04:27:43.032033 progress 80 % (92 MB)
114 04:27:43.789778 progress 85 % (98 MB)
115 04:27:44.645501 progress 90 % (103 MB)
116 04:27:45.418016 progress 95 % (109 MB)
117 04:27:46.258943 progress 100 % (115 MB)
118 04:27:46.271428 115 MB downloaded in 15.11 s (7.63 MB/s)
119 04:27:46.272439 end: 1.4.1 http-download (duration 00:00:15) [common]
121 04:27:46.274238 end: 1.4 download-retry (duration 00:00:15) [common]
122 04:27:46.274820 start: 1.5 download-retry (timeout 00:09:44) [common]
123 04:27:46.275394 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 04:27:46.276255 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/modules.tar.xz
125 04:27:46.276780 saving as /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/modules/modules.tar
126 04:27:46.277244 total size: 11618152 (11 MB)
127 04:27:46.277712 Using unxz to decompress xz
128 04:27:46.318852 progress 0 % (0 MB)
129 04:27:46.385578 progress 5 % (0 MB)
130 04:27:46.459646 progress 10 % (1 MB)
131 04:27:46.555629 progress 15 % (1 MB)
132 04:27:46.648032 progress 20 % (2 MB)
133 04:27:46.728327 progress 25 % (2 MB)
134 04:27:46.804379 progress 30 % (3 MB)
135 04:27:46.882613 progress 35 % (3 MB)
136 04:27:46.955051 progress 40 % (4 MB)
137 04:27:47.030478 progress 45 % (5 MB)
138 04:27:47.114595 progress 50 % (5 MB)
139 04:27:47.195937 progress 55 % (6 MB)
140 04:27:47.276169 progress 60 % (6 MB)
141 04:27:47.356990 progress 65 % (7 MB)
142 04:27:47.436970 progress 70 % (7 MB)
143 04:27:47.514744 progress 75 % (8 MB)
144 04:27:47.597987 progress 80 % (8 MB)
145 04:27:47.677133 progress 85 % (9 MB)
146 04:27:47.759458 progress 90 % (10 MB)
147 04:27:47.832215 progress 95 % (10 MB)
148 04:27:47.909175 progress 100 % (11 MB)
149 04:27:47.921629 11 MB downloaded in 1.64 s (6.74 MB/s)
150 04:27:47.922492 end: 1.5.1 http-download (duration 00:00:02) [common]
152 04:27:47.924124 end: 1.5 download-retry (duration 00:00:02) [common]
153 04:27:47.924661 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 04:27:47.925174 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 04:28:04.156864 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/950831/extract-nfsrootfs-kbcjial5
156 04:28:04.157477 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 04:28:04.157765 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 04:28:04.158386 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj
159 04:28:04.158813 makedir: /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin
160 04:28:04.159214 makedir: /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/tests
161 04:28:04.159546 makedir: /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/results
162 04:28:04.159879 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-add-keys
163 04:28:04.160447 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-add-sources
164 04:28:04.160953 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-background-process-start
165 04:28:04.161452 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-background-process-stop
166 04:28:04.162010 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-common-functions
167 04:28:04.162550 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-echo-ipv4
168 04:28:04.163042 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-install-packages
169 04:28:04.163518 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-installed-packages
170 04:28:04.164013 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-os-build
171 04:28:04.164513 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-probe-channel
172 04:28:04.164988 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-probe-ip
173 04:28:04.165463 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-target-ip
174 04:28:04.165958 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-target-mac
175 04:28:04.166487 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-target-storage
176 04:28:04.166978 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-test-case
177 04:28:04.167457 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-test-event
178 04:28:04.167924 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-test-feedback
179 04:28:04.168438 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-test-raise
180 04:28:04.168909 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-test-reference
181 04:28:04.169383 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-test-runner
182 04:28:04.169886 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-test-set
183 04:28:04.170386 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-test-shell
184 04:28:04.170879 Updating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-add-keys (debian)
185 04:28:04.171401 Updating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-add-sources (debian)
186 04:28:04.171908 Updating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-install-packages (debian)
187 04:28:04.172478 Updating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-installed-packages (debian)
188 04:28:04.172979 Updating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/bin/lava-os-build (debian)
189 04:28:04.173410 Creating /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/environment
190 04:28:04.173788 LAVA metadata
191 04:28:04.174051 - LAVA_JOB_ID=950831
192 04:28:04.174268 - LAVA_DISPATCHER_IP=192.168.6.2
193 04:28:04.174630 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 04:28:04.175575 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 04:28:04.175890 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 04:28:04.176125 skipped lava-vland-overlay
197 04:28:04.176369 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 04:28:04.176622 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 04:28:04.176838 skipped lava-multinode-overlay
200 04:28:04.177080 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 04:28:04.177327 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 04:28:04.177571 Loading test definitions
203 04:28:04.177847 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 04:28:04.178063 Using /lava-950831 at stage 0
205 04:28:04.179143 uuid=950831_1.6.2.4.1 testdef=None
206 04:28:04.179457 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 04:28:04.179718 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 04:28:04.181286 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 04:28:04.182068 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 04:28:04.183960 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 04:28:04.184836 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 04:28:04.186652 runner path: /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/0/tests/0_timesync-off test_uuid 950831_1.6.2.4.1
215 04:28:04.187194 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 04:28:04.188021 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 04:28:04.188251 Using /lava-950831 at stage 0
219 04:28:04.188598 Fetching tests from https://github.com/kernelci/test-definitions.git
220 04:28:04.188883 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/0/tests/1_kselftest-dt'
221 04:28:07.754586 Running '/usr/bin/git checkout kernelci.org
222 04:28:08.287147 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 04:28:08.288613 uuid=950831_1.6.2.4.5 testdef=None
224 04:28:08.288958 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 04:28:08.289698 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 04:28:08.292551 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 04:28:08.293371 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 04:28:08.297042 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 04:28:08.297893 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 04:28:08.301475 runner path: /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/0/tests/1_kselftest-dt test_uuid 950831_1.6.2.4.5
234 04:28:08.301760 BOARD='meson-g12b-a311d-libretech-cc'
235 04:28:08.301965 BRANCH='mainline'
236 04:28:08.302162 SKIPFILE='/dev/null'
237 04:28:08.302358 SKIP_INSTALL='True'
238 04:28:08.302554 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 04:28:08.302753 TST_CASENAME=''
240 04:28:08.302948 TST_CMDFILES='dt'
241 04:28:08.303493 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 04:28:08.304332 Creating lava-test-runner.conf files
244 04:28:08.304545 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950831/lava-overlay-98t6mjmj/lava-950831/0 for stage 0
245 04:28:08.304988 - 0_timesync-off
246 04:28:08.305252 - 1_kselftest-dt
247 04:28:08.305589 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 04:28:08.305870 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 04:28:31.514208 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 04:28:31.514683 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 04:28:31.514990 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 04:28:31.515308 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 04:28:31.515612 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 04:28:32.138782 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 04:28:32.139264 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 04:28:32.139532 extracting modules file /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950831/extract-nfsrootfs-kbcjial5
257 04:28:33.513433 extracting modules file /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950831/extract-overlay-ramdisk-ja8kvnsf/ramdisk
258 04:28:34.920623 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 04:28:34.921111 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 04:28:34.921404 [common] Applying overlay to NFS
261 04:28:34.921631 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950831/compress-overlay-6emet3jt/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950831/extract-nfsrootfs-kbcjial5
262 04:28:37.659055 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 04:28:37.659541 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 04:28:37.659844 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 04:28:37.660136 Converting downloaded kernel to a uImage
266 04:28:37.660475 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/kernel/Image /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/kernel/uImage
267 04:28:38.163287 output: Image Name:
268 04:28:38.163740 output: Created: Thu Nov 7 04:28:37 2024
269 04:28:38.163957 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 04:28:38.164280 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 04:28:38.164493 output: Load Address: 01080000
272 04:28:38.164701 output: Entry Point: 01080000
273 04:28:38.164903 output:
274 04:28:38.165246 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 04:28:38.165523 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 04:28:38.165793 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 04:28:38.166048 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 04:28:38.166308 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 04:28:38.166565 Building ramdisk /var/lib/lava/dispatcher/tmp/950831/extract-overlay-ramdisk-ja8kvnsf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950831/extract-overlay-ramdisk-ja8kvnsf/ramdisk
280 04:28:40.550054 >> 166825 blocks
281 04:28:48.265229 Adding RAMdisk u-boot header.
282 04:28:48.265907 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950831/extract-overlay-ramdisk-ja8kvnsf/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950831/extract-overlay-ramdisk-ja8kvnsf/ramdisk.cpio.gz.uboot
283 04:28:48.510328 output: Image Name:
284 04:28:48.510966 output: Created: Thu Nov 7 04:28:48 2024
285 04:28:48.511403 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 04:28:48.511826 output: Data Size: 23432795 Bytes = 22883.59 KiB = 22.35 MiB
287 04:28:48.512303 output: Load Address: 00000000
288 04:28:48.512716 output: Entry Point: 00000000
289 04:28:48.513131 output:
290 04:28:48.514106 rename /var/lib/lava/dispatcher/tmp/950831/extract-overlay-ramdisk-ja8kvnsf/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/ramdisk/ramdisk.cpio.gz.uboot
291 04:28:48.514834 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 04:28:48.515390 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 04:28:48.515929 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 04:28:48.516427 No LXC device requested
295 04:28:48.516947 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 04:28:48.517467 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 04:28:48.517970 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 04:28:48.518386 Checking files for TFTP limit of 4294967296 bytes.
299 04:28:48.521087 end: 1 tftp-deploy (duration 00:01:18) [common]
300 04:28:48.521678 start: 2 uboot-action (timeout 00:05:00) [common]
301 04:28:48.522216 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 04:28:48.522722 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 04:28:48.523241 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 04:28:48.523781 Using kernel file from prepare-kernel: 950831/tftp-deploy-otq453dv/kernel/uImage
305 04:28:48.524452 substitutions:
306 04:28:48.524875 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 04:28:48.525291 - {DTB_ADDR}: 0x01070000
308 04:28:48.525698 - {DTB}: 950831/tftp-deploy-otq453dv/dtb/meson-g12b-a311d-libretech-cc.dtb
309 04:28:48.526110 - {INITRD}: 950831/tftp-deploy-otq453dv/ramdisk/ramdisk.cpio.gz.uboot
310 04:28:48.526514 - {KERNEL_ADDR}: 0x01080000
311 04:28:48.526914 - {KERNEL}: 950831/tftp-deploy-otq453dv/kernel/uImage
312 04:28:48.527315 - {LAVA_MAC}: None
313 04:28:48.527757 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/950831/extract-nfsrootfs-kbcjial5
314 04:28:48.528203 - {NFS_SERVER_IP}: 192.168.6.2
315 04:28:48.528610 - {PRESEED_CONFIG}: None
316 04:28:48.529028 - {PRESEED_LOCAL}: None
317 04:28:48.529448 - {RAMDISK_ADDR}: 0x08000000
318 04:28:48.529856 - {RAMDISK}: 950831/tftp-deploy-otq453dv/ramdisk/ramdisk.cpio.gz.uboot
319 04:28:48.530255 - {ROOT_PART}: None
320 04:28:48.530652 - {ROOT}: None
321 04:28:48.531045 - {SERVER_IP}: 192.168.6.2
322 04:28:48.531441 - {TEE_ADDR}: 0x83000000
323 04:28:48.531832 - {TEE}: None
324 04:28:48.532256 Parsed boot commands:
325 04:28:48.532643 - setenv autoload no
326 04:28:48.533035 - setenv initrd_high 0xffffffff
327 04:28:48.533427 - setenv fdt_high 0xffffffff
328 04:28:48.533816 - dhcp
329 04:28:48.534206 - setenv serverip 192.168.6.2
330 04:28:48.534599 - tftpboot 0x01080000 950831/tftp-deploy-otq453dv/kernel/uImage
331 04:28:48.534995 - tftpboot 0x08000000 950831/tftp-deploy-otq453dv/ramdisk/ramdisk.cpio.gz.uboot
332 04:28:48.535391 - tftpboot 0x01070000 950831/tftp-deploy-otq453dv/dtb/meson-g12b-a311d-libretech-cc.dtb
333 04:28:48.535783 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950831/extract-nfsrootfs-kbcjial5,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 04:28:48.536225 - bootm 0x01080000 0x08000000 0x01070000
335 04:28:48.536752 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 04:28:48.538284 start: 2.3 connect-device (timeout 00:05:00) [common]
338 04:28:48.538720 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 04:28:48.553703 Setting prompt string to ['lava-test: # ']
340 04:28:48.555240 end: 2.3 connect-device (duration 00:00:00) [common]
341 04:28:48.555871 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 04:28:48.556817 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 04:28:48.557467 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 04:28:48.558636 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 04:28:48.595540 >> OK - accepted request
346 04:28:48.597331 Returned 0 in 0 seconds
347 04:28:48.698441 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 04:28:48.700158 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 04:28:48.700740 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 04:28:48.701256 Setting prompt string to ['Hit any key to stop autoboot']
352 04:28:48.701719 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 04:28:48.703312 Trying 192.168.56.21...
354 04:28:48.703798 Connected to conserv1.
355 04:28:48.704257 Escape character is '^]'.
356 04:28:48.704684
357 04:28:48.705111 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 04:28:48.705533
359 04:29:00.102722 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 04:29:00.103350 bl2_stage_init 0x01
361 04:29:00.103806 bl2_stage_init 0x81
362 04:29:00.108339 hw id: 0x0000 - pwm id 0x01
363 04:29:00.108879 bl2_stage_init 0xc1
364 04:29:00.109296 bl2_stage_init 0x02
365 04:29:00.109705
366 04:29:00.113837 L0:00000000
367 04:29:00.114484 L1:20000703
368 04:29:00.115035 L2:00008067
369 04:29:00.115578 L3:14000000
370 04:29:00.119452 B2:00402000
371 04:29:00.120098 B1:e0f83180
372 04:29:00.120656
373 04:29:00.121171 TE: 58124
374 04:29:00.121695
375 04:29:00.124989 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 04:29:00.125561
377 04:29:00.126077 Board ID = 1
378 04:29:00.130546 Set A53 clk to 24M
379 04:29:00.131118 Set A73 clk to 24M
380 04:29:00.131630 Set clk81 to 24M
381 04:29:00.136287 A53 clk: 1200 MHz
382 04:29:00.136867 A73 clk: 1200 MHz
383 04:29:00.137386 CLK81: 166.6M
384 04:29:00.137891 smccc: 00012a92
385 04:29:00.141798 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 04:29:00.147376 board id: 1
387 04:29:00.153456 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 04:29:00.163822 fw parse done
389 04:29:00.169747 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 04:29:00.212467 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 04:29:00.223287 PIEI prepare done
392 04:29:00.223868 fastboot data load
393 04:29:00.224415 fastboot data verify
394 04:29:00.229067 verify result: 266
395 04:29:00.234661 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 04:29:00.235316 LPDDR4 probe
397 04:29:00.235834 ddr clk to 1584MHz
398 04:29:00.242590 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 04:29:00.279804
400 04:29:00.280322 dmc_version 0001
401 04:29:00.286484 Check phy result
402 04:29:00.292325 INFO : End of CA training
403 04:29:00.292788 INFO : End of initialization
404 04:29:00.297930 INFO : Training has run successfully!
405 04:29:00.298388 Check phy result
406 04:29:00.303530 INFO : End of initialization
407 04:29:00.304018 INFO : End of read enable training
408 04:29:00.309159 INFO : End of fine write leveling
409 04:29:00.314736 INFO : End of Write leveling coarse delay
410 04:29:00.315194 INFO : Training has run successfully!
411 04:29:00.315608 Check phy result
412 04:29:00.320338 INFO : End of initialization
413 04:29:00.320798 INFO : End of read dq deskew training
414 04:29:00.325920 INFO : End of MPR read delay center optimization
415 04:29:00.331526 INFO : End of write delay center optimization
416 04:29:00.337121 INFO : End of read delay center optimization
417 04:29:00.337607 INFO : End of max read latency training
418 04:29:00.342733 INFO : Training has run successfully!
419 04:29:00.343194 1D training succeed
420 04:29:00.351897 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 04:29:00.399601 Check phy result
422 04:29:00.400156 INFO : End of initialization
423 04:29:00.421427 INFO : End of 2D read delay Voltage center optimization
424 04:29:00.441517 INFO : End of 2D read delay Voltage center optimization
425 04:29:00.493581 INFO : End of 2D write delay Voltage center optimization
426 04:29:00.542970 INFO : End of 2D write delay Voltage center optimization
427 04:29:00.548591 INFO : Training has run successfully!
428 04:29:00.549092
429 04:29:00.549521 channel==0
430 04:29:00.554088 RxClkDly_Margin_A0==88 ps 9
431 04:29:00.554590 TxDqDly_Margin_A0==98 ps 10
432 04:29:00.559671 RxClkDly_Margin_A1==88 ps 9
433 04:29:00.560190 TxDqDly_Margin_A1==88 ps 9
434 04:29:00.560610 TrainedVREFDQ_A0==74
435 04:29:00.565278 TrainedVREFDQ_A1==74
436 04:29:00.565760 VrefDac_Margin_A0==25
437 04:29:00.566176 DeviceVref_Margin_A0==40
438 04:29:00.570898 VrefDac_Margin_A1==25
439 04:29:00.571391 DeviceVref_Margin_A1==40
440 04:29:00.571805
441 04:29:00.572261
442 04:29:00.572672 channel==1
443 04:29:00.576602 RxClkDly_Margin_A0==98 ps 10
444 04:29:00.577084 TxDqDly_Margin_A0==98 ps 10
445 04:29:00.582064 RxClkDly_Margin_A1==98 ps 10
446 04:29:00.582545 TxDqDly_Margin_A1==98 ps 10
447 04:29:00.587679 TrainedVREFDQ_A0==77
448 04:29:00.588185 TrainedVREFDQ_A1==77
449 04:29:00.588605 VrefDac_Margin_A0==22
450 04:29:00.593263 DeviceVref_Margin_A0==37
451 04:29:00.593732 VrefDac_Margin_A1==22
452 04:29:00.598899 DeviceVref_Margin_A1==37
453 04:29:00.599373
454 04:29:00.599788 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 04:29:00.604590
456 04:29:00.632424 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 04:29:00.633004 2D training succeed
458 04:29:00.638057 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 04:29:00.643651 auto size-- 65535DDR cs0 size: 2048MB
460 04:29:00.644138 DDR cs1 size: 2048MB
461 04:29:00.649224 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 04:29:00.649691 cs0 DataBus test pass
463 04:29:00.654819 cs1 DataBus test pass
464 04:29:00.655266 cs0 AddrBus test pass
465 04:29:00.655681 cs1 AddrBus test pass
466 04:29:00.656115
467 04:29:00.660439 100bdlr_step_size ps== 420
468 04:29:00.660901 result report
469 04:29:00.666045 boot times 0Enable ddr reg access
470 04:29:00.671489 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 04:29:00.684940 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 04:29:01.258564 0.0;M3 CHK:0;cm4_sp_mode 0
473 04:29:01.258964 MVN_1=0x00000000
474 04:29:01.264044 MVN_2=0x00000000
475 04:29:01.269783 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 04:29:01.270239 OPS=0x10
477 04:29:01.270659 ring efuse init
478 04:29:01.271062 chipver efuse init
479 04:29:01.275397 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 04:29:01.280980 [0.018961 Inits done]
481 04:29:01.281427 secure task start!
482 04:29:01.281836 high task start!
483 04:29:01.285574 low task start!
484 04:29:01.286018 run into bl31
485 04:29:01.292264 NOTICE: BL31: v1.3(release):4fc40b1
486 04:29:01.300068 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 04:29:01.300524 NOTICE: BL31: G12A normal boot!
488 04:29:01.325427 NOTICE: BL31: BL33 decompress pass
489 04:29:01.330139 ERROR: Error initializing runtime service opteed_fast
490 04:29:02.564049
491 04:29:02.564677
492 04:29:02.572367 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 04:29:02.572844
494 04:29:02.573264 Model: Libre Computer AML-A311D-CC Alta
495 04:29:02.780815 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 04:29:02.804179 DRAM: 2 GiB (effective 3.8 GiB)
497 04:29:02.947170 Core: 408 devices, 31 uclasses, devicetree: separate
498 04:29:02.952995 WDT: Not starting watchdog@f0d0
499 04:29:02.985274 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 04:29:02.997732 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 04:29:03.002721 ** Bad device specification mmc 0 **
502 04:29:03.013036 Card did not respond to voltage select! : -110
503 04:29:03.020740 ** Bad device specification mmc 0 **
504 04:29:03.021206 Couldn't find partition mmc 0
505 04:29:03.029099 Card did not respond to voltage select! : -110
506 04:29:03.034597 ** Bad device specification mmc 0 **
507 04:29:03.035125 Couldn't find partition mmc 0
508 04:29:03.039633 Error: could not access storage.
509 04:29:04.293130 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 04:29:04.293780 bl2_stage_init 0x01
511 04:29:04.294243 bl2_stage_init 0x81
512 04:29:04.298776 hw id: 0x0000 - pwm id 0x01
513 04:29:04.299272 bl2_stage_init 0xc1
514 04:29:04.299697 bl2_stage_init 0x02
515 04:29:04.300154
516 04:29:04.304148 L0:00000000
517 04:29:04.304813 L1:20000703
518 04:29:04.305363 L2:00008067
519 04:29:04.305910 L3:14000000
520 04:29:04.306948 B2:00402000
521 04:29:04.307524 B1:e0f83180
522 04:29:04.308209
523 04:29:04.308828 TE: 58167
524 04:29:04.309539
525 04:29:04.318090 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 04:29:04.318795
527 04:29:04.319352 Board ID = 1
528 04:29:04.319943 Set A53 clk to 24M
529 04:29:04.320561 Set A73 clk to 24M
530 04:29:04.323804 Set clk81 to 24M
531 04:29:04.324469 A53 clk: 1200 MHz
532 04:29:04.325025 A73 clk: 1200 MHz
533 04:29:04.329659 CLK81: 166.6M
534 04:29:04.330064 smccc: 00012abd
535 04:29:04.334979 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 04:29:04.335657 board id: 1
537 04:29:04.340523 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 04:29:04.354330 fw parse done
539 04:29:04.360327 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 04:29:04.402897 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 04:29:04.413895 PIEI prepare done
542 04:29:04.414519 fastboot data load
543 04:29:04.415166 fastboot data verify
544 04:29:04.419573 verify result: 266
545 04:29:04.425178 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 04:29:04.425728 LPDDR4 probe
547 04:29:04.426157 ddr clk to 1584MHz
548 04:29:04.433110 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 04:29:04.470375
550 04:29:04.470969 dmc_version 0001
551 04:29:04.477042 Check phy result
552 04:29:04.482889 INFO : End of CA training
553 04:29:04.483416 INFO : End of initialization
554 04:29:04.488502 INFO : Training has run successfully!
555 04:29:04.489026 Check phy result
556 04:29:04.494166 INFO : End of initialization
557 04:29:04.494691 INFO : End of read enable training
558 04:29:04.499687 INFO : End of fine write leveling
559 04:29:04.505307 INFO : End of Write leveling coarse delay
560 04:29:04.505834 INFO : Training has run successfully!
561 04:29:04.506258 Check phy result
562 04:29:04.510900 INFO : End of initialization
563 04:29:04.511431 INFO : End of read dq deskew training
564 04:29:04.516476 INFO : End of MPR read delay center optimization
565 04:29:04.522111 INFO : End of write delay center optimization
566 04:29:04.527654 INFO : End of read delay center optimization
567 04:29:04.528231 INFO : End of max read latency training
568 04:29:04.533341 INFO : Training has run successfully!
569 04:29:04.533868 1D training succeed
570 04:29:04.542546 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 04:29:04.590130 Check phy result
572 04:29:04.590761 INFO : End of initialization
573 04:29:04.611846 INFO : End of 2D read delay Voltage center optimization
574 04:29:04.632190 INFO : End of 2D read delay Voltage center optimization
575 04:29:04.684139 INFO : End of 2D write delay Voltage center optimization
576 04:29:04.733521 INFO : End of 2D write delay Voltage center optimization
577 04:29:04.739012 INFO : Training has run successfully!
578 04:29:04.739536
579 04:29:04.739972 channel==0
580 04:29:04.744644 RxClkDly_Margin_A0==88 ps 9
581 04:29:04.745174 TxDqDly_Margin_A0==98 ps 10
582 04:29:04.750266 RxClkDly_Margin_A1==88 ps 9
583 04:29:04.750838 TxDqDly_Margin_A1==98 ps 10
584 04:29:04.751264 TrainedVREFDQ_A0==74
585 04:29:04.755782 TrainedVREFDQ_A1==75
586 04:29:04.756313 VrefDac_Margin_A0==25
587 04:29:04.756727 DeviceVref_Margin_A0==40
588 04:29:04.761379 VrefDac_Margin_A1==25
589 04:29:04.761882 DeviceVref_Margin_A1==39
590 04:29:04.762296
591 04:29:04.762708
592 04:29:04.766996 channel==1
593 04:29:04.767502 RxClkDly_Margin_A0==98 ps 10
594 04:29:04.767920 TxDqDly_Margin_A0==98 ps 10
595 04:29:04.772583 RxClkDly_Margin_A1==88 ps 9
596 04:29:04.773097 TxDqDly_Margin_A1==88 ps 9
597 04:29:04.778205 TrainedVREFDQ_A0==77
598 04:29:04.778725 TrainedVREFDQ_A1==77
599 04:29:04.779145 VrefDac_Margin_A0==22
600 04:29:04.783811 DeviceVref_Margin_A0==37
601 04:29:04.784357 VrefDac_Margin_A1==24
602 04:29:04.789394 DeviceVref_Margin_A1==37
603 04:29:04.789892
604 04:29:04.790320 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 04:29:04.790733
606 04:29:04.823073 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
607 04:29:04.823705 2D training succeed
608 04:29:04.828674 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 04:29:04.834238 auto size-- 65535DDR cs0 size: 2048MB
610 04:29:04.834764 DDR cs1 size: 2048MB
611 04:29:04.839797 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 04:29:04.840364 cs0 DataBus test pass
613 04:29:04.845398 cs1 DataBus test pass
614 04:29:04.845942 cs0 AddrBus test pass
615 04:29:04.846360 cs1 AddrBus test pass
616 04:29:04.846762
617 04:29:04.850971 100bdlr_step_size ps== 420
618 04:29:04.851475 result report
619 04:29:04.856575 boot times 0Enable ddr reg access
620 04:29:04.861936 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 04:29:04.875363 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 04:29:05.449729 0.0;M3 CHK:0;cm4_sp_mode 0
623 04:29:05.450170 MVN_1=0x00000000
624 04:29:05.454596 MVN_2=0x00000000
625 04:29:05.460319 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 04:29:05.460721 OPS=0x10
627 04:29:05.460961 ring efuse init
628 04:29:05.461183 chipver efuse init
629 04:29:05.466094 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 04:29:05.472488 [0.018961 Inits done]
631 04:29:05.473150 secure task start!
632 04:29:05.473565 high task start!
633 04:29:05.475315 low task start!
634 04:29:05.475780 run into bl31
635 04:29:05.482856 NOTICE: BL31: v1.3(release):4fc40b1
636 04:29:05.490594 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 04:29:05.491231 NOTICE: BL31: G12A normal boot!
638 04:29:05.515851 NOTICE: BL31: BL33 decompress pass
639 04:29:05.522317 ERROR: Error initializing runtime service opteed_fast
640 04:29:06.754528
641 04:29:06.755206
642 04:29:06.762869 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 04:29:06.763384
644 04:29:06.763852 Model: Libre Computer AML-A311D-CC Alta
645 04:29:06.971289 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 04:29:06.994676 DRAM: 2 GiB (effective 3.8 GiB)
647 04:29:07.137702 Core: 408 devices, 31 uclasses, devicetree: separate
648 04:29:07.143542 WDT: Not starting watchdog@f0d0
649 04:29:07.175788 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 04:29:07.188261 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 04:29:07.193204 ** Bad device specification mmc 0 **
652 04:29:07.203548 Card did not respond to voltage select! : -110
653 04:29:07.211187 ** Bad device specification mmc 0 **
654 04:29:07.211672 Couldn't find partition mmc 0
655 04:29:07.219536 Card did not respond to voltage select! : -110
656 04:29:07.225060 ** Bad device specification mmc 0 **
657 04:29:07.225542 Couldn't find partition mmc 0
658 04:29:07.230111 Error: could not access storage.
659 04:29:07.572677 Net: eth0: ethernet@ff3f0000
660 04:29:07.573341 starting USB...
661 04:29:07.824389 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 04:29:07.824950 Starting the controller
663 04:29:07.830415 USB XHCI 1.10
664 04:29:09.543028 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 04:29:09.543710 bl2_stage_init 0x01
666 04:29:09.544257 bl2_stage_init 0x81
667 04:29:09.548598 hw id: 0x0000 - pwm id 0x01
668 04:29:09.549094 bl2_stage_init 0xc1
669 04:29:09.549558 bl2_stage_init 0x02
670 04:29:09.550007
671 04:29:09.554188 L0:00000000
672 04:29:09.554674 L1:20000703
673 04:29:09.555128 L2:00008067
674 04:29:09.555572 L3:14000000
675 04:29:09.559778 B2:00402000
676 04:29:09.560311 B1:e0f83180
677 04:29:09.560775
678 04:29:09.561229 TE: 58159
679 04:29:09.561683
680 04:29:09.565456 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 04:29:09.566010
682 04:29:09.566486 Board ID = 1
683 04:29:09.571049 Set A53 clk to 24M
684 04:29:09.571589 Set A73 clk to 24M
685 04:29:09.572082 Set clk81 to 24M
686 04:29:09.576620 A53 clk: 1200 MHz
687 04:29:09.577144 A73 clk: 1200 MHz
688 04:29:09.577654 CLK81: 166.6M
689 04:29:09.578131 smccc: 00012ab5
690 04:29:09.582275 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 04:29:09.587872 board id: 1
692 04:29:09.593804 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 04:29:09.604387 fw parse done
694 04:29:09.610327 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 04:29:09.652935 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 04:29:09.663825 PIEI prepare done
697 04:29:09.664357 fastboot data load
698 04:29:09.664788 fastboot data verify
699 04:29:09.669576 verify result: 266
700 04:29:09.675178 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 04:29:09.675660 LPDDR4 probe
702 04:29:09.676130 ddr clk to 1584MHz
703 04:29:09.683154 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 04:29:09.720396
705 04:29:09.720919 dmc_version 0001
706 04:29:09.727061 Check phy result
707 04:29:09.732993 INFO : End of CA training
708 04:29:09.733484 INFO : End of initialization
709 04:29:09.738504 INFO : Training has run successfully!
710 04:29:09.738980 Check phy result
711 04:29:09.744096 INFO : End of initialization
712 04:29:09.744555 INFO : End of read enable training
713 04:29:09.749664 INFO : End of fine write leveling
714 04:29:09.755168 INFO : End of Write leveling coarse delay
715 04:29:09.755603 INFO : Training has run successfully!
716 04:29:09.756046 Check phy result
717 04:29:09.760797 INFO : End of initialization
718 04:29:09.761268 INFO : End of read dq deskew training
719 04:29:09.766353 INFO : End of MPR read delay center optimization
720 04:29:09.771949 INFO : End of write delay center optimization
721 04:29:09.777573 INFO : End of read delay center optimization
722 04:29:09.778017 INFO : End of max read latency training
723 04:29:09.783181 INFO : Training has run successfully!
724 04:29:09.783614 1D training succeed
725 04:29:09.792426 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 04:29:09.840043 Check phy result
727 04:29:09.840479 INFO : End of initialization
728 04:29:09.862622 INFO : End of 2D read delay Voltage center optimization
729 04:29:09.882845 INFO : End of 2D read delay Voltage center optimization
730 04:29:09.934847 INFO : End of 2D write delay Voltage center optimization
731 04:29:09.984308 INFO : End of 2D write delay Voltage center optimization
732 04:29:09.989826 INFO : Training has run successfully!
733 04:29:09.990259
734 04:29:09.990674 channel==0
735 04:29:09.995398 RxClkDly_Margin_A0==88 ps 9
736 04:29:09.995840 TxDqDly_Margin_A0==98 ps 10
737 04:29:10.000995 RxClkDly_Margin_A1==88 ps 9
738 04:29:10.001437 TxDqDly_Margin_A1==98 ps 10
739 04:29:10.001850 TrainedVREFDQ_A0==74
740 04:29:10.006577 TrainedVREFDQ_A1==74
741 04:29:10.007012 VrefDac_Margin_A0==25
742 04:29:10.007420 DeviceVref_Margin_A0==40
743 04:29:10.012198 VrefDac_Margin_A1==25
744 04:29:10.012625 DeviceVref_Margin_A1==40
745 04:29:10.013034
746 04:29:10.013439
747 04:29:10.017852 channel==1
748 04:29:10.018367 RxClkDly_Margin_A0==98 ps 10
749 04:29:10.018787 TxDqDly_Margin_A0==98 ps 10
750 04:29:10.023460 RxClkDly_Margin_A1==88 ps 9
751 04:29:10.023969 TxDqDly_Margin_A1==88 ps 9
752 04:29:10.028994 TrainedVREFDQ_A0==77
753 04:29:10.029493 TrainedVREFDQ_A1==77
754 04:29:10.029911 VrefDac_Margin_A0==22
755 04:29:10.034580 DeviceVref_Margin_A0==37
756 04:29:10.035019 VrefDac_Margin_A1==24
757 04:29:10.040228 DeviceVref_Margin_A1==37
758 04:29:10.040666
759 04:29:10.041081 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 04:29:10.041484
761 04:29:10.073785 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
762 04:29:10.074259 2D training succeed
763 04:29:10.079396 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 04:29:10.084977 auto size-- 65535DDR cs0 size: 2048MB
765 04:29:10.085412 DDR cs1 size: 2048MB
766 04:29:10.090588 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 04:29:10.091031 cs0 DataBus test pass
768 04:29:10.096223 cs1 DataBus test pass
769 04:29:10.096672 cs0 AddrBus test pass
770 04:29:10.097080 cs1 AddrBus test pass
771 04:29:10.097483
772 04:29:10.101768 100bdlr_step_size ps== 420
773 04:29:10.102221 result report
774 04:29:10.107395 boot times 0Enable ddr reg access
775 04:29:10.112754 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 04:29:10.126240 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 04:29:10.700113 0.0;M3 CHK:0;cm4_sp_mode 0
778 04:29:10.700701 MVN_1=0x00000000
779 04:29:10.705541 MVN_2=0x00000000
780 04:29:10.711349 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 04:29:10.711853 OPS=0x10
782 04:29:10.712309 ring efuse init
783 04:29:10.712704 chipver efuse init
784 04:29:10.719610 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 04:29:10.720068 [0.018961 Inits done]
786 04:29:10.720466 secure task start!
787 04:29:10.727062 high task start!
788 04:29:10.727476 low task start!
789 04:29:10.727869 run into bl31
790 04:29:10.733725 NOTICE: BL31: v1.3(release):4fc40b1
791 04:29:10.741515 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 04:29:10.741937 NOTICE: BL31: G12A normal boot!
793 04:29:10.766987 NOTICE: BL31: BL33 decompress pass
794 04:29:10.772677 ERROR: Error initializing runtime service opteed_fast
795 04:29:12.005553
796 04:29:12.006189
797 04:29:12.013873 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 04:29:12.014329
799 04:29:12.014747 Model: Libre Computer AML-A311D-CC Alta
800 04:29:12.222522 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 04:29:12.245705 DRAM: 2 GiB (effective 3.8 GiB)
802 04:29:12.388707 Core: 408 devices, 31 uclasses, devicetree: separate
803 04:29:12.394544 WDT: Not starting watchdog@f0d0
804 04:29:12.426815 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 04:29:12.439413 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 04:29:12.443373 ** Bad device specification mmc 0 **
807 04:29:12.454598 Card did not respond to voltage select! : -110
808 04:29:12.462292 ** Bad device specification mmc 0 **
809 04:29:12.462730 Couldn't find partition mmc 0
810 04:29:12.470595 Card did not respond to voltage select! : -110
811 04:29:12.476052 ** Bad device specification mmc 0 **
812 04:29:12.476498 Couldn't find partition mmc 0
813 04:29:12.481177 Error: could not access storage.
814 04:29:12.824619 Net: eth0: ethernet@ff3f0000
815 04:29:12.825145 starting USB...
816 04:29:13.076659 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 04:29:13.077224 Starting the controller
818 04:29:13.083434 USB XHCI 1.10
819 04:29:15.244872 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
820 04:29:15.245540 bl2_stage_init 0x81
821 04:29:15.250356 hw id: 0x0000 - pwm id 0x01
822 04:29:15.250816 bl2_stage_init 0xc1
823 04:29:15.251235 bl2_stage_init 0x02
824 04:29:15.251647
825 04:29:15.256038 L0:00000000
826 04:29:15.256485 L1:20000703
827 04:29:15.256901 L2:00008067
828 04:29:15.257304 L3:14000000
829 04:29:15.257707 B2:00402000
830 04:29:15.261653 B1:e0f83180
831 04:29:15.262095
832 04:29:15.262510 TE: 58150
833 04:29:15.262916
834 04:29:15.267116 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 04:29:15.267556
836 04:29:15.267969 Board ID = 1
837 04:29:15.272785 Set A53 clk to 24M
838 04:29:15.273224 Set A73 clk to 24M
839 04:29:15.273628 Set clk81 to 24M
840 04:29:15.278360 A53 clk: 1200 MHz
841 04:29:15.278793 A73 clk: 1200 MHz
842 04:29:15.279198 CLK81: 166.6M
843 04:29:15.279602 smccc: 00012aab
844 04:29:15.283897 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 04:29:15.289570 board id: 1
846 04:29:15.295444 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 04:29:15.305908 fw parse done
848 04:29:15.311076 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 04:29:15.354569 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 04:29:15.365396 PIEI prepare done
851 04:29:15.365833 fastboot data load
852 04:29:15.366248 fastboot data verify
853 04:29:15.371132 verify result: 266
854 04:29:15.376789 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 04:29:15.377244 LPDDR4 probe
856 04:29:15.377654 ddr clk to 1584MHz
857 04:29:15.384705 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 04:29:15.421345
859 04:29:15.421856 dmc_version 0001
860 04:29:15.428700 Check phy result
861 04:29:15.434556 INFO : End of CA training
862 04:29:15.435001 INFO : End of initialization
863 04:29:15.440101 INFO : Training has run successfully!
864 04:29:15.440540 Check phy result
865 04:29:15.445682 INFO : End of initialization
866 04:29:15.446119 INFO : End of read enable training
867 04:29:15.449004 INFO : End of fine write leveling
868 04:29:15.454594 INFO : End of Write leveling coarse delay
869 04:29:15.460175 INFO : Training has run successfully!
870 04:29:15.460609 Check phy result
871 04:29:15.461021 INFO : End of initialization
872 04:29:15.465696 INFO : End of read dq deskew training
873 04:29:15.471340 INFO : End of MPR read delay center optimization
874 04:29:15.471783 INFO : End of write delay center optimization
875 04:29:15.476981 INFO : End of read delay center optimization
876 04:29:15.482546 INFO : End of max read latency training
877 04:29:15.482980 INFO : Training has run successfully!
878 04:29:15.488138 1D training succeed
879 04:29:15.494115 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 04:29:15.541638 Check phy result
881 04:29:15.542113 INFO : End of initialization
882 04:29:15.563319 INFO : End of 2D read delay Voltage center optimization
883 04:29:15.583728 INFO : End of 2D read delay Voltage center optimization
884 04:29:15.635649 INFO : End of 2D write delay Voltage center optimization
885 04:29:15.684989 INFO : End of 2D write delay Voltage center optimization
886 04:29:15.690563 INFO : Training has run successfully!
887 04:29:15.691002
888 04:29:15.691416 channel==0
889 04:29:15.696202 RxClkDly_Margin_A0==88 ps 9
890 04:29:15.696640 TxDqDly_Margin_A0==98 ps 10
891 04:29:15.701745 RxClkDly_Margin_A1==88 ps 9
892 04:29:15.702177 TxDqDly_Margin_A1==88 ps 9
893 04:29:15.702601 TrainedVREFDQ_A0==74
894 04:29:15.707354 TrainedVREFDQ_A1==74
895 04:29:15.707834 VrefDac_Margin_A0==25
896 04:29:15.708292 DeviceVref_Margin_A0==40
897 04:29:15.712944 VrefDac_Margin_A1==25
898 04:29:15.713414 DeviceVref_Margin_A1==40
899 04:29:15.713805
900 04:29:15.714195
901 04:29:15.714583 channel==1
902 04:29:15.718551 RxClkDly_Margin_A0==98 ps 10
903 04:29:15.718977 TxDqDly_Margin_A0==98 ps 10
904 04:29:15.724177 RxClkDly_Margin_A1==98 ps 10
905 04:29:15.724595 TxDqDly_Margin_A1==88 ps 9
906 04:29:15.729746 TrainedVREFDQ_A0==77
907 04:29:15.730170 TrainedVREFDQ_A1==77
908 04:29:15.730566 VrefDac_Margin_A0==22
909 04:29:15.735348 DeviceVref_Margin_A0==37
910 04:29:15.735762 VrefDac_Margin_A1==22
911 04:29:15.740948 DeviceVref_Margin_A1==37
912 04:29:15.741367
913 04:29:15.741758 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 04:29:15.742144
915 04:29:15.774575 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
916 04:29:15.775076 2D training succeed
917 04:29:15.780217 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 04:29:15.785742 auto size-- 65535DDR cs0 size: 2048MB
919 04:29:15.786167 DDR cs1 size: 2048MB
920 04:29:15.791346 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 04:29:15.791771 cs0 DataBus test pass
922 04:29:15.796952 cs1 DataBus test pass
923 04:29:15.797379 cs0 AddrBus test pass
924 04:29:15.797769 cs1 AddrBus test pass
925 04:29:15.798158
926 04:29:15.802575 100bdlr_step_size ps== 420
927 04:29:15.803011 result report
928 04:29:15.808204 boot times 0Enable ddr reg access
929 04:29:15.813523 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 04:29:15.826985 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 04:29:16.400718 0.0;M3 CHK:0;cm4_sp_mode 0
932 04:29:16.401358 MVN_1=0x00000000
933 04:29:16.406104 MVN_2=0x00000000
934 04:29:16.411876 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 04:29:16.412374 OPS=0x10
936 04:29:16.412794 ring efuse init
937 04:29:16.413200 chipver efuse init
938 04:29:16.420197 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 04:29:16.420667 [0.018961 Inits done]
940 04:29:16.421078 secure task start!
941 04:29:16.427680 high task start!
942 04:29:16.428151 low task start!
943 04:29:16.428561 run into bl31
944 04:29:16.434335 NOTICE: BL31: v1.3(release):4fc40b1
945 04:29:16.442124 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 04:29:16.442570 NOTICE: BL31: G12A normal boot!
947 04:29:16.468029 NOTICE: BL31: BL33 decompress pass
948 04:29:16.473698 ERROR: Error initializing runtime service opteed_fast
949 04:29:17.706735
950 04:29:17.707371
951 04:29:17.715009 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 04:29:17.715485
953 04:29:17.715915 Model: Libre Computer AML-A311D-CC Alta
954 04:29:17.923433 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 04:29:17.946894 DRAM: 2 GiB (effective 3.8 GiB)
956 04:29:18.089926 Core: 408 devices, 31 uclasses, devicetree: separate
957 04:29:18.095177 WDT: Not starting watchdog@f0d0
958 04:29:18.127955 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 04:29:18.140413 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 04:29:18.145396 ** Bad device specification mmc 0 **
961 04:29:18.155704 Card did not respond to voltage select! : -110
962 04:29:18.163370 ** Bad device specification mmc 0 **
963 04:29:18.163817 Couldn't find partition mmc 0
964 04:29:18.171704 Card did not respond to voltage select! : -110
965 04:29:18.177212 ** Bad device specification mmc 0 **
966 04:29:18.177653 Couldn't find partition mmc 0
967 04:29:18.182277 Error: could not access storage.
968 04:29:18.523903 Net: eth0: ethernet@ff3f0000
969 04:29:18.524518 starting USB...
970 04:29:18.776588 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 04:29:18.777103 Starting the controller
972 04:29:18.782593 USB XHCI 1.10
973 04:29:20.337585 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
974 04:29:20.345801 scanning usb for storage devices... 0 Storage Device(s) found
976 04:29:20.397335 Hit any key to stop autoboot: 1
977 04:29:20.398109 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
978 04:29:20.398696 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
979 04:29:20.399175 Setting prompt string to ['=>']
980 04:29:20.399666 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
981 04:29:20.412327 0
982 04:29:20.413224 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
983 04:29:20.413733 Sending with 10 millisecond of delay
985 04:29:21.548318 => setenv autoload no
986 04:29:21.559149 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
987 04:29:21.564106 setenv autoload no
988 04:29:21.564847 Sending with 10 millisecond of delay
990 04:29:23.361539 => setenv initrd_high 0xffffffff
991 04:29:23.372300 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
992 04:29:23.373112 setenv initrd_high 0xffffffff
993 04:29:23.373819 Sending with 10 millisecond of delay
995 04:29:24.989808 => setenv fdt_high 0xffffffff
996 04:29:25.000558 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
997 04:29:25.001345 setenv fdt_high 0xffffffff
998 04:29:25.002047 Sending with 10 millisecond of delay
1000 04:29:25.293820 => dhcp
1001 04:29:25.304505 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1002 04:29:25.305272 dhcp
1003 04:29:25.305703 Speed: 1000, full duplex
1004 04:29:25.306118 BOOTP broadcast 1
1005 04:29:25.537448 DHCP client bound to address 192.168.6.27 (233 ms)
1006 04:29:25.538246 Sending with 10 millisecond of delay
1008 04:29:27.214451 => setenv serverip 192.168.6.2
1009 04:29:27.225209 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1010 04:29:27.226083 setenv serverip 192.168.6.2
1011 04:29:27.226773 Sending with 10 millisecond of delay
1013 04:29:30.949566 => tftpboot 0x01080000 950831/tftp-deploy-otq453dv/kernel/uImage
1014 04:29:30.960322 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1015 04:29:30.961120 tftpboot 0x01080000 950831/tftp-deploy-otq453dv/kernel/uImage
1016 04:29:30.961561 Speed: 1000, full duplex
1017 04:29:30.961975 Using ethernet@ff3f0000 device
1018 04:29:30.962971 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1019 04:29:30.968496 Filename '950831/tftp-deploy-otq453dv/kernel/uImage'.
1020 04:29:30.972566 Load address: 0x1080000
1021 04:29:33.811634 Loading: *################################################## 43.6 MiB
1022 04:29:33.812314 15.3 MiB/s
1023 04:29:33.812761 done
1024 04:29:33.816133 Bytes transferred = 45713984 (2b98a40 hex)
1025 04:29:33.816983 Sending with 10 millisecond of delay
1027 04:29:38.503437 => tftpboot 0x08000000 950831/tftp-deploy-otq453dv/ramdisk/ramdisk.cpio.gz.uboot
1028 04:29:38.514253 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1029 04:29:38.515059 tftpboot 0x08000000 950831/tftp-deploy-otq453dv/ramdisk/ramdisk.cpio.gz.uboot
1030 04:29:38.515502 Speed: 1000, full duplex
1031 04:29:38.515917 Using ethernet@ff3f0000 device
1032 04:29:38.516746 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1033 04:29:38.528517 Filename '950831/tftp-deploy-otq453dv/ramdisk/ramdisk.cpio.gz.uboot'.
1034 04:29:38.528992 Load address: 0x8000000
1035 04:29:43.166928 Loading: *##################### UDP wrong checksum 000000ff 0000b730
1036 04:29:43.175653 UDP wrong checksum 000000ff 00004523
1037 04:29:44.956989 T ############################ UDP wrong checksum 00000005 0000094f
1038 04:29:49.959591 T UDP wrong checksum 00000005 0000094f
1039 04:29:59.960057 T UDP wrong checksum 00000005 0000094f
1040 04:30:19.965356 T T T T T UDP wrong checksum 00000005 0000094f
1041 04:30:34.970481 T T
1042 04:30:34.971147 Retry count exceeded; starting again
1044 04:30:34.972771 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1047 04:30:34.974930 end: 2.4 uboot-commands (duration 00:01:46) [common]
1049 04:30:34.976796 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1051 04:30:34.977969 end: 2 uboot-action (duration 00:01:46) [common]
1053 04:30:34.979646 Cleaning after the job
1054 04:30:34.980285 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/ramdisk
1055 04:30:34.981884 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/kernel
1056 04:30:35.029906 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/dtb
1057 04:30:35.030812 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/nfsrootfs
1058 04:30:35.204847 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950831/tftp-deploy-otq453dv/modules
1059 04:30:35.224895 start: 4.1 power-off (timeout 00:00:30) [common]
1060 04:30:35.225569 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1061 04:30:35.264457 >> OK - accepted request
1062 04:30:35.266577 Returned 0 in 0 seconds
1063 04:30:35.367391 end: 4.1 power-off (duration 00:00:00) [common]
1065 04:30:35.368486 start: 4.2 read-feedback (timeout 00:10:00) [common]
1066 04:30:35.369171 Listened to connection for namespace 'common' for up to 1s
1067 04:30:36.370101 Finalising connection for namespace 'common'
1068 04:30:36.370578 Disconnecting from shell: Finalise
1069 04:30:36.370860 =>
1070 04:30:36.471593 end: 4.2 read-feedback (duration 00:00:01) [common]
1071 04:30:36.472087 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950831
1072 04:30:39.465172 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950831
1073 04:30:39.465775 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.