Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:03:49.264999 lava-dispatcher, installed at version: 2024.01
2 04:03:49.265774 start: 0 validate
3 04:03:49.266259 Start time: 2024-11-07 04:03:49.266229+00:00 (UTC)
4 04:03:49.266800 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:03:49.267344 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 04:03:49.311408 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:03:49.311952 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 04:03:49.345158 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:03:49.345773 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:03:49.378331 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:03:49.378823 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:03:49.409549 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 04:03:49.410159 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 04:03:49.460086 validate duration: 0.19
16 04:03:49.461588 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:03:49.462173 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:03:49.462745 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:03:49.463682 Not decompressing ramdisk as can be used compressed.
20 04:03:49.464481 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 04:03:49.464994 saving as /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/ramdisk/initrd.cpio.gz
22 04:03:49.465497 total size: 5628140 (5 MB)
23 04:03:49.508243 progress 0 % (0 MB)
24 04:03:49.515965 progress 5 % (0 MB)
25 04:03:49.525169 progress 10 % (0 MB)
26 04:03:49.533087 progress 15 % (0 MB)
27 04:03:49.541485 progress 20 % (1 MB)
28 04:03:49.546424 progress 25 % (1 MB)
29 04:03:49.550621 progress 30 % (1 MB)
30 04:03:49.554707 progress 35 % (1 MB)
31 04:03:49.558544 progress 40 % (2 MB)
32 04:03:49.562624 progress 45 % (2 MB)
33 04:03:49.566378 progress 50 % (2 MB)
34 04:03:49.570664 progress 55 % (2 MB)
35 04:03:49.574823 progress 60 % (3 MB)
36 04:03:49.578597 progress 65 % (3 MB)
37 04:03:49.582791 progress 70 % (3 MB)
38 04:03:49.586817 progress 75 % (4 MB)
39 04:03:49.591104 progress 80 % (4 MB)
40 04:03:49.594869 progress 85 % (4 MB)
41 04:03:49.599077 progress 90 % (4 MB)
42 04:03:49.603043 progress 95 % (5 MB)
43 04:03:49.606345 progress 100 % (5 MB)
44 04:03:49.607001 5 MB downloaded in 0.14 s (37.93 MB/s)
45 04:03:49.607565 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:03:49.608498 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:03:49.608795 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:03:49.609071 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:03:49.609552 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/kernel/Image
51 04:03:49.609805 saving as /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/kernel/Image
52 04:03:49.610019 total size: 45713920 (43 MB)
53 04:03:49.610229 No compression specified
54 04:03:49.649430 progress 0 % (0 MB)
55 04:03:49.677672 progress 5 % (2 MB)
56 04:03:49.706056 progress 10 % (4 MB)
57 04:03:49.734969 progress 15 % (6 MB)
58 04:03:49.763289 progress 20 % (8 MB)
59 04:03:49.791826 progress 25 % (10 MB)
60 04:03:49.820097 progress 30 % (13 MB)
61 04:03:49.848610 progress 35 % (15 MB)
62 04:03:49.877177 progress 40 % (17 MB)
63 04:03:49.905558 progress 45 % (19 MB)
64 04:03:49.934082 progress 50 % (21 MB)
65 04:03:49.962649 progress 55 % (24 MB)
66 04:03:49.991058 progress 60 % (26 MB)
67 04:03:50.019711 progress 65 % (28 MB)
68 04:03:50.048161 progress 70 % (30 MB)
69 04:03:50.076597 progress 75 % (32 MB)
70 04:03:50.105270 progress 80 % (34 MB)
71 04:03:50.133153 progress 85 % (37 MB)
72 04:03:50.161602 progress 90 % (39 MB)
73 04:03:50.189866 progress 95 % (41 MB)
74 04:03:50.218197 progress 100 % (43 MB)
75 04:03:50.218741 43 MB downloaded in 0.61 s (71.62 MB/s)
76 04:03:50.219227 end: 1.2.1 http-download (duration 00:00:01) [common]
78 04:03:50.220079 end: 1.2 download-retry (duration 00:00:01) [common]
79 04:03:50.220365 start: 1.3 download-retry (timeout 00:09:59) [common]
80 04:03:50.220635 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 04:03:50.221106 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 04:03:50.221378 saving as /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/dtb/meson-g12b-a311d-libretech-cc.dtb
83 04:03:50.221589 total size: 54703 (0 MB)
84 04:03:50.221800 No compression specified
85 04:03:50.264271 progress 59 % (0 MB)
86 04:03:50.265125 progress 100 % (0 MB)
87 04:03:50.265695 0 MB downloaded in 0.04 s (1.18 MB/s)
88 04:03:50.266183 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:03:50.267003 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:03:50.267265 start: 1.4 download-retry (timeout 00:09:59) [common]
92 04:03:50.267529 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 04:03:50.267997 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 04:03:50.268257 saving as /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/nfsrootfs/full.rootfs.tar
95 04:03:50.268463 total size: 474398908 (452 MB)
96 04:03:50.268675 Using unxz to decompress xz
97 04:03:50.307092 progress 0 % (0 MB)
98 04:03:51.393457 progress 5 % (22 MB)
99 04:03:52.835048 progress 10 % (45 MB)
100 04:03:53.270677 progress 15 % (67 MB)
101 04:03:54.040177 progress 20 % (90 MB)
102 04:03:54.562294 progress 25 % (113 MB)
103 04:03:54.902878 progress 30 % (135 MB)
104 04:03:55.504783 progress 35 % (158 MB)
105 04:03:56.413230 progress 40 % (181 MB)
106 04:03:57.270492 progress 45 % (203 MB)
107 04:03:57.910969 progress 50 % (226 MB)
108 04:03:58.573815 progress 55 % (248 MB)
109 04:03:59.802084 progress 60 % (271 MB)
110 04:04:01.201888 progress 65 % (294 MB)
111 04:04:02.829108 progress 70 % (316 MB)
112 04:04:05.955510 progress 75 % (339 MB)
113 04:04:08.409994 progress 80 % (361 MB)
114 04:04:11.291809 progress 85 % (384 MB)
115 04:04:14.461999 progress 90 % (407 MB)
116 04:04:17.612181 progress 95 % (429 MB)
117 04:04:20.743451 progress 100 % (452 MB)
118 04:04:20.756321 452 MB downloaded in 30.49 s (14.84 MB/s)
119 04:04:20.757276 end: 1.4.1 http-download (duration 00:00:30) [common]
121 04:04:20.759070 end: 1.4 download-retry (duration 00:00:30) [common]
122 04:04:20.759657 start: 1.5 download-retry (timeout 00:09:29) [common]
123 04:04:20.760301 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 04:04:20.761473 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/modules.tar.xz
125 04:04:20.762008 saving as /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/modules/modules.tar
126 04:04:20.762478 total size: 11618152 (11 MB)
127 04:04:20.762954 Using unxz to decompress xz
128 04:04:20.811965 progress 0 % (0 MB)
129 04:04:20.877716 progress 5 % (0 MB)
130 04:04:20.953233 progress 10 % (1 MB)
131 04:04:21.059044 progress 15 % (1 MB)
132 04:04:21.157735 progress 20 % (2 MB)
133 04:04:21.236406 progress 25 % (2 MB)
134 04:04:21.310729 progress 30 % (3 MB)
135 04:04:21.390319 progress 35 % (3 MB)
136 04:04:21.462038 progress 40 % (4 MB)
137 04:04:21.536396 progress 45 % (5 MB)
138 04:04:21.620114 progress 50 % (5 MB)
139 04:04:21.700295 progress 55 % (6 MB)
140 04:04:21.779533 progress 60 % (6 MB)
141 04:04:21.859193 progress 65 % (7 MB)
142 04:04:21.938588 progress 70 % (7 MB)
143 04:04:22.015607 progress 75 % (8 MB)
144 04:04:22.098136 progress 80 % (8 MB)
145 04:04:22.176786 progress 85 % (9 MB)
146 04:04:22.258712 progress 90 % (10 MB)
147 04:04:22.331019 progress 95 % (10 MB)
148 04:04:22.407111 progress 100 % (11 MB)
149 04:04:22.419558 11 MB downloaded in 1.66 s (6.69 MB/s)
150 04:04:22.420864 end: 1.5.1 http-download (duration 00:00:02) [common]
152 04:04:22.423055 end: 1.5 download-retry (duration 00:00:02) [common]
153 04:04:22.423747 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 04:04:22.424529 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 04:04:37.826097 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/950761/extract-nfsrootfs-3zyqqua9
156 04:04:37.826703 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 04:04:37.826992 start: 1.6.2 lava-overlay (timeout 00:09:12) [common]
158 04:04:37.827758 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2
159 04:04:37.828253 makedir: /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin
160 04:04:37.828583 makedir: /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/tests
161 04:04:37.828893 makedir: /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/results
162 04:04:37.829223 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-add-keys
163 04:04:37.829745 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-add-sources
164 04:04:37.830246 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-background-process-start
165 04:04:37.830738 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-background-process-stop
166 04:04:37.831259 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-common-functions
167 04:04:37.831748 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-echo-ipv4
168 04:04:37.832277 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-install-packages
169 04:04:37.832771 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-installed-packages
170 04:04:37.833309 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-os-build
171 04:04:37.833809 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-probe-channel
172 04:04:37.834284 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-probe-ip
173 04:04:37.834752 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-target-ip
174 04:04:37.835214 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-target-mac
175 04:04:37.835681 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-target-storage
176 04:04:37.836183 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-test-case
177 04:04:37.836662 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-test-event
178 04:04:37.837128 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-test-feedback
179 04:04:37.837592 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-test-raise
180 04:04:37.838057 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-test-reference
181 04:04:37.838546 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-test-runner
182 04:04:37.839063 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-test-set
183 04:04:37.839576 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-test-shell
184 04:04:37.840085 Updating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-install-packages (oe)
185 04:04:37.840624 Updating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/bin/lava-installed-packages (oe)
186 04:04:37.841061 Creating /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/environment
187 04:04:37.841431 LAVA metadata
188 04:04:37.841687 - LAVA_JOB_ID=950761
189 04:04:37.841897 - LAVA_DISPATCHER_IP=192.168.6.2
190 04:04:37.842241 start: 1.6.2.1 ssh-authorize (timeout 00:09:12) [common]
191 04:04:37.843177 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 04:04:37.843483 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:12) [common]
193 04:04:37.843692 skipped lava-vland-overlay
194 04:04:37.843932 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 04:04:37.844214 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:12) [common]
196 04:04:37.844435 skipped lava-multinode-overlay
197 04:04:37.844679 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 04:04:37.844930 start: 1.6.2.4 test-definition (timeout 00:09:12) [common]
199 04:04:37.845177 Loading test definitions
200 04:04:37.845452 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:12) [common]
201 04:04:37.845671 Using /lava-950761 at stage 0
202 04:04:37.846791 uuid=950761_1.6.2.4.1 testdef=None
203 04:04:37.847089 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 04:04:37.847349 start: 1.6.2.4.2 test-overlay (timeout 00:09:12) [common]
205 04:04:37.849112 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 04:04:37.849900 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:12) [common]
208 04:04:37.852025 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 04:04:37.852858 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:12) [common]
211 04:04:37.854887 runner path: /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 950761_1.6.2.4.1
212 04:04:37.855439 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 04:04:37.856224 Creating lava-test-runner.conf files
215 04:04:37.856427 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950761/lava-overlay-7_xsn5y2/lava-950761/0 for stage 0
216 04:04:37.856758 - 0_v4l2-decoder-conformance-h264
217 04:04:37.857090 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 04:04:37.857357 start: 1.6.2.5 compress-overlay (timeout 00:09:12) [common]
219 04:04:37.878535 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 04:04:37.878871 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:12) [common]
221 04:04:37.879126 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 04:04:37.879386 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 04:04:37.879645 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:12) [common]
224 04:04:38.492120 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 04:04:38.492613 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 04:04:38.492864 extracting modules file /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950761/extract-nfsrootfs-3zyqqua9
227 04:04:39.848658 extracting modules file /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950761/extract-overlay-ramdisk-3aa3lngr/ramdisk
228 04:04:41.247213 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 04:04:41.247695 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 04:04:41.247974 [common] Applying overlay to NFS
231 04:04:41.248215 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950761/compress-overlay-y0slfr1y/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950761/extract-nfsrootfs-3zyqqua9
232 04:04:41.277130 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 04:04:41.277489 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 04:04:41.277762 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 04:04:41.277992 Converting downloaded kernel to a uImage
236 04:04:41.278309 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/kernel/Image /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/kernel/uImage
237 04:04:41.755397 output: Image Name:
238 04:04:41.755817 output: Created: Thu Nov 7 04:04:41 2024
239 04:04:41.756089 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 04:04:41.756316 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 04:04:41.756525 output: Load Address: 01080000
242 04:04:41.756729 output: Entry Point: 01080000
243 04:04:41.756932 output:
244 04:04:41.757275 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 04:04:41.757552 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 04:04:41.757833 start: 1.6.7 configure-preseed-file (timeout 00:09:08) [common]
247 04:04:41.758097 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 04:04:41.758368 start: 1.6.8 compress-ramdisk (timeout 00:09:08) [common]
249 04:04:41.758632 Building ramdisk /var/lib/lava/dispatcher/tmp/950761/extract-overlay-ramdisk-3aa3lngr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950761/extract-overlay-ramdisk-3aa3lngr/ramdisk
250 04:04:43.866914 >> 166825 blocks
251 04:04:51.560205 Adding RAMdisk u-boot header.
252 04:04:51.560861 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950761/extract-overlay-ramdisk-3aa3lngr/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950761/extract-overlay-ramdisk-3aa3lngr/ramdisk.cpio.gz.uboot
253 04:04:51.821084 output: Image Name:
254 04:04:51.821479 output: Created: Thu Nov 7 04:04:51 2024
255 04:04:51.821693 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 04:04:51.821902 output: Data Size: 23431733 Bytes = 22882.55 KiB = 22.35 MiB
257 04:04:51.822105 output: Load Address: 00000000
258 04:04:51.822305 output: Entry Point: 00000000
259 04:04:51.822501 output:
260 04:04:51.823174 rename /var/lib/lava/dispatcher/tmp/950761/extract-overlay-ramdisk-3aa3lngr/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/ramdisk/ramdisk.cpio.gz.uboot
261 04:04:51.823597 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 04:04:51.823886 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
263 04:04:51.824469 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:58) [common]
264 04:04:51.824981 No LXC device requested
265 04:04:51.825556 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 04:04:51.826122 start: 1.8 deploy-device-env (timeout 00:08:58) [common]
267 04:04:51.826669 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 04:04:51.827127 Checking files for TFTP limit of 4294967296 bytes.
269 04:04:51.830287 end: 1 tftp-deploy (duration 00:01:02) [common]
270 04:04:51.830992 start: 2 uboot-action (timeout 00:05:00) [common]
271 04:04:51.831621 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 04:04:51.832292 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 04:04:51.832934 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 04:04:51.833593 Using kernel file from prepare-kernel: 950761/tftp-deploy-i5tz872v/kernel/uImage
275 04:04:51.834403 substitutions:
276 04:04:51.834993 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 04:04:51.835513 - {DTB_ADDR}: 0x01070000
278 04:04:51.836047 - {DTB}: 950761/tftp-deploy-i5tz872v/dtb/meson-g12b-a311d-libretech-cc.dtb
279 04:04:51.836542 - {INITRD}: 950761/tftp-deploy-i5tz872v/ramdisk/ramdisk.cpio.gz.uboot
280 04:04:51.837025 - {KERNEL_ADDR}: 0x01080000
281 04:04:51.837512 - {KERNEL}: 950761/tftp-deploy-i5tz872v/kernel/uImage
282 04:04:51.838001 - {LAVA_MAC}: None
283 04:04:51.838552 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/950761/extract-nfsrootfs-3zyqqua9
284 04:04:51.839041 - {NFS_SERVER_IP}: 192.168.6.2
285 04:04:51.839513 - {PRESEED_CONFIG}: None
286 04:04:51.840012 - {PRESEED_LOCAL}: None
287 04:04:51.840501 - {RAMDISK_ADDR}: 0x08000000
288 04:04:51.840969 - {RAMDISK}: 950761/tftp-deploy-i5tz872v/ramdisk/ramdisk.cpio.gz.uboot
289 04:04:51.841450 - {ROOT_PART}: None
290 04:04:51.841932 - {ROOT}: None
291 04:04:51.842456 - {SERVER_IP}: 192.168.6.2
292 04:04:51.842982 - {TEE_ADDR}: 0x83000000
293 04:04:51.843512 - {TEE}: None
294 04:04:51.844085 Parsed boot commands:
295 04:04:51.844625 - setenv autoload no
296 04:04:51.845153 - setenv initrd_high 0xffffffff
297 04:04:51.845696 - setenv fdt_high 0xffffffff
298 04:04:51.846208 - dhcp
299 04:04:51.846716 - setenv serverip 192.168.6.2
300 04:04:51.847249 - tftpboot 0x01080000 950761/tftp-deploy-i5tz872v/kernel/uImage
301 04:04:51.847757 - tftpboot 0x08000000 950761/tftp-deploy-i5tz872v/ramdisk/ramdisk.cpio.gz.uboot
302 04:04:51.848311 - tftpboot 0x01070000 950761/tftp-deploy-i5tz872v/dtb/meson-g12b-a311d-libretech-cc.dtb
303 04:04:51.848836 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950761/extract-nfsrootfs-3zyqqua9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 04:04:51.849401 - bootm 0x01080000 0x08000000 0x01070000
305 04:04:51.850074 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 04:04:51.852044 start: 2.3 connect-device (timeout 00:05:00) [common]
308 04:04:51.852626 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 04:04:51.869304 Setting prompt string to ['lava-test: # ']
310 04:04:51.871197 end: 2.3 connect-device (duration 00:00:00) [common]
311 04:04:51.872542 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 04:04:51.873258 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 04:04:51.873919 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 04:04:51.875264 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 04:04:51.911789 >> OK - accepted request
316 04:04:51.913933 Returned 0 in 0 seconds
317 04:04:52.015384 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 04:04:52.018013 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 04:04:52.018937 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 04:04:52.019752 Setting prompt string to ['Hit any key to stop autoboot']
322 04:04:52.020506 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 04:04:52.022836 Trying 192.168.56.21...
324 04:04:52.023514 Connected to conserv1.
325 04:04:52.024158 Escape character is '^]'.
326 04:04:52.024870
327 04:04:52.025453 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 04:04:52.025923
329 04:05:03.244053 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 04:05:03.244734 bl2_stage_init 0x01
331 04:05:03.245270 bl2_stage_init 0x81
332 04:05:03.249351 hw id: 0x0000 - pwm id 0x01
333 04:05:03.250299 bl2_stage_init 0xc1
334 04:05:03.250836 bl2_stage_init 0x02
335 04:05:03.251283
336 04:05:03.254972 L0:00000000
337 04:05:03.255536 L1:20000703
338 04:05:03.256076 L2:00008067
339 04:05:03.256529 L3:14000000
340 04:05:03.260507 B2:00402000
341 04:05:03.261364 B1:e0f83180
342 04:05:03.262187
343 04:05:03.262790 TE: 58159
344 04:05:03.263243
345 04:05:03.265963 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 04:05:03.266516
347 04:05:03.267037 Board ID = 1
348 04:05:03.271801 Set A53 clk to 24M
349 04:05:03.272330 Set A73 clk to 24M
350 04:05:03.272897 Set clk81 to 24M
351 04:05:03.277278 A53 clk: 1200 MHz
352 04:05:03.277837 A73 clk: 1200 MHz
353 04:05:03.278278 CLK81: 166.6M
354 04:05:03.278705 smccc: 00012ab4
355 04:05:03.283019 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 04:05:03.288450 board id: 1
357 04:05:03.294407 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 04:05:03.304989 fw parse done
359 04:05:03.310863 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 04:05:03.353544 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 04:05:03.364344 PIEI prepare done
362 04:05:03.364833 fastboot data load
363 04:05:03.365249 fastboot data verify
364 04:05:03.370078 verify result: 266
365 04:05:03.375709 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 04:05:03.376230 LPDDR4 probe
367 04:05:03.376636 ddr clk to 1584MHz
368 04:05:03.383710 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 04:05:03.420964
370 04:05:03.421501 dmc_version 0001
371 04:05:03.427691 Check phy result
372 04:05:03.433592 INFO : End of CA training
373 04:05:03.434241 INFO : End of initialization
374 04:05:03.439186 INFO : Training has run successfully!
375 04:05:03.439823 Check phy result
376 04:05:03.444853 INFO : End of initialization
377 04:05:03.445349 INFO : End of read enable training
378 04:05:03.450388 INFO : End of fine write leveling
379 04:05:03.456025 INFO : End of Write leveling coarse delay
380 04:05:03.456655 INFO : Training has run successfully!
381 04:05:03.457188 Check phy result
382 04:05:03.461604 INFO : End of initialization
383 04:05:03.462097 INFO : End of read dq deskew training
384 04:05:03.467143 INFO : End of MPR read delay center optimization
385 04:05:03.472865 INFO : End of write delay center optimization
386 04:05:03.478420 INFO : End of read delay center optimization
387 04:05:03.478907 INFO : End of max read latency training
388 04:05:03.484031 INFO : Training has run successfully!
389 04:05:03.484667 1D training succeed
390 04:05:03.493103 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 04:05:03.540814 Check phy result
392 04:05:03.541386 INFO : End of initialization
393 04:05:03.563192 INFO : End of 2D read delay Voltage center optimization
394 04:05:03.583330 INFO : End of 2D read delay Voltage center optimization
395 04:05:03.635308 INFO : End of 2D write delay Voltage center optimization
396 04:05:03.684489 INFO : End of 2D write delay Voltage center optimization
397 04:05:03.690087 INFO : Training has run successfully!
398 04:05:03.690737
399 04:05:03.691283 channel==0
400 04:05:03.695612 RxClkDly_Margin_A0==88 ps 9
401 04:05:03.696277 TxDqDly_Margin_A0==98 ps 10
402 04:05:03.701177 RxClkDly_Margin_A1==88 ps 9
403 04:05:03.701677 TxDqDly_Margin_A1==98 ps 10
404 04:05:03.702085 TrainedVREFDQ_A0==74
405 04:05:03.706892 TrainedVREFDQ_A1==74
406 04:05:03.707522 VrefDac_Margin_A0==25
407 04:05:03.708103 DeviceVref_Margin_A0==40
408 04:05:03.712457 VrefDac_Margin_A1==24
409 04:05:03.713083 DeviceVref_Margin_A1==40
410 04:05:03.713600
411 04:05:03.714115
412 04:05:03.718000 channel==1
413 04:05:03.718646 RxClkDly_Margin_A0==98 ps 10
414 04:05:03.719166 TxDqDly_Margin_A0==88 ps 9
415 04:05:03.723681 RxClkDly_Margin_A1==98 ps 10
416 04:05:03.724387 TxDqDly_Margin_A1==88 ps 9
417 04:05:03.729266 TrainedVREFDQ_A0==77
418 04:05:03.729939 TrainedVREFDQ_A1==77
419 04:05:03.730480 VrefDac_Margin_A0==22
420 04:05:03.734947 DeviceVref_Margin_A0==37
421 04:05:03.735595 VrefDac_Margin_A1==22
422 04:05:03.740416 DeviceVref_Margin_A1==37
423 04:05:03.741084
424 04:05:03.741618 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 04:05:03.742129
426 04:05:03.773953 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 04:05:03.774779 2D training succeed
428 04:05:03.779626 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 04:05:03.785132 auto size-- 65535DDR cs0 size: 2048MB
430 04:05:03.785764 DDR cs1 size: 2048MB
431 04:05:03.790820 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 04:05:03.791440 cs0 DataBus test pass
433 04:05:03.796332 cs1 DataBus test pass
434 04:05:03.796821 cs0 AddrBus test pass
435 04:05:03.797226 cs1 AddrBus test pass
436 04:05:03.797621
437 04:05:03.801942 100bdlr_step_size ps== 420
438 04:05:03.802575 result report
439 04:05:03.807580 boot times 0Enable ddr reg access
440 04:05:03.812929 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 04:05:03.825356 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 04:05:04.398502 0.0;M3 CHK:0;cm4_sp_mode 0
443 04:05:04.399302 MVN_1=0x00000000
444 04:05:04.403930 MVN_2=0x00000000
445 04:05:04.409638 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 04:05:04.410258 OPS=0x10
447 04:05:04.410784 ring efuse init
448 04:05:04.411307 chipver efuse init
449 04:05:04.417883 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 04:05:04.418548 [0.018960 Inits done]
451 04:05:04.419080 secure task start!
452 04:05:04.425425 high task start!
453 04:05:04.426013 low task start!
454 04:05:04.426536 run into bl31
455 04:05:04.432105 NOTICE: BL31: v1.3(release):4fc40b1
456 04:05:04.440110 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 04:05:04.440705 NOTICE: BL31: G12A normal boot!
458 04:05:04.465358 NOTICE: BL31: BL33 decompress pass
459 04:05:04.471021 ERROR: Error initializing runtime service opteed_fast
460 04:05:05.704200
461 04:05:05.705021
462 04:05:05.712391 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 04:05:05.712999
464 04:05:05.713536 Model: Libre Computer AML-A311D-CC Alta
465 04:05:05.920858 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 04:05:05.944370 DRAM: 2 GiB (effective 3.8 GiB)
467 04:05:06.087321 Core: 408 devices, 31 uclasses, devicetree: separate
468 04:05:06.092910 WDT: Not starting watchdog@f0d0
469 04:05:06.125309 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 04:05:06.137810 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 04:05:06.142929 ** Bad device specification mmc 0 **
472 04:05:06.153341 Card did not respond to voltage select! : -110
473 04:05:06.160725 ** Bad device specification mmc 0 **
474 04:05:06.161174 Couldn't find partition mmc 0
475 04:05:06.169118 Card did not respond to voltage select! : -110
476 04:05:06.174437 ** Bad device specification mmc 0 **
477 04:05:06.174846 Couldn't find partition mmc 0
478 04:05:06.179587 Error: could not access storage.
479 04:05:07.444070 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 04:05:07.444698 bl2_stage_init 0x01
481 04:05:07.445109 bl2_stage_init 0x81
482 04:05:07.449530 hw id: 0x0000 - pwm id 0x01
483 04:05:07.450017 bl2_stage_init 0xc1
484 04:05:07.450423 bl2_stage_init 0x02
485 04:05:07.450827
486 04:05:07.455083 L0:00000000
487 04:05:07.455542 L1:20000703
488 04:05:07.455944 L2:00008067
489 04:05:07.456386 L3:14000000
490 04:05:07.460709 B2:00402000
491 04:05:07.461157 B1:e0f83180
492 04:05:07.461552
493 04:05:07.461946 TE: 58167
494 04:05:07.462339
495 04:05:07.466340 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 04:05:07.466793
497 04:05:07.467193 Board ID = 1
498 04:05:07.472022 Set A53 clk to 24M
499 04:05:07.472468 Set A73 clk to 24M
500 04:05:07.472867 Set clk81 to 24M
501 04:05:07.477395 A53 clk: 1200 MHz
502 04:05:07.477833 A73 clk: 1200 MHz
503 04:05:07.478229 CLK81: 166.6M
504 04:05:07.478623 smccc: 00012abe
505 04:05:07.483052 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 04:05:07.488885 board id: 1
507 04:05:07.494824 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 04:05:07.505255 fw parse done
509 04:05:07.511145 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 04:05:07.553789 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 04:05:07.564668 PIEI prepare done
512 04:05:07.565112 fastboot data load
513 04:05:07.565515 fastboot data verify
514 04:05:07.570275 verify result: 266
515 04:05:07.575865 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 04:05:07.576348 LPDDR4 probe
517 04:05:07.576749 ddr clk to 1584MHz
518 04:05:07.583842 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 04:05:07.621181
520 04:05:07.621656 dmc_version 0001
521 04:05:07.627834 Check phy result
522 04:05:07.633710 INFO : End of CA training
523 04:05:07.634138 INFO : End of initialization
524 04:05:07.639287 INFO : Training has run successfully!
525 04:05:07.639730 Check phy result
526 04:05:07.644997 INFO : End of initialization
527 04:05:07.645634 INFO : End of read enable training
528 04:05:07.650542 INFO : End of fine write leveling
529 04:05:07.656153 INFO : End of Write leveling coarse delay
530 04:05:07.656742 INFO : Training has run successfully!
531 04:05:07.657271 Check phy result
532 04:05:07.661729 INFO : End of initialization
533 04:05:07.662309 INFO : End of read dq deskew training
534 04:05:07.667356 INFO : End of MPR read delay center optimization
535 04:05:07.672884 INFO : End of write delay center optimization
536 04:05:07.678512 INFO : End of read delay center optimization
537 04:05:07.679087 INFO : End of max read latency training
538 04:05:07.684123 INFO : Training has run successfully!
539 04:05:07.684684 1D training succeed
540 04:05:07.693369 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 04:05:07.740821 Check phy result
542 04:05:07.741439 INFO : End of initialization
543 04:05:07.762444 INFO : End of 2D read delay Voltage center optimization
544 04:05:07.782556 INFO : End of 2D read delay Voltage center optimization
545 04:05:07.834581 INFO : End of 2D write delay Voltage center optimization
546 04:05:07.883790 INFO : End of 2D write delay Voltage center optimization
547 04:05:07.889356 INFO : Training has run successfully!
548 04:05:07.889908
549 04:05:07.890448 channel==0
550 04:05:07.894949 RxClkDly_Margin_A0==88 ps 9
551 04:05:07.895517 TxDqDly_Margin_A0==98 ps 10
552 04:05:07.900566 RxClkDly_Margin_A1==88 ps 9
553 04:05:07.901116 TxDqDly_Margin_A1==98 ps 10
554 04:05:07.901631 TrainedVREFDQ_A0==74
555 04:05:07.906073 TrainedVREFDQ_A1==75
556 04:05:07.906635 VrefDac_Margin_A0==25
557 04:05:07.907147 DeviceVref_Margin_A0==40
558 04:05:07.911681 VrefDac_Margin_A1==25
559 04:05:07.912277 DeviceVref_Margin_A1==39
560 04:05:07.912803
561 04:05:07.913327
562 04:05:07.917335 channel==1
563 04:05:07.917885 RxClkDly_Margin_A0==98 ps 10
564 04:05:07.918393 TxDqDly_Margin_A0==88 ps 9
565 04:05:07.922909 RxClkDly_Margin_A1==88 ps 9
566 04:05:07.923460 TxDqDly_Margin_A1==88 ps 9
567 04:05:07.928476 TrainedVREFDQ_A0==77
568 04:05:07.929027 TrainedVREFDQ_A1==77
569 04:05:07.929538 VrefDac_Margin_A0==22
570 04:05:07.934054 DeviceVref_Margin_A0==37
571 04:05:07.934611 VrefDac_Margin_A1==24
572 04:05:07.939691 DeviceVref_Margin_A1==37
573 04:05:07.940260
574 04:05:07.940774 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 04:05:07.941281
576 04:05:07.973319 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 04:05:07.973951 2D training succeed
578 04:05:07.978877 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 04:05:07.984476 auto size-- 65535DDR cs0 size: 2048MB
580 04:05:07.985038 DDR cs1 size: 2048MB
581 04:05:07.990116 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 04:05:07.990685 cs0 DataBus test pass
583 04:05:07.995683 cs1 DataBus test pass
584 04:05:07.996292 cs0 AddrBus test pass
585 04:05:07.996805 cs1 AddrBus test pass
586 04:05:07.997311
587 04:05:08.001381 100bdlr_step_size ps== 420
588 04:05:08.001962 result report
589 04:05:08.006901 boot times 0Enable ddr reg access
590 04:05:08.012207 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 04:05:08.025553 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 04:05:08.597763 0.0;M3 CHK:0;cm4_sp_mode 0
593 04:05:08.598594 MVN_1=0x00000000
594 04:05:08.603137 MVN_2=0x00000000
595 04:05:08.608876 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 04:05:08.609511 OPS=0x10
597 04:05:08.610029 ring efuse init
598 04:05:08.610552 chipver efuse init
599 04:05:08.614498 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 04:05:08.620137 [0.018960 Inits done]
601 04:05:08.620656 secure task start!
602 04:05:08.621062 high task start!
603 04:05:08.624607 low task start!
604 04:05:08.625072 run into bl31
605 04:05:08.631356 NOTICE: BL31: v1.3(release):4fc40b1
606 04:05:08.639070 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 04:05:08.639564 NOTICE: BL31: G12A normal boot!
608 04:05:08.664444 NOTICE: BL31: BL33 decompress pass
609 04:05:08.670096 ERROR: Error initializing runtime service opteed_fast
610 04:05:09.903043
611 04:05:09.903690
612 04:05:09.911357 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 04:05:09.911838
614 04:05:09.912303 Model: Libre Computer AML-A311D-CC Alta
615 04:05:10.119808 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 04:05:10.143101 DRAM: 2 GiB (effective 3.8 GiB)
617 04:05:10.286162 Core: 408 devices, 31 uclasses, devicetree: separate
618 04:05:10.291935 WDT: Not starting watchdog@f0d0
619 04:05:10.324320 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 04:05:10.336725 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 04:05:10.341817 ** Bad device specification mmc 0 **
622 04:05:10.352031 Card did not respond to voltage select! : -110
623 04:05:10.359697 ** Bad device specification mmc 0 **
624 04:05:10.360185 Couldn't find partition mmc 0
625 04:05:10.368080 Card did not respond to voltage select! : -110
626 04:05:10.373577 ** Bad device specification mmc 0 **
627 04:05:10.374030 Couldn't find partition mmc 0
628 04:05:10.378624 Error: could not access storage.
629 04:05:10.722054 Net: eth0: ethernet@ff3f0000
630 04:05:10.722493 starting USB...
631 04:05:10.973880 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 04:05:10.974321 Starting the controller
633 04:05:10.980772 USB XHCI 1.10
634 04:05:12.696117 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 04:05:12.696692 bl2_stage_init 0x01
636 04:05:12.696958 bl2_stage_init 0x81
637 04:05:12.699612 hw id: 0x0000 - pwm id 0x01
638 04:05:12.699895 bl2_stage_init 0xc1
639 04:05:12.700168 bl2_stage_init 0x02
640 04:05:12.700411
641 04:05:12.705297 L0:00000000
642 04:05:12.705837 L1:20000703
643 04:05:12.706271 L2:00008067
644 04:05:12.706684 L3:14000000
645 04:05:12.710942 B2:00402000
646 04:05:12.711431 B1:e0f83180
647 04:05:12.711855
648 04:05:12.712318 TE: 58124
649 04:05:12.712735
650 04:05:12.991392 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 04:05:12.992048
652 04:05:12.992505 Board ID = 1
653 04:05:12.992934 Set A53 clk to 24M
654 04:05:12.993351 Set A73 clk to 24M
655 04:05:12.993761 Set clk81 to 24M
656 04:05:12.994171 A53 clk: 1200 MHz
657 04:05:12.994779 A73 clk: 1200 MHz
658 04:05:12.995218 CLK81: 166.6M
659 04:05:12.995636 smccc: 00012a91
660 04:05:12.996065 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 04:05:12.996479 board id: 1
662 04:05:12.996885 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 04:05:12.997296 fw parse done
664 04:05:12.997701 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 04:05:12.998106 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 04:05:12.998504 PIEI prepare done
667 04:05:12.998897 fastboot data load
668 04:05:12.999298 fastboot data verify
669 04:05:12.999697 verify result: 266
670 04:05:13.000146 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 04:05:13.000602 LPDDR4 probe
672 04:05:13.001032 ddr clk to 1584MHz
673 04:05:13.001439 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 04:05:13.001836
675 04:05:13.002232 dmc_version 0001
676 04:05:13.002626 Check phy result
677 04:05:13.003017 INFO : End of CA training
678 04:05:13.003407 INFO : End of initialization
679 04:05:13.003799 INFO : Training has run successfully!
680 04:05:13.004227 Check phy result
681 04:05:13.004627 INFO : End of initialization
682 04:05:13.005022 INFO : End of read enable training
683 04:05:13.005416 INFO : End of fine write leveling
684 04:05:13.005807 INFO : End of Write leveling coarse delay
685 04:05:13.006199 INFO : Training has run successfully!
686 04:05:13.006591 Check phy result
687 04:05:13.006985 INFO : End of initialization
688 04:05:13.007768 INFO : End of read dq deskew training
689 04:05:13.008247 INFO : End of MPR read delay center optimization
690 04:05:13.008660 INFO : End of write delay center optimization
691 04:05:13.009059 INFO : End of read delay center optimization
692 04:05:13.009447 INFO : End of max read latency training
693 04:05:13.009843 INFO : Training has run successfully!
694 04:05:13.010233 1D training succeed
695 04:05:13.010635 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 04:05:13.011030 Check phy result
697 04:05:13.011421 INFO : End of initialization
698 04:05:13.012980 INFO : End of 2D read delay Voltage center optimization
699 04:05:13.033393 INFO : End of 2D read delay Voltage center optimization
700 04:05:13.085477 INFO : End of 2D write delay Voltage center optimization
701 04:05:13.134760 INFO : End of 2D write delay Voltage center optimization
702 04:05:13.140294 INFO : Training has run successfully!
703 04:05:13.140823
704 04:05:13.141261 channel==0
705 04:05:13.145848 RxClkDly_Margin_A0==88 ps 9
706 04:05:13.146361 TxDqDly_Margin_A0==98 ps 10
707 04:05:13.149212 RxClkDly_Margin_A1==88 ps 9
708 04:05:13.149715 TxDqDly_Margin_A1==98 ps 10
709 04:05:13.154720 TrainedVREFDQ_A0==74
710 04:05:13.155226 TrainedVREFDQ_A1==74
711 04:05:13.155653 VrefDac_Margin_A0==25
712 04:05:13.160391 DeviceVref_Margin_A0==40
713 04:05:13.160896 VrefDac_Margin_A1==25
714 04:05:13.165990 DeviceVref_Margin_A1==40
715 04:05:13.166485
716 04:05:13.166911
717 04:05:13.167320 channel==1
718 04:05:13.167721 RxClkDly_Margin_A0==88 ps 9
719 04:05:13.169472 TxDqDly_Margin_A0==88 ps 9
720 04:05:13.175088 RxClkDly_Margin_A1==98 ps 10
721 04:05:13.175594 TxDqDly_Margin_A1==88 ps 9
722 04:05:13.176051 TrainedVREFDQ_A0==77
723 04:05:13.180559 TrainedVREFDQ_A1==77
724 04:05:13.181052 VrefDac_Margin_A0==22
725 04:05:13.186253 DeviceVref_Margin_A0==37
726 04:05:13.186747 VrefDac_Margin_A1==22
727 04:05:13.187165 DeviceVref_Margin_A1==37
728 04:05:13.187575
729 04:05:13.195219 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 04:05:13.195723
731 04:05:13.221107 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 04:05:13.226645 2D training succeed
733 04:05:13.232252 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 04:05:13.232752 auto size-- 65535DDR cs0 size: 2048MB
735 04:05:13.237830 DDR cs1 size: 2048MB
736 04:05:13.238332 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 04:05:13.243437 cs0 DataBus test pass
738 04:05:13.243932 cs1 DataBus test pass
739 04:05:13.249017 cs0 AddrBus test pass
740 04:05:13.249523 cs1 AddrBus test pass
741 04:05:13.249944
742 04:05:13.250358 100bdlr_step_size ps== 420
743 04:05:13.254620 result report
744 04:05:13.255106 boot times 0Enable ddr reg access
745 04:05:13.263034 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 04:05:13.276386 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 04:05:13.850181 0.0;M3 CHK:0;cm4_sp_mode 0
748 04:05:13.850808 MVN_1=0x00000000
749 04:05:13.855613 MVN_2=0x00000000
750 04:05:13.861342 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 04:05:13.861890 OPS=0x10
752 04:05:13.862294 ring efuse init
753 04:05:13.862682 chipver efuse init
754 04:05:13.866939 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 04:05:13.872499 [0.018961 Inits done]
756 04:05:13.872977 secure task start!
757 04:05:13.873373 high task start!
758 04:05:13.877054 low task start!
759 04:05:13.877520 run into bl31
760 04:05:13.883798 NOTICE: BL31: v1.3(release):4fc40b1
761 04:05:13.891549 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 04:05:13.892055 NOTICE: BL31: G12A normal boot!
763 04:05:13.916961 NOTICE: BL31: BL33 decompress pass
764 04:05:13.922551 ERROR: Error initializing runtime service opteed_fast
765 04:05:15.155557
766 04:05:15.156214
767 04:05:15.163894 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 04:05:15.164409
769 04:05:15.164837 Model: Libre Computer AML-A311D-CC Alta
770 04:05:15.372328 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 04:05:15.395744 DRAM: 2 GiB (effective 3.8 GiB)
772 04:05:15.538737 Core: 408 devices, 31 uclasses, devicetree: separate
773 04:05:15.544538 WDT: Not starting watchdog@f0d0
774 04:05:15.576831 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 04:05:15.589191 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 04:05:15.594236 ** Bad device specification mmc 0 **
777 04:05:15.604552 Card did not respond to voltage select! : -110
778 04:05:15.612247 ** Bad device specification mmc 0 **
779 04:05:15.612728 Couldn't find partition mmc 0
780 04:05:15.620544 Card did not respond to voltage select! : -110
781 04:05:15.626201 ** Bad device specification mmc 0 **
782 04:05:15.626690 Couldn't find partition mmc 0
783 04:05:15.631127 Error: could not access storage.
784 04:05:15.973682 Net: eth0: ethernet@ff3f0000
785 04:05:15.974294 starting USB...
786 04:05:16.225479 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 04:05:16.226078 Starting the controller
788 04:05:16.232443 USB XHCI 1.10
789 04:05:18.395837 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 04:05:18.396498 bl2_stage_init 0x01
791 04:05:18.396931 bl2_stage_init 0x81
792 04:05:18.401384 hw id: 0x0000 - pwm id 0x01
793 04:05:18.401862 bl2_stage_init 0xc1
794 04:05:18.402281 bl2_stage_init 0x02
795 04:05:18.402693
796 04:05:18.406958 L0:00000000
797 04:05:18.407424 L1:20000703
798 04:05:18.407839 L2:00008067
799 04:05:18.408286 L3:14000000
800 04:05:18.412672 B2:00402000
801 04:05:18.413157 B1:e0f83180
802 04:05:18.413573
803 04:05:18.413981 TE: 58159
804 04:05:18.414388
805 04:05:18.418274 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 04:05:18.418757
807 04:05:18.419172 Board ID = 1
808 04:05:18.423727 Set A53 clk to 24M
809 04:05:18.424225 Set A73 clk to 24M
810 04:05:18.424640 Set clk81 to 24M
811 04:05:18.429325 A53 clk: 1200 MHz
812 04:05:18.429789 A73 clk: 1200 MHz
813 04:05:18.430198 CLK81: 166.6M
814 04:05:18.430599 smccc: 00012ab5
815 04:05:18.435010 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 04:05:18.440524 board id: 1
817 04:05:18.446631 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 04:05:18.457004 fw parse done
819 04:05:18.463000 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 04:05:18.505679 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 04:05:18.516647 PIEI prepare done
822 04:05:18.517126 fastboot data load
823 04:05:18.517546 fastboot data verify
824 04:05:18.522232 verify result: 266
825 04:05:18.527798 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 04:05:18.528323 LPDDR4 probe
827 04:05:18.528741 ddr clk to 1584MHz
828 04:05:18.535845 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 04:05:18.573107
830 04:05:18.573628 dmc_version 0001
831 04:05:18.579865 Check phy result
832 04:05:18.585633 INFO : End of CA training
833 04:05:18.586107 INFO : End of initialization
834 04:05:18.591262 INFO : Training has run successfully!
835 04:05:18.591723 Check phy result
836 04:05:18.596832 INFO : End of initialization
837 04:05:18.597290 INFO : End of read enable training
838 04:05:18.602466 INFO : End of fine write leveling
839 04:05:18.608058 INFO : End of Write leveling coarse delay
840 04:05:18.608523 INFO : Training has run successfully!
841 04:05:18.608937 Check phy result
842 04:05:18.613653 INFO : End of initialization
843 04:05:18.614107 INFO : End of read dq deskew training
844 04:05:18.619254 INFO : End of MPR read delay center optimization
845 04:05:18.624826 INFO : End of write delay center optimization
846 04:05:18.630417 INFO : End of read delay center optimization
847 04:05:18.630879 INFO : End of max read latency training
848 04:05:18.636072 INFO : Training has run successfully!
849 04:05:18.636530 1D training succeed
850 04:05:18.645222 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 04:05:18.692794 Check phy result
852 04:05:18.693252 INFO : End of initialization
853 04:05:18.714389 INFO : End of 2D read delay Voltage center optimization
854 04:05:18.734504 INFO : End of 2D read delay Voltage center optimization
855 04:05:18.786423 INFO : End of 2D write delay Voltage center optimization
856 04:05:18.835676 INFO : End of 2D write delay Voltage center optimization
857 04:05:18.841268 INFO : Training has run successfully!
858 04:05:18.841721
859 04:05:18.842133 channel==0
860 04:05:18.846889 RxClkDly_Margin_A0==88 ps 9
861 04:05:18.847342 TxDqDly_Margin_A0==98 ps 10
862 04:05:18.850182 RxClkDly_Margin_A1==88 ps 9
863 04:05:18.850639 TxDqDly_Margin_A1==98 ps 10
864 04:05:18.855876 TrainedVREFDQ_A0==74
865 04:05:18.856391 TrainedVREFDQ_A1==74
866 04:05:18.861312 VrefDac_Margin_A0==25
867 04:05:18.861776 DeviceVref_Margin_A0==40
868 04:05:18.862169 VrefDac_Margin_A1==23
869 04:05:18.866909 DeviceVref_Margin_A1==40
870 04:05:18.867355
871 04:05:18.867745
872 04:05:18.868173 channel==1
873 04:05:18.868560 RxClkDly_Margin_A0==98 ps 10
874 04:05:18.870368 TxDqDly_Margin_A0==98 ps 10
875 04:05:18.875887 RxClkDly_Margin_A1==88 ps 9
876 04:05:18.876360 TxDqDly_Margin_A1==88 ps 9
877 04:05:18.876761 TrainedVREFDQ_A0==77
878 04:05:18.881496 TrainedVREFDQ_A1==77
879 04:05:18.881948 VrefDac_Margin_A0==22
880 04:05:18.887032 DeviceVref_Margin_A0==37
881 04:05:18.887477 VrefDac_Margin_A1==24
882 04:05:18.887865 DeviceVref_Margin_A1==37
883 04:05:18.888289
884 04:05:18.892737 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 04:05:18.893185
886 04:05:18.926184 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
887 04:05:18.926662 2D training succeed
888 04:05:18.931834 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 04:05:18.937432 auto size-- 65535DDR cs0 size: 2048MB
890 04:05:18.937882 DDR cs1 size: 2048MB
891 04:05:18.943050 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 04:05:18.943493 cs0 DataBus test pass
893 04:05:18.943883 cs1 DataBus test pass
894 04:05:18.948791 cs0 AddrBus test pass
895 04:05:18.949235 cs1 AddrBus test pass
896 04:05:18.949625
897 04:05:18.954255 100bdlr_step_size ps== 420
898 04:05:18.954725 result report
899 04:05:18.955117 boot times 0Enable ddr reg access
900 04:05:18.964143 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 04:05:18.977568 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 04:05:19.549764 0.0;M3 CHK:0;cm4_sp_mode 0
903 04:05:19.550394 MVN_1=0x00000000
904 04:05:19.555245 MVN_2=0x00000000
905 04:05:19.561063 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 04:05:19.561540 OPS=0x10
907 04:05:19.561960 ring efuse init
908 04:05:19.562363 chipver efuse init
909 04:05:19.569446 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 04:05:19.569957 [0.018961 Inits done]
911 04:05:19.570375 secure task start!
912 04:05:19.576751 high task start!
913 04:05:19.577210 low task start!
914 04:05:19.577619 run into bl31
915 04:05:19.583598 NOTICE: BL31: v1.3(release):4fc40b1
916 04:05:19.591188 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 04:05:19.591650 NOTICE: BL31: G12A normal boot!
918 04:05:19.616548 NOTICE: BL31: BL33 decompress pass
919 04:05:19.622218 ERROR: Error initializing runtime service opteed_fast
920 04:05:20.855390
921 04:05:20.856057
922 04:05:20.863644 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 04:05:20.864139
924 04:05:20.864560 Model: Libre Computer AML-A311D-CC Alta
925 04:05:21.072075 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 04:05:21.095396 DRAM: 2 GiB (effective 3.8 GiB)
927 04:05:21.238467 Core: 408 devices, 31 uclasses, devicetree: separate
928 04:05:21.244213 WDT: Not starting watchdog@f0d0
929 04:05:21.276392 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 04:05:21.288883 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 04:05:21.293822 ** Bad device specification mmc 0 **
932 04:05:21.304345 Card did not respond to voltage select! : -110
933 04:05:21.311821 ** Bad device specification mmc 0 **
934 04:05:21.312305 Couldn't find partition mmc 0
935 04:05:21.320273 Card did not respond to voltage select! : -110
936 04:05:21.325670 ** Bad device specification mmc 0 **
937 04:05:21.326130 Couldn't find partition mmc 0
938 04:05:21.330813 Error: could not access storage.
939 04:05:21.674333 Net: eth0: ethernet@ff3f0000
940 04:05:21.674928 starting USB...
941 04:05:21.926243 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 04:05:21.926775 Starting the controller
943 04:05:21.933238 USB XHCI 1.10
944 04:05:23.487167 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 04:05:23.495525 scanning usb for storage devices... 0 Storage Device(s) found
947 04:05:23.546719 Hit any key to stop autoboot: 1
948 04:05:23.547787 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
949 04:05:23.548198 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
950 04:05:23.548461 Setting prompt string to ['=>']
951 04:05:23.548717 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
952 04:05:23.562857 0
953 04:05:23.563567 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 04:05:23.563879 Sending with 10 millisecond of delay
956 04:05:24.698686 => setenv autoload no
957 04:05:24.709563 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
958 04:05:24.715007 setenv autoload no
959 04:05:24.715813 Sending with 10 millisecond of delay
961 04:05:26.512918 => setenv initrd_high 0xffffffff
962 04:05:26.523772 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
963 04:05:26.524743 setenv initrd_high 0xffffffff
964 04:05:26.525534 Sending with 10 millisecond of delay
966 04:05:28.142003 => setenv fdt_high 0xffffffff
967 04:05:28.152838 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
968 04:05:28.153712 setenv fdt_high 0xffffffff
969 04:05:28.154490 Sending with 10 millisecond of delay
971 04:05:28.446420 => dhcp
972 04:05:28.457193 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
973 04:05:28.743624 dhcp
974 04:05:28.744270 Speed: 1000, full duplex
975 04:05:28.744748 BOOTP broadcast 1
976 04:05:28.755029 DHCP client bound to address 192.168.6.27 (10 ms)
977 04:05:28.755808 Sending with 10 millisecond of delay
979 04:05:30.432496 => setenv serverip 192.168.6.2
980 04:05:30.443368 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
981 04:05:30.444412 setenv serverip 192.168.6.2
982 04:05:30.445169 Sending with 10 millisecond of delay
984 04:05:34.168383 => tftpboot 0x01080000 950761/tftp-deploy-i5tz872v/kernel/uImage
985 04:05:34.179240 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
986 04:05:34.180239 tftpboot 0x01080000 950761/tftp-deploy-i5tz872v/kernel/uImage
987 04:05:34.180746 Speed: 1000, full duplex
988 04:05:34.181211 Using ethernet@ff3f0000 device
989 04:05:34.182121 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
990 04:05:34.187618 Filename '950761/tftp-deploy-i5tz872v/kernel/uImage'.
991 04:05:34.191613 Load address: 0x1080000
992 04:05:37.029460 Loading: *################################################## 43.6 MiB
993 04:05:37.029894 15.3 MiB/s
994 04:05:37.030147 done
995 04:05:37.033885 Bytes transferred = 45713984 (2b98a40 hex)
996 04:05:37.034769 Sending with 10 millisecond of delay
998 04:05:41.721394 => tftpboot 0x08000000 950761/tftp-deploy-i5tz872v/ramdisk/ramdisk.cpio.gz.uboot
999 04:05:41.732234 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1000 04:05:41.733097 tftpboot 0x08000000 950761/tftp-deploy-i5tz872v/ramdisk/ramdisk.cpio.gz.uboot
1001 04:05:41.733591 Speed: 1000, full duplex
1002 04:05:41.734052 Using ethernet@ff3f0000 device
1003 04:05:41.734859 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1004 04:05:41.746792 Filename '950761/tftp-deploy-i5tz872v/ramdisk/ramdisk.cpio.gz.uboot'.
1005 04:05:41.747334 Load address: 0x8000000
1006 04:05:48.650189 Loading: *#########################T ######################## UDP wrong checksum 00000005 00007a8b
1007 04:05:53.650928 T UDP wrong checksum 00000005 00007a8b
1008 04:06:03.654155 T T UDP wrong checksum 00000005 00007a8b
1009 04:06:23.657985 T T T T UDP wrong checksum 00000005 00007a8b
1010 04:06:38.662193 T T
1011 04:06:38.662649 Retry count exceeded; starting again
1013 04:06:38.664590 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1016 04:06:38.665550 end: 2.4 uboot-commands (duration 00:01:47) [common]
1018 04:06:38.666264 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1020 04:06:38.666809 end: 2 uboot-action (duration 00:01:47) [common]
1022 04:06:38.667620 Cleaning after the job
1023 04:06:38.667937 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/ramdisk
1024 04:06:38.668806 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/kernel
1025 04:06:38.705291 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/dtb
1026 04:06:38.706140 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/nfsrootfs
1027 04:06:39.048323 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950761/tftp-deploy-i5tz872v/modules
1028 04:06:39.072057 start: 4.1 power-off (timeout 00:00:30) [common]
1029 04:06:39.072774 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1030 04:06:39.108539 >> OK - accepted request
1031 04:06:39.110634 Returned 0 in 0 seconds
1032 04:06:39.211525 end: 4.1 power-off (duration 00:00:00) [common]
1034 04:06:39.212603 start: 4.2 read-feedback (timeout 00:10:00) [common]
1035 04:06:39.213303 Listened to connection for namespace 'common' for up to 1s
1036 04:06:40.214198 Finalising connection for namespace 'common'
1037 04:06:40.214788 Disconnecting from shell: Finalise
1038 04:06:40.215099 =>
1039 04:06:40.315839 end: 4.2 read-feedback (duration 00:00:01) [common]
1040 04:06:40.316435 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950761
1041 04:06:43.274277 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950761
1042 04:06:43.274894 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.