Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:19:09.795559 lava-dispatcher, installed at version: 2024.01
2 04:19:09.796347 start: 0 validate
3 04:19:09.796821 Start time: 2024-11-07 04:19:09.796791+00:00 (UTC)
4 04:19:09.797339 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:19:09.797875 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 04:19:09.841570 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:19:09.842109 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 04:19:09.875111 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:19:09.876077 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:19:09.908606 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:19:09.909101 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:19:09.943345 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 04:19:09.944118 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-110-gff7afaeca1a15%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 04:19:09.987741 validate duration: 0.19
16 04:19:09.989270 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:19:09.989877 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:19:09.990478 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:19:09.991430 Not decompressing ramdisk as can be used compressed.
20 04:19:09.992231 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 04:19:09.992746 saving as /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/ramdisk/initrd.cpio.gz
22 04:19:09.993261 total size: 5628140 (5 MB)
23 04:19:10.036071 progress 0 % (0 MB)
24 04:19:10.043930 progress 5 % (0 MB)
25 04:19:10.052515 progress 10 % (0 MB)
26 04:19:10.059728 progress 15 % (0 MB)
27 04:19:10.065905 progress 20 % (1 MB)
28 04:19:10.069654 progress 25 % (1 MB)
29 04:19:10.073807 progress 30 % (1 MB)
30 04:19:10.077988 progress 35 % (1 MB)
31 04:19:10.081757 progress 40 % (2 MB)
32 04:19:10.085820 progress 45 % (2 MB)
33 04:19:10.089590 progress 50 % (2 MB)
34 04:19:10.093710 progress 55 % (2 MB)
35 04:19:10.097848 progress 60 % (3 MB)
36 04:19:10.101656 progress 65 % (3 MB)
37 04:19:10.105746 progress 70 % (3 MB)
38 04:19:10.109381 progress 75 % (4 MB)
39 04:19:10.113586 progress 80 % (4 MB)
40 04:19:10.117296 progress 85 % (4 MB)
41 04:19:10.121437 progress 90 % (4 MB)
42 04:19:10.125429 progress 95 % (5 MB)
43 04:19:10.128718 progress 100 % (5 MB)
44 04:19:10.129365 5 MB downloaded in 0.14 s (39.44 MB/s)
45 04:19:10.129939 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:19:10.130866 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:19:10.131186 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:19:10.131479 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:19:10.131964 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/kernel/Image
51 04:19:10.132246 saving as /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/kernel/Image
52 04:19:10.132468 total size: 45713920 (43 MB)
53 04:19:10.132687 No compression specified
54 04:19:10.171006 progress 0 % (0 MB)
55 04:19:10.200297 progress 5 % (2 MB)
56 04:19:10.229926 progress 10 % (4 MB)
57 04:19:10.259394 progress 15 % (6 MB)
58 04:19:10.289030 progress 20 % (8 MB)
59 04:19:10.318319 progress 25 % (10 MB)
60 04:19:10.347448 progress 30 % (13 MB)
61 04:19:10.377015 progress 35 % (15 MB)
62 04:19:10.406753 progress 40 % (17 MB)
63 04:19:10.435887 progress 45 % (19 MB)
64 04:19:10.465551 progress 50 % (21 MB)
65 04:19:10.495023 progress 55 % (24 MB)
66 04:19:10.524851 progress 60 % (26 MB)
67 04:19:10.554084 progress 65 % (28 MB)
68 04:19:10.583740 progress 70 % (30 MB)
69 04:19:10.613438 progress 75 % (32 MB)
70 04:19:10.642797 progress 80 % (34 MB)
71 04:19:10.671715 progress 85 % (37 MB)
72 04:19:10.701210 progress 90 % (39 MB)
73 04:19:10.731075 progress 95 % (41 MB)
74 04:19:10.759821 progress 100 % (43 MB)
75 04:19:10.760369 43 MB downloaded in 0.63 s (69.43 MB/s)
76 04:19:10.760873 end: 1.2.1 http-download (duration 00:00:01) [common]
78 04:19:10.761734 end: 1.2 download-retry (duration 00:00:01) [common]
79 04:19:10.762027 start: 1.3 download-retry (timeout 00:09:59) [common]
80 04:19:10.762308 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 04:19:10.762786 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 04:19:10.763068 saving as /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/dtb/meson-g12b-a311d-libretech-cc.dtb
83 04:19:10.763290 total size: 54703 (0 MB)
84 04:19:10.763511 No compression specified
85 04:19:10.808325 progress 59 % (0 MB)
86 04:19:10.809174 progress 100 % (0 MB)
87 04:19:10.809741 0 MB downloaded in 0.05 s (1.12 MB/s)
88 04:19:10.810221 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:19:10.811067 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:19:10.811347 start: 1.4 download-retry (timeout 00:09:59) [common]
92 04:19:10.811625 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 04:19:10.812103 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 04:19:10.812359 saving as /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/nfsrootfs/full.rootfs.tar
95 04:19:10.812576 total size: 474398908 (452 MB)
96 04:19:10.812794 Using unxz to decompress xz
97 04:19:10.854328 progress 0 % (0 MB)
98 04:19:11.954978 progress 5 % (22 MB)
99 04:19:13.421795 progress 10 % (45 MB)
100 04:19:13.913343 progress 15 % (67 MB)
101 04:19:14.709123 progress 20 % (90 MB)
102 04:19:15.264984 progress 25 % (113 MB)
103 04:19:15.619927 progress 30 % (135 MB)
104 04:19:16.220971 progress 35 % (158 MB)
105 04:19:17.131771 progress 40 % (181 MB)
106 04:19:17.972841 progress 45 % (203 MB)
107 04:19:18.690638 progress 50 % (226 MB)
108 04:19:19.398766 progress 55 % (248 MB)
109 04:19:20.624634 progress 60 % (271 MB)
110 04:19:22.105681 progress 65 % (294 MB)
111 04:19:23.691827 progress 70 % (316 MB)
112 04:19:26.770159 progress 75 % (339 MB)
113 04:19:29.200484 progress 80 % (361 MB)
114 04:19:32.059166 progress 85 % (384 MB)
115 04:19:35.185649 progress 90 % (407 MB)
116 04:19:38.340913 progress 95 % (429 MB)
117 04:19:41.481094 progress 100 % (452 MB)
118 04:19:41.493929 452 MB downloaded in 30.68 s (14.75 MB/s)
119 04:19:41.494922 end: 1.4.1 http-download (duration 00:00:31) [common]
121 04:19:41.496790 end: 1.4 download-retry (duration 00:00:31) [common]
122 04:19:41.497386 start: 1.5 download-retry (timeout 00:09:28) [common]
123 04:19:41.497981 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 04:19:41.499033 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-110-gff7afaeca1a15/arm64/defconfig/gcc-12/modules.tar.xz
125 04:19:41.499568 saving as /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/modules/modules.tar
126 04:19:41.500071 total size: 11618152 (11 MB)
127 04:19:41.500558 Using unxz to decompress xz
128 04:19:41.543579 progress 0 % (0 MB)
129 04:19:41.609838 progress 5 % (0 MB)
130 04:19:41.682819 progress 10 % (1 MB)
131 04:19:41.777383 progress 15 % (1 MB)
132 04:19:41.868127 progress 20 % (2 MB)
133 04:19:41.946698 progress 25 % (2 MB)
134 04:19:42.020942 progress 30 % (3 MB)
135 04:19:42.098407 progress 35 % (3 MB)
136 04:19:42.169805 progress 40 % (4 MB)
137 04:19:42.243871 progress 45 % (5 MB)
138 04:19:42.326685 progress 50 % (5 MB)
139 04:19:42.407223 progress 55 % (6 MB)
140 04:19:42.486740 progress 60 % (6 MB)
141 04:19:42.567099 progress 65 % (7 MB)
142 04:19:42.646514 progress 70 % (7 MB)
143 04:19:42.723552 progress 75 % (8 MB)
144 04:19:42.805690 progress 80 % (8 MB)
145 04:19:42.884388 progress 85 % (9 MB)
146 04:19:42.966112 progress 90 % (10 MB)
147 04:19:43.038419 progress 95 % (10 MB)
148 04:19:43.114631 progress 100 % (11 MB)
149 04:19:43.126925 11 MB downloaded in 1.63 s (6.81 MB/s)
150 04:19:43.127594 end: 1.5.1 http-download (duration 00:00:02) [common]
152 04:19:43.129362 end: 1.5 download-retry (duration 00:00:02) [common]
153 04:19:43.130041 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 04:19:43.130712 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 04:19:59.394756 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/950795/extract-nfsrootfs-m3vmq1m3
156 04:19:59.395369 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 04:19:59.395659 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 04:19:59.396382 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q
159 04:19:59.396826 makedir: /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin
160 04:19:59.397149 makedir: /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/tests
161 04:19:59.397460 makedir: /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/results
162 04:19:59.397793 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-add-keys
163 04:19:59.398317 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-add-sources
164 04:19:59.398811 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-background-process-start
165 04:19:59.399302 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-background-process-stop
166 04:19:59.399813 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-common-functions
167 04:19:59.400342 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-echo-ipv4
168 04:19:59.400824 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-install-packages
169 04:19:59.401305 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-installed-packages
170 04:19:59.401772 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-os-build
171 04:19:59.402258 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-probe-channel
172 04:19:59.402726 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-probe-ip
173 04:19:59.403211 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-target-ip
174 04:19:59.403725 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-target-mac
175 04:19:59.404222 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-target-storage
176 04:19:59.404715 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-test-case
177 04:19:59.405185 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-test-event
178 04:19:59.405708 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-test-feedback
179 04:19:59.406174 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-test-raise
180 04:19:59.406634 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-test-reference
181 04:19:59.407115 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-test-runner
182 04:19:59.407625 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-test-set
183 04:19:59.408119 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-test-shell
184 04:19:59.408603 Updating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-install-packages (oe)
185 04:19:59.409130 Updating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/bin/lava-installed-packages (oe)
186 04:19:59.409565 Creating /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/environment
187 04:19:59.409929 LAVA metadata
188 04:19:59.410184 - LAVA_JOB_ID=950795
189 04:19:59.410397 - LAVA_DISPATCHER_IP=192.168.6.2
190 04:19:59.410755 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 04:19:59.411694 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 04:19:59.412062 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 04:19:59.412283 skipped lava-vland-overlay
194 04:19:59.412530 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 04:19:59.412787 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 04:19:59.413004 skipped lava-multinode-overlay
197 04:19:59.413249 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 04:19:59.413501 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 04:19:59.413759 Loading test definitions
200 04:19:59.414041 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 04:19:59.414262 Using /lava-950795 at stage 0
202 04:19:59.415439 uuid=950795_1.6.2.4.1 testdef=None
203 04:19:59.415764 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 04:19:59.416055 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 04:19:59.417800 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 04:19:59.418590 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 04:19:59.420731 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 04:19:59.421558 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 04:19:59.423573 runner path: /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 950795_1.6.2.4.1
212 04:19:59.424141 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 04:19:59.424898 Creating lava-test-runner.conf files
215 04:19:59.425098 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/950795/lava-overlay-7c224p5q/lava-950795/0 for stage 0
216 04:19:59.425426 - 0_v4l2-decoder-conformance-h265
217 04:19:59.425759 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 04:19:59.426026 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 04:19:59.447233 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 04:19:59.447577 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 04:19:59.447833 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 04:19:59.448133 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 04:19:59.448402 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 04:20:00.143163 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 04:20:00.143649 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 04:20:00.143902 extracting modules file /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950795/extract-nfsrootfs-m3vmq1m3
227 04:20:01.481338 extracting modules file /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/modules/modules.tar to /var/lib/lava/dispatcher/tmp/950795/extract-overlay-ramdisk-_6qjcv7l/ramdisk
228 04:20:02.847562 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 04:20:02.848070 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 04:20:02.848355 [common] Applying overlay to NFS
231 04:20:02.848569 [common] Applying overlay /var/lib/lava/dispatcher/tmp/950795/compress-overlay-hzku2fhu/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/950795/extract-nfsrootfs-m3vmq1m3
232 04:20:02.877424 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 04:20:02.877780 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 04:20:02.878053 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 04:20:02.878279 Converting downloaded kernel to a uImage
236 04:20:02.878584 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/kernel/Image /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/kernel/uImage
237 04:20:03.351808 output: Image Name:
238 04:20:03.352254 output: Created: Thu Nov 7 04:20:02 2024
239 04:20:03.352472 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 04:20:03.352677 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 04:20:03.352880 output: Load Address: 01080000
242 04:20:03.353079 output: Entry Point: 01080000
243 04:20:03.353277 output:
244 04:20:03.353612 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 04:20:03.353880 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 04:20:03.354150 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 04:20:03.354405 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 04:20:03.354663 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 04:20:03.354919 Building ramdisk /var/lib/lava/dispatcher/tmp/950795/extract-overlay-ramdisk-_6qjcv7l/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/950795/extract-overlay-ramdisk-_6qjcv7l/ramdisk
250 04:20:05.458055 >> 166825 blocks
251 04:20:13.156566 Adding RAMdisk u-boot header.
252 04:20:13.157279 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/950795/extract-overlay-ramdisk-_6qjcv7l/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/950795/extract-overlay-ramdisk-_6qjcv7l/ramdisk.cpio.gz.uboot
253 04:20:13.410216 output: Image Name:
254 04:20:13.410714 output: Created: Thu Nov 7 04:20:13 2024
255 04:20:13.410975 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 04:20:13.411227 output: Data Size: 23432351 Bytes = 22883.16 KiB = 22.35 MiB
257 04:20:13.411473 output: Load Address: 00000000
258 04:20:13.411719 output: Entry Point: 00000000
259 04:20:13.411962 output:
260 04:20:13.413398 rename /var/lib/lava/dispatcher/tmp/950795/extract-overlay-ramdisk-_6qjcv7l/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/ramdisk/ramdisk.cpio.gz.uboot
261 04:20:13.414350 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 04:20:13.415068 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 04:20:13.415767 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 04:20:13.416408 No LXC device requested
265 04:20:13.417063 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 04:20:13.417730 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 04:20:13.418373 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 04:20:13.418913 Checking files for TFTP limit of 4294967296 bytes.
269 04:20:13.422386 end: 1 tftp-deploy (duration 00:01:03) [common]
270 04:20:13.423132 start: 2 uboot-action (timeout 00:05:00) [common]
271 04:20:13.423821 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 04:20:13.424493 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 04:20:13.425152 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 04:20:13.425832 Using kernel file from prepare-kernel: 950795/tftp-deploy-4717e21s/kernel/uImage
275 04:20:13.426639 substitutions:
276 04:20:13.427164 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 04:20:13.427690 - {DTB_ADDR}: 0x01070000
278 04:20:13.428310 - {DTB}: 950795/tftp-deploy-4717e21s/dtb/meson-g12b-a311d-libretech-cc.dtb
279 04:20:13.428841 - {INITRD}: 950795/tftp-deploy-4717e21s/ramdisk/ramdisk.cpio.gz.uboot
280 04:20:13.429354 - {KERNEL_ADDR}: 0x01080000
281 04:20:13.429862 - {KERNEL}: 950795/tftp-deploy-4717e21s/kernel/uImage
282 04:20:13.430370 - {LAVA_MAC}: None
283 04:20:13.430921 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/950795/extract-nfsrootfs-m3vmq1m3
284 04:20:13.431433 - {NFS_SERVER_IP}: 192.168.6.2
285 04:20:13.431937 - {PRESEED_CONFIG}: None
286 04:20:13.432531 - {PRESEED_LOCAL}: None
287 04:20:13.433044 - {RAMDISK_ADDR}: 0x08000000
288 04:20:13.433545 - {RAMDISK}: 950795/tftp-deploy-4717e21s/ramdisk/ramdisk.cpio.gz.uboot
289 04:20:13.434051 - {ROOT_PART}: None
290 04:20:13.434554 - {ROOT}: None
291 04:20:13.435056 - {SERVER_IP}: 192.168.6.2
292 04:20:13.435558 - {TEE_ADDR}: 0x83000000
293 04:20:13.436087 - {TEE}: None
294 04:20:13.436596 Parsed boot commands:
295 04:20:13.437092 - setenv autoload no
296 04:20:13.437591 - setenv initrd_high 0xffffffff
297 04:20:13.438094 - setenv fdt_high 0xffffffff
298 04:20:13.438594 - dhcp
299 04:20:13.439085 - setenv serverip 192.168.6.2
300 04:20:13.439588 - tftpboot 0x01080000 950795/tftp-deploy-4717e21s/kernel/uImage
301 04:20:13.440118 - tftpboot 0x08000000 950795/tftp-deploy-4717e21s/ramdisk/ramdisk.cpio.gz.uboot
302 04:20:13.440635 - tftpboot 0x01070000 950795/tftp-deploy-4717e21s/dtb/meson-g12b-a311d-libretech-cc.dtb
303 04:20:13.441144 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/950795/extract-nfsrootfs-m3vmq1m3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 04:20:13.441671 - bootm 0x01080000 0x08000000 0x01070000
305 04:20:13.442323 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 04:20:13.444301 start: 2.3 connect-device (timeout 00:05:00) [common]
308 04:20:13.444839 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 04:20:13.461158 Setting prompt string to ['lava-test: # ']
310 04:20:13.462971 end: 2.3 connect-device (duration 00:00:00) [common]
311 04:20:13.463739 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 04:20:13.464492 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 04:20:13.465167 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 04:20:13.466565 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 04:20:13.505222 >> OK - accepted request
316 04:20:13.507349 Returned 0 in 0 seconds
317 04:20:13.608765 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 04:20:13.610804 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 04:20:13.611528 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 04:20:13.612244 Setting prompt string to ['Hit any key to stop autoboot']
322 04:20:13.612857 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 04:20:13.614821 Trying 192.168.56.21...
324 04:20:13.615438 Connected to conserv1.
325 04:20:13.615976 Escape character is '^]'.
326 04:20:13.616546
327 04:20:13.617087 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 04:20:13.617628
329 04:20:24.689638 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 04:20:24.690427 bl2_stage_init 0x01
331 04:20:24.691021 bl2_stage_init 0x81
332 04:20:24.695231 hw id: 0x0000 - pwm id 0x01
333 04:20:24.695873 bl2_stage_init 0xc1
334 04:20:24.696427 bl2_stage_init 0x02
335 04:20:24.696947
336 04:20:24.700763 L0:00000000
337 04:20:24.701339 L1:20000703
338 04:20:24.701850 L2:00008067
339 04:20:24.702364 L3:14000000
340 04:20:24.703728 B2:00402000
341 04:20:24.704288 B1:e0f83180
342 04:20:24.704789
343 04:20:24.705289 TE: 58124
344 04:20:24.705781
345 04:20:24.714575 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 04:20:24.715121
347 04:20:24.715628 Board ID = 1
348 04:20:24.716155 Set A53 clk to 24M
349 04:20:24.716660 Set A73 clk to 24M
350 04:20:24.720194 Set clk81 to 24M
351 04:20:24.720719 A53 clk: 1200 MHz
352 04:20:24.721219 A73 clk: 1200 MHz
353 04:20:24.723912 CLK81: 166.6M
354 04:20:24.724450 smccc: 00012a92
355 04:20:24.729479 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 04:20:24.735014 board id: 1
357 04:20:24.740180 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 04:20:24.750779 fw parse done
359 04:20:24.756772 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 04:20:24.799526 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 04:20:24.810358 PIEI prepare done
362 04:20:24.810887 fastboot data load
363 04:20:24.811393 fastboot data verify
364 04:20:24.815930 verify result: 266
365 04:20:24.821607 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 04:20:24.822188 LPDDR4 probe
367 04:20:24.822724 ddr clk to 1584MHz
368 04:20:24.829527 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 04:20:24.866832
370 04:20:24.867391 dmc_version 0001
371 04:20:24.873461 Check phy result
372 04:20:24.879299 INFO : End of CA training
373 04:20:24.879845 INFO : End of initialization
374 04:20:24.884911 INFO : Training has run successfully!
375 04:20:24.885465 Check phy result
376 04:20:24.890535 INFO : End of initialization
377 04:20:24.891074 INFO : End of read enable training
378 04:20:24.896109 INFO : End of fine write leveling
379 04:20:24.901710 INFO : End of Write leveling coarse delay
380 04:20:24.902255 INFO : Training has run successfully!
381 04:20:24.902771 Check phy result
382 04:20:24.907288 INFO : End of initialization
383 04:20:24.907836 INFO : End of read dq deskew training
384 04:20:24.912899 INFO : End of MPR read delay center optimization
385 04:20:24.918547 INFO : End of write delay center optimization
386 04:20:24.924107 INFO : End of read delay center optimization
387 04:20:24.924656 INFO : End of max read latency training
388 04:20:24.929710 INFO : Training has run successfully!
389 04:20:24.930252 1D training succeed
390 04:20:24.938902 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 04:20:24.986566 Check phy result
392 04:20:24.987141 INFO : End of initialization
393 04:20:25.009076 INFO : End of 2D read delay Voltage center optimization
394 04:20:25.029410 INFO : End of 2D read delay Voltage center optimization
395 04:20:25.081416 INFO : End of 2D write delay Voltage center optimization
396 04:20:25.130820 INFO : End of 2D write delay Voltage center optimization
397 04:20:25.136363 INFO : Training has run successfully!
398 04:20:25.136910
399 04:20:25.137459 channel==0
400 04:20:25.142000 RxClkDly_Margin_A0==88 ps 9
401 04:20:25.142545 TxDqDly_Margin_A0==98 ps 10
402 04:20:25.147670 RxClkDly_Margin_A1==88 ps 9
403 04:20:25.148270 TxDqDly_Margin_A1==88 ps 9
404 04:20:25.148811 TrainedVREFDQ_A0==74
405 04:20:25.153191 TrainedVREFDQ_A1==74
406 04:20:25.153752 VrefDac_Margin_A0==25
407 04:20:25.154281 DeviceVref_Margin_A0==40
408 04:20:25.158805 VrefDac_Margin_A1==24
409 04:20:25.159345 DeviceVref_Margin_A1==40
410 04:20:25.159861
411 04:20:25.160416
412 04:20:25.160942 channel==1
413 04:20:25.164310 RxClkDly_Margin_A0==98 ps 10
414 04:20:25.164861 TxDqDly_Margin_A0==98 ps 10
415 04:20:25.169950 RxClkDly_Margin_A1==88 ps 9
416 04:20:25.170495 TxDqDly_Margin_A1==88 ps 9
417 04:20:25.175653 TrainedVREFDQ_A0==77
418 04:20:25.176232 TrainedVREFDQ_A1==77
419 04:20:25.176764 VrefDac_Margin_A0==22
420 04:20:25.181197 DeviceVref_Margin_A0==37
421 04:20:25.181747 VrefDac_Margin_A1==24
422 04:20:25.186749 DeviceVref_Margin_A1==37
423 04:20:25.187289
424 04:20:25.187825 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 04:20:25.188393
426 04:20:25.220249 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 04:20:25.220893 2D training succeed
428 04:20:25.225833 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 04:20:25.231549 auto size-- 65535DDR cs0 size: 2048MB
430 04:20:25.232117 DDR cs1 size: 2048MB
431 04:20:25.237037 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 04:20:25.237591 cs0 DataBus test pass
433 04:20:25.242655 cs1 DataBus test pass
434 04:20:25.243199 cs0 AddrBus test pass
435 04:20:25.243730 cs1 AddrBus test pass
436 04:20:25.244279
437 04:20:25.248249 100bdlr_step_size ps== 420
438 04:20:25.248803 result report
439 04:20:25.253828 boot times 0Enable ddr reg access
440 04:20:25.259096 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 04:20:25.272642 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 04:20:25.846254 0.0;M3 CHK:0;cm4_sp_mode 0
443 04:20:25.846974 MVN_1=0x00000000
444 04:20:25.851691 MVN_2=0x00000000
445 04:20:25.857441 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 04:20:25.857999 OPS=0x10
447 04:20:25.858539 ring efuse init
448 04:20:25.859055 chipver efuse init
449 04:20:25.863027 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 04:20:25.868625 [0.018961 Inits done]
451 04:20:25.869173 secure task start!
452 04:20:25.869690 high task start!
453 04:20:25.873244 low task start!
454 04:20:25.873801 run into bl31
455 04:20:25.879881 NOTICE: BL31: v1.3(release):4fc40b1
456 04:20:25.887672 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 04:20:25.888263 NOTICE: BL31: G12A normal boot!
458 04:20:25.913023 NOTICE: BL31: BL33 decompress pass
459 04:20:25.918721 ERROR: Error initializing runtime service opteed_fast
460 04:20:27.151873
461 04:20:27.152747
462 04:20:27.160397 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 04:20:27.161127
464 04:20:27.161702 Model: Libre Computer AML-A311D-CC Alta
465 04:20:27.368564 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 04:20:27.392050 DRAM: 2 GiB (effective 3.8 GiB)
467 04:20:27.534994 Core: 408 devices, 31 uclasses, devicetree: separate
468 04:20:27.540767 WDT: Not starting watchdog@f0d0
469 04:20:27.573012 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 04:20:27.585431 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 04:20:27.590434 ** Bad device specification mmc 0 **
472 04:20:27.600922 Card did not respond to voltage select! : -110
473 04:20:27.608451 ** Bad device specification mmc 0 **
474 04:20:27.609048 Couldn't find partition mmc 0
475 04:20:27.616882 Card did not respond to voltage select! : -110
476 04:20:27.622262 ** Bad device specification mmc 0 **
477 04:20:27.622825 Couldn't find partition mmc 0
478 04:20:27.627314 Error: could not access storage.
479 04:20:28.889691 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
480 04:20:28.890357 bl2_stage_init 0x81
481 04:20:28.895272 hw id: 0x0000 - pwm id 0x01
482 04:20:28.895821 bl2_stage_init 0xc1
483 04:20:28.896347 bl2_stage_init 0x02
484 04:20:28.896838
485 04:20:28.900898 L0:00000000
486 04:20:28.901411 L1:20000703
487 04:20:28.901866 L2:00008067
488 04:20:28.902309 L3:14000000
489 04:20:28.902753 B2:00402000
490 04:20:28.903716 B1:e0f83180
491 04:20:28.904227
492 04:20:28.904675 TE: 58150
493 04:20:28.905118
494 04:20:28.914908 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 04:20:28.915396
496 04:20:28.915848 Board ID = 1
497 04:20:28.916339 Set A53 clk to 24M
498 04:20:28.916781 Set A73 clk to 24M
499 04:20:28.920464 Set clk81 to 24M
500 04:20:28.920943 A53 clk: 1200 MHz
501 04:20:28.921389 A73 clk: 1200 MHz
502 04:20:28.926089 CLK81: 166.6M
503 04:20:28.926581 smccc: 00012aab
504 04:20:28.931671 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 04:20:28.932179 board id: 1
506 04:20:28.940254 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 04:20:28.950915 fw parse done
508 04:20:28.956879 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 04:20:28.999533 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 04:20:29.010405 PIEI prepare done
511 04:20:29.010899 fastboot data load
512 04:20:29.011354 fastboot data verify
513 04:20:29.016069 verify result: 266
514 04:20:29.021715 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 04:20:29.022205 LPDDR4 probe
516 04:20:29.022656 ddr clk to 1584MHz
517 04:20:29.029679 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 04:20:29.066904
519 04:20:29.067395 dmc_version 0001
520 04:20:29.073522 Check phy result
521 04:20:29.079381 INFO : End of CA training
522 04:20:29.079873 INFO : End of initialization
523 04:20:29.085082 INFO : Training has run successfully!
524 04:20:29.085551 Check phy result
525 04:20:29.090576 INFO : End of initialization
526 04:20:29.091042 INFO : End of read enable training
527 04:20:29.093986 INFO : End of fine write leveling
528 04:20:29.099521 INFO : End of Write leveling coarse delay
529 04:20:29.105131 INFO : Training has run successfully!
530 04:20:29.105610 Check phy result
531 04:20:29.106053 INFO : End of initialization
532 04:20:29.110726 INFO : End of read dq deskew training
533 04:20:29.116310 INFO : End of MPR read delay center optimization
534 04:20:29.116786 INFO : End of write delay center optimization
535 04:20:29.121947 INFO : End of read delay center optimization
536 04:20:29.127515 INFO : End of max read latency training
537 04:20:29.128011 INFO : Training has run successfully!
538 04:20:29.133116 1D training succeed
539 04:20:29.139015 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 04:20:29.186561 Check phy result
541 04:20:29.187015 INFO : End of initialization
542 04:20:29.208226 INFO : End of 2D read delay Voltage center optimization
543 04:20:29.228296 INFO : End of 2D read delay Voltage center optimization
544 04:20:29.280211 INFO : End of 2D write delay Voltage center optimization
545 04:20:29.329396 INFO : End of 2D write delay Voltage center optimization
546 04:20:29.335097 INFO : Training has run successfully!
547 04:20:29.335538
548 04:20:29.335970 channel==0
549 04:20:29.340614 RxClkDly_Margin_A0==88 ps 9
550 04:20:29.341096 TxDqDly_Margin_A0==98 ps 10
551 04:20:29.346190 RxClkDly_Margin_A1==88 ps 9
552 04:20:29.346662 TxDqDly_Margin_A1==98 ps 10
553 04:20:29.347093 TrainedVREFDQ_A0==74
554 04:20:29.351795 TrainedVREFDQ_A1==74
555 04:20:29.352295 VrefDac_Margin_A0==25
556 04:20:29.352718 DeviceVref_Margin_A0==40
557 04:20:29.357395 VrefDac_Margin_A1==25
558 04:20:29.357842 DeviceVref_Margin_A1==40
559 04:20:29.358256
560 04:20:29.358668
561 04:20:29.363102 channel==1
562 04:20:29.363543 RxClkDly_Margin_A0==98 ps 10
563 04:20:29.363953 TxDqDly_Margin_A0==98 ps 10
564 04:20:29.368577 RxClkDly_Margin_A1==88 ps 9
565 04:20:29.369063 TxDqDly_Margin_A1==88 ps 9
566 04:20:29.374267 TrainedVREFDQ_A0==77
567 04:20:29.374868 TrainedVREFDQ_A1==77
568 04:20:29.375352 VrefDac_Margin_A0==22
569 04:20:29.379952 DeviceVref_Margin_A0==37
570 04:20:29.380532 VrefDac_Margin_A1==24
571 04:20:29.385544 DeviceVref_Margin_A1==37
572 04:20:29.386109
573 04:20:29.386576 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 04:20:29.387029
575 04:20:29.419200 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
576 04:20:29.419844 2D training succeed
577 04:20:29.424739 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 04:20:29.430323 auto size-- 65535DDR cs0 size: 2048MB
579 04:20:29.430871 DDR cs1 size: 2048MB
580 04:20:29.435919 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 04:20:29.436508 cs0 DataBus test pass
582 04:20:29.441523 cs1 DataBus test pass
583 04:20:29.442070 cs0 AddrBus test pass
584 04:20:29.442537 cs1 AddrBus test pass
585 04:20:29.442987
586 04:20:29.447117 100bdlr_step_size ps== 420
587 04:20:29.447679 result report
588 04:20:29.452719 boot times 0Enable ddr reg access
589 04:20:29.458072 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 04:20:29.471478 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 04:20:30.043576 0.0;M3 CHK:0;cm4_sp_mode 0
592 04:20:30.044290 MVN_1=0x00000000
593 04:20:30.049084 MVN_2=0x00000000
594 04:20:30.054851 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 04:20:30.055429 OPS=0x10
596 04:20:30.055924 ring efuse init
597 04:20:30.056480 chipver efuse init
598 04:20:30.060415 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 04:20:30.065982 [0.018961 Inits done]
600 04:20:30.066528 secure task start!
601 04:20:30.066968 high task start!
602 04:20:30.070566 low task start!
603 04:20:30.071118 run into bl31
604 04:20:30.077293 NOTICE: BL31: v1.3(release):4fc40b1
605 04:20:30.085046 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 04:20:30.085581 NOTICE: BL31: G12A normal boot!
607 04:20:30.110454 NOTICE: BL31: BL33 decompress pass
608 04:20:30.116150 ERROR: Error initializing runtime service opteed_fast
609 04:20:31.349343
610 04:20:31.349999
611 04:20:31.357616 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 04:20:31.358167
613 04:20:31.358656 Model: Libre Computer AML-A311D-CC Alta
614 04:20:31.566157 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 04:20:31.589470 DRAM: 2 GiB (effective 3.8 GiB)
616 04:20:31.732326 Core: 408 devices, 31 uclasses, devicetree: separate
617 04:20:31.738344 WDT: Not starting watchdog@f0d0
618 04:20:31.770634 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 04:20:31.782977 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 04:20:31.787974 ** Bad device specification mmc 0 **
621 04:20:31.798240 Card did not respond to voltage select! : -110
622 04:20:31.806046 ** Bad device specification mmc 0 **
623 04:20:31.806590 Couldn't find partition mmc 0
624 04:20:31.814237 Card did not respond to voltage select! : -110
625 04:20:31.819817 ** Bad device specification mmc 0 **
626 04:20:31.820418 Couldn't find partition mmc 0
627 04:20:31.825000 Error: could not access storage.
628 04:20:32.167304 Net: eth0: ethernet@ff3f0000
629 04:20:32.167959 starting USB...
630 04:20:32.419247 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 04:20:32.419888 Starting the controller
632 04:20:32.426164 USB XHCI 1.10
633 04:20:34.140079 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
634 04:20:34.140755 bl2_stage_init 0x81
635 04:20:34.145620 hw id: 0x0000 - pwm id 0x01
636 04:20:34.146138 bl2_stage_init 0xc1
637 04:20:34.146599 bl2_stage_init 0x02
638 04:20:34.147049
639 04:20:34.151161 L0:00000000
640 04:20:34.151669 L1:20000703
641 04:20:34.152155 L2:00008067
642 04:20:34.152601 L3:14000000
643 04:20:34.153044 B2:00402000
644 04:20:34.156988 B1:e0f83180
645 04:20:34.157492
646 04:20:34.157942 TE: 58150
647 04:20:34.158386
648 04:20:34.162420 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
649 04:20:34.162926
650 04:20:34.163381 Board ID = 1
651 04:20:34.168058 Set A53 clk to 24M
652 04:20:34.168570 Set A73 clk to 24M
653 04:20:34.169025 Set clk81 to 24M
654 04:20:34.173519 A53 clk: 1200 MHz
655 04:20:34.174024 A73 clk: 1200 MHz
656 04:20:34.174475 CLK81: 166.6M
657 04:20:34.174917 smccc: 00012aab
658 04:20:34.179155 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
659 04:20:34.184856 board id: 1
660 04:20:34.190650 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
661 04:20:34.201189 fw parse done
662 04:20:34.207299 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
663 04:20:34.249668 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
664 04:20:34.260608 PIEI prepare done
665 04:20:34.261118 fastboot data load
666 04:20:34.261574 fastboot data verify
667 04:20:34.266235 verify result: 266
668 04:20:34.271923 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
669 04:20:34.272469 LPDDR4 probe
670 04:20:34.272920 ddr clk to 1584MHz
671 04:20:34.279846 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
672 04:20:34.317032
673 04:20:34.317548 dmc_version 0001
674 04:20:34.323750 Check phy result
675 04:20:34.329596 INFO : End of CA training
676 04:20:34.330102 INFO : End of initialization
677 04:20:34.335208 INFO : Training has run successfully!
678 04:20:34.335709 Check phy result
679 04:20:34.340896 INFO : End of initialization
680 04:20:34.341403 INFO : End of read enable training
681 04:20:34.346398 INFO : End of fine write leveling
682 04:20:34.352043 INFO : End of Write leveling coarse delay
683 04:20:34.352549 INFO : Training has run successfully!
684 04:20:34.353002 Check phy result
685 04:20:34.357609 INFO : End of initialization
686 04:20:34.358142 INFO : End of read dq deskew training
687 04:20:34.363227 INFO : End of MPR read delay center optimization
688 04:20:34.368963 INFO : End of write delay center optimization
689 04:20:34.374494 INFO : End of read delay center optimization
690 04:20:34.375060 INFO : End of max read latency training
691 04:20:34.380114 INFO : Training has run successfully!
692 04:20:34.380691 1D training succeed
693 04:20:34.389227 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 04:20:34.436966 Check phy result
695 04:20:34.437631 INFO : End of initialization
696 04:20:34.458737 INFO : End of 2D read delay Voltage center optimization
697 04:20:34.478856 INFO : End of 2D read delay Voltage center optimization
698 04:20:34.530883 INFO : End of 2D write delay Voltage center optimization
699 04:20:34.580328 INFO : End of 2D write delay Voltage center optimization
700 04:20:34.585836 INFO : Training has run successfully!
701 04:20:34.586416
702 04:20:34.586882 channel==0
703 04:20:34.591419 RxClkDly_Margin_A0==88 ps 9
704 04:20:34.592039 TxDqDly_Margin_A0==98 ps 10
705 04:20:34.597051 RxClkDly_Margin_A1==88 ps 9
706 04:20:34.597638 TxDqDly_Margin_A1==88 ps 9
707 04:20:34.598107 TrainedVREFDQ_A0==74
708 04:20:34.602640 TrainedVREFDQ_A1==74
709 04:20:34.603218 VrefDac_Margin_A0==25
710 04:20:34.603675 DeviceVref_Margin_A0==40
711 04:20:34.608171 VrefDac_Margin_A1==25
712 04:20:34.608691 DeviceVref_Margin_A1==40
713 04:20:34.609138
714 04:20:34.609581
715 04:20:34.610018 channel==1
716 04:20:34.613720 RxClkDly_Margin_A0==98 ps 10
717 04:20:34.614221 TxDqDly_Margin_A0==88 ps 9
718 04:20:34.619322 RxClkDly_Margin_A1==88 ps 9
719 04:20:34.619831 TxDqDly_Margin_A1==98 ps 10
720 04:20:34.624934 TrainedVREFDQ_A0==76
721 04:20:34.625442 TrainedVREFDQ_A1==77
722 04:20:34.625895 VrefDac_Margin_A0==22
723 04:20:34.630529 DeviceVref_Margin_A0==38
724 04:20:34.631031 VrefDac_Margin_A1==24
725 04:20:34.636125 DeviceVref_Margin_A1==37
726 04:20:34.636625
727 04:20:34.637073 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
728 04:20:34.637516
729 04:20:34.669684 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
730 04:20:34.670243 2D training succeed
731 04:20:34.675341 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
732 04:20:34.680932 auto size-- 65535DDR cs0 size: 2048MB
733 04:20:34.681430 DDR cs1 size: 2048MB
734 04:20:34.686531 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
735 04:20:34.687034 cs0 DataBus test pass
736 04:20:34.692115 cs1 DataBus test pass
737 04:20:34.692616 cs0 AddrBus test pass
738 04:20:34.693060 cs1 AddrBus test pass
739 04:20:34.693500
740 04:20:34.697717 100bdlr_step_size ps== 420
741 04:20:34.698229 result report
742 04:20:34.703299 boot times 0Enable ddr reg access
743 04:20:34.708567 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
744 04:20:34.722041 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
745 04:20:35.295213 0.0;M3 CHK:0;cm4_sp_mode 0
746 04:20:35.295834 MVN_1=0x00000000
747 04:20:35.300675 MVN_2=0x00000000
748 04:20:35.306430 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
749 04:20:35.306966 OPS=0x10
750 04:20:35.307401 ring efuse init
751 04:20:35.307824 chipver efuse init
752 04:20:35.312037 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
753 04:20:35.317565 [0.018961 Inits done]
754 04:20:35.318054 secure task start!
755 04:20:35.318481 high task start!
756 04:20:35.322161 low task start!
757 04:20:35.322659 run into bl31
758 04:20:35.328902 NOTICE: BL31: v1.3(release):4fc40b1
759 04:20:35.336641 NOTICE: BL31: Built : 15:58:17, May 22 2019
760 04:20:35.337139 NOTICE: BL31: G12A normal boot!
761 04:20:35.362037 NOTICE: BL31: BL33 decompress pass
762 04:20:35.367678 ERROR: Error initializing runtime service opteed_fast
763 04:20:36.600564
764 04:20:36.601210
765 04:20:36.608904 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
766 04:20:36.609415
767 04:20:36.609870 Model: Libre Computer AML-A311D-CC Alta
768 04:20:36.817371 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
769 04:20:36.840691 DRAM: 2 GiB (effective 3.8 GiB)
770 04:20:36.983680 Core: 408 devices, 31 uclasses, devicetree: separate
771 04:20:36.989549 WDT: Not starting watchdog@f0d0
772 04:20:37.021859 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
773 04:20:37.034382 Loading Environment from FAT... Card did not respond to voltage select! : -110
774 04:20:37.039349 ** Bad device specification mmc 0 **
775 04:20:37.049557 Card did not respond to voltage select! : -110
776 04:20:37.057322 ** Bad device specification mmc 0 **
777 04:20:37.057832 Couldn't find partition mmc 0
778 04:20:37.065569 Card did not respond to voltage select! : -110
779 04:20:37.071134 ** Bad device specification mmc 0 **
780 04:20:37.071638 Couldn't find partition mmc 0
781 04:20:37.076206 Error: could not access storage.
782 04:20:37.418713 Net: eth0: ethernet@ff3f0000
783 04:20:37.419337 starting USB...
784 04:20:37.670505 Bus usb@ff500000: Register 3000140 NbrPorts 3
785 04:20:37.671136 Starting the controller
786 04:20:37.677434 USB XHCI 1.10
787 04:20:39.841816 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
788 04:20:39.842464 bl2_stage_init 0x01
789 04:20:39.842918 bl2_stage_init 0x81
790 04:20:39.847334 hw id: 0x0000 - pwm id 0x01
791 04:20:39.847847 bl2_stage_init 0xc1
792 04:20:39.848398 bl2_stage_init 0x02
793 04:20:39.848851
794 04:20:39.852895 L0:00000000
795 04:20:39.853401 L1:20000703
796 04:20:39.853845 L2:00008067
797 04:20:39.854284 L3:14000000
798 04:20:39.858403 B2:00402000
799 04:20:39.858904 B1:e0f83180
800 04:20:39.859349
801 04:20:39.859787 TE: 58159
802 04:20:39.860276
803 04:20:39.864098 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
804 04:20:39.864601
805 04:20:39.865055 Board ID = 1
806 04:20:39.869814 Set A53 clk to 24M
807 04:20:39.870315 Set A73 clk to 24M
808 04:20:39.870766 Set clk81 to 24M
809 04:20:39.875304 A53 clk: 1200 MHz
810 04:20:39.875801 A73 clk: 1200 MHz
811 04:20:39.876289 CLK81: 166.6M
812 04:20:39.876732 smccc: 00012ab5
813 04:20:39.881020 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
814 04:20:39.886524 board id: 1
815 04:20:39.892462 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
816 04:20:39.902877 fw parse done
817 04:20:39.908852 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
818 04:20:39.951454 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
819 04:20:39.962387 PIEI prepare done
820 04:20:39.962891 fastboot data load
821 04:20:39.963347 fastboot data verify
822 04:20:39.968018 verify result: 266
823 04:20:39.973687 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
824 04:20:39.974193 LPDDR4 probe
825 04:20:39.974644 ddr clk to 1584MHz
826 04:20:39.981647 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
827 04:20:40.018865
828 04:20:40.019432 dmc_version 0001
829 04:20:40.025581 Check phy result
830 04:20:40.031389 INFO : End of CA training
831 04:20:40.031933 INFO : End of initialization
832 04:20:40.037024 INFO : Training has run successfully!
833 04:20:40.037548 Check phy result
834 04:20:40.042706 INFO : End of initialization
835 04:20:40.043210 INFO : End of read enable training
836 04:20:40.048212 INFO : End of fine write leveling
837 04:20:40.053791 INFO : End of Write leveling coarse delay
838 04:20:40.054298 INFO : Training has run successfully!
839 04:20:40.054750 Check phy result
840 04:20:40.059359 INFO : End of initialization
841 04:20:40.059861 INFO : End of read dq deskew training
842 04:20:40.064963 INFO : End of MPR read delay center optimization
843 04:20:40.070569 INFO : End of write delay center optimization
844 04:20:40.076199 INFO : End of read delay center optimization
845 04:20:40.076726 INFO : End of max read latency training
846 04:20:40.081807 INFO : Training has run successfully!
847 04:20:40.082323 1D training succeed
848 04:20:40.090931 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 04:20:40.138555 Check phy result
850 04:20:40.139071 INFO : End of initialization
851 04:20:40.160309 INFO : End of 2D read delay Voltage center optimization
852 04:20:40.180568 INFO : End of 2D read delay Voltage center optimization
853 04:20:40.232577 INFO : End of 2D write delay Voltage center optimization
854 04:20:40.281960 INFO : End of 2D write delay Voltage center optimization
855 04:20:40.287603 INFO : Training has run successfully!
856 04:20:40.288152
857 04:20:40.288612 channel==0
858 04:20:40.293146 RxClkDly_Margin_A0==88 ps 9
859 04:20:40.293659 TxDqDly_Margin_A0==98 ps 10
860 04:20:40.298735 RxClkDly_Margin_A1==88 ps 9
861 04:20:40.299237 TxDqDly_Margin_A1==88 ps 9
862 04:20:40.299702 TrainedVREFDQ_A0==74
863 04:20:40.304348 TrainedVREFDQ_A1==74
864 04:20:40.304816 VrefDac_Margin_A0==25
865 04:20:40.305216 DeviceVref_Margin_A0==40
866 04:20:40.309860 VrefDac_Margin_A1==25
867 04:20:40.310289 DeviceVref_Margin_A1==40
868 04:20:40.310680
869 04:20:40.311072
870 04:20:40.311456 channel==1
871 04:20:40.315427 RxClkDly_Margin_A0==98 ps 10
872 04:20:40.315852 TxDqDly_Margin_A0==98 ps 10
873 04:20:40.321015 RxClkDly_Margin_A1==98 ps 10
874 04:20:40.321440 TxDqDly_Margin_A1==88 ps 9
875 04:20:40.326625 TrainedVREFDQ_A0==77
876 04:20:40.327049 TrainedVREFDQ_A1==77
877 04:20:40.327439 VrefDac_Margin_A0==22
878 04:20:40.332216 DeviceVref_Margin_A0==37
879 04:20:40.332639 VrefDac_Margin_A1==22
880 04:20:40.337810 DeviceVref_Margin_A1==37
881 04:20:40.338226
882 04:20:40.338613 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
883 04:20:40.338997
884 04:20:40.371420 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
885 04:20:40.371878 2D training succeed
886 04:20:40.377014 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
887 04:20:40.382630 auto size-- 65535DDR cs0 size: 2048MB
888 04:20:40.383057 DDR cs1 size: 2048MB
889 04:20:40.388235 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
890 04:20:40.388657 cs0 DataBus test pass
891 04:20:40.393803 cs1 DataBus test pass
892 04:20:40.394229 cs0 AddrBus test pass
893 04:20:40.394616 cs1 AddrBus test pass
894 04:20:40.394993
895 04:20:40.399418 100bdlr_step_size ps== 420
896 04:20:40.399934 result report
897 04:20:40.405041 boot times 0Enable ddr reg access
898 04:20:40.410409 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
899 04:20:40.423875 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
900 04:20:40.997629 0.0;M3 CHK:0;cm4_sp_mode 0
901 04:20:40.998177 MVN_1=0x00000000
902 04:20:41.003031 MVN_2=0x00000000
903 04:20:41.008783 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
904 04:20:41.009240 OPS=0x10
905 04:20:41.009661 ring efuse init
906 04:20:41.010066 chipver efuse init
907 04:20:41.014375 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
908 04:20:41.020121 [0.018961 Inits done]
909 04:20:41.020576 secure task start!
910 04:20:41.020990 high task start!
911 04:20:41.024636 low task start!
912 04:20:41.025091 run into bl31
913 04:20:41.031332 NOTICE: BL31: v1.3(release):4fc40b1
914 04:20:41.039121 NOTICE: BL31: Built : 15:58:17, May 22 2019
915 04:20:41.039601 NOTICE: BL31: G12A normal boot!
916 04:20:41.064399 NOTICE: BL31: BL33 decompress pass
917 04:20:41.070056 ERROR: Error initializing runtime service opteed_fast
918 04:20:42.303058
919 04:20:42.303664
920 04:20:42.311369 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
921 04:20:42.311840
922 04:20:42.312298 Model: Libre Computer AML-A311D-CC Alta
923 04:20:42.519912 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
924 04:20:42.543209 DRAM: 2 GiB (effective 3.8 GiB)
925 04:20:42.686265 Core: 408 devices, 31 uclasses, devicetree: separate
926 04:20:42.692059 WDT: Not starting watchdog@f0d0
927 04:20:42.724289 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
928 04:20:42.736814 Loading Environment from FAT... Card did not respond to voltage select! : -110
929 04:20:42.741719 ** Bad device specification mmc 0 **
930 04:20:42.752076 Card did not respond to voltage select! : -110
931 04:20:42.759707 ** Bad device specification mmc 0 **
932 04:20:42.760193 Couldn't find partition mmc 0
933 04:20:42.768077 Card did not respond to voltage select! : -110
934 04:20:42.773567 ** Bad device specification mmc 0 **
935 04:20:42.774013 Couldn't find partition mmc 0
936 04:20:42.778652 Error: could not access storage.
937 04:20:43.122169 Net: eth0: ethernet@ff3f0000
938 04:20:43.122682 starting USB...
939 04:20:43.373995 Bus usb@ff500000: Register 3000140 NbrPorts 3
940 04:20:43.374504 Starting the controller
941 04:20:43.380912 USB XHCI 1.10
942 04:20:45.241493 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
943 04:20:45.242101 bl2_stage_init 0x01
944 04:20:45.242536 bl2_stage_init 0x81
945 04:20:45.247157 hw id: 0x0000 - pwm id 0x01
946 04:20:45.247618 bl2_stage_init 0xc1
947 04:20:45.248080 bl2_stage_init 0x02
948 04:20:45.248494
949 04:20:45.252763 L0:00000000
950 04:20:45.253261 L1:20000703
951 04:20:45.253680 L2:00008067
952 04:20:45.254082 L3:14000000
953 04:20:45.258423 B2:00402000
954 04:20:45.258870 B1:e0f83180
955 04:20:45.259275
956 04:20:45.259675 TE: 58167
957 04:20:45.260103
958 04:20:45.263860 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
959 04:20:45.264341
960 04:20:45.264746 Board ID = 1
961 04:20:45.269449 Set A53 clk to 24M
962 04:20:45.269893 Set A73 clk to 24M
963 04:20:45.270297 Set clk81 to 24M
964 04:20:45.275105 A53 clk: 1200 MHz
965 04:20:45.275548 A73 clk: 1200 MHz
966 04:20:45.275953 CLK81: 166.6M
967 04:20:45.276388 smccc: 00012abe
968 04:20:45.280700 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
969 04:20:45.286336 board id: 1
970 04:20:45.292254 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
971 04:20:45.302724 fw parse done
972 04:20:45.308735 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
973 04:20:45.351421 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
974 04:20:45.362212 PIEI prepare done
975 04:20:45.362638 fastboot data load
976 04:20:45.363025 fastboot data verify
977 04:20:45.367814 verify result: 266
978 04:20:45.373428 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
979 04:20:45.373854 LPDDR4 probe
980 04:20:45.374238 ddr clk to 1584MHz
981 04:20:45.381453 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
982 04:20:45.418884
983 04:20:45.419458 dmc_version 0001
984 04:20:45.425513 Check phy result
985 04:20:45.431258 INFO : End of CA training
986 04:20:45.431685 INFO : End of initialization
987 04:20:45.436898 INFO : Training has run successfully!
988 04:20:45.437394 Check phy result
989 04:20:45.442465 INFO : End of initialization
990 04:20:45.442916 INFO : End of read enable training
991 04:20:45.445745 INFO : End of fine write leveling
992 04:20:45.451430 INFO : End of Write leveling coarse delay
993 04:20:45.456920 INFO : Training has run successfully!
994 04:20:45.457363 Check phy result
995 04:20:45.457773 INFO : End of initialization
996 04:20:45.462468 INFO : End of read dq deskew training
997 04:20:45.465885 INFO : End of MPR read delay center optimization
998 04:20:45.471388 INFO : End of write delay center optimization
999 04:20:45.477053 INFO : End of read delay center optimization
1000 04:20:45.477495 INFO : End of max read latency training
1001 04:20:45.482642 INFO : Training has run successfully!
1002 04:20:45.483076 1D training succeed
1003 04:20:45.490889 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 04:20:45.538479 Check phy result
1005 04:20:45.538944 INFO : End of initialization
1006 04:20:45.560053 INFO : End of 2D read delay Voltage center optimization
1007 04:20:45.580125 INFO : End of 2D read delay Voltage center optimization
1008 04:20:45.632200 INFO : End of 2D write delay Voltage center optimization
1009 04:20:45.681297 INFO : End of 2D write delay Voltage center optimization
1010 04:20:45.686793 INFO : Training has run successfully!
1011 04:20:45.687235
1012 04:20:45.687650 channel==0
1013 04:20:45.692459 RxClkDly_Margin_A0==88 ps 9
1014 04:20:45.692920 TxDqDly_Margin_A0==98 ps 10
1015 04:20:45.695759 RxClkDly_Margin_A1==88 ps 9
1016 04:20:45.696228 TxDqDly_Margin_A1==88 ps 9
1017 04:20:45.701330 TrainedVREFDQ_A0==74
1018 04:20:45.701769 TrainedVREFDQ_A1==74
1019 04:20:45.702180 VrefDac_Margin_A0==25
1020 04:20:45.706892 DeviceVref_Margin_A0==40
1021 04:20:45.707333 VrefDac_Margin_A1==25
1022 04:20:45.712504 DeviceVref_Margin_A1==40
1023 04:20:45.712947
1024 04:20:45.713354
1025 04:20:45.713755 channel==1
1026 04:20:45.714148 RxClkDly_Margin_A0==98 ps 10
1027 04:20:45.715938 TxDqDly_Margin_A0==98 ps 10
1028 04:20:45.721484 RxClkDly_Margin_A1==98 ps 10
1029 04:20:45.721928 TxDqDly_Margin_A1==88 ps 9
1030 04:20:45.722337 TrainedVREFDQ_A0==77
1031 04:20:45.727048 TrainedVREFDQ_A1==77
1032 04:20:45.727489 VrefDac_Margin_A0==22
1033 04:20:45.732734 DeviceVref_Margin_A0==37
1034 04:20:45.733169 VrefDac_Margin_A1==22
1035 04:20:45.733571 DeviceVref_Margin_A1==37
1036 04:20:45.733967
1037 04:20:45.738260 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1038 04:20:45.738699
1039 04:20:45.771813 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
1040 04:20:45.772313 2D training succeed
1041 04:20:45.777419 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1042 04:20:45.783040 auto size-- 65535DDR cs0 size: 2048MB
1043 04:20:45.783486 DDR cs1 size: 2048MB
1044 04:20:45.788722 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1045 04:20:45.789167 cs0 DataBus test pass
1046 04:20:45.789572 cs1 DataBus test pass
1047 04:20:45.794376 cs0 AddrBus test pass
1048 04:20:45.794821 cs1 AddrBus test pass
1049 04:20:45.795230
1050 04:20:45.799842 100bdlr_step_size ps== 420
1051 04:20:45.800328 result report
1052 04:20:45.800734 boot times 0Enable ddr reg access
1053 04:20:45.809745 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1054 04:20:45.823207 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1055 04:20:46.395562 0.0;M3 CHK:0;cm4_sp_mode 0
1056 04:20:46.396181 MVN_1=0x00000000
1057 04:20:46.400974 MVN_2=0x00000000
1058 04:20:46.406744 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1059 04:20:46.407291 OPS=0x10
1060 04:20:46.407761 ring efuse init
1061 04:20:46.408257 chipver efuse init
1062 04:20:46.412419 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1063 04:20:46.418057 [0.018960 Inits done]
1064 04:20:46.418651 secure task start!
1065 04:20:46.419123 high task start!
1066 04:20:46.422611 low task start!
1067 04:20:46.423161 run into bl31
1068 04:20:46.429111 NOTICE: BL31: v1.3(release):4fc40b1
1069 04:20:46.437006 NOTICE: BL31: Built : 15:58:17, May 22 2019
1070 04:20:46.437551 NOTICE: BL31: G12A normal boot!
1071 04:20:46.462298 NOTICE: BL31: BL33 decompress pass
1072 04:20:46.468047 ERROR: Error initializing runtime service opteed_fast
1073 04:20:47.700825
1074 04:20:47.701488
1075 04:20:47.709208 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1076 04:20:47.709760
1077 04:20:47.710228 Model: Libre Computer AML-A311D-CC Alta
1078 04:20:47.917657 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1079 04:20:47.941065 DRAM: 2 GiB (effective 3.8 GiB)
1080 04:20:48.084160 Core: 408 devices, 31 uclasses, devicetree: separate
1081 04:20:48.090005 WDT: Not starting watchdog@f0d0
1082 04:20:48.122208 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1083 04:20:48.134542 Loading Environment from FAT... Card did not respond to voltage select! : -110
1084 04:20:48.139517 ** Bad device specification mmc 0 **
1085 04:20:48.149961 Card did not respond to voltage select! : -110
1086 04:20:48.157534 ** Bad device specification mmc 0 **
1087 04:20:48.158079 Couldn't find partition mmc 0
1088 04:20:48.165919 Card did not respond to voltage select! : -110
1089 04:20:48.171362 ** Bad device specification mmc 0 **
1090 04:20:48.171905 Couldn't find partition mmc 0
1091 04:20:48.176446 Error: could not access storage.
1092 04:20:48.520055 Net: eth0: ethernet@ff3f0000
1093 04:20:48.520709 starting USB...
1094 04:20:48.771861 Bus usb@ff500000: Register 3000140 NbrPorts 3
1095 04:20:48.772530 Starting the controller
1096 04:20:48.778747 USB XHCI 1.10
1097 04:20:50.333054 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1098 04:20:50.341444 scanning usb for storage devices... 0 Storage Device(s) found
1100 04:20:50.393197 Hit any key to stop autoboot: 1
1101 04:20:50.394060 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1102 04:20:50.394776 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1103 04:20:50.395291 Setting prompt string to ['=>']
1104 04:20:50.395813 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1105 04:20:50.408736 0
1106 04:20:50.409714 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1107 04:20:50.410245 Sending with 10 millisecond of delay
1109 04:20:51.545212 => setenv autoload no
1110 04:20:51.556081 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1111 04:20:51.561475 setenv autoload no
1112 04:20:51.562294 Sending with 10 millisecond of delay
1114 04:20:53.359390 => setenv initrd_high 0xffffffff
1115 04:20:53.370279 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1116 04:20:53.371219 setenv initrd_high 0xffffffff
1117 04:20:53.372016 Sending with 10 millisecond of delay
1119 04:20:54.988525 => setenv fdt_high 0xffffffff
1120 04:20:54.999365 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1121 04:20:55.000330 setenv fdt_high 0xffffffff
1122 04:20:55.001104 Sending with 10 millisecond of delay
1124 04:20:55.293024 => dhcp
1125 04:20:55.303799 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1126 04:20:55.304732 dhcp
1127 04:20:55.305217 Speed: 1000, full duplex
1128 04:20:55.305675 BOOTP broadcast 1
1129 04:20:55.312316 DHCP client bound to address 192.168.6.27 (9 ms)
1130 04:20:55.313097 Sending with 10 millisecond of delay
1132 04:20:56.989709 => setenv serverip 192.168.6.2
1133 04:20:57.000553 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1134 04:20:57.001496 setenv serverip 192.168.6.2
1135 04:20:57.002237 Sending with 10 millisecond of delay
1137 04:21:00.725813 => tftpboot 0x01080000 950795/tftp-deploy-4717e21s/kernel/uImage
1138 04:21:00.736669 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1139 04:21:00.737599 tftpboot 0x01080000 950795/tftp-deploy-4717e21s/kernel/uImage
1140 04:21:00.738091 Speed: 1000, full duplex
1141 04:21:00.738550 Using ethernet@ff3f0000 device
1142 04:21:00.739781 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1143 04:21:00.745286 Filename '950795/tftp-deploy-4717e21s/kernel/uImage'.
1144 04:21:00.749076 Load address: 0x1080000
1145 04:21:03.549399 Loading: *################################################## 43.6 MiB
1146 04:21:03.550085 15.6 MiB/s
1147 04:21:03.550564 done
1148 04:21:03.553919 Bytes transferred = 45713984 (2b98a40 hex)
1149 04:21:03.554776 Sending with 10 millisecond of delay
1151 04:21:08.242574 => tftpboot 0x08000000 950795/tftp-deploy-4717e21s/ramdisk/ramdisk.cpio.gz.uboot
1152 04:21:08.253441 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1153 04:21:08.254370 tftpboot 0x08000000 950795/tftp-deploy-4717e21s/ramdisk/ramdisk.cpio.gz.uboot
1154 04:21:08.254860 Speed: 1000, full duplex
1155 04:21:08.255318 Using ethernet@ff3f0000 device
1156 04:21:08.256361 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1157 04:21:08.268049 Filename '950795/tftp-deploy-4717e21s/ramdisk/ramdisk.cpio.gz.uboot'.
1158 04:21:08.268620 Load address: 0x8000000
1159 04:21:14.869141 Loading: *######################T ########################### UDP wrong checksum 00000005 0000fe56
1160 04:21:19.869723 T UDP wrong checksum 00000005 0000fe56
1161 04:21:29.872846 T T UDP wrong checksum 00000005 0000fe56
1162 04:21:49.876938 T T T T UDP wrong checksum 00000005 0000fe56
1163 04:22:02.384313 T T UDP wrong checksum 000000ff 0000ef66
1164 04:22:02.424256 UDP wrong checksum 000000ff 00008b59
1165 04:22:04.880945
1166 04:22:04.881624 Retry count exceeded; starting again
1168 04:22:04.883133 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1171 04:22:04.885218 end: 2.4 uboot-commands (duration 00:01:51) [common]
1173 04:22:04.886712 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1175 04:22:04.887833 end: 2 uboot-action (duration 00:01:51) [common]
1177 04:22:04.889565 Cleaning after the job
1178 04:22:04.890181 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/ramdisk
1179 04:22:04.891719 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/kernel
1180 04:22:04.939631 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/dtb
1181 04:22:04.940480 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/nfsrootfs
1182 04:22:05.234220 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/950795/tftp-deploy-4717e21s/modules
1183 04:22:05.253016 start: 4.1 power-off (timeout 00:00:30) [common]
1184 04:22:05.253672 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1185 04:22:05.286402 >> OK - accepted request
1186 04:22:05.288539 Returned 0 in 0 seconds
1187 04:22:05.389346 end: 4.1 power-off (duration 00:00:00) [common]
1189 04:22:05.390340 start: 4.2 read-feedback (timeout 00:10:00) [common]
1190 04:22:05.390977 Listened to connection for namespace 'common' for up to 1s
1191 04:22:06.391923 Finalising connection for namespace 'common'
1192 04:22:06.392439 Disconnecting from shell: Finalise
1193 04:22:06.392706 =>
1194 04:22:06.493418 end: 4.2 read-feedback (duration 00:00:01) [common]
1195 04:22:06.493883 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/950795
1196 04:22:09.047326 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/950795
1197 04:22:09.047951 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.