Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 19:41:31.065699 lava-dispatcher, installed at version: 2024.01
2 19:41:31.066481 start: 0 validate
3 19:41:31.066964 Start time: 2024-11-07 19:41:31.066935+00:00 (UTC)
4 19:41:31.067499 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 19:41:31.068025 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 19:41:31.101411 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 19:41:31.102084 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-114-g80fb25341631b%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fkernel%2FzImage exists
8 19:41:31.132145 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 19:41:31.132706 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-114-g80fb25341631b%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 19:41:31.158446 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 19:41:31.158922 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 19:41:31.184724 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 19:41:31.185176 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-114-g80fb25341631b%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fmodules.tar.xz exists
14 19:41:31.216342 validate duration: 0.15
16 19:41:31.217236 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:41:31.217568 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:41:31.217895 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:41:31.218489 Not decompressing ramdisk as can be used compressed.
20 19:41:31.218915 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 19:41:31.219204 saving as /var/lib/lava/dispatcher/tmp/954958/tftp-deploy-lgfupg_3/ramdisk/initrd.cpio.gz
22 19:41:31.219473 total size: 4775763 (4 MB)
23 19:41:31.250585 progress 0 % (0 MB)
24 19:41:31.254178 progress 5 % (0 MB)
25 19:41:31.257447 progress 10 % (0 MB)
26 19:41:31.260734 progress 15 % (0 MB)
27 19:41:31.264400 progress 20 % (0 MB)
28 19:41:31.267628 progress 25 % (1 MB)
29 19:41:31.270804 progress 30 % (1 MB)
30 19:41:31.274341 progress 35 % (1 MB)
31 19:41:31.277503 progress 40 % (1 MB)
32 19:41:31.280766 progress 45 % (2 MB)
33 19:41:31.283909 progress 50 % (2 MB)
34 19:41:31.287492 progress 55 % (2 MB)
35 19:41:31.290624 progress 60 % (2 MB)
36 19:41:31.293737 progress 65 % (2 MB)
37 19:41:31.297218 progress 70 % (3 MB)
38 19:41:31.300416 progress 75 % (3 MB)
39 19:41:31.303597 progress 80 % (3 MB)
40 19:41:31.306772 progress 85 % (3 MB)
41 19:41:31.310539 progress 90 % (4 MB)
42 19:41:31.313517 progress 95 % (4 MB)
43 19:41:31.316392 progress 100 % (4 MB)
44 19:41:31.317018 4 MB downloaded in 0.10 s (46.70 MB/s)
45 19:41:31.317558 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:41:31.318465 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:41:31.318777 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:41:31.319060 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:41:31.319611 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/kernel/zImage
51 19:41:31.319884 saving as /var/lib/lava/dispatcher/tmp/954958/tftp-deploy-lgfupg_3/kernel/zImage
52 19:41:31.320123 total size: 12050944 (11 MB)
53 19:41:31.320343 No compression specified
54 19:41:31.359582 progress 0 % (0 MB)
55 19:41:31.367653 progress 5 % (0 MB)
56 19:41:31.375637 progress 10 % (1 MB)
57 19:41:31.384171 progress 15 % (1 MB)
58 19:41:31.392136 progress 20 % (2 MB)
59 19:41:31.399939 progress 25 % (2 MB)
60 19:41:31.408298 progress 30 % (3 MB)
61 19:41:31.416129 progress 35 % (4 MB)
62 19:41:31.424407 progress 40 % (4 MB)
63 19:41:31.432274 progress 45 % (5 MB)
64 19:41:31.440047 progress 50 % (5 MB)
65 19:41:31.448263 progress 55 % (6 MB)
66 19:41:31.456080 progress 60 % (6 MB)
67 19:41:31.464183 progress 65 % (7 MB)
68 19:41:31.472155 progress 70 % (8 MB)
69 19:41:31.480346 progress 75 % (8 MB)
70 19:41:31.488625 progress 80 % (9 MB)
71 19:41:31.496443 progress 85 % (9 MB)
72 19:41:31.504339 progress 90 % (10 MB)
73 19:41:31.512303 progress 95 % (10 MB)
74 19:41:31.519693 progress 100 % (11 MB)
75 19:41:31.520400 11 MB downloaded in 0.20 s (57.39 MB/s)
76 19:41:31.520917 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:41:31.521783 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:41:31.522084 start: 1.3 download-retry (timeout 00:10:00) [common]
80 19:41:31.522348 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 19:41:31.522814 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
82 19:41:31.523082 saving as /var/lib/lava/dispatcher/tmp/954958/tftp-deploy-lgfupg_3/dtb/am335x-boneblack.dtb
83 19:41:31.523287 total size: 70568 (0 MB)
84 19:41:31.523494 No compression specified
85 19:41:31.558729 progress 46 % (0 MB)
86 19:41:31.559580 progress 92 % (0 MB)
87 19:41:31.560261 progress 100 % (0 MB)
88 19:41:31.560650 0 MB downloaded in 0.04 s (1.80 MB/s)
89 19:41:31.561118 end: 1.3.1 http-download (duration 00:00:00) [common]
91 19:41:31.561979 end: 1.3 download-retry (duration 00:00:00) [common]
92 19:41:31.562263 start: 1.4 download-retry (timeout 00:10:00) [common]
93 19:41:31.562550 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 19:41:31.563058 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 19:41:31.563317 saving as /var/lib/lava/dispatcher/tmp/954958/tftp-deploy-lgfupg_3/nfsrootfs/full.rootfs.tar
96 19:41:31.563548 total size: 117747780 (112 MB)
97 19:41:31.563768 Using unxz to decompress xz
98 19:41:31.595832 progress 0 % (0 MB)
99 19:41:32.312929 progress 5 % (5 MB)
100 19:41:33.054343 progress 10 % (11 MB)
101 19:41:33.904676 progress 15 % (16 MB)
102 19:41:34.650874 progress 20 % (22 MB)
103 19:41:35.229551 progress 25 % (28 MB)
104 19:41:36.024720 progress 30 % (33 MB)
105 19:41:36.815969 progress 35 % (39 MB)
106 19:41:37.175171 progress 40 % (44 MB)
107 19:41:37.563217 progress 45 % (50 MB)
108 19:41:38.212723 progress 50 % (56 MB)
109 19:41:39.050634 progress 55 % (61 MB)
110 19:41:39.834063 progress 60 % (67 MB)
111 19:41:40.556748 progress 65 % (73 MB)
112 19:41:41.328255 progress 70 % (78 MB)
113 19:41:42.088130 progress 75 % (84 MB)
114 19:41:42.808892 progress 80 % (89 MB)
115 19:41:43.518170 progress 85 % (95 MB)
116 19:41:44.327393 progress 90 % (101 MB)
117 19:41:45.083619 progress 95 % (106 MB)
118 19:41:45.885711 progress 100 % (112 MB)
119 19:41:45.897923 112 MB downloaded in 14.33 s (7.83 MB/s)
120 19:41:45.898794 end: 1.4.1 http-download (duration 00:00:14) [common]
122 19:41:45.900404 end: 1.4 download-retry (duration 00:00:14) [common]
123 19:41:45.900928 start: 1.5 download-retry (timeout 00:09:45) [common]
124 19:41:45.901440 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 19:41:45.902351 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/modules.tar.xz
126 19:41:45.902818 saving as /var/lib/lava/dispatcher/tmp/954958/tftp-deploy-lgfupg_3/modules/modules.tar
127 19:41:45.903233 total size: 6916396 (6 MB)
128 19:41:45.903652 Using unxz to decompress xz
129 19:41:45.937159 progress 0 % (0 MB)
130 19:41:45.972306 progress 5 % (0 MB)
131 19:41:46.019655 progress 10 % (0 MB)
132 19:41:46.063314 progress 15 % (1 MB)
133 19:41:46.112865 progress 20 % (1 MB)
134 19:41:46.158062 progress 25 % (1 MB)
135 19:41:46.205999 progress 30 % (2 MB)
136 19:41:46.248792 progress 35 % (2 MB)
137 19:41:46.296380 progress 40 % (2 MB)
138 19:41:46.339391 progress 45 % (2 MB)
139 19:41:46.387597 progress 50 % (3 MB)
140 19:41:46.434023 progress 55 % (3 MB)
141 19:41:46.481396 progress 60 % (3 MB)
142 19:41:46.528425 progress 65 % (4 MB)
143 19:41:46.572905 progress 70 % (4 MB)
144 19:41:46.622167 progress 75 % (4 MB)
145 19:41:46.665034 progress 80 % (5 MB)
146 19:41:46.713072 progress 85 % (5 MB)
147 19:41:46.757916 progress 90 % (5 MB)
148 19:41:46.804905 progress 95 % (6 MB)
149 19:41:46.853532 progress 100 % (6 MB)
150 19:41:46.863747 6 MB downloaded in 0.96 s (6.87 MB/s)
151 19:41:46.864322 end: 1.5.1 http-download (duration 00:00:01) [common]
153 19:41:46.865147 end: 1.5 download-retry (duration 00:00:01) [common]
154 19:41:46.865417 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 19:41:46.865683 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 19:42:03.375412 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/954958/extract-nfsrootfs-cmbtkxxg
157 19:42:03.375975 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 19:42:03.376259 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 19:42:03.376891 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke
160 19:42:03.377343 makedir: /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin
161 19:42:03.377709 makedir: /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/tests
162 19:42:03.378070 makedir: /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/results
163 19:42:03.378407 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-add-keys
164 19:42:03.378935 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-add-sources
165 19:42:03.379444 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-background-process-start
166 19:42:03.379957 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-background-process-stop
167 19:42:03.380645 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-common-functions
168 19:42:03.381237 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-echo-ipv4
169 19:42:03.381773 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-install-packages
170 19:42:03.382338 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-installed-packages
171 19:42:03.382830 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-os-build
172 19:42:03.383319 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-probe-channel
173 19:42:03.383803 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-probe-ip
174 19:42:03.384282 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-target-ip
175 19:42:03.384763 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-target-mac
176 19:42:03.385239 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-target-storage
177 19:42:03.385751 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-test-case
178 19:42:03.386294 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-test-event
179 19:42:03.386777 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-test-feedback
180 19:42:03.387261 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-test-raise
181 19:42:03.387736 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-test-reference
182 19:42:03.388215 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-test-runner
183 19:42:03.388723 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-test-set
184 19:42:03.389204 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-test-shell
185 19:42:03.389715 Updating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-add-keys (debian)
186 19:42:03.390309 Updating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-add-sources (debian)
187 19:42:03.390822 Updating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-install-packages (debian)
188 19:42:03.391320 Updating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-installed-packages (debian)
189 19:42:03.391810 Updating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/bin/lava-os-build (debian)
190 19:42:03.392237 Creating /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/environment
191 19:42:03.392631 LAVA metadata
192 19:42:03.392893 - LAVA_JOB_ID=954958
193 19:42:03.393105 - LAVA_DISPATCHER_IP=192.168.6.3
194 19:42:03.393467 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 19:42:03.394420 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 19:42:03.394735 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 19:42:03.394939 skipped lava-vland-overlay
198 19:42:03.395175 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 19:42:03.395423 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 19:42:03.395637 skipped lava-multinode-overlay
201 19:42:03.395874 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 19:42:03.396121 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 19:42:03.396365 Loading test definitions
204 19:42:03.396636 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 19:42:03.396867 Using /lava-954958 at stage 0
206 19:42:03.397942 uuid=954958_1.6.2.4.1 testdef=None
207 19:42:03.398238 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 19:42:03.398496 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 19:42:03.400085 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 19:42:03.400867 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 19:42:03.402818 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 19:42:03.403631 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 19:42:03.405452 runner path: /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/0/tests/0_timesync-off test_uuid 954958_1.6.2.4.1
216 19:42:03.406059 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 19:42:03.406878 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 19:42:03.407101 Using /lava-954958 at stage 0
220 19:42:03.407454 Fetching tests from https://github.com/kernelci/test-definitions.git
221 19:42:03.407740 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/0/tests/1_kselftest-dt'
222 19:42:06.911641 Running '/usr/bin/git checkout kernelci.org
223 19:42:07.361530 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 19:42:07.363954 uuid=954958_1.6.2.4.5 testdef=None
225 19:42:07.364550 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 19:42:07.366011 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 19:42:07.371392 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 19:42:07.372952 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 19:42:07.380041 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 19:42:07.381672 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 19:42:07.388555 runner path: /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/0/tests/1_kselftest-dt test_uuid 954958_1.6.2.4.5
235 19:42:07.389075 BOARD='beaglebone-black'
236 19:42:07.389469 BRANCH='mainline'
237 19:42:07.389881 SKIPFILE='/dev/null'
238 19:42:07.390268 SKIP_INSTALL='True'
239 19:42:07.390647 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
240 19:42:07.391037 TST_CASENAME=''
241 19:42:07.391415 TST_CMDFILES='dt'
242 19:42:07.392382 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 19:42:07.393921 Creating lava-test-runner.conf files
245 19:42:07.394325 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/954958/lava-overlay-k6d7ipke/lava-954958/0 for stage 0
246 19:42:07.394988 - 0_timesync-off
247 19:42:07.395438 - 1_kselftest-dt
248 19:42:07.396056 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 19:42:07.396586 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 19:42:31.059906 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 19:42:31.060365 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 19:42:31.060654 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 19:42:31.060946 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 19:42:31.061255 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 19:42:31.422440 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 19:42:31.422916 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 19:42:31.423186 extracting modules file /var/lib/lava/dispatcher/tmp/954958/tftp-deploy-lgfupg_3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954958/extract-nfsrootfs-cmbtkxxg
258 19:42:32.336814 extracting modules file /var/lib/lava/dispatcher/tmp/954958/tftp-deploy-lgfupg_3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/954958/extract-overlay-ramdisk-d_jjvkha/ramdisk
259 19:42:33.340697 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 19:42:33.341196 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 19:42:33.341452 [common] Applying overlay to NFS
262 19:42:33.341664 [common] Applying overlay /var/lib/lava/dispatcher/tmp/954958/compress-overlay-6b759n7_/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/954958/extract-nfsrootfs-cmbtkxxg
263 19:42:36.172516 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 19:42:36.173001 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 19:42:36.173270 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 19:42:36.173588 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 19:42:36.173866 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 19:42:36.174129 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 19:42:36.174376 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 19:42:36.174629 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 19:42:36.174852 Building ramdisk /var/lib/lava/dispatcher/tmp/954958/extract-overlay-ramdisk-d_jjvkha/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/954958/extract-overlay-ramdisk-d_jjvkha/ramdisk
272 19:42:37.445424 >> 79012 blocks
273 19:42:42.458580 Adding RAMdisk u-boot header.
274 19:42:42.459085 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/954958/extract-overlay-ramdisk-d_jjvkha/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/954958/extract-overlay-ramdisk-d_jjvkha/ramdisk.cpio.gz.uboot
275 19:42:42.661517 output: Image Name:
276 19:42:42.662030 output: Created: Thu Nov 7 19:42:42 2024
277 19:42:42.662495 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 19:42:42.662939 output: Data Size: 15350330 Bytes = 14990.56 KiB = 14.64 MiB
279 19:42:42.663384 output: Load Address: 00000000
280 19:42:42.663818 output: Entry Point: 00000000
281 19:42:42.664251 output:
282 19:42:42.665522 rename /var/lib/lava/dispatcher/tmp/954958/extract-overlay-ramdisk-d_jjvkha/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/954958/tftp-deploy-lgfupg_3/ramdisk/ramdisk.cpio.gz.uboot
283 19:42:42.666362 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 19:42:42.666962 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 19:42:42.667542 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 19:42:42.668038 No LXC device requested
287 19:42:42.668594 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 19:42:42.669152 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 19:42:42.669694 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 19:42:42.670186 Checking files for TFTP limit of 4294967296 bytes.
291 19:42:42.673155 end: 1 tftp-deploy (duration 00:01:11) [common]
292 19:42:42.673842 start: 2 uboot-action (timeout 00:05:00) [common]
293 19:42:42.674429 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 19:42:42.674974 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 19:42:42.675526 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 19:42:42.676369 substitutions:
297 19:42:42.676834 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 19:42:42.677279 - {DTB_ADDR}: 0x88000000
299 19:42:42.677715 - {DTB}: 954958/tftp-deploy-lgfupg_3/dtb/am335x-boneblack.dtb
300 19:42:42.678183 - {INITRD}: 954958/tftp-deploy-lgfupg_3/ramdisk/ramdisk.cpio.gz.uboot
301 19:42:42.678617 - {KERNEL_ADDR}: 0x82000000
302 19:42:42.679043 - {KERNEL}: 954958/tftp-deploy-lgfupg_3/kernel/zImage
303 19:42:42.679470 - {LAVA_MAC}: None
304 19:42:42.679941 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/954958/extract-nfsrootfs-cmbtkxxg
305 19:42:42.680376 - {NFS_SERVER_IP}: 192.168.6.3
306 19:42:42.680807 - {PRESEED_CONFIG}: None
307 19:42:42.681234 - {PRESEED_LOCAL}: None
308 19:42:42.681658 - {RAMDISK_ADDR}: 0x83000000
309 19:42:42.682108 - {RAMDISK}: 954958/tftp-deploy-lgfupg_3/ramdisk/ramdisk.cpio.gz.uboot
310 19:42:42.682538 - {ROOT_PART}: None
311 19:42:42.682959 - {ROOT}: None
312 19:42:42.683381 - {SERVER_IP}: 192.168.6.3
313 19:42:42.683801 - {TEE_ADDR}: 0x83000000
314 19:42:42.684221 - {TEE}: None
315 19:42:42.684642 Parsed boot commands:
316 19:42:42.685052 - setenv autoload no
317 19:42:42.685472 - setenv initrd_high 0xffffffff
318 19:42:42.685917 - setenv fdt_high 0xffffffff
319 19:42:42.686338 - dhcp
320 19:42:42.686758 - setenv serverip 192.168.6.3
321 19:42:42.687176 - tftp 0x82000000 954958/tftp-deploy-lgfupg_3/kernel/zImage
322 19:42:42.687594 - tftp 0x83000000 954958/tftp-deploy-lgfupg_3/ramdisk/ramdisk.cpio.gz.uboot
323 19:42:42.688010 - setenv initrd_size ${filesize}
324 19:42:42.688425 - tftp 0x88000000 954958/tftp-deploy-lgfupg_3/dtb/am335x-boneblack.dtb
325 19:42:42.688843 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/954958/extract-nfsrootfs-cmbtkxxg,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 19:42:42.689272 - bootz 0x82000000 0x83000000 0x88000000
327 19:42:42.689843 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 19:42:42.691493 start: 2.3 connect-device (timeout 00:05:00) [common]
330 19:42:42.691953 [common] connect-device Connecting to device using 'telnet conserv3 3000'
331 19:42:42.708120 Setting prompt string to ['lava-test: # ']
332 19:42:42.709804 end: 2.3 connect-device (duration 00:00:00) [common]
333 19:42:42.710528 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 19:42:42.711134 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 19:42:42.711715 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 19:42:42.713029 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
337 19:42:42.751648 >> OK - accepted request
338 19:42:42.753628 Returned 0 in 0 seconds
339 19:42:42.854919 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 19:42:42.856800 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 19:42:42.857410 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 19:42:42.858039 Setting prompt string to ['Hit any key to stop autoboot']
344 19:42:42.858566 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 19:42:42.860248 Trying 192.168.56.22...
346 19:42:42.860786 Connected to conserv3.
347 19:42:42.861259 Escape character is '^]'.
348 19:42:42.861721
349 19:42:42.862227 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 19:42:42.862679
351 19:42:50.668958
352 19:42:50.675937 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
353 19:42:50.676285 Trying to boot from MMC1
354 19:42:51.262002
355 19:42:51.262691
356 19:42:51.267353 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
357 19:42:51.267682
358 19:42:51.267930 CPU : AM335X-GP rev 2.0
359 19:42:51.272823 Model: TI AM335x BeagleBone Black
360 19:42:51.273168 DRAM: 512 MiB
361 19:42:54.723903
362 19:42:54.730924 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
363 19:42:54.731500 Trying to boot from MMC1
364 19:42:55.316736
365 19:42:55.317407
366 19:42:55.322250 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
367 19:42:55.322776
368 19:42:55.323239 CPU : AM335X-GP rev 2.0
369 19:42:55.327567 Model: TI AM335x BeagleBone Black
370 19:42:55.328077 DRAM: 512 MiB
371 19:42:57.421641
372 19:42:57.428840 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
373 19:42:57.429379 Trying to boot from MMC1
374 19:42:58.018754
375 19:42:58.019413
376 19:42:58.024450 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
377 19:42:58.024994
378 19:42:58.025478 CPU : AM335X-GP rev 2.0
379 19:42:58.029668 Model: TI AM335x BeagleBone Black
380 19:42:58.030248 DRAM: 512 MiB
381 19:42:58.114460 Core: 160 devices, 18 uclasses, devicetree: separate
382 19:42:58.128244 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 19:42:58.529073 NAND: 0 MiB
384 19:42:58.539172 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 19:42:58.614017 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 19:42:58.635083 <ethaddr> not set. Validating first E-fuse MAC
387 19:42:58.664890 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 19:42:58.723619 Hit any key to stop autoboot: 2
390 19:42:58.724875 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
391 19:42:58.725580 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
392 19:42:58.726175 Setting prompt string to ['=>']
393 19:42:58.726721 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
394 19:42:58.733373 0
395 19:42:58.734505 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 19:42:58.735070 Sending with 10 millisecond of delay
398 19:42:59.871234 => setenv autoload no
399 19:42:59.882027 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
400 19:42:59.886917 setenv autoload no
401 19:42:59.887677 Sending with 10 millisecond of delay
403 19:43:01.684668 => setenv initrd_high 0xffffffff
404 19:43:01.695436 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
405 19:43:01.696258 setenv initrd_high 0xffffffff
406 19:43:01.696960 Sending with 10 millisecond of delay
408 19:43:03.314251 => setenv fdt_high 0xffffffff
409 19:43:03.325067 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
410 19:43:03.325993 setenv fdt_high 0xffffffff
411 19:43:03.326705 Sending with 10 millisecond of delay
413 19:43:03.618622 => dhcp
414 19:43:03.629169 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
415 19:43:03.629639 dhcp
416 19:43:03.629907 link up on port 0, speed 100, full duplex
417 19:43:03.630157 BOOTP broadcast 1
418 19:43:03.884118 BOOTP broadcast 2
419 19:43:04.386208 BOOTP broadcast 3
420 19:43:05.388283 BOOTP broadcast 4
421 19:43:05.467161 DHCP client bound to address 192.168.6.23 (1832 ms)
422 19:43:05.467865 Sending with 10 millisecond of delay
424 19:43:07.145034 => setenv serverip 192.168.6.3
425 19:43:07.155796 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
426 19:43:07.156609 setenv serverip 192.168.6.3
427 19:43:07.157327 Sending with 10 millisecond of delay
429 19:43:10.640484 => tftp 0x82000000 954958/tftp-deploy-lgfupg_3/kernel/zImage
430 19:43:10.651325 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
431 19:43:10.652230 tftp 0x82000000 954958/tftp-deploy-lgfupg_3/kernel/zImage
432 19:43:10.652657 link up on port 0, speed 100, full duplex
433 19:43:10.656193 Using ethernet@4a100000 device
434 19:43:10.661722 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
435 19:43:10.662223 Filename '954958/tftp-deploy-lgfupg_3/kernel/zImage'.
436 19:43:10.668767 Load address: 0x82000000
437 19:43:12.849661 Loading: *################################################## 11.5 MiB
438 19:43:12.850231 5.3 MiB/s
439 19:43:12.850709 done
440 19:43:12.854243 Bytes transferred = 12050944 (b7e200 hex)
441 19:43:12.855206 Sending with 10 millisecond of delay
443 19:43:17.304108 => tftp 0x83000000 954958/tftp-deploy-lgfupg_3/ramdisk/ramdisk.cpio.gz.uboot
444 19:43:17.314958 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
445 19:43:17.315801 tftp 0x83000000 954958/tftp-deploy-lgfupg_3/ramdisk/ramdisk.cpio.gz.uboot
446 19:43:17.316269 link up on port 0, speed 100, full duplex
447 19:43:17.320174 Using ethernet@4a100000 device
448 19:43:17.325865 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
449 19:43:17.334294 Filename '954958/tftp-deploy-lgfupg_3/ramdisk/ramdisk.cpio.gz.uboot'.
450 19:43:17.334630 Load address: 0x83000000
451 19:43:20.036922 Loading: *################################################## 14.6 MiB
452 19:43:20.037553 5.4 MiB/s
453 19:43:20.038061 done
454 19:43:20.041122 Bytes transferred = 15350394 (ea3a7a hex)
455 19:43:20.041942 Sending with 10 millisecond of delay
457 19:43:21.899543 => setenv initrd_size ${filesize}
458 19:43:21.910069 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
459 19:43:21.910546 setenv initrd_size ${filesize}
460 19:43:21.911513 Sending with 10 millisecond of delay
462 19:43:26.059545 => tftp 0x88000000 954958/tftp-deploy-lgfupg_3/dtb/am335x-boneblack.dtb
463 19:43:26.070809 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
464 19:43:26.071469 tftp 0x88000000 954958/tftp-deploy-lgfupg_3/dtb/am335x-boneblack.dtb
465 19:43:26.071722 link up on port 0, speed 100, full duplex
466 19:43:26.075477 Using ethernet@4a100000 device
467 19:43:26.081055 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
468 19:43:26.093525 Filename '954958/tftp-deploy-lgfupg_3/dtb/am335x-boneblack.dtb'.
469 19:43:26.093981 Load address: 0x88000000
470 19:43:26.104580 Loading: *################################################## 68.9 KiB
471 19:43:26.105008 4.8 MiB/s
472 19:43:26.105226 done
473 19:43:26.109984 Bytes transferred = 70568 (113a8 hex)
474 19:43:26.110623 Sending with 10 millisecond of delay
476 19:43:39.290416 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/954958/extract-nfsrootfs-cmbtkxxg,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
477 19:43:39.301289 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
478 19:43:39.302298 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/954958/extract-nfsrootfs-cmbtkxxg,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
479 19:43:39.303063 Sending with 10 millisecond of delay
481 19:43:41.642212 => bootz 0x82000000 0x83000000 0x88000000
482 19:43:41.653114 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 19:43:41.653783 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
484 19:43:41.654953 bootz 0x82000000 0x83000000 0x88000000
485 19:43:41.655469 Kernel image @ 0x82000000 [ 0x000000 - 0xb7e200 ]
486 19:43:41.656022 ## Loading init Ramdisk from Legacy Image at 83000000 ...
487 19:43:41.661211 Image Name:
488 19:43:41.661731 Created: 2024-11-07 19:42:42 UTC
489 19:43:41.664267 Image Type: ARM Linux RAMDisk Image (uncompressed)
490 19:43:41.669722 Data Size: 15350330 Bytes = 14.6 MiB
491 19:43:41.678131 Load Address: 00000000
492 19:43:41.678662 Entry Point: 00000000
493 19:43:41.852731 Verifying Checksum ... OK
494 19:43:41.853370 ## Flattened Device Tree blob at 88000000
495 19:43:41.859312 Booting using the fdt blob at 0x88000000
496 19:43:41.859846 Working FDT set to 88000000
497 19:43:41.864916 Using Device Tree in place at 88000000, end 880143a7
498 19:43:41.869272 Working FDT set to 88000000
499 19:43:41.882568
500 19:43:41.883107 Starting kernel ...
501 19:43:41.883570
502 19:43:41.884519 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
503 19:43:41.885169 start: 2.4.4 auto-login-action (timeout 00:04:01) [common]
504 19:43:41.885689 Setting prompt string to ['Linux version [0-9]']
505 19:43:41.886246 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
506 19:43:41.886783 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
507 19:43:42.777171 [ 0.000000] Booting Linux on physical CPU 0x0
508 19:43:42.783085 start: 2.4.4.1 login-action (timeout 00:04:00) [common]
509 19:43:42.783706 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
510 19:43:42.784227 Setting prompt string to []
511 19:43:42.784772 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
512 19:43:42.785287 Using line separator: #'\n'#
513 19:43:42.785742 No login prompt set.
514 19:43:42.786275 Parsing kernel messages
515 19:43:42.786722 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
516 19:43:42.787598 [login-action] Waiting for messages, (timeout 00:04:00)
517 19:43:42.788315 Waiting using forced prompt support (timeout 00:02:00)
518 19:43:42.797000 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j367068-arm-clang-15-multi-v7-defconfig-8xshf) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Thu Nov 7 18:55:34 UTC 2024
519 19:43:42.802669 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
520 19:43:42.808415 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
521 19:43:42.814130 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
522 19:43:42.819818 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
523 19:43:42.825504 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
524 19:43:42.831309 [ 0.000000] Memory policy: Data cache writeback
525 19:43:42.838291 [ 0.000000] efi: UEFI not found.
526 19:43:42.846833 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
527 19:43:42.847396 [ 0.000000] Zone ranges:
528 19:43:42.852459 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
529 19:43:42.858164 [ 0.000000] Normal empty
530 19:43:42.858718 [ 0.000000] HighMem empty
531 19:43:42.864031 [ 0.000000] Movable zone start for each node
532 19:43:42.869742 [ 0.000000] Early memory node ranges
533 19:43:42.875476 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
534 19:43:42.882370 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
535 19:43:42.900630 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 19:43:42.906232 [ 0.000000] AM335X ES2.0 (sgx neon)
537 19:43:42.918124 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
538 19:43:42.935799 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/954958/extract-nfsrootfs-cmbtkxxg,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 19:43:42.947332 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
540 19:43:42.953166 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
541 19:43:42.958889 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
542 19:43:42.968855 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
543 19:43:42.998182 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
544 19:43:43.004229 <6>[ 0.000000] trace event string verifier disabled
545 19:43:43.004752 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
546 19:43:43.009932 <6>[ 0.000000] rcu: RCU event tracing is enabled.
547 19:43:43.021368 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
548 19:43:43.027155 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
549 19:43:43.034434 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
550 19:43:43.049489 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
551 19:43:43.067765 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
552 19:43:43.074514 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
553 19:43:43.177953 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
554 19:43:43.189396 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
555 19:43:43.196271 <6>[ 0.008340] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
556 19:43:43.209288 <6>[ 0.019249] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
557 19:43:43.217287 <6>[ 0.034612] Console: colour dummy device 80x30
558 19:43:43.223398 Matched prompt #6: WARNING:
559 19:43:43.223901 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
560 19:43:43.228747 <3>[ 0.039607] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
561 19:43:43.234474 <3>[ 0.046598] This ensures that you still see kernel messages. Please
562 19:43:43.237718 <3>[ 0.053323] update your kernel commandline.
563 19:43:43.277976 <6>[ 0.057932] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
564 19:43:43.283598 <6>[ 0.096257] CPU: Testing write buffer coherency: ok
565 19:43:43.289545 <6>[ 0.101630] CPU0: Spectre v2: using BPIALL workaround
566 19:43:43.290087 <6>[ 0.107098] pid_max: default: 32768 minimum: 301
567 19:43:43.300978 <6>[ 0.112298] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 19:43:43.308028 <6>[ 0.120121] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 19:43:43.315119 <6>[ 0.129577] CPU0: thread -1, cpu 0, socket -1, mpidr 0
570 19:43:43.323844 <6>[ 0.136567] Setting up static identity map for 0x80300000 - 0x803000ac
571 19:43:43.329612 <6>[ 0.146407] rcu: Hierarchical SRCU implementation.
572 19:43:43.337274 <6>[ 0.151699] rcu: Max phase no-delay instances is 1000.
573 19:43:43.346357 <6>[ 0.163380] EFI services will not be available.
574 19:43:43.352277 <6>[ 0.168682] smp: Bringing up secondary CPUs ...
575 19:43:43.358135 <6>[ 0.173751] smp: Brought up 1 node, 1 CPU
576 19:43:43.363821 <6>[ 0.178151] SMP: Total of 1 processors activated (996.14 BogoMIPS).
577 19:43:43.369737 <6>[ 0.184921] CPU: All CPU(s) started in SVC mode.
578 19:43:43.390173 <6>[ 0.190128] Memory: 404432K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50616K reserved, 65536K cma-reserved, 0K highmem)
579 19:43:43.390767 <6>[ 0.206425] devtmpfs: initialized
580 19:43:43.413268 <6>[ 0.224433] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
581 19:43:43.424794 <6>[ 0.233060] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
582 19:43:43.430779 <6>[ 0.243526] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
583 19:43:43.441534 <6>[ 0.255902] pinctrl core: initialized pinctrl subsystem
584 19:43:43.451267 <6>[ 0.266987] DMI not present or invalid.
585 19:43:43.459819 <6>[ 0.272886] NET: Registered PF_NETLINK/PF_ROUTE protocol family
586 19:43:43.469269 <6>[ 0.281906] DMA: preallocated 256 KiB pool for atomic coherent allocations
587 19:43:43.484661 <6>[ 0.293639] thermal_sys: Registered thermal governor 'step_wise'
588 19:43:43.485268 <6>[ 0.293835] cpuidle: using governor menu
589 19:43:43.512396 <6>[ 0.329655] No ATAGs?
590 19:43:43.518542 <6>[ 0.332299] hw-breakpoint: debug architecture 0x4 unsupported.
591 19:43:43.529104 <6>[ 0.344599] Serial: AMBA PL011 UART driver
592 19:43:43.558211 <6>[ 0.375280] iommu: Default domain type: Translated
593 19:43:43.567196 <6>[ 0.380634] iommu: DMA domain TLB invalidation policy: strict mode
594 19:43:43.594919 <5>[ 0.410780] SCSI subsystem initialized
595 19:43:43.608808 <6>[ 0.420223] usbcore: registered new interface driver usbfs
596 19:43:43.615587 <6>[ 0.426193] usbcore: registered new interface driver hub
597 19:43:43.616163 <6>[ 0.432025] usbcore: registered new device driver usb
598 19:43:43.621305 <6>[ 0.438582] pps_core: LinuxPPS API ver. 1 registered
599 19:43:43.632946 <6>[ 0.444013] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
600 19:43:43.641759 <6>[ 0.453732] PTP clock support registered
601 19:43:43.642380 <6>[ 0.458180] EDAC MC: Ver: 3.0.0
602 19:43:43.696572 <6>[ 0.510900] scmi_core: SCMI protocol bus registered
603 19:43:43.702253 <6>[ 0.519070] vgaarb: loaded
604 19:43:43.714500 <6>[ 0.531852] clocksource: Switched to clocksource dmtimer
605 19:43:43.742373 <6>[ 0.559168] NET: Registered PF_INET protocol family
606 19:43:43.754980 <6>[ 0.564912] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
607 19:43:43.760895 <6>[ 0.573912] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
608 19:43:43.772360 <6>[ 0.582847] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
609 19:43:43.778055 <6>[ 0.591094] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
610 19:43:43.789670 <6>[ 0.599382] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
611 19:43:43.795608 <6>[ 0.607101] TCP: Hash tables configured (established 4096 bind 4096)
612 19:43:43.801876 <6>[ 0.614023] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
613 19:43:43.807268 <6>[ 0.621039] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
614 19:43:43.814712 <6>[ 0.628655] NET: Registered PF_UNIX/PF_LOCAL protocol family
615 19:43:43.907859 <6>[ 0.719279] RPC: Registered named UNIX socket transport module.
616 19:43:43.908489 <6>[ 0.725727] RPC: Registered udp transport module.
617 19:43:43.913540 <6>[ 0.730837] RPC: Registered tcp transport module.
618 19:43:43.919204 <6>[ 0.735966] RPC: Registered tcp-with-tls transport module.
619 19:43:43.932250 <6>[ 0.741891] RPC: Registered tcp NFSv4.1 backchannel transport module.
620 19:43:43.932610 <6>[ 0.748800] PCI: CLS 0 bytes, default 64
621 19:43:43.939398 <5>[ 0.754671] Initialise system trusted keyrings
622 19:43:43.961607 <6>[ 0.775732] Trying to unpack rootfs image as initramfs...
623 19:43:44.031142 <6>[ 0.842126] workingset: timestamp_bits=30 max_order=17 bucket_order=0
624 19:43:44.035833 <6>[ 0.849654] squashfs: version 4.0 (2009/01/31) Phillip Lougher
625 19:43:44.065264 <5>[ 0.882442] NFS: Registering the id_resolver key type
626 19:43:44.071106 <5>[ 0.888028] Key type id_resolver registered
627 19:43:44.076982 <5>[ 0.892721] Key type id_legacy registered
628 19:43:44.082637 <6>[ 0.897166] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
629 19:43:44.091409 <6>[ 0.904372] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
630 19:43:44.178310 <5>[ 0.995604] Key type asymmetric registered
631 19:43:44.184227 <5>[ 1.000130] Asymmetric key parser 'x509' registered
632 19:43:44.192443 <6>[ 1.005630] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
633 19:43:44.198383 <6>[ 1.013578] io scheduler mq-deadline registered
634 19:43:44.207224 <6>[ 1.018511] io scheduler kyber registered
635 19:43:44.207866 <6>[ 1.022986] io scheduler bfq registered
636 19:43:44.328319 <6>[ 1.142038] ledtrig-cpu: registered to indicate activity on CPUs
637 19:43:44.623133 <6>[ 1.436498] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
638 19:43:44.649969 <6>[ 1.466984] msm_serial: driver initialized
639 19:43:44.655948 <6>[ 1.471783] SuperH (H)SCI(F) driver initialized
640 19:43:44.661885 <6>[ 1.477108] STMicroelectronics ASC driver initialized
641 19:43:44.667099 <6>[ 1.482766] STM32 USART driver initialized
642 19:43:44.794004 <6>[ 1.610669] brd: module loaded
643 19:43:44.839808 <6>[ 1.656397] loop: module loaded
644 19:43:44.893737 <6>[ 1.710127] CAN device driver interface
645 19:43:44.900511 <6>[ 1.715429] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
646 19:43:44.906104 <6>[ 1.722547] e1000e: Intel(R) PRO/1000 Network Driver
647 19:43:44.912823 <6>[ 1.727937] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
648 19:43:44.918540 <6>[ 1.734396] igb: Intel(R) Gigabit Ethernet Network Driver
649 19:43:44.926040 <6>[ 1.740223] igb: Copyright (c) 2007-2014 Intel Corporation.
650 19:43:44.937993 <6>[ 1.749538] pegasus: Pegasus/Pegasus II USB Ethernet driver
651 19:43:44.943826 <6>[ 1.755698] usbcore: registered new interface driver pegasus
652 19:43:44.949553 <6>[ 1.761859] usbcore: registered new interface driver asix
653 19:43:44.955352 <6>[ 1.767713] usbcore: registered new interface driver ax88179_178a
654 19:43:44.961134 <6>[ 1.774318] usbcore: registered new interface driver cdc_ether
655 19:43:44.966993 <6>[ 1.780618] usbcore: registered new interface driver smsc75xx
656 19:43:44.972745 <6>[ 1.786881] usbcore: registered new interface driver smsc95xx
657 19:43:44.978460 <6>[ 1.793126] usbcore: registered new interface driver net1080
658 19:43:44.984278 <6>[ 1.799246] usbcore: registered new interface driver cdc_subset
659 19:43:44.990047 <6>[ 1.805659] usbcore: registered new interface driver zaurus
660 19:43:44.997678 <6>[ 1.811705] usbcore: registered new interface driver cdc_ncm
661 19:43:45.006598 <6>[ 1.821252] usbcore: registered new interface driver usb-storage
662 19:43:45.017206 <6>[ 1.832599] i2c_dev: i2c /dev entries driver
663 19:43:45.041593 <5>[ 1.850893] cpuidle: enable-method property 'ti,am3352' found operations
664 19:43:45.047489 <6>[ 1.860451] sdhci: Secure Digital Host Controller Interface driver
665 19:43:45.054996 <6>[ 1.867232] sdhci: Copyright(c) Pierre Ossman
666 19:43:45.062100 <6>[ 1.873716] Synopsys Designware Multimedia Card Interface Driver
667 19:43:45.067564 <6>[ 1.881526] sdhci-pltfm: SDHCI platform and OF driver helper
668 19:43:45.080817 <6>[ 1.891508] usbcore: registered new interface driver usbhid
669 19:43:45.081329 <6>[ 1.897659] usbhid: USB HID core driver
670 19:43:45.094638 <6>[ 1.909307] NET: Registered PF_INET6 protocol family
671 19:43:45.555994 <6>[ 2.373353] Segment Routing with IPv6
672 19:43:45.561842 <6>[ 2.377507] In-situ OAM (IOAM) with IPv6
673 19:43:45.568667 <6>[ 2.382034] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
674 19:43:45.575992 <6>[ 2.389387] NET: Registered PF_PACKET protocol family
675 19:43:45.582009 <6>[ 2.394959] can: controller area network core
676 19:43:45.582550 <6>[ 2.399786] NET: Registered PF_CAN protocol family
677 19:43:45.587707 <6>[ 2.405017] can: raw protocol
678 19:43:45.593422 <6>[ 2.408344] can: broadcast manager protocol
679 19:43:45.600361 <6>[ 2.412952] can: netlink gateway - max_hops=1
680 19:43:45.600825 <5>[ 2.418462] Key type dns_resolver registered
681 19:43:45.606144 <6>[ 2.423545] ThumbEE CPU extension supported.
682 19:43:45.612351 <5>[ 2.428236] Registering SWP/SWPB emulation handler
683 19:43:45.619913 <3>[ 2.433946] omap_voltage_late_init: Voltage driver support not added
684 19:43:45.823990 <5>[ 2.638892] Loading compiled-in X.509 certificates
685 19:43:45.967344 <6>[ 2.771694] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
686 19:43:45.973774 <6>[ 2.788467] pinctrl-single 44e10800.pinmux: 142 pins, size 568
687 19:43:46.001988 <3>[ 2.813071] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
688 19:43:46.184448 <3>[ 2.995674] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
689 19:43:46.407454 <6>[ 3.222937] OMAP GPIO hardware version 0.1
690 19:43:46.428674 <6>[ 3.242322] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
691 19:43:46.510724 <4>[ 3.324092] at24 2-0054: supply vcc not found, using dummy regulator
692 19:43:46.542494 <4>[ 3.355897] at24 2-0055: supply vcc not found, using dummy regulator
693 19:43:46.583895 <4>[ 3.397270] at24 2-0056: supply vcc not found, using dummy regulator
694 19:43:46.621632 <4>[ 3.435817] at24 2-0057: supply vcc not found, using dummy regulator
695 19:43:46.662526 <6>[ 3.476544] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
696 19:43:46.718707 <3>[ 3.528863] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
697 19:43:46.743862 <6>[ 3.550255] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 19:43:46.766813 <4>[ 3.577574] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
699 19:43:46.774715 <4>[ 3.586637] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
700 19:43:46.861089 <6>[ 3.677271] Freeing initrd memory: 14992K
701 19:43:46.869333 <6>[ 3.682816] omap_rng 48310000.rng: Random Number Generator ver. 20
702 19:43:46.893449 <5>[ 3.709731] random: crng init done
703 19:43:46.939841 <6>[ 3.751869] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
704 19:43:46.993220 <6>[ 3.804321] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
705 19:43:46.999074 <6>[ 3.814656] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
706 19:43:47.010812 <6>[ 3.821998] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
707 19:43:47.016661 <6>[ 3.829478] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
708 19:43:47.028132 <6>[ 3.837622] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
709 19:43:47.035651 <6>[ 3.849262] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
710 19:43:47.048848 <5>[ 3.858379] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
711 19:43:47.077439 <3>[ 3.889036] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
712 19:43:47.083213 <6>[ 3.897657] edma 49000000.dma: TI EDMA DMA engine driver
713 19:43:47.156851 <3>[ 3.967745] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
714 19:43:47.172153 <6>[ 3.982738] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
715 19:43:47.185140 <3>[ 3.999891] l3-aon-clkctrl:0000:0: failed to disable
716 19:43:47.239017 <6>[ 4.050502] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
717 19:43:47.244742 <6>[ 4.060032] printk: legacy console [ttyS0] enabled
718 19:43:47.250457 <6>[ 4.060032] printk: legacy console [ttyS0] enabled
719 19:43:47.256109 <6>[ 4.070368] printk: legacy bootconsole [omap8250] disabled
720 19:43:47.261033 <6>[ 4.070368] printk: legacy bootconsole [omap8250] disabled
721 19:43:47.292165 <4>[ 4.102706] tps65217-pmic: Failed to locate of_node [id: -1]
722 19:43:47.294943 <4>[ 4.110123] tps65217-bl: Failed to locate of_node [id: -1]
723 19:43:47.312933 <6>[ 4.130494] tps65217 0-0024: TPS65217 ID 0xe version 1.2
724 19:43:47.331372 <6>[ 4.137527] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
725 19:43:47.343095 <6>[ 4.151227] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
726 19:43:47.348990 <6>[ 4.163134] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
727 19:43:47.371505 <6>[ 4.183389] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
728 19:43:47.377381 <6>[ 4.192563] sdhci-omap 48060000.mmc: Got CD GPIO
729 19:43:47.385467 <4>[ 4.197715] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
730 19:43:47.400516 <4>[ 4.211602] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
731 19:43:47.406953 <4>[ 4.220292] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
732 19:43:47.416705 <4>[ 4.229036] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
733 19:43:47.516340 <6>[ 4.329326] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
734 19:43:47.554904 <6>[ 4.367768] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
735 19:43:47.576296 <6>[ 4.387422] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
736 19:43:47.583056 <6>[ 4.396402] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
737 19:43:47.623849 <6>[ 4.431321] mmc0: new high speed SDHC card at address 0001
738 19:43:47.624289 <6>[ 4.439383] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
739 19:43:47.630936 <6>[ 4.448249] mmcblk0: p1
740 19:43:47.663813 <6>[ 4.473145] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
741 19:43:47.684592 <6>[ 4.492790] mmc1: new high speed MMC card at address 0001
742 19:43:47.685040 <6>[ 4.500066] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
743 19:43:47.693006 <6>[ 4.509858] mmcblk1:
744 19:43:47.701035 <6>[ 4.513198] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
745 19:43:47.708925 <6>[ 4.520783] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
746 19:43:47.714605 <6>[ 4.528252] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
747 19:43:49.781433 <6>[ 6.592927] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
748 19:43:50.084888 <5>[ 6.621961] Sending DHCP requests ., OK
749 19:43:50.096076 <6>[ 6.906311] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.23
750 19:43:50.096548 <6>[ 6.914501] IP-Config: Complete:
751 19:43:50.110178 <6>[ 6.918041] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.6.23, mask=255.255.255.0, gw=192.168.6.1
752 19:43:50.115815 <6>[ 6.928562] host=192.168.6.23, domain=, nis-domain=(none)
753 19:43:50.119277 <6>[ 6.934777] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
754 19:43:50.125893 <6>[ 6.934815] nameserver0=10.255.253.1
755 19:43:50.131973 <6>[ 6.947446] clk: Disabling unused clocks
756 19:43:50.137305 <6>[ 6.952215] PM: genpd: Disabling unused power domains
757 19:43:50.155496 <6>[ 6.969484] Freeing unused kernel image (initmem) memory: 2048K
758 19:43:50.163137 <6>[ 6.979390] Run /init as init process
759 19:43:50.189403 Loading, please wait...
760 19:43:50.267798 Starting systemd-udevd version 252.22-1~deb12u1
761 19:43:53.243738 <4>[ 10.053918] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
762 19:43:53.473335 <4>[ 10.283440] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
763 19:43:53.624040 <6>[ 10.441610] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
764 19:43:53.634879 <6>[ 10.447495] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
765 19:43:53.826920 <6>[ 10.643243] hub 1-0:1.0: USB hub found
766 19:43:53.897206 <6>[ 10.713151] hub 1-0:1.0: 1 port detected
767 19:43:54.090578 <6>[ 10.906323] tda998x 0-0070: found TDA19988
768 19:43:56.950577 Begin: Loading essential drivers ... done.
769 19:43:56.960768 Begin: Running /scripts/init-premount ... done.
770 19:43:56.971948 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
771 19:43:56.975263 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
772 19:43:56.984269 Device /sys/class/net/eth0 found
773 19:43:56.984831 done.
774 19:43:57.066326 Begin: Waiting up to 180 secs for any network device to become available ... done.
775 19:43:57.136562 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
776 19:43:57.225445 IP-Config: eth0 guessed broadcast address 192.168.6.255
777 19:43:57.231017 IP-Config: eth0 complete (dhcp from 192.168.6.1):
778 19:43:57.236519 address: 192.168.6.23 broadcast: 192.168.6.255 netmask: 255.255.255.0
779 19:43:57.247566 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
780 19:43:57.247900 rootserver: 192.168.6.1 rootpath:
781 19:43:57.251310 filename :
782 19:43:57.341860 done.
783 19:43:57.358320 Begin: Running /scripts/nfs-bottom ... done.
784 19:43:57.427115 Begin: Running /scripts/init-bottom ... done.
785 19:43:59.023272 <30>[ 15.837696] systemd[1]: System time before build time, advancing clock.
786 19:43:59.183178 <30>[ 15.971314] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
787 19:43:59.192002 <30>[ 16.008044] systemd[1]: Detected architecture arm.
788 19:43:59.205154
789 19:43:59.205460 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
790 19:43:59.205671
791 19:43:59.227610 <30>[ 16.041520] systemd[1]: Hostname set to <debian-bookworm-armhf>.
792 19:44:01.412283 <30>[ 18.225198] systemd[1]: Queued start job for default target graphical.target.
793 19:44:01.429181 <30>[ 18.239951] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
794 19:44:01.436281 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
795 19:44:01.467552 <30>[ 18.277780] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
796 19:44:01.474400 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
797 19:44:01.502725 <30>[ 18.314666] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
798 19:44:01.513074 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
799 19:44:01.545095 <30>[ 18.355665] systemd[1]: Created slice user.slice - User and Session Slice.
800 19:44:01.551827 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
801 19:44:01.577555 <30>[ 18.383134] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
802 19:44:01.583760 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
803 19:44:01.601734 <30>[ 18.413043] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
804 19:44:01.611726 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
805 19:44:01.642377 <30>[ 18.442945] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
806 19:44:01.648857 <30>[ 18.463453] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
807 19:44:01.657418 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
808 19:44:01.680590 <30>[ 18.492308] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
809 19:44:01.688870 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
810 19:44:01.711390 <30>[ 18.522790] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
811 19:44:01.719829 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
812 19:44:01.741232 <30>[ 18.552846] systemd[1]: Reached target paths.target - Path Units.
813 19:44:01.746289 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
814 19:44:01.770936 <30>[ 18.582544] systemd[1]: Reached target remote-fs.target - Remote File Systems.
815 19:44:01.778282 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
816 19:44:01.800774 <30>[ 18.612435] systemd[1]: Reached target slices.target - Slice Units.
817 19:44:01.806238 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
818 19:44:01.830988 <30>[ 18.642642] systemd[1]: Reached target swap.target - Swaps.
819 19:44:01.835061 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
820 19:44:01.862137 <30>[ 18.673921] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
821 19:44:01.874643 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
822 19:44:01.902077 <30>[ 18.713483] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
823 19:44:01.910326 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
824 19:44:01.996445 <30>[ 18.803060] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
825 19:44:02.009173 <30>[ 18.820522] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
826 19:44:02.017552 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
827 19:44:02.043449 <30>[ 18.856411] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
828 19:44:02.055700 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
829 19:44:02.082170 <30>[ 18.894667] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
830 19:44:02.092878 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
831 19:44:02.127739 <30>[ 18.939749] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
832 19:44:02.141033 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
833 19:44:02.162875 <30>[ 18.973820] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
834 19:44:02.170320 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
835 19:44:02.198291 <30>[ 19.003597] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
836 19:44:02.214847 <30>[ 19.020250] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
837 19:44:02.265337 <30>[ 19.077653] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
838 19:44:02.291297 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
839 19:44:02.342135 <30>[ 19.155313] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
840 19:44:02.363457 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
841 19:44:02.433167 <30>[ 19.245440] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
842 19:44:02.459662 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
843 19:44:02.511304 <30>[ 19.323180] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
844 19:44:02.541165 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
845 19:44:02.592891 <30>[ 19.405145] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
846 19:44:02.619759 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
847 19:44:02.671444 <30>[ 19.484177] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
848 19:44:02.695746 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
849 19:44:02.741716 <30>[ 19.553226] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
850 19:44:02.760286 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
851 19:44:02.811171 <30>[ 19.623788] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
852 19:44:02.831198 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
853 19:44:02.880742 <30>[ 19.693286] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
854 19:44:02.909593 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
855 19:44:02.937932 <28>[ 19.744248] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
856 19:44:02.946455 <28>[ 19.758085] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
857 19:44:02.990270 <30>[ 19.803250] systemd[1]: Starting systemd-journald.service - Journal Service...
858 19:44:03.001833 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
859 19:44:03.083273 <30>[ 19.895614] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
860 19:44:03.100634 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
861 19:44:03.134890 <30>[ 19.947355] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
862 19:44:03.179742 Starting [0;1;39msystemd-network-g… units from Kernel command line...
863 19:44:03.243607 <30>[ 20.054638] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
864 19:44:03.300065 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
865 19:44:03.373393 <30>[ 20.185183] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
866 19:44:03.430815 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
867 19:44:03.522132 <30>[ 20.334841] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
868 19:44:03.569598 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
869 19:44:03.593084 <30>[ 20.405623] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
870 19:44:03.631390 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
871 19:44:03.656321 <30>[ 20.467786] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
872 19:44:03.684311 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
873 19:44:03.843118 <30>[ 20.656373] systemd[1]: modprobe@configfs.service: Deactivated successfully.
874 19:44:03.881695 <30>[ 20.693771] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
875 19:44:03.909780 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
876 19:44:03.931303 <30>[ 20.744691] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
877 19:44:03.961307 <30>[ 20.773767] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
878 19:44:03.980760 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
879 19:44:04.001788 <30>[ 20.813603] systemd[1]: Started systemd-journald.service - Journal Service.
880 19:44:04.008640 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
881 19:44:04.041211 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
882 19:44:04.072459 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
883 19:44:04.096567 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
884 19:44:04.132822 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
885 19:44:04.160990 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
886 19:44:04.183274 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
887 19:44:04.211128 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
888 19:44:04.235331 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
889 19:44:04.300226 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
890 19:44:04.371607 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
891 19:44:04.441523 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
892 19:44:04.524958 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
893 19:44:04.593248 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
894 19:44:04.711297 <46>[ 21.523844] systemd-journald[163]: Received client request to flush runtime journal.
895 19:44:04.751942 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
896 19:44:04.920753 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
897 19:44:05.703366 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
898 19:44:06.050379 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
899 19:44:06.112951 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
900 19:44:06.423942 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
901 19:44:06.673862 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
902 19:44:06.714043 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
903 19:44:06.741773 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
904 19:44:06.810997 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
905 19:44:06.853738 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
906 19:44:07.848717 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
907 19:44:07.922742 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
908 19:44:08.040826 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
909 19:44:08.140826 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
910 19:44:08.220527 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
911 19:44:10.211657 [[0m[0;31m* [0m] (1 of 5) Job systemd-networkd.service/start running (8s / 1min 36s)
912 19:44:10.414372 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
913 19:44:10.814334 [K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
914 19:44:11.131914 <5>[ 27.944408] cfg80211: Loading compiled-in X.509 certificates for regulatory database
915 19:44:11.857536 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
916 19:44:12.610385 <5>[ 29.425547] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
917 19:44:12.649860 <5>[ 29.463975] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
918 19:44:12.669950 <4>[ 29.482428] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
919 19:44:12.675250 <6>[ 29.491405] cfg80211: failed to load regulatory.db
920 19:44:13.288568 <46>[ 30.091444] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
921 19:44:13.370419 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
922 19:44:13.406681 <46>[ 30.212316] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
923 19:44:13.614599 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
924 19:44:22.302804 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
925 19:44:22.331289 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
926 19:44:22.352917 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
927 19:44:22.372028 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
928 19:44:22.432305 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
929 19:44:22.482299 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
930 19:44:22.521784 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
931 19:44:22.582627 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
932 19:44:22.654236 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
933 19:44:22.672899 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
934 19:44:22.707287 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
935 19:44:22.735540 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
936 19:44:22.777743 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
937 19:44:22.809171 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
938 19:44:22.843863 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
939 19:44:22.871434 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
940 19:44:22.902309 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
941 19:44:22.955636 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
942 19:44:22.981695 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
943 19:44:23.006367 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
944 19:44:23.042630 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
945 19:44:23.059839 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
946 19:44:23.083360 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
947 19:44:23.159258 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
948 19:44:23.208310 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
949 19:44:23.314831 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
950 19:44:23.391564 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
951 19:44:23.474589 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
952 19:44:23.524249 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
953 19:44:23.558685 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
954 19:44:23.753142 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
955 19:44:23.800969 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
956 19:44:23.870389 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
957 19:44:23.893051 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
958 19:44:23.922395 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
959 19:44:24.150600 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
960 19:44:24.482942 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
961 19:44:24.535365 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
962 19:44:24.564616 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
963 19:44:24.640802 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
964 19:44:24.912105 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
965 19:44:25.047706
966 19:44:25.050620 Debian GNU/Linux 12 worm-armhf login: root (automatic login)
967 19:44:25.051160
968 19:44:25.368214 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Thu Nov 7 18:55:34 UTC 2024 armv7l
969 19:44:25.368863
970 19:44:25.373448 The programs included with the Debian GNU/Linux system are free software;
971 19:44:25.378874 the exact distribution terms for each program are described in the
972 19:44:25.384527 individual files in /usr/share/doc/*/copyright.
973 19:44:25.385075
974 19:44:25.391570 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
975 19:44:25.392079 permitted by applicable law.
976 19:44:30.134462 Unable to match end of the kernel message
978 19:44:30.135934 Setting prompt string to ['/ #']
979 19:44:30.136576 end: 2.4.4.1 login-action (duration 00:00:47) [common]
981 19:44:30.138161 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
982 19:44:30.138800 start: 2.4.5 expect-shell-connection (timeout 00:03:13) [common]
983 19:44:30.139321 Setting prompt string to ['/ #']
984 19:44:30.139820 Forcing a shell prompt, looking for ['/ #']
986 19:44:30.190858 / #
987 19:44:30.191636 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
988 19:44:30.191918 Waiting using forced prompt support (timeout 00:02:30)
989 19:44:30.195702
990 19:44:30.204944 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
991 19:44:30.205596 start: 2.4.6 export-device-env (timeout 00:03:12) [common]
992 19:44:30.206220 Sending with 10 millisecond of delay
994 19:44:35.203430 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/954958/extract-nfsrootfs-cmbtkxxg'
995 19:44:35.214407 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/954958/extract-nfsrootfs-cmbtkxxg'
996 19:44:35.216741 Sending with 10 millisecond of delay
998 19:44:37.314911 / # export NFS_SERVER_IP='192.168.6.3'
999 19:44:37.325877 export NFS_SERVER_IP='192.168.6.3'
1000 19:44:37.327108 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1001 19:44:37.327757 end: 2.4 uboot-commands (duration 00:01:55) [common]
1002 19:44:37.328408 end: 2 uboot-action (duration 00:01:55) [common]
1003 19:44:37.329043 start: 3 lava-test-retry (timeout 00:06:54) [common]
1004 19:44:37.329679 start: 3.1 lava-test-shell (timeout 00:06:54) [common]
1005 19:44:37.330230 Using namespace: common
1007 19:44:37.431489 / # #
1008 19:44:37.432196 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1009 19:44:37.436969 #
1010 19:44:37.443467 Using /lava-954958
1012 19:44:37.544687 / # export SHELL=/bin/bash
1013 19:44:37.549042 export SHELL=/bin/bash
1015 19:44:37.657230 / # . /lava-954958/environment
1016 19:44:37.662330 . /lava-954958/environment
1018 19:44:37.776328 / # /lava-954958/bin/lava-test-runner /lava-954958/0
1019 19:44:37.776954 Test shell timeout: 10s (minimum of the action and connection timeout)
1020 19:44:37.781134 /lava-954958/bin/lava-test-runner /lava-954958/0
1021 19:44:38.177169 + export TESTRUN_ID=0_timesync-off
1022 19:44:38.184994 + TESTRUN_ID=0_timesync-off
1023 19:44:38.185442 + cd /lava-954958/0/tests/0_timesync-off
1024 19:44:38.185909 ++ cat uuid
1025 19:44:38.202142 + UUID=954958_1.6.2.4.1
1026 19:44:38.202629 + set +x
1027 19:44:38.210715 <LAVA_SIGNAL_STARTRUN 0_timesync-off 954958_1.6.2.4.1>
1028 19:44:38.211192 + systemctl stop systemd-timesyncd
1029 19:44:38.211925 Received signal: <STARTRUN> 0_timesync-off 954958_1.6.2.4.1
1030 19:44:38.212409 Starting test lava.0_timesync-off (954958_1.6.2.4.1)
1031 19:44:38.212980 Skipping test definition patterns.
1032 19:44:38.560278 + set +x
1033 19:44:38.560869 <LAVA_SIGNAL_ENDRUN 0_timesync-off 954958_1.6.2.4.1>
1034 19:44:38.561600 Received signal: <ENDRUN> 0_timesync-off 954958_1.6.2.4.1
1035 19:44:38.562181 Ending use of test pattern.
1036 19:44:38.562610 Ending test lava.0_timesync-off (954958_1.6.2.4.1), duration 0.35
1038 19:44:38.730665 + export TESTRUN_ID=1_kselftest-dt
1039 19:44:38.738619 + TESTRUN_ID=1_kselftest-dt
1040 19:44:38.739102 + cd /lava-954958/0/tests/1_kselftest-dt
1041 19:44:38.739558 ++ cat uuid
1042 19:44:38.755814 + UUID=954958_1.6.2.4.5
1043 19:44:38.756288 + set +x
1044 19:44:38.761438 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 954958_1.6.2.4.5>
1045 19:44:38.761950 + cd ./automated/linux/kselftest/
1046 19:44:38.762657 Received signal: <STARTRUN> 1_kselftest-dt 954958_1.6.2.4.5
1047 19:44:38.763122 Starting test lava.1_kselftest-dt (954958_1.6.2.4.5)
1048 19:44:38.763648 Skipping test definition patterns.
1049 19:44:38.788889 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1050 19:44:38.903994 INFO: install_deps skipped
1051 19:44:39.519994 --2024-11-07 19:44:39-- http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1052 19:44:39.544360 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1053 19:44:39.689548 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1054 19:44:39.833446 HTTP request sent, awaiting response... 200 OK
1055 19:44:39.833980 Length: 2541784 (2.4M) [application/octet-stream]
1056 19:44:39.839138 Saving to: 'kselftest_armhf.tar.gz'
1057 19:44:39.839611
1058 19:44:41.174953
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 44.73K 159KB/s
kselftest_armhf.tar 8%[> ] 208.82K 358KB/s
kselftest_armhf.tar 33%[=====> ] 822.39K 828KB/s
kselftest_armhf.tar 50%[=========> ] 1.21M 1.01MB/s
kselftest_armhf.tar 100%[===================>] 2.42M 1.82MB/s in 1.3s
1059 19:44:41.175630
1060 19:44:41.582947 2024-11-07 19:44:41 (1.82 MB/s) - 'kselftest_armhf.tar.gz' saved [2541784/2541784]
1061 19:44:41.583615
1062 19:44:54.890554 skiplist:
1063 19:44:54.891275 ========================================
1064 19:44:54.895079 ========================================
1065 19:44:55.018597 dt:test_unprobed_devices.sh
1066 19:44:55.054388 ============== Tests to run ===============
1067 19:44:55.063293 dt:test_unprobed_devices.sh
1068 19:44:55.066240 ===========End Tests to run ===============
1069 19:44:55.076378 shardfile-dt pass
1070 19:44:55.310593 <12>[ 72.128901] kselftest: Running tests in dt
1071 19:44:55.341257 TAP version 13
1072 19:44:55.366288 1..1
1073 19:44:55.422778 # timeout set to 45
1074 19:44:55.423501 # selftests: dt: test_unprobed_devices.sh
1075 19:44:56.259109 # TAP version 13
1076 19:45:21.953540 # 1..257
1077 19:45:22.129095 # ok 1 / # SKIP
1078 19:45:22.151550 # ok 2 /clk_mcasp0
1079 19:45:22.228566 # ok 3 /clk_mcasp0_fixed # SKIP
1080 19:45:22.301285 # ok 4 /cpus/cpu@0 # SKIP
1081 19:45:22.371141 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1082 19:45:22.392142 # ok 6 /fixedregulator0
1083 19:45:22.412436 # ok 7 /leds
1084 19:45:22.439252 # ok 8 /ocp
1085 19:45:22.462568 # ok 9 /ocp/interconnect@44c00000
1086 19:45:22.484082 # ok 10 /ocp/interconnect@44c00000/segment@0
1087 19:45:22.508235 # ok 11 /ocp/interconnect@44c00000/segment@100000
1088 19:45:22.533290 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1089 19:45:22.611367 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1090 19:45:22.632356 # ok 14 /ocp/interconnect@44c00000/segment@200000
1091 19:45:22.654857 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1092 19:45:22.762652 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1093 19:45:22.842496 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1094 19:45:22.916556 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1095 19:45:22.987999 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1096 19:45:23.064745 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1097 19:45:23.137871 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1098 19:45:23.210470 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1099 19:45:23.282666 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1100 19:45:23.356580 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1101 19:45:23.432031 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1102 19:45:23.504220 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1103 19:45:23.579360 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1104 19:45:23.654097 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1105 19:45:23.730087 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1106 19:45:23.800243 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1107 19:45:23.875999 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1108 19:45:23.953644 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1109 19:45:24.028261 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1110 19:45:24.101357 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1111 19:45:24.173053 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1112 19:45:24.246203 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1113 19:45:24.320948 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1114 19:45:24.395528 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1115 19:45:24.469943 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1116 19:45:24.544709 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1117 19:45:24.624941 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1118 19:45:24.695069 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1119 19:45:24.771843 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1120 19:45:24.844869 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1121 19:45:24.919343 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1122 19:45:24.992815 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1123 19:45:25.068512 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1124 19:45:25.143055 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1125 19:45:25.217664 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1126 19:45:25.292718 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1127 19:45:25.367256 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1128 19:45:25.445775 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1129 19:45:25.523472 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1130 19:45:25.598842 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1131 19:45:25.670035 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1132 19:45:25.743549 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1133 19:45:25.819832 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1134 19:45:25.893408 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1135 19:45:25.969902 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1136 19:45:26.046624 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1137 19:45:26.121926 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1138 19:45:26.196252 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1139 19:45:26.272083 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1140 19:45:26.347611 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1141 19:45:26.422691 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1142 19:45:26.497519 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1143 19:45:26.573543 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1144 19:45:26.648582 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1145 19:45:26.724128 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1146 19:45:26.807951 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1147 19:45:26.878596 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1148 19:45:26.965425 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1149 19:45:27.154872 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1150 19:45:27.277221 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1151 19:45:27.352528 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1152 19:45:27.426889 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1153 19:45:27.502132 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1154 19:45:27.574847 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1155 19:45:27.650065 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1156 19:45:27.724791 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1157 19:45:27.801307 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1158 19:45:27.875647 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1159 19:45:27.954231 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1160 19:45:28.027728 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1161 19:45:28.103307 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1162 19:45:28.174078 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1163 19:45:28.252092 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1164 19:45:28.327820 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1165 19:45:28.401887 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1166 19:45:28.475641 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1167 19:45:28.549523 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1168 19:45:28.624188 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1169 19:45:28.700334 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1170 19:45:28.775738 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1171 19:45:28.797314 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1172 19:45:28.821925 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1173 19:45:28.851417 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1174 19:45:28.871830 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1175 19:45:28.900314 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1176 19:45:28.921745 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1177 19:45:28.947792 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1178 19:45:28.969022 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1179 19:45:29.081840 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1180 19:45:29.107179 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1181 19:45:29.129905 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1182 19:45:29.154198 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1183 19:45:29.263696 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1184 19:45:29.341025 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1185 19:45:29.414910 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1186 19:45:29.496112 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1187 19:45:29.569704 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1188 19:45:29.642501 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1189 19:45:29.715887 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1190 19:45:29.791344 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1191 19:45:29.865762 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1192 19:45:29.941489 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1193 19:45:30.017364 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1194 19:45:30.091887 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1195 19:45:30.165979 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1196 19:45:30.248031 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1197 19:45:30.321023 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1198 19:45:30.393763 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1199 19:45:30.416721 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1200 19:45:30.490459 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1201 19:45:30.562246 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1202 19:45:30.641397 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1203 19:45:30.664674 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1204 19:45:30.736567 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1205 19:45:30.758488 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1206 19:45:30.831107 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1207 19:45:30.855417 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1208 19:45:30.884755 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1209 19:45:30.905527 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1210 19:45:30.928913 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1211 19:45:30.955359 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1212 19:45:30.978482 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1213 19:45:31.004928 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1214 19:45:31.082580 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1215 19:45:31.104670 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1216 19:45:31.129142 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1217 19:45:31.206956 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1218 19:45:31.283876 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1219 19:45:31.305606 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1220 19:45:31.407386 # not ok 144 /ocp/interconnect@47c00000
1221 19:45:31.484145 # not ok 145 /ocp/interconnect@47c00000/segment@0
1222 19:45:31.504685 # ok 146 /ocp/interconnect@48000000
1223 19:45:31.532746 # ok 147 /ocp/interconnect@48000000/segment@0
1224 19:45:31.553978 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1225 19:45:31.582688 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1226 19:45:31.605255 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1227 19:45:31.631016 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1228 19:45:31.655086 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1229 19:45:31.680077 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1230 19:45:31.704896 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1231 19:45:31.775386 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1232 19:45:31.854311 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1233 19:45:31.875304 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1234 19:45:31.898084 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1235 19:45:31.920877 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1236 19:45:31.951818 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1237 19:45:31.970290 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1238 19:45:31.995646 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1239 19:45:32.023083 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1240 19:45:32.045781 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1241 19:45:32.066104 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1242 19:45:32.091669 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1243 19:45:32.120921 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1244 19:45:32.140736 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1245 19:45:32.163552 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1246 19:45:32.189101 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1247 19:45:32.212404 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1248 19:45:32.238116 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1249 19:45:32.260765 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1250 19:45:32.289452 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1251 19:45:32.312376 # ok 175 /ocp/interconnect@48000000/segment@100000
1252 19:45:32.333887 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1253 19:45:32.363108 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1254 19:45:32.437687 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1255 19:45:32.511689 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1256 19:45:32.584309 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1257 19:45:32.664973 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1258 19:45:32.736942 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1259 19:45:32.811675 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1260 19:45:32.884225 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1261 19:45:32.965580 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1262 19:45:32.985293 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1263 19:45:33.006317 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1264 19:45:33.030402 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1265 19:45:33.053507 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1266 19:45:33.083013 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1267 19:45:33.105905 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1268 19:45:33.127654 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1269 19:45:33.152524 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1270 19:45:33.176160 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1271 19:45:33.200266 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1272 19:45:33.225297 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1273 19:45:33.249762 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1274 19:45:33.273616 # ok 198 /ocp/interconnect@48000000/segment@200000
1275 19:45:33.297080 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1276 19:45:33.376114 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1277 19:45:33.399934 # ok 201 /ocp/interconnect@48000000/segment@300000
1278 19:45:33.418935 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1279 19:45:33.444072 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1280 19:45:33.473865 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1281 19:45:33.495249 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1282 19:45:33.517707 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1283 19:45:33.541606 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1284 19:45:33.617126 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1285 19:45:33.636532 # ok 209 /ocp/interconnect@4a000000
1286 19:45:33.660777 # ok 210 /ocp/interconnect@4a000000/segment@0
1287 19:45:33.687153 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1288 19:45:33.715659 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1289 19:45:33.738252 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1290 19:45:33.761607 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1291 19:45:33.837049 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1292 19:45:33.952506 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1293 19:45:34.028029 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1294 19:45:34.135627 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1295 19:45:34.205985 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1296 19:45:34.283304 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1297 19:45:34.383173 # not ok 221 /ocp/interconnect@4b140000
1298 19:45:34.462392 # not ok 222 /ocp/interconnect@4b140000/segment@0
1299 19:45:34.533767 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1300 19:45:34.554159 # ok 224 /ocp/target-module@40300000
1301 19:45:34.581984 # ok 225 /ocp/target-module@40300000/sram@0
1302 19:45:34.654903 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1303 19:45:34.733129 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1304 19:45:34.752299 # ok 228 /ocp/target-module@47400000
1305 19:45:34.780076 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1306 19:45:34.798564 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1307 19:45:34.823373 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1308 19:45:34.845397 # ok 232 /ocp/target-module@47400000/usb@1400
1309 19:45:34.873046 # ok 233 /ocp/target-module@47400000/usb@1800
1310 19:45:34.892352 # ok 234 /ocp/target-module@47810000
1311 19:45:34.919008 # ok 235 /ocp/target-module@49000000
1312 19:45:34.942808 # ok 236 /ocp/target-module@49000000/dma@0
1313 19:45:34.960421 # ok 237 /ocp/target-module@49800000
1314 19:45:34.988748 # ok 238 /ocp/target-module@49800000/dma@0
1315 19:45:35.010921 # ok 239 /ocp/target-module@49900000
1316 19:45:35.030367 # ok 240 /ocp/target-module@49900000/dma@0
1317 19:45:35.052771 # ok 241 /ocp/target-module@49a00000
1318 19:45:35.081597 # ok 242 /ocp/target-module@49a00000/dma@0
1319 19:45:35.099928 # ok 243 /ocp/target-module@4c000000
1320 19:45:35.179671 # not ok 244 /ocp/target-module@4c000000/emif@0
1321 19:45:35.201626 # ok 245 /ocp/target-module@50000000
1322 19:45:35.220336 # ok 246 /ocp/target-module@53100000
1323 19:45:35.299762 # not ok 247 /ocp/target-module@53100000/sham@0
1324 19:45:35.317231 # ok 248 /ocp/target-module@53500000
1325 19:45:35.393234 # not ok 249 /ocp/target-module@53500000/aes@0
1326 19:45:35.419028 # ok 250 /ocp/target-module@56000000
1327 19:45:35.523513 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1328 19:45:35.599033 # ok 252 /opp-table # SKIP
1329 19:45:35.670952 # ok 253 /soc # SKIP
1330 19:45:35.690537 # ok 254 /sound
1331 19:45:35.719561 # ok 255 /target-module@4b000000
1332 19:45:35.743836 # ok 256 /target-module@4b000000/target-module@140000
1333 19:45:35.762130 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1334 19:45:35.773108 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1335 19:45:35.781067 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1336 19:45:38.127602 dt_test_unprobed_devices_sh_ skip
1337 19:45:38.134029 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1338 19:45:38.138716 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1339 19:45:38.139174 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1340 19:45:38.144142 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1341 19:45:38.149763 dt_test_unprobed_devices_sh_fixedregulator0 pass
1342 19:45:38.155335 dt_test_unprobed_devices_sh_leds pass
1343 19:45:38.155791 dt_test_unprobed_devices_sh_ocp pass
1344 19:45:38.160989 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1345 19:45:38.166526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1346 19:45:38.172170 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1347 19:45:38.183470 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1348 19:45:38.189009 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1349 19:45:38.194533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1350 19:45:38.205719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1351 19:45:38.211400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1352 19:45:38.222574 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1353 19:45:38.234028 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1354 19:45:38.245013 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1355 19:45:38.250673 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1356 19:45:38.261971 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1357 19:45:38.273161 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1358 19:45:38.284315 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1359 19:45:38.295480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1360 19:45:38.301054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1361 19:45:38.312211 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1362 19:45:38.323462 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1363 19:45:38.334600 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1364 19:45:38.345780 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1365 19:45:38.351588 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1366 19:45:38.362627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1367 19:45:38.373859 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1368 19:45:38.385166 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1369 19:45:38.390720 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1370 19:45:38.401894 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1371 19:45:38.413078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1372 19:45:38.424365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1373 19:45:38.435586 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1374 19:45:38.441257 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1375 19:45:38.452584 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1376 19:45:38.463661 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1377 19:45:38.475116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1378 19:45:38.486142 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1379 19:45:38.497267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1380 19:45:38.508467 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1381 19:45:38.519625 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1382 19:45:38.530854 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1383 19:45:38.542083 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1384 19:45:38.553198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1385 19:45:38.564423 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1386 19:45:38.575565 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1387 19:45:38.586793 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1388 19:45:38.598046 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1389 19:45:38.609183 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1390 19:45:38.620349 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1391 19:45:38.631562 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1392 19:45:38.642828 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1393 19:45:38.654111 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1394 19:45:38.665123 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1395 19:45:38.676427 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1396 19:45:38.687597 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1397 19:45:38.698868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1398 19:45:38.710052 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1399 19:45:38.721229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1400 19:45:38.726872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1401 19:45:38.738062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1402 19:45:38.749241 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1403 19:45:38.760440 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1404 19:45:38.771635 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1405 19:45:38.782819 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1406 19:45:38.794055 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1407 19:45:38.805214 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1408 19:45:38.816405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1409 19:45:38.827603 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1410 19:45:38.838796 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1411 19:45:38.850061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1412 19:45:38.861166 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1413 19:45:38.872350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1414 19:45:38.883537 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1415 19:45:38.894747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1416 19:45:38.905944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1417 19:45:38.917173 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1418 19:45:38.922780 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1419 19:45:38.933972 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1420 19:45:38.945233 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1421 19:45:38.956282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1422 19:45:38.967464 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1423 19:45:38.973093 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1424 19:45:38.989903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1425 19:45:39.001038 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1426 19:45:39.006685 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1427 19:45:39.023446 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1428 19:45:39.034742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1429 19:45:39.045837 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1430 19:45:39.051455 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1431 19:45:39.062597 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1432 19:45:39.073758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1433 19:45:39.079463 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1434 19:45:39.090535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1435 19:45:39.101993 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1436 19:45:39.107365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1437 19:45:39.118505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1438 19:45:39.124245 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1439 19:45:39.135318 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1440 19:45:39.146543 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1441 19:45:39.157711 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1442 19:45:39.168960 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1443 19:45:39.180220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1444 19:45:39.191306 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1445 19:45:39.202535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1446 19:45:39.213717 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1447 19:45:39.225011 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1448 19:45:39.236137 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1449 19:45:39.247218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1450 19:45:39.258492 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1451 19:45:39.275355 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1452 19:45:39.286441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1453 19:45:39.297647 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1454 19:45:39.308879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1455 19:45:39.320045 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1456 19:45:39.336788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1457 19:45:39.348031 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1458 19:45:39.359213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1459 19:45:39.370476 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1460 19:45:39.376008 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1461 19:45:39.387185 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1462 19:45:39.398397 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1463 19:45:39.403950 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1464 19:45:39.415138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1465 19:45:39.420792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1466 19:45:39.431947 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1467 19:45:39.437519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1468 19:45:39.448846 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1469 19:45:39.454330 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1470 19:45:39.465553 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1471 19:45:39.471196 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1472 19:45:39.482323 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1473 19:45:39.493587 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1474 19:45:39.504757 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1475 19:45:39.515975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1476 19:45:39.527177 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1477 19:45:39.532904 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1478 19:45:39.543886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1479 19:45:39.549503 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1480 19:45:39.555143 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1481 19:45:39.560652 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1482 19:45:39.566264 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1483 19:45:39.571850 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1484 19:45:39.583180 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1485 19:45:39.588811 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1486 19:45:39.594314 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1487 19:45:39.605505 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1488 19:45:39.611187 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1489 19:45:39.622287 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1490 19:45:39.627895 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1491 19:45:39.639130 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1492 19:45:39.644691 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1493 19:45:39.655900 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1494 19:45:39.661511 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1495 19:45:39.672723 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1496 19:45:39.678372 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1497 19:45:39.689535 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1498 19:45:39.695179 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1499 19:45:39.706372 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1500 19:45:39.712007 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1501 19:45:39.717585 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1502 19:45:39.728813 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1503 19:45:39.734373 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1504 19:45:39.745616 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1505 19:45:39.751279 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1506 19:45:39.762567 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1507 19:45:39.768097 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1508 19:45:39.779323 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1509 19:45:39.784894 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1510 19:45:39.790485 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1511 19:45:39.801967 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1512 19:45:39.807313 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1513 19:45:39.818520 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1514 19:45:39.829731 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1515 19:45:39.840924 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1516 19:45:39.852304 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1517 19:45:39.863388 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1518 19:45:39.874722 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1519 19:45:39.885744 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1520 19:45:39.896918 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1521 19:45:39.902627 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1522 19:45:39.913725 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1523 19:45:39.919356 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1524 19:45:39.930520 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1525 19:45:39.936154 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1526 19:45:39.947254 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1527 19:45:39.952883 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1528 19:45:39.964081 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1529 19:45:39.969666 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1530 19:45:39.980918 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1531 19:45:39.986609 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1532 19:45:39.997679 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1533 19:45:40.003271 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1534 19:45:40.014458 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1535 19:45:40.020089 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1536 19:45:40.025640 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1537 19:45:40.036844 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1538 19:45:40.043342 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1539 19:45:40.053642 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1540 19:45:40.059330 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1541 19:45:40.070503 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1542 19:45:40.076165 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1543 19:45:40.087337 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1544 19:45:40.092964 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1545 19:45:40.098469 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1546 19:45:40.104136 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1547 19:45:40.115469 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1548 19:45:40.126644 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1549 19:45:40.132311 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1550 19:45:40.137791 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1551 19:45:40.148983 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1552 19:45:40.160198 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1553 19:45:40.171403 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1554 19:45:40.182715 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1555 19:45:40.188360 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1556 19:45:40.193965 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1557 19:45:40.199547 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1558 19:45:40.205189 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1559 19:45:40.210733 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1560 19:45:40.216280 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1561 19:45:40.227451 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1562 19:45:40.233129 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1563 19:45:40.238583 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1564 19:45:40.244281 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1565 19:45:40.249972 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1566 19:45:40.260989 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1567 19:45:40.266685 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1568 19:45:40.272326 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1569 19:45:40.277832 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1570 19:45:40.283414 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1571 19:45:40.289001 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1572 19:45:40.294852 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1573 19:45:40.300237 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1574 19:45:40.305864 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1575 19:45:40.311435 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1576 19:45:40.316988 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1577 19:45:40.322802 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1578 19:45:40.328445 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1579 19:45:40.334078 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1580 19:45:40.339704 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1581 19:45:40.345269 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1582 19:45:40.350915 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1583 19:45:40.356549 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1584 19:45:40.362105 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1585 19:45:40.368220 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1586 19:45:40.373336 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1587 19:45:40.373975 dt_test_unprobed_devices_sh_opp-table skip
1588 19:45:40.379003 dt_test_unprobed_devices_sh_soc skip
1589 19:45:40.384533 dt_test_unprobed_devices_sh_sound pass
1590 19:45:40.390141 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1591 19:45:40.395606 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1592 19:45:40.401199 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1593 19:45:40.406979 dt_test_unprobed_devices_sh fail
1594 19:45:40.407554 + ../../utils/send-to-lava.sh ./output/result.txt
1595 19:45:40.414987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1596 19:45:40.415995 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1598 19:45:40.426074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1599 19:45:40.426872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1601 19:45:40.534382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1602 19:45:40.535282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1604 19:45:40.691604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1605 19:45:40.692186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1607 19:45:40.790142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1608 19:45:40.791020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1610 19:45:40.898676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1611 19:45:40.899305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1613 19:45:40.998883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1614 19:45:40.999746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1616 19:45:41.091749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1617 19:45:41.092606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1619 19:45:41.192888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1620 19:45:41.193775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1622 19:45:41.291504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1623 19:45:41.292365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1625 19:45:41.388604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1626 19:45:41.389468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1628 19:45:41.486071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1629 19:45:41.486990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1631 19:45:41.583286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1632 19:45:41.584171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1634 19:45:41.686038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1635 19:45:41.686938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1637 19:45:41.779039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1638 19:45:41.779903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1640 19:45:41.876203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1641 19:45:41.876832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1643 19:45:41.975807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1644 19:45:41.976447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1646 19:45:42.077855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1647 19:45:42.078503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1649 19:45:42.179437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1650 19:45:42.180064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1652 19:45:42.284817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1653 19:45:42.285482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1655 19:45:42.383671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1656 19:45:42.384356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1658 19:45:42.484178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1659 19:45:42.484807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1661 19:45:42.585179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1662 19:45:42.585792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1664 19:45:42.687093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1665 19:45:42.687721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1667 19:45:42.784078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1668 19:45:42.784696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1670 19:45:42.884930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1671 19:45:42.885557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1673 19:45:42.985252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1674 19:45:42.985882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1676 19:45:43.087894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1677 19:45:43.088519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1679 19:45:43.185426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1680 19:45:43.186066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1682 19:45:43.285887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1683 19:45:43.286519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1685 19:45:43.384302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1686 19:45:43.385216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1688 19:45:43.484432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1689 19:45:43.485601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1691 19:45:43.583906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1692 19:45:43.584902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1694 19:45:43.707686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1695 19:45:43.708769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1697 19:45:43.811939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1698 19:45:43.812678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1700 19:45:43.914717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1701 19:45:43.915677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1703 19:45:44.011125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1704 19:45:44.012086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1706 19:45:44.116611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1707 19:45:44.117654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1709 19:45:44.217308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1710 19:45:44.218039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1712 19:45:44.316342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1713 19:45:44.317019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1715 19:45:44.414251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1716 19:45:44.414901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1718 19:45:44.512966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1719 19:45:44.513646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1721 19:45:44.612968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1722 19:45:44.613623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1724 19:45:44.708586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1725 19:45:44.709275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1727 19:45:44.806353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1728 19:45:44.806992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1730 19:45:44.909104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1731 19:45:44.909736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1733 19:45:45.017920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1734 19:45:45.018581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1736 19:45:45.118543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1737 19:45:45.119196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1739 19:45:45.229280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1740 19:45:45.230651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1742 19:45:45.333000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1743 19:45:45.333647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1745 19:45:45.434155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1746 19:45:45.434807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1748 19:45:45.556877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1749 19:45:45.557935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1751 19:45:45.656496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1752 19:45:45.657155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1754 19:45:45.750483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1755 19:45:45.751295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1757 19:45:45.840479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1758 19:45:45.841304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1760 19:45:45.941057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1761 19:45:45.941922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1763 19:45:46.043358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1764 19:45:46.044327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1766 19:45:46.144564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1767 19:45:46.145222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1769 19:45:46.242569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1770 19:45:46.243410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1772 19:45:46.338415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1773 19:45:46.339269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1775 19:45:46.434596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1776 19:45:46.435449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1778 19:45:46.529464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1779 19:45:46.530345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1781 19:45:46.630210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1782 19:45:46.631076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1784 19:45:46.731879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1785 19:45:46.732726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1787 19:45:46.833598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1788 19:45:46.834471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1790 19:45:46.933326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1791 19:45:46.934282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1793 19:45:47.036115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1794 19:45:47.037040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1796 19:45:47.137247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1797 19:45:47.138225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1799 19:45:47.236440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1800 19:45:47.237321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1802 19:45:47.334050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1803 19:45:47.335052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1805 19:45:47.435972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1806 19:45:47.436802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1808 19:45:47.532862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1809 19:45:47.533697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1811 19:45:47.629982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1812 19:45:47.630812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1814 19:45:47.731924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1815 19:45:47.732749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1817 19:45:47.832573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1818 19:45:47.833406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1820 19:45:47.934149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1821 19:45:47.935005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1823 19:45:48.035503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1824 19:45:48.036361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1826 19:45:48.136587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1827 19:45:48.137433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1829 19:45:48.236699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1830 19:45:48.237539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1832 19:45:48.339148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1833 19:45:48.339993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1835 19:45:48.439192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1836 19:45:48.440004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1838 19:45:48.540416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1839 19:45:48.541680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1841 19:45:48.648211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1842 19:45:48.649382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1844 19:45:48.748349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1845 19:45:48.749560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1847 19:45:48.850347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1848 19:45:48.851489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1850 19:45:48.951068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1851 19:45:48.951916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1853 19:45:49.054578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1854 19:45:49.055756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1856 19:45:49.152744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1857 19:45:49.153972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1859 19:45:49.249001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1860 19:45:49.250243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1862 19:45:49.352979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1863 19:45:49.353923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1865 19:45:49.454436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1866 19:45:49.455350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1868 19:45:49.553389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1869 19:45:49.554363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1871 19:45:49.651239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1872 19:45:49.652176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1874 19:45:49.752025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1875 19:45:49.752679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1877 19:45:49.854124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1878 19:45:49.855038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1880 19:45:49.953315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1881 19:45:49.954257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1883 19:45:50.053029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1884 19:45:50.053944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1886 19:45:50.154070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1887 19:45:50.155095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1889 19:45:50.256176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1890 19:45:50.257225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1892 19:45:50.355024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1893 19:45:50.355932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1895 19:45:50.451423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1896 19:45:50.452436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1898 19:45:50.547743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1899 19:45:50.548750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1901 19:45:50.644839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1902 19:45:50.645769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1904 19:45:50.742431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1905 19:45:50.743782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1907 19:45:50.839722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1908 19:45:50.840600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1910 19:45:50.936116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1911 19:45:50.937014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1913 19:45:51.033165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1914 19:45:51.034110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1916 19:45:51.130520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1917 19:45:51.131447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1919 19:45:51.230401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1920 19:45:51.231287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1922 19:45:51.332745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1923 19:45:51.333641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1925 19:45:51.432685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1926 19:45:51.433614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1928 19:45:51.529428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1929 19:45:51.530377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1931 19:45:51.625465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1932 19:45:51.626416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1934 19:45:51.723719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1935 19:45:51.724632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1937 19:45:51.823801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1938 19:45:51.824688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1940 19:45:51.921049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1941 19:45:51.921934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1943 19:45:52.018914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1944 19:45:52.019806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1946 19:45:52.118224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1947 19:45:52.119133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1949 19:45:52.214483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1950 19:45:52.215364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1952 19:45:52.310142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1953 19:45:52.311036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1955 19:45:52.405233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1957 19:45:52.408565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1958 19:45:52.500591 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1960 19:45:52.503668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1961 19:45:52.595899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1963 19:45:52.599041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1964 19:45:52.693661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1965 19:45:52.694543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1967 19:45:52.794189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1968 19:45:52.795049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1970 19:45:52.889252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1971 19:45:52.890137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1973 19:45:52.986153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1974 19:45:52.987009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1976 19:45:53.081260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1977 19:45:53.082198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1979 19:45:53.178358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1980 19:45:53.179670 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1982 19:45:53.274902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1983 19:45:53.276279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1985 19:45:53.373461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1986 19:45:53.374421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1988 19:45:53.468233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1989 19:45:53.469154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1991 19:45:53.564321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1992 19:45:53.565392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1994 19:45:53.659816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1995 19:45:53.660737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1997 19:45:53.758556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1998 19:45:53.759567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2000 19:45:53.853853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2001 19:45:53.854819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2003 19:45:53.950440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2004 19:45:53.951285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2006 19:45:54.048875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2007 19:45:54.049986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2009 19:45:54.148090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2010 19:45:54.149178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2012 19:45:54.240397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2013 19:45:54.241263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2015 19:45:54.336042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2016 19:45:54.336907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2018 19:45:54.436226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2019 19:45:54.437134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2021 19:45:54.535550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2022 19:45:54.536441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2024 19:45:54.631274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2025 19:45:54.632084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2027 19:45:54.725452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2028 19:45:54.726307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2030 19:45:54.824243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2031 19:45:54.825042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2033 19:45:54.918979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2034 19:45:54.919784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2036 19:45:55.016235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2037 19:45:55.017075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2039 19:45:55.115819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2040 19:45:55.116425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2042 19:45:55.213923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2043 19:45:55.214737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2045 19:45:55.309514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2046 19:45:55.310363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2048 19:45:55.406133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2049 19:45:55.406985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2051 19:45:55.503418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2052 19:45:55.506054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2054 19:45:55.602844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2055 19:45:55.603663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2057 19:45:55.702590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2058 19:45:55.703327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2060 19:45:55.805746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2061 19:45:55.808325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2063 19:45:55.908380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2064 19:45:55.909201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2066 19:45:56.005461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2067 19:45:56.006655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2069 19:45:56.103254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2070 19:45:56.104504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2072 19:45:56.198018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2073 19:45:56.199355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2075 19:45:56.295631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2076 19:45:56.296922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2078 19:45:56.391686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2079 19:45:56.392944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2081 19:45:56.488434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2082 19:45:56.489752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2084 19:45:56.585559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2085 19:45:56.586555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2087 19:45:56.682369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2088 19:45:56.683174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2090 19:45:56.778857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2091 19:45:56.779639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2093 19:45:56.877987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2094 19:45:56.879213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2096 19:45:56.978616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2097 19:45:56.979737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2099 19:45:57.077804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2100 19:45:57.079119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2102 19:45:57.175515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2103 19:45:57.176119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2105 19:45:57.276329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2106 19:45:57.276916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2108 19:45:57.374586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2109 19:45:57.375205 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2111 19:45:57.472010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2112 19:45:57.472636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2114 19:45:57.568048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2115 19:45:57.568849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2117 19:45:57.665628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2118 19:45:57.666487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2120 19:45:57.765241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2121 19:45:57.766516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2123 19:45:57.865101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2124 19:45:57.865924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2126 19:45:57.960952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2127 19:45:57.961671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2129 19:45:58.059618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2130 19:45:58.060468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2132 19:45:58.156571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2133 19:45:58.157315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2135 19:45:58.255673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2136 19:45:58.256428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2138 19:45:58.356254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2139 19:45:58.357033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2141 19:45:58.453367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2142 19:45:58.454225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2144 19:45:58.550848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2145 19:45:58.551765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2147 19:45:58.646957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2148 19:45:58.647947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2150 19:45:58.745796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2151 19:45:58.746713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2153 19:45:58.839420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2154 19:45:58.840276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2156 19:45:58.935899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2157 19:45:58.936750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2159 19:45:59.032588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2160 19:45:59.033595 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2162 19:45:59.129027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2163 19:45:59.129963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2165 19:45:59.224586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2166 19:45:59.225518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2168 19:45:59.318968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2169 19:45:59.319823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2171 19:45:59.421319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2172 19:45:59.422602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2174 19:45:59.519121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2175 19:45:59.520587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2177 19:45:59.613882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2178 19:45:59.614990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2180 19:45:59.709873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2181 19:45:59.710711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2183 19:45:59.813685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2184 19:45:59.814584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2186 19:45:59.912694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2187 19:45:59.913542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2189 19:46:00.006698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2190 19:46:00.007554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2192 19:46:00.104250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2193 19:46:00.104886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2195 19:46:00.201161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2196 19:46:00.202126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2198 19:46:00.294985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2199 19:46:00.295939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2201 19:46:00.393370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2202 19:46:00.394867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2204 19:46:00.492589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2205 19:46:00.494269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2207 19:46:00.589452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2208 19:46:00.590097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2210 19:46:00.951138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2211 19:46:00.952600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2213 19:46:01.055460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2214 19:46:01.056484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2216 19:46:01.149597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2217 19:46:01.150492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2219 19:46:01.243895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2220 19:46:01.244729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2222 19:46:01.335013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2223 19:46:01.335933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2225 19:46:01.429230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2226 19:46:01.430111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2228 19:46:01.526815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2229 19:46:01.527616 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2231 19:46:01.623709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2232 19:46:01.624431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2234 19:46:01.720265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2235 19:46:01.721068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2237 19:46:01.814261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2238 19:46:01.815083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2240 19:46:01.905535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2241 19:46:01.906378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2243 19:46:02.003142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2244 19:46:02.003906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2246 19:46:02.101563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2247 19:46:02.102474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2249 19:46:02.196065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2250 19:46:02.196898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2252 19:46:02.291323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2253 19:46:02.292145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2255 19:46:02.387214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2256 19:46:02.388080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2258 19:46:02.480388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2259 19:46:02.481269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2261 19:46:02.575407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2262 19:46:02.576265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2264 19:46:02.673338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2265 19:46:02.674325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2267 19:46:02.768570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2268 19:46:02.769439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2270 19:46:02.867485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2271 19:46:02.868959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2273 19:46:02.964582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2274 19:46:02.965614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2276 19:46:03.058547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2278 19:46:03.061677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2279 19:46:03.153929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2280 19:46:03.154876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2282 19:46:03.252360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2283 19:46:03.253258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2285 19:46:03.346685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2286 19:46:03.347728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2288 19:46:03.442669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2289 19:46:03.443603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2291 19:46:03.538915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2292 19:46:03.539844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2294 19:46:03.635016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2295 19:46:03.635876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2297 19:46:03.729426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2298 19:46:03.730379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2300 19:46:03.825340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2301 19:46:03.826250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2303 19:46:03.921959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2304 19:46:03.922830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2306 19:46:04.016321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2307 19:46:04.017189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2309 19:46:04.112638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2310 19:46:04.113559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2312 19:46:04.205326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2313 19:46:04.206255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2315 19:46:04.301144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2316 19:46:04.302129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2318 19:46:04.398397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2319 19:46:04.399832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2321 19:46:04.491810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2322 19:46:04.492694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2324 19:46:04.578862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2325 19:46:04.579753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2327 19:46:04.674123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2328 19:46:04.675112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2330 19:46:04.770062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2331 19:46:04.771005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2333 19:46:04.866021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2334 19:46:04.866906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2336 19:46:04.962556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2337 19:46:04.963368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2339 19:46:05.056963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2340 19:46:05.057859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2342 19:46:05.152940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2343 19:46:05.153757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2345 19:46:05.248202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2346 19:46:05.249057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2348 19:46:05.346557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2349 19:46:05.347390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2351 19:46:05.440542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2352 19:46:05.441369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2354 19:46:05.533668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2355 19:46:05.534565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2357 19:46:05.631165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2358 19:46:05.631971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2360 19:46:05.729935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2361 19:46:05.730751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2363 19:46:05.831185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2364 19:46:05.831971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2366 19:46:05.927918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2367 19:46:05.928655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2369 19:46:06.033027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2370 19:46:06.033467 + set +x
2371 19:46:06.033947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2373 19:46:06.037177 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 954958_1.6.2.4.5>
2374 19:46:06.037734 Received signal: <ENDRUN> 1_kselftest-dt 954958_1.6.2.4.5
2375 19:46:06.038182 Ending use of test pattern.
2376 19:46:06.038634 Ending test lava.1_kselftest-dt (954958_1.6.2.4.5), duration 87.28
2378 19:46:06.049431 <LAVA_TEST_RUNNER EXIT>
2379 19:46:06.050353 ok: lava_test_shell seems to have completed
2380 19:46:06.064456 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2381 19:46:06.065933 end: 3.1 lava-test-shell (duration 00:01:29) [common]
2382 19:46:06.066323 end: 3 lava-test-retry (duration 00:01:29) [common]
2383 19:46:06.066830 start: 4 finalize (timeout 00:05:25) [common]
2384 19:46:06.067744 start: 4.1 power-off (timeout 00:00:30) [common]
2385 19:46:06.068986 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2386 19:46:06.109953 >> OK - accepted request
2387 19:46:06.111904 Returned 0 in 0 seconds
2388 19:46:06.212872 end: 4.1 power-off (duration 00:00:00) [common]
2390 19:46:06.214774 start: 4.2 read-feedback (timeout 00:05:25) [common]
2391 19:46:06.215998 Listened to connection for namespace 'common' for up to 1s
2392 19:46:06.216911 Listened to connection for namespace 'common' for up to 1s
2393 19:46:07.216735 Finalising connection for namespace 'common'
2394 19:46:07.217552 Disconnecting from shell: Finalise
2395 19:46:07.218225 / #
2396 19:46:07.319391 end: 4.2 read-feedback (duration 00:00:01) [common]
2397 19:46:07.320198 end: 4 finalize (duration 00:00:01) [common]
2398 19:46:07.320899 Cleaning after the job
2399 19:46:07.321545 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954958/tftp-deploy-lgfupg_3/ramdisk
2400 19:46:07.331931 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954958/tftp-deploy-lgfupg_3/kernel
2401 19:46:07.333995 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954958/tftp-deploy-lgfupg_3/dtb
2402 19:46:07.335153 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954958/tftp-deploy-lgfupg_3/nfsrootfs
2403 19:46:07.425531 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/954958/tftp-deploy-lgfupg_3/modules
2404 19:46:07.436002 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/954958
2405 19:46:10.436687 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/954958
2406 19:46:10.437245 Job finished correctly