Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 19:41:13.070859 lava-dispatcher, installed at version: 2023.08
2 19:41:13.071156 start: 0 validate
3 19:41:13.071344 Start time: 2024-11-07 19:41:13.071333+00:00 (UTC)
4 19:41:13.071567 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 19:41:13.568112 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/kernel/zImage exists
6 19:41:13.682629 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb exists
7 19:41:13.796775 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 19:41:13.911192 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/modules.tar.xz exists
9 19:41:14.030318 validate duration: 0.96
11 19:41:14.031097 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 19:41:14.031431 start: 1.1 download-retry (timeout 00:10:00) [common]
13 19:41:14.031744 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 19:41:14.032203 Not decompressing ramdisk as can be used compressed.
15 19:41:14.032500 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 19:41:14.032755 saving as /var/lib/lava/dispatcher/tmp/1218799/tftp-deploy-8iavx6z_/ramdisk/initrd.cpio.gz
17 19:41:14.033004 total size: 4775763 (4 MB)
18 19:41:14.259993 progress 0 % (0 MB)
19 19:41:14.605950 progress 5 % (0 MB)
20 19:41:14.716639 progress 10 % (0 MB)
21 19:41:14.969637 progress 15 % (0 MB)
22 19:41:14.975086 progress 20 % (0 MB)
23 19:41:14.979741 progress 25 % (1 MB)
24 19:41:14.982341 progress 30 % (1 MB)
25 19:41:15.067402 progress 35 % (1 MB)
26 19:41:15.087381 progress 40 % (1 MB)
27 19:41:15.287148 progress 45 % (2 MB)
28 19:41:15.291913 progress 50 % (2 MB)
29 19:41:15.309982 progress 55 % (2 MB)
30 19:41:15.407948 progress 60 % (2 MB)
31 19:41:15.500954 progress 65 % (2 MB)
32 19:41:15.535085 progress 70 % (3 MB)
33 19:41:15.633081 progress 75 % (3 MB)
34 19:41:15.725528 progress 80 % (3 MB)
35 19:41:15.755464 progress 85 % (3 MB)
36 19:41:15.854589 progress 90 % (4 MB)
37 19:41:15.937747 progress 95 % (4 MB)
38 19:41:15.979139 progress 100 % (4 MB)
39 19:41:15.979919 4 MB downloaded in 1.95 s (2.34 MB/s)
40 19:41:15.980403 end: 1.1.1 http-download (duration 00:00:02) [common]
42 19:41:15.981300 end: 1.1 download-retry (duration 00:00:02) [common]
43 19:41:15.981600 start: 1.2 download-retry (timeout 00:09:58) [common]
44 19:41:15.981887 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 19:41:15.982297 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/kernel/zImage
46 19:41:15.982526 saving as /var/lib/lava/dispatcher/tmp/1218799/tftp-deploy-8iavx6z_/kernel/zImage
47 19:41:15.982744 total size: 12050944 (11 MB)
48 19:41:15.982965 No compression specified
49 19:41:16.102662 progress 0 % (0 MB)
50 19:41:16.440563 progress 5 % (0 MB)
51 19:41:16.670496 progress 10 % (1 MB)
52 19:41:17.018678 progress 15 % (1 MB)
53 19:41:17.598573 progress 20 % (2 MB)
54 19:41:18.364108 progress 25 % (2 MB)
55 19:41:19.843169 progress 30 % (3 MB)
56 19:41:21.279345 progress 35 % (4 MB)
57 19:41:22.533549 progress 40 % (4 MB)
58 19:41:23.613451 progress 45 % (5 MB)
59 19:41:24.544109 progress 50 % (5 MB)
60 19:41:25.439930 progress 55 % (6 MB)
61 19:41:26.113452 progress 60 % (6 MB)
62 19:41:26.673929 progress 65 % (7 MB)
63 19:41:27.121870 progress 70 % (8 MB)
64 19:41:27.545279 progress 75 % (8 MB)
65 19:41:27.895839 progress 80 % (9 MB)
66 19:41:28.211353 progress 85 % (9 MB)
67 19:41:28.458414 progress 90 % (10 MB)
68 19:41:28.692186 progress 95 % (10 MB)
69 19:41:28.916698 progress 100 % (11 MB)
70 19:41:28.917554 11 MB downloaded in 12.93 s (0.89 MB/s)
71 19:41:28.918014 end: 1.2.1 http-download (duration 00:00:13) [common]
73 19:41:28.918846 end: 1.2 download-retry (duration 00:00:13) [common]
74 19:41:28.919149 start: 1.3 download-retry (timeout 00:09:45) [common]
75 19:41:28.919437 start: 1.3.1 http-download (timeout 00:09:45) [common]
76 19:41:28.919847 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
77 19:41:28.920079 saving as /var/lib/lava/dispatcher/tmp/1218799/tftp-deploy-8iavx6z_/dtb/am335x-boneblack.dtb
78 19:41:28.920297 total size: 70568 (0 MB)
79 19:41:28.920515 No compression specified
80 19:41:29.036770 progress 46 % (0 MB)
81 19:41:29.039584 progress 92 % (0 MB)
82 19:41:29.040569 progress 100 % (0 MB)
83 19:41:29.040986 0 MB downloaded in 0.12 s (0.56 MB/s)
84 19:41:29.041394 end: 1.3.1 http-download (duration 00:00:00) [common]
86 19:41:29.042198 end: 1.3 download-retry (duration 00:00:00) [common]
87 19:41:29.042485 start: 1.4 download-retry (timeout 00:09:45) [common]
88 19:41:29.042772 start: 1.4.1 http-download (timeout 00:09:45) [common]
89 19:41:29.043133 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 19:41:29.043364 saving as /var/lib/lava/dispatcher/tmp/1218799/tftp-deploy-8iavx6z_/nfsrootfs/full.rootfs.tar
91 19:41:29.043582 total size: 117747780 (112 MB)
92 19:41:29.043807 Using unxz to decompress xz
93 19:41:29.160569 progress 0 % (0 MB)
94 19:41:31.742004 progress 5 % (5 MB)
95 19:41:33.874849 progress 10 % (11 MB)
96 19:41:35.995673 progress 15 % (16 MB)
97 19:41:38.093398 progress 20 % (22 MB)
98 19:41:39.914732 progress 25 % (28 MB)
99 19:41:41.481922 progress 30 % (33 MB)
100 19:41:42.754522 progress 35 % (39 MB)
101 19:41:43.779987 progress 40 % (44 MB)
102 19:41:44.626400 progress 45 % (50 MB)
103 19:41:45.378091 progress 50 % (56 MB)
104 19:41:46.015934 progress 55 % (61 MB)
105 19:41:46.589402 progress 60 % (67 MB)
106 19:41:47.109331 progress 65 % (73 MB)
107 19:41:47.716434 progress 70 % (78 MB)
108 19:41:48.257838 progress 75 % (84 MB)
109 19:41:48.837048 progress 80 % (89 MB)
110 19:41:49.393321 progress 85 % (95 MB)
111 19:41:49.927139 progress 90 % (101 MB)
112 19:41:50.439991 progress 95 % (106 MB)
113 19:41:50.944702 progress 100 % (112 MB)
114 19:41:50.948177 112 MB downloaded in 21.90 s (5.13 MB/s)
115 19:41:50.948512 end: 1.4.1 http-download (duration 00:00:22) [common]
117 19:41:50.949136 end: 1.4 download-retry (duration 00:00:22) [common]
118 19:41:50.949349 start: 1.5 download-retry (timeout 00:09:23) [common]
119 19:41:50.949558 start: 1.5.1 http-download (timeout 00:09:23) [common]
120 19:41:50.949864 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/modules.tar.xz
121 19:41:50.950033 saving as /var/lib/lava/dispatcher/tmp/1218799/tftp-deploy-8iavx6z_/modules/modules.tar
122 19:41:50.950192 total size: 6916396 (6 MB)
123 19:41:50.950354 Using unxz to decompress xz
124 19:41:51.066605 progress 0 % (0 MB)
125 19:41:51.302155 progress 5 % (0 MB)
126 19:41:51.417807 progress 10 % (0 MB)
127 19:41:51.627583 progress 15 % (1 MB)
128 19:41:51.653586 progress 20 % (1 MB)
129 19:41:51.679366 progress 25 % (1 MB)
130 19:41:51.851137 progress 30 % (2 MB)
131 19:41:51.878733 progress 35 % (2 MB)
132 19:41:51.905394 progress 40 % (2 MB)
133 19:41:51.929197 progress 45 % (2 MB)
134 19:41:51.981110 progress 50 % (3 MB)
135 19:41:52.011742 progress 55 % (3 MB)
136 19:41:52.097978 progress 60 % (3 MB)
137 19:41:52.126083 progress 65 % (4 MB)
138 19:41:52.212625 progress 70 % (4 MB)
139 19:41:52.243254 progress 75 % (4 MB)
140 19:41:52.325279 progress 80 % (5 MB)
141 19:41:52.355998 progress 85 % (5 MB)
142 19:41:52.437300 progress 90 % (5 MB)
143 19:41:52.516801 progress 95 % (6 MB)
144 19:41:52.549136 progress 100 % (6 MB)
145 19:41:52.553821 6 MB downloaded in 1.60 s (4.11 MB/s)
146 19:41:52.554123 end: 1.5.1 http-download (duration 00:00:02) [common]
148 19:41:52.554651 end: 1.5 download-retry (duration 00:00:02) [common]
149 19:41:52.554839 start: 1.6 prepare-tftp-overlay (timeout 00:09:21) [common]
150 19:41:52.555026 start: 1.6.1 extract-nfsrootfs (timeout 00:09:21) [common]
151 19:41:58.068998 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1218799/extract-nfsrootfs-wxhtks97
152 19:41:58.069298 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 19:41:58.069449 start: 1.6.2 lava-overlay (timeout 00:09:16) [common]
154 19:41:58.069747 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm
155 19:41:58.069936 makedir: /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin
156 19:41:58.070080 makedir: /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/tests
157 19:41:58.070234 makedir: /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/results
158 19:41:58.070395 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-add-keys
159 19:41:58.070618 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-add-sources
160 19:41:58.070801 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-background-process-start
161 19:41:58.070990 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-background-process-stop
162 19:41:58.071195 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-common-functions
163 19:41:58.071387 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-echo-ipv4
164 19:41:58.071571 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-install-packages
165 19:41:58.071754 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-installed-packages
166 19:41:58.071928 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-os-build
167 19:41:58.072102 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-probe-channel
168 19:41:58.072276 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-probe-ip
169 19:41:58.072452 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-target-ip
170 19:41:58.072624 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-target-mac
171 19:41:58.073050 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-target-storage
172 19:41:58.073228 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-test-case
173 19:41:58.073403 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-test-event
174 19:41:58.073576 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-test-feedback
175 19:41:58.073747 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-test-raise
176 19:41:58.073919 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-test-reference
177 19:41:58.074091 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-test-runner
178 19:41:58.074263 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-test-set
179 19:41:58.074436 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-test-shell
180 19:41:58.074611 Updating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-add-keys (debian)
181 19:41:58.074837 Updating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-add-sources (debian)
182 19:41:58.075032 Updating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-install-packages (debian)
183 19:41:58.075226 Updating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-installed-packages (debian)
184 19:41:58.075420 Updating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/bin/lava-os-build (debian)
185 19:41:58.075591 Creating /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/environment
186 19:41:58.075723 LAVA metadata
187 19:41:58.075826 - LAVA_JOB_ID=1218799
188 19:41:58.075924 - LAVA_DISPATCHER_IP=192.168.11.5
189 19:41:58.076070 start: 1.6.2.1 ssh-authorize (timeout 00:09:16) [common]
190 19:41:58.076401 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 19:41:58.076528 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:16) [common]
192 19:41:58.076623 skipped lava-vland-overlay
193 19:41:58.076754 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 19:41:58.076882 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:16) [common]
195 19:41:58.076981 skipped lava-multinode-overlay
196 19:41:58.077095 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 19:41:58.077213 start: 1.6.2.4 test-definition (timeout 00:09:16) [common]
198 19:41:58.077316 Loading test definitions
199 19:41:58.077440 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:16) [common]
200 19:41:58.077541 Using /lava-1218799 at stage 0
201 19:41:58.077945 uuid=1218799_1.6.2.4.1 testdef=None
202 19:41:58.078069 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 19:41:58.078189 start: 1.6.2.4.2 test-overlay (timeout 00:09:16) [common]
204 19:41:58.078810 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 19:41:58.079146 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:16) [common]
207 19:41:58.079932 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 19:41:58.080299 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:16) [common]
210 19:41:58.081109 runner path: /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/0/tests/0_timesync-off test_uuid 1218799_1.6.2.4.1
211 19:41:58.081329 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 19:41:58.081692 start: 1.6.2.4.5 git-repo-action (timeout 00:09:16) [common]
214 19:41:58.081797 Using /lava-1218799 at stage 0
215 19:41:58.081938 Fetching tests from https://github.com/kernelci/test-definitions.git
216 19:41:58.082044 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/0/tests/1_kselftest-dt'
217 19:42:02.966797 Running '/usr/bin/git checkout kernelci.org
218 19:42:03.259711 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 19:42:03.260648 uuid=1218799_1.6.2.4.5 testdef=None
220 19:42:03.260907 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 19:42:03.261440 start: 1.6.2.4.6 test-overlay (timeout 00:09:11) [common]
223 19:42:03.263177 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 19:42:03.263737 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:11) [common]
226 19:42:03.303642 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 19:42:03.304349 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:11) [common]
229 19:42:03.369901 runner path: /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/0/tests/1_kselftest-dt test_uuid 1218799_1.6.2.4.5
230 19:42:03.370219 BOARD='beaglebone-black'
231 19:42:03.370446 BRANCH='mainline'
232 19:42:03.370673 SKIPFILE='/dev/null'
233 19:42:03.370897 SKIP_INSTALL='True'
234 19:42:03.371117 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
235 19:42:03.371314 TST_CASENAME=''
236 19:42:03.371517 TST_CMDFILES='dt'
237 19:42:03.372036 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 19:42:03.372842 Creating lava-test-runner.conf files
240 19:42:03.373078 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1218799/lava-overlay-bjepvuxm/lava-1218799/0 for stage 0
241 19:42:03.389895 - 0_timesync-off
242 19:42:03.390189 - 1_kselftest-dt
243 19:42:03.390569 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 19:42:03.390885 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
245 19:42:11.907877 end: 1.6.2.5 compress-overlay (duration 00:00:09) [common]
246 19:42:11.908078 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:02) [common]
247 19:42:11.908224 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 19:42:11.908371 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
249 19:42:11.908500 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:02) [common]
250 19:42:12.033594 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 19:42:12.033887 start: 1.6.4 extract-modules (timeout 00:09:02) [common]
252 19:42:12.034049 extracting modules file /var/lib/lava/dispatcher/tmp/1218799/tftp-deploy-8iavx6z_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1218799/extract-nfsrootfs-wxhtks97
253 19:42:12.338463 extracting modules file /var/lib/lava/dispatcher/tmp/1218799/tftp-deploy-8iavx6z_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1218799/extract-overlay-ramdisk-zce0sv8n/ramdisk
254 19:42:12.652010 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 19:42:12.652229 start: 1.6.5 apply-overlay-tftp (timeout 00:09:01) [common]
256 19:42:12.652363 [common] Applying overlay to NFS
257 19:42:12.652463 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1218799/compress-overlay-ny4lsl4y/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1218799/extract-nfsrootfs-wxhtks97
258 19:42:13.835504 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 19:42:13.835718 start: 1.6.6 prepare-kernel (timeout 00:09:00) [common]
260 19:42:13.835845 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:00) [common]
261 19:42:13.835974 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 19:42:13.836092 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 19:42:13.836211 start: 1.6.7 configure-preseed-file (timeout 00:09:00) [common]
264 19:42:13.836326 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 19:42:13.836442 start: 1.6.8 compress-ramdisk (timeout 00:09:00) [common]
266 19:42:13.836543 Building ramdisk /var/lib/lava/dispatcher/tmp/1218799/extract-overlay-ramdisk-zce0sv8n/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1218799/extract-overlay-ramdisk-zce0sv8n/ramdisk
267 19:42:14.154413 >> 79012 blocks
268 19:42:16.287785 Adding RAMdisk u-boot header.
269 19:42:16.288059 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1218799/extract-overlay-ramdisk-zce0sv8n/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1218799/extract-overlay-ramdisk-zce0sv8n/ramdisk.cpio.gz.uboot
270 19:42:16.442331 output: Image Name:
271 19:42:16.442692 output: Created: Thu Nov 7 19:42:16 2024
272 19:42:16.442928 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 19:42:16.443153 output: Data Size: 15350164 Bytes = 14990.39 KiB = 14.64 MiB
274 19:42:16.443371 output: Load Address: 00000000
275 19:42:16.443581 output: Entry Point: 00000000
276 19:42:16.443793 output:
277 19:42:16.444128 rename /var/lib/lava/dispatcher/tmp/1218799/extract-overlay-ramdisk-zce0sv8n/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1218799/tftp-deploy-8iavx6z_/ramdisk/ramdisk.cpio.gz.uboot
278 19:42:16.444479 end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
279 19:42:16.444800 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
280 19:42:16.445092 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:58) [common]
281 19:42:16.445318 No LXC device requested
282 19:42:16.445587 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 19:42:16.445863 start: 1.8 deploy-device-env (timeout 00:08:58) [common]
284 19:42:16.446131 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 19:42:16.446346 Checking files for TFTP limit of 4294967296 bytes.
286 19:42:16.447632 end: 1 tftp-deploy (duration 00:01:02) [common]
287 19:42:16.447931 start: 2 uboot-action (timeout 00:05:00) [common]
288 19:42:16.448218 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 19:42:16.448492 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 19:42:16.448806 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 19:42:16.449215 substitutions:
292 19:42:16.449438 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 19:42:16.449658 - {DTB_ADDR}: 0x88000000
294 19:42:16.449873 - {DTB}: 1218799/tftp-deploy-8iavx6z_/dtb/am335x-boneblack.dtb
295 19:42:16.450088 - {INITRD}: 1218799/tftp-deploy-8iavx6z_/ramdisk/ramdisk.cpio.gz.uboot
296 19:42:16.450300 - {KERNEL_ADDR}: 0x82000000
297 19:42:16.450509 - {KERNEL}: 1218799/tftp-deploy-8iavx6z_/kernel/zImage
298 19:42:16.450717 - {LAVA_MAC}: None
299 19:42:16.450936 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1218799/extract-nfsrootfs-wxhtks97
300 19:42:16.451145 - {NFS_SERVER_IP}: 192.168.11.5
301 19:42:16.451350 - {PRESEED_CONFIG}: None
302 19:42:16.451553 - {PRESEED_LOCAL}: None
303 19:42:16.451755 - {RAMDISK_ADDR}: 0x83000000
304 19:42:16.451958 - {RAMDISK}: 1218799/tftp-deploy-8iavx6z_/ramdisk/ramdisk.cpio.gz.uboot
305 19:42:16.452162 - {ROOT_PART}: None
306 19:42:16.452365 - {ROOT}: None
307 19:42:16.452565 - {SERVER_IP}: 192.168.11.5
308 19:42:16.452803 - {TEE_ADDR}: 0x83000000
309 19:42:16.453006 - {TEE}: None
310 19:42:16.453208 Parsed boot commands:
311 19:42:16.453405 - setenv autoload no
312 19:42:16.453606 - setenv initrd_high 0xffffffff
313 19:42:16.453803 - setenv fdt_high 0xffffffff
314 19:42:16.454000 - dhcp
315 19:42:16.454196 - setenv serverip 192.168.11.5
316 19:42:16.454395 - tftp 0x82000000 1218799/tftp-deploy-8iavx6z_/kernel/zImage
317 19:42:16.454595 - tftp 0x83000000 1218799/tftp-deploy-8iavx6z_/ramdisk/ramdisk.cpio.gz.uboot
318 19:42:16.454795 - setenv initrd_size ${filesize}
319 19:42:16.454994 - tftp 0x88000000 1218799/tftp-deploy-8iavx6z_/dtb/am335x-boneblack.dtb
320 19:42:16.455193 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1218799/extract-nfsrootfs-wxhtks97,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 19:42:16.455400 - bootz 0x82000000 0x83000000 0x88000000
322 19:42:16.455658 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 19:42:16.456392 start: 2.3 connect-device (timeout 00:05:00) [common]
325 19:42:16.456605 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 19:42:16.817058 Setting prompt string to ['lava-test: # ']
327 19:42:16.817470 end: 2.3 connect-device (duration 00:00:00) [common]
328 19:42:16.817634 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 19:42:16.817818 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 19:42:16.817967 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 19:42:16.818291 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 19:42:17.182837 Returned 0 in 0 seconds
333 19:42:17.283708 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 19:42:17.284608 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 19:42:17.284947 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 19:42:17.285227 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 19:42:17.285475 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 19:42:17.286223 Trying 127.0.0.1...
340 19:42:17.286455 Connected to 127.0.0.1.
341 19:42:17.286668 Escape character is '^]'.
342 19:42:22.201029
343 19:42:22.204824 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 19:42:22.261329 Trying to boot from MMC2
345 19:42:22.309734 Loading Environment from EXT4... Card did not respond to voltage select!
346 19:42:22.377338
347 19:42:22.377639
348 19:42:22.382915 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 19:42:22.383173
350 19:42:22.387815 CPU : AM335X-GP rev 2.1
351 19:42:22.442004 I2C: ready
352 19:42:22.442349 DRAM: 512 MiB
353 19:42:22.496300 No match for driver 'omap_hsmmc'
354 19:42:22.501894 No match for driver 'omap_hsmmc'
355 19:42:22.502160 Some drivers were not found
356 19:42:22.508168 Reset Source: Power-on reset has occurred.
357 19:42:22.508426 RTC 32KCLK Source: External.
358 19:42:22.515692 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 19:42:22.528992 Loading Environment from EXT4... Card did not respond to voltage select!
360 19:42:22.593551 Board: BeagleBone Black
361 19:42:22.597355 <ethaddr> not set. Validating first E-fuse MAC
362 19:42:22.654066 BeagleBone Black:
363 19:42:22.654381 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 19:42:22.659658 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 19:42:22.665689 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 19:42:22.665949 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 19:42:22.670647 Net: eth0: MII MODE
368 19:42:22.679999 cpsw, usb_ether
369 19:42:22.680275 Press SPACE to abort autoboot in 2 seconds
370 19:42:22.731103 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 19:42:22.731472 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 19:42:22.731779 Setting prompt string to ['=> ']
373 19:42:22.732045 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 19:42:22.735293 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 19:42:22.735600 Sending with 10 millisecond of delay
377 19:42:23.870179 => setenv autoload no
378 19:42:23.880662 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 19:42:23.883030 setenv autoload no
380 19:42:23.883501 Sending with 10 millisecond of delay
382 19:42:25.680404 => setenv initrd_high 0xffffffff
383 19:42:25.690938 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 19:42:25.691413 setenv initrd_high 0xffffffff
385 19:42:25.691863 Sending with 10 millisecond of delay
387 19:42:27.308220 => setenv fdt_high 0xffffffff
388 19:42:27.318735 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 19:42:27.319192 setenv fdt_high 0xffffffff
390 19:42:27.319638 Sending with 10 millisecond of delay
392 19:42:27.611119 => dhcp
393 19:42:27.621579 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 19:42:27.622039 dhcp
395 19:42:27.622273 link up on port 0, speed 100, full duplex
396 19:42:27.622500 BOOTP broadcast 1
397 19:42:27.630796 DHCP client bound to address 192.168.11.3 (4 ms)
398 19:42:27.631300 Sending with 10 millisecond of delay
400 19:42:29.367963 => setenv serverip 192.168.11.5
401 19:42:29.378495 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 19:42:29.378975 setenv serverip 192.168.11.5
403 19:42:29.379429 Sending with 10 millisecond of delay
405 19:42:32.922391 => tftp 0x82000000 1218799/tftp-deploy-8iavx6z_/kernel/zImage
406 19:42:32.932878 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 19:42:32.933340 tftp 0x82000000 1218799/tftp-deploy-8iavx6z_/kernel/zImage
408 19:42:32.933573 link up on port 0, speed 100, full duplex
409 19:42:32.933790 Using cpsw device
410 19:42:32.937316 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
411 19:42:32.942808 Filename '1218799/tftp-deploy-8iavx6z_/kernel/zImage'.
412 19:42:33.042997 Load address: 0x82000000
413 19:42:33.131439 Loading: *#################################################################
414 19:42:33.306545 #################################################################
415 19:42:33.577035 #################################################################
416 19:42:33.665788 #################################################################
417 19:42:33.838388 #################################################################
418 19:42:34.010499 #################################################################
419 19:42:34.199762 #################################################################
420 19:42:34.356463 #################################################################
421 19:42:34.552456 #################################################################
422 19:42:34.727583 #################################################################
423 19:42:34.902683 #################################################################
424 19:42:35.075197 #################################################################
425 19:42:35.179325 #########################################
426 19:42:35.179614 5.2 MiB/s
427 19:42:35.179880 done
428 19:42:35.183020 Bytes transferred = 12050944 (b7e200 hex)
429 19:42:35.183500 Sending with 10 millisecond of delay
431 19:42:39.690288 => tftp 0x83000000 1218799/tftp-deploy-8iavx6z_/ramdisk/ramdisk.cpio.gz.uboot
432 19:42:39.700778 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
433 19:42:39.701248 tftp 0x83000000 1218799/tftp-deploy-8iavx6z_/ramdisk/ramdisk.cpio.gz.uboot
434 19:42:39.701481 link up on port 0, speed 100, full duplex
435 19:42:39.701699 Using cpsw device
436 19:42:39.705048 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
437 19:42:39.718983 Filename '1218799/tftp-deploy-8iavx6z_/ramdisk/ramdisk.cpio.gz.uboot'.
438 19:42:39.719285 Load address: 0x83000000
439 19:42:39.913459 Loading: *#################################################################
440 19:42:40.088570 #################################################################
441 19:42:40.263309 #################################################################
442 19:42:40.436048 #################################################################
443 19:42:40.599470 #################################################################
444 19:42:40.773115 #################################################################
445 19:42:40.990007 #################################################################
446 19:42:41.171617 #################################################################
447 19:42:41.282110 #################################################################
448 19:42:41.479815 #################################################################
449 19:42:41.655870 #################################################################
450 19:42:41.832745 #################################################################
451 19:42:42.016353 #################################################################
452 19:42:42.177656 #################################################################
453 19:42:42.354085 #################################################################
454 19:42:42.538353 #################################################################
455 19:42:42.549632 ######
456 19:42:42.549912 5.2 MiB/s
457 19:42:42.550138 done
458 19:42:42.553174 Bytes transferred = 15350228 (ea39d4 hex)
459 19:42:42.553716 Sending with 10 millisecond of delay
461 19:42:44.410902 => setenv initrd_size ${filesize}
462 19:42:44.421389 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
463 19:42:44.421854 setenv initrd_size ${filesize}
464 19:42:44.422308 Sending with 10 millisecond of delay
466 19:42:48.627866 => tftp 0x88000000 1218799/tftp-deploy-8iavx6z_/dtb/am335x-boneblack.dtb
467 19:42:48.638339 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
468 19:42:48.638861 tftp 0x88000000 1218799/tftp-deploy-8iavx6z_/dtb/am335x-boneblack.dtb
469 19:42:48.639129 link up on port 0, speed 100, full duplex
470 19:42:48.639390 Using cpsw device
471 19:42:48.642659 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
472 19:42:48.667667 Filename '1218799/tftp-deploy-8iavx6z_/dtb/am335x-boneblack.dtb'.
473 19:42:48.667987 Load address: 0x88000000
474 19:42:48.668254 Loading: *#####
475 19:42:48.668505 4.8 MiB/s
476 19:42:48.674349 done
477 19:42:48.674573 Bytes transferred = 70568 (113a8 hex)
478 19:42:48.674995 Sending with 10 millisecond of delay
480 19:43:01.974081 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1218799/extract-nfsrootfs-wxhtks97,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 19:43:01.984592 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:14)
482 19:43:01.985066 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1218799/extract-nfsrootfs-wxhtks97,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
483 19:43:01.985525 Sending with 10 millisecond of delay
485 19:43:04.324439 => bootz 0x82000000 0x83000000 0x88000000
486 19:43:04.334951 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
487 19:43:04.335284 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
488 19:43:04.335824 bootz 0x82000000 0x83000000 0x88000000
489 19:43:04.336068 ## Loading init Ramdisk from Legacy Image at 83000000 ...
490 19:43:04.336643 Image Name:
491 19:43:04.336900 Created: 2024-11-07 19:42:16 UTC
492 19:43:04.342156 Image Type: ARM Linux RAMDisk Image (uncompressed)
493 19:43:04.347751 Data Size: 15350164 Bytes = 14.6 MiB
494 19:43:04.348032 Load Address: 00000000
495 19:43:04.354936 Entry Point: 00000000
496 19:43:04.497448 Verifying Checksum ... OK
497 19:43:04.497728 ## Flattened Device Tree blob at 88000000
498 19:43:04.503932 Booting using the fdt blob at 0x88000000
499 19:43:04.508828 Using Device Tree in place at 88000000, end 880143a7
500 19:43:04.516326
501 19:43:04.516612 Starting kernel ...
502 19:43:04.516865
503 19:43:04.517418 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
504 19:43:04.517727 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
505 19:43:04.517989 Setting prompt string to ['Linux version [0-9]']
506 19:43:04.518238 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
507 19:43:04.518490 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
508 19:43:05.409923 [ 0.000000] Booting Linux on physical CPU 0x0
509 19:43:05.415941 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
510 19:43:05.416217 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 19:43:05.416475 Setting prompt string to []
512 19:43:05.416743 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 19:43:05.416997 Using line separator: #'\n'#
514 19:43:05.417216 No login prompt set.
515 19:43:05.417441 Parsing kernel messages
516 19:43:05.417648 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 19:43:05.418045 [login-action] Waiting for messages, (timeout 00:04:11)
518 19:43:05.427109 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j367068-arm-clang-15-multi-v7-defconfig-8xshf) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Thu Nov 7 18:55:34 UTC 2024
519 19:43:05.432725 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
520 19:43:05.444143 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
521 19:43:05.449892 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
522 19:43:05.455640 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
523 19:43:05.461390 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
524 19:43:05.468142 [ 0.000000] Memory policy: Data cache writeback
525 19:43:05.468422 [ 0.000000] efi: UEFI not found.
526 19:43:05.475808 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
527 19:43:05.481521 [ 0.000000] Zone ranges:
528 19:43:05.487267 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
529 19:43:05.493017 [ 0.000000] Normal empty
530 19:43:05.493294 [ 0.000000] HighMem empty
531 19:43:05.498637 [ 0.000000] Movable zone start for each node
532 19:43:05.498915 [ 0.000000] Early memory node ranges
533 19:43:05.510151 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
534 19:43:05.515506 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
535 19:43:05.533663 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 19:43:05.539322 [ 0.000000] AM335X ES2.1 (sgx neon)
537 19:43:05.551266 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
538 19:43:05.571771 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1218799/extract-nfsrootfs-wxhtks97,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 19:43:05.577521 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
540 19:43:05.589019 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
541 19:43:05.594768 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
542 19:43:05.602210 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
543 19:43:05.631521 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
544 19:43:05.637521 <6>[ 0.000000] trace event string verifier disabled
545 19:43:05.637801 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
546 19:43:05.643267 <6>[ 0.000000] rcu: RCU event tracing is enabled.
547 19:43:05.654769 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
548 19:43:05.660393 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
549 19:43:05.667693 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
550 19:43:05.682819 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
551 19:43:05.701146 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
552 19:43:05.707815 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
553 19:43:05.811388 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
554 19:43:05.822874 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
555 19:43:05.829665 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
556 19:43:05.842756 <6>[ 0.019242] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
557 19:43:05.850731 <6>[ 0.034602] Console: colour dummy device 80x30
558 19:43:05.856793 Matched prompt #6: WARNING:
559 19:43:05.857085 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
560 19:43:05.862088 <3>[ 0.039593] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
561 19:43:05.867834 <3>[ 0.046584] This ensures that you still see kernel messages. Please
562 19:43:05.871142 <3>[ 0.053309] update your kernel commandline.
563 19:43:05.911206 <6>[ 0.057923] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
564 19:43:05.917133 <6>[ 0.096248] CPU: Testing write buffer coherency: ok
565 19:43:05.922957 <6>[ 0.101618] CPU0: Spectre v2: using BPIALL workaround
566 19:43:05.923238 <6>[ 0.107082] pid_max: default: 32768 minimum: 301
567 19:43:05.934453 <6>[ 0.112283] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 19:43:05.941456 <6>[ 0.120110] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 19:43:05.948580 <6>[ 0.129564] CPU0: thread -1, cpu 0, socket -1, mpidr 0
570 19:43:05.957164 <6>[ 0.136549] Setting up static identity map for 0x80300000 - 0x803000ac
571 19:43:05.962957 <6>[ 0.146379] rcu: Hierarchical SRCU implementation.
572 19:43:05.970506 <6>[ 0.151664] rcu: Max phase no-delay instances is 1000.
573 19:43:05.979734 <6>[ 0.163347] EFI services will not be available.
574 19:43:05.985459 <6>[ 0.168644] smp: Bringing up secondary CPUs ...
575 19:43:05.991204 <6>[ 0.173706] smp: Brought up 1 node, 1 CPU
576 19:43:05.997125 <6>[ 0.178107] SMP: Total of 1 processors activated (996.14 BogoMIPS).
577 19:43:06.003080 <6>[ 0.184879] CPU: All CPU(s) started in SVC mode.
578 19:43:06.023265 <6>[ 0.190082] Memory: 404432K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50616K reserved, 65536K cma-reserved, 0K highmem)
579 19:43:06.023557 <6>[ 0.206371] devtmpfs: initialized
580 19:43:06.046450 <6>[ 0.224333] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
581 19:43:06.058075 <6>[ 0.232944] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
582 19:43:06.063876 <6>[ 0.243408] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
583 19:43:06.074644 <6>[ 0.255739] pinctrl core: initialized pinctrl subsystem
584 19:43:06.084506 <6>[ 0.266819] DMI not present or invalid.
585 19:43:06.092865 <6>[ 0.272715] NET: Registered PF_NETLINK/PF_ROUTE protocol family
586 19:43:06.102281 <6>[ 0.281725] DMA: preallocated 256 KiB pool for atomic coherent allocations
587 19:43:06.117748 <6>[ 0.293474] thermal_sys: Registered thermal governor 'step_wise'
588 19:43:06.118028 <6>[ 0.293670] cpuidle: using governor menu
589 19:43:06.145516 <6>[ 0.329346] No ATAGs?
590 19:43:06.151630 <6>[ 0.332090] hw-breakpoint: debug architecture 0x4 unsupported.
591 19:43:06.162145 <6>[ 0.344381] Serial: AMBA PL011 UART driver
592 19:43:06.192227 <6>[ 0.376069] iommu: Default domain type: Translated
593 19:43:06.201282 <6>[ 0.381421] iommu: DMA domain TLB invalidation policy: strict mode
594 19:43:06.227893 <5>[ 0.410557] SCSI subsystem initialized
595 19:43:06.241819 <6>[ 0.420161] usbcore: registered new interface driver usbfs
596 19:43:06.248835 <6>[ 0.426122] usbcore: registered new interface driver hub
597 19:43:06.249116 <6>[ 0.431958] usbcore: registered new device driver usb
598 19:43:06.254568 <6>[ 0.438512] pps_core: LinuxPPS API ver. 1 registered
599 19:43:06.266066 <6>[ 0.443950] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
600 19:43:06.274867 <6>[ 0.453668] PTP clock support registered
601 19:43:06.275146 <6>[ 0.458124] EDAC MC: Ver: 3.0.0
602 19:43:06.329756 <6>[ 0.510672] scmi_core: SCMI protocol bus registered
603 19:43:06.335135 <6>[ 0.518856] vgaarb: loaded
604 19:43:06.347586 <6>[ 0.531631] clocksource: Switched to clocksource dmtimer
605 19:43:06.375330 <6>[ 0.558961] NET: Registered PF_INET protocol family
606 19:43:06.388059 <6>[ 0.564692] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
607 19:43:06.393818 <6>[ 0.573689] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
608 19:43:06.405306 <6>[ 0.582613] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
609 19:43:06.411060 <6>[ 0.590857] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
610 19:43:06.422693 <6>[ 0.599141] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
611 19:43:06.428560 <6>[ 0.606861] TCP: Hash tables configured (established 4096 bind 4096)
612 19:43:06.434317 <6>[ 0.613779] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
613 19:43:06.440235 <6>[ 0.620792] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
614 19:43:06.447751 <6>[ 0.628402] NET: Registered PF_UNIX/PF_LOCAL protocol family
615 19:43:06.540690 <6>[ 0.719011] RPC: Registered named UNIX socket transport module.
616 19:43:06.541036 <6>[ 0.725456] RPC: Registered udp transport module.
617 19:43:06.546438 <6>[ 0.730566] RPC: Registered tcp transport module.
618 19:43:06.555201 <6>[ 0.735697] RPC: Registered tcp-with-tls transport module.
619 19:43:06.561065 <6>[ 0.741624] RPC: Registered tcp NFSv4.1 backchannel transport module.
620 19:43:06.568316 <6>[ 0.748534] PCI: CLS 0 bytes, default 64
621 19:43:06.570503 <5>[ 0.754419] Initialise system trusted keyrings
622 19:43:06.594577 <6>[ 0.775522] Trying to unpack rootfs image as initramfs...
623 19:43:06.654186 <6>[ 0.831928] workingset: timestamp_bits=30 max_order=17 bucket_order=0
624 19:43:06.658896 <6>[ 0.839431] squashfs: version 4.0 (2009/01/31) Phillip Lougher
625 19:43:06.698597 <5>[ 0.882556] NFS: Registering the id_resolver key type
626 19:43:06.704438 <5>[ 0.888158] Key type id_resolver registered
627 19:43:06.710183 <5>[ 0.892852] Key type id_legacy registered
628 19:43:06.716048 <6>[ 0.897290] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
629 19:43:06.725611 <6>[ 0.904506] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
630 19:43:06.811215 <5>[ 0.995180] Key type asymmetric registered
631 19:43:06.817087 <5>[ 0.999706] Asymmetric key parser 'x509' registered
632 19:43:06.828667 <6>[ 1.005245] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
633 19:43:06.828966 <6>[ 1.013202] io scheduler mq-deadline registered
634 19:43:06.834407 <6>[ 1.018135] io scheduler kyber registered
635 19:43:06.840152 <6>[ 1.022611] io scheduler bfq registered
636 19:43:06.961768 <6>[ 1.142061] ledtrig-cpu: registered to indicate activity on CPUs
637 19:43:07.223240 <6>[ 1.403343] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
638 19:43:07.261542 <6>[ 1.445301] msm_serial: driver initialized
639 19:43:07.267683 <6>[ 1.450117] SuperH (H)SCI(F) driver initialized
640 19:43:07.273528 <6>[ 1.455482] STMicroelectronics ASC driver initialized
641 19:43:07.278693 <6>[ 1.461104] STM32 USART driver initialized
642 19:43:07.406862 <6>[ 1.590169] brd: module loaded
643 19:43:07.462349 <6>[ 1.645598] loop: module loaded
644 19:43:07.504689 <6>[ 1.687681] CAN device driver interface
645 19:43:07.511300 <6>[ 1.692963] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
646 19:43:07.517036 <6>[ 1.699956] e1000e: Intel(R) PRO/1000 Network Driver
647 19:43:07.522902 <6>[ 1.705425] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
648 19:43:07.528619 <6>[ 1.711873] igb: Intel(R) Gigabit Ethernet Network Driver
649 19:43:07.536802 <6>[ 1.717695] igb: Copyright (c) 2007-2014 Intel Corporation.
650 19:43:07.548996 <6>[ 1.727186] pegasus: Pegasus/Pegasus II USB Ethernet driver
651 19:43:07.554661 <6>[ 1.733352] usbcore: registered new interface driver pegasus
652 19:43:07.560503 <6>[ 1.739480] usbcore: registered new interface driver asix
653 19:43:07.566281 <6>[ 1.745367] usbcore: registered new interface driver ax88179_178a
654 19:43:07.571998 <6>[ 1.751959] usbcore: registered new interface driver cdc_ether
655 19:43:07.577879 <6>[ 1.758259] usbcore: registered new interface driver smsc75xx
656 19:43:07.583625 <6>[ 1.764499] usbcore: registered new interface driver smsc95xx
657 19:43:07.589379 <6>[ 1.770720] usbcore: registered new interface driver net1080
658 19:43:07.595130 <6>[ 1.776866] usbcore: registered new interface driver cdc_subset
659 19:43:07.601019 <6>[ 1.783296] usbcore: registered new interface driver zaurus
660 19:43:07.608561 <6>[ 1.789339] usbcore: registered new interface driver cdc_ncm
661 19:43:07.618604 <6>[ 1.799004] usbcore: registered new interface driver usb-storage
662 19:43:07.628262 <6>[ 1.810326] i2c_dev: i2c /dev entries driver
663 19:43:07.653148 <5>[ 1.829175] cpuidle: enable-method property 'ti,am3352' found operations
664 19:43:07.659053 <6>[ 1.838715] sdhci: Secure Digital Host Controller Interface driver
665 19:43:07.666504 <6>[ 1.845474] sdhci: Copyright(c) Pierre Ossman
666 19:43:07.673651 <6>[ 1.852042] Synopsys Designware Multimedia Card Interface Driver
667 19:43:07.679186 <6>[ 1.859895] sdhci-pltfm: SDHCI platform and OF driver helper
668 19:43:07.693320 <6>[ 1.869851] usbcore: registered new interface driver usbhid
669 19:43:07.693601 <6>[ 1.875966] usbhid: USB HID core driver
670 19:43:07.706213 <6>[ 1.887648] NET: Registered PF_INET6 protocol family
671 19:43:08.169686 <6>[ 2.353673] Segment Routing with IPv6
672 19:43:08.175604 <6>[ 2.357823] In-situ OAM (IOAM) with IPv6
673 19:43:08.182359 <6>[ 2.362380] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
674 19:43:08.188107 <6>[ 2.369714] NET: Registered PF_PACKET protocol family
675 19:43:08.193979 <6>[ 2.375290] can: controller area network core
676 19:43:08.199765 <6>[ 2.380117] NET: Registered PF_CAN protocol family
677 19:43:08.200045 <6>[ 2.385352] can: raw protocol
678 19:43:08.205478 <6>[ 2.388681] can: broadcast manager protocol
679 19:43:08.211976 <6>[ 2.393292] can: netlink gateway - max_hops=1
680 19:43:08.218116 <5>[ 2.398786] Key type dns_resolver registered
681 19:43:08.224503 <6>[ 2.403858] ThumbEE CPU extension supported.
682 19:43:08.224797 <5>[ 2.408550] Registering SWP/SWPB emulation handler
683 19:43:08.234163 <3>[ 2.414263] omap_voltage_late_init: Voltage driver support not added
684 19:43:08.440705 <5>[ 2.622346] Loading compiled-in X.509 certificates
685 19:43:08.597213 <6>[ 2.768203] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
686 19:43:08.604404 <6>[ 2.784944] pinctrl-single 44e10800.pinmux: 142 pins, size 568
687 19:43:08.631406 <3>[ 2.809341] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
688 19:43:08.844877 <3>[ 3.022848] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
689 19:43:09.039774 <6>[ 3.222178] OMAP GPIO hardware version 0.1
690 19:43:09.061001 <6>[ 3.241321] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
691 19:43:09.133870 <4>[ 3.313949] at24 2-0054: supply vcc not found, using dummy regulator
692 19:43:09.167512 <4>[ 3.347570] at24 2-0055: supply vcc not found, using dummy regulator
693 19:43:09.207243 <4>[ 3.387370] at24 2-0056: supply vcc not found, using dummy regulator
694 19:43:09.246504 <4>[ 3.426564] at24 2-0057: supply vcc not found, using dummy regulator
695 19:43:09.283989 <6>[ 3.464836] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
696 19:43:09.342074 <3>[ 3.518754] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
697 19:43:09.366867 <6>[ 3.540046] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 19:43:09.389573 <4>[ 3.566942] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
699 19:43:09.397374 <4>[ 3.576160] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
700 19:43:09.491522 <6>[ 3.675382] Freeing initrd memory: 14992K
701 19:43:09.499787 <6>[ 3.680054] omap_rng 48310000.rng: Random Number Generator ver. 20
702 19:43:09.523963 <5>[ 3.706991] random: crng init done
703 19:43:09.572868 <6>[ 3.751628] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
704 19:43:09.626315 <6>[ 3.804088] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
705 19:43:09.632070 <6>[ 3.814429] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
706 19:43:09.643942 <6>[ 3.821771] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
707 19:43:09.649676 <6>[ 3.829247] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
708 19:43:09.661202 <6>[ 3.837384] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
709 19:43:09.668675 <6>[ 3.849022] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
710 19:43:09.681740 <5>[ 3.858130] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
711 19:43:09.710427 <3>[ 3.888764] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
712 19:43:09.716140 <6>[ 3.897362] edma 49000000.dma: TI EDMA DMA engine driver
713 19:43:09.789726 <3>[ 3.967469] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
714 19:43:09.805051 <6>[ 3.982432] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
715 19:43:09.818129 <3>[ 3.999584] l3-aon-clkctrl:0000:0: failed to disable
716 19:43:09.871911 <6>[ 4.050209] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
717 19:43:09.877650 <6>[ 4.059724] printk: legacy console [ttyS0] enabled
718 19:43:09.883253 <6>[ 4.059724] printk: legacy console [ttyS0] enabled
719 19:43:09.889039 <6>[ 4.070065] printk: legacy bootconsole [omap8250] disabled
720 19:43:09.894799 <6>[ 4.070065] printk: legacy bootconsole [omap8250] disabled
721 19:43:09.925186 <4>[ 4.102453] tps65217-pmic: Failed to locate of_node [id: -1]
722 19:43:09.928726 <4>[ 4.109860] tps65217-bl: Failed to locate of_node [id: -1]
723 19:43:09.945906 <6>[ 4.130264] tps65217 0-0024: TPS65217 ID 0xe version 1.2
724 19:43:09.964388 <6>[ 4.137283] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
725 19:43:09.976113 <6>[ 4.150977] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
726 19:43:09.981793 <6>[ 4.162873] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
727 19:43:10.004368 <6>[ 4.183091] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
728 19:43:10.010245 <6>[ 4.192262] sdhci-omap 48060000.mmc: Got CD GPIO
729 19:43:10.018296 <4>[ 4.197411] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
730 19:43:10.033275 <4>[ 4.211270] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
731 19:43:10.039771 <4>[ 4.219972] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
732 19:43:10.049596 <4>[ 4.228676] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
733 19:43:10.149288 <6>[ 4.328960] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
734 19:43:10.188646 <6>[ 4.367453] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
735 19:43:10.233942 <6>[ 4.411891] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
736 19:43:10.240612 <6>[ 4.420718] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
737 19:43:10.309500 <6>[ 4.483088] mmc1: new high speed MMC card at address 0001
738 19:43:10.309781 <6>[ 4.491558] mmcblk1: mmc1:0001 M62704 3.56 GiB
739 19:43:10.321072 <6>[ 4.502845] mmcblk1: p1
740 19:43:10.329242 <6>[ 4.508195] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
741 19:43:10.340940 <6>[ 4.515958] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
742 19:43:10.345487 <6>[ 4.527208] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
743 19:43:10.362727 <6>[ 4.543112] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
744 19:43:13.534306 <6>[ 7.712678] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
745 19:43:13.607605 <5>[ 7.751722] Sending DHCP requests ., OK
746 19:43:13.618918 <6>[ 7.796083] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.3
747 19:43:13.619193 <6>[ 7.804328] IP-Config: Complete:
748 19:43:13.630164 <6>[ 7.807867] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.3, mask=255.255.255.0, gw=192.168.11.1
749 19:43:13.635911 <6>[ 7.818467] host=192.168.11.3, domain=usen.ad.jp, nis-domain=(none)
750 19:43:13.648289 <6>[ 7.825554] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
751 19:43:13.648566 <6>[ 7.825589] nameserver0=192.168.11.1
752 19:43:13.654411 <6>[ 7.837904] clk: Disabling unused clocks
753 19:43:13.660968 <6>[ 7.842703] PM: genpd: Disabling unused power domains
754 19:43:13.679283 <6>[ 7.859863] Freeing unused kernel image (initmem) memory: 2048K
755 19:43:13.686604 <6>[ 7.869713] Run /init as init process
756 19:43:13.712618 Loading, please wait...
757 19:43:13.790868 Starting systemd-udevd version 252.22-1~deb12u1
758 19:43:16.911738 <4>[ 11.088894] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
759 19:43:17.045987 <4>[ 11.223165] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 19:43:17.165850 <6>[ 11.350516] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
761 19:43:17.176837 <6>[ 11.356346] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
762 19:43:17.419854 <6>[ 11.603073] hub 1-0:1.0: USB hub found
763 19:43:17.490008 <6>[ 11.672960] hub 1-0:1.0: 1 port detected
764 19:43:17.645499 <6>[ 11.828328] tda998x 0-0070: found TDA19988
765 19:43:20.340124 Begin: Loading essential drivers ... done.
766 19:43:20.345688 Begin: Running /scripts/init-premount ... done.
767 19:43:20.351293 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
768 19:43:20.359557 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
769 19:43:20.365119 Device /sys/class/net/eth0 found
770 19:43:20.365400 done.
771 19:43:20.442895 Begin: Waiting up to 180 secs for any network device to become available ... done.
772 19:43:20.532542 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
773 19:43:20.532860 IP-Config: eth0 guessed broadcast address 192.168.11.255
774 19:43:20.538192 IP-Config: eth0 complete (dhcp from 192.168.11.1):
775 19:43:20.549284 address: 192.168.11.3 broadcast: 192.168.11.255 netmask: 255.255.255.0
776 19:43:20.554967 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
777 19:43:20.560537 domain : usen.ad.jp
778 19:43:20.565491 rootserver: 192.168.11.1 rootpath:
779 19:43:20.565769 filename :
780 19:43:20.644818 done.
781 19:43:20.657320 Begin: Running /scripts/nfs-bottom ... done.
782 19:43:20.722334 Begin: Running /scripts/init-bottom ... done.
783 19:43:22.256627 <30>[ 16.437058] systemd[1]: System time before build time, advancing clock.
784 19:43:22.505289 <30>[ 16.659510] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 19:43:22.513958 <30>[ 16.696213] systemd[1]: Detected architecture arm.
786 19:43:22.526679
787 19:43:22.526963 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 19:43:22.527192
789 19:43:22.550398 <30>[ 16.731418] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 19:43:24.767279 <30>[ 18.947144] systemd[1]: Queued start job for default target graphical.target.
791 19:43:24.784530 <30>[ 18.962582] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 19:43:24.791945 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 19:43:24.817037 <30>[ 18.995092] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 19:43:24.825441 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 19:43:24.846898 <30>[ 19.025013] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 19:43:24.855194 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 19:43:24.875653 <30>[ 19.053851] systemd[1]: Created slice user.slice - User and Session Slice.
798 19:43:24.882440 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 19:43:24.910408 <30>[ 19.083015] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 19:43:24.916467 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 19:43:24.934631 <30>[ 19.112867] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 19:43:24.945594 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 19:43:24.975278 <30>[ 19.142648] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 19:43:24.981621 <30>[ 19.163183] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 19:43:24.990182 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 19:43:25.013658 <30>[ 19.192148] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 19:43:25.021833 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 19:43:25.044392 <30>[ 19.222550] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 19:43:25.052665 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 19:43:25.074056 <30>[ 19.252588] systemd[1]: Reached target paths.target - Path Units.
811 19:43:25.079056 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 19:43:25.103766 <30>[ 19.282304] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 19:43:25.111085 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 19:43:25.133751 <30>[ 19.312345] systemd[1]: Reached target slices.target - Slice Units.
815 19:43:25.139174 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 19:43:25.163803 <30>[ 19.342375] systemd[1]: Reached target swap.target - Swaps.
817 19:43:25.167817 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 19:43:25.194186 <30>[ 19.372435] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 19:43:25.202938 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 19:43:25.225158 <30>[ 19.403339] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 19:43:25.233447 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 19:43:25.317439 <30>[ 19.490929] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 19:43:25.330367 <30>[ 19.508486] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 19:43:25.338679 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 19:43:25.365716 <30>[ 19.543402] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 19:43:25.373098 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 19:43:25.397403 <30>[ 19.575459] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 19:43:25.405582 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 19:43:25.435637 <30>[ 19.613083] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 19:43:25.441242 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 19:43:25.465120 <30>[ 19.643366] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 19:43:25.473706 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 19:43:25.501364 <30>[ 19.673506] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 19:43:25.517830 <30>[ 19.690184] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 19:43:25.568031 <30>[ 19.747246] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 19:43:25.594262 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 19:43:25.621785 <30>[ 19.800911] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 19:43:25.646154 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 19:43:25.719201 <30>[ 19.897347] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 19:43:25.745454 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 19:43:25.795860 <30>[ 19.974594] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 19:43:25.824082 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 19:43:25.884065 <30>[ 20.063200] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 19:43:25.901062 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 19:43:25.963275 <30>[ 20.142947] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 19:43:25.979413 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 19:43:26.044460 <30>[ 20.222849] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 19:43:26.063664 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 19:43:26.093806 <30>[ 20.273269] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 19:43:26.113448 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 19:43:26.146659 <30>[ 20.326206] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 19:43:26.182677 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 19:43:26.210515 <28>[ 20.383955] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 19:43:26.218921 <28>[ 20.397638] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 19:43:26.264097 <30>[ 20.442743] systemd[1]: Starting systemd-journald.service - Journal Service...
856 19:43:26.270510 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 19:43:26.313907 <30>[ 20.493189] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 19:43:26.333420 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 19:43:26.364360 <30>[ 20.543811] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 19:43:26.416642 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 19:43:26.475440 <30>[ 20.653340] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 19:43:26.520047 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 19:43:26.604155 <30>[ 20.782843] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 19:43:26.656188 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 19:43:26.734451 <30>[ 20.914100] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 19:43:26.774332 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 19:43:26.785590 <30>[ 20.965124] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 19:43:26.825368 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 19:43:26.850490 <30>[ 21.028928] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 19:43:26.883760 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 19:43:27.046161 <30>[ 21.226262] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 19:43:27.084526 <30>[ 21.263595] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 19:43:27.113373 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 19:43:27.134105 <30>[ 21.314486] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
875 19:43:27.154027 <30>[ 21.333441] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
876 19:43:27.183555 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 19:43:27.194026 <30>[ 21.374644] systemd[1]: modprobe@drm.service: Deactivated successfully.
878 19:43:27.223810 <30>[ 21.403685] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
879 19:43:27.252440 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
880 19:43:27.283867 <30>[ 21.462508] systemd[1]: Started systemd-journald.service - Journal Service.
881 19:43:27.290648 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
882 19:43:27.329525 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
883 19:43:27.363523 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
884 19:43:27.397145 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
885 19:43:27.427148 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
886 19:43:27.446020 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
887 19:43:27.466277 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
888 19:43:27.493552 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
889 19:43:27.556804 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
890 19:43:27.605733 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
891 19:43:27.655404 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
892 19:43:27.735244 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
893 19:43:27.797583 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
894 19:43:27.956739 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
895 19:43:28.073658 <46>[ 22.253177] systemd-journald[162]: Received client request to flush runtime journal.
896 19:43:28.163499 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
897 19:43:28.224533 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
898 19:43:28.754748 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
899 19:43:28.821882 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
900 19:43:29.826827 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
901 19:43:29.926235 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
902 19:43:29.954505 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
903 19:43:29.973220 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
904 19:43:30.038390 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
905 19:43:30.086621 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
906 19:43:31.020870 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
907 19:43:31.093726 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
908 19:43:31.313643 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
909 19:43:31.405220 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
910 19:43:31.460323 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
911 19:43:33.217891 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
912 19:43:33.994357 <5>[ 28.174257] cfg80211: Loading compiled-in X.509 certificates for regulatory database
913 19:43:34.067503 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
914 19:43:35.238907 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
915 19:43:35.638656 <5>[ 29.820759] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
916 19:43:35.709558 <5>[ 29.890014] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
917 19:43:35.723342 <4>[ 29.903031] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
918 19:43:35.729166 <6>[ 29.912149] cfg80211: failed to load regulatory.db
919 19:43:36.309551 <46>[ 30.479376] systemd-journald[162]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
920 19:43:36.327017 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
921 19:43:36.489206 <46>[ 30.662171] systemd-journald[162]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
922 19:43:36.716205 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
923 19:43:46.902380 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
924 19:43:46.927727 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
925 19:43:46.955103 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
926 19:43:46.975624 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
927 19:43:47.033158 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
928 19:43:47.084021 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
929 19:43:47.147233 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
930 19:43:47.201773 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
931 19:43:47.260928 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
932 19:43:47.292396 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
933 19:43:47.319855 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
934 19:43:47.348619 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
935 19:43:47.390249 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
936 19:43:47.432281 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
937 19:43:47.482962 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
938 19:43:47.503604 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
939 19:43:47.533260 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
940 19:43:47.564634 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
941 19:43:47.588597 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
942 19:43:47.613371 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
943 19:43:47.644001 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
944 19:43:47.663613 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
945 19:43:47.685967 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
946 19:43:47.764603 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
947 19:43:47.853362 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
948 19:43:47.971617 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
949 19:43:48.036934 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
950 19:43:48.102912 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
951 19:43:48.118557 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
952 19:43:48.161062 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
953 19:43:48.373082 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
954 19:43:48.442533 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
955 19:43:48.515074 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
956 19:43:48.543236 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
957 19:43:48.573840 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
958 19:43:48.807314 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
959 19:43:49.120551 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
960 19:43:49.150320 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
961 19:43:49.179027 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
962 19:43:49.244877 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
963 19:43:49.420794 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
964 19:43:49.559243
965 19:43:49.563074 Debian GNU/Linux 12 debian-rm-armhf login: root (automatic login)
966 19:43:49.563354
967 19:43:49.922731 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Thu Nov 7 18:55:34 UTC 2024 armv7l
968 19:43:49.923078
969 19:43:49.928328 The programs included with the Debian GNU/Linux system are free software;
970 19:43:49.933850 the exact distribution terms for each program are described in the
971 19:43:49.939484 individual files in /usr/share/doc/*/copyright.
972 19:43:49.939763
973 19:43:49.947502 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
974 19:43:49.947782 permitted by applicable law.
975 19:43:54.570479 Unable to match end of the kernel message
977 19:43:54.571295 Setting prompt string to ['/ #']
978 19:43:54.571602 end: 2.4.4.1 login-action (duration 00:00:49) [common]
980 19:43:54.572301 end: 2.4.4 auto-login-action (duration 00:00:50) [common]
981 19:43:54.572598 start: 2.4.5 expect-shell-connection (timeout 00:03:22) [common]
982 19:43:54.572883 Setting prompt string to ['/ #']
983 19:43:54.573099 Forcing a shell prompt, looking for ['/ #']
985 19:43:54.623657 / #
986 19:43:54.624035 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
987 19:43:54.624291 Waiting using forced prompt support (timeout 00:02:30)
988 19:43:54.628609
989 19:43:54.637898 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
990 19:43:54.638235 start: 2.4.6 export-device-env (timeout 00:03:22) [common]
991 19:43:54.638495 Sending with 10 millisecond of delay
993 19:43:59.687269 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1218799/extract-nfsrootfs-wxhtks97'
994 19:43:59.697885 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1218799/extract-nfsrootfs-wxhtks97'
995 19:43:59.699233 Sending with 10 millisecond of delay
997 19:44:01.857545 / # export NFS_SERVER_IP='192.168.11.5'
998 19:44:01.868123 export NFS_SERVER_IP='192.168.11.5'
999 19:44:01.869306 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1000 19:44:01.869655 end: 2.4 uboot-commands (duration 00:01:45) [common]
1001 19:44:01.869983 end: 2 uboot-action (duration 00:01:45) [common]
1002 19:44:01.870305 start: 3 lava-test-retry (timeout 00:07:12) [common]
1003 19:44:01.870629 start: 3.1 lava-test-shell (timeout 00:07:12) [common]
1004 19:44:01.870890 Using namespace: common
1006 19:44:01.971623 / # #
1007 19:44:01.972012 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1008 19:44:01.976409 #
1009 19:44:01.982646 Using /lava-1218799
1011 19:44:02.083400 / # export SHELL=/bin/bash
1012 19:44:02.088241 export SHELL=/bin/bash
1014 19:44:02.195562 / # . /lava-1218799/environment
1015 19:44:02.200262 . /lava-1218799/environment
1017 19:44:02.314307 / # /lava-1218799/bin/lava-test-runner /lava-1218799/0
1018 19:44:02.314797 Test shell timeout: 10s (minimum of the action and connection timeout)
1019 19:44:02.319256 /lava-1218799/bin/lava-test-runner /lava-1218799/0
1020 19:44:02.723834 + export TESTRUN_ID=0_timesync-off
1021 19:44:02.731797 + TESTRUN_ID=0_timesync-off
1022 19:44:02.732057 + cd /lava-1218799/0/tests/0_timesync-off
1023 19:44:02.732292 ++ cat uuid
1024 19:44:02.749218 + UUID=1218799_1.6.2.4.1
1025 19:44:02.749459 + set +x
1026 19:44:02.754826 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1218799_1.6.2.4.1>
1027 19:44:02.755320 Received signal: <STARTRUN> 0_timesync-off 1218799_1.6.2.4.1
1028 19:44:02.755561 Starting test lava.0_timesync-off (1218799_1.6.2.4.1)
1029 19:44:02.755872 Skipping test definition patterns.
1030 19:44:02.758031 + systemctl stop systemd-timesyncd
1031 19:44:03.087001 + set +x
1032 19:44:03.087496 Received signal: <ENDRUN> 0_timesync-off 1218799_1.6.2.4.1
1033 19:44:03.087769 Ending use of test pattern.
1034 19:44:03.087993 Ending test lava.0_timesync-off (1218799_1.6.2.4.1), duration 0.33
1036 19:44:03.090127 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1218799_1.6.2.4.1>
1037 19:44:03.271242 + export TESTRUN_ID=1_kselftest-dt
1038 19:44:03.279255 + TESTRUN_ID=1_kselftest-dt
1039 19:44:03.279539 + cd /lava-1218799/0/tests/1_kselftest-dt
1040 19:44:03.279773 ++ cat uuid
1041 19:44:03.298262 + UUID=1218799_1.6.2.4.5
1042 19:44:03.298605 + set +x
1043 19:44:03.303689 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1218799_1.6.2.4.5>
1044 19:44:03.303938 + cd ./automated/linux/kselftest/
1045 19:44:03.304406 Received signal: <STARTRUN> 1_kselftest-dt 1218799_1.6.2.4.5
1046 19:44:03.304664 Starting test lava.1_kselftest-dt (1218799_1.6.2.4.5)
1047 19:44:03.304978 Skipping test definition patterns.
1048 19:44:03.332300 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1049 19:44:03.442790 INFO: install_deps skipped
1050 19:44:04.114057 --2024-11-07 19:44:04-- http://storage.kernelci.org/mainline/master/v6.12-rc6-114-g80fb25341631b/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1051 19:44:04.134296 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1052 19:44:04.248666 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1053 19:44:04.360373 HTTP request sent, awaiting response... 200 OK
1054 19:44:04.360745 Length: 2541784 (2.4M) [application/octet-stream]
1055 19:44:04.365948 Saving to: 'kselftest_armhf.tar.gz'
1056 19:44:04.366227
1057 19:44:05.513841 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 2%[ ] 49.92K 221KB/s kselftest_armhf.tar 7%[> ] 194.76K 436KB/s kselftest_armhf.tar 26%[====> ] 647.57K 798KB/s kselftest_armhf.tar 70%[=============> ] 1.71M 1.69MB/s kselftest_armhf.tar 100%[===================>] 2.42M 2.11MB/s in 1.1s
1058 19:44:05.514293
1059 19:44:05.924035 2024-11-07 19:44:05 (2.11 MB/s) - 'kselftest_armhf.tar.gz' saved [2541784/2541784]
1060 19:44:05.924429
1061 19:44:26.612421 skiplist:
1062 19:44:26.612819 ========================================
1063 19:44:26.618156 ========================================
1064 19:44:26.731097 dt:test_unprobed_devices.sh
1065 19:44:26.763934 ============== Tests to run ===============
1066 19:44:26.772231 dt:test_unprobed_devices.sh
1067 19:44:26.776219 ===========End Tests to run ===============
1068 19:44:26.789244 shardfile-dt pass
1069 19:44:27.021075 <12>[ 81.206669] kselftest: Running tests in dt
1070 19:44:27.050876 TAP version 13
1071 19:44:27.075853 1..1
1072 19:44:27.132393 # timeout set to 45
1073 19:44:27.132673 # selftests: dt: test_unprobed_devices.sh
1074 19:44:27.937339 # TAP version 13
1075 19:44:53.891769 # 1..257
1076 19:44:54.111434 # ok 1 / # SKIP
1077 19:44:54.139675 # ok 2 /clk_mcasp0
1078 19:44:54.207346 # ok 3 /clk_mcasp0_fixed # SKIP
1079 19:44:54.282395 # ok 4 /cpus/cpu@0 # SKIP
1080 19:44:54.357302 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1081 19:44:54.382724 # ok 6 /fixedregulator0
1082 19:44:54.400391 # ok 7 /leds
1083 19:44:54.423686 # ok 8 /ocp
1084 19:44:54.448286 # ok 9 /ocp/interconnect@44c00000
1085 19:44:54.474627 # ok 10 /ocp/interconnect@44c00000/segment@0
1086 19:44:54.496953 # ok 11 /ocp/interconnect@44c00000/segment@100000
1087 19:44:54.522232 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1088 19:44:54.603853 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1089 19:44:54.619714 # ok 14 /ocp/interconnect@44c00000/segment@200000
1090 19:44:54.646602 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1091 19:44:54.757443 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1092 19:44:54.837460 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1093 19:44:54.913326 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1094 19:44:54.989313 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1095 19:44:55.062176 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1096 19:44:55.137677 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1097 19:44:55.214023 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1098 19:44:55.291369 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1099 19:44:55.366121 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1100 19:44:55.441647 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1101 19:44:55.516361 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1102 19:44:55.593391 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1103 19:44:55.670251 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1104 19:44:55.744881 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1105 19:44:55.825502 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1106 19:44:55.898365 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1107 19:44:55.978248 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1108 19:44:56.054382 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1109 19:44:56.124865 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1110 19:44:56.201601 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1111 19:44:56.275608 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1112 19:44:56.352608 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1113 19:44:56.428860 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1114 19:44:56.509354 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1115 19:44:56.581274 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1116 19:44:56.656147 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1117 19:44:56.733202 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1118 19:44:56.809023 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1119 19:44:56.885535 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1120 19:44:56.966489 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1121 19:44:57.040030 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1122 19:44:57.115048 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1123 19:44:57.190753 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1124 19:44:57.267009 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1125 19:44:57.343041 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1126 19:44:57.419001 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1127 19:44:57.494933 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1128 19:44:57.571413 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1129 19:44:57.650662 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1130 19:44:57.725120 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1131 19:44:57.807039 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1132 19:44:57.880088 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1133 19:44:57.952072 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1134 19:44:58.027961 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1135 19:44:58.104527 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1136 19:44:58.182153 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1137 19:44:58.254522 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1138 19:44:58.331637 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1139 19:44:58.407634 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1140 19:44:58.482285 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1141 19:44:58.558519 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1142 19:44:58.635123 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1143 19:44:58.715081 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1144 19:44:58.785710 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1145 19:44:58.862073 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1146 19:44:58.939191 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1147 19:44:59.014854 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1148 19:44:59.092726 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1149 19:44:59.169700 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1150 19:44:59.242199 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1151 19:44:59.316612 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1152 19:44:59.392933 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1153 19:44:59.467315 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1154 19:44:59.543804 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1155 19:44:59.622190 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1156 19:44:59.695276 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1157 19:44:59.772255 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1158 19:44:59.846244 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1159 19:44:59.922707 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1160 19:45:00.001452 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1161 19:45:00.074540 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1162 19:45:00.151548 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1163 19:45:00.227160 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1164 19:45:00.305531 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1165 19:45:00.382193 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1166 19:45:00.456074 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1167 19:45:00.533694 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1168 19:45:00.609081 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1169 19:45:00.685176 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1170 19:45:00.706191 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1171 19:45:00.731192 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1172 19:45:00.755668 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1173 19:45:00.780424 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1174 19:45:00.804797 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1175 19:45:00.830083 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1176 19:45:00.854433 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1177 19:45:00.882396 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1178 19:45:00.994949 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1179 19:45:01.018027 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1180 19:45:01.041305 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1181 19:45:01.065293 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1182 19:45:01.177415 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1183 19:45:01.256459 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1184 19:45:01.336899 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1185 19:45:01.410665 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1186 19:45:01.490168 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1187 19:45:01.561954 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1188 19:45:01.636651 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1189 19:45:01.713404 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1190 19:45:01.789643 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1191 19:45:01.866769 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1192 19:45:01.943610 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1193 19:45:02.020214 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1194 19:45:02.095528 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1195 19:45:02.178642 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1196 19:45:02.252058 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1197 19:45:02.327401 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1198 19:45:02.354947 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1199 19:45:02.424399 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1200 19:45:02.497996 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1201 19:45:02.574919 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1202 19:45:02.598949 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1203 19:45:02.674251 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1204 19:45:02.697265 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1205 19:45:02.772212 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1206 19:45:02.801129 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1207 19:45:02.822283 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1208 19:45:02.845893 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1209 19:45:02.871656 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1210 19:45:02.896453 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1211 19:45:02.920768 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1212 19:45:02.948510 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1213 19:45:03.030471 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1214 19:45:03.056538 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1215 19:45:03.075216 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1216 19:45:03.152002 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1217 19:45:03.228598 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1218 19:45:03.248627 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1219 19:45:03.354235 # not ok 144 /ocp/interconnect@47c00000
1220 19:45:03.434604 # not ok 145 /ocp/interconnect@47c00000/segment@0
1221 19:45:03.452854 # ok 146 /ocp/interconnect@48000000
1222 19:45:03.481514 # ok 147 /ocp/interconnect@48000000/segment@0
1223 19:45:03.502932 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1224 19:45:03.527489 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1225 19:45:03.556075 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1226 19:45:03.576116 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1227 19:45:03.604496 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1228 19:45:03.626836 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1229 19:45:03.653675 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1230 19:45:03.726376 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1231 19:45:03.806358 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1232 19:45:03.825996 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1233 19:45:03.854855 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1234 19:45:03.876012 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1235 19:45:03.899501 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1236 19:45:03.922947 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1237 19:45:03.954871 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1238 19:45:03.975929 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1239 19:45:03.999472 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1240 19:45:04.023129 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1241 19:45:04.048864 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1242 19:45:04.072142 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1243 19:45:04.101668 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1244 19:45:04.125378 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1245 19:45:04.150766 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1246 19:45:04.169359 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1247 19:45:04.195721 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1248 19:45:04.223862 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1249 19:45:04.246974 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1250 19:45:04.266982 # ok 175 /ocp/interconnect@48000000/segment@100000
1251 19:45:04.292647 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1252 19:45:04.317857 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1253 19:45:04.398714 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1254 19:45:04.472702 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1255 19:45:04.546699 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1256 19:45:04.624600 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1257 19:45:04.701581 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1258 19:45:04.777494 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1259 19:45:04.851927 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1260 19:45:04.930071 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1261 19:45:04.950230 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1262 19:45:04.975190 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1263 19:45:04.999929 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1264 19:45:05.024208 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1265 19:45:05.049489 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1266 19:45:05.076945 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1267 19:45:05.098952 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1268 19:45:05.124107 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1269 19:45:05.152539 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1270 19:45:05.176565 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1271 19:45:05.201660 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1272 19:45:05.226898 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1273 19:45:05.246296 # ok 198 /ocp/interconnect@48000000/segment@200000
1274 19:45:05.276074 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1275 19:45:05.353404 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1276 19:45:05.374532 # ok 201 /ocp/interconnect@48000000/segment@300000
1277 19:45:05.396257 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1278 19:45:05.421144 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1279 19:45:05.446748 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1280 19:45:05.474375 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1281 19:45:05.496476 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1282 19:45:05.519251 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1283 19:45:05.595430 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1284 19:45:05.615313 # ok 209 /ocp/interconnect@4a000000
1285 19:45:05.643819 # ok 210 /ocp/interconnect@4a000000/segment@0
1286 19:45:05.666968 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1287 19:45:05.696216 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1288 19:45:05.722785 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1289 19:45:05.739925 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1290 19:45:05.821277 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1291 19:45:05.929423 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1292 19:45:06.005543 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1293 19:45:06.115912 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1294 19:45:06.194453 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1295 19:45:06.267902 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1296 19:45:06.370783 # not ok 221 /ocp/interconnect@4b140000
1297 19:45:06.447532 # not ok 222 /ocp/interconnect@4b140000/segment@0
1298 19:45:06.522936 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1299 19:45:06.545656 # ok 224 /ocp/target-module@40300000
1300 19:45:06.573896 # ok 225 /ocp/target-module@40300000/sram@0
1301 19:45:06.647405 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1302 19:45:06.726138 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1303 19:45:06.748147 # ok 228 /ocp/target-module@47400000
1304 19:45:06.769392 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1305 19:45:06.792378 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1306 19:45:06.816391 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1307 19:45:06.844291 # ok 232 /ocp/target-module@47400000/usb@1400
1308 19:45:06.864111 # ok 233 /ocp/target-module@47400000/usb@1800
1309 19:45:06.890646 # ok 234 /ocp/target-module@47810000
1310 19:45:06.909069 # ok 235 /ocp/target-module@49000000
1311 19:45:06.933854 # ok 236 /ocp/target-module@49000000/dma@0
1312 19:45:06.960933 # ok 237 /ocp/target-module@49800000
1313 19:45:06.983814 # ok 238 /ocp/target-module@49800000/dma@0
1314 19:45:07.008273 # ok 239 /ocp/target-module@49900000
1315 19:45:07.032610 # ok 240 /ocp/target-module@49900000/dma@0
1316 19:45:07.053274 # ok 241 /ocp/target-module@49a00000
1317 19:45:07.075454 # ok 242 /ocp/target-module@49a00000/dma@0
1318 19:45:07.102762 # ok 243 /ocp/target-module@4c000000
1319 19:45:07.174841 # not ok 244 /ocp/target-module@4c000000/emif@0
1320 19:45:07.201521 # ok 245 /ocp/target-module@50000000
1321 19:45:07.223405 # ok 246 /ocp/target-module@53100000
1322 19:45:07.296185 # not ok 247 /ocp/target-module@53100000/sham@0
1323 19:45:07.322723 # ok 248 /ocp/target-module@53500000
1324 19:45:07.398637 # not ok 249 /ocp/target-module@53500000/aes@0
1325 19:45:07.416474 # ok 250 /ocp/target-module@56000000
1326 19:45:07.531820 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1327 19:45:07.600007 # ok 252 /opp-table # SKIP
1328 19:45:07.678922 # ok 253 /soc # SKIP
1329 19:45:07.695580 # ok 254 /sound
1330 19:45:07.720826 # ok 255 /target-module@4b000000
1331 19:45:07.751247 # ok 256 /target-module@4b000000/target-module@140000
1332 19:45:07.768435 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1333 19:45:07.776745 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1334 19:45:07.785675 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1335 19:45:09.903222 dt_test_unprobed_devices_sh_ skip
1336 19:45:09.908748 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1337 19:45:09.914510 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1338 19:45:09.914784 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1339 19:45:09.919978 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1340 19:45:09.925611 dt_test_unprobed_devices_sh_fixedregulator0 pass
1341 19:45:09.931219 dt_test_unprobed_devices_sh_leds pass
1342 19:45:09.931483 dt_test_unprobed_devices_sh_ocp pass
1343 19:45:09.936844 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1344 19:45:09.942469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1345 19:45:09.947965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1346 19:45:09.959265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1347 19:45:09.964908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1348 19:45:09.970600 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1349 19:45:09.981787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1350 19:45:09.987308 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1351 19:45:09.998563 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1352 19:45:10.009800 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1353 19:45:10.021029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1354 19:45:10.026655 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1355 19:45:10.037909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1356 19:45:10.049064 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1357 19:45:10.060275 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1358 19:45:10.071506 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1359 19:45:10.077067 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1360 19:45:10.088292 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1361 19:45:10.099526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1362 19:45:10.110678 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1363 19:45:10.121784 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1364 19:45:10.127576 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1365 19:45:10.138645 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1366 19:45:10.149770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1367 19:45:10.161044 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1368 19:45:10.166662 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1369 19:45:10.177812 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1370 19:45:10.189051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1371 19:45:10.200209 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1372 19:45:10.211457 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1373 19:45:10.216970 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1374 19:45:10.228199 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1375 19:45:10.239456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1376 19:45:10.250581 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1377 19:45:10.261825 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1378 19:45:10.272965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1379 19:45:10.284204 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1380 19:45:10.295328 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1381 19:45:10.306579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1382 19:45:10.317829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1383 19:45:10.328966 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1384 19:45:10.340229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1385 19:45:10.351284 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1386 19:45:10.362535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1387 19:45:10.373624 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1388 19:45:10.384962 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1389 19:45:10.396074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1390 19:45:10.407324 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1391 19:45:10.418576 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1392 19:45:10.429696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1393 19:45:10.440938 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1394 19:45:10.452072 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1395 19:45:10.463319 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1396 19:45:10.474554 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1397 19:45:10.485694 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1398 19:45:10.496813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1399 19:45:10.502565 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1400 19:45:10.513690 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1401 19:45:10.524812 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1402 19:45:10.536063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1403 19:45:10.547184 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1404 19:45:10.558435 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1405 19:45:10.569557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1406 19:45:10.580809 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1407 19:45:10.591935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1408 19:45:10.603189 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1409 19:45:10.614428 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1410 19:45:10.625555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1411 19:45:10.636862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1412 19:45:10.647957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1413 19:45:10.659130 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1414 19:45:10.670261 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1415 19:45:10.681507 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1416 19:45:10.692635 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1417 19:45:10.698256 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1418 19:45:10.709495 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1419 19:45:10.720631 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1420 19:45:10.731865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1421 19:45:10.742989 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1422 19:45:10.748620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1423 19:45:10.765504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1424 19:45:10.776617 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1425 19:45:10.782243 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1426 19:45:10.799003 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1427 19:45:10.810247 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1428 19:45:10.821501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1429 19:45:10.826988 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1430 19:45:10.838115 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1431 19:45:10.849383 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1432 19:45:10.854950 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1433 19:45:10.866069 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1434 19:45:10.877350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1435 19:45:10.882945 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1436 19:45:10.894073 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1437 19:45:10.899692 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1438 19:45:10.910818 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1439 19:45:10.922067 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1440 19:45:10.933316 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1441 19:45:10.944446 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1442 19:45:10.955696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1443 19:45:10.966824 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1444 19:45:10.978071 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1445 19:45:10.989187 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1446 19:45:11.000439 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1447 19:45:11.011563 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1448 19:45:11.022813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1449 19:45:11.034067 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1450 19:45:11.050850 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1451 19:45:11.062125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1452 19:45:11.073260 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1453 19:45:11.084493 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1454 19:45:11.095754 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1455 19:45:11.112509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1456 19:45:11.123616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1457 19:45:11.134865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1458 19:45:11.145988 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1459 19:45:11.151630 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1460 19:45:11.162871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1461 19:45:11.174004 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1462 19:45:11.179650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1463 19:45:11.190874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1464 19:45:11.196488 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1465 19:45:11.207612 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1466 19:45:11.213237 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1467 19:45:11.224498 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1468 19:45:11.230020 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1469 19:45:11.241127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1470 19:45:11.246737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1471 19:45:11.258020 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1472 19:45:11.269123 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1473 19:45:11.280359 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1474 19:45:11.291609 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1475 19:45:11.302734 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1476 19:45:11.308360 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1477 19:45:11.319608 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1478 19:45:11.325109 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1479 19:45:11.330750 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1480 19:45:11.336359 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1481 19:45:11.341859 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1482 19:45:11.347509 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1483 19:45:11.358733 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1484 19:45:11.364358 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1485 19:45:11.369869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1486 19:45:11.381107 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1487 19:45:11.386747 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1488 19:45:11.397855 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1489 19:45:11.403481 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1490 19:45:11.414747 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1491 19:45:11.420257 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1492 19:45:11.431490 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1493 19:45:11.437125 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1494 19:45:11.448239 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1495 19:45:11.453856 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1496 19:45:11.465121 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1497 19:45:11.470746 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1498 19:45:11.481911 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1499 19:45:11.487489 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1500 19:45:11.493171 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1501 19:45:11.504366 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1502 19:45:11.509990 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1503 19:45:11.521119 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1504 19:45:11.526737 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1505 19:45:11.537975 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1506 19:45:11.543606 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1507 19:45:11.554849 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1508 19:45:11.560509 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1509 19:45:11.565976 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1510 19:45:11.577237 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1511 19:45:11.582861 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1512 19:45:11.594068 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1513 19:45:11.605360 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1514 19:45:11.616586 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1515 19:45:11.627712 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1516 19:45:11.638832 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1517 19:45:11.650098 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1518 19:45:11.661335 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1519 19:45:11.672457 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1520 19:45:11.678088 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1521 19:45:11.689206 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1522 19:45:11.694834 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1523 19:45:11.706081 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1524 19:45:11.711582 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1525 19:45:11.722831 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1526 19:45:11.728457 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1527 19:45:11.739577 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1528 19:45:11.745222 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1529 19:45:11.756454 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1530 19:45:11.761953 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1531 19:45:11.773203 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1532 19:45:11.778833 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1533 19:45:11.789964 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1534 19:45:11.795580 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1535 19:45:11.801204 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1536 19:45:11.812452 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1537 19:45:11.817951 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1538 19:45:11.829199 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1539 19:45:11.834700 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1540 19:45:11.845962 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1541 19:45:11.851628 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1542 19:45:11.862719 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1543 19:45:11.868456 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1544 19:45:11.873957 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1545 19:45:11.879595 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1546 19:45:11.890701 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1547 19:45:11.901966 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1548 19:45:11.907574 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1549 19:45:11.913092 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1550 19:45:11.924325 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1551 19:45:11.935446 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1552 19:45:11.946714 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1553 19:45:11.957952 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1554 19:45:11.963617 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1555 19:45:11.969242 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1556 19:45:11.974831 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1557 19:45:11.980455 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1558 19:45:11.985934 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1559 19:45:11.991577 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1560 19:45:12.002823 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1561 19:45:12.008449 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1562 19:45:12.013981 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1563 19:45:12.019606 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1564 19:45:12.025301 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1565 19:45:12.036473 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1566 19:45:12.042079 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1567 19:45:12.047577 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1568 19:45:12.053278 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1569 19:45:12.058880 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1570 19:45:12.064482 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1571 19:45:12.070102 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1572 19:45:12.075578 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1573 19:45:12.081207 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1574 19:45:12.086826 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1575 19:45:12.092453 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1576 19:45:12.098092 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1577 19:45:12.103803 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1578 19:45:12.109254 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1579 19:45:12.114873 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1580 19:45:12.120467 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1581 19:45:12.126126 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1582 19:45:12.131686 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1583 19:45:12.137366 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1584 19:45:12.142920 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1585 19:45:12.148433 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1586 19:45:12.148674 dt_test_unprobed_devices_sh_opp-table skip
1587 19:45:12.154042 dt_test_unprobed_devices_sh_soc skip
1588 19:45:12.159689 dt_test_unprobed_devices_sh_sound pass
1589 19:45:12.165341 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1590 19:45:12.170983 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1591 19:45:12.176588 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1592 19:45:12.182074 dt_test_unprobed_devices_sh fail
1593 19:45:12.182385 + ../../utils/send-to-lava.sh ./output/result.txt
1594 19:45:12.190045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1595 19:45:12.190632 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1597 19:45:12.207546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1598 19:45:12.208034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1600 19:45:12.309542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1601 19:45:12.310028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1603 19:45:12.413395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1604 19:45:12.413915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1606 19:45:12.512995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1607 19:45:12.513554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1609 19:45:12.612396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1610 19:45:12.612896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1612 19:45:12.709043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1613 19:45:12.709529 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1615 19:45:12.821002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1616 19:45:12.821491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1618 19:45:12.930415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1619 19:45:12.930973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1621 19:45:13.032201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1622 19:45:13.032687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1624 19:45:13.131153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1625 19:45:13.131642 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1627 19:45:13.230957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1628 19:45:13.231443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1630 19:45:13.331068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1631 19:45:13.331546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1633 19:45:13.431313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1634 19:45:13.431793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1636 19:45:13.527806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1637 19:45:13.528344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1639 19:45:13.630597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1640 19:45:13.631084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1642 19:45:13.731379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1643 19:45:13.731866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1645 19:45:13.831877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1646 19:45:13.832364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1648 19:45:13.936012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1649 19:45:13.936563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1651 19:45:14.036119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1652 19:45:14.036609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1654 19:45:14.135119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1655 19:45:14.135610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1657 19:45:14.235862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1658 19:45:14.236350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1660 19:45:14.335572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1661 19:45:14.336064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1663 19:45:14.434232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1664 19:45:14.434734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1666 19:45:14.535840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1667 19:45:14.536394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1669 19:45:14.638188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1670 19:45:14.638674 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1672 19:45:14.741717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1673 19:45:14.742210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1675 19:45:14.848838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1676 19:45:14.849327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1678 19:45:14.950430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1679 19:45:14.950991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1681 19:45:15.055996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1682 19:45:15.056485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1684 19:45:15.157597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1685 19:45:15.158083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1687 19:45:15.260102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1688 19:45:15.260587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1690 19:45:15.366324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1691 19:45:15.366810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1693 19:45:15.468488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1694 19:45:15.469012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1696 19:45:15.567568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1697 19:45:15.568125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1699 19:45:15.675805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1700 19:45:15.676309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1702 19:45:15.777366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1703 19:45:15.777854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1705 19:45:15.881873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1706 19:45:15.882420 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1708 19:45:15.986343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1709 19:45:15.986800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1711 19:45:16.091569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1712 19:45:16.092050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1714 19:45:16.196538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1715 19:45:16.197059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1717 19:45:16.300870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1718 19:45:16.301388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1720 19:45:16.406607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1721 19:45:16.407089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1723 19:45:16.512189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1724 19:45:16.512776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1726 19:45:16.616847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1727 19:45:16.617333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1729 19:45:16.721874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1730 19:45:16.722380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1732 19:45:16.826710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1733 19:45:16.827189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1735 19:45:16.930580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1736 19:45:16.931125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1738 19:45:17.033281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1739 19:45:17.033762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1741 19:45:17.138590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1742 19:45:17.139113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1744 19:45:17.239022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1745 19:45:17.239550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1747 19:45:17.340548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1748 19:45:17.341069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1750 19:45:17.444136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1751 19:45:17.444549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1753 19:45:17.548417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1754 19:45:17.548999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1756 19:45:17.650165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1757 19:45:17.650666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1759 19:45:17.751396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1760 19:45:17.751886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1762 19:45:17.856683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1763 19:45:17.857195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1765 19:45:17.958800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1766 19:45:17.959361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1768 19:45:18.062925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1769 19:45:18.063410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1771 19:45:18.164225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1772 19:45:18.164732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1774 19:45:18.265909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1775 19:45:18.266393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1777 19:45:18.367300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1778 19:45:18.367792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1780 19:45:18.471021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1781 19:45:18.471509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1783 19:45:18.570425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1784 19:45:18.570982 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1786 19:45:18.672032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1787 19:45:18.672522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1789 19:45:18.774784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1790 19:45:18.775277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1792 19:45:18.876557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1793 19:45:18.877147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1795 19:45:18.977134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1796 19:45:18.977625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1798 19:45:19.075249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1799 19:45:19.075743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1801 19:45:19.176496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1802 19:45:19.177003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1804 19:45:19.275116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1805 19:45:19.275608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1807 19:45:19.373941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1808 19:45:19.374431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1810 19:45:19.475805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1811 19:45:19.476292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1813 19:45:19.575242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1814 19:45:19.575793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1816 19:45:19.679947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1817 19:45:19.680440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1819 19:45:19.781599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1820 19:45:19.782084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1822 19:45:19.885431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1823 19:45:19.885989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1825 19:45:19.988667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1826 19:45:19.989203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1828 19:45:20.095667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1829 19:45:20.096147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1831 19:45:20.197769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1832 19:45:20.198252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1834 19:45:20.300159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1835 19:45:20.300641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1837 19:45:20.407283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1838 19:45:20.407797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1840 19:45:20.509628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1841 19:45:20.510211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1843 19:45:20.614410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1844 19:45:20.614889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1846 19:45:20.715164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1847 19:45:20.715621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1849 19:45:20.816363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1850 19:45:20.816853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1852 19:45:20.917751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1853 19:45:20.918335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1855 19:45:21.022495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1856 19:45:21.023017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1858 19:45:21.125238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1859 19:45:21.125752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1861 19:45:21.228194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1862 19:45:21.228721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1864 19:45:21.329731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1865 19:45:21.330228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1867 19:45:21.434716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1868 19:45:21.435221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1870 19:45:21.538866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1871 19:45:21.539433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1873 19:45:21.639670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1874 19:45:21.640167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1876 19:45:21.742802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1877 19:45:21.743284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1879 19:45:21.844645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1880 19:45:21.845174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1882 19:45:21.944407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1883 19:45:21.944988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1885 19:45:22.044897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1886 19:45:22.045390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1888 19:45:22.149511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1889 19:45:22.150009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1891 19:45:22.254254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1892 19:45:22.254748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1894 19:45:22.356442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1895 19:45:22.356952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1897 19:45:22.455743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1898 19:45:22.456232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1900 19:45:22.557296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1901 19:45:22.557857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1903 19:45:22.658583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1904 19:45:22.659072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1906 19:45:22.760759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1907 19:45:22.761237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1909 19:45:22.859743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1910 19:45:22.860223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1912 19:45:22.964339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1913 19:45:22.964900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1915 19:45:23.067913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1916 19:45:23.068406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1918 19:45:23.172205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1919 19:45:23.172701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1921 19:45:23.279351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1922 19:45:23.279849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1924 19:45:23.379880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1925 19:45:23.380380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1927 19:45:23.482117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1928 19:45:23.482644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1930 19:45:23.588201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1931 19:45:23.588776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1933 19:45:23.686581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1934 19:45:23.687073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1936 19:45:23.787505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1937 19:45:23.787999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1939 19:45:23.889278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1940 19:45:23.889851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1942 19:45:23.991712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1943 19:45:23.992207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1945 19:45:24.091112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1946 19:45:24.091606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1948 19:45:24.190346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1949 19:45:24.190850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1951 19:45:24.289212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1952 19:45:24.289742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1954 19:45:24.389595 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1956 19:45:24.392574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1957 19:45:24.492199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1959 19:45:24.495318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1960 19:45:24.596584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1962 19:45:24.599565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1963 19:45:24.698481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1964 19:45:24.698973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1966 19:45:24.800119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1967 19:45:24.800614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1969 19:45:24.903853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1970 19:45:24.904408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1972 19:45:25.010469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1973 19:45:25.010965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1975 19:45:25.116571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1976 19:45:25.117099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1978 19:45:25.219459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1979 19:45:25.219944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1981 19:45:25.324494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1982 19:45:25.325006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1984 19:45:25.427290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1985 19:45:25.427776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1987 19:45:25.529581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1988 19:45:25.530134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1990 19:45:25.638235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1991 19:45:25.638724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1993 19:45:25.739479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1994 19:45:25.739967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1996 19:45:25.844474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1997 19:45:25.844979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1999 19:45:25.954065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2000 19:45:25.954618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2002 19:45:26.058218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2003 19:45:26.058704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2005 19:45:26.162823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2006 19:45:26.163309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2008 19:45:26.266483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2009 19:45:26.266970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2011 19:45:26.367226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2012 19:45:26.367714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2014 19:45:26.470435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2015 19:45:26.470932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2017 19:45:26.575848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2018 19:45:26.576406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2020 19:45:26.679049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2021 19:45:26.679543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2023 19:45:26.780811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2024 19:45:26.781300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2026 19:45:26.880569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2027 19:45:26.881078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2029 19:45:26.984197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2030 19:45:26.984764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2032 19:45:27.090925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2033 19:45:27.091408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2035 19:45:27.193921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2036 19:45:27.194401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2038 19:45:27.299667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2039 19:45:27.300152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2041 19:45:27.403790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2042 19:45:27.404277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2044 19:45:27.504468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2045 19:45:27.504782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2047 19:45:27.607689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2048 19:45:27.608245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2050 19:45:27.712995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2051 19:45:27.713484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2053 19:45:27.816923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2054 19:45:27.817412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2056 19:45:27.915173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2057 19:45:27.915714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2059 19:45:28.022063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2060 19:45:28.022547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2062 19:45:28.123913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2063 19:45:28.124409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2065 19:45:28.225934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2066 19:45:28.226424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2068 19:45:28.329993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2069 19:45:28.330477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2071 19:45:28.433190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2072 19:45:28.433695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2074 19:45:28.535347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2075 19:45:28.535892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2077 19:45:28.639408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2078 19:45:28.639904 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2080 19:45:28.743645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2081 19:45:28.744136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2083 19:45:28.845786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2084 19:45:28.846276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2086 19:45:28.953142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2087 19:45:28.953698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2089 19:45:29.053256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2090 19:45:29.053746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2092 19:45:29.156000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2093 19:45:29.156489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2095 19:45:29.256834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2096 19:45:29.257314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2098 19:45:29.357144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2099 19:45:29.357635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2101 19:45:29.455606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2102 19:45:29.456097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2104 19:45:29.556909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2105 19:45:29.557467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2107 19:45:29.659585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2108 19:45:29.660078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2110 19:45:29.763335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2111 19:45:29.763853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2113 19:45:29.862624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2114 19:45:29.863104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2116 19:45:29.964340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2117 19:45:29.964868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2119 19:45:30.065067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2120 19:45:30.065550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2122 19:45:30.167005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2123 19:45:30.167497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2125 19:45:30.270803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2126 19:45:30.271280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2128 19:45:30.375150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2129 19:45:30.375604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2131 19:45:30.479170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2132 19:45:30.479630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2134 19:45:30.578672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2135 19:45:30.579238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2137 19:45:30.685669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2138 19:45:30.686180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2140 19:45:30.785907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2141 19:45:30.786359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2143 19:45:30.887936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2144 19:45:30.888428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2146 19:45:30.989290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2147 19:45:30.989834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2149 19:45:31.090295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2150 19:45:31.090783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2152 19:45:31.186187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2153 19:45:31.186654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2155 19:45:31.287991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2156 19:45:31.288485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2158 19:45:31.390889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2159 19:45:31.391346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2161 19:45:31.493299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2162 19:45:31.493791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2164 19:45:31.595264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2165 19:45:31.595817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2167 19:45:31.697057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2168 19:45:31.697519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2170 19:45:31.802903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2171 19:45:31.803391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2173 19:45:31.905734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2174 19:45:31.906310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2176 19:45:32.006160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2177 19:45:32.006654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2179 19:45:32.109814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2180 19:45:32.110302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2182 19:45:32.212850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2183 19:45:32.213337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2185 19:45:32.314789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2186 19:45:32.315277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2188 19:45:32.413794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2189 19:45:32.414285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2191 19:45:32.518783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2192 19:45:32.519284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2194 19:45:32.622285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2195 19:45:32.622835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2197 19:45:32.721409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2198 19:45:32.721901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2200 19:45:32.827776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2201 19:45:32.828269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2203 19:45:32.927398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2204 19:45:32.927959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2206 19:45:33.031133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2207 19:45:33.031624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2209 19:45:33.132768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2210 19:45:33.133257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2212 19:45:33.234752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2213 19:45:33.235262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2215 19:45:33.335877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2216 19:45:33.336368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2218 19:45:33.438887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2219 19:45:33.439379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2221 19:45:33.534231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2222 19:45:33.534722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2224 19:45:33.634754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2225 19:45:33.635323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2227 19:45:33.737505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2228 19:45:33.737994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2230 19:45:33.844738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2231 19:45:33.845232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2233 19:45:33.947301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2234 19:45:33.947857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2236 19:45:34.047297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2237 19:45:34.047790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2239 19:45:34.152292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2240 19:45:34.152766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2242 19:45:34.256784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2243 19:45:34.257306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2245 19:45:34.361075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2246 19:45:34.361569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2248 19:45:34.462026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2249 19:45:34.462571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2251 19:45:34.563557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2252 19:45:34.564179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2254 19:45:34.665360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2255 19:45:34.665848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2257 19:45:34.762176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2258 19:45:34.762695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2260 19:45:34.866479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2261 19:45:34.866974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2263 19:45:34.971993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2264 19:45:34.972544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2266 19:45:35.073166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2267 19:45:35.073715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2269 19:45:35.175021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2270 19:45:35.175510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2272 19:45:35.276438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2273 19:45:35.276943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2275 19:45:35.374687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2277 19:45:35.377671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2278 19:45:35.477523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2279 19:45:35.478018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2281 19:45:35.583299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2282 19:45:35.583868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2284 19:45:35.700283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2285 19:45:35.700765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2287 19:45:35.804666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2288 19:45:35.805191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2290 19:45:35.906792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2291 19:45:35.907291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2293 19:45:36.010412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2294 19:45:36.010972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2296 19:45:36.111388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2297 19:45:36.111905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2299 19:45:36.213791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2300 19:45:36.214317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2302 19:45:36.319896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2303 19:45:36.320389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2305 19:45:36.419409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2306 19:45:36.419900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2308 19:45:36.521922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2309 19:45:36.522411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2311 19:45:36.625000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2312 19:45:36.625562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2314 19:45:36.726386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2315 19:45:36.726877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2317 19:45:36.829111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2318 19:45:36.829601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2320 19:45:36.931567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2321 19:45:36.932119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2323 19:45:37.029184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2324 19:45:37.029664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2326 19:45:37.129909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2327 19:45:37.130383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2329 19:45:37.229313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2330 19:45:37.229782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2332 19:45:37.326844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2333 19:45:37.327333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2335 19:45:37.428536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2336 19:45:37.429048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2338 19:45:37.530463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2339 19:45:37.530962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2341 19:45:37.632593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2342 19:45:37.633156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2344 19:45:37.734315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2345 19:45:37.734796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2347 19:45:37.833818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2348 19:45:37.834310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2350 19:45:37.931353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2351 19:45:37.931895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2353 19:45:38.030291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2354 19:45:38.030681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2356 19:45:38.132515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2357 19:45:38.133015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2359 19:45:38.233715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2360 19:45:38.234210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2362 19:45:38.335911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2363 19:45:38.336397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2365 19:45:38.436670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2366 19:45:38.437190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2368 19:45:38.539599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2369 19:45:38.539924 + set +x
2370 19:45:38.540430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2372 19:45:38.543896 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1218799_1.6.2.4.5>
2373 19:45:38.544342 Received signal: <ENDRUN> 1_kselftest-dt 1218799_1.6.2.4.5
2374 19:45:38.544601 Ending use of test pattern.
2375 19:45:38.544877 Ending test lava.1_kselftest-dt (1218799_1.6.2.4.5), duration 95.24
2377 19:45:38.551250 <LAVA_TEST_RUNNER EXIT>
2378 19:45:38.551820 ok: lava_test_shell seems to have completed
2379 19:45:38.557918 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2380 19:45:38.559030 end: 3.1 lava-test-shell (duration 00:01:37) [common]
2381 19:45:38.559368 end: 3 lava-test-retry (duration 00:01:37) [common]
2382 19:45:38.559706 start: 4 finalize (timeout 00:05:35) [common]
2383 19:45:38.560044 start: 4.1 power-off (timeout 00:00:30) [common]
2384 19:45:38.560469 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2385 19:45:38.930688 Returned 0 in 0 seconds
2386 19:45:39.031611 end: 4.1 power-off (duration 00:00:00) [common]
2388 19:45:39.032611 start: 4.2 read-feedback (timeout 00:05:35) [common]
2389 19:45:39.033294 Listened to connection for namespace 'common' for up to 1s
2390 19:45:39.033882 Listened to connection for namespace 'common' for up to 1s
2391 19:45:40.034203 Finalising connection for namespace 'common'
2392 19:45:40.034675 Disconnecting from shell: Finalise
2393 19:45:40.034991 / #
2394 19:45:40.135583 end: 4.2 read-feedback (duration 00:00:01) [common]
2395 19:45:40.135998 end: 4 finalize (duration 00:00:02) [common]
2396 19:45:40.136503 Cleaning after the job
2397 19:45:40.136973 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1218799/tftp-deploy-8iavx6z_/ramdisk
2398 19:45:40.142602 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1218799/tftp-deploy-8iavx6z_/kernel
2399 19:45:40.147192 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1218799/tftp-deploy-8iavx6z_/dtb
2400 19:45:40.147829 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1218799/tftp-deploy-8iavx6z_/nfsrootfs
2401 19:45:40.199066 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1218799/tftp-deploy-8iavx6z_/modules
2402 19:45:40.202634 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1218799
2403 19:45:40.863850 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1218799
2404 19:45:40.864134 Job finished correctly