Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 00:02:40.805770 lava-dispatcher, installed at version: 2024.01
2 00:02:40.806611 start: 0 validate
3 00:02:40.807095 Start time: 2024-11-08 00:02:40.807065+00:00 (UTC)
4 00:02:40.807628 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 00:02:40.808158 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 00:02:40.843115 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 00:02:40.843669 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-164-gbfc64d9b7e8c%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 00:02:40.866859 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 00:02:40.867503 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-164-gbfc64d9b7e8c%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 00:02:40.891517 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 00:02:40.892022 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 00:02:40.915451 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 00:02:40.915942 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-164-gbfc64d9b7e8c%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 00:02:40.944995 validate duration: 0.14
16 00:02:40.946146 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:02:40.946484 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:02:40.946785 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:02:40.947365 Not decompressing ramdisk as can be used compressed.
20 00:02:40.947805 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 00:02:40.948083 saving as /var/lib/lava/dispatcher/tmp/956489/tftp-deploy-63p351ov/ramdisk/initrd.cpio.gz
22 00:02:40.948351 total size: 4775763 (4 MB)
23 00:02:40.977312 progress 0 % (0 MB)
24 00:02:40.980859 progress 5 % (0 MB)
25 00:02:40.984213 progress 10 % (0 MB)
26 00:02:40.987549 progress 15 % (0 MB)
27 00:02:40.991306 progress 20 % (0 MB)
28 00:02:40.994626 progress 25 % (1 MB)
29 00:02:40.997872 progress 30 % (1 MB)
30 00:02:41.001596 progress 35 % (1 MB)
31 00:02:41.004885 progress 40 % (1 MB)
32 00:02:41.008120 progress 45 % (2 MB)
33 00:02:41.011408 progress 50 % (2 MB)
34 00:02:41.015072 progress 55 % (2 MB)
35 00:02:41.018362 progress 60 % (2 MB)
36 00:02:41.021572 progress 65 % (2 MB)
37 00:02:41.025310 progress 70 % (3 MB)
38 00:02:41.028760 progress 75 % (3 MB)
39 00:02:41.032069 progress 80 % (3 MB)
40 00:02:41.035444 progress 85 % (3 MB)
41 00:02:41.039145 progress 90 % (4 MB)
42 00:02:41.042280 progress 95 % (4 MB)
43 00:02:41.045208 progress 100 % (4 MB)
44 00:02:41.045864 4 MB downloaded in 0.10 s (46.73 MB/s)
45 00:02:41.046447 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:02:41.047339 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:02:41.047628 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:02:41.047906 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:02:41.048392 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-164-gbfc64d9b7e8c/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 00:02:41.048647 saving as /var/lib/lava/dispatcher/tmp/956489/tftp-deploy-63p351ov/kernel/zImage
52 00:02:41.048886 total size: 11444736 (10 MB)
53 00:02:41.049110 No compression specified
54 00:02:41.081002 progress 0 % (0 MB)
55 00:02:41.088598 progress 5 % (0 MB)
56 00:02:41.095897 progress 10 % (1 MB)
57 00:02:41.103670 progress 15 % (1 MB)
58 00:02:41.110984 progress 20 % (2 MB)
59 00:02:41.118679 progress 25 % (2 MB)
60 00:02:41.126059 progress 30 % (3 MB)
61 00:02:41.133573 progress 35 % (3 MB)
62 00:02:41.140868 progress 40 % (4 MB)
63 00:02:41.148673 progress 45 % (4 MB)
64 00:02:41.155876 progress 50 % (5 MB)
65 00:02:41.163592 progress 55 % (6 MB)
66 00:02:41.170895 progress 60 % (6 MB)
67 00:02:41.178578 progress 65 % (7 MB)
68 00:02:41.185772 progress 70 % (7 MB)
69 00:02:41.193079 progress 75 % (8 MB)
70 00:02:41.200665 progress 80 % (8 MB)
71 00:02:41.208064 progress 85 % (9 MB)
72 00:02:41.215667 progress 90 % (9 MB)
73 00:02:41.222896 progress 95 % (10 MB)
74 00:02:41.230131 progress 100 % (10 MB)
75 00:02:41.230652 10 MB downloaded in 0.18 s (60.05 MB/s)
76 00:02:41.231142 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:02:41.231977 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:02:41.232267 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:02:41.232539 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:02:41.233020 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-164-gbfc64d9b7e8c/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 00:02:41.233295 saving as /var/lib/lava/dispatcher/tmp/956489/tftp-deploy-63p351ov/dtb/am335x-boneblack.dtb
83 00:02:41.233508 total size: 70568 (0 MB)
84 00:02:41.233722 No compression specified
85 00:02:41.266116 progress 46 % (0 MB)
86 00:02:41.266936 progress 92 % (0 MB)
87 00:02:41.267734 progress 100 % (0 MB)
88 00:02:41.268155 0 MB downloaded in 0.03 s (1.94 MB/s)
89 00:02:41.268622 end: 1.3.1 http-download (duration 00:00:00) [common]
91 00:02:41.269450 end: 1.3 download-retry (duration 00:00:00) [common]
92 00:02:41.269728 start: 1.4 download-retry (timeout 00:10:00) [common]
93 00:02:41.270037 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 00:02:41.270517 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 00:02:41.270784 saving as /var/lib/lava/dispatcher/tmp/956489/tftp-deploy-63p351ov/nfsrootfs/full.rootfs.tar
96 00:02:41.271003 total size: 117747780 (112 MB)
97 00:02:41.271230 Using unxz to decompress xz
98 00:02:41.302589 progress 0 % (0 MB)
99 00:02:42.019145 progress 5 % (5 MB)
100 00:02:42.758751 progress 10 % (11 MB)
101 00:02:43.526196 progress 15 % (16 MB)
102 00:02:44.241131 progress 20 % (22 MB)
103 00:02:44.815091 progress 25 % (28 MB)
104 00:02:45.652989 progress 30 % (33 MB)
105 00:02:46.441240 progress 35 % (39 MB)
106 00:02:46.788113 progress 40 % (44 MB)
107 00:02:47.163728 progress 45 % (50 MB)
108 00:02:47.836881 progress 50 % (56 MB)
109 00:02:48.730811 progress 55 % (61 MB)
110 00:02:49.474818 progress 60 % (67 MB)
111 00:02:50.176859 progress 65 % (73 MB)
112 00:02:50.922947 progress 70 % (78 MB)
113 00:02:51.668275 progress 75 % (84 MB)
114 00:02:52.386235 progress 80 % (89 MB)
115 00:02:53.087057 progress 85 % (95 MB)
116 00:02:53.964357 progress 90 % (101 MB)
117 00:02:54.891343 progress 95 % (106 MB)
118 00:02:55.767713 progress 100 % (112 MB)
119 00:02:55.779999 112 MB downloaded in 14.51 s (7.74 MB/s)
120 00:02:55.780883 end: 1.4.1 http-download (duration 00:00:15) [common]
122 00:02:55.782596 end: 1.4 download-retry (duration 00:00:15) [common]
123 00:02:55.783112 start: 1.5 download-retry (timeout 00:09:45) [common]
124 00:02:55.783620 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 00:02:55.784374 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-164-gbfc64d9b7e8c/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 00:02:55.784820 saving as /var/lib/lava/dispatcher/tmp/956489/tftp-deploy-63p351ov/modules/modules.tar
127 00:02:55.785224 total size: 6610956 (6 MB)
128 00:02:55.785636 Using unxz to decompress xz
129 00:02:55.824081 progress 0 % (0 MB)
130 00:02:55.860037 progress 5 % (0 MB)
131 00:02:55.903265 progress 10 % (0 MB)
132 00:02:55.946338 progress 15 % (0 MB)
133 00:02:55.990624 progress 20 % (1 MB)
134 00:02:56.036962 progress 25 % (1 MB)
135 00:02:56.080169 progress 30 % (1 MB)
136 00:02:56.122857 progress 35 % (2 MB)
137 00:02:56.166150 progress 40 % (2 MB)
138 00:02:56.209026 progress 45 % (2 MB)
139 00:02:56.252664 progress 50 % (3 MB)
140 00:02:56.295318 progress 55 % (3 MB)
141 00:02:56.344821 progress 60 % (3 MB)
142 00:02:56.387846 progress 65 % (4 MB)
143 00:02:56.431141 progress 70 % (4 MB)
144 00:02:56.477509 progress 75 % (4 MB)
145 00:02:56.520989 progress 80 % (5 MB)
146 00:02:56.563914 progress 85 % (5 MB)
147 00:02:56.607083 progress 90 % (5 MB)
148 00:02:56.650438 progress 95 % (6 MB)
149 00:02:56.694131 progress 100 % (6 MB)
150 00:02:56.707358 6 MB downloaded in 0.92 s (6.84 MB/s)
151 00:02:56.707949 end: 1.5.1 http-download (duration 00:00:01) [common]
153 00:02:56.708773 end: 1.5 download-retry (duration 00:00:01) [common]
154 00:02:56.709042 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 00:02:56.709303 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 00:03:13.410182 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/956489/extract-nfsrootfs-sc4re3gr
157 00:03:13.410797 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 00:03:13.411090 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 00:03:13.411737 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx
160 00:03:13.412186 makedir: /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin
161 00:03:13.412574 makedir: /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/tests
162 00:03:13.412922 makedir: /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/results
163 00:03:13.413282 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-add-keys
164 00:03:13.413874 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-add-sources
165 00:03:13.414500 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-background-process-start
166 00:03:13.415220 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-background-process-stop
167 00:03:13.415853 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-common-functions
168 00:03:13.416421 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-echo-ipv4
169 00:03:13.416974 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-install-packages
170 00:03:13.417554 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-installed-packages
171 00:03:13.418248 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-os-build
172 00:03:13.418855 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-probe-channel
173 00:03:13.419409 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-probe-ip
174 00:03:13.419931 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-target-ip
175 00:03:13.420439 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-target-mac
176 00:03:13.420956 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-target-storage
177 00:03:13.421492 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-test-case
178 00:03:13.422047 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-test-event
179 00:03:13.422590 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-test-feedback
180 00:03:13.423109 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-test-raise
181 00:03:13.423678 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-test-reference
182 00:03:13.424210 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-test-runner
183 00:03:13.424740 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-test-set
184 00:03:13.425325 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-test-shell
185 00:03:13.425894 Updating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-add-keys (debian)
186 00:03:13.426507 Updating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-add-sources (debian)
187 00:03:13.427124 Updating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-install-packages (debian)
188 00:03:13.427693 Updating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-installed-packages (debian)
189 00:03:13.428241 Updating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/bin/lava-os-build (debian)
190 00:03:13.428729 Creating /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/environment
191 00:03:13.429151 LAVA metadata
192 00:03:13.429422 - LAVA_JOB_ID=956489
193 00:03:13.429640 - LAVA_DISPATCHER_IP=192.168.6.3
194 00:03:13.430067 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 00:03:13.431144 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 00:03:13.431505 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 00:03:13.431715 skipped lava-vland-overlay
198 00:03:13.431958 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 00:03:13.432215 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 00:03:13.432421 skipped lava-multinode-overlay
201 00:03:13.432661 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 00:03:13.432911 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 00:03:13.433169 Loading test definitions
204 00:03:13.433450 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 00:03:13.433692 Using /lava-956489 at stage 0
206 00:03:13.435129 uuid=956489_1.6.2.4.1 testdef=None
207 00:03:13.435489 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 00:03:13.435762 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 00:03:13.437497 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 00:03:13.438371 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 00:03:13.441783 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 00:03:13.442726 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 00:03:13.444707 runner path: /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/0/tests/0_timesync-off test_uuid 956489_1.6.2.4.1
216 00:03:13.445360 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 00:03:13.446249 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 00:03:13.446480 Using /lava-956489 at stage 0
220 00:03:13.446861 Fetching tests from https://github.com/kernelci/test-definitions.git
221 00:03:13.447166 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/0/tests/1_kselftest-dt'
222 00:03:17.027294 Running '/usr/bin/git checkout kernelci.org
223 00:03:17.053537 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 00:03:17.054980 uuid=956489_1.6.2.4.5 testdef=None
225 00:03:17.055327 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 00:03:17.056072 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 00:03:17.058866 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 00:03:17.059695 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 00:03:17.063378 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 00:03:17.064244 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 00:03:17.067836 runner path: /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/0/tests/1_kselftest-dt test_uuid 956489_1.6.2.4.5
235 00:03:17.068150 BOARD='beaglebone-black'
236 00:03:17.068359 BRANCH='mainline'
237 00:03:17.068558 SKIPFILE='/dev/null'
238 00:03:17.068755 SKIP_INSTALL='True'
239 00:03:17.068949 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-164-gbfc64d9b7e8c/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 00:03:17.069149 TST_CASENAME=''
241 00:03:17.069342 TST_CMDFILES='dt'
242 00:03:17.069896 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 00:03:17.070706 Creating lava-test-runner.conf files
245 00:03:17.070912 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/956489/lava-overlay-qie3olhx/lava-956489/0 for stage 0
246 00:03:17.071285 - 0_timesync-off
247 00:03:17.071549 - 1_kselftest-dt
248 00:03:17.071885 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 00:03:17.072171 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 00:03:40.488417 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 00:03:40.488878 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 00:03:40.489144 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 00:03:40.489416 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 00:03:40.489682 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 00:03:40.902893 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 00:03:40.903426 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 00:03:40.903727 extracting modules file /var/lib/lava/dispatcher/tmp/956489/tftp-deploy-63p351ov/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956489/extract-nfsrootfs-sc4re3gr
258 00:03:41.795215 extracting modules file /var/lib/lava/dispatcher/tmp/956489/tftp-deploy-63p351ov/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956489/extract-overlay-ramdisk-j9979yo1/ramdisk
259 00:03:42.703014 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 00:03:42.703493 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 00:03:42.703795 [common] Applying overlay to NFS
262 00:03:42.704034 [common] Applying overlay /var/lib/lava/dispatcher/tmp/956489/compress-overlay-6gyyxek0/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/956489/extract-nfsrootfs-sc4re3gr
263 00:03:45.449941 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 00:03:45.450425 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 00:03:45.450723 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 00:03:45.451048 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 00:03:45.451322 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 00:03:45.451594 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 00:03:45.451857 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 00:03:45.452155 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 00:03:45.452408 Building ramdisk /var/lib/lava/dispatcher/tmp/956489/extract-overlay-ramdisk-j9979yo1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/956489/extract-overlay-ramdisk-j9979yo1/ramdisk
272 00:03:46.442116 >> 74900 blocks
273 00:03:50.992116 Adding RAMdisk u-boot header.
274 00:03:50.994175 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/956489/extract-overlay-ramdisk-j9979yo1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/956489/extract-overlay-ramdisk-j9979yo1/ramdisk.cpio.gz.uboot
275 00:03:51.160599 output: Image Name:
276 00:03:51.161076 output: Created: Fri Nov 8 00:03:50 2024
277 00:03:51.161316 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 00:03:51.161551 output: Data Size: 14790578 Bytes = 14443.92 KiB = 14.11 MiB
279 00:03:51.161777 output: Load Address: 00000000
280 00:03:51.162066 output: Entry Point: 00000000
281 00:03:51.162318 output:
282 00:03:51.163028 rename /var/lib/lava/dispatcher/tmp/956489/extract-overlay-ramdisk-j9979yo1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/956489/tftp-deploy-63p351ov/ramdisk/ramdisk.cpio.gz.uboot
283 00:03:51.163618 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 00:03:51.164006 end: 1.6 prepare-tftp-overlay (duration 00:00:54) [common]
285 00:03:51.164364 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 00:03:51.164665 No LXC device requested
287 00:03:51.164991 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 00:03:51.165308 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 00:03:51.165622 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 00:03:51.165887 Checking files for TFTP limit of 4294967296 bytes.
291 00:03:51.167605 end: 1 tftp-deploy (duration 00:01:10) [common]
292 00:03:51.168048 start: 2 uboot-action (timeout 00:05:00) [common]
293 00:03:51.168375 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 00:03:51.168662 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 00:03:51.168946 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 00:03:51.169400 substitutions:
297 00:03:51.169646 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 00:03:51.169889 - {DTB_ADDR}: 0x88000000
299 00:03:51.170109 - {DTB}: 956489/tftp-deploy-63p351ov/dtb/am335x-boneblack.dtb
300 00:03:51.170317 - {INITRD}: 956489/tftp-deploy-63p351ov/ramdisk/ramdisk.cpio.gz.uboot
301 00:03:51.170525 - {KERNEL_ADDR}: 0x82000000
302 00:03:51.170728 - {KERNEL}: 956489/tftp-deploy-63p351ov/kernel/zImage
303 00:03:51.170971 - {LAVA_MAC}: None
304 00:03:51.171251 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/956489/extract-nfsrootfs-sc4re3gr
305 00:03:51.171502 - {NFS_SERVER_IP}: 192.168.6.3
306 00:03:51.171727 - {PRESEED_CONFIG}: None
307 00:03:51.171933 - {PRESEED_LOCAL}: None
308 00:03:51.172162 - {RAMDISK_ADDR}: 0x83000000
309 00:03:51.172388 - {RAMDISK}: 956489/tftp-deploy-63p351ov/ramdisk/ramdisk.cpio.gz.uboot
310 00:03:51.172601 - {ROOT_PART}: None
311 00:03:51.172804 - {ROOT}: None
312 00:03:51.173004 - {SERVER_IP}: 192.168.6.3
313 00:03:51.173240 - {TEE_ADDR}: 0x83000000
314 00:03:51.173477 - {TEE}: None
315 00:03:51.173715 Parsed boot commands:
316 00:03:51.173970 - setenv autoload no
317 00:03:51.174302 - setenv initrd_high 0xffffffff
318 00:03:51.174707 - setenv fdt_high 0xffffffff
319 00:03:51.174957 - dhcp
320 00:03:51.175175 - setenv serverip 192.168.6.3
321 00:03:51.175385 - tftp 0x82000000 956489/tftp-deploy-63p351ov/kernel/zImage
322 00:03:51.175592 - tftp 0x83000000 956489/tftp-deploy-63p351ov/ramdisk/ramdisk.cpio.gz.uboot
323 00:03:51.175823 - setenv initrd_size ${filesize}
324 00:03:51.176068 - tftp 0x88000000 956489/tftp-deploy-63p351ov/dtb/am335x-boneblack.dtb
325 00:03:51.176318 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/956489/extract-nfsrootfs-sc4re3gr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 00:03:51.176558 - bootz 0x82000000 0x83000000 0x88000000
327 00:03:51.176885 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 00:03:51.177783 start: 2.3 connect-device (timeout 00:05:00) [common]
330 00:03:51.178073 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 00:03:51.189669 Setting prompt string to ['lava-test: # ']
332 00:03:51.190753 end: 2.3 connect-device (duration 00:00:00) [common]
333 00:03:51.191186 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 00:03:51.191582 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 00:03:51.191940 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 00:03:51.192938 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 00:03:51.226714 >> OK - accepted request
338 00:03:51.228492 Returned 0 in 0 seconds
339 00:03:51.329458 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 00:03:51.331262 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 00:03:51.331873 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 00:03:51.332400 Setting prompt string to ['Hit any key to stop autoboot']
344 00:03:51.332881 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 00:03:51.334509 Trying 192.168.56.22...
346 00:03:51.335024 Connected to conserv3.
347 00:03:51.335462 Escape character is '^]'.
348 00:03:51.335891
349 00:03:51.336319 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 00:03:51.336752
351 00:03:59.647793
352 00:03:59.654735 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 00:03:59.655041 Trying to boot from MMC1
354 00:04:03.705457
355 00:04:03.712553 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 00:04:03.712915 Trying to boot from MMC1
357 00:04:06.394332
358 00:04:06.400909 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 00:04:06.401433 Trying to boot from MMC1
360 00:04:06.984407
361 00:04:06.984845
362 00:04:06.989695 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 00:04:06.990269
364 00:04:06.990703 CPU : AM335X-GP rev 2.0
365 00:04:06.994952 Model: TI AM335x BeagleBone Black
366 00:04:06.995398 DRAM: 512 MiB
367 00:04:07.074622 Core: 160 devices, 18 uclasses, devicetree: separate
368 00:04:07.088589 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 00:04:07.489420 NAND: 0 MiB
370 00:04:07.499835 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 00:04:07.596822 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 00:04:07.617424 <ethaddr> not set. Validating first E-fuse MAC
373 00:04:07.648544 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 00:04:07.707168 Hit any key to stop autoboot: 2
376 00:04:07.708032 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
377 00:04:07.708652 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
378 00:04:07.709144 Setting prompt string to ['=>']
379 00:04:07.709642 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
380 00:04:07.716989 0
381 00:04:07.717981 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 00:04:07.718511 Sending with 10 millisecond of delay
384 00:04:08.853623 => setenv autoload no
385 00:04:08.866365 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
386 00:04:08.869068 setenv autoload no
387 00:04:08.869615 Sending with 10 millisecond of delay
389 00:04:10.666473 => setenv initrd_high 0xffffffff
390 00:04:10.677088 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
391 00:04:10.679006 setenv initrd_high 0xffffffff
392 00:04:10.679821 Sending with 10 millisecond of delay
394 00:04:12.296633 => setenv fdt_high 0xffffffff
395 00:04:12.307478 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
396 00:04:12.308406 setenv fdt_high 0xffffffff
397 00:04:12.309191 Sending with 10 millisecond of delay
399 00:04:12.601304 => dhcp
400 00:04:12.612196 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
401 00:04:12.613075 dhcp
402 00:04:12.613555 link up on port 0, speed 100, full duplex
403 00:04:12.614051 BOOTP broadcast 1
404 00:04:12.866616 BOOTP broadcast 2
405 00:04:13.368665 BOOTP broadcast 3
406 00:04:14.369889 BOOTP broadcast 4
407 00:04:16.372837 BOOTP broadcast 5
408 00:04:16.456089 DHCP client bound to address 192.168.6.8 (3839 ms)
409 00:04:16.456759 Sending with 10 millisecond of delay
411 00:04:18.133344 => setenv serverip 192.168.6.3
412 00:04:18.144023 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
413 00:04:18.144669 setenv serverip 192.168.6.3
414 00:04:18.145205 Sending with 10 millisecond of delay
416 00:04:21.631194 => tftp 0x82000000 956489/tftp-deploy-63p351ov/kernel/zImage
417 00:04:21.642069 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:30)
418 00:04:21.643030 tftp 0x82000000 956489/tftp-deploy-63p351ov/kernel/zImage
419 00:04:21.643504 link up on port 0, speed 100, full duplex
420 00:04:21.646903 Using ethernet@4a100000 device
421 00:04:21.653395 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
422 00:04:21.653905 Filename '956489/tftp-deploy-63p351ov/kernel/zImage'.
423 00:04:21.656189 Load address: 0x82000000
424 00:04:23.691657 Loading: *################################################## 10.9 MiB
425 00:04:23.692076 5.4 MiB/s
426 00:04:23.692286 done
427 00:04:23.696031 Bytes transferred = 11444736 (aea200 hex)
428 00:04:23.696548 Sending with 10 millisecond of delay
430 00:04:28.142572 => tftp 0x83000000 956489/tftp-deploy-63p351ov/ramdisk/ramdisk.cpio.gz.uboot
431 00:04:28.153423 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
432 00:04:28.154418 tftp 0x83000000 956489/tftp-deploy-63p351ov/ramdisk/ramdisk.cpio.gz.uboot
433 00:04:28.154899 link up on port 0, speed 100, full duplex
434 00:04:28.158259 Using ethernet@4a100000 device
435 00:04:28.163869 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
436 00:04:28.172523 Filename '956489/tftp-deploy-63p351ov/ramdisk/ramdisk.cpio.gz.uboot'.
437 00:04:28.173094 Load address: 0x83000000
438 00:04:30.818343 Loading: *################################################## 14.1 MiB
439 00:04:30.818978 5.3 MiB/s
440 00:04:30.819453 done
441 00:04:30.822522 Bytes transferred = 14790642 (e1aff2 hex)
442 00:04:30.823289 Sending with 10 millisecond of delay
444 00:04:32.680373 => setenv initrd_size ${filesize}
445 00:04:32.690967 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
446 00:04:32.692645 setenv initrd_size ${filesize}
447 00:04:32.694023 Sending with 10 millisecond of delay
449 00:04:36.840795 => tftp 0x88000000 956489/tftp-deploy-63p351ov/dtb/am335x-boneblack.dtb
450 00:04:36.851649 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
451 00:04:36.852584 tftp 0x88000000 956489/tftp-deploy-63p351ov/dtb/am335x-boneblack.dtb
452 00:04:36.853059 link up on port 0, speed 100, full duplex
453 00:04:36.856268 Using ethernet@4a100000 device
454 00:04:36.861942 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
455 00:04:36.873196 Filename '956489/tftp-deploy-63p351ov/dtb/am335x-boneblack.dtb'.
456 00:04:36.873679 Load address: 0x88000000
457 00:04:36.882678 Loading: *################################################## 68.9 KiB
458 00:04:36.883152 4.8 MiB/s
459 00:04:36.883591 done
460 00:04:36.891066 Bytes transferred = 70568 (113a8 hex)
461 00:04:36.891801 Sending with 10 millisecond of delay
463 00:04:50.070109 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/956489/extract-nfsrootfs-sc4re3gr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
464 00:04:50.080926 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
465 00:04:50.081788 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/956489/extract-nfsrootfs-sc4re3gr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
466 00:04:50.082563 Sending with 10 millisecond of delay
468 00:04:52.422372 => bootz 0x82000000 0x83000000 0x88000000
469 00:04:52.433447 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
470 00:04:52.434192 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
471 00:04:52.435525 bootz 0x82000000 0x83000000 0x88000000
472 00:04:52.436116 Kernel image @ 0x82000000 [ 0x000000 - 0xaea200 ]
473 00:04:52.436681 ## Loading init Ramdisk from Legacy Image at 83000000 ...
474 00:04:52.440978 Image Name:
475 00:04:52.441343 Created: 2024-11-08 0:03:50 UTC
476 00:04:52.446589 Image Type: ARM Linux RAMDisk Image (uncompressed)
477 00:04:52.452089 Data Size: 14790578 Bytes = 14.1 MiB
478 00:04:52.452450 Load Address: 00000000
479 00:04:52.458253 Entry Point: 00000000
480 00:04:52.626722 Verifying Checksum ... OK
481 00:04:52.627543 ## Flattened Device Tree blob at 88000000
482 00:04:52.633068 Booting using the fdt blob at 0x88000000
483 00:04:52.633669 Working FDT set to 88000000
484 00:04:52.638638 Using Device Tree in place at 88000000, end 880143a7
485 00:04:52.643059 Working FDT set to 88000000
486 00:04:52.656606
487 00:04:52.657250 Starting kernel ...
488 00:04:52.657848
489 00:04:52.658982 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
490 00:04:52.659764 start: 2.4.4 auto-login-action (timeout 00:03:59) [common]
491 00:04:52.660387 Setting prompt string to ['Linux version [0-9]']
492 00:04:52.660998 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
493 00:04:52.661626 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
494 00:04:53.497456 [ 0.000000] Booting Linux on physical CPU 0x0
495 00:04:53.503301 start: 2.4.4.1 login-action (timeout 00:03:58) [common]
496 00:04:53.503802 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
497 00:04:53.504105 Setting prompt string to []
498 00:04:53.504388 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
499 00:04:53.504644 Using line separator: #'\n'#
500 00:04:53.504869 No login prompt set.
501 00:04:53.505106 Parsing kernel messages
502 00:04:53.505321 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
503 00:04:53.505758 [login-action] Waiting for messages, (timeout 00:03:58)
504 00:04:53.506048 Waiting using forced prompt support (timeout 00:01:59)
505 00:04:53.520174 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j367584-arm-gcc-12-multi-v7-defconfig-l6kxm) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Nov 7 23:30:07 UTC 2024
506 00:04:53.525958 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
507 00:04:53.531702 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
508 00:04:53.542994 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
509 00:04:53.548943 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
510 00:04:53.554562 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
511 00:04:53.555053 [ 0.000000] Memory policy: Data cache writeback
512 00:04:53.561251 [ 0.000000] efi: UEFI not found.
513 00:04:53.569996 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
514 00:04:53.570482 [ 0.000000] Zone ranges:
515 00:04:53.575693 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
516 00:04:53.581444 [ 0.000000] Normal empty
517 00:04:53.587172 [ 0.000000] HighMem empty
518 00:04:53.587658 [ 0.000000] Movable zone start for each node
519 00:04:53.592958 [ 0.000000] Early memory node ranges
520 00:04:53.599256 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
521 00:04:53.606531 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
522 00:04:53.631783 [ 0.000000] CPU: All CPU(s) started in SVC mode.
523 00:04:53.637378 [ 0.000000] AM335X ES2.0 (sgx neon)
524 00:04:53.649033 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
525 00:04:53.666666 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/956489/extract-nfsrootfs-sc4re3gr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
526 00:04:53.678156 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
527 00:04:53.683950 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
528 00:04:53.689637 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
529 00:04:53.699687 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
530 00:04:53.728845 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
531 00:04:53.734866 <6>[ 0.000000] trace event string verifier disabled
532 00:04:53.735199 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
533 00:04:53.740473 <6>[ 0.000000] rcu: RCU event tracing is enabled.
534 00:04:53.751889 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
535 00:04:53.757686 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
536 00:04:53.765113 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
537 00:04:53.779940 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
538 00:04:53.797008 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
539 00:04:53.803815 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
540 00:04:53.896306 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
541 00:04:53.907858 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
542 00:04:53.914582 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
543 00:04:53.927585 <6>[ 0.019142] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
544 00:04:53.934979 <6>[ 0.033957] Console: colour dummy device 80x30
545 00:04:53.941096 Matched prompt #6: WARNING:
546 00:04:53.941619 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
547 00:04:53.946542 <3>[ 0.038853] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
548 00:04:53.949311 <3>[ 0.045917] This ensures that you still see kernel messages. Please
549 00:04:53.955537 <3>[ 0.052643] update your kernel commandline.
550 00:04:53.995898 <6>[ 0.057255] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
551 00:04:54.001726 <6>[ 0.096149] CPU: Testing write buffer coherency: ok
552 00:04:54.007741 <6>[ 0.101516] CPU0: Spectre v2: using BPIALL workaround
553 00:04:54.008224 <6>[ 0.106982] pid_max: default: 32768 minimum: 301
554 00:04:54.019062 <6>[ 0.112177] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
555 00:04:54.026136 <6>[ 0.120000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
556 00:04:54.033230 <6>[ 0.129363] CPU0: thread -1, cpu 0, socket -1, mpidr 0
557 00:04:54.041657 <6>[ 0.136377] Setting up static identity map for 0x80300000 - 0x803000ac
558 00:04:54.047419 <6>[ 0.146024] rcu: Hierarchical SRCU implementation.
559 00:04:54.055079 <6>[ 0.151313] rcu: Max phase no-delay instances is 1000.
560 00:04:54.063541 <6>[ 0.162437] EFI services will not be available.
561 00:04:54.069421 <6>[ 0.167712] smp: Bringing up secondary CPUs ...
562 00:04:54.075084 <6>[ 0.172758] smp: Brought up 1 node, 1 CPU
563 00:04:54.080964 <6>[ 0.177158] SMP: Total of 1 processors activated (996.14 BogoMIPS).
564 00:04:54.086811 <6>[ 0.183925] CPU: All CPU(s) started in SVC mode.
565 00:04:54.107102 <6>[ 0.189110] Memory: 406000K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49048K reserved, 65536K cma-reserved, 0K highmem)
566 00:04:54.107611 <6>[ 0.205391] devtmpfs: initialized
567 00:04:54.129204 <6>[ 0.222348] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
568 00:04:54.140712 <6>[ 0.230931] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
569 00:04:54.146578 <6>[ 0.241385] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
570 00:04:54.157135 <6>[ 0.253703] pinctrl core: initialized pinctrl subsystem
571 00:04:54.166755 <6>[ 0.264320] DMI not present or invalid.
572 00:04:54.175031 <6>[ 0.270173] NET: Registered PF_NETLINK/PF_ROUTE protocol family
573 00:04:54.184491 <6>[ 0.279099] DMA: preallocated 256 KiB pool for atomic coherent allocations
574 00:04:54.199569 <6>[ 0.290643] thermal_sys: Registered thermal governor 'step_wise'
575 00:04:54.200068 <6>[ 0.290808] cpuidle: using governor menu
576 00:04:54.227180 <6>[ 0.326355] No ATAGs?
577 00:04:54.233350 <6>[ 0.328999] hw-breakpoint: debug architecture 0x4 unsupported.
578 00:04:54.243570 <6>[ 0.340981] Serial: AMBA PL011 UART driver
579 00:04:54.275811 <6>[ 0.374883] iommu: Default domain type: Translated
580 00:04:54.284872 <6>[ 0.380228] iommu: DMA domain TLB invalidation policy: strict mode
581 00:04:54.312158 <5>[ 0.410619] SCSI subsystem initialized
582 00:04:54.318069 <6>[ 0.415501] usbcore: registered new interface driver usbfs
583 00:04:54.323773 <6>[ 0.421528] usbcore: registered new interface driver hub
584 00:04:54.332376 <6>[ 0.427305] usbcore: registered new device driver usb
585 00:04:54.338230 <6>[ 0.433799] pps_core: LinuxPPS API ver. 1 registered
586 00:04:54.343997 <6>[ 0.439184] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
587 00:04:54.350072 <6>[ 0.448910] PTP clock support registered
588 00:04:54.355010 <6>[ 0.453368] EDAC MC: Ver: 3.0.0
589 00:04:54.402837 <6>[ 0.499379] scmi_core: SCMI protocol bus registered
590 00:04:54.417924 <6>[ 0.516726] vgaarb: loaded
591 00:04:54.439589 <6>[ 0.538791] clocksource: Switched to clocksource dmtimer
592 00:04:54.458019 <6>[ 0.556730] NET: Registered PF_INET protocol family
593 00:04:54.470475 <6>[ 0.562427] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
594 00:04:54.476360 <6>[ 0.571284] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
595 00:04:54.487627 <6>[ 0.580212] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
596 00:04:54.493451 <6>[ 0.588451] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
597 00:04:54.505049 <6>[ 0.596736] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
598 00:04:54.511080 <6>[ 0.604453] TCP: Hash tables configured (established 4096 bind 4096)
599 00:04:54.516735 <6>[ 0.611370] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
600 00:04:54.522611 <6>[ 0.618384] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
601 00:04:54.530185 <6>[ 0.625993] NET: Registered PF_UNIX/PF_LOCAL protocol family
602 00:04:54.616028 <6>[ 0.709567] RPC: Registered named UNIX socket transport module.
603 00:04:54.616414 <6>[ 0.715955] RPC: Registered udp transport module.
604 00:04:54.621871 <6>[ 0.721108] RPC: Registered tcp transport module.
605 00:04:54.627467 <6>[ 0.726214] RPC: Registered tcp-with-tls transport module.
606 00:04:54.640464 <6>[ 0.732144] RPC: Registered tcp NFSv4.1 backchannel transport module.
607 00:04:54.640773 <6>[ 0.739067] PCI: CLS 0 bytes, default 64
608 00:04:54.647702 <5>[ 0.744829] Initialise system trusted keyrings
609 00:04:54.668596 <6>[ 0.764876] Trying to unpack rootfs image as initramfs...
610 00:04:54.746167 <6>[ 0.839148] workingset: timestamp_bits=30 max_order=17 bucket_order=0
611 00:04:54.750999 <6>[ 0.846652] squashfs: version 4.0 (2009/01/31) Phillip Lougher
612 00:04:54.790562 <5>[ 0.889620] NFS: Registering the id_resolver key type
613 00:04:54.796294 <5>[ 0.895225] Key type id_resolver registered
614 00:04:54.802105 <5>[ 0.899877] Key type id_legacy registered
615 00:04:54.807814 <6>[ 0.904315] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
616 00:04:54.817386 <6>[ 0.911507] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
617 00:04:54.880206 <5>[ 0.979346] Key type asymmetric registered
618 00:04:54.886114 <5>[ 0.983869] Asymmetric key parser 'x509' registered
619 00:04:54.894450 <6>[ 0.989396] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
620 00:04:54.900223 <6>[ 0.997280] io scheduler mq-deadline registered
621 00:04:54.908975 <6>[ 1.002263] io scheduler kyber registered
622 00:04:54.909452 <6>[ 1.006717] io scheduler bfq registered
623 00:04:55.004142 <6>[ 1.099546] ledtrig-cpu: registered to indicate activity on CPUs
624 00:04:55.296859 <6>[ 1.392122] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
625 00:04:55.335147 <6>[ 1.433981] msm_serial: driver initialized
626 00:04:55.341072 <6>[ 1.438914] SuperH (H)SCI(F) driver initialized
627 00:04:55.347037 <6>[ 1.444067] STMicroelectronics ASC driver initialized
628 00:04:55.352216 <6>[ 1.449736] STM32 USART driver initialized
629 00:04:55.454426 <6>[ 1.552895] brd: module loaded
630 00:04:55.487989 <6>[ 1.586362] loop: module loaded
631 00:04:55.527886 <6>[ 1.626241] CAN device driver interface
632 00:04:55.534397 <6>[ 1.631393] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
633 00:04:55.540152 <6>[ 1.638276] e1000e: Intel(R) PRO/1000 Network Driver
634 00:04:55.545947 <6>[ 1.643724] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
635 00:04:55.551639 <6>[ 1.650159] igb: Intel(R) Gigabit Ethernet Network Driver
636 00:04:55.559927 <6>[ 1.655981] igb: Copyright (c) 2007-2014 Intel Corporation.
637 00:04:55.571665 <6>[ 1.665105] pegasus: Pegasus/Pegasus II USB Ethernet driver
638 00:04:55.577482 <6>[ 1.671287] usbcore: registered new interface driver pegasus
639 00:04:55.583282 <6>[ 1.677413] usbcore: registered new interface driver asix
640 00:04:55.589068 <6>[ 1.683294] usbcore: registered new interface driver ax88179_178a
641 00:04:55.594811 <6>[ 1.689883] usbcore: registered new interface driver cdc_ether
642 00:04:55.600554 <6>[ 1.696178] usbcore: registered new interface driver smsc75xx
643 00:04:55.606336 <6>[ 1.702404] usbcore: registered new interface driver smsc95xx
644 00:04:55.612208 <6>[ 1.708626] usbcore: registered new interface driver net1080
645 00:04:55.617955 <6>[ 1.714767] usbcore: registered new interface driver cdc_subset
646 00:04:55.623695 <6>[ 1.721173] usbcore: registered new interface driver zaurus
647 00:04:55.630439 <6>[ 1.727213] usbcore: registered new interface driver cdc_ncm
648 00:04:55.641036 <6>[ 1.736570] usbcore: registered new interface driver usb-storage
649 00:04:55.650367 <6>[ 1.747582] i2c_dev: i2c /dev entries driver
650 00:04:55.674604 <5>[ 1.765833] cpuidle: enable-method property 'ti,am3352' found operations
651 00:04:55.680524 <6>[ 1.775392] sdhci: Secure Digital Host Controller Interface driver
652 00:04:55.688370 <6>[ 1.782167] sdhci: Copyright(c) Pierre Ossman
653 00:04:55.695672 <6>[ 1.788626] Synopsys Designware Multimedia Card Interface Driver
654 00:04:55.700794 <6>[ 1.796665] sdhci-pltfm: SDHCI platform and OF driver helper
655 00:04:55.714997 <6>[ 1.806607] usbcore: registered new interface driver usbhid
656 00:04:55.715506 <6>[ 1.812728] usbhid: USB HID core driver
657 00:04:55.727958 <6>[ 1.824499] NET: Registered PF_INET6 protocol family
658 00:04:56.171362 <6>[ 2.270330] Segment Routing with IPv6
659 00:04:56.177073 <6>[ 2.274481] In-situ OAM (IOAM) with IPv6
660 00:04:56.183728 <6>[ 2.279035] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
661 00:04:56.189518 <6>[ 2.286305] NET: Registered PF_PACKET protocol family
662 00:04:56.195341 <6>[ 2.291875] can: controller area network core
663 00:04:56.201199 <6>[ 2.296698] NET: Registered PF_CAN protocol family
664 00:04:56.201716 <6>[ 2.301925] can: raw protocol
665 00:04:56.206888 <6>[ 2.305252] can: broadcast manager protocol
666 00:04:56.213363 <6>[ 2.309845] can: netlink gateway - max_hops=1
667 00:04:56.219520 <5>[ 2.315325] Key type dns_resolver registered
668 00:04:56.225758 <6>[ 2.320401] ThumbEE CPU extension supported.
669 00:04:56.226465 <5>[ 2.325103] Registering SWP/SWPB emulation handler
670 00:04:56.234573 <3>[ 2.330815] omap_voltage_late_init: Voltage driver support not added
671 00:04:56.422435 <5>[ 2.519268] Loading compiled-in X.509 certificates
672 00:04:56.551531 <6>[ 2.637906] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
673 00:04:56.558848 <6>[ 2.654591] pinctrl-single 44e10800.pinmux: 142 pins, size 568
674 00:04:56.585104 <3>[ 2.678197] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
675 00:04:56.785036 <3>[ 2.878165] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
676 00:04:56.981764 <6>[ 3.079196] OMAP GPIO hardware version 0.1
677 00:04:57.002259 <6>[ 3.097791] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
678 00:04:57.096281 <4>[ 3.191564] at24 2-0054: supply vcc not found, using dummy regulator
679 00:04:57.134404 <4>[ 3.229592] at24 2-0055: supply vcc not found, using dummy regulator
680 00:04:57.187689 <4>[ 3.283010] at24 2-0056: supply vcc not found, using dummy regulator
681 00:04:57.227453 <4>[ 3.322557] at24 2-0057: supply vcc not found, using dummy regulator
682 00:04:57.268951 <6>[ 3.364972] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
683 00:04:57.349703 <3>[ 3.441691] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
684 00:04:57.374214 <6>[ 3.462548] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
685 00:04:57.394597 <4>[ 3.488585] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
686 00:04:57.415542 <4>[ 3.509537] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
687 00:04:57.553680 <6>[ 3.649069] omap_rng 48310000.rng: Random Number Generator ver. 20
688 00:04:57.577141 <5>[ 3.675352] random: crng init done
689 00:04:57.625242 <6>[ 3.719090] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
690 00:04:57.693367 <6>[ 3.790952] Freeing initrd memory: 14444K
691 00:04:57.748241 <6>[ 3.841219] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
692 00:04:57.754067 <6>[ 3.851557] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
693 00:04:57.762176 <6>[ 3.858891] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
694 00:04:57.773689 <6>[ 3.866338] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
695 00:04:57.785238 <6>[ 3.874477] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
696 00:04:57.792655 <6>[ 3.886111] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
697 00:04:57.803641 <5>[ 3.895142] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
698 00:04:57.831240 <3>[ 3.924762] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
699 00:04:57.837048 <6>[ 3.933359] edma 49000000.dma: TI EDMA DMA engine driver
700 00:04:57.907791 <3>[ 4.000610] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
701 00:04:57.922530 <6>[ 4.014950] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
702 00:04:57.935390 <3>[ 4.032003] l3-aon-clkctrl:0000:0: failed to disable
703 00:04:57.983625 <6>[ 4.077080] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
704 00:04:57.989514 <6>[ 4.086593] printk: legacy console [ttyS0] enabled
705 00:04:57.995070 <6>[ 4.086593] printk: legacy console [ttyS0] enabled
706 00:04:58.000770 <6>[ 4.096950] printk: legacy bootconsole [omap8250] disabled
707 00:04:58.006653 <6>[ 4.096950] printk: legacy bootconsole [omap8250] disabled
708 00:04:58.047135 <4>[ 4.139579] tps65217-pmic: Failed to locate of_node [id: -1]
709 00:04:58.050775 <4>[ 4.146998] tps65217-bl: Failed to locate of_node [id: -1]
710 00:04:58.067046 <6>[ 4.166499] tps65217 0-0024: TPS65217 ID 0xe version 1.2
711 00:04:58.085465 <6>[ 4.173432] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
712 00:04:58.097111 <6>[ 4.187112] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
713 00:04:58.102839 <6>[ 4.199025] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
714 00:04:58.125059 <6>[ 4.218965] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
715 00:04:58.130986 <6>[ 4.228026] sdhci-omap 48060000.mmc: Got CD GPIO
716 00:04:58.139042 <4>[ 4.233215] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
717 00:04:58.153838 <4>[ 4.246672] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
718 00:04:58.160421 <4>[ 4.255630] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
719 00:04:58.170202 <4>[ 4.264444] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
720 00:04:58.268623 <6>[ 4.363502] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
721 00:04:58.316026 <6>[ 4.409576] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
722 00:04:58.322602 <6>[ 4.418035] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
723 00:04:58.331749 <6>[ 4.426999] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
724 00:04:58.400809 <6>[ 4.497075] mmc1: new high speed MMC card at address 0001
725 00:04:58.408692 <6>[ 4.505931] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
726 00:04:58.424593 <6>[ 4.521302] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
727 00:04:58.431335 <6>[ 4.529102] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
728 00:04:58.444610 <6>[ 4.535528] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
729 00:04:58.451956 <6>[ 4.548494] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
730 00:04:58.508654 <6>[ 4.598348] mmc0: new high speed SDHC card at address aaaa
731 00:04:58.509185 <6>[ 4.605987] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
732 00:04:58.521267 <6>[ 4.618458] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
733 00:05:00.596400 <6>[ 6.689836] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
734 00:05:00.719767 <5>[ 6.718808] Sending DHCP requests ., OK
735 00:05:00.731005 <6>[ 6.823274] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
736 00:05:00.731468 <6>[ 6.831357] IP-Config: Complete:
737 00:05:00.745272 <6>[ 6.834896] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
738 00:05:00.751000 <6>[ 6.845337] host=192.168.6.8, domain=, nis-domain=(none)
739 00:05:00.754330 <6>[ 6.851462] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
740 00:05:00.760958 <6>[ 6.851497] nameserver0=10.255.253.1
741 00:05:00.766935 <6>[ 6.864058] clk: Disabling unused clocks
742 00:05:00.772106 <6>[ 6.868661] PM: genpd: Disabling unused power domains
743 00:05:00.791122 <6>[ 6.886707] Freeing unused kernel image (initmem) memory: 2048K
744 00:05:00.798117 <6>[ 6.896210] Run /init as init process
745 00:05:00.824393 Loading, please wait...
746 00:05:00.899522 Starting systemd-udevd version 252.22-1~deb12u1
747 00:05:03.898344 <4>[ 9.990494] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 00:05:04.093720 <4>[ 10.185964] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 00:05:04.242929 <6>[ 10.342573] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
750 00:05:04.253617 <6>[ 10.348245] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
751 00:05:04.492191 <6>[ 10.590382] hub 1-0:1.0: USB hub found
752 00:05:04.542823 <6>[ 10.640868] hub 1-0:1.0: 1 port detected
753 00:05:04.654333 <6>[ 10.752191] tda998x 0-0070: found TDA19988
754 00:05:07.704748 Begin: Loading essential drivers ... done.
755 00:05:07.709754 Begin: Running /scripts/init-premount ... done.
756 00:05:07.715290 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
757 00:05:07.725522 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
758 00:05:07.734755 Device /sys/class/net/eth0 found
759 00:05:07.735208 done.
760 00:05:07.794004 Begin: Waiting up to 180 secs for any network device to become available ... done.
761 00:05:07.872645 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
762 00:05:08.038192 IP-Config: eth0 guessed broadcast address 192.168.6.255
763 00:05:08.043569 IP-Config: eth0 complete (dhcp from 192.168.6.1):
764 00:05:08.049142 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
765 00:05:08.060796 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
766 00:05:08.061433 rootserver: 192.168.6.1 rootpath:
767 00:05:08.063531 filename :
768 00:05:08.123140 done.
769 00:05:08.138009 Begin: Running /scripts/nfs-bottom ... done.
770 00:05:08.214011 Begin: Running /scripts/init-bottom ... done.
771 00:05:09.642972 <30>[ 15.738211] systemd[1]: System time before build time, advancing clock.
772 00:05:09.814307 <30>[ 15.884093] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
773 00:05:09.823318 <30>[ 15.920706] systemd[1]: Detected architecture arm.
774 00:05:09.834700
775 00:05:09.835345 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
776 00:05:09.835924
777 00:05:09.863327 <30>[ 15.959124] systemd[1]: Hostname set to <debian-bookworm-armhf>.
778 00:05:12.000974 <30>[ 18.095769] systemd[1]: Queued start job for default target graphical.target.
779 00:05:12.018115 <30>[ 18.110900] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
780 00:05:12.025744 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
781 00:05:12.051130 <30>[ 18.145228] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
782 00:05:12.064099 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
783 00:05:12.089097 <30>[ 18.181235] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
784 00:05:12.096637 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
785 00:05:12.118183 <30>[ 18.211173] systemd[1]: Created slice user.slice - User and Session Slice.
786 00:05:12.124869 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
787 00:05:12.150652 <30>[ 18.241554] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
788 00:05:12.163586 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
789 00:05:12.187474 <30>[ 18.279708] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
790 00:05:12.198596 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
791 00:05:12.225446 <30>[ 18.310009] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
792 00:05:12.239107 <30>[ 18.332154] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
793 00:05:12.243830 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
794 00:05:12.265727 <30>[ 18.359340] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
795 00:05:12.273158 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
796 00:05:12.296505 <30>[ 18.389666] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
797 00:05:12.304428 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
798 00:05:12.326303 <30>[ 18.419883] systemd[1]: Reached target paths.target - Path Units.
799 00:05:12.330609 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
800 00:05:12.356063 <30>[ 18.449594] systemd[1]: Reached target remote-fs.target - Remote File Systems.
801 00:05:12.363425 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
802 00:05:12.385906 <30>[ 18.479407] systemd[1]: Reached target slices.target - Slice Units.
803 00:05:12.390413 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
804 00:05:12.416122 <30>[ 18.509671] systemd[1]: Reached target swap.target - Swaps.
805 00:05:12.419233 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
806 00:05:12.446144 <30>[ 18.539516] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
807 00:05:12.454178 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
808 00:05:12.477205 <30>[ 18.570439] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
809 00:05:12.485462 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
810 00:05:12.563529 <30>[ 18.653048] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
811 00:05:12.577196 <30>[ 18.670613] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
812 00:05:12.585156 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
813 00:05:12.609073 <30>[ 18.701558] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
814 00:05:12.615473 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
815 00:05:12.638620 <30>[ 18.731953] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
816 00:05:12.646422 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
817 00:05:12.671524 <30>[ 18.763810] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
818 00:05:12.677199 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
819 00:05:12.705496 <30>[ 18.800514] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
820 00:05:12.716480 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
821 00:05:12.744907 <30>[ 18.832344] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
822 00:05:12.765641 <30>[ 18.852890] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
823 00:05:12.804742 <30>[ 18.899946] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
824 00:05:12.819670 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
825 00:05:12.852292 <30>[ 18.947343] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
826 00:05:12.882191 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
827 00:05:12.947055 <30>[ 19.041081] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
828 00:05:12.983790 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
829 00:05:13.036705 <30>[ 19.130410] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
830 00:05:13.066068 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
831 00:05:13.116601 <30>[ 19.210666] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
832 00:05:13.135365 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
833 00:05:13.173382 <30>[ 19.268081] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
834 00:05:13.204748 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
835 00:05:13.259157 <30>[ 19.353510] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
836 00:05:13.285486 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
837 00:05:13.336295 <30>[ 19.430694] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
838 00:05:13.356107 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
839 00:05:13.385191 <30>[ 19.480002] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
840 00:05:13.415002 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
841 00:05:13.443357 <28>[ 19.531218] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
842 00:05:13.450787 <28>[ 19.545440] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
843 00:05:13.495294 <30>[ 19.590158] systemd[1]: Starting systemd-journald.service - Journal Service...
844 00:05:13.512854 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
845 00:05:13.577763 <30>[ 19.672010] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
846 00:05:13.601194 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
847 00:05:13.655789 <30>[ 19.750176] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
848 00:05:13.708687 Starting [0;1;39msystemd-network-g… units from Kernel command line...
849 00:05:13.788327 <30>[ 19.882161] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
850 00:05:13.839336 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
851 00:05:13.895554 <30>[ 19.990227] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
852 00:05:13.955343 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
853 00:05:14.016346 <30>[ 20.110902] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
854 00:05:14.055756 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
855 00:05:14.076130 <30>[ 20.170562] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
856 00:05:14.102418 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
857 00:05:14.120006 <30>[ 20.213370] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
858 00:05:14.149585 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
859 00:05:14.275963 <30>[ 20.371068] systemd[1]: modprobe@configfs.service: Deactivated successfully.
860 00:05:14.315701 <30>[ 20.409653] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
861 00:05:14.343884 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
862 00:05:14.375576 <30>[ 20.471691] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
863 00:05:14.406118 <30>[ 20.500564] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
864 00:05:14.427229 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
865 00:05:14.446856 <30>[ 20.540553] systemd[1]: Started systemd-journald.service - Journal Service.
866 00:05:14.452732 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
867 00:05:14.487623 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
868 00:05:14.516312 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
869 00:05:14.541302 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
870 00:05:14.576923 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
871 00:05:14.607266 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
872 00:05:14.628074 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
873 00:05:14.656042 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
874 00:05:14.680348 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
875 00:05:14.746341 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
876 00:05:14.820011 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
877 00:05:14.875443 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
878 00:05:14.931040 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
879 00:05:15.009793 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
880 00:05:15.165793 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
881 00:05:15.216188 <46>[ 21.310907] systemd-journald[164]: Received client request to flush runtime journal.
882 00:05:15.304400 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
883 00:05:15.803560 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
884 00:05:16.485511 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
885 00:05:16.538101 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
886 00:05:16.847883 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
887 00:05:17.079829 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
888 00:05:17.107960 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
889 00:05:17.125443 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
890 00:05:17.208179 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
891 00:05:17.269510 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
892 00:05:18.218124 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
893 00:05:18.278353 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
894 00:05:18.386481 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
895 00:05:18.457322 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
896 00:05:18.519124 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
897 00:05:20.240387 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
898 00:05:20.975858 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
899 00:05:21.338054 <5>[ 27.432445] cfg80211: Loading compiled-in X.509 certificates for regulatory database
900 00:05:21.828433 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
901 00:05:22.314330 <5>[ 28.411015] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
902 00:05:22.392010 <5>[ 28.487082] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
903 00:05:22.408172 <4>[ 28.502520] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
904 00:05:22.414013 <6>[ 28.511638] cfg80211: failed to load regulatory.db
905 00:05:22.589575 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
906 00:05:22.796223 <46>[ 28.881614] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
907 00:05:23.058362 <46>[ 29.146717] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
908 00:05:23.787651 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
909 00:05:32.612883 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
910 00:05:32.641492 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
911 00:05:32.667696 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
912 00:05:32.687938 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
913 00:05:32.745860 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
914 00:05:32.795548 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
915 00:05:32.847619 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
916 00:05:32.893049 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
917 00:05:32.953087 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
918 00:05:32.981945 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
919 00:05:33.010684 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
920 00:05:33.050211 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
921 00:05:33.079320 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
922 00:05:33.125639 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
923 00:05:33.148753 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
924 00:05:33.190202 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
925 00:05:33.226869 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
926 00:05:33.250896 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
927 00:05:33.277447 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
928 00:05:33.296195 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
929 00:05:33.331680 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
930 00:05:33.356205 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
931 00:05:33.378437 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
932 00:05:33.445993 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
933 00:05:33.504702 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
934 00:05:33.623820 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
935 00:05:33.727204 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
936 00:05:33.764982 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
937 00:05:33.810250 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
938 00:05:33.838754 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
939 00:05:34.027523 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
940 00:05:34.056074 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
941 00:05:34.165251 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
942 00:05:34.226829 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
943 00:05:34.244953 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
944 00:05:34.390471 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
945 00:05:34.750315 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
946 00:05:34.814700 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
947 00:05:34.839303 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
948 00:05:34.929380 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
949 00:05:35.104375 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
950 00:05:35.244627
951 00:05:35.245182 Debian GNU/Linux 12worm-armhf login: root (automatic login)
952 00:05:35.247191
953 00:05:35.573057 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Thu Nov 7 23:30:07 UTC 2024 armv7l
954 00:05:35.573645
955 00:05:35.578592 The programs included with the Debian GNU/Linux system are free software;
956 00:05:35.582274 the exact distribution terms for each program are described in the
957 00:05:35.587633 individual files in /usr/share/doc/*/copyright.
958 00:05:35.588124
959 00:05:35.593095 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
960 00:05:35.597952 permitted by applicable law.
961 00:05:40.645838 Unable to match end of the kernel message
963 00:05:40.646717 Setting prompt string to ['/ #']
964 00:05:40.647019 end: 2.4.4.1 login-action (duration 00:00:47) [common]
966 00:05:40.647712 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
967 00:05:40.647993 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
968 00:05:40.648225 Setting prompt string to ['/ #']
969 00:05:40.648430 Forcing a shell prompt, looking for ['/ #']
971 00:05:40.698953 / #
972 00:05:40.699564 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
973 00:05:40.700084 Waiting using forced prompt support (timeout 00:02:30)
974 00:05:40.703353
975 00:05:40.713022 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
976 00:05:40.713611 start: 2.4.6 export-device-env (timeout 00:03:10) [common]
977 00:05:40.714147 Sending with 10 millisecond of delay
979 00:05:45.702826 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/956489/extract-nfsrootfs-sc4re3gr'
980 00:05:45.713761 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/956489/extract-nfsrootfs-sc4re3gr'
981 00:05:45.714606 Sending with 10 millisecond of delay
983 00:05:47.812683 / # export NFS_SERVER_IP='192.168.6.3'
984 00:05:47.823575 export NFS_SERVER_IP='192.168.6.3'
985 00:05:47.824490 end: 2.4.6 export-device-env (duration 00:00:07) [common]
986 00:05:47.825071 end: 2.4 uboot-commands (duration 00:01:57) [common]
987 00:05:47.825658 end: 2 uboot-action (duration 00:01:57) [common]
988 00:05:47.826268 start: 3 lava-test-retry (timeout 00:06:53) [common]
989 00:05:47.826850 start: 3.1 lava-test-shell (timeout 00:06:53) [common]
990 00:05:47.827308 Using namespace: common
992 00:05:47.928431 / # #
993 00:05:47.929260 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
994 00:05:47.933914 #
995 00:05:47.940068 Using /lava-956489
997 00:05:48.041221 / # export SHELL=/bin/bash
998 00:05:48.047974 export SHELL=/bin/bash
1000 00:05:48.155801 / # . /lava-956489/environment
1001 00:05:48.160676 . /lava-956489/environment
1003 00:05:48.273854 / # /lava-956489/bin/lava-test-runner /lava-956489/0
1004 00:05:48.274527 Test shell timeout: 10s (minimum of the action and connection timeout)
1005 00:05:48.278317 /lava-956489/bin/lava-test-runner /lava-956489/0
1006 00:05:48.644284 + export TESTRUN_ID=0_timesync-off
1007 00:05:48.652386 + TESTRUN_ID=0_timesync-off
1008 00:05:48.652893 + cd /lava-956489/0/tests/0_timesync-off
1009 00:05:48.653311 ++ cat uuid
1010 00:05:48.667235 + UUID=956489_1.6.2.4.1
1011 00:05:48.667738 + set +x
1012 00:05:48.675020 <LAVA_SIGNAL_STARTRUN 0_timesync-off 956489_1.6.2.4.1>
1013 00:05:48.675337 + systemctl stop systemd-timesyncd
1014 00:05:48.676003 Received signal: <STARTRUN> 0_timesync-off 956489_1.6.2.4.1
1015 00:05:48.676540 Starting test lava.0_timesync-off (956489_1.6.2.4.1)
1016 00:05:48.676853 Skipping test definition patterns.
1017 00:05:48.982542 + set +x
1018 00:05:48.983116 <LAVA_SIGNAL_ENDRUN 0_timesync-off 956489_1.6.2.4.1>
1019 00:05:48.983789 Received signal: <ENDRUN> 0_timesync-off 956489_1.6.2.4.1
1020 00:05:48.984280 Ending use of test pattern.
1021 00:05:48.984683 Ending test lava.0_timesync-off (956489_1.6.2.4.1), duration 0.31
1023 00:05:49.157266 + export TESTRUN_ID=1_kselftest-dt
1024 00:05:49.165230 + TESTRUN_ID=1_kselftest-dt
1025 00:05:49.165737 + cd /lava-956489/0/tests/1_kselftest-dt
1026 00:05:49.166179 ++ cat uuid
1027 00:05:49.187214 + UUID=956489_1.6.2.4.5
1028 00:05:49.187716 + set +x
1029 00:05:49.192925 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 956489_1.6.2.4.5>
1030 00:05:49.193424 + cd ./automated/linux/kselftest/
1031 00:05:49.194113 Received signal: <STARTRUN> 1_kselftest-dt 956489_1.6.2.4.5
1032 00:05:49.194547 Starting test lava.1_kselftest-dt (956489_1.6.2.4.5)
1033 00:05:49.195021 Skipping test definition patterns.
1034 00:05:49.221007 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-164-gbfc64d9b7e8c/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1035 00:05:49.318332 INFO: install_deps skipped
1036 00:05:49.902239 --2024-11-08 00:05:49-- http://storage.kernelci.org/mainline/master/v6.12-rc6-164-gbfc64d9b7e8c/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1037 00:05:49.928317 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1038 00:05:50.070630 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1039 00:05:50.210556 HTTP request sent, awaiting response... 200 OK
1040 00:05:50.211071 Length: 4108340 (3.9M) [application/octet-stream]
1041 00:05:50.216034 Saving to: 'kselftest_armhf.tar.gz'
1042 00:05:50.216516
1043 00:05:52.018551
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 44.73K 163KB/s
kselftest_armhf.tar 5%[> ] 208.82K 371KB/s
kselftest_armhf.tar 20%[===> ] 813.51K 960KB/s
kselftest_armhf.tar 32%[=====> ] 1.28M 1.22MB/s
kselftest_armhf.tar 52%[=========> ] 2.05M 1.55MB/s
kselftest_armhf.tar 80%[===============> ] 3.14M 2.03MB/s
kselftest_armhf.tar 98%[==================> ] 3.87M 2.22MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 2.17MB/s in 1.8s
1044 00:05:52.019187
1045 00:05:52.668954 2024-11-08 00:05:51 (2.17 MB/s) - 'kselftest_armhf.tar.gz' saved [4108340/4108340]
1046 00:05:52.669595
1047 00:06:07.167729 skiplist:
1048 00:06:07.168130 ========================================
1049 00:06:07.172882 ========================================
1050 00:06:07.289351 dt:test_unprobed_devices.sh
1051 00:06:07.323926 ============== Tests to run ===============
1052 00:06:07.330962 dt:test_unprobed_devices.sh
1053 00:06:07.333959 ===========End Tests to run ===============
1054 00:06:07.342802 shardfile-dt pass
1055 00:06:07.578946 <12>[ 73.678299] kselftest: Running tests in dt
1056 00:06:07.606974 TAP version 13
1057 00:06:07.629883 1..1
1058 00:06:07.682665 # timeout set to 45
1059 00:06:07.683030 # selftests: dt: test_unprobed_devices.sh
1060 00:06:08.555975 # TAP version 13
1061 00:06:33.193430 # 1..257
1062 00:06:33.365260 # ok 1 / # SKIP
1063 00:06:33.392308 # ok 2 /clk_mcasp0
1064 00:06:33.464212 # ok 3 /clk_mcasp0_fixed # SKIP
1065 00:06:33.532836 # ok 4 /cpus/cpu@0 # SKIP
1066 00:06:33.597632 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1067 00:06:33.617909 # ok 6 /fixedregulator0
1068 00:06:33.641668 # ok 7 /leds
1069 00:06:33.659190 # ok 8 /ocp
1070 00:06:33.682563 # ok 9 /ocp/interconnect@44c00000
1071 00:06:33.706444 # ok 10 /ocp/interconnect@44c00000/segment@0
1072 00:06:33.733310 # ok 11 /ocp/interconnect@44c00000/segment@100000
1073 00:06:33.756499 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1074 00:06:33.826375 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1075 00:06:33.847157 # ok 14 /ocp/interconnect@44c00000/segment@200000
1076 00:06:33.866080 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1077 00:06:33.975865 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1078 00:06:34.042487 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1079 00:06:34.113749 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1080 00:06:34.183531 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1081 00:06:34.258123 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1082 00:06:34.330027 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1083 00:06:34.399813 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1084 00:06:34.471361 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1085 00:06:34.541135 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1086 00:06:34.612614 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1087 00:06:34.677729 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1088 00:06:34.752772 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1089 00:06:34.818744 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1090 00:06:34.889522 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1091 00:06:34.958191 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1092 00:06:35.030594 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1093 00:06:35.099691 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1094 00:06:35.172098 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1095 00:06:35.244539 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1096 00:06:35.314947 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1097 00:06:35.383377 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1098 00:06:35.455880 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1099 00:06:35.527126 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1100 00:06:35.597378 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1101 00:06:35.667715 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1102 00:06:35.738783 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1103 00:06:35.810143 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1104 00:06:35.882684 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1105 00:06:35.955645 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1106 00:06:36.025488 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1107 00:06:36.097109 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1108 00:06:36.167795 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1109 00:06:36.237989 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1110 00:06:36.309540 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1111 00:06:36.380387 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1112 00:06:36.452118 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1113 00:06:36.523177 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1114 00:06:36.596783 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1115 00:06:36.670271 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1116 00:06:36.741322 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1117 00:06:36.812470 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1118 00:06:36.879618 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1119 00:06:36.949138 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1120 00:06:37.020220 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1121 00:06:37.091502 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1122 00:06:37.162180 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1123 00:06:37.236474 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1124 00:06:37.308618 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1125 00:06:37.382020 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1126 00:06:37.452795 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1127 00:06:37.522675 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1128 00:06:37.591295 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1129 00:06:37.662064 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1130 00:06:37.734633 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1131 00:06:37.805058 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1132 00:06:37.876662 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1133 00:06:37.947256 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1134 00:06:38.018189 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1135 00:06:38.089059 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1136 00:06:38.160152 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1137 00:06:38.237435 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1138 00:06:38.304983 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1139 00:06:38.374830 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1140 00:06:38.449835 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1141 00:06:38.520487 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1142 00:06:38.591461 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1143 00:06:38.662002 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1144 00:06:38.732079 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1145 00:06:38.802716 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1146 00:06:38.869680 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1147 00:06:38.940550 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1148 00:06:39.011343 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1149 00:06:39.082216 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1150 00:06:39.154781 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1151 00:06:39.230626 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1152 00:06:39.299776 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1153 00:06:39.372077 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1154 00:06:39.442425 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1155 00:06:39.509711 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1156 00:06:39.529833 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1157 00:06:39.552905 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1158 00:06:39.581427 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1159 00:06:39.601265 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1160 00:06:39.628463 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1161 00:06:39.651301 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1162 00:06:39.675205 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1163 00:06:39.698180 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1164 00:06:39.801229 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1165 00:06:39.824610 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1166 00:06:39.846876 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1167 00:06:39.869897 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1168 00:06:39.974032 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1169 00:06:40.048068 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1170 00:06:40.118198 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1171 00:06:40.188288 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1172 00:06:40.259989 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1173 00:06:40.331222 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1174 00:06:40.402370 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1175 00:06:40.473260 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1176 00:06:40.546553 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1177 00:06:40.616410 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1178 00:06:40.691834 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1179 00:06:40.757614 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1180 00:06:40.828277 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1181 00:06:40.901376 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1182 00:06:40.975386 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1183 00:06:41.052273 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1184 00:06:41.069460 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1185 00:06:41.138275 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1186 00:06:41.206922 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1187 00:06:41.278680 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1188 00:06:41.303286 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1189 00:06:41.370212 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1190 00:06:41.393489 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1191 00:06:41.463704 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1192 00:06:41.485399 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1193 00:06:41.509155 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1194 00:06:41.536094 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1195 00:06:41.560444 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1196 00:06:41.582389 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1197 00:06:41.600980 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1198 00:06:41.628028 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1199 00:06:41.701087 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1200 00:06:41.721569 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1201 00:06:41.745482 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1202 00:06:41.815739 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1203 00:06:41.885861 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1204 00:06:41.906213 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1205 00:06:42.004700 # not ok 144 /ocp/interconnect@47c00000
1206 00:06:42.078747 # not ok 145 /ocp/interconnect@47c00000/segment@0
1207 00:06:42.096887 # ok 146 /ocp/interconnect@48000000
1208 00:06:42.120139 # ok 147 /ocp/interconnect@48000000/segment@0
1209 00:06:42.143149 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1210 00:06:42.166752 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1211 00:06:42.192278 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1212 00:06:42.212148 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1213 00:06:42.235465 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1214 00:06:42.259037 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1215 00:06:42.285875 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1216 00:06:42.356679 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1217 00:06:42.427951 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1218 00:06:42.449262 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1219 00:06:42.470690 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1220 00:06:42.495788 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1221 00:06:42.519395 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1222 00:06:42.539950 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1223 00:06:42.561437 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1224 00:06:42.587844 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1225 00:06:42.612444 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1226 00:06:42.634325 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1227 00:06:42.654767 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1228 00:06:42.681666 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1229 00:06:42.700731 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1230 00:06:42.724337 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1231 00:06:42.747009 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1232 00:06:42.770374 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1233 00:06:42.794677 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1234 00:06:42.819939 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1235 00:06:42.846532 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1236 00:06:42.861130 # ok 175 /ocp/interconnect@48000000/segment@100000
1237 00:06:42.890306 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1238 00:06:42.910677 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1239 00:06:42.987221 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1240 00:06:43.055695 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1241 00:06:43.125206 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1242 00:06:43.197154 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1243 00:06:43.266396 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1244 00:06:43.337573 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1245 00:06:43.406751 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1246 00:06:43.480064 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1247 00:06:43.498512 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1248 00:06:43.522597 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1249 00:06:43.545468 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1250 00:06:43.568403 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1251 00:06:43.591219 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1252 00:06:43.619096 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1253 00:06:43.640341 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1254 00:06:43.666938 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1255 00:06:43.689237 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1256 00:06:43.709865 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1257 00:06:43.731631 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1258 00:06:43.759330 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1259 00:06:43.777843 # ok 198 /ocp/interconnect@48000000/segment@200000
1260 00:06:43.805376 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1261 00:06:43.871330 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1262 00:06:43.897042 # ok 201 /ocp/interconnect@48000000/segment@300000
1263 00:06:43.919037 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1264 00:06:43.940881 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1265 00:06:43.968088 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1266 00:06:43.989427 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1267 00:06:44.018625 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1268 00:06:44.039658 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1269 00:06:44.107547 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1270 00:06:44.125709 # ok 209 /ocp/interconnect@4a000000
1271 00:06:44.149363 # ok 210 /ocp/interconnect@4a000000/segment@0
1272 00:06:44.178584 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1273 00:06:44.200875 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1274 00:06:44.223876 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1275 00:06:44.244960 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1276 00:06:44.315948 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1277 00:06:44.419747 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1278 00:06:44.493525 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1279 00:06:44.594355 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1280 00:06:44.664062 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1281 00:06:44.732080 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1282 00:06:44.828116 # not ok 221 /ocp/interconnect@4b140000
1283 00:06:44.900960 # not ok 222 /ocp/interconnect@4b140000/segment@0
1284 00:06:44.974724 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1285 00:06:44.995833 # ok 224 /ocp/target-module@40300000
1286 00:06:45.014609 # ok 225 /ocp/target-module@40300000/sram@0
1287 00:06:45.090276 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1288 00:06:45.457272 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1289 00:06:45.457995 # ok 228 /ocp/target-module@47400000
1290 00:06:45.458266 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1291 00:06:45.458938 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1292 00:06:45.459357 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1293 00:06:45.459723 # ok 232 /ocp/target-module@47400000/usb@1400
1294 00:06:45.460090 # ok 233 /ocp/target-module@47400000/usb@1800
1295 00:06:45.460451 # ok 234 /ocp/target-module@47810000
1296 00:06:45.460814 # ok 235 /ocp/target-module@49000000
1297 00:06:45.461079 # ok 236 /ocp/target-module@49000000/dma@0
1298 00:06:45.461306 # ok 237 /ocp/target-module@49800000
1299 00:06:45.461520 # ok 238 /ocp/target-module@49800000/dma@0
1300 00:06:45.461731 # ok 239 /ocp/target-module@49900000
1301 00:06:45.464673 # ok 240 /ocp/target-module@49900000/dma@0
1302 00:06:45.465137 # ok 241 /ocp/target-module@49a00000
1303 00:06:45.487773 # ok 242 /ocp/target-module@49a00000/dma@0
1304 00:06:45.513295 # ok 243 /ocp/target-module@4c000000
1305 00:06:45.583432 # not ok 244 /ocp/target-module@4c000000/emif@0
1306 00:06:45.605097 # ok 245 /ocp/target-module@50000000
1307 00:06:45.627549 # ok 246 /ocp/target-module@53100000
1308 00:06:45.698416 # not ok 247 /ocp/target-module@53100000/sham@0
1309 00:06:45.720818 # ok 248 /ocp/target-module@53500000
1310 00:06:45.791151 # not ok 249 /ocp/target-module@53500000/aes@0
1311 00:06:45.810236 # ok 250 /ocp/target-module@56000000
1312 00:06:45.917770 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1313 00:06:45.983135 # ok 252 /opp-table # SKIP
1314 00:06:46.056139 # ok 253 /soc # SKIP
1315 00:06:46.072691 # ok 254 /sound
1316 00:06:46.096809 # ok 255 /target-module@4b000000
1317 00:06:46.124404 # ok 256 /target-module@4b000000/target-module@140000
1318 00:06:46.141227 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1319 00:06:46.149402 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1320 00:06:46.157179 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1321 00:06:48.239514 dt_test_unprobed_devices_sh_ skip
1322 00:06:48.244753 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1323 00:06:48.250340 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1324 00:06:48.250820 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1325 00:06:48.259589 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1326 00:06:48.260063 dt_test_unprobed_devices_sh_fixedregulator0 pass
1327 00:06:48.265418 dt_test_unprobed_devices_sh_leds pass
1328 00:06:48.270832 dt_test_unprobed_devices_sh_ocp pass
1329 00:06:48.274577 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1330 00:06:48.279518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1331 00:06:48.285029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1332 00:06:48.295233 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1333 00:06:48.300616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1334 00:06:48.311679 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1335 00:06:48.315829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1336 00:06:48.326744 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1337 00:06:48.332382 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1338 00:06:48.347143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1339 00:06:48.352759 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1340 00:06:48.363940 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1341 00:06:48.375144 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1342 00:06:48.386349 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1343 00:06:48.397687 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1344 00:06:48.403298 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1345 00:06:48.414504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1346 00:06:48.425671 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1347 00:06:48.436882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1348 00:06:48.448076 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1349 00:06:48.453693 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1350 00:06:48.464882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1351 00:06:48.476061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1352 00:06:48.487242 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1353 00:06:48.492916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1354 00:06:48.504004 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1355 00:06:48.515251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1356 00:06:48.526326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1357 00:06:48.531935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1358 00:06:48.543190 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1359 00:06:48.554391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1360 00:06:48.565553 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1361 00:06:48.576777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1362 00:06:48.587994 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1363 00:06:48.599199 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1364 00:06:48.610391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1365 00:06:48.621548 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1366 00:06:48.632761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1367 00:06:48.643942 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1368 00:06:48.655146 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1369 00:06:48.666331 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1370 00:06:48.677535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1371 00:06:48.688723 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1372 00:06:48.699927 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1373 00:06:48.711115 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1374 00:06:48.722298 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1375 00:06:48.733490 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1376 00:06:48.744659 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1377 00:06:48.755954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1378 00:06:48.767075 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1379 00:06:48.778245 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1380 00:06:48.789419 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1381 00:06:48.800700 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1382 00:06:48.806220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1383 00:06:48.817406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1384 00:06:48.828686 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1385 00:06:48.839944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1386 00:06:48.850976 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1387 00:06:48.862191 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1388 00:06:48.873375 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1389 00:06:48.884580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1390 00:06:48.895706 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1391 00:06:48.906954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1392 00:06:48.918115 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1393 00:06:48.929323 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1394 00:06:48.940514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1395 00:06:48.951664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1396 00:06:48.963028 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1397 00:06:48.974096 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1398 00:06:48.985281 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1399 00:06:48.996446 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1400 00:06:49.002059 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1401 00:06:49.013269 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1402 00:06:49.024519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1403 00:06:49.035724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1404 00:06:49.046902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1405 00:06:49.058070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1406 00:06:49.069227 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1407 00:06:49.074836 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1408 00:06:49.086013 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1409 00:06:49.097172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1410 00:06:49.108377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1411 00:06:49.119561 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1412 00:06:49.130747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1413 00:06:49.141993 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1414 00:06:49.158756 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1415 00:06:49.164373 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1416 00:06:49.175560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1417 00:06:49.186735 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1418 00:06:49.192318 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1419 00:06:49.203500 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1420 00:06:49.209102 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1421 00:06:49.220388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1422 00:06:49.231572 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1423 00:06:49.237085 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1424 00:06:49.248294 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1425 00:06:49.259513 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1426 00:06:49.270767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1427 00:06:49.276285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1428 00:06:49.287477 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1429 00:06:49.304260 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1430 00:06:49.315449 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1431 00:06:49.326630 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1432 00:06:49.337893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1433 00:06:49.349042 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1434 00:06:49.360188 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1435 00:06:49.371418 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1436 00:06:49.382574 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1437 00:06:49.399299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1438 00:06:49.410457 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1439 00:06:49.421677 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1440 00:06:49.432948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1441 00:06:49.449779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1442 00:06:49.461060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1443 00:06:49.472115 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1444 00:06:49.483345 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1445 00:06:49.489083 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1446 00:06:49.500573 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1447 00:06:49.505735 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1448 00:06:49.516944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1449 00:06:49.522474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1450 00:06:49.533653 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1451 00:06:49.539276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1452 00:06:49.550444 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1453 00:06:49.556036 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1454 00:06:49.567219 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1455 00:06:49.578423 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1456 00:06:49.584032 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1457 00:06:49.595176 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1458 00:06:49.606439 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1459 00:06:49.617589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1460 00:06:49.623191 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1461 00:06:49.634378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1462 00:06:49.645563 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1463 00:06:49.656830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1464 00:06:49.657291 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1465 00:06:49.668062 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1466 00:06:49.673589 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1467 00:06:49.679170 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1468 00:06:49.684843 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1469 00:06:49.690350 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1470 00:06:49.701557 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1471 00:06:49.707183 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1472 00:06:49.718323 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1473 00:06:49.723912 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1474 00:06:49.735124 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1475 00:06:49.740716 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1476 00:06:49.751946 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1477 00:06:49.757518 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1478 00:06:49.763142 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1479 00:06:49.774331 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1480 00:06:49.780031 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1481 00:06:49.791083 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1482 00:06:49.796703 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1483 00:06:49.807959 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1484 00:06:49.813490 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1485 00:06:49.824658 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1486 00:06:49.830270 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1487 00:06:49.841489 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1488 00:06:49.847138 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1489 00:06:49.858220 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1490 00:06:49.863876 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1491 00:06:49.869452 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1492 00:06:49.880678 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1493 00:06:49.886322 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1494 00:06:49.897398 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1495 00:06:49.903143 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1496 00:06:49.914188 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1497 00:06:49.919917 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1498 00:06:49.931135 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1499 00:06:49.942152 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1500 00:06:49.953409 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1501 00:06:49.964590 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1502 00:06:49.975757 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1503 00:06:49.987027 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1504 00:06:49.998096 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1505 00:06:50.009468 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1506 00:06:50.014990 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1507 00:06:50.026134 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1508 00:06:50.031766 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1509 00:06:50.042942 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1510 00:06:50.048582 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1511 00:06:50.059768 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1512 00:06:50.065354 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1513 00:06:50.076542 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1514 00:06:50.082212 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1515 00:06:50.093283 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1516 00:06:50.098930 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1517 00:06:50.110252 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1518 00:06:50.115794 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1519 00:06:50.121332 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1520 00:06:50.132462 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1521 00:06:50.138218 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1522 00:06:50.143682 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1523 00:06:50.154872 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1524 00:06:50.166189 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1525 00:06:50.171675 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1526 00:06:50.177252 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1527 00:06:50.188478 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1528 00:06:50.199569 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1529 00:06:50.200090 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1530 00:06:50.210891 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1531 00:06:50.216470 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1532 00:06:50.227560 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1533 00:06:50.233190 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1534 00:06:50.244405 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1535 00:06:50.250011 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1536 00:06:50.261160 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1537 00:06:50.272347 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1538 00:06:50.283521 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1539 00:06:50.289238 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1540 00:06:50.300430 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1541 00:06:50.306140 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1542 00:06:50.311812 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1543 00:06:50.317351 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1544 00:06:50.322997 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1545 00:06:50.328522 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1546 00:06:50.334305 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1547 00:06:50.345324 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1548 00:06:50.351025 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1549 00:06:50.356551 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1550 00:06:50.362276 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1551 00:06:50.367773 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1552 00:06:50.373330 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1553 00:06:50.384545 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1554 00:06:50.385112 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1555 00:06:50.390317 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1556 00:06:50.395725 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1557 00:06:50.401343 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1558 00:06:50.407061 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1559 00:06:50.412585 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1560 00:06:50.418166 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1561 00:06:50.423738 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1562 00:06:50.429359 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1563 00:06:50.434958 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1564 00:06:50.440540 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1565 00:06:50.446472 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1566 00:06:50.451726 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1567 00:06:50.457317 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1568 00:06:50.462941 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1569 00:06:50.468618 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1570 00:06:50.474190 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1571 00:06:50.479771 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1572 00:06:50.485338 dt_test_unprobed_devices_sh_opp-table skip
1573 00:06:50.491001 dt_test_unprobed_devices_sh_soc skip
1574 00:06:50.491550 dt_test_unprobed_devices_sh_sound pass
1575 00:06:50.496581 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1576 00:06:50.502337 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1577 00:06:50.513459 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1578 00:06:50.514116 dt_test_unprobed_devices_sh fail
1579 00:06:50.519021 + ../../utils/send-to-lava.sh ./output/result.txt
1580 00:06:50.525316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1581 00:06:50.526245 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1583 00:06:50.536613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1584 00:06:50.537383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1586 00:06:50.627320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1587 00:06:50.628211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1589 00:06:50.720001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1590 00:06:50.720895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1592 00:06:50.811981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1593 00:06:50.812819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1595 00:06:50.905198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1596 00:06:50.906059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1598 00:06:50.995716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1599 00:06:50.996590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1601 00:06:51.084720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1602 00:06:51.085768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1604 00:06:51.176187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1605 00:06:51.177050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1607 00:06:51.269623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1608 00:06:51.270582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1610 00:06:51.365940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1611 00:06:51.366905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1613 00:06:51.456208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1614 00:06:51.457087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1616 00:06:51.548984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1617 00:06:51.549923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1619 00:06:51.640446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1620 00:06:51.641360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1622 00:06:51.730885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1623 00:06:51.731741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1625 00:06:51.824858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1626 00:06:51.825768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1628 00:06:51.919021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1629 00:06:51.919954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1631 00:06:52.013042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1632 00:06:52.013966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1634 00:06:52.108013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1635 00:06:52.108939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1637 00:06:52.200823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1638 00:06:52.201774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1640 00:06:52.291409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1641 00:06:52.292269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1643 00:06:52.377095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1644 00:06:52.377970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1646 00:06:52.469407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1647 00:06:52.470301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1649 00:06:52.560594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1650 00:06:52.561335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1652 00:06:52.651959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1653 00:06:52.652838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1655 00:06:52.742793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1656 00:06:52.743906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1658 00:06:52.834480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1659 00:06:52.835785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1661 00:06:52.928417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1662 00:06:52.929337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1664 00:06:53.020406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1665 00:06:53.021298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1667 00:06:53.113270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1668 00:06:53.114148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1670 00:06:53.203685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1671 00:06:53.204486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1673 00:06:53.301547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1674 00:06:53.302464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1676 00:06:53.394152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1677 00:06:53.395008 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1679 00:06:53.486624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1680 00:06:53.487486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1682 00:06:53.576553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1683 00:06:53.577349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1685 00:06:53.668691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1686 00:06:53.669499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1688 00:06:53.759282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1689 00:06:53.760058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1691 00:06:53.851670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1692 00:06:53.852513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1694 00:06:53.943923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1695 00:06:53.944771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1697 00:06:54.036605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1698 00:06:54.037556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1700 00:06:54.132987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1701 00:06:54.133894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1703 00:06:54.223032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1704 00:06:54.223905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1706 00:06:54.314589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1707 00:06:54.315449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1709 00:06:54.406016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1710 00:06:54.406946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1712 00:06:54.497780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1713 00:06:54.498729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1715 00:06:54.590073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1716 00:06:54.590941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1718 00:06:54.681333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1719 00:06:54.682284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1721 00:06:54.774304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1722 00:06:54.776662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1724 00:06:54.866699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1725 00:06:54.867312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1727 00:06:54.959085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1728 00:06:54.959694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1730 00:06:55.050015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1731 00:06:55.050629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1733 00:06:55.142704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1734 00:06:55.143319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1736 00:06:55.235077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1737 00:06:55.235653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1739 00:06:55.330463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1740 00:06:55.331044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1742 00:06:55.423338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1743 00:06:55.423951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1745 00:06:55.517063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1746 00:06:55.517683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1748 00:06:55.612431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1749 00:06:55.613007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1751 00:06:55.702496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1752 00:06:55.703062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1754 00:06:55.793425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1755 00:06:55.793991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1757 00:06:55.885891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1758 00:06:55.886455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1760 00:06:55.979103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1761 00:06:55.979662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1763 00:06:56.071897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1764 00:06:56.072494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1766 00:06:56.163134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1767 00:06:56.163697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1769 00:06:56.255786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1770 00:06:56.256395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1772 00:06:56.348945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1773 00:06:56.349543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1775 00:06:56.443933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1776 00:06:56.444548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1778 00:06:56.538997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1779 00:06:56.539601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1781 00:06:56.630829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1782 00:06:56.631379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1784 00:06:56.721949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1785 00:06:56.722990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1787 00:06:56.811038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1788 00:06:56.811590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1790 00:06:56.901700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1791 00:06:56.902291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1793 00:06:56.992817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1794 00:06:56.993408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1796 00:06:57.085059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1797 00:06:57.085673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1799 00:06:57.176529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1800 00:06:57.177132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1802 00:06:57.269717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1803 00:06:57.270349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1805 00:06:57.362317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1806 00:06:57.362940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1808 00:06:57.453684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1809 00:06:57.454328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1811 00:06:57.556029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1812 00:06:57.556980 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1814 00:06:57.650172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1815 00:06:57.651058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1817 00:06:57.742400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1818 00:06:57.743286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1820 00:06:57.833771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1821 00:06:57.834685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1823 00:06:57.926785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1824 00:06:57.927633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1826 00:06:58.020058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1827 00:06:58.021311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1829 00:06:58.110667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1830 00:06:58.111561 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1832 00:06:58.203201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1833 00:06:58.204086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1835 00:06:58.295489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1836 00:06:58.296372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1838 00:06:58.393412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1839 00:06:58.394603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1841 00:06:58.483882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1842 00:06:58.484803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1844 00:06:58.574680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1845 00:06:58.575549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1847 00:06:58.671588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1848 00:06:58.672461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1850 00:06:58.767612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1851 00:06:58.768542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1853 00:06:58.856601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1854 00:06:58.857475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1856 00:06:58.951351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1857 00:06:58.952348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1859 00:06:59.042133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1860 00:06:59.043079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1862 00:06:59.134411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1863 00:06:59.135330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1865 00:06:59.223493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1866 00:06:59.224385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1868 00:06:59.318812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1869 00:06:59.319725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1871 00:06:59.408340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1872 00:06:59.408966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1874 00:06:59.501555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1875 00:06:59.502294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1877 00:06:59.594198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1878 00:06:59.595070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1880 00:06:59.688066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1881 00:06:59.688947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1883 00:06:59.778524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1884 00:06:59.779409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1886 00:06:59.869359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1887 00:06:59.870433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1889 00:06:59.959802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1890 00:06:59.960658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1892 00:07:00.051032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1893 00:07:00.051669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1895 00:07:00.145911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1896 00:07:00.146774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1898 00:07:00.236412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1899 00:07:00.237269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1901 00:07:00.330168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1902 00:07:00.331022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1904 00:07:00.424929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1905 00:07:00.425849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1907 00:07:00.520170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1908 00:07:00.521075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1910 00:07:00.616958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1911 00:07:00.617979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1913 00:07:00.708898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1914 00:07:00.709730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1916 00:07:00.800777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1917 00:07:00.801667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1919 00:07:00.892982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1920 00:07:00.893900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1922 00:07:00.982666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1923 00:07:00.983544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1925 00:07:01.076656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1926 00:07:01.077517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1928 00:07:01.171764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1929 00:07:01.172619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1931 00:07:01.265650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1932 00:07:01.266571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1934 00:07:01.357340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1935 00:07:01.359678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1937 00:07:01.448295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1938 00:07:01.449148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1940 00:07:01.539200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1942 00:07:01.542373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1943 00:07:01.633648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1945 00:07:01.636909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1946 00:07:01.726548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1948 00:07:01.729955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1949 00:07:01.819635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1950 00:07:01.820656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1952 00:07:01.911254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1953 00:07:01.912131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1955 00:07:02.001421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1956 00:07:02.002596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1958 00:07:02.098224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1959 00:07:02.099081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1961 00:07:02.191586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1962 00:07:02.192424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1964 00:07:02.284825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1965 00:07:02.285918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1967 00:07:02.377093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1968 00:07:02.378096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1970 00:07:02.472236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1971 00:07:02.473100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1973 00:07:02.563663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1974 00:07:02.564573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1976 00:07:02.655880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1977 00:07:02.656799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1979 00:07:02.747920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1980 00:07:02.748791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1982 00:07:02.840167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1983 00:07:02.841027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1985 00:07:02.928674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1986 00:07:02.929564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1988 00:07:03.016894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1989 00:07:03.017556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1991 00:07:03.112824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1992 00:07:03.113681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1994 00:07:03.205493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1995 00:07:03.206349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
1997 00:07:03.301630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1998 00:07:03.302514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2000 00:07:03.398623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2001 00:07:03.399470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2003 00:07:03.494539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2004 00:07:03.495381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2006 00:07:03.589612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2007 00:07:03.590464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2009 00:07:03.679257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2010 00:07:03.680075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2012 00:07:03.765856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2013 00:07:03.766648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2015 00:07:03.858157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2016 00:07:03.858937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2018 00:07:03.950001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2019 00:07:03.950783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2021 00:07:04.042601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2022 00:07:04.043429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2024 00:07:04.137088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2025 00:07:04.137927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2027 00:07:04.228826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2028 00:07:04.229711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2030 00:07:04.320368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2031 00:07:04.321227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2033 00:07:04.414333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2034 00:07:04.415235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2036 00:07:04.507068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2037 00:07:04.508038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2039 00:07:04.599409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2040 00:07:04.600253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2042 00:07:04.689766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2043 00:07:04.690619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2045 00:07:04.781381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2046 00:07:04.782348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2048 00:07:04.873660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2049 00:07:04.874539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2051 00:07:04.963727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2052 00:07:04.964520 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2054 00:07:05.058570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2055 00:07:05.059506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2057 00:07:05.148837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2058 00:07:05.149475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2060 00:07:05.240269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2061 00:07:05.240900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2063 00:07:05.333701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2064 00:07:05.334363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2066 00:07:05.428440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2067 00:07:05.429071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2069 00:07:05.519692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2070 00:07:05.520289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2072 00:07:05.613037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2073 00:07:05.613665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2075 00:07:05.704503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2076 00:07:05.705276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2078 00:07:05.798944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2079 00:07:05.799739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2081 00:07:05.890274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2082 00:07:05.891087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2084 00:07:05.982024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2085 00:07:05.982821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2087 00:07:06.072884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2088 00:07:06.073704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2090 00:07:06.165115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2091 00:07:06.165939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2093 00:07:06.256098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2094 00:07:06.256896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2096 00:07:06.346456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2097 00:07:06.347256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2099 00:07:06.436548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2100 00:07:06.437402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2102 00:07:06.527310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2103 00:07:06.527949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2105 00:07:06.617424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2106 00:07:06.618058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2108 00:07:06.710135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2109 00:07:06.710755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2111 00:07:06.803991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2112 00:07:06.804656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2114 00:07:06.896836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2115 00:07:06.897448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2117 00:07:06.990838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2118 00:07:06.991432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2120 00:07:07.081233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2121 00:07:07.081855 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2123 00:07:07.172128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2124 00:07:07.172701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2126 00:07:07.272293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2127 00:07:07.273177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2129 00:07:07.368737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2130 00:07:07.369640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2132 00:07:07.461280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2133 00:07:07.462250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2135 00:07:07.550176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2136 00:07:07.551065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2138 00:07:07.633054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2139 00:07:07.633931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2141 00:07:07.723143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2142 00:07:07.723988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2144 00:07:07.814772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2145 00:07:07.816107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2147 00:07:07.906736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2148 00:07:07.907637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2150 00:07:07.997461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2151 00:07:07.998330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2153 00:07:08.088489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2154 00:07:08.089424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2156 00:07:08.178808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2157 00:07:08.179783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2159 00:07:08.270089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2160 00:07:08.271013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2162 00:07:08.356983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2163 00:07:08.358020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2165 00:07:08.447365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2166 00:07:08.448226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2168 00:07:08.538939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2169 00:07:08.539884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2171 00:07:08.628556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2172 00:07:08.629410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2174 00:07:08.712578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2175 00:07:08.713377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2177 00:07:08.806369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2178 00:07:08.807232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2180 00:07:08.897923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2181 00:07:08.898794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2183 00:07:08.987620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2184 00:07:08.988532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2186 00:07:09.081493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2187 00:07:09.082402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2189 00:07:09.173993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2190 00:07:09.174883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2192 00:07:09.267305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2193 00:07:09.268111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2195 00:07:09.358529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2196 00:07:09.359417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2198 00:07:09.449024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2199 00:07:09.449951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2201 00:07:09.538344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2202 00:07:09.539258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2204 00:07:09.630240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2205 00:07:09.631221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2207 00:07:09.718037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2208 00:07:09.718703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2210 00:07:09.810065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2211 00:07:09.810606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2213 00:07:09.902720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2214 00:07:09.903534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2216 00:07:09.995136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2217 00:07:09.995917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2219 00:07:10.089443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2220 00:07:10.090248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2222 00:07:10.180079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2223 00:07:10.180850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2225 00:07:10.272944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2226 00:07:10.273759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2228 00:07:10.364903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2229 00:07:10.365799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2231 00:07:10.460570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2232 00:07:10.461421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2234 00:07:10.550688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2235 00:07:10.551589 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2237 00:07:10.642907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2238 00:07:10.643755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2240 00:07:10.736888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2241 00:07:10.737758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2243 00:07:10.824889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2244 00:07:10.825697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2246 00:07:10.915306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2247 00:07:10.916115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2249 00:07:11.007298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2250 00:07:11.008130 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2252 00:07:11.096559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2253 00:07:11.097411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2255 00:07:11.187532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2256 00:07:11.188343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2258 00:07:11.280357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2259 00:07:11.281255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2261 00:07:11.368606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2263 00:07:11.371574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2264 00:07:11.459224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2265 00:07:11.459837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2267 00:07:11.552229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2268 00:07:11.552875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2270 00:07:11.642809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2271 00:07:11.643399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2273 00:07:11.735046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2274 00:07:11.735688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2276 00:07:11.825548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2277 00:07:11.826207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2279 00:07:11.916029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2280 00:07:11.916691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2282 00:07:12.005935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2283 00:07:12.006567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2285 00:07:12.095954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2286 00:07:12.096588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2288 00:07:12.185952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2289 00:07:12.186561 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2291 00:07:12.275982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2292 00:07:12.276554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2294 00:07:12.365791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2295 00:07:12.366396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2297 00:07:12.450678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2298 00:07:12.451316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2300 00:07:12.542082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2301 00:07:12.542705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2303 00:07:12.634673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2304 00:07:12.635210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2306 00:07:12.725881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2307 00:07:12.726416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2309 00:07:12.815791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2310 00:07:12.816312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2312 00:07:12.905897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2313 00:07:12.906439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2315 00:07:12.996535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2316 00:07:12.997089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2318 00:07:13.087362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2319 00:07:13.087999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2321 00:07:13.179218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2322 00:07:13.179807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2324 00:07:13.271400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2325 00:07:13.271974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2327 00:07:13.362310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2328 00:07:13.362884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2330 00:07:13.451706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2331 00:07:13.452316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2333 00:07:13.544581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2334 00:07:13.545163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2336 00:07:13.632046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2337 00:07:13.632882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2339 00:07:13.721057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2340 00:07:13.721940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2342 00:07:13.813043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2343 00:07:13.813912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2345 00:07:13.902364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2346 00:07:13.903224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2348 00:07:13.996217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2349 00:07:13.997072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2351 00:07:14.089353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2352 00:07:14.090260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2354 00:07:14.177907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2355 00:07:14.178540 + set +x
2356 00:07:14.179301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2358 00:07:14.181128 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 956489_1.6.2.4.5>
2359 00:07:14.182093 Received signal: <ENDRUN> 1_kselftest-dt 956489_1.6.2.4.5
2360 00:07:14.182738 Ending use of test pattern.
2361 00:07:14.183427 Ending test lava.1_kselftest-dt (956489_1.6.2.4.5), duration 84.99
2363 00:07:14.188523 <LAVA_TEST_RUNNER EXIT>
2364 00:07:14.189514 ok: lava_test_shell seems to have completed
2365 00:07:14.204070 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2366 00:07:14.206239 end: 3.1 lava-test-shell (duration 00:01:26) [common]
2367 00:07:14.206953 end: 3 lava-test-retry (duration 00:01:26) [common]
2368 00:07:14.207612 start: 4 finalize (timeout 00:05:27) [common]
2369 00:07:14.208249 start: 4.1 power-off (timeout 00:00:30) [common]
2370 00:07:14.209639 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2371 00:07:14.242436 >> OK - accepted request
2372 00:07:14.244467 Returned 0 in 0 seconds
2373 00:07:14.345792 end: 4.1 power-off (duration 00:00:00) [common]
2375 00:07:14.347712 start: 4.2 read-feedback (timeout 00:05:27) [common]
2376 00:07:14.348970 Listened to connection for namespace 'common' for up to 1s
2377 00:07:14.349908 Listened to connection for namespace 'common' for up to 1s
2378 00:07:15.349701 Finalising connection for namespace 'common'
2379 00:07:15.350519 Disconnecting from shell: Finalise
2380 00:07:15.351103 / #
2381 00:07:15.452218 end: 4.2 read-feedback (duration 00:00:01) [common]
2382 00:07:15.453029 end: 4 finalize (duration 00:00:01) [common]
2383 00:07:15.453739 Cleaning after the job
2384 00:07:15.454466 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956489/tftp-deploy-63p351ov/ramdisk
2385 00:07:15.464095 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956489/tftp-deploy-63p351ov/kernel
2386 00:07:15.471874 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956489/tftp-deploy-63p351ov/dtb
2387 00:07:15.473249 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956489/tftp-deploy-63p351ov/nfsrootfs
2388 00:07:15.613363 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956489/tftp-deploy-63p351ov/modules
2389 00:07:15.622094 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/956489
2390 00:07:18.500860 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/956489
2391 00:07:18.501462 Job finished correctly