Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 02:04:40.192561 lava-dispatcher, installed at version: 2024.01
2 02:04:40.193311 start: 0 validate
3 02:04:40.193788 Start time: 2024-11-08 02:04:40.193758+00:00 (UTC)
4 02:04:40.194325 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:04:40.194862 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 02:04:40.235299 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:04:40.235837 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fkernel%2FzImage exists
8 02:04:40.262682 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:04:40.263303 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 02:04:40.293137 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:04:40.293622 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 02:04:40.322294 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:04:40.322792 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fmodules.tar.xz exists
14 02:04:40.360331 validate duration: 0.17
16 02:04:40.361265 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:04:40.361611 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:04:40.361932 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:04:40.362537 Not decompressing ramdisk as can be used compressed.
20 02:04:40.362941 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 02:04:40.363213 saving as /var/lib/lava/dispatcher/tmp/957239/tftp-deploy-c2gbn8dc/ramdisk/initrd.cpio.gz
22 02:04:40.363491 total size: 4775763 (4 MB)
23 02:04:40.401110 progress 0 % (0 MB)
24 02:04:40.405039 progress 5 % (0 MB)
25 02:04:40.408473 progress 10 % (0 MB)
26 02:04:40.411788 progress 15 % (0 MB)
27 02:04:40.415522 progress 20 % (0 MB)
28 02:04:40.418879 progress 25 % (1 MB)
29 02:04:40.422171 progress 30 % (1 MB)
30 02:04:40.425846 progress 35 % (1 MB)
31 02:04:40.429132 progress 40 % (1 MB)
32 02:04:40.432413 progress 45 % (2 MB)
33 02:04:40.435641 progress 50 % (2 MB)
34 02:04:40.439298 progress 55 % (2 MB)
35 02:04:40.442521 progress 60 % (2 MB)
36 02:04:40.445809 progress 65 % (2 MB)
37 02:04:40.449471 progress 70 % (3 MB)
38 02:04:40.452655 progress 75 % (3 MB)
39 02:04:40.455796 progress 80 % (3 MB)
40 02:04:40.459075 progress 85 % (3 MB)
41 02:04:40.462350 progress 90 % (4 MB)
42 02:04:40.465230 progress 95 % (4 MB)
43 02:04:40.468151 progress 100 % (4 MB)
44 02:04:40.468800 4 MB downloaded in 0.11 s (43.26 MB/s)
45 02:04:40.469329 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:04:40.470203 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:04:40.470495 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:04:40.470767 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:04:40.471239 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm/multi_v7_defconfig/clang-15/kernel/zImage
51 02:04:40.471483 saving as /var/lib/lava/dispatcher/tmp/957239/tftp-deploy-c2gbn8dc/kernel/zImage
52 02:04:40.471693 total size: 12050944 (11 MB)
53 02:04:40.471906 No compression specified
54 02:04:40.508830 progress 0 % (0 MB)
55 02:04:40.516796 progress 5 % (0 MB)
56 02:04:40.524291 progress 10 % (1 MB)
57 02:04:40.532291 progress 15 % (1 MB)
58 02:04:40.539856 progress 20 % (2 MB)
59 02:04:40.547464 progress 25 % (2 MB)
60 02:04:40.555372 progress 30 % (3 MB)
61 02:04:40.562889 progress 35 % (4 MB)
62 02:04:40.570882 progress 40 % (4 MB)
63 02:04:40.578412 progress 45 % (5 MB)
64 02:04:40.585860 progress 50 % (5 MB)
65 02:04:40.593777 progress 55 % (6 MB)
66 02:04:40.601275 progress 60 % (6 MB)
67 02:04:40.609462 progress 65 % (7 MB)
68 02:04:40.616869 progress 70 % (8 MB)
69 02:04:40.624306 progress 75 % (8 MB)
70 02:04:40.632115 progress 80 % (9 MB)
71 02:04:40.639518 progress 85 % (9 MB)
72 02:04:40.646918 progress 90 % (10 MB)
73 02:04:40.654357 progress 95 % (10 MB)
74 02:04:40.661179 progress 100 % (11 MB)
75 02:04:40.661837 11 MB downloaded in 0.19 s (60.45 MB/s)
76 02:04:40.662315 end: 1.2.1 http-download (duration 00:00:00) [common]
78 02:04:40.663125 end: 1.2 download-retry (duration 00:00:00) [common]
79 02:04:40.663399 start: 1.3 download-retry (timeout 00:10:00) [common]
80 02:04:40.663664 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 02:04:40.664155 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
82 02:04:40.664429 saving as /var/lib/lava/dispatcher/tmp/957239/tftp-deploy-c2gbn8dc/dtb/am335x-boneblack.dtb
83 02:04:40.664639 total size: 70568 (0 MB)
84 02:04:40.664847 No compression specified
85 02:04:40.700979 progress 46 % (0 MB)
86 02:04:40.701826 progress 92 % (0 MB)
87 02:04:40.702569 progress 100 % (0 MB)
88 02:04:40.703007 0 MB downloaded in 0.04 s (1.75 MB/s)
89 02:04:40.703507 end: 1.3.1 http-download (duration 00:00:00) [common]
91 02:04:40.704420 end: 1.3 download-retry (duration 00:00:00) [common]
92 02:04:40.704729 start: 1.4 download-retry (timeout 00:10:00) [common]
93 02:04:40.705028 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 02:04:40.705522 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 02:04:40.705794 saving as /var/lib/lava/dispatcher/tmp/957239/tftp-deploy-c2gbn8dc/nfsrootfs/full.rootfs.tar
96 02:04:40.706023 total size: 117747780 (112 MB)
97 02:04:40.706255 Using unxz to decompress xz
98 02:04:40.738149 progress 0 % (0 MB)
99 02:04:41.470969 progress 5 % (5 MB)
100 02:04:42.221358 progress 10 % (11 MB)
101 02:04:43.061601 progress 15 % (16 MB)
102 02:04:43.790811 progress 20 % (22 MB)
103 02:04:44.363213 progress 25 % (28 MB)
104 02:04:45.162494 progress 30 % (33 MB)
105 02:04:45.955279 progress 35 % (39 MB)
106 02:04:46.302889 progress 40 % (44 MB)
107 02:04:46.659509 progress 45 % (50 MB)
108 02:04:47.304279 progress 50 % (56 MB)
109 02:04:48.100794 progress 55 % (61 MB)
110 02:04:48.822464 progress 60 % (67 MB)
111 02:04:49.532340 progress 65 % (73 MB)
112 02:04:50.289662 progress 70 % (78 MB)
113 02:04:51.044428 progress 75 % (84 MB)
114 02:04:51.771482 progress 80 % (89 MB)
115 02:04:52.469851 progress 85 % (95 MB)
116 02:04:53.249814 progress 90 % (101 MB)
117 02:04:54.009061 progress 95 % (106 MB)
118 02:04:54.816605 progress 100 % (112 MB)
119 02:04:54.829902 112 MB downloaded in 14.12 s (7.95 MB/s)
120 02:04:54.830834 end: 1.4.1 http-download (duration 00:00:14) [common]
122 02:04:54.832691 end: 1.4 download-retry (duration 00:00:14) [common]
123 02:04:54.833274 start: 1.5 download-retry (timeout 00:09:46) [common]
124 02:04:54.833844 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 02:04:54.834884 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm/multi_v7_defconfig/clang-15/modules.tar.xz
126 02:04:54.835399 saving as /var/lib/lava/dispatcher/tmp/957239/tftp-deploy-c2gbn8dc/modules/modules.tar
127 02:04:54.835862 total size: 6916884 (6 MB)
128 02:04:54.836375 Using unxz to decompress xz
129 02:04:54.881057 progress 0 % (0 MB)
130 02:04:54.916318 progress 5 % (0 MB)
131 02:04:54.964064 progress 10 % (0 MB)
132 02:04:55.008812 progress 15 % (1 MB)
133 02:04:55.060295 progress 20 % (1 MB)
134 02:04:55.107090 progress 25 % (1 MB)
135 02:04:55.156108 progress 30 % (2 MB)
136 02:04:55.199397 progress 35 % (2 MB)
137 02:04:55.247138 progress 40 % (2 MB)
138 02:04:55.291356 progress 45 % (2 MB)
139 02:04:55.339581 progress 50 % (3 MB)
140 02:04:55.386479 progress 55 % (3 MB)
141 02:04:55.432518 progress 60 % (3 MB)
142 02:04:55.479071 progress 65 % (4 MB)
143 02:04:55.523930 progress 70 % (4 MB)
144 02:04:55.574532 progress 75 % (4 MB)
145 02:04:55.617909 progress 80 % (5 MB)
146 02:04:55.666293 progress 85 % (5 MB)
147 02:04:55.709828 progress 90 % (5 MB)
148 02:04:55.757576 progress 95 % (6 MB)
149 02:04:55.805702 progress 100 % (6 MB)
150 02:04:55.816941 6 MB downloaded in 0.98 s (6.72 MB/s)
151 02:04:55.817670 end: 1.5.1 http-download (duration 00:00:01) [common]
153 02:04:55.819478 end: 1.5 download-retry (duration 00:00:01) [common]
154 02:04:55.820122 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 02:04:55.820730 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 02:05:12.065353 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/957239/extract-nfsrootfs-uuun834o
157 02:05:12.065961 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 02:05:12.066279 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 02:05:12.066920 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf
160 02:05:12.067394 makedir: /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin
161 02:05:12.067777 makedir: /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/tests
162 02:05:12.068181 makedir: /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/results
163 02:05:12.068559 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-add-keys
164 02:05:12.069099 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-add-sources
165 02:05:12.069604 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-background-process-start
166 02:05:12.070164 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-background-process-stop
167 02:05:12.070691 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-common-functions
168 02:05:12.071171 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-echo-ipv4
169 02:05:12.071654 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-install-packages
170 02:05:12.072187 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-installed-packages
171 02:05:12.072772 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-os-build
172 02:05:12.073253 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-probe-channel
173 02:05:12.073721 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-probe-ip
174 02:05:12.074181 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-target-ip
175 02:05:12.074638 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-target-mac
176 02:05:12.075100 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-target-storage
177 02:05:12.075571 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-test-case
178 02:05:12.076077 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-test-event
179 02:05:12.076558 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-test-feedback
180 02:05:12.077022 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-test-raise
181 02:05:12.077481 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-test-reference
182 02:05:12.077944 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-test-runner
183 02:05:12.078411 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-test-set
184 02:05:12.078898 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-test-shell
185 02:05:12.079377 Updating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-add-keys (debian)
186 02:05:12.079894 Updating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-add-sources (debian)
187 02:05:12.080423 Updating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-install-packages (debian)
188 02:05:12.080936 Updating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-installed-packages (debian)
189 02:05:12.081431 Updating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/bin/lava-os-build (debian)
190 02:05:12.081857 Creating /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/environment
191 02:05:12.082228 LAVA metadata
192 02:05:12.082493 - LAVA_JOB_ID=957239
193 02:05:12.082709 - LAVA_DISPATCHER_IP=192.168.6.2
194 02:05:12.083073 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 02:05:12.084037 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 02:05:12.084355 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 02:05:12.084562 skipped lava-vland-overlay
198 02:05:12.084799 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 02:05:12.085050 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 02:05:12.085267 skipped lava-multinode-overlay
201 02:05:12.085506 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 02:05:12.085755 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 02:05:12.085995 Loading test definitions
204 02:05:12.086268 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 02:05:12.086485 Using /lava-957239 at stage 0
206 02:05:12.087557 uuid=957239_1.6.2.4.1 testdef=None
207 02:05:12.087858 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 02:05:12.088186 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 02:05:12.089732 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 02:05:12.090511 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 02:05:12.092453 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 02:05:12.093280 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 02:05:12.095095 runner path: /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/0/tests/0_timesync-off test_uuid 957239_1.6.2.4.1
216 02:05:12.095632 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 02:05:12.096465 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 02:05:12.096689 Using /lava-957239 at stage 0
220 02:05:12.097036 Fetching tests from https://github.com/kernelci/test-definitions.git
221 02:05:12.097320 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/0/tests/1_kselftest-dt'
222 02:05:15.352433 Running '/usr/bin/git checkout kernelci.org
223 02:05:15.666326 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 02:05:15.667749 uuid=957239_1.6.2.4.5 testdef=None
225 02:05:15.668121 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 02:05:15.668877 start: 1.6.2.4.6 test-overlay (timeout 00:09:25) [common]
228 02:05:15.671817 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 02:05:15.672678 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:25) [common]
231 02:05:15.676538 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 02:05:15.677414 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:25) [common]
234 02:05:15.681039 runner path: /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/0/tests/1_kselftest-dt test_uuid 957239_1.6.2.4.5
235 02:05:15.681329 BOARD='beaglebone-black'
236 02:05:15.681531 BRANCH='mainline'
237 02:05:15.681725 SKIPFILE='/dev/null'
238 02:05:15.681920 SKIP_INSTALL='True'
239 02:05:15.682130 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
240 02:05:15.682362 TST_CASENAME=''
241 02:05:15.682575 TST_CMDFILES='dt'
242 02:05:15.683169 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 02:05:15.683958 Creating lava-test-runner.conf files
245 02:05:15.684200 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/957239/lava-overlay-fn53svpf/lava-957239/0 for stage 0
246 02:05:15.684567 - 0_timesync-off
247 02:05:15.684816 - 1_kselftest-dt
248 02:05:15.685151 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 02:05:15.685433 start: 1.6.2.5 compress-overlay (timeout 00:09:25) [common]
250 02:05:39.626339 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 02:05:39.626781 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 02:05:39.627051 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 02:05:39.627321 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 02:05:39.627584 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 02:05:39.998860 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 02:05:39.999342 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 02:05:39.999618 extracting modules file /var/lib/lava/dispatcher/tmp/957239/tftp-deploy-c2gbn8dc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/957239/extract-nfsrootfs-uuun834o
258 02:05:40.918338 extracting modules file /var/lib/lava/dispatcher/tmp/957239/tftp-deploy-c2gbn8dc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/957239/extract-overlay-ramdisk-6o9u323t/ramdisk
259 02:05:41.880083 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 02:05:41.880565 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 02:05:41.880843 [common] Applying overlay to NFS
262 02:05:41.881058 [common] Applying overlay /var/lib/lava/dispatcher/tmp/957239/compress-overlay-7i0ybrng/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/957239/extract-nfsrootfs-uuun834o
263 02:05:44.622057 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 02:05:44.622542 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 02:05:44.622817 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 02:05:44.623096 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 02:05:44.623346 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 02:05:44.623604 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 02:05:44.623851 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 02:05:44.624146 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 02:05:44.624403 Building ramdisk /var/lib/lava/dispatcher/tmp/957239/extract-overlay-ramdisk-6o9u323t/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/957239/extract-overlay-ramdisk-6o9u323t/ramdisk
272 02:05:45.720696 >> 79012 blocks
273 02:05:50.886651 Adding RAMdisk u-boot header.
274 02:05:50.887410 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/957239/extract-overlay-ramdisk-6o9u323t/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/957239/extract-overlay-ramdisk-6o9u323t/ramdisk.cpio.gz.uboot
275 02:05:51.050687 output: Image Name:
276 02:05:51.051094 output: Created: Fri Nov 8 02:05:50 2024
277 02:05:51.051307 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 02:05:51.051512 output: Data Size: 15350573 Bytes = 14990.79 KiB = 14.64 MiB
279 02:05:51.051716 output: Load Address: 00000000
280 02:05:51.051918 output: Entry Point: 00000000
281 02:05:51.052289 output:
282 02:05:51.053331 rename /var/lib/lava/dispatcher/tmp/957239/extract-overlay-ramdisk-6o9u323t/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/957239/tftp-deploy-c2gbn8dc/ramdisk/ramdisk.cpio.gz.uboot
283 02:05:51.054050 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 02:05:51.054593 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 02:05:51.055118 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 02:05:51.055573 No LXC device requested
287 02:05:51.056131 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 02:05:51.056650 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 02:05:51.057137 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 02:05:51.057546 Checking files for TFTP limit of 4294967296 bytes.
291 02:05:51.060190 end: 1 tftp-deploy (duration 00:01:11) [common]
292 02:05:51.060774 start: 2 uboot-action (timeout 00:05:00) [common]
293 02:05:51.061293 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 02:05:51.061783 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 02:05:51.062276 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 02:05:51.063020 substitutions:
297 02:05:51.063431 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 02:05:51.063831 - {DTB_ADDR}: 0x88000000
299 02:05:51.064259 - {DTB}: 957239/tftp-deploy-c2gbn8dc/dtb/am335x-boneblack.dtb
300 02:05:51.064656 - {INITRD}: 957239/tftp-deploy-c2gbn8dc/ramdisk/ramdisk.cpio.gz.uboot
301 02:05:51.065047 - {KERNEL_ADDR}: 0x82000000
302 02:05:51.065434 - {KERNEL}: 957239/tftp-deploy-c2gbn8dc/kernel/zImage
303 02:05:51.065823 - {LAVA_MAC}: None
304 02:05:51.066253 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/957239/extract-nfsrootfs-uuun834o
305 02:05:51.066648 - {NFS_SERVER_IP}: 192.168.6.2
306 02:05:51.067037 - {PRESEED_CONFIG}: None
307 02:05:51.067424 - {PRESEED_LOCAL}: None
308 02:05:51.067811 - {RAMDISK_ADDR}: 0x83000000
309 02:05:51.068222 - {RAMDISK}: 957239/tftp-deploy-c2gbn8dc/ramdisk/ramdisk.cpio.gz.uboot
310 02:05:51.068617 - {ROOT_PART}: None
311 02:05:51.069001 - {ROOT}: None
312 02:05:51.069387 - {SERVER_IP}: 192.168.6.2
313 02:05:51.069771 - {TEE_ADDR}: 0x83000000
314 02:05:51.070150 - {TEE}: None
315 02:05:51.070532 Parsed boot commands:
316 02:05:51.070908 - setenv autoload no
317 02:05:51.071290 - setenv initrd_high 0xffffffff
318 02:05:51.071672 - setenv fdt_high 0xffffffff
319 02:05:51.072074 - dhcp
320 02:05:51.072458 - setenv serverip 192.168.6.2
321 02:05:51.072842 - tftp 0x82000000 957239/tftp-deploy-c2gbn8dc/kernel/zImage
322 02:05:51.073226 - tftp 0x83000000 957239/tftp-deploy-c2gbn8dc/ramdisk/ramdisk.cpio.gz.uboot
323 02:05:51.073608 - setenv initrd_size ${filesize}
324 02:05:51.073988 - tftp 0x88000000 957239/tftp-deploy-c2gbn8dc/dtb/am335x-boneblack.dtb
325 02:05:51.074370 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/957239/extract-nfsrootfs-uuun834o,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 02:05:51.074765 - bootz 0x82000000 0x83000000 0x88000000
327 02:05:51.075264 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 02:05:51.076759 start: 2.3 connect-device (timeout 00:05:00) [common]
330 02:05:51.077179 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 02:05:51.093635 Setting prompt string to ['lava-test: # ']
332 02:05:51.095142 end: 2.3 connect-device (duration 00:00:00) [common]
333 02:05:51.095734 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 02:05:51.096338 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 02:05:51.096875 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 02:05:51.098088 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 02:05:51.132314 >> OK - accepted request
338 02:05:51.134502 Returned 0 in 0 seconds
339 02:05:51.235608 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 02:05:51.237414 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 02:05:51.238010 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 02:05:51.238557 Setting prompt string to ['Hit any key to stop autoboot']
344 02:05:51.239021 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 02:05:51.240667 Trying 192.168.56.21...
346 02:05:51.241179 Connected to conserv1.
347 02:05:51.241585 Escape character is '^]'.
348 02:05:51.241984
349 02:05:51.242392 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 02:05:51.242805
351 02:05:59.480927
352 02:05:59.481568 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 02:05:59.485941 Trying to boot from MMC1
354 02:06:00.057907
355 02:06:00.058548
356 02:06:00.058988 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 02:06:00.059403
358 02:06:00.063419 CPU : AM335X-GP rev 2.1
359 02:06:00.063915 Model: TI AM335x BeagleBone Black
360 02:06:00.067501 DRAM: 512 MiB
361 02:06:00.150204 Core: 160 devices, 18 uclasses, devicetree: separate
362 02:06:00.159892 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 02:06:03.531493 7[r[999;999H[6n8NAND:
364 02:06:03.532239 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 02:06:03.534218 Trying to boot from MMC1
366 02:06:04.106973
367 02:06:04.107809
368 02:06:04.108527 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 02:06:04.109159
370 02:06:04.111881 CPU : AM335X-GP rev 2.1
371 02:06:04.112589 Model: TI AM335x BeagleBone Black
372 02:06:04.116074 DRAM: 512 MiB
373 02:06:04.198825 Core: 160 devices, 18 uclasses, devicetree: separate
374 02:06:04.208531 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 02:06:06.231106 7[r[999;999H[6n8NAND:
376 02:06:06.231705 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 02:06:06.236099 Trying to boot from MMC1
378 02:06:06.809243
379 02:06:06.809842
380 02:06:06.810265 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 02:06:06.810676
382 02:06:06.814537 CPU : AM335X-GP rev 2.1
383 02:06:06.814986 Model: TI AM335x BeagleBone Black
384 02:06:06.817518 DRAM: 512 MiB
385 02:06:06.900249 Core: 160 devices, 18 uclasses, devicetree: separate
386 02:06:06.910834 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 02:06:07.414919 7[r[999;999H[6n8NAND: 0 MiB
388 02:06:07.426241 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 02:06:07.498022 Loading Environment from FAT... Unable to use mmc 0:1...
390 02:06:07.519526 <ethaddr> not set. Validating first E-fuse MAC
391 02:06:07.549883 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 02:06:07.608369 Hit any key to stop autoboot: 2
394 02:06:07.609186 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 02:06:07.609792 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
396 02:06:07.610271 Setting prompt string to ['=>']
397 02:06:07.610759 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
398 02:06:07.618308 0
399 02:06:07.619209 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 02:06:07.619701 Sending with 10 millisecond of delay
402 02:06:08.754466 => setenv autoload no
403 02:06:08.765279 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
404 02:06:08.770197 setenv autoload no
405 02:06:08.770917 Sending with 10 millisecond of delay
407 02:06:10.568676 => setenv initrd_high 0xffffffff
408 02:06:10.579674 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
409 02:06:10.580823 setenv initrd_high 0xffffffff
410 02:06:10.581713 Sending with 10 millisecond of delay
412 02:06:12.199373 => setenv fdt_high 0xffffffff
413 02:06:12.210370 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 02:06:12.211431 setenv fdt_high 0xffffffff
415 02:06:12.212357 Sending with 10 millisecond of delay
417 02:06:12.504483 => dhcp
418 02:06:12.515439 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 02:06:12.516549 dhcp
420 02:06:12.518403 link up on port 0, speed 100, full duplex
421 02:06:12.518980 BOOTP broadcast 1
422 02:06:12.543038 DHCP client bound to address 192.168.6.12 (22 ms)
423 02:06:12.543945 Sending with 10 millisecond of delay
425 02:06:14.222686 => setenv serverip 192.168.6.2
426 02:06:14.236092 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
427 02:06:14.236782 setenv serverip 192.168.6.2
428 02:06:14.237578 Sending with 10 millisecond of delay
430 02:06:17.722624 => tftp 0x82000000 957239/tftp-deploy-c2gbn8dc/kernel/zImage
431 02:06:17.733423 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
432 02:06:17.734236 tftp 0x82000000 957239/tftp-deploy-c2gbn8dc/kernel/zImage
433 02:06:17.734701 link up on port 0, speed 100, full duplex
434 02:06:17.738411 Using ethernet@4a100000 device
435 02:06:17.743751 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 02:06:17.744247 Filename '957239/tftp-deploy-c2gbn8dc/kernel/zImage'.
437 02:06:17.751110 Load address: 0x82000000
438 02:06:20.056929 Loading: *################################################## 11.5 MiB
439 02:06:20.057559 5 MiB/s
440 02:06:20.057991 done
441 02:06:20.060920 Bytes transferred = 12050944 (b7e200 hex)
442 02:06:20.061702 Sending with 10 millisecond of delay
444 02:06:24.511872 => tftp 0x83000000 957239/tftp-deploy-c2gbn8dc/ramdisk/ramdisk.cpio.gz.uboot
445 02:06:24.522711 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 02:06:24.523519 tftp 0x83000000 957239/tftp-deploy-c2gbn8dc/ramdisk/ramdisk.cpio.gz.uboot
447 02:06:24.524012 link up on port 0, speed 100, full duplex
448 02:06:24.527226 Using ethernet@4a100000 device
449 02:06:24.532759 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 02:06:24.541390 Filename '957239/tftp-deploy-c2gbn8dc/ramdisk/ramdisk.cpio.gz.uboot'.
451 02:06:24.541850 Load address: 0x83000000
452 02:06:27.376260 Loading: *################################################## 14.6 MiB
453 02:06:27.376885 5.2 MiB/s
454 02:06:27.377291 done
455 02:06:27.379232 Bytes transferred = 15350637 (ea3b6d hex)
456 02:06:27.380044 Sending with 10 millisecond of delay
458 02:06:29.237626 => setenv initrd_size ${filesize}
459 02:06:29.248401 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
460 02:06:29.249356 setenv initrd_size ${filesize}
461 02:06:29.250113 Sending with 10 millisecond of delay
463 02:06:33.396515 => tftp 0x88000000 957239/tftp-deploy-c2gbn8dc/dtb/am335x-boneblack.dtb
464 02:06:33.407083 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 02:06:33.407624 tftp 0x88000000 957239/tftp-deploy-c2gbn8dc/dtb/am335x-boneblack.dtb
466 02:06:33.407860 link up on port 0, speed 100, full duplex
467 02:06:33.411764 Using ethernet@4a100000 device
468 02:06:33.417432 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 02:06:33.420750 Filename '957239/tftp-deploy-c2gbn8dc/dtb/am335x-boneblack.dtb'.
470 02:06:33.424438 Load address: 0x88000000
471 02:06:33.437928 Loading: *################################################## 68.9 KiB
472 02:06:33.445684 4.2 MiB/s
473 02:06:33.446184 done
474 02:06:33.446621 Bytes transferred = 70568 (113a8 hex)
475 02:06:33.447333 Sending with 10 millisecond of delay
477 02:06:46.639893 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/957239/extract-nfsrootfs-uuun834o,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 02:06:46.651087 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
479 02:06:46.651812 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/957239/extract-nfsrootfs-uuun834o,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 02:06:46.652432 Sending with 10 millisecond of delay
482 02:06:48.993067 => bootz 0x82000000 0x83000000 0x88000000
483 02:06:49.003852 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 02:06:49.004479 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
485 02:06:49.005466 bootz 0x82000000 0x83000000 0x88000000
486 02:06:49.006067 Kernel image @ 0x82000000 [ 0x000000 - 0xb7e200 ]
487 02:06:49.006583 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 02:06:49.011487 Image Name:
489 02:06:49.012014 Created: 2024-11-08 2:05:50 UTC
490 02:06:49.020400 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 02:06:49.020896 Data Size: 15350573 Bytes = 14.6 MiB
492 02:06:49.028800 Load Address: 00000000
493 02:06:49.029294 Entry Point: 00000000
494 02:06:49.203430 Verifying Checksum ... OK
495 02:06:49.204093 ## Flattened Device Tree blob at 88000000
496 02:06:49.210035 Booting using the fdt blob at 0x88000000
497 02:06:49.213915 Using Device Tree in place at 88000000, end 880143a7
498 02:06:49.227547
499 02:06:49.228083 Starting kernel ...
500 02:06:49.228509
501 02:06:49.229382 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 02:06:49.229962 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
503 02:06:49.230450 Setting prompt string to ['Linux version [0-9]']
504 02:06:49.230934 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 02:06:49.231434 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 02:06:50.120233 [ 0.000000] Booting Linux on physical CPU 0x0
507 02:06:50.126652 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
508 02:06:50.127213 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 02:06:50.127688 Setting prompt string to []
510 02:06:50.128225 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 02:06:50.128693 Using line separator: #'\n'#
512 02:06:50.129104 No login prompt set.
513 02:06:50.129533 Parsing kernel messages
514 02:06:50.129927 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 02:06:50.130712 [login-action] Waiting for messages, (timeout 00:04:01)
516 02:06:50.131158 Waiting using forced prompt support (timeout 00:02:00)
517 02:06:50.137735 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j367761-arm-clang-15-multi-v7-defconfig-rs45f) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Fri Nov 8 01:18:01 UTC 2024
518 02:06:50.143253 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 02:06:50.154550 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 02:06:50.160327 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 02:06:50.166003 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 02:06:50.171671 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 02:06:50.179121 [ 0.000000] Memory policy: Data cache writeback
524 02:06:50.179593 [ 0.000000] efi: UEFI not found.
525 02:06:50.185430 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 02:06:50.191866 [ 0.000000] Zone ranges:
527 02:06:50.197690 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 02:06:50.203493 [ 0.000000] Normal empty
529 02:06:50.203963 [ 0.000000] HighMem empty
530 02:06:50.209072 [ 0.000000] Movable zone start for each node
531 02:06:50.209540 [ 0.000000] Early memory node ranges
532 02:06:50.220650 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 02:06:50.225700 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 02:06:50.243900 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 02:06:50.248598 [ 0.000000] AM335X ES2.1 (sgx neon)
536 02:06:50.261482 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
537 02:06:50.279116 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/957239/extract-nfsrootfs-uuun834o,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 02:06:50.290644 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 02:06:50.296537 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 02:06:50.302175 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 02:06:50.312218 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 02:06:50.341524 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 02:06:50.347553 <6>[ 0.000000] trace event string verifier disabled
544 02:06:50.348081 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 02:06:50.353202 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 02:06:50.364584 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 02:06:50.370251 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 02:06:50.377722 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 02:06:50.392593 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 02:06:50.411001 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 02:06:50.416794 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 02:06:50.521282 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 02:06:50.532741 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 02:06:50.539657 <6>[ 0.008339] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 02:06:50.552682 <6>[ 0.019239] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 02:06:50.560665 <6>[ 0.034603] Console: colour dummy device 80x30
557 02:06:50.566862 Matched prompt #6: WARNING:
558 02:06:50.567383 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 02:06:50.572271 <3>[ 0.039596] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 02:06:50.574917 <3>[ 0.046582] This ensures that you still see kernel messages. Please
561 02:06:50.580204 <3>[ 0.053309] update your kernel commandline.
562 02:06:50.621130 <6>[ 0.057924] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 02:06:50.626964 <6>[ 0.096250] CPU: Testing write buffer coherency: ok
564 02:06:50.629789 <6>[ 0.101624] CPU0: Spectre v2: using BPIALL workaround
565 02:06:50.635599 <6>[ 0.107090] pid_max: default: 32768 minimum: 301
566 02:06:50.641336 <6>[ 0.112288] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 02:06:50.649807 <6>[ 0.120116] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 02:06:50.657009 <6>[ 0.129563] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 02:06:50.671336 <6>[ 0.136554] Setting up static identity map for 0x80300000 - 0x803000ac
570 02:06:50.677073 <6>[ 0.146394] rcu: Hierarchical SRCU implementation.
571 02:06:50.680487 <6>[ 0.151676] rcu: Max phase no-delay instances is 1000.
572 02:06:50.689615 <6>[ 0.163319] EFI services will not be available.
573 02:06:50.695408 <6>[ 0.168607] smp: Bringing up secondary CPUs ...
574 02:06:50.701127 <6>[ 0.173666] smp: Brought up 1 node, 1 CPU
575 02:06:50.707019 <6>[ 0.178066] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 02:06:50.712972 <6>[ 0.184832] CPU: All CPU(s) started in SVC mode.
577 02:06:50.732226 <6>[ 0.190032] Memory: 404432K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50616K reserved, 65536K cma-reserved, 0K highmem)
578 02:06:50.732731 <6>[ 0.206326] devtmpfs: initialized
579 02:06:50.756527 <6>[ 0.224451] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 02:06:50.768003 <6>[ 0.233067] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 02:06:50.773896 <6>[ 0.243527] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 02:06:50.784725 <6>[ 0.255834] pinctrl core: initialized pinctrl subsystem
583 02:06:50.794587 <6>[ 0.266889] DMI not present or invalid.
584 02:06:50.802814 <6>[ 0.272789] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 02:06:50.812285 <6>[ 0.281788] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 02:06:50.827725 <6>[ 0.293508] thermal_sys: Registered thermal governor 'step_wise'
587 02:06:50.828410 <6>[ 0.293704] cpuidle: using governor menu
588 02:06:50.855230 <6>[ 0.329284] No ATAGs?
589 02:06:50.860389 <6>[ 0.332026] hw-breakpoint: debug architecture 0x4 unsupported.
590 02:06:50.870952 <6>[ 0.344275] Serial: AMBA PL011 UART driver
591 02:06:50.901920 <6>[ 0.375872] iommu: Default domain type: Translated
592 02:06:50.910949 <6>[ 0.381227] iommu: DMA domain TLB invalidation policy: strict mode
593 02:06:50.938180 <5>[ 0.410852] SCSI subsystem initialized
594 02:06:50.951591 <6>[ 0.420063] usbcore: registered new interface driver usbfs
595 02:06:50.958557 <6>[ 0.426028] usbcore: registered new interface driver hub
596 02:06:50.959081 <6>[ 0.431864] usbcore: registered new device driver usb
597 02:06:50.964310 <6>[ 0.438422] pps_core: LinuxPPS API ver. 1 registered
598 02:06:50.975803 <6>[ 0.443854] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 02:06:50.983627 <6>[ 0.453556] PTP clock support registered
600 02:06:50.984185 <6>[ 0.458002] EDAC MC: Ver: 3.0.0
601 02:06:51.039359 <6>[ 0.510488] scmi_core: SCMI protocol bus registered
602 02:06:51.044884 <6>[ 0.518670] vgaarb: loaded
603 02:06:51.057286 <6>[ 0.531447] clocksource: Switched to clocksource dmtimer
604 02:06:51.096677 <6>[ 0.570243] NET: Registered PF_INET protocol family
605 02:06:51.109242 <6>[ 0.575958] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 02:06:51.116191 <6>[ 0.584963] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 02:06:51.127711 <6>[ 0.593891] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 02:06:51.133370 <6>[ 0.602151] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 02:06:51.139460 <6>[ 0.610421] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 02:06:51.144973 <6>[ 0.618148] TCP: Hash tables configured (established 4096 bind 4096)
611 02:06:51.156600 <6>[ 0.625072] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 02:06:51.162550 <6>[ 0.632114] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 02:06:51.168898 <6>[ 0.639697] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 02:06:51.250673 <6>[ 0.719035] RPC: Registered named UNIX socket transport module.
615 02:06:51.251286 <6>[ 0.725489] RPC: Registered udp transport module.
616 02:06:51.256384 <6>[ 0.730594] RPC: Registered tcp transport module.
617 02:06:51.264886 <6>[ 0.735719] RPC: Registered tcp-with-tls transport module.
618 02:06:51.270642 <6>[ 0.741643] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 02:06:51.277976 <6>[ 0.748548] PCI: CLS 0 bytes, default 64
620 02:06:51.282431 <5>[ 0.754421] Initialise system trusted keyrings
621 02:06:51.303563 <6>[ 0.775485] Trying to unpack rootfs image as initramfs...
622 02:06:51.373915 <6>[ 0.841773] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 02:06:51.377823 <6>[ 0.849291] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 02:06:51.435868 <5>[ 0.909837] NFS: Registering the id_resolver key type
625 02:06:51.441656 <5>[ 0.915498] Key type id_resolver registered
626 02:06:51.447453 <5>[ 0.920078] Key type id_legacy registered
627 02:06:51.455706 <6>[ 0.924536] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 02:06:51.461833 <6>[ 0.931739] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 02:06:51.528140 <5>[ 1.002230] Key type asymmetric registered
630 02:06:51.534103 <5>[ 1.006759] Asymmetric key parser 'x509' registered
631 02:06:51.542396 <6>[ 1.012309] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 02:06:51.548079 <6>[ 1.020199] io scheduler mq-deadline registered
633 02:06:51.553821 <6>[ 1.025177] io scheduler kyber registered
634 02:06:51.554409 <6>[ 1.029631] io scheduler bfq registered
635 02:06:51.670846 <6>[ 1.142123] ledtrig-cpu: registered to indicate activity on CPUs
636 02:06:51.963559 <6>[ 1.434768] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 02:06:52.011269 <6>[ 1.485102] msm_serial: driver initialized
638 02:06:52.017378 <6>[ 1.489894] SuperH (H)SCI(F) driver initialized
639 02:06:52.023223 <6>[ 1.495263] STMicroelectronics ASC driver initialized
640 02:06:52.027496 <6>[ 1.500872] STM32 USART driver initialized
641 02:06:52.148715 <6>[ 1.622319] brd: module loaded
642 02:06:52.193055 <6>[ 1.667327] loop: module loaded
643 02:06:52.239097 <6>[ 1.712404] CAN device driver interface
644 02:06:52.245738 <6>[ 1.717437] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 02:06:52.251412 <6>[ 1.724524] e1000e: Intel(R) PRO/1000 Network Driver
646 02:06:52.258309 <6>[ 1.729911] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 02:06:52.264112 <6>[ 1.736380] igb: Intel(R) Gigabit Ethernet Network Driver
648 02:06:52.270284 <6>[ 1.742224] igb: Copyright (c) 2007-2014 Intel Corporation.
649 02:06:52.283186 <6>[ 1.751637] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 02:06:52.288956 <6>[ 1.757710] usbcore: registered new interface driver pegasus
651 02:06:52.294742 <6>[ 1.763882] usbcore: registered new interface driver asix
652 02:06:52.300602 <6>[ 1.769738] usbcore: registered new interface driver ax88179_178a
653 02:06:52.306270 <6>[ 1.776341] usbcore: registered new interface driver cdc_ether
654 02:06:52.312070 <6>[ 1.782670] usbcore: registered new interface driver smsc75xx
655 02:06:52.317936 <6>[ 1.788892] usbcore: registered new interface driver smsc95xx
656 02:06:52.323748 <6>[ 1.795155] usbcore: registered new interface driver net1080
657 02:06:52.329510 <6>[ 1.801275] usbcore: registered new interface driver cdc_subset
658 02:06:52.335439 <6>[ 1.807691] usbcore: registered new interface driver zaurus
659 02:06:52.341981 <6>[ 1.813760] usbcore: registered new interface driver cdc_ncm
660 02:06:52.352480 <6>[ 1.823379] usbcore: registered new interface driver usb-storage
661 02:06:52.361352 <6>[ 1.834572] i2c_dev: i2c /dev entries driver
662 02:06:52.382121 <5>[ 1.852872] cpuidle: enable-method property 'ti,am3352' found operations
663 02:06:52.395778 <6>[ 1.862410] sdhci: Secure Digital Host Controller Interface driver
664 02:06:52.396365 <6>[ 1.869067] sdhci: Copyright(c) Pierre Ossman
665 02:06:52.402476 <6>[ 1.875555] Synopsys Designware Multimedia Card Interface Driver
666 02:06:52.411716 <6>[ 1.883538] sdhci-pltfm: SDHCI platform and OF driver helper
667 02:06:52.425871 <6>[ 1.893515] usbcore: registered new interface driver usbhid
668 02:06:52.426504 <6>[ 1.899543] usbhid: USB HID core driver
669 02:06:52.438812 <6>[ 1.911247] NET: Registered PF_INET6 protocol family
670 02:06:52.905417 <6>[ 2.379371] Segment Routing with IPv6
671 02:06:52.911218 <6>[ 2.383602] In-situ OAM (IOAM) with IPv6
672 02:06:52.917902 <6>[ 2.388013] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 02:06:52.925866 <6>[ 2.395348] NET: Registered PF_PACKET protocol family
674 02:06:52.931203 <6>[ 2.400833] can: controller area network core
675 02:06:52.931790 <6>[ 2.405727] NET: Registered PF_CAN protocol family
676 02:06:52.936781 <6>[ 2.410934] can: raw protocol
677 02:06:52.939521 <6>[ 2.414295] can: broadcast manager protocol
678 02:06:52.945918 <6>[ 2.418875] can: netlink gateway - max_hops=1
679 02:06:52.952154 <5>[ 2.424404] Key type dns_resolver registered
680 02:06:52.957880 <6>[ 2.429404] ThumbEE CPU extension supported.
681 02:06:52.964021 <5>[ 2.434177] Registering SWP/SWPB emulation handler
682 02:06:52.969567 <3>[ 2.439842] omap_voltage_late_init: Voltage driver support not added
683 02:06:53.180459 <5>[ 2.652147] Loading compiled-in X.509 certificates
684 02:06:53.319929 <6>[ 2.781095] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 02:06:53.326180 <6>[ 2.797860] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 02:06:53.354185 <3>[ 2.822375] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 02:06:53.547527 <3>[ 3.015660] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 02:06:53.739883 <6>[ 3.212253] OMAP GPIO hardware version 0.1
689 02:06:53.761073 <6>[ 3.231601] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 02:06:53.843025 <4>[ 3.313211] at24 2-0054: supply vcc not found, using dummy regulator
691 02:06:53.884748 <4>[ 3.355038] at24 2-0055: supply vcc not found, using dummy regulator
692 02:06:53.926040 <4>[ 3.397000] at24 2-0056: supply vcc not found, using dummy regulator
693 02:06:53.964332 <4>[ 3.434559] at24 2-0057: supply vcc not found, using dummy regulator
694 02:06:54.004830 <6>[ 3.475821] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 02:06:54.062072 <3>[ 3.528991] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 02:06:54.087051 <6>[ 3.550363] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 02:06:54.109571 <4>[ 3.577033] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 02:06:54.117351 <4>[ 3.586279] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 02:06:54.202133 <6>[ 3.676019] Freeing initrd memory: 14992K
700 02:06:54.210400 <6>[ 3.680691] omap_rng 48310000.rng: Random Number Generator ver. 20
701 02:06:54.234572 <5>[ 3.707643] random: crng init done
702 02:06:54.281754 <6>[ 3.751458] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 02:06:54.336109 <6>[ 3.803906] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 02:06:54.341861 <6>[ 3.814252] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 02:06:54.353548 <6>[ 3.821591] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 02:06:54.359452 <6>[ 3.829071] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 02:06:54.370932 <6>[ 3.837210] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 02:06:54.378403 <6>[ 3.848854] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
709 02:06:54.391561 <5>[ 3.857963] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 02:06:54.420144 <3>[ 3.888551] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 02:06:54.425931 <6>[ 3.897172] edma 49000000.dma: TI EDMA DMA engine driver
712 02:06:54.499555 <3>[ 3.967308] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 02:06:54.514937 <6>[ 3.982266] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 02:06:54.527887 <3>[ 3.999405] l3-aon-clkctrl:0000:0: failed to disable
715 02:06:54.582013 <6>[ 4.050349] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 02:06:54.587736 <6>[ 4.059866] printk: legacy console [ttyS0] enabled
717 02:06:54.593383 <6>[ 4.059866] printk: legacy console [ttyS0] enabled
718 02:06:54.599188 <6>[ 4.070207] printk: legacy bootconsole [omap8250] disabled
719 02:06:54.605036 <6>[ 4.070207] printk: legacy bootconsole [omap8250] disabled
720 02:06:54.634896 <4>[ 4.102301] tps65217-pmic: Failed to locate of_node [id: -1]
721 02:06:54.638486 <4>[ 4.109699] tps65217-bl: Failed to locate of_node [id: -1]
722 02:06:54.655590 <6>[ 4.130032] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 02:06:54.676169 <6>[ 4.137053] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 02:06:54.687755 <6>[ 4.150762] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 02:06:54.690586 <6>[ 4.162666] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 02:06:54.714319 <6>[ 4.183046] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 02:06:54.720241 <6>[ 4.192231] sdhci-omap 48060000.mmc: Got CD GPIO
728 02:06:54.728279 <4>[ 4.197378] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 02:06:54.743262 <4>[ 4.211227] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 02:06:54.749656 <4>[ 4.220010] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 02:06:54.759477 <4>[ 4.228675] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 02:06:54.883447 <6>[ 4.353806] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 02:06:54.933224 <6>[ 4.401613] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 02:06:54.939810 <6>[ 4.410175] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 02:06:54.948963 <6>[ 4.419189] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 02:06:54.996491 <6>[ 4.461373] mmc0: new high speed SDHC card at address 1234
737 02:06:54.997153 <6>[ 4.468834] mmcblk0: mmc0:1234 SA32G 29.1 GiB
738 02:06:55.003419 <6>[ 4.477566] mmcblk0: p1
739 02:06:55.036489 <6>[ 4.502615] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
740 02:06:55.061858 <6>[ 4.527113] mmc1: new high speed MMC card at address 0001
741 02:06:55.062436 <6>[ 4.535081] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
742 02:06:55.072048 <6>[ 4.544575] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
743 02:06:55.080809 <6>[ 4.552811] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
744 02:06:55.089899 <6>[ 4.560396] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
745 02:06:57.124097 <6>[ 6.592510] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 02:06:57.197631 <5>[ 6.631538] Sending DHCP requests ., OK
747 02:06:57.208670 <6>[ 6.675977] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
748 02:06:57.209220 <6>[ 6.684114] IP-Config: Complete:
749 02:06:57.222840 <6>[ 6.687650] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
750 02:06:57.228534 <6>[ 6.698187] host=192.168.6.12, domain=, nis-domain=(none)
751 02:06:57.231738 <6>[ 6.704406] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
752 02:06:57.238503 <6>[ 6.704442] nameserver0=10.255.253.1
753 02:06:57.244490 <6>[ 6.717075] clk: Disabling unused clocks
754 02:06:57.250192 <6>[ 6.721852] PM: genpd: Disabling unused power domains
755 02:06:57.268587 <6>[ 6.739291] Freeing unused kernel image (initmem) memory: 2048K
756 02:06:57.275898 <6>[ 6.749129] Run /init as init process
757 02:06:57.298784 Loading, please wait...
758 02:06:57.377379 Starting systemd-udevd version 252.22-1~deb12u1
759 02:07:00.440751 <4>[ 9.908067] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 02:07:00.541245 <4>[ 10.008575] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 02:07:00.706947 <6>[ 10.181755] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
762 02:07:00.717679 <6>[ 10.187443] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
763 02:07:00.941114 <6>[ 10.414354] hub 1-0:1.0: USB hub found
764 02:07:01.008248 <6>[ 10.481313] hub 1-0:1.0: 1 port detected
765 02:07:01.251273 <6>[ 10.724216] tda998x 0-0070: found TDA19988
766 02:07:04.229304 Begin: Loading essential drivers ... done.
767 02:07:04.234749 Begin: Running /scripts/init-premount ... done.
768 02:07:04.240462 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
769 02:07:04.256856 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
770 02:07:04.257351 Device /sys/class/net/eth0 found
771 02:07:04.257750 done.
772 02:07:04.317297 Begin: Waiting up to 180 secs for any network device to become available ... done.
773 02:07:04.390061 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
774 02:07:04.414862 IP-Config: eth0 guessed broadcast address 192.168.6.255
775 02:07:04.420479 IP-Config: eth0 complete (dhcp from 192.168.6.1):
776 02:07:04.426030 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
777 02:07:04.437238 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
778 02:07:04.437715 rootserver: 192.168.6.1 rootpath:
779 02:07:04.440812 filename :
780 02:07:04.551188 done.
781 02:07:04.568286 Begin: Running /scripts/nfs-bottom ... done.
782 02:07:04.639853 Begin: Running /scripts/init-bottom ... done.
783 02:07:06.295502 <30>[ 15.766183] systemd[1]: System time before build time, advancing clock.
784 02:07:06.459955 <30>[ 15.905434] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 02:07:06.472706 <30>[ 15.945238] systemd[1]: Detected architecture arm.
786 02:07:06.486189
787 02:07:06.486676 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 02:07:06.487092
789 02:07:06.509624 <30>[ 15.981251] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 02:07:08.762748 <30>[ 18.233167] systemd[1]: Queued start job for default target graphical.target.
791 02:07:08.779933 <30>[ 18.247977] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 02:07:08.786681 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 02:07:08.817207 <30>[ 18.284285] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 02:07:08.824664 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 02:07:08.849249 <30>[ 18.317786] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 02:07:08.862486 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 02:07:08.884793 <30>[ 18.353383] systemd[1]: Created slice user.slice - User and Session Slice.
798 02:07:08.891516 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 02:07:08.920223 <30>[ 18.382836] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 02:07:08.925377 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 02:07:08.944182 <30>[ 18.412605] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 02:07:08.954059 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 02:07:08.984515 <30>[ 18.442364] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 02:07:08.990939 <30>[ 18.462757] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 02:07:08.999459 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 02:07:09.023160 <30>[ 18.491960] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 02:07:09.031394 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 02:07:09.053747 <30>[ 18.522265] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 02:07:09.062222 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 02:07:09.084072 <30>[ 18.552576] systemd[1]: Reached target paths.target - Path Units.
811 02:07:09.088571 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 02:07:09.113404 <30>[ 18.582127] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 02:07:09.119816 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 02:07:09.143304 <30>[ 18.611995] systemd[1]: Reached target slices.target - Slice Units.
815 02:07:09.148714 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 02:07:09.173341 <30>[ 18.642156] systemd[1]: Reached target swap.target - Swaps.
817 02:07:09.177435 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 02:07:09.203691 <30>[ 18.672218] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 02:07:09.211601 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 02:07:09.234541 <30>[ 18.703018] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 02:07:09.242848 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 02:07:09.325878 <30>[ 18.790480] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 02:07:09.339675 <30>[ 18.808090] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 02:07:09.348108 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 02:07:09.375754 <30>[ 18.845885] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 02:07:09.387681 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 02:07:09.417282 <30>[ 18.884340] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 02:07:09.424249 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 02:07:09.460230 <30>[ 18.929401] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 02:07:09.472611 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 02:07:09.495278 <30>[ 18.963476] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 02:07:09.503801 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 02:07:09.530748 <30>[ 18.993227] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 02:07:09.547401 <30>[ 19.009917] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 02:07:09.596748 <30>[ 19.067179] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 02:07:09.622573 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 02:07:09.673883 <30>[ 19.143295] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 02:07:09.700270 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 02:07:09.774299 <30>[ 19.242701] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 02:07:09.803721 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 02:07:09.864747 <30>[ 19.334539] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 02:07:09.892928 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 02:07:09.953613 <30>[ 19.423078] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 02:07:09.970834 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 02:07:10.031948 <30>[ 19.502846] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 02:07:10.061066 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 02:07:10.115653 <30>[ 19.584328] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 02:07:10.144440 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 02:07:10.195311 <30>[ 19.664991] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 02:07:10.222076 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 02:07:10.272360 <30>[ 19.742763] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 02:07:10.289890 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 02:07:10.321373 <28>[ 19.785907] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 02:07:10.333703 <28>[ 19.802616] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 02:07:10.383560 <30>[ 19.852511] systemd[1]: Starting systemd-journald.service - Journal Service...
856 02:07:10.389161 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 02:07:10.465472 <30>[ 19.934935] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 02:07:10.483918 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 02:07:10.514068 <30>[ 19.983616] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 02:07:10.568521 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 02:07:10.627049 <30>[ 20.096103] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 02:07:10.683629 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 02:07:10.755833 <30>[ 20.225617] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 02:07:10.802277 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 02:07:10.891767 <30>[ 20.361370] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 02:07:10.916728 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 02:07:10.927954 <30>[ 20.397668] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 02:07:10.973047 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 02:07:10.996410 <30>[ 20.465030] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 02:07:11.035429 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 02:07:11.203049 <30>[ 20.674408] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 02:07:11.233994 <30>[ 20.703225] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 02:07:11.262894 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 02:07:11.293738 <30>[ 20.764339] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
875 02:07:11.323618 <30>[ 20.793279] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
876 02:07:11.344671 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 02:07:11.372217 <30>[ 20.843430] systemd[1]: Started systemd-journald.service - Journal Service.
878 02:07:11.391661 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
879 02:07:11.432071 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
880 02:07:11.464623 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
881 02:07:11.497921 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
882 02:07:11.534375 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
883 02:07:11.563193 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
884 02:07:11.593343 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
885 02:07:11.615611 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
886 02:07:11.642368 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
887 02:07:11.691798 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
888 02:07:11.738121 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
889 02:07:11.804989 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
890 02:07:11.857148 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
891 02:07:11.915873 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
892 02:07:12.054812 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
893 02:07:12.211894 <46>[ 21.682541] systemd-journald[163]: Received client request to flush runtime journal.
894 02:07:12.254383 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
895 02:07:12.347407 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
896 02:07:13.142374 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
897 02:07:13.208734 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
898 02:07:14.067224 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
899 02:07:14.155668 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
900 02:07:14.192880 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
901 02:07:14.211889 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
902 02:07:14.285205 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
903 02:07:14.331758 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
904 02:07:15.283797 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
905 02:07:15.365351 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
906 02:07:16.272440 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
907 02:07:17.683146 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
908 02:07:18.206757 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
909 02:07:18.592936 <5>[ 28.064113] cfg80211: Loading compiled-in X.509 certificates for regulatory database
910 02:07:19.927491 <5>[ 29.400762] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
911 02:07:20.003013 <5>[ 29.474856] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
912 02:07:20.021782 <4>[ 29.491981] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
913 02:07:20.026700 <6>[ 29.500957] cfg80211: failed to load regulatory.db
914 02:07:20.608880 [[0m[0;31m* [0m] Job systemd-networkd.service/start running (11s / 1min 36s)
915 02:07:20.876309 M
[K[[0;1;31m*[0m[0;31m* [0m] Job systemd-networkd.service/start running (12s / 1min 36s)
916 02:07:20.910752 M
[K[[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
917 02:07:28.173420 [K[[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
918 02:07:28.203668 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
919 02:07:28.223821 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
920 02:07:28.281813 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
921 02:07:28.333548 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
922 02:07:28.385580 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
923 02:07:28.442481 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
924 02:07:28.532212 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
925 02:07:28.570257 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
926 02:07:28.626739 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
927 02:07:28.672037 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
928 02:07:28.694930 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
929 02:07:28.741340 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
930 02:07:28.934598 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
931 02:07:29.234947 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
932 02:07:29.263215 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
933 02:07:29.286095 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
934 02:07:29.303442 <46>[ 38.764144] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
935 02:07:29.314898 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
936 02:07:29.328227 <46>[ 38.791104] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
937 02:07:29.364578 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
938 02:07:29.404612 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
939 02:07:29.432285 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
940 02:07:30.127488 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
941 02:07:30.580586 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
942 02:07:30.610576 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
943 02:07:30.913220 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
944 02:07:30.931307 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
945 02:07:31.037301 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
946 02:07:31.198650 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
947 02:07:31.254429 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
948 02:07:31.886322 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
949 02:07:32.131961 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
950 02:07:32.174483 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
951 02:07:32.224797 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
952 02:07:32.270743 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
953 02:07:32.459373 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
954 02:07:32.532459 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
955 02:07:32.593734 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
956 02:07:32.614355 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
957 02:07:32.850608 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
958 02:07:32.947885 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
959 02:07:33.363773 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
960 02:07:33.414008 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
961 02:07:33.446590 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
962 02:07:33.536071 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
963 02:07:33.709805 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
964 02:07:33.823605
965 02:07:33.826403 Debian GNU/Linux 12 debiaworm-armhf login: root (automatic login)
966 02:07:33.826889
967 02:07:34.142850 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Fri Nov 8 01:18:01 UTC 2024 armv7l
968 02:07:34.143431
969 02:07:34.148501 The programs included with the Debian GNU/Linux system are free software;
970 02:07:34.151750 the exact distribution terms for each program are described in the
971 02:07:34.157362 individual files in /usr/share/doc/*/copyright.
972 02:07:34.157892
973 02:07:34.162917 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
974 02:07:34.166730 permitted by applicable law.
975 02:07:38.836659 Unable to match end of the kernel message
977 02:07:38.837580 Setting prompt string to ['/ #']
978 02:07:38.837904 end: 2.4.4.1 login-action (duration 00:00:49) [common]
980 02:07:38.838655 end: 2.4.4 auto-login-action (duration 00:00:50) [common]
981 02:07:38.838944 start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
982 02:07:38.839175 Setting prompt string to ['/ #']
983 02:07:38.839386 Forcing a shell prompt, looking for ['/ #']
985 02:07:38.889925 / #
986 02:07:38.890530 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
987 02:07:38.890811 Waiting using forced prompt support (timeout 00:02:30)
988 02:07:38.894044
989 02:07:38.900326 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
990 02:07:38.900664 start: 2.4.6 export-device-env (timeout 00:03:12) [common]
991 02:07:38.900908 Sending with 10 millisecond of delay
993 02:07:43.887922 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/957239/extract-nfsrootfs-uuun834o'
994 02:07:43.898963 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/957239/extract-nfsrootfs-uuun834o'
995 02:07:43.899846 Sending with 10 millisecond of delay
997 02:07:45.997780 / # export NFS_SERVER_IP='192.168.6.2'
998 02:07:46.008683 export NFS_SERVER_IP='192.168.6.2'
999 02:07:46.009639 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1000 02:07:46.010276 end: 2.4 uboot-commands (duration 00:01:55) [common]
1001 02:07:46.010869 end: 2 uboot-action (duration 00:01:55) [common]
1002 02:07:46.011429 start: 3 lava-test-retry (timeout 00:06:54) [common]
1003 02:07:46.012045 start: 3.1 lava-test-shell (timeout 00:06:54) [common]
1004 02:07:46.012518 Using namespace: common
1006 02:07:46.113699 / # #
1007 02:07:46.114555 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1008 02:07:46.118001 #
1009 02:07:46.124677 Using /lava-957239
1011 02:07:46.225805 / # export SHELL=/bin/bash
1012 02:07:46.229963 export SHELL=/bin/bash
1014 02:07:46.337303 / # . /lava-957239/environment
1015 02:07:46.341499 . /lava-957239/environment
1017 02:07:46.455223 / # /lava-957239/bin/lava-test-runner /lava-957239/0
1018 02:07:46.456150 Test shell timeout: 10s (minimum of the action and connection timeout)
1019 02:07:46.459468 /lava-957239/bin/lava-test-runner /lava-957239/0
1020 02:07:46.859064 + export TESTRUN_ID=0_timesync-off
1021 02:07:46.866288 + TESTRUN_ID=0_timesync-off
1022 02:07:46.866768 + cd /lava-957239/0/tests/0_timesync-off
1023 02:07:46.867195 ++ cat uuid
1024 02:07:46.884044 + UUID=957239_1.6.2.4.1
1025 02:07:46.884513 + set +x
1026 02:07:46.891533 <LAVA_SIGNAL_STARTRUN 0_timesync-off 957239_1.6.2.4.1>
1027 02:07:46.892020 + systemctl stop systemd-timesyncd
1028 02:07:46.892726 Received signal: <STARTRUN> 0_timesync-off 957239_1.6.2.4.1
1029 02:07:46.893156 Starting test lava.0_timesync-off (957239_1.6.2.4.1)
1030 02:07:46.893667 Skipping test definition patterns.
1031 02:07:47.207947 + set +x
1032 02:07:47.208546 <LAVA_SIGNAL_ENDRUN 0_timesync-off 957239_1.6.2.4.1>
1033 02:07:47.209228 Received signal: <ENDRUN> 0_timesync-off 957239_1.6.2.4.1
1034 02:07:47.209719 Ending use of test pattern.
1035 02:07:47.210130 Ending test lava.0_timesync-off (957239_1.6.2.4.1), duration 0.32
1037 02:07:47.380196 + export TESTRUN_ID=1_kselftest-dt
1038 02:07:47.387100 + TESTRUN_ID=1_kselftest-dt
1039 02:07:47.387567 + cd /lava-957239/0/tests/1_kselftest-dt
1040 02:07:47.388021 ++ cat uuid
1041 02:07:47.405880 + UUID=957239_1.6.2.4.5
1042 02:07:47.406379 + set +x
1043 02:07:47.411453 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 957239_1.6.2.4.5>
1044 02:07:47.411922 + cd ./automated/linux/kselftest/
1045 02:07:47.412647 Received signal: <STARTRUN> 1_kselftest-dt 957239_1.6.2.4.5
1046 02:07:47.413075 Starting test lava.1_kselftest-dt (957239_1.6.2.4.5)
1047 02:07:47.413560 Skipping test definition patterns.
1048 02:07:47.438743 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1049 02:07:47.558215 INFO: install_deps skipped
1050 02:07:48.145511 --2024-11-08 02:07:48-- http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1051 02:07:48.169370 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1052 02:07:48.310284 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1053 02:07:48.451575 HTTP request sent, awaiting response... 200 OK
1054 02:07:48.452171 Length: 2542220 (2.4M) [application/octet-stream]
1055 02:07:48.457061 Saving to: 'kselftest_armhf.tar.gz'
1056 02:07:48.457521
1057 02:07:49.487314
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 2%[ ] 49.92K 180KB/s
kselftest_armhf.tar 8%[> ] 217.70K 394KB/s
kselftest_armhf.tar 35%[======> ] 889.89K 1.05MB/s
kselftest_armhf.tar 100%[===================>] 2.42M 2.35MB/s in 1.0s
1058 02:07:49.487957
1059 02:07:49.900597 2024-11-08 02:07:49 (2.35 MB/s) - 'kselftest_armhf.tar.gz' saved [2542220/2542220]
1060 02:07:49.901185
1061 02:08:01.123859 skiplist:
1062 02:08:01.124523 ========================================
1063 02:08:01.129541 ========================================
1064 02:08:01.230036 dt:test_unprobed_devices.sh
1065 02:08:01.258154 ============== Tests to run ===============
1066 02:08:01.266822 dt:test_unprobed_devices.sh
1067 02:08:01.270712 ===========End Tests to run ===============
1068 02:08:01.279275 shardfile-dt pass
1069 02:08:01.519831 <12>[ 70.995842] kselftest: Running tests in dt
1070 02:08:01.549343 TAP version 13
1071 02:08:01.574362 1..1
1072 02:08:01.631322 # timeout set to 45
1073 02:08:01.631850 # selftests: dt: test_unprobed_devices.sh
1074 02:08:02.487012 # TAP version 13
1075 02:08:27.921256 # 1..257
1076 02:08:28.104353 # ok 1 / # SKIP
1077 02:08:28.130448 # ok 2 /clk_mcasp0
1078 02:08:28.203207 # ok 3 /clk_mcasp0_fixed # SKIP
1079 02:08:28.275300 # ok 4 /cpus/cpu@0 # SKIP
1080 02:08:28.353037 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1081 02:08:28.369365 # ok 6 /fixedregulator0
1082 02:08:28.391101 # ok 7 /leds
1083 02:08:28.411802 # ok 8 /ocp
1084 02:08:28.436999 # ok 9 /ocp/interconnect@44c00000
1085 02:08:28.463684 # ok 10 /ocp/interconnect@44c00000/segment@0
1086 02:08:28.488770 # ok 11 /ocp/interconnect@44c00000/segment@100000
1087 02:08:28.513847 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1088 02:08:28.586434 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1089 02:08:28.610310 # ok 14 /ocp/interconnect@44c00000/segment@200000
1090 02:08:28.629191 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1091 02:08:28.738623 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1092 02:08:28.812926 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1093 02:08:28.886672 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1094 02:08:28.960752 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1095 02:08:29.034375 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1096 02:08:29.108169 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1097 02:08:29.185923 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1098 02:08:29.258283 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1099 02:08:29.329399 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1100 02:08:29.403421 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1101 02:08:29.475977 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1102 02:08:29.550654 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1103 02:08:29.624434 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1104 02:08:29.698404 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1105 02:08:29.770236 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1106 02:08:29.844990 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1107 02:08:29.918669 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1108 02:08:29.992861 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1109 02:08:30.065602 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1110 02:08:30.144525 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1111 02:08:30.217487 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1112 02:08:30.287210 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1113 02:08:30.362227 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1114 02:08:30.435411 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1115 02:08:30.509776 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1116 02:08:30.583510 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1117 02:08:30.657428 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1118 02:08:30.735784 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1119 02:08:30.809442 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1120 02:08:30.884988 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1121 02:08:30.954591 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1122 02:08:31.028282 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1123 02:08:31.102738 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1124 02:08:31.176504 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1125 02:08:31.255583 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1126 02:08:31.329370 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1127 02:08:31.400796 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1128 02:08:31.474122 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1129 02:08:31.548879 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1130 02:08:31.622630 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1131 02:08:31.696773 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1132 02:08:31.770626 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1133 02:08:31.844527 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1134 02:08:31.918612 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1135 02:08:31.991440 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1136 02:08:32.072914 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1137 02:08:32.148611 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1138 02:08:32.224683 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1139 02:08:32.298910 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1140 02:08:32.373811 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1141 02:08:32.449056 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1142 02:08:32.527067 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1143 02:08:32.598712 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1144 02:08:32.675964 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1145 02:08:32.749114 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1146 02:08:32.824752 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1147 02:08:32.900247 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1148 02:08:32.972405 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1149 02:08:33.047376 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1150 02:08:33.125716 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1151 02:08:33.195810 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1152 02:08:33.273659 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1153 02:08:33.343906 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1154 02:08:33.417404 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1155 02:08:33.492504 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1156 02:08:33.565922 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1157 02:08:33.640211 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1158 02:08:33.712836 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1159 02:08:33.786503 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1160 02:08:33.860343 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1161 02:08:33.933967 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1162 02:08:34.008181 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1163 02:08:34.081572 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1164 02:08:34.157796 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1165 02:08:34.232690 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1166 02:08:34.303944 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1167 02:08:34.381913 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1168 02:08:34.454230 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1169 02:08:34.528977 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1170 02:08:34.550500 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1171 02:08:34.574763 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1172 02:08:34.599521 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1173 02:08:34.623541 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1174 02:08:34.648612 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1175 02:08:34.676607 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1176 02:08:34.698548 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1177 02:08:34.724727 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1178 02:08:34.835809 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1179 02:08:34.858901 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1180 02:08:34.881460 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1181 02:08:34.906062 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1182 02:08:35.015324 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1183 02:08:35.093081 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1184 02:08:35.166963 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1185 02:08:35.241032 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1186 02:08:35.315836 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1187 02:08:35.393081 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1188 02:08:35.465102 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1189 02:08:35.538599 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1190 02:08:35.613517 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1191 02:08:35.688342 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1192 02:08:35.762977 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1193 02:08:35.837512 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1194 02:08:35.911835 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1195 02:08:35.988726 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1196 02:08:36.070208 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1197 02:08:36.141137 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1198 02:08:36.160912 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1199 02:08:36.233716 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1200 02:08:36.305166 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1201 02:08:36.380232 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1202 02:08:36.402354 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1203 02:08:36.475746 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1204 02:08:36.499132 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1205 02:08:36.576423 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1206 02:08:36.603380 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1207 02:08:36.620746 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1208 02:08:36.644545 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1209 02:08:36.674481 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1210 02:08:36.695519 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1211 02:08:36.718406 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1212 02:08:36.744394 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1213 02:08:36.820781 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1214 02:08:36.843341 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1215 02:08:36.871876 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1216 02:08:36.941608 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1217 02:08:37.014590 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1218 02:08:37.036364 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1219 02:08:37.140234 # not ok 144 /ocp/interconnect@47c00000
1220 02:08:37.214507 # not ok 145 /ocp/interconnect@47c00000/segment@0
1221 02:08:37.240325 # ok 146 /ocp/interconnect@48000000
1222 02:08:37.263443 # ok 147 /ocp/interconnect@48000000/segment@0
1223 02:08:37.285903 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1224 02:08:37.309735 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1225 02:08:37.333369 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1226 02:08:37.357310 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1227 02:08:37.380773 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1228 02:08:37.407670 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1229 02:08:37.433989 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1230 02:08:37.505579 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1231 02:08:37.582640 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1232 02:08:37.605319 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1233 02:08:37.631636 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1234 02:08:37.655184 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1235 02:08:37.677034 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1236 02:08:37.700460 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1237 02:08:37.730137 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1238 02:08:37.749392 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1239 02:08:37.774086 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1240 02:08:37.797335 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1241 02:08:37.821942 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1242 02:08:37.845493 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1243 02:08:37.874329 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1244 02:08:37.895096 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1245 02:08:37.918147 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1246 02:08:37.940918 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1247 02:08:37.971510 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1248 02:08:37.989686 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1249 02:08:38.016235 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1250 02:08:38.036290 # ok 175 /ocp/interconnect@48000000/segment@100000
1251 02:08:38.061428 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1252 02:08:38.090571 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1253 02:08:38.162041 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1254 02:08:38.237326 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1255 02:08:38.314555 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1256 02:08:38.389195 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1257 02:08:38.460086 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1258 02:08:38.535177 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1259 02:08:38.607204 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1260 02:08:38.683026 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1261 02:08:38.702914 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1262 02:08:38.731687 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1263 02:08:38.755507 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1264 02:08:38.775079 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1265 02:08:38.804375 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1266 02:08:38.824485 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1267 02:08:38.852262 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1268 02:08:38.876127 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1269 02:08:38.900515 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1270 02:08:38.924244 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1271 02:08:38.945434 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1272 02:08:38.968527 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1273 02:08:38.993701 # ok 198 /ocp/interconnect@48000000/segment@200000
1274 02:08:39.015088 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1275 02:08:39.093867 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1276 02:08:39.113901 # ok 201 /ocp/interconnect@48000000/segment@300000
1277 02:08:39.135871 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1278 02:08:39.160389 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1279 02:08:39.184937 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1280 02:08:39.212724 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1281 02:08:39.235525 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1282 02:08:39.256107 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1283 02:08:39.330662 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1284 02:08:39.349459 # ok 209 /ocp/interconnect@4a000000
1285 02:08:39.378074 # ok 210 /ocp/interconnect@4a000000/segment@0
1286 02:08:39.403637 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1287 02:08:39.425899 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1288 02:08:39.454647 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1289 02:08:39.475021 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1290 02:08:39.550155 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1291 02:08:39.654745 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1292 02:08:39.737862 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1293 02:08:39.837075 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1294 02:08:39.909408 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1295 02:08:39.981914 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1296 02:08:40.083590 # not ok 221 /ocp/interconnect@4b140000
1297 02:08:40.161758 # not ok 222 /ocp/interconnect@4b140000/segment@0
1298 02:08:40.233851 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1299 02:08:40.251653 # ok 224 /ocp/target-module@40300000
1300 02:08:40.275519 # ok 225 /ocp/target-module@40300000/sram@0
1301 02:08:40.350868 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1302 02:08:40.429661 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1303 02:08:40.445014 # ok 228 /ocp/target-module@47400000
1304 02:08:40.473838 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1305 02:08:40.499495 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1306 02:08:40.518555 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1307 02:08:40.543275 # ok 232 /ocp/target-module@47400000/usb@1400
1308 02:08:40.569151 # ok 233 /ocp/target-module@47400000/usb@1800
1309 02:08:40.591377 # ok 234 /ocp/target-module@47810000
1310 02:08:40.609768 # ok 235 /ocp/target-module@49000000
1311 02:08:40.637961 # ok 236 /ocp/target-module@49000000/dma@0
1312 02:08:40.660256 # ok 237 /ocp/target-module@49800000
1313 02:08:40.678332 # ok 238 /ocp/target-module@49800000/dma@0
1314 02:08:40.701548 # ok 239 /ocp/target-module@49900000
1315 02:08:40.729956 # ok 240 /ocp/target-module@49900000/dma@0
1316 02:08:40.747735 # ok 241 /ocp/target-module@49a00000
1317 02:08:40.773050 # ok 242 /ocp/target-module@49a00000/dma@0
1318 02:08:40.794085 # ok 243 /ocp/target-module@4c000000
1319 02:08:40.872916 # not ok 244 /ocp/target-module@4c000000/emif@0
1320 02:08:40.892416 # ok 245 /ocp/target-module@50000000
1321 02:08:40.918225 # ok 246 /ocp/target-module@53100000
1322 02:08:40.992829 # not ok 247 /ocp/target-module@53100000/sham@0
1323 02:08:41.010068 # ok 248 /ocp/target-module@53500000
1324 02:08:41.088062 # not ok 249 /ocp/target-module@53500000/aes@0
1325 02:08:41.109904 # ok 250 /ocp/target-module@56000000
1326 02:08:41.212888 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1327 02:08:41.288606 # ok 252 /opp-table # SKIP
1328 02:08:41.361068 # ok 253 /soc # SKIP
1329 02:08:41.377015 # ok 254 /sound
1330 02:08:41.402136 # ok 255 /target-module@4b000000
1331 02:08:41.431651 # ok 256 /target-module@4b000000/target-module@140000
1332 02:08:41.448996 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1333 02:08:41.459637 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1334 02:08:41.466641 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1335 02:08:43.606804 dt_test_unprobed_devices_sh_ skip
1336 02:08:43.612341 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1337 02:08:43.617834 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1338 02:08:43.618346 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1339 02:08:43.626797 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1340 02:08:43.627265 dt_test_unprobed_devices_sh_fixedregulator0 pass
1341 02:08:43.632519 dt_test_unprobed_devices_sh_leds pass
1342 02:08:43.638234 dt_test_unprobed_devices_sh_ocp pass
1343 02:08:43.638684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1344 02:08:43.647326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1345 02:08:43.652937 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1346 02:08:43.662041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1347 02:08:43.667681 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1348 02:08:43.678828 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1349 02:08:43.684305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1350 02:08:43.695495 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1351 02:08:43.701160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1352 02:08:43.712318 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1353 02:08:43.723531 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1354 02:08:43.734747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1355 02:08:43.740419 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1356 02:08:43.751582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1357 02:08:43.762794 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1358 02:08:43.774001 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1359 02:08:43.785184 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1360 02:08:43.790816 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1361 02:08:43.802012 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1362 02:08:43.813145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1363 02:08:43.824333 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1364 02:08:43.830071 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1365 02:08:43.841123 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1366 02:08:43.852324 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1367 02:08:43.863520 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1368 02:08:43.869190 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1369 02:08:43.880315 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1370 02:08:43.891509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1371 02:08:43.902711 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1372 02:08:43.913916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1373 02:08:43.925063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1374 02:08:43.930730 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1375 02:08:43.941909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1376 02:08:43.953061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1377 02:08:43.964285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1378 02:08:43.975517 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1379 02:08:43.986712 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1380 02:08:43.997943 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1381 02:08:44.009075 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1382 02:08:44.020276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1383 02:08:44.031456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1384 02:08:44.042678 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1385 02:08:44.053849 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1386 02:08:44.065089 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1387 02:08:44.076250 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1388 02:08:44.087403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1389 02:08:44.098623 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1390 02:08:44.109793 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1391 02:08:44.121077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1392 02:08:44.132234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1393 02:08:44.143403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1394 02:08:44.154571 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1395 02:08:44.165758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1396 02:08:44.176968 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1397 02:08:44.188213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1398 02:08:44.199348 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1399 02:08:44.205098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1400 02:08:44.216203 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1401 02:08:44.227329 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1402 02:08:44.238518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1403 02:08:44.249722 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1404 02:08:44.260862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1405 02:08:44.272178 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1406 02:08:44.283281 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1407 02:08:44.294465 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1408 02:08:44.305669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1409 02:08:44.316887 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1410 02:08:44.328162 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1411 02:08:44.339251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1412 02:08:44.350429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1413 02:08:44.361612 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1414 02:08:44.372831 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1415 02:08:44.384036 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1416 02:08:44.395175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1417 02:08:44.406526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1418 02:08:44.412161 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1419 02:08:44.423188 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1420 02:08:44.434367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1421 02:08:44.445579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1422 02:08:44.456762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1423 02:08:44.468011 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1424 02:08:44.479109 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1425 02:08:44.490291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1426 02:08:44.501500 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1427 02:08:44.512685 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1428 02:08:44.523884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1429 02:08:44.535127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1430 02:08:44.540690 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1431 02:08:44.551831 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1432 02:08:44.563075 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1433 02:08:44.568676 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1434 02:08:44.579694 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1435 02:08:44.590978 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1436 02:08:44.596541 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1437 02:08:44.607830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1438 02:08:44.613451 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1439 02:08:44.624558 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1440 02:08:44.635771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1441 02:08:44.647001 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1442 02:08:44.658179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1443 02:08:44.669340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1444 02:08:44.680547 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1445 02:08:44.691737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1446 02:08:44.703002 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1447 02:08:44.714138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1448 02:08:44.725326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1449 02:08:44.742141 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1450 02:08:44.753307 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1451 02:08:44.764522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1452 02:08:44.775689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1453 02:08:44.786903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1454 02:08:44.803661 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1455 02:08:44.814861 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1456 02:08:44.826161 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1457 02:08:44.837252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1458 02:08:44.848439 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1459 02:08:44.859641 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1460 02:08:44.865282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1461 02:08:44.876447 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1462 02:08:44.882082 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1463 02:08:44.893206 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1464 02:08:44.898854 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1465 02:08:44.910032 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1466 02:08:44.915623 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1467 02:08:44.926792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1468 02:08:44.932441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1469 02:08:44.943564 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1470 02:08:44.949198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1471 02:08:44.960376 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1472 02:08:44.971550 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1473 02:08:44.982747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1474 02:08:44.993931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1475 02:08:45.005167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1476 02:08:45.010794 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1477 02:08:45.021927 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1478 02:08:45.027609 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1479 02:08:45.033243 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1480 02:08:45.038752 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1481 02:08:45.044356 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1482 02:08:45.049967 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1483 02:08:45.061183 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1484 02:08:45.066738 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1485 02:08:45.077893 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1486 02:08:45.083521 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1487 02:08:45.094675 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1488 02:08:45.100355 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1489 02:08:45.105925 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1490 02:08:45.117170 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1491 02:08:45.122728 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1492 02:08:45.133866 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1493 02:08:45.139520 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1494 02:08:45.150676 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1495 02:08:45.156338 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1496 02:08:45.167453 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1497 02:08:45.173104 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1498 02:08:45.184282 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1499 02:08:45.189906 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1500 02:08:45.201109 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1501 02:08:45.206687 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1502 02:08:45.212286 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1503 02:08:45.223396 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1504 02:08:45.229070 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1505 02:08:45.240284 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1506 02:08:45.245847 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1507 02:08:45.256977 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1508 02:08:45.262627 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1509 02:08:45.273755 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1510 02:08:45.279450 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1511 02:08:45.290559 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1512 02:08:45.296318 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1513 02:08:45.307347 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1514 02:08:45.318559 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1515 02:08:45.329747 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1516 02:08:45.340937 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1517 02:08:45.352112 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1518 02:08:45.363300 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1519 02:08:45.374532 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1520 02:08:45.385672 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1521 02:08:45.391311 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1522 02:08:45.396903 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1523 02:08:45.408145 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1524 02:08:45.413770 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1525 02:08:45.424863 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1526 02:08:45.436149 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1527 02:08:45.441681 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1528 02:08:45.452823 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1529 02:08:45.458493 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1530 02:08:45.469621 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1531 02:08:45.475292 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1532 02:08:45.480848 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1533 02:08:45.492027 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1534 02:08:45.497602 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1535 02:08:45.503271 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1536 02:08:45.514331 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1537 02:08:45.519974 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1538 02:08:45.531237 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1539 02:08:45.536763 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1540 02:08:45.547955 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1541 02:08:45.553549 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1542 02:08:45.564691 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1543 02:08:45.570554 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1544 02:08:45.575881 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1545 02:08:45.581465 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1546 02:08:45.592603 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1547 02:08:45.603907 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1548 02:08:45.609558 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1549 02:08:45.620701 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1550 02:08:45.626427 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1551 02:08:45.637504 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1552 02:08:45.648726 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1553 02:08:45.659904 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1554 02:08:45.665582 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1555 02:08:45.671200 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1556 02:08:45.676780 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1557 02:08:45.688016 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1558 02:08:45.688542 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1559 02:08:45.699308 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1560 02:08:45.704855 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1561 02:08:45.710567 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1562 02:08:45.716277 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1563 02:08:45.721744 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1564 02:08:45.732893 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1565 02:08:45.738546 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1566 02:08:45.744258 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1567 02:08:45.749754 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1568 02:08:45.755367 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1569 02:08:45.760922 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1570 02:08:45.766534 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1571 02:08:45.772241 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1572 02:08:45.777727 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1573 02:08:45.783319 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1574 02:08:45.788932 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1575 02:08:45.794631 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1576 02:08:45.800148 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1577 02:08:45.805740 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1578 02:08:45.811326 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1579 02:08:45.816899 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1580 02:08:45.822513 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1581 02:08:45.828129 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1582 02:08:45.833749 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1583 02:08:45.839366 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1584 02:08:45.844954 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1585 02:08:45.850546 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1586 02:08:45.856175 dt_test_unprobed_devices_sh_opp-table skip
1587 02:08:45.856646 dt_test_unprobed_devices_sh_soc skip
1588 02:08:45.861750 dt_test_unprobed_devices_sh_sound pass
1589 02:08:45.867334 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1590 02:08:45.872922 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1591 02:08:45.878557 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1592 02:08:45.884228 dt_test_unprobed_devices_sh fail
1593 02:08:45.884703 + ../../utils/send-to-lava.sh ./output/result.txt
1594 02:08:45.892684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1595 02:08:45.893625 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1597 02:08:45.922425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1598 02:08:45.923207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1600 02:08:46.013431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1601 02:08:46.014292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1603 02:08:46.108436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1604 02:08:46.109267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1606 02:08:46.203325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1607 02:08:46.204165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1609 02:08:46.300082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1610 02:08:46.300918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1612 02:08:46.393993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1613 02:08:46.394813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1615 02:08:46.484263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1616 02:08:46.485116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1618 02:08:46.573809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1619 02:08:46.574422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1621 02:08:46.671187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1622 02:08:46.672059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1624 02:08:46.766804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1625 02:08:46.767603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1627 02:08:46.856249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1628 02:08:46.857100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1630 02:08:46.946908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1631 02:08:46.947727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1633 02:08:47.043095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1634 02:08:47.043946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1636 02:08:47.130701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1637 02:08:47.131542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1639 02:08:47.227255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1640 02:08:47.228080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1642 02:08:47.318452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1643 02:08:47.319272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1645 02:08:47.414503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1646 02:08:47.415444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1648 02:08:47.505081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1649 02:08:47.505935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1651 02:08:47.600230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1652 02:08:47.601079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1654 02:08:47.690537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1655 02:08:47.691335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1657 02:08:47.780344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1658 02:08:47.781190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1660 02:08:47.875474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1661 02:08:47.876471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1663 02:08:47.970453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1664 02:08:47.971336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1666 02:08:48.060439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1667 02:08:48.061312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1669 02:08:48.149519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1670 02:08:48.150433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1672 02:08:48.245165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1673 02:08:48.246010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1675 02:08:48.335199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1676 02:08:48.336043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1678 02:08:48.430747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1679 02:08:48.431601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1681 02:08:48.526075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1682 02:08:48.526923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1684 02:08:48.620156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1685 02:08:48.620971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1687 02:08:48.711520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1688 02:08:48.712399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1690 02:08:48.807491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1691 02:08:48.808306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1693 02:08:48.904931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1694 02:08:48.905780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1696 02:08:48.997924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1697 02:08:48.998763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1699 02:08:49.094106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1700 02:08:49.094948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1702 02:08:49.190132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1703 02:08:49.190956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1705 02:08:49.286854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1706 02:08:49.287689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1708 02:08:49.382015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1709 02:08:49.382845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1711 02:08:49.473330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1712 02:08:49.474204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1714 02:08:49.569116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1715 02:08:49.569999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1717 02:08:49.665739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1718 02:08:49.666598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1720 02:08:49.760235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1721 02:08:49.761112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1723 02:08:49.850049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1724 02:08:49.850877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1726 02:08:49.943454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1727 02:08:49.944282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1729 02:08:50.032713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1730 02:08:50.033541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1732 02:08:50.129199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1733 02:08:50.129975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1735 02:08:50.218998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1736 02:08:50.219816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1738 02:08:50.316198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1739 02:08:50.317021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1741 02:08:50.411413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1742 02:08:50.412268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1744 02:08:50.506874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1745 02:08:50.507745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1747 02:08:50.601158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1748 02:08:50.601971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1750 02:08:50.689497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1751 02:08:50.690283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1753 02:08:50.778253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1754 02:08:50.779021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1756 02:08:50.868073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1757 02:08:50.868856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1759 02:08:50.962263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1760 02:08:50.963069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1762 02:08:51.052610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1763 02:08:51.053439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1765 02:08:51.142352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1766 02:08:51.143121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1768 02:08:51.237070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1769 02:08:51.237839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1771 02:08:51.332250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1772 02:08:51.333027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1774 02:08:51.422605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1775 02:08:51.423440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1777 02:08:51.518182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1778 02:08:51.518989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1780 02:08:51.607848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1781 02:08:51.608687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1783 02:08:51.702922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1784 02:08:51.703708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1786 02:08:51.792590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1787 02:08:51.793374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1789 02:08:51.888677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1790 02:08:51.889465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1792 02:08:51.979255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1793 02:08:51.980060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1795 02:08:52.074687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1796 02:08:52.075480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1798 02:08:52.171460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1799 02:08:52.172287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1801 02:08:52.266958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1802 02:08:52.267756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1804 02:08:52.357565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1805 02:08:52.358353 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1807 02:08:52.465205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1808 02:08:52.466103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1810 02:08:52.563894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1811 02:08:52.564861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1813 02:08:52.658573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1814 02:08:52.659820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1816 02:08:52.748225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1817 02:08:52.749088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1819 02:08:52.837900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1820 02:08:52.838507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1822 02:08:52.935250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1823 02:08:52.936101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1825 02:08:53.029559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1826 02:08:53.030507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1828 02:08:53.125772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1829 02:08:53.126641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1831 02:08:53.222334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1832 02:08:53.223212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1834 02:08:53.310562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1835 02:08:53.311374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1837 02:08:53.406659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1838 02:08:53.407493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1840 02:08:53.497733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1841 02:08:53.498593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1843 02:08:53.591691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1844 02:08:53.592576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1846 02:08:53.680826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1847 02:08:53.681616 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1849 02:08:53.770209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1850 02:08:53.771036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1852 02:08:53.865722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1853 02:08:53.866499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1855 02:08:53.960797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1856 02:08:53.961584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1858 02:08:54.056496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1859 02:08:54.057317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1861 02:08:54.152117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1862 02:08:54.152959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1864 02:08:54.241739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1865 02:08:54.242555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1867 02:08:54.337244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1868 02:08:54.338031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1870 02:08:54.428242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1871 02:08:54.429133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1873 02:08:54.523039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1874 02:08:54.523859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1876 02:08:54.613143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1877 02:08:54.613949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1879 02:08:54.700235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1880 02:08:54.701037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1882 02:08:54.795444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1883 02:08:54.796228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1885 02:08:54.890356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1886 02:08:54.891181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1888 02:08:54.986553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1889 02:08:54.987344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1891 02:08:55.085752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1892 02:08:55.086548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1894 02:08:55.181472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1895 02:08:55.182262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1897 02:08:55.270638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1898 02:08:55.271440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1900 02:08:55.361864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1901 02:08:55.362654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1903 02:08:55.458516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1904 02:08:55.459384 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1906 02:08:55.548980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1907 02:08:55.549801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1909 02:08:55.645077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1910 02:08:55.645881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1912 02:08:55.739611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1913 02:08:55.740450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1915 02:08:55.835120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1916 02:08:55.835907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1918 02:08:55.933485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1919 02:08:55.934275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1921 02:08:56.022918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1922 02:08:56.023741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1924 02:08:56.113048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1925 02:08:56.113846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1927 02:08:56.208644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1928 02:08:56.209439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1930 02:08:56.303485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1931 02:08:56.304307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1933 02:08:56.400062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1934 02:08:56.400980 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1936 02:08:56.495342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1937 02:08:56.496191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1939 02:08:56.585686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1940 02:08:56.586496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1942 02:08:56.681270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1943 02:08:56.682063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1945 02:08:56.771189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1946 02:08:56.772018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1948 02:08:56.868892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1949 02:08:56.869686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1951 02:08:56.958505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1952 02:08:56.959313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1954 02:08:57.053256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1956 02:08:57.056387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1957 02:08:57.148467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1959 02:08:57.151637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1960 02:08:57.237918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1962 02:08:57.241142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1963 02:08:57.328231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1964 02:08:57.329078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1966 02:08:57.422701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1967 02:08:57.423578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1969 02:08:57.511145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1970 02:08:57.512013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1972 02:08:57.607131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1973 02:08:57.608030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1975 02:08:57.695865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1976 02:08:57.696729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1978 02:08:57.793708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1979 02:08:57.794507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1981 02:08:57.885865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1982 02:08:57.886641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1984 02:08:57.983274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1985 02:08:57.984223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1987 02:08:58.078653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1988 02:08:58.079473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1990 02:08:58.168779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1991 02:08:58.169570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1993 02:08:58.256964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1994 02:08:58.257747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1996 02:08:58.353116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1997 02:08:58.353935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1999 02:08:58.449271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2000 02:08:58.450123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2002 02:08:58.546330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2003 02:08:58.547168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2005 02:08:58.643245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2006 02:08:58.644080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2008 02:08:58.738827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2009 02:08:58.739651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2011 02:08:58.825540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2012 02:08:58.826362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2014 02:08:58.914285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2015 02:08:58.915087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2017 02:08:59.010458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2018 02:08:59.011232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2020 02:08:59.100337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2021 02:08:59.101156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2023 02:08:59.193866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2024 02:08:59.194664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2026 02:08:59.279906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2027 02:08:59.280741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2029 02:08:59.375585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2030 02:08:59.376493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2032 02:08:59.463726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2033 02:08:59.464582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2035 02:08:59.554904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2036 02:08:59.555569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2038 02:08:59.653789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2039 02:08:59.654645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2041 02:08:59.748983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2042 02:08:59.749763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2044 02:08:59.843910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2045 02:08:59.844708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2047 02:08:59.939034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2048 02:08:59.939792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2050 02:09:00.028498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2051 02:09:00.029264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2053 02:09:00.118564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2054 02:09:00.119333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2056 02:09:00.213227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2057 02:09:00.214005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2059 02:09:00.307660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2060 02:09:00.308565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2062 02:09:00.398165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2063 02:09:00.398966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2065 02:09:00.487474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2066 02:09:00.488473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2068 02:09:00.583735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2069 02:09:00.584369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2071 02:09:00.685145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2072 02:09:00.685951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2074 02:09:00.793433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2075 02:09:00.794295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2077 02:09:00.897295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2078 02:09:00.898104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2080 02:09:00.990795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2081 02:09:00.991649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2083 02:09:01.091645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2084 02:09:01.092356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2086 02:09:01.188096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2087 02:09:01.188752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2089 02:09:01.282334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2090 02:09:01.282995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2092 02:09:01.377649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2093 02:09:01.378304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2095 02:09:01.464647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2096 02:09:01.465314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2098 02:09:01.560712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2099 02:09:01.561520 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2101 02:09:01.656226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2102 02:09:01.657073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2104 02:09:01.755335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2105 02:09:01.756098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2107 02:09:01.852190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2108 02:09:01.852954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2110 02:09:01.946858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2111 02:09:01.947605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2113 02:09:02.052024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2114 02:09:02.052880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2116 02:09:02.139252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2117 02:09:02.140066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2119 02:09:02.226328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2120 02:09:02.227079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2122 02:09:02.317579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2123 02:09:02.318434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2125 02:09:02.414948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2126 02:09:02.416179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2128 02:09:02.506836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2129 02:09:02.507787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2131 02:09:02.604169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2132 02:09:02.605069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2134 02:09:02.700736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2135 02:09:02.701607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2137 02:09:02.798893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2138 02:09:02.799749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2140 02:09:02.894828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2141 02:09:02.895695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2143 02:09:02.989421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2144 02:09:02.990291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2146 02:09:03.083724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2147 02:09:03.084627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2149 02:09:03.178380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2150 02:09:03.179214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2152 02:09:03.271534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2153 02:09:03.272378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2155 02:09:03.368204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2156 02:09:03.369009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2158 02:09:03.463263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2159 02:09:03.464121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2161 02:09:03.558363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2162 02:09:03.559169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2164 02:09:03.652965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2165 02:09:03.653760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2167 02:09:03.748367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2168 02:09:03.749171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2170 02:09:03.837589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2171 02:09:03.838430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2173 02:09:03.933740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2174 02:09:03.934549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2176 02:09:04.022298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2177 02:09:04.023149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2179 02:09:04.116904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2180 02:09:04.117725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2182 02:09:04.206703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2183 02:09:04.207529 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2185 02:09:04.303201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2186 02:09:04.304061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2188 02:09:04.396612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2189 02:09:04.397415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2191 02:09:04.494007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2192 02:09:04.494889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2194 02:09:04.584007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2195 02:09:04.584823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2197 02:09:04.676271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2198 02:09:04.677110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2200 02:09:04.767175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2201 02:09:04.768027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2203 02:09:04.856613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2204 02:09:04.857435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2206 02:09:04.953536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2207 02:09:04.954325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2209 02:09:05.047068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2210 02:09:05.047885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2212 02:09:05.135823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2213 02:09:05.136683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2215 02:09:05.224779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2216 02:09:05.225580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2218 02:09:05.319360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2219 02:09:05.320173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2221 02:09:05.409862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2222 02:09:05.410694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2224 02:09:05.499122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2225 02:09:05.499961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2227 02:09:05.595841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2228 02:09:05.596709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2230 02:09:05.702040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2231 02:09:05.703097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2233 02:09:05.807316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2234 02:09:05.808244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2236 02:09:05.902773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2237 02:09:05.903654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2239 02:09:06.005382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2240 02:09:06.006266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2242 02:09:06.097984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2243 02:09:06.098871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2245 02:09:06.193787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2246 02:09:06.194787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2248 02:09:06.286785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2249 02:09:06.287618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2251 02:09:06.376498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2252 02:09:06.377357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2254 02:09:06.465502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2255 02:09:06.466366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2257 02:09:06.555407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2258 02:09:06.556076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2260 02:09:06.645740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2261 02:09:06.646381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2263 02:09:06.734359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2264 02:09:06.734992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2266 02:09:06.828549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2267 02:09:06.829165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2269 02:09:06.923275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2270 02:09:06.923923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2272 02:09:07.013306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2273 02:09:07.013947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2275 02:09:07.099507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2277 02:09:07.102534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2278 02:09:07.194135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2279 02:09:07.194929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2281 02:09:07.284745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2282 02:09:07.285621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2284 02:09:07.379290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2285 02:09:07.380117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2287 02:09:07.476278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2288 02:09:07.477148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2290 02:09:07.570153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2291 02:09:07.571016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2293 02:09:07.658794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2294 02:09:07.659615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2296 02:09:07.746426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2297 02:09:07.747258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2299 02:09:07.841615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2300 02:09:07.842440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2302 02:09:07.936893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2303 02:09:07.937718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2305 02:09:08.025281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2306 02:09:08.026096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2308 02:09:08.119825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2309 02:09:08.120637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2311 02:09:08.206509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2312 02:09:08.207314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2314 02:09:08.294324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2315 02:09:08.295169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2317 02:09:08.382354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2318 02:09:08.383175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2320 02:09:08.476238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2321 02:09:08.477080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2323 02:09:08.564676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2324 02:09:08.565526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2326 02:09:08.653231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2327 02:09:08.653938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2329 02:09:08.749483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2330 02:09:08.751430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2332 02:09:08.934976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2333 02:09:08.935887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2335 02:09:09.039284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2336 02:09:09.040168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2338 02:09:09.133254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2339 02:09:09.134162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2341 02:09:09.223498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2342 02:09:09.224473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2344 02:09:09.318187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2345 02:09:09.319105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2347 02:09:09.413071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2348 02:09:09.413997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2350 02:09:09.505833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2351 02:09:09.506737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2353 02:09:09.601079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2354 02:09:09.602137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2356 02:09:09.695369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2357 02:09:09.696312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2359 02:09:09.791310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2360 02:09:09.792149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2362 02:09:09.908814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2363 02:09:09.909452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2365 02:09:09.991061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2366 02:09:09.991699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2368 02:09:10.081321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2369 02:09:10.081724 + set +x
2370 02:09:10.082218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2372 02:09:10.089280 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 957239_1.6.2.4.5>
2373 02:09:10.089698 <LAVA_TEST_RUNNER EXIT>
2374 02:09:10.090151 Received signal: <ENDRUN> 1_kselftest-dt 957239_1.6.2.4.5
2375 02:09:10.090419 Ending use of test pattern.
2376 02:09:10.090630 Ending test lava.1_kselftest-dt (957239_1.6.2.4.5), duration 82.68
2378 02:09:10.091434 ok: lava_test_shell seems to have completed
2379 02:09:10.097949 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2380 02:09:10.099010 end: 3.1 lava-test-shell (duration 00:01:24) [common]
2381 02:09:10.099333 end: 3 lava-test-retry (duration 00:01:24) [common]
2382 02:09:10.099644 start: 4 finalize (timeout 00:05:30) [common]
2383 02:09:10.099938 start: 4.1 power-off (timeout 00:00:30) [common]
2384 02:09:10.100503 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2385 02:09:10.133612 >> OK - accepted request
2386 02:09:10.135544 Returned 0 in 0 seconds
2387 02:09:10.236559 end: 4.1 power-off (duration 00:00:00) [common]
2389 02:09:10.237627 start: 4.2 read-feedback (timeout 00:05:30) [common]
2390 02:09:10.238298 Listened to connection for namespace 'common' for up to 1s
2391 02:09:10.238964 Listened to connection for namespace 'common' for up to 1s
2392 02:09:11.239204 Finalising connection for namespace 'common'
2393 02:09:11.239882 Disconnecting from shell: Finalise
2394 02:09:11.240388 / #
2395 02:09:11.341214 end: 4.2 read-feedback (duration 00:00:01) [common]
2396 02:09:11.341866 end: 4 finalize (duration 00:00:01) [common]
2397 02:09:11.342369 Cleaning after the job
2398 02:09:11.342845 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957239/tftp-deploy-c2gbn8dc/ramdisk
2399 02:09:11.348346 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957239/tftp-deploy-c2gbn8dc/kernel
2400 02:09:11.352934 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957239/tftp-deploy-c2gbn8dc/dtb
2401 02:09:11.353844 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957239/tftp-deploy-c2gbn8dc/nfsrootfs
2402 02:09:11.497979 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957239/tftp-deploy-c2gbn8dc/modules
2403 02:09:11.508424 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/957239
2404 02:09:14.523741 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/957239
2405 02:09:14.524341 Job finished correctly