Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:27:38.822270 lava-dispatcher, installed at version: 2024.01
2 01:27:38.823091 start: 0 validate
3 01:27:38.823616 Start time: 2024-11-08 01:27:38.823585+00:00 (UTC)
4 01:27:38.824254 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:27:38.824827 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 01:27:38.865547 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:27:38.866185 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 01:27:38.896622 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:27:38.897307 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 01:27:39.949664 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:27:39.950194 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
12 01:27:39.995486 validate duration: 1.17
14 01:27:39.996466 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:27:39.996811 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:27:39.997126 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:27:39.998024 Not decompressing ramdisk as can be used compressed.
18 01:27:39.998887 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 01:27:40.002396 saving as /var/lib/lava/dispatcher/tmp/956994/tftp-deploy-12u9rq7c/ramdisk/rootfs.cpio.gz
20 01:27:40.002882 total size: 8181887 (7 MB)
21 01:27:40.042532 progress 0 % (0 MB)
22 01:27:40.051255 progress 5 % (0 MB)
23 01:27:40.056931 progress 10 % (0 MB)
24 01:27:40.063820 progress 15 % (1 MB)
25 01:27:40.069612 progress 20 % (1 MB)
26 01:27:40.075666 progress 25 % (1 MB)
27 01:27:40.081217 progress 30 % (2 MB)
28 01:27:40.087367 progress 35 % (2 MB)
29 01:27:40.093510 progress 40 % (3 MB)
30 01:27:40.099376 progress 45 % (3 MB)
31 01:27:40.104980 progress 50 % (3 MB)
32 01:27:40.110937 progress 55 % (4 MB)
33 01:27:40.116422 progress 60 % (4 MB)
34 01:27:40.122295 progress 65 % (5 MB)
35 01:27:40.127682 progress 70 % (5 MB)
36 01:27:40.133600 progress 75 % (5 MB)
37 01:27:40.138979 progress 80 % (6 MB)
38 01:27:40.144853 progress 85 % (6 MB)
39 01:27:40.150043 progress 90 % (7 MB)
40 01:27:40.155355 progress 95 % (7 MB)
41 01:27:40.160264 progress 100 % (7 MB)
42 01:27:40.160972 7 MB downloaded in 0.16 s (49.36 MB/s)
43 01:27:40.161544 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:27:40.162459 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:27:40.162773 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:27:40.163058 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:27:40.163542 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/clang-16/kernel/Image
49 01:27:40.163805 saving as /var/lib/lava/dispatcher/tmp/956994/tftp-deploy-12u9rq7c/kernel/Image
50 01:27:40.164040 total size: 37880320 (36 MB)
51 01:27:40.164263 No compression specified
52 01:27:40.201658 progress 0 % (0 MB)
53 01:27:40.226054 progress 5 % (1 MB)
54 01:27:40.250063 progress 10 % (3 MB)
55 01:27:40.273881 progress 15 % (5 MB)
56 01:27:40.297652 progress 20 % (7 MB)
57 01:27:40.321351 progress 25 % (9 MB)
58 01:27:40.345018 progress 30 % (10 MB)
59 01:27:40.368594 progress 35 % (12 MB)
60 01:27:40.391824 progress 40 % (14 MB)
61 01:27:40.415108 progress 45 % (16 MB)
62 01:27:40.438501 progress 50 % (18 MB)
63 01:27:40.461357 progress 55 % (19 MB)
64 01:27:40.484604 progress 60 % (21 MB)
65 01:27:40.507892 progress 65 % (23 MB)
66 01:27:40.531108 progress 70 % (25 MB)
67 01:27:40.554516 progress 75 % (27 MB)
68 01:27:40.577446 progress 80 % (28 MB)
69 01:27:40.600700 progress 85 % (30 MB)
70 01:27:40.623947 progress 90 % (32 MB)
71 01:27:40.647273 progress 95 % (34 MB)
72 01:27:40.669548 progress 100 % (36 MB)
73 01:27:40.670045 36 MB downloaded in 0.51 s (71.40 MB/s)
74 01:27:40.670524 end: 1.2.1 http-download (duration 00:00:01) [common]
76 01:27:40.671321 end: 1.2 download-retry (duration 00:00:01) [common]
77 01:27:40.671590 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:27:40.671850 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:27:40.672333 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/clang-16/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 01:27:40.672601 saving as /var/lib/lava/dispatcher/tmp/956994/tftp-deploy-12u9rq7c/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 01:27:40.672810 total size: 53209 (0 MB)
82 01:27:40.673017 No compression specified
83 01:27:40.708876 progress 61 % (0 MB)
84 01:27:40.709710 progress 100 % (0 MB)
85 01:27:40.710230 0 MB downloaded in 0.04 s (1.36 MB/s)
86 01:27:40.710707 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:27:40.711506 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:27:40.711762 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:27:40.712055 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:27:40.712537 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/clang-16/modules.tar.xz
92 01:27:40.712776 saving as /var/lib/lava/dispatcher/tmp/956994/tftp-deploy-12u9rq7c/modules/modules.tar
93 01:27:40.712980 total size: 11768564 (11 MB)
94 01:27:40.713191 Using unxz to decompress xz
95 01:27:40.746999 progress 0 % (0 MB)
96 01:27:40.814182 progress 5 % (0 MB)
97 01:27:40.889549 progress 10 % (1 MB)
98 01:27:40.985940 progress 15 % (1 MB)
99 01:27:41.083307 progress 20 % (2 MB)
100 01:27:41.163303 progress 25 % (2 MB)
101 01:27:41.241349 progress 30 % (3 MB)
102 01:27:41.322721 progress 35 % (3 MB)
103 01:27:41.403508 progress 40 % (4 MB)
104 01:27:41.480181 progress 45 % (5 MB)
105 01:27:41.566711 progress 50 % (5 MB)
106 01:27:41.649784 progress 55 % (6 MB)
107 01:27:41.735851 progress 60 % (6 MB)
108 01:27:41.818011 progress 65 % (7 MB)
109 01:27:41.902203 progress 70 % (7 MB)
110 01:27:41.985721 progress 75 % (8 MB)
111 01:27:42.071732 progress 80 % (9 MB)
112 01:27:42.154190 progress 85 % (9 MB)
113 01:27:42.238474 progress 90 % (10 MB)
114 01:27:42.322406 progress 95 % (10 MB)
115 01:27:42.400161 progress 100 % (11 MB)
116 01:27:42.410859 11 MB downloaded in 1.70 s (6.61 MB/s)
117 01:27:42.411471 end: 1.4.1 http-download (duration 00:00:02) [common]
119 01:27:42.412647 end: 1.4 download-retry (duration 00:00:02) [common]
120 01:27:42.413180 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 01:27:42.413698 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 01:27:42.414184 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:27:42.414713 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 01:27:42.415795 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx
125 01:27:42.416687 makedir: /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin
126 01:27:42.417313 makedir: /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/tests
127 01:27:42.417912 makedir: /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/results
128 01:27:42.418511 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-add-keys
129 01:27:42.419443 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-add-sources
130 01:27:42.420391 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-background-process-start
131 01:27:42.421323 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-background-process-stop
132 01:27:42.422294 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-common-functions
133 01:27:42.423193 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-echo-ipv4
134 01:27:42.424109 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-install-packages
135 01:27:42.425004 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-installed-packages
136 01:27:42.425865 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-os-build
137 01:27:42.426734 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-probe-channel
138 01:27:42.427607 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-probe-ip
139 01:27:42.428540 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-target-ip
140 01:27:42.429424 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-target-mac
141 01:27:42.430289 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-target-storage
142 01:27:42.431168 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-test-case
143 01:27:42.432074 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-test-event
144 01:27:42.432945 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-test-feedback
145 01:27:42.433830 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-test-raise
146 01:27:42.434705 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-test-reference
147 01:27:42.435584 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-test-runner
148 01:27:42.436510 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-test-set
149 01:27:42.437447 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-test-shell
150 01:27:42.438334 Updating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-install-packages (oe)
151 01:27:42.439271 Updating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/bin/lava-installed-packages (oe)
152 01:27:42.440098 Creating /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/environment
153 01:27:42.440805 LAVA metadata
154 01:27:42.441278 - LAVA_JOB_ID=956994
155 01:27:42.441700 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:27:42.442344 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 01:27:42.444179 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:27:42.444763 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 01:27:42.445171 skipped lava-vland-overlay
160 01:27:42.445653 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:27:42.446155 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 01:27:42.446577 skipped lava-multinode-overlay
163 01:27:42.447054 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:27:42.447544 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 01:27:42.448045 Loading test definitions
166 01:27:42.448349 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 01:27:42.448576 Using /lava-956994 at stage 0
168 01:27:42.449769 uuid=956994_1.5.2.4.1 testdef=None
169 01:27:42.450079 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:27:42.450346 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 01:27:42.452142 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:27:42.452933 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 01:27:42.455165 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:27:42.456001 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 01:27:42.458126 runner path: /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/0/tests/0_dmesg test_uuid 956994_1.5.2.4.1
178 01:27:42.458670 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:27:42.459425 Creating lava-test-runner.conf files
181 01:27:42.459625 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/956994/lava-overlay-o02yjtrx/lava-956994/0 for stage 0
182 01:27:42.459955 - 0_dmesg
183 01:27:42.460320 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:27:42.460594 start: 1.5.2.5 compress-overlay (timeout 00:09:58) [common]
185 01:27:42.484439 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:27:42.484820 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:58) [common]
187 01:27:42.485081 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:27:42.485346 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:27:42.485607 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
190 01:27:43.419177 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 01:27:43.419734 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 01:27:43.420075 extracting modules file /var/lib/lava/dispatcher/tmp/956994/tftp-deploy-12u9rq7c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956994/extract-overlay-ramdisk-xrlizod_/ramdisk
193 01:27:45.028491 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 01:27:45.029073 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 01:27:45.029403 [common] Applying overlay /var/lib/lava/dispatcher/tmp/956994/compress-overlay-osg9znl2/overlay-1.5.2.5.tar.gz to ramdisk
196 01:27:45.029666 [common] Applying overlay /var/lib/lava/dispatcher/tmp/956994/compress-overlay-osg9znl2/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/956994/extract-overlay-ramdisk-xrlizod_/ramdisk
197 01:27:45.066018 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:27:45.066499 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 01:27:45.066826 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 01:27:45.067096 Converting downloaded kernel to a uImage
201 01:27:45.067465 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/956994/tftp-deploy-12u9rq7c/kernel/Image /var/lib/lava/dispatcher/tmp/956994/tftp-deploy-12u9rq7c/kernel/uImage
202 01:27:45.458361 output: Image Name:
203 01:27:45.458795 output: Created: Fri Nov 8 01:27:45 2024
204 01:27:45.459006 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:27:45.459212 output: Data Size: 37880320 Bytes = 36992.50 KiB = 36.13 MiB
206 01:27:45.459414 output: Load Address: 01080000
207 01:27:45.459613 output: Entry Point: 01080000
208 01:27:45.459811 output:
209 01:27:45.460196 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 01:27:45.460478 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 01:27:45.460753 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 01:27:45.461007 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:27:45.461265 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 01:27:45.461525 Building ramdisk /var/lib/lava/dispatcher/tmp/956994/extract-overlay-ramdisk-xrlizod_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/956994/extract-overlay-ramdisk-xrlizod_/ramdisk
215 01:27:47.859523 >> 188226 blocks
216 01:27:56.273214 Adding RAMdisk u-boot header.
217 01:27:56.273857 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/956994/extract-overlay-ramdisk-xrlizod_/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/956994/extract-overlay-ramdisk-xrlizod_/ramdisk.cpio.gz.uboot
218 01:27:56.564975 output: Image Name:
219 01:27:56.565560 output: Created: Fri Nov 8 01:27:56 2024
220 01:27:56.565968 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:27:56.566370 output: Data Size: 26772683 Bytes = 26145.20 KiB = 25.53 MiB
222 01:27:56.566762 output: Load Address: 00000000
223 01:27:56.567151 output: Entry Point: 00000000
224 01:27:56.567537 output:
225 01:27:56.568614 rename /var/lib/lava/dispatcher/tmp/956994/extract-overlay-ramdisk-xrlizod_/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/956994/tftp-deploy-12u9rq7c/ramdisk/ramdisk.cpio.gz.uboot
226 01:27:56.569343 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 01:27:56.569875 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 01:27:56.570393 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 01:27:56.570839 No LXC device requested
230 01:27:56.571327 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:27:56.571828 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 01:27:56.572353 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:27:56.572760 Checking files for TFTP limit of 4294967296 bytes.
234 01:27:56.575379 end: 1 tftp-deploy (duration 00:00:17) [common]
235 01:27:56.575932 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:27:56.576477 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:27:56.576966 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:27:56.577469 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:27:56.577983 Using kernel file from prepare-kernel: 956994/tftp-deploy-12u9rq7c/kernel/uImage
240 01:27:56.578580 substitutions:
241 01:27:56.578978 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:27:56.579374 - {DTB_ADDR}: 0x01070000
243 01:27:56.579768 - {DTB}: 956994/tftp-deploy-12u9rq7c/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 01:27:56.580197 - {INITRD}: 956994/tftp-deploy-12u9rq7c/ramdisk/ramdisk.cpio.gz.uboot
245 01:27:56.580590 - {KERNEL_ADDR}: 0x01080000
246 01:27:56.580979 - {KERNEL}: 956994/tftp-deploy-12u9rq7c/kernel/uImage
247 01:27:56.581370 - {LAVA_MAC}: None
248 01:27:56.581791 - {PRESEED_CONFIG}: None
249 01:27:56.582178 - {PRESEED_LOCAL}: None
250 01:27:56.582562 - {RAMDISK_ADDR}: 0x08000000
251 01:27:56.582944 - {RAMDISK}: 956994/tftp-deploy-12u9rq7c/ramdisk/ramdisk.cpio.gz.uboot
252 01:27:56.583330 - {ROOT_PART}: None
253 01:27:56.583715 - {ROOT}: None
254 01:27:56.584121 - {SERVER_IP}: 192.168.6.2
255 01:27:56.584511 - {TEE_ADDR}: 0x83000000
256 01:27:56.584895 - {TEE}: None
257 01:27:56.585282 Parsed boot commands:
258 01:27:56.585655 - setenv autoload no
259 01:27:56.586036 - setenv initrd_high 0xffffffff
260 01:27:56.586415 - setenv fdt_high 0xffffffff
261 01:27:56.586795 - dhcp
262 01:27:56.587175 - setenv serverip 192.168.6.2
263 01:27:56.587553 - tftpboot 0x01080000 956994/tftp-deploy-12u9rq7c/kernel/uImage
264 01:27:56.587936 - tftpboot 0x08000000 956994/tftp-deploy-12u9rq7c/ramdisk/ramdisk.cpio.gz.uboot
265 01:27:56.588342 - tftpboot 0x01070000 956994/tftp-deploy-12u9rq7c/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 01:27:56.588725 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:27:56.589114 - bootm 0x01080000 0x08000000 0x01070000
268 01:27:56.589596 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:27:56.591043 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:27:56.591474 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 01:27:56.605499 Setting prompt string to ['lava-test: # ']
273 01:27:56.606933 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:27:56.607518 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:27:56.608127 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:27:56.608671 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:27:56.609795 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 01:27:56.644370 >> OK - accepted request
279 01:27:56.646547 Returned 0 in 0 seconds
280 01:27:56.747601 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:27:56.749170 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:27:56.749716 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:27:56.750211 Setting prompt string to ['Hit any key to stop autoboot']
285 01:27:56.750642 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:27:56.752207 Trying 192.168.56.21...
287 01:27:56.752682 Connected to conserv1.
288 01:27:56.753096 Escape character is '^]'.
289 01:27:56.753507
290 01:27:56.753917 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 01:27:56.754333
292 01:28:03.749368 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 01:28:03.749803 bl2_stage_init 0x01
294 01:28:03.750052 bl2_stage_init 0x81
295 01:28:03.754903 hw id: 0x0000 - pwm id 0x01
296 01:28:03.755319 bl2_stage_init 0xc1
297 01:28:03.760514 bl2_stage_init 0x02
298 01:28:03.760938
299 01:28:03.761292 L0:00000000
300 01:28:03.761632 L1:00000703
301 01:28:03.761888 L2:00008067
302 01:28:03.762103 L3:15000000
303 01:28:03.766108 S1:00000000
304 01:28:03.766500 B2:20282000
305 01:28:03.766839 B1:a0f83180
306 01:28:03.767176
307 01:28:03.767510 TE: 68161
308 01:28:03.767841
309 01:28:03.771712 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 01:28:03.772009
311 01:28:03.777331 Board ID = 1
312 01:28:03.777625 Set cpu clk to 24M
313 01:28:03.777841 Set clk81 to 24M
314 01:28:03.782881 Use GP1_pll as DSU clk.
315 01:28:03.783272 DSU clk: 1200 Mhz
316 01:28:03.783608 CPU clk: 1200 MHz
317 01:28:03.788471 Set clk81 to 166.6M
318 01:28:03.794083 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 01:28:03.794474 board id: 1
320 01:28:03.801308 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:28:03.812201 fw parse done
322 01:28:03.818133 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:28:03.861284 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:28:03.872514 PIEI prepare done
325 01:28:03.872825 fastboot data load
326 01:28:03.873050 fastboot data verify
327 01:28:03.878031 verify result: 266
328 01:28:03.883766 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 01:28:03.884083 LPDDR4 probe
330 01:28:03.884320 ddr clk to 1584MHz
331 01:28:03.891676 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:28:03.929399
333 01:28:03.929754 dmc_version 0001
334 01:28:03.936419 Check phy result
335 01:28:03.942394 INFO : End of CA training
336 01:28:03.942818 INFO : End of initialization
337 01:28:03.948012 INFO : Training has run successfully!
338 01:28:03.948295 Check phy result
339 01:28:03.953594 INFO : End of initialization
340 01:28:03.954007 INFO : End of read enable training
341 01:28:03.959200 INFO : End of fine write leveling
342 01:28:03.964788 INFO : End of Write leveling coarse delay
343 01:28:03.965073 INFO : Training has run successfully!
344 01:28:03.965303 Check phy result
345 01:28:03.970387 INFO : End of initialization
346 01:28:03.970799 INFO : End of read dq deskew training
347 01:28:03.975966 INFO : End of MPR read delay center optimization
348 01:28:03.981581 INFO : End of write delay center optimization
349 01:28:03.987171 INFO : End of read delay center optimization
350 01:28:03.987457 INFO : End of max read latency training
351 01:28:03.992871 INFO : Training has run successfully!
352 01:28:03.993308 1D training succeed
353 01:28:04.002171 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:28:04.050413 Check phy result
355 01:28:04.051023 INFO : End of initialization
356 01:28:04.077781 INFO : End of 2D read delay Voltage center optimization
357 01:28:04.101945 INFO : End of 2D read delay Voltage center optimization
358 01:28:04.158675 INFO : End of 2D write delay Voltage center optimization
359 01:28:04.212630 INFO : End of 2D write delay Voltage center optimization
360 01:28:04.218162 INFO : Training has run successfully!
361 01:28:04.218606
362 01:28:04.219041 channel==0
363 01:28:04.223877 RxClkDly_Margin_A0==78 ps 8
364 01:28:04.224411 TxDqDly_Margin_A0==88 ps 9
365 01:28:04.229380 RxClkDly_Margin_A1==88 ps 9
366 01:28:04.229821 TxDqDly_Margin_A1==88 ps 9
367 01:28:04.230224 TrainedVREFDQ_A0==74
368 01:28:04.234941 TrainedVREFDQ_A1==74
369 01:28:04.235369 VrefDac_Margin_A0==23
370 01:28:04.235769 DeviceVref_Margin_A0==40
371 01:28:04.240646 VrefDac_Margin_A1==23
372 01:28:04.241081 DeviceVref_Margin_A1==40
373 01:28:04.241487
374 01:28:04.241884
375 01:28:04.242278 channel==1
376 01:28:04.246157 RxClkDly_Margin_A0==78 ps 8
377 01:28:04.246581 TxDqDly_Margin_A0==98 ps 10
378 01:28:04.251848 RxClkDly_Margin_A1==78 ps 8
379 01:28:04.252323 TxDqDly_Margin_A1==88 ps 9
380 01:28:04.257302 TrainedVREFDQ_A0==78
381 01:28:04.257747 TrainedVREFDQ_A1==75
382 01:28:04.258147 VrefDac_Margin_A0==22
383 01:28:04.262927 DeviceVref_Margin_A0==36
384 01:28:04.263355 VrefDac_Margin_A1==20
385 01:28:04.263752 DeviceVref_Margin_A1==39
386 01:28:04.268557
387 01:28:04.268989 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:28:04.269395
389 01:28:04.302168 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000017 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000016 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 01:28:04.302714 2D training succeed
391 01:28:04.307883 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:28:04.313374 auto size-- 65535DDR cs0 size: 2048MB
393 01:28:04.313807 DDR cs1 size: 2048MB
394 01:28:04.318960 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:28:04.319388 cs0 DataBus test pass
396 01:28:04.324635 cs1 DataBus test pass
397 01:28:04.325063 cs0 AddrBus test pass
398 01:28:04.325461 cs1 AddrBus test pass
399 01:28:04.325849
400 01:28:04.330141 100bdlr_step_size ps== 485
401 01:28:04.330578 result report
402 01:28:04.335874 boot times 0Enable ddr reg access
403 01:28:04.340925 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:28:04.354709 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 01:28:05.014188 bl2z: ptr: 05129330, size: 00001e40
406 01:28:05.022988 0.0;M3 CHK:0;cm4_sp_mode 0
407 01:28:05.023458 MVN_1=0x00000000
408 01:28:05.023867 MVN_2=0x00000000
409 01:28:05.034515 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 01:28:05.034978 OPS=0x04
411 01:28:05.035385 ring efuse init
412 01:28:05.040124 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 01:28:05.040570 [0.017354 Inits done]
414 01:28:05.040971 secure task start!
415 01:28:05.048235 high task start!
416 01:28:05.048674 low task start!
417 01:28:05.049078 run into bl31
418 01:28:05.056897 NOTICE: BL31: v1.3(release):4fc40b1
419 01:28:05.063755 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 01:28:05.064243 NOTICE: BL31: G12A normal boot!
421 01:28:05.080299 NOTICE: BL31: BL33 decompress pass
422 01:28:05.085986 ERROR: Error initializing runtime service opteed_fast
423 01:28:06.302062 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 01:28:06.302681 bl2_stage_init 0x01
425 01:28:06.303102 bl2_stage_init 0x81
426 01:28:06.307420 hw id: 0x0000 - pwm id 0x01
427 01:28:06.307885 bl2_stage_init 0xc1
428 01:28:06.311732 bl2_stage_init 0x02
429 01:28:06.312240
430 01:28:06.312652 L0:00000000
431 01:28:06.313050 L1:00000703
432 01:28:06.313449 L2:00008067
433 01:28:06.317401 L3:15000000
434 01:28:06.317854 S1:00000000
435 01:28:06.318257 B2:20282000
436 01:28:06.318658 B1:a0f83180
437 01:28:06.319053
438 01:28:06.319444 TE: 70298
439 01:28:06.322778
440 01:28:06.328414 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 01:28:06.328978
442 01:28:06.329460 Board ID = 1
443 01:28:06.329927 Set cpu clk to 24M
444 01:28:06.333967 Set clk81 to 24M
445 01:28:06.334412 Use GP1_pll as DSU clk.
446 01:28:06.334815 DSU clk: 1200 Mhz
447 01:28:06.335209 CPU clk: 1200 MHz
448 01:28:06.339567 Set clk81 to 166.6M
449 01:28:06.345183 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 01:28:06.345633 board id: 1
451 01:28:06.352774 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 01:28:06.364520 fw parse done
453 01:28:06.369457 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 01:28:06.412144 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 01:28:06.424121 PIEI prepare done
456 01:28:06.424581 fastboot data load
457 01:28:06.425000 fastboot data verify
458 01:28:06.429542 verify result: 266
459 01:28:06.435164 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 01:28:06.435596 LPDDR4 probe
461 01:28:06.436040 ddr clk to 1584MHz
462 01:28:07.803533 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 01:28:07.804192 bl2_stage_init 0x01
464 01:28:07.804628 bl2_stage_init 0x81
465 01:28:07.809129 hw id: 0x0000 - pwm id 0x01
466 01:28:07.809612 bl2_stage_init 0xc1
467 01:28:07.814136 bl2_stage_init 0x02
468 01:28:07.814655
469 01:28:07.815053 L0:00000000
470 01:28:07.815439 L1:00000703
471 01:28:07.815829 L2:00008067
472 01:28:07.819573 L3:15000000
473 01:28:07.820017 S1:00000000
474 01:28:07.820413 B2:20282000
475 01:28:07.820797 B1:a0f83180
476 01:28:07.821174
477 01:28:07.821554 TE: 70961
478 01:28:07.821934
479 01:28:07.830767 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 01:28:07.831190
481 01:28:07.831573 Board ID = 1
482 01:28:07.831950 Set cpu clk to 24M
483 01:28:07.832357 Set clk81 to 24M
484 01:28:07.836360 Use GP1_pll as DSU clk.
485 01:28:07.836770 DSU clk: 1200 Mhz
486 01:28:07.837150 CPU clk: 1200 MHz
487 01:28:07.842019 Set clk81 to 166.6M
488 01:28:07.847564 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 01:28:07.848015 board id: 1
490 01:28:07.855482 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 01:28:07.866177 fw parse done
492 01:28:07.872131 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 01:28:07.914743 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 01:28:07.925708 PIEI prepare done
495 01:28:07.926117 fastboot data load
496 01:28:07.926506 fastboot data verify
497 01:28:07.931375 verify result: 266
498 01:28:07.936890 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 01:28:07.937306 LPDDR4 probe
500 01:28:07.937689 ddr clk to 1584MHz
501 01:28:07.944858 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 01:28:07.982110
503 01:28:07.982524 dmc_version 0001
504 01:28:07.988799 Check phy result
505 01:28:07.994745 INFO : End of CA training
506 01:28:07.995157 INFO : End of initialization
507 01:28:08.000416 INFO : Training has run successfully!
508 01:28:08.000900 Check phy result
509 01:28:08.005934 INFO : End of initialization
510 01:28:08.006376 INFO : End of read enable training
511 01:28:08.011528 INFO : End of fine write leveling
512 01:28:08.017129 INFO : End of Write leveling coarse delay
513 01:28:08.017560 INFO : Training has run successfully!
514 01:28:08.017962 Check phy result
515 01:28:08.022703 INFO : End of initialization
516 01:28:08.023130 INFO : End of read dq deskew training
517 01:28:08.028387 INFO : End of MPR read delay center optimization
518 01:28:08.033918 INFO : End of write delay center optimization
519 01:28:08.039534 INFO : End of read delay center optimization
520 01:28:08.039959 INFO : End of max read latency training
521 01:28:08.045146 INFO : Training has run successfully!
522 01:28:08.045569 1D training succeed
523 01:28:08.054480 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 01:28:08.101960 Check phy result
525 01:28:08.102389 INFO : End of initialization
526 01:28:08.124284 INFO : End of 2D read delay Voltage center optimization
527 01:28:08.143505 INFO : End of 2D read delay Voltage center optimization
528 01:28:08.195301 INFO : End of 2D write delay Voltage center optimization
529 01:28:08.244489 INFO : End of 2D write delay Voltage center optimization
530 01:28:08.250063 INFO : Training has run successfully!
531 01:28:08.250500
532 01:28:08.250913 channel==0
533 01:28:08.255636 RxClkDly_Margin_A0==78 ps 8
534 01:28:08.256090 TxDqDly_Margin_A0==88 ps 9
535 01:28:08.261227 RxClkDly_Margin_A1==78 ps 8
536 01:28:08.261649 TxDqDly_Margin_A1==98 ps 10
537 01:28:08.262049 TrainedVREFDQ_A0==74
538 01:28:08.266833 TrainedVREFDQ_A1==74
539 01:28:08.267259 VrefDac_Margin_A0==23
540 01:28:08.267657 DeviceVref_Margin_A0==40
541 01:28:08.272430 VrefDac_Margin_A1==23
542 01:28:08.272848 DeviceVref_Margin_A1==40
543 01:28:08.273248
544 01:28:08.273669
545 01:28:08.274065 channel==1
546 01:28:08.278049 RxClkDly_Margin_A0==78 ps 8
547 01:28:08.278485 TxDqDly_Margin_A0==98 ps 10
548 01:28:08.283615 RxClkDly_Margin_A1==78 ps 8
549 01:28:08.284070 TxDqDly_Margin_A1==88 ps 9
550 01:28:08.289229 TrainedVREFDQ_A0==78
551 01:28:08.289654 TrainedVREFDQ_A1==78
552 01:28:08.290056 VrefDac_Margin_A0==22
553 01:28:08.294833 DeviceVref_Margin_A0==36
554 01:28:08.295258 VrefDac_Margin_A1==22
555 01:28:08.300426 DeviceVref_Margin_A1==36
556 01:28:08.300852
557 01:28:08.301251 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 01:28:08.301646
559 01:28:08.334026 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000015 00000017 dram_vref_reg_value 0x 00000061
560 01:28:08.334485 2D training succeed
561 01:28:08.339629 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 01:28:08.345223 auto size-- 65535DDR cs0 size: 2048MB
563 01:28:08.345649 DDR cs1 size: 2048MB
564 01:28:08.350831 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 01:28:08.351259 cs0 DataBus test pass
566 01:28:08.356415 cs1 DataBus test pass
567 01:28:08.356837 cs0 AddrBus test pass
568 01:28:08.357232 cs1 AddrBus test pass
569 01:28:08.357624
570 01:28:08.362054 100bdlr_step_size ps== 478
571 01:28:08.362485 result report
572 01:28:08.367617 boot times 0Enable ddr reg access
573 01:28:08.372799 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 01:28:08.386645 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 01:28:09.041926 bl2z: ptr: 05129330, size: 00001e40
576 01:28:09.049371 0.0;M3 CHK:0;cm4_sp_mode 0
577 01:28:09.049847 MVN_1=0x00000000
578 01:28:09.050260 MVN_2=0x00000000
579 01:28:09.060878 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 01:28:09.061338 OPS=0x04
581 01:28:09.061749 ring efuse init
582 01:28:09.066490 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 01:28:09.066936 [0.017310 Inits done]
584 01:28:09.067339 secure task start!
585 01:28:09.073820 high task start!
586 01:28:09.074274 low task start!
587 01:28:09.074677 run into bl31
588 01:28:09.082481 NOTICE: BL31: v1.3(release):4fc40b1
589 01:28:09.090193 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 01:28:09.090630 NOTICE: BL31: G12A normal boot!
591 01:28:09.105696 NOTICE: BL31: BL33 decompress pass
592 01:28:09.111391 ERROR: Error initializing runtime service opteed_fast
593 01:28:10.350789 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 01:28:10.351225 bl2_stage_init 0x01
595 01:28:10.351433 bl2_stage_init 0x81
596 01:28:10.356308 hw id: 0x0000 - pwm id 0x01
597 01:28:10.356680 bl2_stage_init 0xc1
598 01:28:10.362971 bl2_stage_init 0x02
599 01:28:10.363554
600 01:28:10.363965 L0:00000000
601 01:28:10.364198 L1:00000703
602 01:28:10.364404 L2:00008067
603 01:28:10.364606 L3:15000000
604 01:28:10.367514 S1:00000000
605 01:28:10.367966 B2:20282000
606 01:28:10.368679 B1:a0f83180
607 01:28:10.369160
608 01:28:10.369613 TE: 69430
609 01:28:10.370066
610 01:28:10.373286 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 01:28:10.373888
612 01:28:10.378869 Board ID = 1
613 01:28:10.379461 Set cpu clk to 24M
614 01:28:10.379942 Set clk81 to 24M
615 01:28:10.384471 Use GP1_pll as DSU clk.
616 01:28:10.385070 DSU clk: 1200 Mhz
617 01:28:10.385548 CPU clk: 1200 MHz
618 01:28:10.390051 Set clk81 to 166.6M
619 01:28:10.395595 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 01:28:10.396190 board id: 1
621 01:28:10.402898 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 01:28:10.413866 fw parse done
623 01:28:10.419717 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 01:28:10.462785 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 01:28:10.473932 PIEI prepare done
626 01:28:10.474501 fastboot data load
627 01:28:10.474973 fastboot data verify
628 01:28:10.479477 verify result: 266
629 01:28:10.485055 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 01:28:10.485612 LPDDR4 probe
631 01:28:10.486073 ddr clk to 1584MHz
632 01:28:10.493092 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 01:28:10.530992
634 01:28:10.531596 dmc_version 0001
635 01:28:10.537969 Check phy result
636 01:28:10.543870 INFO : End of CA training
637 01:28:10.544471 INFO : End of initialization
638 01:28:10.549452 INFO : Training has run successfully!
639 01:28:10.550016 Check phy result
640 01:28:10.555046 INFO : End of initialization
641 01:28:10.555599 INFO : End of read enable training
642 01:28:10.560670 INFO : End of fine write leveling
643 01:28:10.566265 INFO : End of Write leveling coarse delay
644 01:28:10.566841 INFO : Training has run successfully!
645 01:28:10.567304 Check phy result
646 01:28:10.571862 INFO : End of initialization
647 01:28:10.572447 INFO : End of read dq deskew training
648 01:28:10.577429 INFO : End of MPR read delay center optimization
649 01:28:10.583029 INFO : End of write delay center optimization
650 01:28:10.588631 INFO : End of read delay center optimization
651 01:28:10.589177 INFO : End of max read latency training
652 01:28:10.594212 INFO : Training has run successfully!
653 01:28:10.594764 1D training succeed
654 01:28:10.603377 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 01:28:10.651761 Check phy result
656 01:28:10.652377 INFO : End of initialization
657 01:28:10.679117 INFO : End of 2D read delay Voltage center optimization
658 01:28:10.703257 INFO : End of 2D read delay Voltage center optimization
659 01:28:10.760051 INFO : End of 2D write delay Voltage center optimization
660 01:28:10.813968 INFO : End of 2D write delay Voltage center optimization
661 01:28:10.819541 INFO : Training has run successfully!
662 01:28:10.820127
663 01:28:10.820617 channel==0
664 01:28:10.825141 RxClkDly_Margin_A0==78 ps 8
665 01:28:10.825685 TxDqDly_Margin_A0==98 ps 10
666 01:28:10.830702 RxClkDly_Margin_A1==88 ps 9
667 01:28:10.831252 TxDqDly_Margin_A1==98 ps 10
668 01:28:10.831717 TrainedVREFDQ_A0==74
669 01:28:10.836310 TrainedVREFDQ_A1==74
670 01:28:10.836866 VrefDac_Margin_A0==24
671 01:28:10.837324 DeviceVref_Margin_A0==40
672 01:28:10.841959 VrefDac_Margin_A1==23
673 01:28:10.842509 DeviceVref_Margin_A1==40
674 01:28:10.842970
675 01:28:10.843419
676 01:28:10.847536 channel==1
677 01:28:10.848114 RxClkDly_Margin_A0==88 ps 9
678 01:28:10.848587 TxDqDly_Margin_A0==88 ps 9
679 01:28:10.853134 RxClkDly_Margin_A1==88 ps 9
680 01:28:10.853681 TxDqDly_Margin_A1==78 ps 8
681 01:28:10.858711 TrainedVREFDQ_A0==75
682 01:28:10.859271 TrainedVREFDQ_A1==75
683 01:28:10.859734 VrefDac_Margin_A0==23
684 01:28:10.864349 DeviceVref_Margin_A0==38
685 01:28:10.864904 VrefDac_Margin_A1==20
686 01:28:10.869922 DeviceVref_Margin_A1==39
687 01:28:10.870467
688 01:28:10.870924 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 01:28:10.871369
690 01:28:10.903471 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000019 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000016 dram_vref_reg_value 0x 00000060
691 01:28:10.904123 2D training succeed
692 01:28:10.909143 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 01:28:10.914719 auto size-- 65535DDR cs0 size: 2048MB
694 01:28:10.915271 DDR cs1 size: 2048MB
695 01:28:10.920328 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 01:28:10.920877 cs0 DataBus test pass
697 01:28:10.925959 cs1 DataBus test pass
698 01:28:10.926505 cs0 AddrBus test pass
699 01:28:10.926967 cs1 AddrBus test pass
700 01:28:10.927413
701 01:28:10.931549 100bdlr_step_size ps== 471
702 01:28:10.932160 result report
703 01:28:10.936979 boot times 0Enable ddr reg access
704 01:28:10.942148 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 01:28:10.955101 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 01:28:11.616269 bl2z: ptr: 05129330, size: 00001e40
707 01:28:11.625317 0.0;M3 CHK:0;cm4_sp_mode 0
708 01:28:11.625786 MVN_1=0x00000000
709 01:28:11.626058 MVN_2=0x00000000
710 01:28:11.636966 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 01:28:11.637300 OPS=0x04
712 01:28:11.637532 ring efuse init
713 01:28:11.642498 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 01:28:11.642821 [0.017354 Inits done]
715 01:28:11.643048 secure task start!
716 01:28:11.649909 high task start!
717 01:28:11.650354 low task start!
718 01:28:11.650697 run into bl31
719 01:28:11.658465 NOTICE: BL31: v1.3(release):4fc40b1
720 01:28:11.666284 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 01:28:11.666727 NOTICE: BL31: G12A normal boot!
722 01:28:11.681760 NOTICE: BL31: BL33 decompress pass
723 01:28:11.687571 ERROR: Error initializing runtime service opteed_fast
724 01:28:12.482782
725 01:28:12.483368
726 01:28:12.488368 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 01:28:12.488689
728 01:28:12.491828 Model: Libre Computer AML-S905D3-CC Solitude
729 01:28:12.638727 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 01:28:12.654213 DRAM: 2 GiB (effective 3.8 GiB)
731 01:28:12.755129 Core: 406 devices, 33 uclasses, devicetree: separate
732 01:28:12.760892 WDT: Not starting watchdog@f0d0
733 01:28:12.786139 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 01:28:12.798248 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 01:28:12.803260 ** Bad device specification mmc 0 **
736 01:28:12.813168 Card did not respond to voltage select! : -110
737 01:28:12.820981 ** Bad device specification mmc 0 **
738 01:28:12.821660 Couldn't find partition mmc 0
739 01:28:12.829209 Card did not respond to voltage select! : -110
740 01:28:12.834792 ** Bad device specification mmc 0 **
741 01:28:12.835409 Couldn't find partition mmc 0
742 01:28:12.839795 Error: could not access storage.
743 01:28:13.137452 Net: eth0: ethernet@ff3f0000
744 01:28:13.138221 starting USB...
745 01:28:13.382144 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 01:28:13.382878 Starting the controller
747 01:28:13.388231 USB XHCI 1.10
748 01:28:14.945288 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 01:28:14.952768 scanning usb for storage devices... 0 Storage Device(s) found
751 01:28:15.004629 Hit any key to stop autoboot: 1
752 01:28:15.005638 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
753 01:28:15.006294 start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
754 01:28:15.006785 Setting prompt string to ['=>']
755 01:28:15.007271 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:42)
756 01:28:15.019573 0
757 01:28:15.020478 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 01:28:15.121679 => setenv autoload no
760 01:28:15.122616 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 01:28:15.127477 setenv autoload no
763 01:28:15.228939 => setenv initrd_high 0xffffffff
764 01:28:15.229793 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 01:28:15.234370 setenv initrd_high 0xffffffff
767 01:28:15.335780 => setenv fdt_high 0xffffffff
768 01:28:15.336675 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 01:28:15.341053 setenv fdt_high 0xffffffff
771 01:28:15.442526 => dhcp
772 01:28:15.443441 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 01:28:15.447732 dhcp
774 01:28:16.353344 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 01:28:16.353931 Speed: 1000, full duplex
776 01:28:16.354353 BOOTP broadcast 1
777 01:28:16.375781 DHCP client bound to address 192.168.6.21 (22 ms)
779 01:28:16.477299 => setenv serverip 192.168.6.2
780 01:28:16.478202 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
781 01:28:16.482782 setenv serverip 192.168.6.2
783 01:28:16.584215 => tftpboot 0x01080000 956994/tftp-deploy-12u9rq7c/kernel/uImage
784 01:28:16.585181 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
785 01:28:16.591781 tftpboot 0x01080000 956994/tftp-deploy-12u9rq7c/kernel/uImage
786 01:28:16.592309 Speed: 1000, full duplex
787 01:28:16.592725 Using ethernet@ff3f0000 device
788 01:28:16.597304 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
789 01:28:16.602777 Filename '956994/tftp-deploy-12u9rq7c/kernel/uImage'.
790 01:28:16.607051 Load address: 0x1080000
791 01:28:18.936445 Loading: *################################################## 36.1 MiB
792 01:28:18.937063 15.5 MiB/s
793 01:28:18.937492 done
794 01:28:18.940747 Bytes transferred = 37880384 (2420240 hex)
796 01:28:19.042239 => tftpboot 0x08000000 956994/tftp-deploy-12u9rq7c/ramdisk/ramdisk.cpio.gz.uboot
797 01:28:19.042956 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
798 01:28:19.049737 tftpboot 0x08000000 956994/tftp-deploy-12u9rq7c/ramdisk/ramdisk.cpio.gz.uboot
799 01:28:19.050183 Speed: 1000, full duplex
800 01:28:19.050572 Using ethernet@ff3f0000 device
801 01:28:19.055201 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
802 01:28:19.064983 Filename '956994/tftp-deploy-12u9rq7c/ramdisk/ramdisk.cpio.gz.uboot'.
803 01:28:19.065413 Load address: 0x8000000
804 01:28:20.675851 Loading: *################################################# UDP wrong checksum 00000005 00000cab
805 01:28:25.677594 T UDP wrong checksum 00000005 00000cab
806 01:28:35.679725 T T UDP wrong checksum 00000005 00000cab
807 01:28:41.556296 T UDP wrong checksum 00000005 0000813e
808 01:28:55.682547 T T T UDP wrong checksum 00000005 00000cab
809 01:29:02.679198 T UDP wrong checksum 000000ff 0000016a
810 01:29:02.693109 UDP wrong checksum 000000ff 00008a5c
811 01:29:10.408720 T UDP wrong checksum 000000ff 0000de3b
812 01:29:10.426370 UDP wrong checksum 000000ff 0000742e
813 01:29:15.688296 T
814 01:29:15.688883 Retry count exceeded; starting again
816 01:29:15.690245 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
819 01:29:15.692046 end: 2.4 uboot-commands (duration 00:01:19) [common]
821 01:29:15.693405 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
823 01:29:15.694419 end: 2 uboot-action (duration 00:01:19) [common]
825 01:29:15.695942 Cleaning after the job
826 01:29:15.696532 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956994/tftp-deploy-12u9rq7c/ramdisk
827 01:29:15.697811 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956994/tftp-deploy-12u9rq7c/kernel
828 01:29:15.736661 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956994/tftp-deploy-12u9rq7c/dtb
829 01:29:15.738019 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956994/tftp-deploy-12u9rq7c/modules
830 01:29:15.758458 start: 4.1 power-off (timeout 00:00:30) [common]
831 01:29:15.759074 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
832 01:29:15.790835 >> OK - accepted request
833 01:29:15.793120 Returned 0 in 0 seconds
834 01:29:15.894299 end: 4.1 power-off (duration 00:00:00) [common]
836 01:29:15.895940 start: 4.2 read-feedback (timeout 00:10:00) [common]
837 01:29:15.897084 Listened to connection for namespace 'common' for up to 1s
838 01:29:16.897915 Finalising connection for namespace 'common'
839 01:29:16.898662 Disconnecting from shell: Finalise
840 01:29:16.899164 =>
841 01:29:17.000214 end: 4.2 read-feedback (duration 00:00:01) [common]
842 01:29:17.000880 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/956994
843 01:29:17.335108 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/956994
844 01:29:17.335714 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.