Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:53:42.027067 lava-dispatcher, installed at version: 2024.01
2 02:53:42.027906 start: 0 validate
3 02:53:42.028429 Start time: 2024-11-08 02:53:42.028399+00:00 (UTC)
4 02:53:42.028979 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:53:42.029536 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:53:42.069311 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:53:42.069863 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 02:53:42.099650 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:53:42.100301 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:53:42.129541 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:53:42.130052 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:53:42.161816 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:53:42.162307 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
14 02:53:42.199076 validate duration: 0.17
16 02:53:42.199920 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:53:42.200268 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:53:42.200588 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:53:42.201307 Not decompressing ramdisk as can be used compressed.
20 02:53:42.201775 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 02:53:42.202063 saving as /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/ramdisk/initrd.cpio.gz
22 02:53:42.202337 total size: 5628169 (5 MB)
23 02:53:42.239974 progress 0 % (0 MB)
24 02:53:42.247392 progress 5 % (0 MB)
25 02:53:42.255246 progress 10 % (0 MB)
26 02:53:42.261197 progress 15 % (0 MB)
27 02:53:42.265270 progress 20 % (1 MB)
28 02:53:42.268859 progress 25 % (1 MB)
29 02:53:42.272765 progress 30 % (1 MB)
30 02:53:42.276731 progress 35 % (1 MB)
31 02:53:42.280335 progress 40 % (2 MB)
32 02:53:42.284339 progress 45 % (2 MB)
33 02:53:42.287933 progress 50 % (2 MB)
34 02:53:42.291913 progress 55 % (2 MB)
35 02:53:42.295870 progress 60 % (3 MB)
36 02:53:42.299442 progress 65 % (3 MB)
37 02:53:42.303482 progress 70 % (3 MB)
38 02:53:42.307051 progress 75 % (4 MB)
39 02:53:42.311010 progress 80 % (4 MB)
40 02:53:42.314565 progress 85 % (4 MB)
41 02:53:42.318504 progress 90 % (4 MB)
42 02:53:42.322292 progress 95 % (5 MB)
43 02:53:42.325523 progress 100 % (5 MB)
44 02:53:42.326153 5 MB downloaded in 0.12 s (43.35 MB/s)
45 02:53:42.326687 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:53:42.327590 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:53:42.327901 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:53:42.328211 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:53:42.328833 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/clang-16/kernel/Image
51 02:53:42.329100 saving as /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/kernel/Image
52 02:53:42.329324 total size: 37880320 (36 MB)
53 02:53:42.329542 No compression specified
54 02:53:42.363586 progress 0 % (0 MB)
55 02:53:42.387593 progress 5 % (1 MB)
56 02:53:42.411390 progress 10 % (3 MB)
57 02:53:42.435164 progress 15 % (5 MB)
58 02:53:42.458391 progress 20 % (7 MB)
59 02:53:42.482199 progress 25 % (9 MB)
60 02:53:42.505421 progress 30 % (10 MB)
61 02:53:42.528864 progress 35 % (12 MB)
62 02:53:42.552492 progress 40 % (14 MB)
63 02:53:42.576532 progress 45 % (16 MB)
64 02:53:42.599909 progress 50 % (18 MB)
65 02:53:42.622948 progress 55 % (19 MB)
66 02:53:42.646408 progress 60 % (21 MB)
67 02:53:42.669725 progress 65 % (23 MB)
68 02:53:42.693494 progress 70 % (25 MB)
69 02:53:42.716935 progress 75 % (27 MB)
70 02:53:42.739795 progress 80 % (28 MB)
71 02:53:42.763182 progress 85 % (30 MB)
72 02:53:42.787057 progress 90 % (32 MB)
73 02:53:42.810309 progress 95 % (34 MB)
74 02:53:42.833258 progress 100 % (36 MB)
75 02:53:42.833729 36 MB downloaded in 0.50 s (71.62 MB/s)
76 02:53:42.834197 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:53:42.835003 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:53:42.835273 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:53:42.835535 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:53:42.836022 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 02:53:42.836294 saving as /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/dtb/meson-g12b-a311d-libretech-cc.dtb
83 02:53:42.836501 total size: 54703 (0 MB)
84 02:53:42.836708 No compression specified
85 02:53:42.875410 progress 59 % (0 MB)
86 02:53:42.876284 progress 100 % (0 MB)
87 02:53:42.876826 0 MB downloaded in 0.04 s (1.29 MB/s)
88 02:53:42.877290 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:53:42.878095 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:53:42.878356 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:53:42.878615 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:53:42.879056 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 02:53:42.879292 saving as /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/nfsrootfs/full.rootfs.tar
95 02:53:42.879496 total size: 120894716 (115 MB)
96 02:53:42.879703 Using unxz to decompress xz
97 02:53:42.915688 progress 0 % (0 MB)
98 02:53:43.705742 progress 5 % (5 MB)
99 02:53:44.543235 progress 10 % (11 MB)
100 02:53:45.338704 progress 15 % (17 MB)
101 02:53:46.079801 progress 20 % (23 MB)
102 02:53:46.674731 progress 25 % (28 MB)
103 02:53:47.560398 progress 30 % (34 MB)
104 02:53:48.343706 progress 35 % (40 MB)
105 02:53:48.715835 progress 40 % (46 MB)
106 02:53:49.107849 progress 45 % (51 MB)
107 02:53:49.829537 progress 50 % (57 MB)
108 02:53:50.713461 progress 55 % (63 MB)
109 02:53:51.498357 progress 60 % (69 MB)
110 02:53:52.262575 progress 65 % (74 MB)
111 02:53:53.047854 progress 70 % (80 MB)
112 02:53:53.879658 progress 75 % (86 MB)
113 02:53:54.677446 progress 80 % (92 MB)
114 02:53:55.446778 progress 85 % (98 MB)
115 02:53:56.308706 progress 90 % (103 MB)
116 02:53:57.086832 progress 95 % (109 MB)
117 02:53:57.920897 progress 100 % (115 MB)
118 02:53:57.933404 115 MB downloaded in 15.05 s (7.66 MB/s)
119 02:53:57.934138 end: 1.4.1 http-download (duration 00:00:15) [common]
121 02:53:57.935926 end: 1.4 download-retry (duration 00:00:15) [common]
122 02:53:57.936560 start: 1.5 download-retry (timeout 00:09:44) [common]
123 02:53:57.937140 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 02:53:57.938035 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/clang-16/modules.tar.xz
125 02:53:57.938545 saving as /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/modules/modules.tar
126 02:53:57.939000 total size: 11768564 (11 MB)
127 02:53:57.939463 Using unxz to decompress xz
128 02:53:57.983167 progress 0 % (0 MB)
129 02:53:58.050446 progress 5 % (0 MB)
130 02:53:58.125498 progress 10 % (1 MB)
131 02:53:58.221163 progress 15 % (1 MB)
132 02:53:58.317558 progress 20 % (2 MB)
133 02:53:58.396863 progress 25 % (2 MB)
134 02:53:58.474039 progress 30 % (3 MB)
135 02:53:58.554923 progress 35 % (3 MB)
136 02:53:58.635353 progress 40 % (4 MB)
137 02:53:58.711264 progress 45 % (5 MB)
138 02:53:58.799063 progress 50 % (5 MB)
139 02:53:58.880753 progress 55 % (6 MB)
140 02:53:58.965634 progress 60 % (6 MB)
141 02:53:59.046884 progress 65 % (7 MB)
142 02:53:59.128667 progress 70 % (7 MB)
143 02:53:59.211753 progress 75 % (8 MB)
144 02:53:59.295677 progress 80 % (9 MB)
145 02:53:59.376553 progress 85 % (9 MB)
146 02:53:59.463803 progress 90 % (10 MB)
147 02:53:59.543500 progress 95 % (10 MB)
148 02:53:59.621618 progress 100 % (11 MB)
149 02:53:59.632243 11 MB downloaded in 1.69 s (6.63 MB/s)
150 02:53:59.632982 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:53:59.634832 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:53:59.635419 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 02:53:59.636052 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 02:54:16.048894 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/957003/extract-nfsrootfs-ubfb6k11
156 02:54:16.049503 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 02:54:16.049790 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 02:54:16.050476 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum
159 02:54:16.050914 makedir: /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin
160 02:54:16.051236 makedir: /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/tests
161 02:54:16.051544 makedir: /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/results
162 02:54:16.051869 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-add-keys
163 02:54:16.052432 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-add-sources
164 02:54:16.052932 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-background-process-start
165 02:54:16.053423 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-background-process-stop
166 02:54:16.053949 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-common-functions
167 02:54:16.054543 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-echo-ipv4
168 02:54:16.055078 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-install-packages
169 02:54:16.055555 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-installed-packages
170 02:54:16.056116 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-os-build
171 02:54:16.056607 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-probe-channel
172 02:54:16.057076 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-probe-ip
173 02:54:16.057575 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-target-ip
174 02:54:16.058086 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-target-mac
175 02:54:16.058560 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-target-storage
176 02:54:16.059033 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-test-case
177 02:54:16.059497 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-test-event
178 02:54:16.059956 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-test-feedback
179 02:54:16.060465 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-test-raise
180 02:54:16.060934 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-test-reference
181 02:54:16.061430 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-test-runner
182 02:54:16.061930 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-test-set
183 02:54:16.062399 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-test-shell
184 02:54:16.062876 Updating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-add-keys (debian)
185 02:54:16.063401 Updating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-add-sources (debian)
186 02:54:16.063887 Updating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-install-packages (debian)
187 02:54:16.064435 Updating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-installed-packages (debian)
188 02:54:16.064926 Updating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/bin/lava-os-build (debian)
189 02:54:16.065347 Creating /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/environment
190 02:54:16.065705 LAVA metadata
191 02:54:16.065969 - LAVA_JOB_ID=957003
192 02:54:16.066182 - LAVA_DISPATCHER_IP=192.168.6.2
193 02:54:16.066542 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 02:54:16.067483 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 02:54:16.067792 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 02:54:16.068023 skipped lava-vland-overlay
197 02:54:16.068266 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 02:54:16.068520 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 02:54:16.068735 skipped lava-multinode-overlay
200 02:54:16.068973 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 02:54:16.069306 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 02:54:16.069560 Loading test definitions
203 02:54:16.069839 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 02:54:16.070055 Using /lava-957003 at stage 0
205 02:54:16.071156 uuid=957003_1.6.2.4.1 testdef=None
206 02:54:16.071458 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 02:54:16.071716 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 02:54:16.073280 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 02:54:16.074059 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 02:54:16.075931 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 02:54:16.076775 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 02:54:16.078571 runner path: /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/0/tests/0_timesync-off test_uuid 957003_1.6.2.4.1
215 02:54:16.079111 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 02:54:16.079912 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 02:54:16.080161 Using /lava-957003 at stage 0
219 02:54:16.080512 Fetching tests from https://github.com/kernelci/test-definitions.git
220 02:54:16.080798 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/0/tests/1_kselftest-dt'
221 02:54:19.782667 Running '/usr/bin/git checkout kernelci.org
222 02:54:20.230476 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 02:54:20.231909 uuid=957003_1.6.2.4.5 testdef=None
224 02:54:20.232283 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 02:54:20.233023 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 02:54:20.235827 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 02:54:20.236659 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 02:54:20.240297 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 02:54:20.241149 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 02:54:20.244673 runner path: /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/0/tests/1_kselftest-dt test_uuid 957003_1.6.2.4.5
234 02:54:20.244952 BOARD='meson-g12b-a311d-libretech-cc'
235 02:54:20.245155 BRANCH='mainline'
236 02:54:20.245350 SKIPFILE='/dev/null'
237 02:54:20.245545 SKIP_INSTALL='True'
238 02:54:20.245737 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/clang-16/kselftest.tar.xz'
239 02:54:20.245934 TST_CASENAME=''
240 02:54:20.246127 TST_CMDFILES='dt'
241 02:54:20.246649 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 02:54:20.247423 Creating lava-test-runner.conf files
244 02:54:20.247625 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/957003/lava-overlay-yj8mjtum/lava-957003/0 for stage 0
245 02:54:20.248059 - 0_timesync-off
246 02:54:20.248319 - 1_kselftest-dt
247 02:54:20.248655 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 02:54:20.248935 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 02:54:43.487579 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 02:54:43.488055 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 02:54:43.488361 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 02:54:43.488674 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 02:54:43.488969 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 02:54:44.138164 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 02:54:44.138648 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 02:54:44.138900 extracting modules file /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/modules/modules.tar to /var/lib/lava/dispatcher/tmp/957003/extract-nfsrootfs-ubfb6k11
257 02:54:45.627638 extracting modules file /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/modules/modules.tar to /var/lib/lava/dispatcher/tmp/957003/extract-overlay-ramdisk-uqdom7yz/ramdisk
258 02:54:47.035494 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 02:54:47.035999 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 02:54:47.036299 [common] Applying overlay to NFS
261 02:54:47.036523 [common] Applying overlay /var/lib/lava/dispatcher/tmp/957003/compress-overlay-pxe3bd3z/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/957003/extract-nfsrootfs-ubfb6k11
262 02:54:49.729693 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 02:54:49.730161 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 02:54:49.730464 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 02:54:49.730725 Converting downloaded kernel to a uImage
266 02:54:49.731048 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/kernel/Image /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/kernel/uImage
267 02:54:50.126797 output: Image Name:
268 02:54:50.127224 output: Created: Fri Nov 8 02:54:49 2024
269 02:54:50.127434 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 02:54:50.127637 output: Data Size: 37880320 Bytes = 36992.50 KiB = 36.13 MiB
271 02:54:50.127838 output: Load Address: 01080000
272 02:54:50.128077 output: Entry Point: 01080000
273 02:54:50.128279 output:
274 02:54:50.128609 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 02:54:50.128878 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 02:54:50.129149 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 02:54:50.129405 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 02:54:50.129660 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 02:54:50.129916 Building ramdisk /var/lib/lava/dispatcher/tmp/957003/extract-overlay-ramdisk-uqdom7yz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/957003/extract-overlay-ramdisk-uqdom7yz/ramdisk
280 02:54:52.368190 >> 173443 blocks
281 02:55:00.018445 Adding RAMdisk u-boot header.
282 02:55:00.018899 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/957003/extract-overlay-ramdisk-uqdom7yz/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/957003/extract-overlay-ramdisk-uqdom7yz/ramdisk.cpio.gz.uboot
283 02:55:00.291084 output: Image Name:
284 02:55:00.291507 output: Created: Fri Nov 8 02:55:00 2024
285 02:55:00.291719 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 02:55:00.291922 output: Data Size: 24150081 Bytes = 23584.06 KiB = 23.03 MiB
287 02:55:00.292337 output: Load Address: 00000000
288 02:55:00.292778 output: Entry Point: 00000000
289 02:55:00.293217 output:
290 02:55:00.294232 rename /var/lib/lava/dispatcher/tmp/957003/extract-overlay-ramdisk-uqdom7yz/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/ramdisk/ramdisk.cpio.gz.uboot
291 02:55:00.294993 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 02:55:00.295588 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 02:55:00.296207 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 02:55:00.296712 No LXC device requested
295 02:55:00.297261 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 02:55:00.297820 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 02:55:00.298362 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 02:55:00.298809 Checking files for TFTP limit of 4294967296 bytes.
299 02:55:00.301723 end: 1 tftp-deploy (duration 00:01:18) [common]
300 02:55:00.302348 start: 2 uboot-action (timeout 00:05:00) [common]
301 02:55:00.302921 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 02:55:00.303465 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 02:55:00.304049 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 02:55:00.304642 Using kernel file from prepare-kernel: 957003/tftp-deploy-dz74c194/kernel/uImage
305 02:55:00.305351 substitutions:
306 02:55:00.305799 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 02:55:00.306244 - {DTB_ADDR}: 0x01070000
308 02:55:00.306685 - {DTB}: 957003/tftp-deploy-dz74c194/dtb/meson-g12b-a311d-libretech-cc.dtb
309 02:55:00.307129 - {INITRD}: 957003/tftp-deploy-dz74c194/ramdisk/ramdisk.cpio.gz.uboot
310 02:55:00.307568 - {KERNEL_ADDR}: 0x01080000
311 02:55:00.308031 - {KERNEL}: 957003/tftp-deploy-dz74c194/kernel/uImage
312 02:55:00.308472 - {LAVA_MAC}: None
313 02:55:00.308949 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/957003/extract-nfsrootfs-ubfb6k11
314 02:55:00.309391 - {NFS_SERVER_IP}: 192.168.6.2
315 02:55:00.309822 - {PRESEED_CONFIG}: None
316 02:55:00.310254 - {PRESEED_LOCAL}: None
317 02:55:00.310687 - {RAMDISK_ADDR}: 0x08000000
318 02:55:00.311116 - {RAMDISK}: 957003/tftp-deploy-dz74c194/ramdisk/ramdisk.cpio.gz.uboot
319 02:55:00.311550 - {ROOT_PART}: None
320 02:55:00.312022 - {ROOT}: None
321 02:55:00.312466 - {SERVER_IP}: 192.168.6.2
322 02:55:00.312897 - {TEE_ADDR}: 0x83000000
323 02:55:00.313324 - {TEE}: None
324 02:55:00.313753 Parsed boot commands:
325 02:55:00.314169 - setenv autoload no
326 02:55:00.314594 - setenv initrd_high 0xffffffff
327 02:55:00.315022 - setenv fdt_high 0xffffffff
328 02:55:00.315445 - dhcp
329 02:55:00.315868 - setenv serverip 192.168.6.2
330 02:55:00.316345 - tftpboot 0x01080000 957003/tftp-deploy-dz74c194/kernel/uImage
331 02:55:00.316785 - tftpboot 0x08000000 957003/tftp-deploy-dz74c194/ramdisk/ramdisk.cpio.gz.uboot
332 02:55:00.317217 - tftpboot 0x01070000 957003/tftp-deploy-dz74c194/dtb/meson-g12b-a311d-libretech-cc.dtb
333 02:55:00.317647 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/957003/extract-nfsrootfs-ubfb6k11,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 02:55:00.318090 - bootm 0x01080000 0x08000000 0x01070000
335 02:55:00.318644 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 02:55:00.320308 start: 2.3 connect-device (timeout 00:05:00) [common]
338 02:55:00.320769 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 02:55:00.336675 Setting prompt string to ['lava-test: # ']
340 02:55:00.338361 end: 2.3 connect-device (duration 00:00:00) [common]
341 02:55:00.339040 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 02:55:00.339649 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 02:55:00.340263 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 02:55:00.341738 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 02:55:00.383514 >> OK - accepted request
346 02:55:00.385664 Returned 0 in 0 seconds
347 02:55:00.486885 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 02:55:00.488747 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 02:55:00.489352 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 02:55:00.489902 Setting prompt string to ['Hit any key to stop autoboot']
352 02:55:00.490402 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 02:55:00.492132 Trying 192.168.56.21...
354 02:55:00.492649 Connected to conserv1.
355 02:55:00.493095 Escape character is '^]'.
356 02:55:00.493549
357 02:55:00.494007 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 02:55:00.494469
359 02:55:11.618768 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
360 02:55:11.619461 bl2_stage_init 0x81
361 02:55:11.624215 hw id: 0x0000 - pwm id 0x01
362 02:55:11.624758 bl2_stage_init 0xc1
363 02:55:11.625211 bl2_stage_init 0x02
364 02:55:11.625662
365 02:55:11.629789 L0:00000000
366 02:55:11.630297 L1:20000703
367 02:55:11.630758 L2:00008067
368 02:55:11.631206 L3:14000000
369 02:55:11.631648 B2:00402000
370 02:55:11.632790 B1:e0f83180
371 02:55:11.633282
372 02:55:11.633730 TE: 58150
373 02:55:11.634160
374 02:55:11.643879 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
375 02:55:11.644459
376 02:55:11.644909 Board ID = 1
377 02:55:11.645341 Set A53 clk to 24M
378 02:55:11.645769 Set A73 clk to 24M
379 02:55:11.649399 Set clk81 to 24M
380 02:55:11.649887 A53 clk: 1200 MHz
381 02:55:11.650323 A73 clk: 1200 MHz
382 02:55:11.654982 CLK81: 166.6M
383 02:55:11.655463 smccc: 00012aac
384 02:55:11.660654 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
385 02:55:11.661144 board id: 1
386 02:55:11.669268 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
387 02:55:11.679932 fw parse done
388 02:55:11.685876 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
389 02:55:11.728335 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
390 02:55:11.739233 PIEI prepare done
391 02:55:11.739720 fastboot data load
392 02:55:11.740210 fastboot data verify
393 02:55:11.744931 verify result: 266
394 02:55:11.750499 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
395 02:55:11.751002 LPDDR4 probe
396 02:55:11.751439 ddr clk to 1584MHz
397 02:55:11.758575 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
398 02:55:11.795763
399 02:55:11.796313 dmc_version 0001
400 02:55:11.802463 Check phy result
401 02:55:11.808314 INFO : End of CA training
402 02:55:11.808813 INFO : End of initialization
403 02:55:11.813910 INFO : Training has run successfully!
404 02:55:11.814406 Check phy result
405 02:55:11.819522 INFO : End of initialization
406 02:55:11.820041 INFO : End of read enable training
407 02:55:11.825089 INFO : End of fine write leveling
408 02:55:11.830699 INFO : End of Write leveling coarse delay
409 02:55:11.831192 INFO : Training has run successfully!
410 02:55:11.831628 Check phy result
411 02:55:11.836307 INFO : End of initialization
412 02:55:11.836801 INFO : End of read dq deskew training
413 02:55:11.841936 INFO : End of MPR read delay center optimization
414 02:55:11.847527 INFO : End of write delay center optimization
415 02:55:11.853131 INFO : End of read delay center optimization
416 02:55:11.853624 INFO : End of max read latency training
417 02:55:11.858716 INFO : Training has run successfully!
418 02:55:11.859228 1D training succeed
419 02:55:11.867841 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
420 02:55:11.915487 Check phy result
421 02:55:11.916046 INFO : End of initialization
422 02:55:11.937256 INFO : End of 2D read delay Voltage center optimization
423 02:55:11.957506 INFO : End of 2D read delay Voltage center optimization
424 02:55:12.009524 INFO : End of 2D write delay Voltage center optimization
425 02:55:12.059339 INFO : End of 2D write delay Voltage center optimization
426 02:55:12.064693 INFO : Training has run successfully!
427 02:55:12.065292
428 02:55:12.065707 channel==0
429 02:55:12.070080 RxClkDly_Margin_A0==88 ps 9
430 02:55:12.070677 TxDqDly_Margin_A0==98 ps 10
431 02:55:12.075767 RxClkDly_Margin_A1==88 ps 9
432 02:55:12.076304 TxDqDly_Margin_A1==98 ps 10
433 02:55:12.076716 TrainedVREFDQ_A0==74
434 02:55:12.081326 TrainedVREFDQ_A1==74
435 02:55:12.081948 VrefDac_Margin_A0==25
436 02:55:12.082352 DeviceVref_Margin_A0==40
437 02:55:12.086982 VrefDac_Margin_A1==25
438 02:55:12.087463 DeviceVref_Margin_A1==40
439 02:55:12.087865
440 02:55:12.088310
441 02:55:12.092666 channel==1
442 02:55:12.093271 RxClkDly_Margin_A0==98 ps 10
443 02:55:12.093672 TxDqDly_Margin_A0==98 ps 10
444 02:55:12.098054 RxClkDly_Margin_A1==98 ps 10
445 02:55:12.098511 TxDqDly_Margin_A1==108 ps 11
446 02:55:12.103636 TrainedVREFDQ_A0==77
447 02:55:12.104206 TrainedVREFDQ_A1==77
448 02:55:12.104612 VrefDac_Margin_A0==22
449 02:55:12.109224 DeviceVref_Margin_A0==37
450 02:55:12.109707 VrefDac_Margin_A1==22
451 02:55:12.114979 DeviceVref_Margin_A1==37
452 02:55:12.115427
453 02:55:12.120468 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
454 02:55:12.120918
455 02:55:12.148460 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
456 02:55:12.149008 2D training succeed
457 02:55:12.153997 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
458 02:55:12.159592 auto size-- 65535DDR cs0 size: 2048MB
459 02:55:12.160087 DDR cs1 size: 2048MB
460 02:55:12.165182 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
461 02:55:12.165633 cs0 DataBus test pass
462 02:55:12.170772 cs1 DataBus test pass
463 02:55:12.171206 cs0 AddrBus test pass
464 02:55:12.171596 cs1 AddrBus test pass
465 02:55:12.172013
466 02:55:12.176433 100bdlr_step_size ps== 420
467 02:55:12.176869 result report
468 02:55:12.181998 boot times 0Enable ddr reg access
469 02:55:12.187592 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
470 02:55:12.201090 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
471 02:55:12.774894 0.0;M3 CHK:0;cm4_sp_mode 0
472 02:55:12.775525 MVN_1=0x00000000
473 02:55:12.780224 MVN_2=0x00000000
474 02:55:12.785997 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
475 02:55:12.786447 OPS=0x10
476 02:55:12.786858 ring efuse init
477 02:55:12.787256 chipver efuse init
478 02:55:12.791568 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
479 02:55:12.797177 [0.018960 Inits done]
480 02:55:12.797613 secure task start!
481 02:55:12.798021 high task start!
482 02:55:12.801768 low task start!
483 02:55:12.802229 run into bl31
484 02:55:12.808416 NOTICE: BL31: v1.3(release):4fc40b1
485 02:55:12.816203 NOTICE: BL31: Built : 15:58:17, May 22 2019
486 02:55:12.816644 NOTICE: BL31: G12A normal boot!
487 02:55:12.842136 NOTICE: BL31: BL33 decompress pass
488 02:55:12.847818 ERROR: Error initializing runtime service opteed_fast
489 02:55:14.080795
490 02:55:14.081421
491 02:55:14.089056 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
492 02:55:14.089525
493 02:55:14.089944 Model: Libre Computer AML-A311D-CC Alta
494 02:55:14.297445 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
495 02:55:14.320842 DRAM: 2 GiB (effective 3.8 GiB)
496 02:55:14.464049 Core: 408 devices, 31 uclasses, devicetree: separate
497 02:55:14.469726 WDT: Not starting watchdog@f0d0
498 02:55:14.501965 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
499 02:55:14.514421 Loading Environment from FAT... Card did not respond to voltage select! : -110
500 02:55:14.519386 ** Bad device specification mmc 0 **
501 02:55:14.529767 Card did not respond to voltage select! : -110
502 02:55:14.537381 ** Bad device specification mmc 0 **
503 02:55:14.537740 Couldn't find partition mmc 0
504 02:55:14.545792 Card did not respond to voltage select! : -110
505 02:55:14.551269 ** Bad device specification mmc 0 **
506 02:55:14.551772 Couldn't find partition mmc 0
507 02:55:14.556302 Error: could not access storage.
508 02:55:15.818831 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
509 02:55:15.819454 bl2_stage_init 0x01
510 02:55:15.819887 bl2_stage_init 0x81
511 02:55:15.824363 hw id: 0x0000 - pwm id 0x01
512 02:55:15.824816 bl2_stage_init 0xc1
513 02:55:15.825226 bl2_stage_init 0x02
514 02:55:15.825628
515 02:55:15.829986 L0:00000000
516 02:55:15.830416 L1:20000703
517 02:55:15.830819 L2:00008067
518 02:55:15.831215 L3:14000000
519 02:55:15.835565 B2:00402000
520 02:55:15.836027 B1:e0f83180
521 02:55:15.836443
522 02:55:15.836844 TE: 58167
523 02:55:15.837242
524 02:55:15.841146 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 02:55:15.841583
526 02:55:15.841987 Board ID = 1
527 02:55:15.846731 Set A53 clk to 24M
528 02:55:15.847167 Set A73 clk to 24M
529 02:55:15.847573 Set clk81 to 24M
530 02:55:15.852334 A53 clk: 1200 MHz
531 02:55:15.852766 A73 clk: 1200 MHz
532 02:55:15.853193 CLK81: 166.6M
533 02:55:15.853589 smccc: 00012abe
534 02:55:15.857995 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 02:55:15.863517 board id: 1
536 02:55:15.869428 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 02:55:15.880074 fw parse done
538 02:55:15.886067 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 02:55:15.928701 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 02:55:15.939580 PIEI prepare done
541 02:55:15.940068 fastboot data load
542 02:55:15.940477 fastboot data verify
543 02:55:15.945198 verify result: 266
544 02:55:15.950785 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 02:55:15.951213 LPDDR4 probe
546 02:55:15.951604 ddr clk to 1584MHz
547 02:55:15.958771 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 02:55:15.996065
549 02:55:15.996520 dmc_version 0001
550 02:55:16.002678 Check phy result
551 02:55:16.008556 INFO : End of CA training
552 02:55:16.008978 INFO : End of initialization
553 02:55:16.014189 INFO : Training has run successfully!
554 02:55:16.014658 Check phy result
555 02:55:16.019743 INFO : End of initialization
556 02:55:16.020225 INFO : End of read enable training
557 02:55:16.025371 INFO : End of fine write leveling
558 02:55:16.030969 INFO : End of Write leveling coarse delay
559 02:55:16.031394 INFO : Training has run successfully!
560 02:55:16.031785 Check phy result
561 02:55:16.036576 INFO : End of initialization
562 02:55:16.037002 INFO : End of read dq deskew training
563 02:55:16.042153 INFO : End of MPR read delay center optimization
564 02:55:16.047768 INFO : End of write delay center optimization
565 02:55:16.053368 INFO : End of read delay center optimization
566 02:55:16.053800 INFO : End of max read latency training
567 02:55:16.058969 INFO : Training has run successfully!
568 02:55:16.059392 1D training succeed
569 02:55:16.068203 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 02:55:16.115741 Check phy result
571 02:55:16.116220 INFO : End of initialization
572 02:55:16.137439 INFO : End of 2D read delay Voltage center optimization
573 02:55:16.157682 INFO : End of 2D read delay Voltage center optimization
574 02:55:16.209727 INFO : End of 2D write delay Voltage center optimization
575 02:55:16.259097 INFO : End of 2D write delay Voltage center optimization
576 02:55:16.264675 INFO : Training has run successfully!
577 02:55:16.265111
578 02:55:16.265507 channel==0
579 02:55:16.270284 RxClkDly_Margin_A0==88 ps 9
580 02:55:16.270709 TxDqDly_Margin_A0==98 ps 10
581 02:55:16.275912 RxClkDly_Margin_A1==88 ps 9
582 02:55:16.276446 TxDqDly_Margin_A1==98 ps 10
583 02:55:16.276846 TrainedVREFDQ_A0==74
584 02:55:16.281477 TrainedVREFDQ_A1==74
585 02:55:16.281910 VrefDac_Margin_A0==25
586 02:55:16.282300 DeviceVref_Margin_A0==40
587 02:55:16.287074 VrefDac_Margin_A1==25
588 02:55:16.287506 DeviceVref_Margin_A1==40
589 02:55:16.287898
590 02:55:16.288321
591 02:55:16.292687 channel==1
592 02:55:16.293121 RxClkDly_Margin_A0==98 ps 10
593 02:55:16.293510 TxDqDly_Margin_A0==98 ps 10
594 02:55:16.298257 RxClkDly_Margin_A1==98 ps 10
595 02:55:16.298683 TxDqDly_Margin_A1==88 ps 9
596 02:55:16.303862 TrainedVREFDQ_A0==77
597 02:55:16.304329 TrainedVREFDQ_A1==77
598 02:55:16.304726 VrefDac_Margin_A0==22
599 02:55:16.309513 DeviceVref_Margin_A0==37
600 02:55:16.309940 VrefDac_Margin_A1==22
601 02:55:16.315092 DeviceVref_Margin_A1==37
602 02:55:16.315516
603 02:55:16.315907 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 02:55:16.320676
605 02:55:16.348712 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
606 02:55:16.349242 2D training succeed
607 02:55:16.354262 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 02:55:16.359872 auto size-- 65535DDR cs0 size: 2048MB
609 02:55:16.360345 DDR cs1 size: 2048MB
610 02:55:16.365479 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 02:55:16.365918 cs0 DataBus test pass
612 02:55:16.371083 cs1 DataBus test pass
613 02:55:16.371538 cs0 AddrBus test pass
614 02:55:16.371933 cs1 AddrBus test pass
615 02:55:16.372357
616 02:55:16.376687 100bdlr_step_size ps== 420
617 02:55:16.377142 result report
618 02:55:16.382285 boot times 0Enable ddr reg access
619 02:55:16.387694 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 02:55:16.401322 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 02:55:16.975068 0.0;M3 CHK:0;cm4_sp_mode 0
622 02:55:16.975691 MVN_1=0x00000000
623 02:55:16.980447 MVN_2=0x00000000
624 02:55:16.986293 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 02:55:16.986786 OPS=0x10
626 02:55:16.987226 ring efuse init
627 02:55:16.987621 chipver efuse init
628 02:55:16.991821 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 02:55:16.997492 [0.018960 Inits done]
630 02:55:16.997926 secure task start!
631 02:55:16.998314 high task start!
632 02:55:17.002086 low task start!
633 02:55:17.002502 run into bl31
634 02:55:17.008659 NOTICE: BL31: v1.3(release):4fc40b1
635 02:55:17.016476 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 02:55:17.016945 NOTICE: BL31: G12A normal boot!
637 02:55:17.041868 NOTICE: BL31: BL33 decompress pass
638 02:55:17.047553 ERROR: Error initializing runtime service opteed_fast
639 02:55:18.280637
640 02:55:18.281265
641 02:55:18.288890 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 02:55:18.289340
643 02:55:18.289753 Model: Libre Computer AML-A311D-CC Alta
644 02:55:18.497507 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 02:55:18.520707 DRAM: 2 GiB (effective 3.8 GiB)
646 02:55:18.663562 Core: 408 devices, 31 uclasses, devicetree: separate
647 02:55:18.669564 WDT: Not starting watchdog@f0d0
648 02:55:18.701643 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 02:55:18.714127 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 02:55:18.719139 ** Bad device specification mmc 0 **
651 02:55:18.729437 Card did not respond to voltage select! : -110
652 02:55:18.737139 ** Bad device specification mmc 0 **
653 02:55:18.737570 Couldn't find partition mmc 0
654 02:55:18.745435 Card did not respond to voltage select! : -110
655 02:55:18.751016 ** Bad device specification mmc 0 **
656 02:55:18.751447 Couldn't find partition mmc 0
657 02:55:18.756086 Error: could not access storage.
658 02:55:19.098599 Net: eth0: ethernet@ff3f0000
659 02:55:19.099146 starting USB...
660 02:55:19.350306 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 02:55:19.350841 Starting the controller
662 02:55:19.357304 USB XHCI 1.10
663 02:55:21.067700 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
664 02:55:21.068369 bl2_stage_init 0x01
665 02:55:21.068803 bl2_stage_init 0x81
666 02:55:21.073174 hw id: 0x0000 - pwm id 0x01
667 02:55:21.073623 bl2_stage_init 0xc1
668 02:55:21.074033 bl2_stage_init 0x02
669 02:55:21.074433
670 02:55:21.078791 L0:00000000
671 02:55:21.079223 L1:20000703
672 02:55:21.079622 L2:00008067
673 02:55:21.080048 L3:14000000
674 02:55:21.081794 B2:00402000
675 02:55:21.082224 B1:e0f83180
676 02:55:21.082624
677 02:55:21.083022 TE: 58124
678 02:55:21.083419
679 02:55:21.092925 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 02:55:21.093366
681 02:55:21.093771 Board ID = 1
682 02:55:21.094167 Set A53 clk to 24M
683 02:55:21.094559 Set A73 clk to 24M
684 02:55:21.098525 Set clk81 to 24M
685 02:55:21.098959 A53 clk: 1200 MHz
686 02:55:21.099358 A73 clk: 1200 MHz
687 02:55:21.104103 CLK81: 166.6M
688 02:55:21.104540 smccc: 00012a92
689 02:55:21.109823 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 02:55:21.110263 board id: 1
691 02:55:21.118338 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 02:55:21.129031 fw parse done
693 02:55:21.135001 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 02:55:21.177404 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 02:55:21.188349 PIEI prepare done
696 02:55:21.188784 fastboot data load
697 02:55:21.189188 fastboot data verify
698 02:55:21.193910 verify result: 266
699 02:55:21.199535 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 02:55:21.199964 LPDDR4 probe
701 02:55:21.200416 ddr clk to 1584MHz
702 02:55:21.207651 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 02:55:21.244846
704 02:55:21.245293 dmc_version 0001
705 02:55:21.251438 Check phy result
706 02:55:21.257294 INFO : End of CA training
707 02:55:21.257716 INFO : End of initialization
708 02:55:21.262924 INFO : Training has run successfully!
709 02:55:21.263354 Check phy result
710 02:55:21.268515 INFO : End of initialization
711 02:55:21.268962 INFO : End of read enable training
712 02:55:21.274103 INFO : End of fine write leveling
713 02:55:21.279672 INFO : End of Write leveling coarse delay
714 02:55:21.280130 INFO : Training has run successfully!
715 02:55:21.280534 Check phy result
716 02:55:21.285308 INFO : End of initialization
717 02:55:21.285734 INFO : End of read dq deskew training
718 02:55:21.290889 INFO : End of MPR read delay center optimization
719 02:55:21.296482 INFO : End of write delay center optimization
720 02:55:21.302082 INFO : End of read delay center optimization
721 02:55:21.302504 INFO : End of max read latency training
722 02:55:21.307688 INFO : Training has run successfully!
723 02:55:21.308153 1D training succeed
724 02:55:21.316909 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 02:55:21.364470 Check phy result
726 02:55:21.364933 INFO : End of initialization
727 02:55:21.386257 INFO : End of 2D read delay Voltage center optimization
728 02:55:21.406546 INFO : End of 2D read delay Voltage center optimization
729 02:55:21.458613 INFO : End of 2D write delay Voltage center optimization
730 02:55:21.507869 INFO : End of 2D write delay Voltage center optimization
731 02:55:21.513405 INFO : Training has run successfully!
732 02:55:21.513855
733 02:55:21.514264 channel==0
734 02:55:21.519011 RxClkDly_Margin_A0==88 ps 9
735 02:55:21.519468 TxDqDly_Margin_A0==98 ps 10
736 02:55:21.524628 RxClkDly_Margin_A1==88 ps 9
737 02:55:21.525101 TxDqDly_Margin_A1==98 ps 10
738 02:55:21.525517 TrainedVREFDQ_A0==74
739 02:55:21.530215 TrainedVREFDQ_A1==74
740 02:55:21.530671 VrefDac_Margin_A0==25
741 02:55:21.531076 DeviceVref_Margin_A0==40
742 02:55:21.535801 VrefDac_Margin_A1==25
743 02:55:21.536276 DeviceVref_Margin_A1==40
744 02:55:21.536678
745 02:55:21.537083
746 02:55:21.541397 channel==1
747 02:55:21.541846 RxClkDly_Margin_A0==98 ps 10
748 02:55:21.542251 TxDqDly_Margin_A0==88 ps 9
749 02:55:21.546960 RxClkDly_Margin_A1==98 ps 10
750 02:55:21.547412 TxDqDly_Margin_A1==88 ps 9
751 02:55:21.552581 TrainedVREFDQ_A0==76
752 02:55:21.553029 TrainedVREFDQ_A1==77
753 02:55:21.553438 VrefDac_Margin_A0==22
754 02:55:21.558185 DeviceVref_Margin_A0==38
755 02:55:21.558649 VrefDac_Margin_A1==24
756 02:55:21.563793 DeviceVref_Margin_A1==37
757 02:55:21.564269
758 02:55:21.564681 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 02:55:21.565085
760 02:55:21.597378 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
761 02:55:21.597870 2D training succeed
762 02:55:21.602960 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 02:55:21.608954 auto size-- 65535DDR cs0 size: 2048MB
764 02:55:21.609385 DDR cs1 size: 2048MB
765 02:55:21.614250 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 02:55:21.614680 cs0 DataBus test pass
767 02:55:21.619788 cs1 DataBus test pass
768 02:55:21.620255 cs0 AddrBus test pass
769 02:55:21.620658 cs1 AddrBus test pass
770 02:55:21.621047
771 02:55:21.625393 100bdlr_step_size ps== 420
772 02:55:21.625835 result report
773 02:55:21.631005 boot times 0Enable ddr reg access
774 02:55:21.636350 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 02:55:21.649857 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 02:55:22.223585 0.0;M3 CHK:0;cm4_sp_mode 0
777 02:55:22.224205 MVN_1=0x00000000
778 02:55:22.229093 MVN_2=0x00000000
779 02:55:22.234867 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 02:55:22.235402 OPS=0x10
781 02:55:22.235796 ring efuse init
782 02:55:22.236270 chipver efuse init
783 02:55:22.240436 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 02:55:22.246033 [0.018961 Inits done]
785 02:55:22.246459 secure task start!
786 02:55:22.246843 high task start!
787 02:55:22.250583 low task start!
788 02:55:22.251004 run into bl31
789 02:55:22.257245 NOTICE: BL31: v1.3(release):4fc40b1
790 02:55:22.265086 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 02:55:22.265522 NOTICE: BL31: G12A normal boot!
792 02:55:22.290475 NOTICE: BL31: BL33 decompress pass
793 02:55:22.296164 ERROR: Error initializing runtime service opteed_fast
794 02:55:23.529165
795 02:55:23.529791
796 02:55:23.537415 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 02:55:23.537886
798 02:55:23.538299 Model: Libre Computer AML-A311D-CC Alta
799 02:55:23.745940 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 02:55:23.769255 DRAM: 2 GiB (effective 3.8 GiB)
801 02:55:23.912296 Core: 408 devices, 31 uclasses, devicetree: separate
802 02:55:23.918138 WDT: Not starting watchdog@f0d0
803 02:55:23.950354 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 02:55:23.962822 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 02:55:23.967794 ** Bad device specification mmc 0 **
806 02:55:23.978170 Card did not respond to voltage select! : -110
807 02:55:23.985801 ** Bad device specification mmc 0 **
808 02:55:23.986259 Couldn't find partition mmc 0
809 02:55:23.994138 Card did not respond to voltage select! : -110
810 02:55:23.999665 ** Bad device specification mmc 0 **
811 02:55:24.000157 Couldn't find partition mmc 0
812 02:55:24.004712 Error: could not access storage.
813 02:55:24.347237 Net: eth0: ethernet@ff3f0000
814 02:55:24.347824 starting USB...
815 02:55:24.599106 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 02:55:24.599687 Starting the controller
817 02:55:24.605947 USB XHCI 1.10
818 02:55:26.768746 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 02:55:26.769344 bl2_stage_init 0x01
820 02:55:26.769763 bl2_stage_init 0x81
821 02:55:26.774353 hw id: 0x0000 - pwm id 0x01
822 02:55:26.774790 bl2_stage_init 0xc1
823 02:55:26.775194 bl2_stage_init 0x02
824 02:55:26.775594
825 02:55:26.779887 L0:00000000
826 02:55:26.780351 L1:20000703
827 02:55:26.780756 L2:00008067
828 02:55:26.781148 L3:14000000
829 02:55:26.785541 B2:00402000
830 02:55:26.785968 B1:e0f83180
831 02:55:26.786368
832 02:55:26.786768 TE: 58167
833 02:55:26.787162
834 02:55:26.791118 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 02:55:26.791553
836 02:55:26.791955 Board ID = 1
837 02:55:26.796712 Set A53 clk to 24M
838 02:55:26.797138 Set A73 clk to 24M
839 02:55:26.797533 Set clk81 to 24M
840 02:55:26.802319 A53 clk: 1200 MHz
841 02:55:26.802748 A73 clk: 1200 MHz
842 02:55:26.803143 CLK81: 166.6M
843 02:55:26.803537 smccc: 00012abe
844 02:55:26.807857 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 02:55:26.813407 board id: 1
846 02:55:26.819534 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 02:55:26.829837 fw parse done
848 02:55:26.835804 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 02:55:26.878446 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 02:55:26.889325 PIEI prepare done
851 02:55:26.889749 fastboot data load
852 02:55:26.890152 fastboot data verify
853 02:55:26.894946 verify result: 266
854 02:55:26.900534 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 02:55:26.900958 LPDDR4 probe
856 02:55:26.901355 ddr clk to 1584MHz
857 02:55:26.908541 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 02:55:26.945773
859 02:55:26.946206 dmc_version 0001
860 02:55:26.952445 Check phy result
861 02:55:26.958332 INFO : End of CA training
862 02:55:26.958754 INFO : End of initialization
863 02:55:26.963913 INFO : Training has run successfully!
864 02:55:26.964379 Check phy result
865 02:55:26.969508 INFO : End of initialization
866 02:55:26.969934 INFO : End of read enable training
867 02:55:26.975115 INFO : End of fine write leveling
868 02:55:26.980736 INFO : End of Write leveling coarse delay
869 02:55:26.981176 INFO : Training has run successfully!
870 02:55:26.981578 Check phy result
871 02:55:26.986349 INFO : End of initialization
872 02:55:26.986775 INFO : End of read dq deskew training
873 02:55:26.991920 INFO : End of MPR read delay center optimization
874 02:55:26.997518 INFO : End of write delay center optimization
875 02:55:27.003116 INFO : End of read delay center optimization
876 02:55:27.003545 INFO : End of max read latency training
877 02:55:27.008714 INFO : Training has run successfully!
878 02:55:27.009141 1D training succeed
879 02:55:27.017930 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 02:55:27.065513 Check phy result
881 02:55:27.066005 INFO : End of initialization
882 02:55:27.087251 INFO : End of 2D read delay Voltage center optimization
883 02:55:27.107495 INFO : End of 2D read delay Voltage center optimization
884 02:55:27.159626 INFO : End of 2D write delay Voltage center optimization
885 02:55:27.208896 INFO : End of 2D write delay Voltage center optimization
886 02:55:27.214503 INFO : Training has run successfully!
887 02:55:27.214928
888 02:55:27.215334 channel==0
889 02:55:27.220114 RxClkDly_Margin_A0==88 ps 9
890 02:55:27.220541 TxDqDly_Margin_A0==98 ps 10
891 02:55:27.225694 RxClkDly_Margin_A1==88 ps 9
892 02:55:27.226113 TxDqDly_Margin_A1==98 ps 10
893 02:55:27.226535 TrainedVREFDQ_A0==74
894 02:55:27.231302 TrainedVREFDQ_A1==74
895 02:55:27.231778 VrefDac_Margin_A0==25
896 02:55:27.232289 DeviceVref_Margin_A0==40
897 02:55:27.236900 VrefDac_Margin_A1==25
898 02:55:27.237348 DeviceVref_Margin_A1==40
899 02:55:27.237735
900 02:55:27.238122
901 02:55:27.242508 channel==1
902 02:55:27.242939 RxClkDly_Margin_A0==88 ps 9
903 02:55:27.243335 TxDqDly_Margin_A0==98 ps 10
904 02:55:27.248078 RxClkDly_Margin_A1==98 ps 10
905 02:55:27.248497 TxDqDly_Margin_A1==98 ps 10
906 02:55:27.253690 TrainedVREFDQ_A0==77
907 02:55:27.254104 TrainedVREFDQ_A1==77
908 02:55:27.254491 VrefDac_Margin_A0==22
909 02:55:27.259295 DeviceVref_Margin_A0==37
910 02:55:27.259702 VrefDac_Margin_A1==22
911 02:55:27.264885 DeviceVref_Margin_A1==37
912 02:55:27.265291
913 02:55:27.265677 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 02:55:27.270508
915 02:55:27.298523 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
916 02:55:27.298998 2D training succeed
917 02:55:27.304099 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 02:55:27.309672 auto size-- 65535DDR cs0 size: 2048MB
919 02:55:27.310087 DDR cs1 size: 2048MB
920 02:55:27.315252 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 02:55:27.315661 cs0 DataBus test pass
922 02:55:27.320878 cs1 DataBus test pass
923 02:55:27.321292 cs0 AddrBus test pass
924 02:55:27.321673 cs1 AddrBus test pass
925 02:55:27.322054
926 02:55:27.326493 100bdlr_step_size ps== 420
927 02:55:27.326922 result report
928 02:55:27.332103 boot times 0Enable ddr reg access
929 02:55:27.337537 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 02:55:27.351028 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 02:55:27.924694 0.0;M3 CHK:0;cm4_sp_mode 0
932 02:55:27.925277 MVN_1=0x00000000
933 02:55:27.930172 MVN_2=0x00000000
934 02:55:27.935920 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 02:55:27.936406 OPS=0x10
936 02:55:27.936820 ring efuse init
937 02:55:27.937219 chipver efuse init
938 02:55:27.944158 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 02:55:27.944608 [0.018961 Inits done]
940 02:55:27.950887 secure task start!
941 02:55:27.951348 high task start!
942 02:55:27.951761 low task start!
943 02:55:27.952201 run into bl31
944 02:55:27.958367 NOTICE: BL31: v1.3(release):4fc40b1
945 02:55:27.965258 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 02:55:27.965721 NOTICE: BL31: G12A normal boot!
947 02:55:27.991523 NOTICE: BL31: BL33 decompress pass
948 02:55:27.996344 ERROR: Error initializing runtime service opteed_fast
949 02:55:29.229990
950 02:55:29.230610
951 02:55:29.238404 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 02:55:29.238870
953 02:55:29.239300 Model: Libre Computer AML-A311D-CC Alta
954 02:55:29.447007 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 02:55:29.470232 DRAM: 2 GiB (effective 3.8 GiB)
956 02:55:29.613281 Core: 408 devices, 31 uclasses, devicetree: separate
957 02:55:29.619234 WDT: Not starting watchdog@f0d0
958 02:55:29.651462 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 02:55:29.663889 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 02:55:29.668885 ** Bad device specification mmc 0 **
961 02:55:29.679210 Card did not respond to voltage select! : -110
962 02:55:29.686883 ** Bad device specification mmc 0 **
963 02:55:29.687396 Couldn't find partition mmc 0
964 02:55:29.695163 Card did not respond to voltage select! : -110
965 02:55:29.700683 ** Bad device specification mmc 0 **
966 02:55:29.701214 Couldn't find partition mmc 0
967 02:55:29.705730 Error: could not access storage.
968 02:55:30.049183 Net: eth0: ethernet@ff3f0000
969 02:55:30.049795 starting USB...
970 02:55:30.300977 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 02:55:30.301584 Starting the controller
972 02:55:30.308096 USB XHCI 1.10
973 02:55:32.139008 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
974 02:55:32.139740 bl2_stage_init 0x81
975 02:55:32.144651 hw id: 0x0000 - pwm id 0x01
976 02:55:32.145200 bl2_stage_init 0xc1
977 02:55:32.145662 bl2_stage_init 0x02
978 02:55:32.146109
979 02:55:32.150204 L0:00000000
980 02:55:32.150743 L1:20000703
981 02:55:32.151196 L2:00008067
982 02:55:32.151638 L3:14000000
983 02:55:32.152114 B2:00402000
984 02:55:32.153094 B1:e0f83180
985 02:55:32.153603
986 02:55:32.154061 TE: 58150
987 02:55:32.154510
988 02:55:32.164277 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
989 02:55:32.164880
990 02:55:32.165355 Board ID = 1
991 02:55:32.165807 Set A53 clk to 24M
992 02:55:32.166251 Set A73 clk to 24M
993 02:55:32.169905 Set clk81 to 24M
994 02:55:32.170442 A53 clk: 1200 MHz
995 02:55:32.170897 A73 clk: 1200 MHz
996 02:55:32.175397 CLK81: 166.6M
997 02:55:32.175942 smccc: 00012aac
998 02:55:32.181096 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
999 02:55:32.181642 board id: 1
1000 02:55:32.189680 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1001 02:55:32.200344 fw parse done
1002 02:55:32.206282 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1003 02:55:32.248868 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1004 02:55:32.259805 PIEI prepare done
1005 02:55:32.260471 fastboot data load
1006 02:55:32.260921 fastboot data verify
1007 02:55:32.265441 verify result: 266
1008 02:55:32.270978 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1009 02:55:32.271474 LPDDR4 probe
1010 02:55:32.271907 ddr clk to 1584MHz
1011 02:55:32.278890 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1012 02:55:32.315167
1013 02:55:32.315689 dmc_version 0001
1014 02:55:32.321957 Check phy result
1015 02:55:32.328731 INFO : End of CA training
1016 02:55:32.329244 INFO : End of initialization
1017 02:55:32.334356 INFO : Training has run successfully!
1018 02:55:32.334866 Check phy result
1019 02:55:32.339931 INFO : End of initialization
1020 02:55:32.340468 INFO : End of read enable training
1021 02:55:32.345528 INFO : End of fine write leveling
1022 02:55:32.351166 INFO : End of Write leveling coarse delay
1023 02:55:32.351665 INFO : Training has run successfully!
1024 02:55:32.352135 Check phy result
1025 02:55:32.356721 INFO : End of initialization
1026 02:55:32.357218 INFO : End of read dq deskew training
1027 02:55:32.362287 INFO : End of MPR read delay center optimization
1028 02:55:32.367899 INFO : End of write delay center optimization
1029 02:55:32.373643 INFO : End of read delay center optimization
1030 02:55:32.374170 INFO : End of max read latency training
1031 02:55:32.379233 INFO : Training has run successfully!
1032 02:55:32.379770 1D training succeed
1033 02:55:32.387476 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1034 02:55:32.435888 Check phy result
1035 02:55:32.436514 INFO : End of initialization
1036 02:55:32.457691 INFO : End of 2D read delay Voltage center optimization
1037 02:55:32.477944 INFO : End of 2D read delay Voltage center optimization
1038 02:55:32.530017 INFO : End of 2D write delay Voltage center optimization
1039 02:55:32.579427 INFO : End of 2D write delay Voltage center optimization
1040 02:55:32.584929 INFO : Training has run successfully!
1041 02:55:32.585435
1042 02:55:32.585893 channel==0
1043 02:55:32.590520 RxClkDly_Margin_A0==88 ps 9
1044 02:55:32.591037 TxDqDly_Margin_A0==98 ps 10
1045 02:55:32.596121 RxClkDly_Margin_A1==88 ps 9
1046 02:55:32.596620 TxDqDly_Margin_A1==98 ps 10
1047 02:55:32.597076 TrainedVREFDQ_A0==74
1048 02:55:32.601688 TrainedVREFDQ_A1==74
1049 02:55:32.602187 VrefDac_Margin_A0==25
1050 02:55:32.602630 DeviceVref_Margin_A0==40
1051 02:55:32.607360 VrefDac_Margin_A1==23
1052 02:55:32.607855 DeviceVref_Margin_A1==40
1053 02:55:32.608341
1054 02:55:32.608786
1055 02:55:32.612912 channel==1
1056 02:55:32.613407 RxClkDly_Margin_A0==98 ps 10
1057 02:55:32.613848 TxDqDly_Margin_A0==98 ps 10
1058 02:55:32.618521 RxClkDly_Margin_A1==98 ps 10
1059 02:55:32.619024 TxDqDly_Margin_A1==88 ps 9
1060 02:55:32.624113 TrainedVREFDQ_A0==77
1061 02:55:32.624613 TrainedVREFDQ_A1==77
1062 02:55:32.625057 VrefDac_Margin_A0==22
1063 02:55:32.629710 DeviceVref_Margin_A0==37
1064 02:55:32.630207 VrefDac_Margin_A1==24
1065 02:55:32.635349 DeviceVref_Margin_A1==37
1066 02:55:32.635842
1067 02:55:32.636332 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1068 02:55:32.640898
1069 02:55:32.668879 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1070 02:55:32.669437 2D training succeed
1071 02:55:32.674515 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1072 02:55:32.680131 auto size-- 65535DDR cs0 size: 2048MB
1073 02:55:32.680630 DDR cs1 size: 2048MB
1074 02:55:32.685729 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1075 02:55:32.686232 cs0 DataBus test pass
1076 02:55:32.691364 cs1 DataBus test pass
1077 02:55:32.691858 cs0 AddrBus test pass
1078 02:55:32.692358 cs1 AddrBus test pass
1079 02:55:32.692797
1080 02:55:32.696926 100bdlr_step_size ps== 420
1081 02:55:32.697440 result report
1082 02:55:32.702481 boot times 0Enable ddr reg access
1083 02:55:32.707941 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1084 02:55:32.721412 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1085 02:55:33.295050 0.0;M3 CHK:0;cm4_sp_mode 0
1086 02:55:33.295701 MVN_1=0x00000000
1087 02:55:33.300629 MVN_2=0x00000000
1088 02:55:33.306325 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1089 02:55:33.306839 OPS=0x10
1090 02:55:33.307293 ring efuse init
1091 02:55:33.307732 chipver efuse init
1092 02:55:33.311920 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1093 02:55:33.317524 [0.018961 Inits done]
1094 02:55:33.318034 secure task start!
1095 02:55:33.318488 high task start!
1096 02:55:33.322103 low task start!
1097 02:55:33.322603 run into bl31
1098 02:55:33.328794 NOTICE: BL31: v1.3(release):4fc40b1
1099 02:55:33.336600 NOTICE: BL31: Built : 15:58:17, May 22 2019
1100 02:55:33.337131 NOTICE: BL31: G12A normal boot!
1101 02:55:33.361941 NOTICE: BL31: BL33 decompress pass
1102 02:55:33.367601 ERROR: Error initializing runtime service opteed_fast
1103 02:55:34.600362
1104 02:55:34.601020
1105 02:55:34.607937 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1106 02:55:34.608493
1107 02:55:34.608950 Model: Libre Computer AML-A311D-CC Alta
1108 02:55:34.817194 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1109 02:55:34.839622 DRAM: 2 GiB (effective 3.8 GiB)
1110 02:55:34.983531 Core: 408 devices, 31 uclasses, devicetree: separate
1111 02:55:34.989522 WDT: Not starting watchdog@f0d0
1112 02:55:35.021770 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1113 02:55:35.034189 Loading Environment from FAT... Card did not respond to voltage select! : -110
1114 02:55:35.039225 ** Bad device specification mmc 0 **
1115 02:55:35.049529 Card did not respond to voltage select! : -110
1116 02:55:35.057182 ** Bad device specification mmc 0 **
1117 02:55:35.057691 Couldn't find partition mmc 0
1118 02:55:35.065514 Card did not respond to voltage select! : -110
1119 02:55:35.071033 ** Bad device specification mmc 0 **
1120 02:55:35.071538 Couldn't find partition mmc 0
1121 02:55:35.076099 Error: could not access storage.
1122 02:55:35.418530 Net: eth0: ethernet@ff3f0000
1123 02:55:35.419328 starting USB...
1124 02:55:35.670247 Bus usb@ff500000: Register 3000140 NbrPorts 3
1125 02:55:35.670969 Starting the controller
1126 02:55:35.676243 USB XHCI 1.10
1127 02:55:37.231466 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1128 02:55:37.239790 scanning usb for storage devices... 0 Storage Device(s) found
1130 02:55:37.291802 Hit any key to stop autoboot: 1
1131 02:55:37.292930 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1132 02:55:37.293740 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1133 02:55:37.294369 Setting prompt string to ['=>']
1134 02:55:37.294992 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1135 02:55:37.307286 0
1136 02:55:37.308390 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1137 02:55:37.309024 Sending with 10 millisecond of delay
1139 02:55:38.444477 => setenv autoload no
1140 02:55:38.455513 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1141 02:55:38.461734 setenv autoload no
1142 02:55:38.462619 Sending with 10 millisecond of delay
1144 02:55:40.260153 => setenv initrd_high 0xffffffff
1145 02:55:40.271138 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1146 02:55:40.272265 setenv initrd_high 0xffffffff
1147 02:55:40.273154 Sending with 10 millisecond of delay
1149 02:55:41.890016 => setenv fdt_high 0xffffffff
1150 02:55:41.901016 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1151 02:55:41.902053 setenv fdt_high 0xffffffff
1152 02:55:41.902926 Sending with 10 millisecond of delay
1154 02:55:42.195114 => dhcp
1155 02:55:42.206070 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1156 02:55:42.207095 dhcp
1157 02:55:42.207656 Speed: 1000, full duplex
1158 02:55:42.208247 BOOTP broadcast 1
1159 02:55:42.415946 DHCP client bound to address 192.168.6.27 (209 ms)
1160 02:55:42.416948 Sending with 10 millisecond of delay
1162 02:55:44.095950 => setenv serverip 192.168.6.2
1163 02:55:44.106761 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1164 02:55:44.107459 setenv serverip 192.168.6.2
1165 02:55:44.108088 Sending with 10 millisecond of delay
1167 02:55:47.832689 => tftpboot 0x01080000 957003/tftp-deploy-dz74c194/kernel/uImage
1168 02:55:47.843537 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1169 02:55:47.844498 tftpboot 0x01080000 957003/tftp-deploy-dz74c194/kernel/uImage
1170 02:55:47.844978 Speed: 1000, full duplex
1171 02:55:47.845417 Using ethernet@ff3f0000 device
1172 02:55:47.846838 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1173 02:55:47.851821 Filename '957003/tftp-deploy-dz74c194/kernel/uImage'.
1174 02:55:47.855898 Load address: 0x1080000
1175 02:55:50.417773 Loading: *################################################## 36.1 MiB
1176 02:55:50.418448 14.1 MiB/s
1177 02:55:50.418902 done
1178 02:55:50.422193 Bytes transferred = 37880384 (2420240 hex)
1179 02:55:50.423002 Sending with 10 millisecond of delay
1181 02:55:55.111504 => tftpboot 0x08000000 957003/tftp-deploy-dz74c194/ramdisk/ramdisk.cpio.gz.uboot
1182 02:55:55.122478 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1183 02:55:55.123504 tftpboot 0x08000000 957003/tftp-deploy-dz74c194/ramdisk/ramdisk.cpio.gz.uboot
1184 02:55:55.123975 Speed: 1000, full duplex
1185 02:55:55.124474 Using ethernet@ff3f0000 device
1186 02:55:55.125442 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1187 02:55:55.137309 Filename '957003/tftp-deploy-dz74c194/ramdisk/ramdisk.cpio.gz.uboot'.
1188 02:55:55.137944 Load address: 0x8000000
1189 02:56:02.077996 Loading: *#############################T #################### UDP wrong checksum 00000005 000002b4
1190 02:56:07.078414 T UDP wrong checksum 00000005 000002b4
1191 02:56:17.081075 T UDP wrong checksum 00000005 000002b4
1192 02:56:30.448654 T T T UDP wrong checksum 000000ff 00005eed
1193 02:56:30.488476 UDP wrong checksum 000000ff 0000f8df
1194 02:56:37.086263 T T UDP wrong checksum 00000005 000002b4
1195 02:56:52.090542 T T
1196 02:56:52.090954 Retry count exceeded; starting again
1198 02:56:52.091813 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1201 02:56:52.092800 end: 2.4 uboot-commands (duration 00:01:52) [common]
1203 02:56:52.093505 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1205 02:56:52.094056 end: 2 uboot-action (duration 00:01:52) [common]
1207 02:56:52.094882 Cleaning after the job
1208 02:56:52.095221 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/ramdisk
1209 02:56:52.096082 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/kernel
1210 02:56:52.117528 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/dtb
1211 02:56:52.118275 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/nfsrootfs
1212 02:56:52.296620 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957003/tftp-deploy-dz74c194/modules
1213 02:56:52.320587 start: 4.1 power-off (timeout 00:00:30) [common]
1214 02:56:52.321267 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1215 02:56:52.354732 >> OK - accepted request
1216 02:56:52.356785 Returned 0 in 0 seconds
1217 02:56:52.457559 end: 4.1 power-off (duration 00:00:00) [common]
1219 02:56:52.458551 start: 4.2 read-feedback (timeout 00:10:00) [common]
1220 02:56:52.459196 Listened to connection for namespace 'common' for up to 1s
1221 02:56:53.460186 Finalising connection for namespace 'common'
1222 02:56:53.460681 Disconnecting from shell: Finalise
1223 02:56:53.460981 =>
1224 02:56:53.561724 end: 4.2 read-feedback (duration 00:00:01) [common]
1225 02:56:53.562206 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/957003
1226 02:56:56.471616 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/957003
1227 02:56:56.472386 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.