Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:39:41.471354 lava-dispatcher, installed at version: 2024.01
2 02:39:41.472197 start: 0 validate
3 02:39:41.472725 Start time: 2024-11-08 02:39:41.472693+00:00 (UTC)
4 02:39:41.473274 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:39:41.473827 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:39:41.512815 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:39:41.513382 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 02:39:41.548678 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:39:41.549318 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:39:41.586419 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:39:41.586947 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:39:41.617210 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:39:41.617931 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
14 02:39:41.658230 validate duration: 0.19
16 02:39:41.659514 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:39:41.660069 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:39:41.660626 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:39:41.661554 Not decompressing ramdisk as can be used compressed.
20 02:39:41.662278 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 02:39:41.662777 saving as /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/ramdisk/initrd.cpio.gz
22 02:39:41.663223 total size: 5628169 (5 MB)
23 02:39:41.701444 progress 0 % (0 MB)
24 02:39:41.707167 progress 5 % (0 MB)
25 02:39:41.713359 progress 10 % (0 MB)
26 02:39:41.718405 progress 15 % (0 MB)
27 02:39:41.723886 progress 20 % (1 MB)
28 02:39:41.729049 progress 25 % (1 MB)
29 02:39:41.734503 progress 30 % (1 MB)
30 02:39:41.740171 progress 35 % (1 MB)
31 02:39:41.745136 progress 40 % (2 MB)
32 02:39:41.750643 progress 45 % (2 MB)
33 02:39:41.755563 progress 50 % (2 MB)
34 02:39:41.760958 progress 55 % (2 MB)
35 02:39:41.766523 progress 60 % (3 MB)
36 02:39:41.771517 progress 65 % (3 MB)
37 02:39:41.777079 progress 70 % (3 MB)
38 02:39:41.782016 progress 75 % (4 MB)
39 02:39:41.787440 progress 80 % (4 MB)
40 02:39:41.792515 progress 85 % (4 MB)
41 02:39:41.797658 progress 90 % (4 MB)
42 02:39:41.802594 progress 95 % (5 MB)
43 02:39:41.807142 progress 100 % (5 MB)
44 02:39:41.808088 5 MB downloaded in 0.14 s (37.06 MB/s)
45 02:39:41.808898 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:39:41.810307 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:39:41.810785 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:39:41.811234 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:39:41.811920 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/clang-16/kernel/Image
51 02:39:41.812341 saving as /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/kernel/Image
52 02:39:41.812665 total size: 37880320 (36 MB)
53 02:39:41.813005 No compression specified
54 02:39:41.848791 progress 0 % (0 MB)
55 02:39:41.880526 progress 5 % (1 MB)
56 02:39:41.912989 progress 10 % (3 MB)
57 02:39:41.944837 progress 15 % (5 MB)
58 02:39:41.976811 progress 20 % (7 MB)
59 02:39:42.008324 progress 25 % (9 MB)
60 02:39:42.039319 progress 30 % (10 MB)
61 02:39:42.070722 progress 35 % (12 MB)
62 02:39:42.102040 progress 40 % (14 MB)
63 02:39:42.133485 progress 45 % (16 MB)
64 02:39:42.165647 progress 50 % (18 MB)
65 02:39:42.196630 progress 55 % (19 MB)
66 02:39:42.227956 progress 60 % (21 MB)
67 02:39:42.259368 progress 65 % (23 MB)
68 02:39:42.290853 progress 70 % (25 MB)
69 02:39:42.322348 progress 75 % (27 MB)
70 02:39:42.353255 progress 80 % (28 MB)
71 02:39:42.384645 progress 85 % (30 MB)
72 02:39:42.416299 progress 90 % (32 MB)
73 02:39:42.448078 progress 95 % (34 MB)
74 02:39:42.478201 progress 100 % (36 MB)
75 02:39:42.478907 36 MB downloaded in 0.67 s (54.22 MB/s)
76 02:39:42.479627 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:39:42.480904 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:39:42.481348 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:39:42.481755 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:39:42.482458 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 02:39:42.482845 saving as /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/dtb/meson-g12b-a311d-libretech-cc.dtb
83 02:39:42.483183 total size: 54703 (0 MB)
84 02:39:42.483497 No compression specified
85 02:39:42.527381 progress 59 % (0 MB)
86 02:39:42.529012 progress 100 % (0 MB)
87 02:39:42.530193 0 MB downloaded in 0.05 s (1.11 MB/s)
88 02:39:42.531109 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:39:42.532485 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:39:42.532761 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:39:42.533028 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:39:42.533514 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 02:39:42.533762 saving as /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/nfsrootfs/full.rootfs.tar
95 02:39:42.533968 total size: 120894716 (115 MB)
96 02:39:42.534175 Using unxz to decompress xz
97 02:39:42.565849 progress 0 % (0 MB)
98 02:39:43.358939 progress 5 % (5 MB)
99 02:39:44.196505 progress 10 % (11 MB)
100 02:39:45.001524 progress 15 % (17 MB)
101 02:39:45.739073 progress 20 % (23 MB)
102 02:39:46.337193 progress 25 % (28 MB)
103 02:39:47.164584 progress 30 % (34 MB)
104 02:39:47.960119 progress 35 % (40 MB)
105 02:39:48.314223 progress 40 % (46 MB)
106 02:39:48.685579 progress 45 % (51 MB)
107 02:39:49.406041 progress 50 % (57 MB)
108 02:39:50.291003 progress 55 % (63 MB)
109 02:39:51.073455 progress 60 % (69 MB)
110 02:39:51.885127 progress 65 % (74 MB)
111 02:39:52.723742 progress 70 % (80 MB)
112 02:39:53.581725 progress 75 % (86 MB)
113 02:39:54.365786 progress 80 % (92 MB)
114 02:39:55.144696 progress 85 % (98 MB)
115 02:39:56.057199 progress 90 % (103 MB)
116 02:39:56.862938 progress 95 % (109 MB)
117 02:39:57.693848 progress 100 % (115 MB)
118 02:39:57.706289 115 MB downloaded in 15.17 s (7.60 MB/s)
119 02:39:57.706870 end: 1.4.1 http-download (duration 00:00:15) [common]
121 02:39:57.707686 end: 1.4 download-retry (duration 00:00:15) [common]
122 02:39:57.707953 start: 1.5 download-retry (timeout 00:09:44) [common]
123 02:39:57.708480 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 02:39:57.709704 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/clang-16/modules.tar.xz
125 02:39:57.710223 saving as /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/modules/modules.tar
126 02:39:57.710636 total size: 11768564 (11 MB)
127 02:39:57.711061 Using unxz to decompress xz
128 02:39:57.754914 progress 0 % (0 MB)
129 02:39:57.821727 progress 5 % (0 MB)
130 02:39:57.896289 progress 10 % (1 MB)
131 02:39:57.991112 progress 15 % (1 MB)
132 02:39:58.087046 progress 20 % (2 MB)
133 02:39:58.165834 progress 25 % (2 MB)
134 02:39:58.242348 progress 30 % (3 MB)
135 02:39:58.321917 progress 35 % (3 MB)
136 02:39:58.402697 progress 40 % (4 MB)
137 02:39:58.478478 progress 45 % (5 MB)
138 02:39:58.563889 progress 50 % (5 MB)
139 02:39:58.646975 progress 55 % (6 MB)
140 02:39:58.731760 progress 60 % (6 MB)
141 02:39:58.812691 progress 65 % (7 MB)
142 02:39:58.894334 progress 70 % (7 MB)
143 02:39:58.977055 progress 75 % (8 MB)
144 02:39:59.060800 progress 80 % (9 MB)
145 02:39:59.144159 progress 85 % (9 MB)
146 02:39:59.228197 progress 90 % (10 MB)
147 02:39:59.306859 progress 95 % (10 MB)
148 02:39:59.385422 progress 100 % (11 MB)
149 02:39:59.395972 11 MB downloaded in 1.69 s (6.66 MB/s)
150 02:39:59.396948 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:39:59.398544 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:39:59.399064 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 02:39:59.399580 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 02:40:15.464371 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/956964/extract-nfsrootfs-dvbg48ty
156 02:40:15.464978 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 02:40:15.465262 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 02:40:15.465991 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif
159 02:40:15.466434 makedir: /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin
160 02:40:15.466800 makedir: /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/tests
161 02:40:15.467127 makedir: /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/results
162 02:40:15.467461 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-add-keys
163 02:40:15.468041 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-add-sources
164 02:40:15.468560 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-background-process-start
165 02:40:15.469045 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-background-process-stop
166 02:40:15.469562 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-common-functions
167 02:40:15.470093 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-echo-ipv4
168 02:40:15.470595 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-install-packages
169 02:40:15.471067 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-installed-packages
170 02:40:15.471531 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-os-build
171 02:40:15.472023 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-probe-channel
172 02:40:15.472503 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-probe-ip
173 02:40:15.472968 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-target-ip
174 02:40:15.473427 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-target-mac
175 02:40:15.473888 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-target-storage
176 02:40:15.474355 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-test-case
177 02:40:15.474824 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-test-event
178 02:40:15.475282 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-test-feedback
179 02:40:15.475743 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-test-raise
180 02:40:15.476265 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-test-reference
181 02:40:15.476772 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-test-runner
182 02:40:15.477277 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-test-set
183 02:40:15.477749 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-test-shell
184 02:40:15.478225 Updating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-add-keys (debian)
185 02:40:15.478733 Updating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-add-sources (debian)
186 02:40:15.479222 Updating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-install-packages (debian)
187 02:40:15.479722 Updating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-installed-packages (debian)
188 02:40:15.480244 Updating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/bin/lava-os-build (debian)
189 02:40:15.480676 Creating /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/environment
190 02:40:15.481043 LAVA metadata
191 02:40:15.481297 - LAVA_JOB_ID=956964
192 02:40:15.481508 - LAVA_DISPATCHER_IP=192.168.6.2
193 02:40:15.481857 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 02:40:15.482779 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 02:40:15.483081 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 02:40:15.483285 skipped lava-vland-overlay
197 02:40:15.483522 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 02:40:15.483774 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 02:40:15.484011 skipped lava-multinode-overlay
200 02:40:15.484257 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 02:40:15.484510 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 02:40:15.484753 Loading test definitions
203 02:40:15.485024 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 02:40:15.485239 Using /lava-956964 at stage 0
205 02:40:15.486315 uuid=956964_1.6.2.4.1 testdef=None
206 02:40:15.486623 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 02:40:15.486883 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 02:40:15.488463 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 02:40:15.489242 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 02:40:15.491122 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 02:40:15.491924 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 02:40:15.493760 runner path: /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/0/tests/0_timesync-off test_uuid 956964_1.6.2.4.1
215 02:40:15.494287 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 02:40:15.495082 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 02:40:15.495303 Using /lava-956964 at stage 0
219 02:40:15.495647 Fetching tests from https://github.com/kernelci/test-definitions.git
220 02:40:15.495935 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/0/tests/1_kselftest-rtc'
221 02:40:19.077351 Running '/usr/bin/git checkout kernelci.org
222 02:40:19.203906 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 02:40:19.205370 uuid=956964_1.6.2.4.5 testdef=None
224 02:40:19.205717 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 02:40:19.206460 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 02:40:19.209315 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 02:40:19.210126 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 02:40:19.213815 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 02:40:19.214660 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 02:40:19.218227 runner path: /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/0/tests/1_kselftest-rtc test_uuid 956964_1.6.2.4.5
234 02:40:19.218509 BOARD='meson-g12b-a311d-libretech-cc'
235 02:40:19.218713 BRANCH='mainline'
236 02:40:19.218910 SKIPFILE='/dev/null'
237 02:40:19.219104 SKIP_INSTALL='True'
238 02:40:19.219296 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/clang-16/kselftest.tar.xz'
239 02:40:19.219493 TST_CASENAME=''
240 02:40:19.219686 TST_CMDFILES='rtc'
241 02:40:19.220242 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 02:40:19.221029 Creating lava-test-runner.conf files
244 02:40:19.221233 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/956964/lava-overlay-q4c9taif/lava-956964/0 for stage 0
245 02:40:19.221572 - 0_timesync-off
246 02:40:19.221807 - 1_kselftest-rtc
247 02:40:19.222132 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 02:40:19.222430 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 02:40:42.736858 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 02:40:42.737300 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 02:40:42.737598 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 02:40:42.737907 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 02:40:42.738197 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 02:40:43.351163 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 02:40:43.351605 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 02:40:43.351856 extracting modules file /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956964/extract-nfsrootfs-dvbg48ty
257 02:40:44.926414 extracting modules file /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956964/extract-overlay-ramdisk-9z9ly2ck/ramdisk
258 02:40:46.331389 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 02:40:46.331877 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 02:40:46.332196 [common] Applying overlay to NFS
261 02:40:46.332428 [common] Applying overlay /var/lib/lava/dispatcher/tmp/956964/compress-overlay-0teojkxj/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/956964/extract-nfsrootfs-dvbg48ty
262 02:40:49.059922 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 02:40:49.060428 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 02:40:49.060737 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 02:40:49.061003 Converting downloaded kernel to a uImage
266 02:40:49.061329 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/kernel/Image /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/kernel/uImage
267 02:40:49.440764 output: Image Name:
268 02:40:49.441195 output: Created: Fri Nov 8 02:40:49 2024
269 02:40:49.441405 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 02:40:49.441610 output: Data Size: 37880320 Bytes = 36992.50 KiB = 36.13 MiB
271 02:40:49.441812 output: Load Address: 01080000
272 02:40:49.442012 output: Entry Point: 01080000
273 02:40:49.442210 output:
274 02:40:49.442541 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 02:40:49.442805 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 02:40:49.443075 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 02:40:49.443366 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 02:40:49.443655 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 02:40:49.443917 Building ramdisk /var/lib/lava/dispatcher/tmp/956964/extract-overlay-ramdisk-9z9ly2ck/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/956964/extract-overlay-ramdisk-9z9ly2ck/ramdisk
280 02:40:51.677628 >> 173443 blocks
281 02:40:59.364287 Adding RAMdisk u-boot header.
282 02:40:59.365002 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/956964/extract-overlay-ramdisk-9z9ly2ck/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/956964/extract-overlay-ramdisk-9z9ly2ck/ramdisk.cpio.gz.uboot
283 02:40:59.622810 output: Image Name:
284 02:40:59.623439 output: Created: Fri Nov 8 02:40:59 2024
285 02:40:59.623941 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 02:40:59.624466 output: Data Size: 24148121 Bytes = 23582.15 KiB = 23.03 MiB
287 02:40:59.624884 output: Load Address: 00000000
288 02:40:59.625279 output: Entry Point: 00000000
289 02:40:59.625673 output:
290 02:40:59.626829 rename /var/lib/lava/dispatcher/tmp/956964/extract-overlay-ramdisk-9z9ly2ck/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/ramdisk/ramdisk.cpio.gz.uboot
291 02:40:59.627670 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 02:40:59.628349 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 02:40:59.628983 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 02:40:59.629481 No LXC device requested
295 02:40:59.630076 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 02:40:59.630686 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 02:40:59.631237 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 02:40:59.631743 Checking files for TFTP limit of 4294967296 bytes.
299 02:40:59.634820 end: 1 tftp-deploy (duration 00:01:18) [common]
300 02:40:59.635486 start: 2 uboot-action (timeout 00:05:00) [common]
301 02:40:59.636130 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 02:40:59.636733 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 02:40:59.637330 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 02:40:59.637909 Using kernel file from prepare-kernel: 956964/tftp-deploy-7qxfifjj/kernel/uImage
305 02:40:59.638672 substitutions:
306 02:40:59.639136 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 02:40:59.639543 - {DTB_ADDR}: 0x01070000
308 02:40:59.639940 - {DTB}: 956964/tftp-deploy-7qxfifjj/dtb/meson-g12b-a311d-libretech-cc.dtb
309 02:40:59.640372 - {INITRD}: 956964/tftp-deploy-7qxfifjj/ramdisk/ramdisk.cpio.gz.uboot
310 02:40:59.640771 - {KERNEL_ADDR}: 0x01080000
311 02:40:59.641163 - {KERNEL}: 956964/tftp-deploy-7qxfifjj/kernel/uImage
312 02:40:59.641617 - {LAVA_MAC}: None
313 02:40:59.642052 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/956964/extract-nfsrootfs-dvbg48ty
314 02:40:59.642448 - {NFS_SERVER_IP}: 192.168.6.2
315 02:40:59.642838 - {PRESEED_CONFIG}: None
316 02:40:59.643228 - {PRESEED_LOCAL}: None
317 02:40:59.643617 - {RAMDISK_ADDR}: 0x08000000
318 02:40:59.644030 - {RAMDISK}: 956964/tftp-deploy-7qxfifjj/ramdisk/ramdisk.cpio.gz.uboot
319 02:40:59.644464 - {ROOT_PART}: None
320 02:40:59.644862 - {ROOT}: None
321 02:40:59.645249 - {SERVER_IP}: 192.168.6.2
322 02:40:59.645631 - {TEE_ADDR}: 0x83000000
323 02:40:59.646012 - {TEE}: None
324 02:40:59.646395 Parsed boot commands:
325 02:40:59.646766 - setenv autoload no
326 02:40:59.647146 - setenv initrd_high 0xffffffff
327 02:40:59.647528 - setenv fdt_high 0xffffffff
328 02:40:59.647953 - dhcp
329 02:40:59.648236 - setenv serverip 192.168.6.2
330 02:40:59.648434 - tftpboot 0x01080000 956964/tftp-deploy-7qxfifjj/kernel/uImage
331 02:40:59.648632 - tftpboot 0x08000000 956964/tftp-deploy-7qxfifjj/ramdisk/ramdisk.cpio.gz.uboot
332 02:40:59.648829 - tftpboot 0x01070000 956964/tftp-deploy-7qxfifjj/dtb/meson-g12b-a311d-libretech-cc.dtb
333 02:40:59.649033 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/956964/extract-nfsrootfs-dvbg48ty,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 02:40:59.649236 - bootm 0x01080000 0x08000000 0x01070000
335 02:40:59.649490 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 02:40:59.650244 start: 2.3 connect-device (timeout 00:05:00) [common]
338 02:40:59.650456 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 02:40:59.663352 Setting prompt string to ['lava-test: # ']
340 02:40:59.665020 end: 2.3 connect-device (duration 00:00:00) [common]
341 02:40:59.665639 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 02:40:59.666195 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 02:40:59.666720 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 02:40:59.667915 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 02:40:59.703084 >> OK - accepted request
346 02:40:59.705245 Returned 0 in 0 seconds
347 02:40:59.806475 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 02:40:59.808368 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 02:40:59.809096 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 02:40:59.809722 Setting prompt string to ['Hit any key to stop autoboot']
352 02:40:59.810280 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 02:40:59.812123 Trying 192.168.56.21...
354 02:40:59.812709 Connected to conserv1.
355 02:40:59.813185 Escape character is '^]'.
356 02:40:59.813684
357 02:40:59.814108 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 02:40:59.814587
359 02:41:11.361847 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 02:41:11.362533 bl2_stage_init 0x01
361 02:41:11.363059 bl2_stage_init 0x81
362 02:41:11.367289 hw id: 0x0000 - pwm id 0x01
363 02:41:11.367800 bl2_stage_init 0xc1
364 02:41:11.368258 bl2_stage_init 0x02
365 02:41:11.368667
366 02:41:11.373071 L0:00000000
367 02:41:11.373651 L1:20000703
368 02:41:11.374116 L2:00008067
369 02:41:11.374564 L3:14000000
370 02:41:11.375782 B2:00402000
371 02:41:11.376320 B1:e0f83180
372 02:41:11.376776
373 02:41:11.377211 TE: 58124
374 02:41:11.377644
375 02:41:11.387007 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 02:41:11.387511
377 02:41:11.387951 Board ID = 1
378 02:41:11.388426 Set A53 clk to 24M
379 02:41:11.388854 Set A73 clk to 24M
380 02:41:11.392592 Set clk81 to 24M
381 02:41:11.393069 A53 clk: 1200 MHz
382 02:41:11.393502 A73 clk: 1200 MHz
383 02:41:11.395966 CLK81: 166.6M
384 02:41:11.396476 smccc: 00012a92
385 02:41:11.401418 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 02:41:11.407016 board id: 1
387 02:41:11.411396 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 02:41:11.422989 fw parse done
389 02:41:11.428163 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 02:41:11.470652 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 02:41:11.482708 PIEI prepare done
392 02:41:11.483176 fastboot data load
393 02:41:11.483612 fastboot data verify
394 02:41:11.488180 verify result: 266
395 02:41:11.493827 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 02:41:11.494301 LPDDR4 probe
397 02:41:11.494741 ddr clk to 1584MHz
398 02:41:11.500780 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 02:41:11.538078
400 02:41:11.538613 dmc_version 0001
401 02:41:11.544681 Check phy result
402 02:41:11.551540 INFO : End of CA training
403 02:41:11.552047 INFO : End of initialization
404 02:41:11.557132 INFO : Training has run successfully!
405 02:41:11.557606 Check phy result
406 02:41:11.562726 INFO : End of initialization
407 02:41:11.563202 INFO : End of read enable training
408 02:41:11.566119 INFO : End of fine write leveling
409 02:41:11.571634 INFO : End of Write leveling coarse delay
410 02:41:11.577272 INFO : Training has run successfully!
411 02:41:11.577753 Check phy result
412 02:41:11.578192 INFO : End of initialization
413 02:41:11.582827 INFO : End of read dq deskew training
414 02:41:11.586269 INFO : End of MPR read delay center optimization
415 02:41:11.591796 INFO : End of write delay center optimization
416 02:41:11.597364 INFO : End of read delay center optimization
417 02:41:11.597860 INFO : End of max read latency training
418 02:41:11.603062 INFO : Training has run successfully!
419 02:41:11.603546 1D training succeed
420 02:41:11.610208 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 02:41:11.657780 Check phy result
422 02:41:11.658257 INFO : End of initialization
423 02:41:11.680363 INFO : End of 2D read delay Voltage center optimization
424 02:41:11.700614 INFO : End of 2D read delay Voltage center optimization
425 02:41:11.752642 INFO : End of 2D write delay Voltage center optimization
426 02:41:11.802909 INFO : End of 2D write delay Voltage center optimization
427 02:41:11.808445 INFO : Training has run successfully!
428 02:41:11.808919
429 02:41:11.809363 channel==0
430 02:41:11.814086 RxClkDly_Margin_A0==88 ps 9
431 02:41:11.814555 TxDqDly_Margin_A0==98 ps 10
432 02:41:11.817379 RxClkDly_Margin_A1==88 ps 9
433 02:41:11.817844 TxDqDly_Margin_A1==98 ps 10
434 02:41:11.822921 TrainedVREFDQ_A0==74
435 02:41:11.823394 TrainedVREFDQ_A1==74
436 02:41:11.828501 VrefDac_Margin_A0==24
437 02:41:11.828969 DeviceVref_Margin_A0==40
438 02:41:11.829404 VrefDac_Margin_A1==25
439 02:41:11.834093 DeviceVref_Margin_A1==40
440 02:41:11.834553
441 02:41:11.834992
442 02:41:11.835428 channel==1
443 02:41:11.835855 RxClkDly_Margin_A0==98 ps 10
444 02:41:11.837506 TxDqDly_Margin_A0==98 ps 10
445 02:41:11.843086 RxClkDly_Margin_A1==98 ps 10
446 02:41:11.843570 TxDqDly_Margin_A1==98 ps 10
447 02:41:11.848627 TrainedVREFDQ_A0==77
448 02:41:11.849107 TrainedVREFDQ_A1==78
449 02:41:11.849545 VrefDac_Margin_A0==22
450 02:41:11.854267 DeviceVref_Margin_A0==37
451 02:41:11.854736 VrefDac_Margin_A1==24
452 02:41:11.855171 DeviceVref_Margin_A1==36
453 02:41:11.855598
454 02:41:11.863150 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 02:41:11.863628
456 02:41:11.894476 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 02:41:11.895016 2D training succeed
458 02:41:11.897856 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 02:41:11.903296 auto size-- 65535DDR cs0 size: 2048MB
460 02:41:11.903786 DDR cs1 size: 2048MB
461 02:41:11.908922 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 02:41:11.909394 cs0 DataBus test pass
463 02:41:11.914606 cs1 DataBus test pass
464 02:41:11.915075 cs0 AddrBus test pass
465 02:41:11.915512 cs1 AddrBus test pass
466 02:41:11.915941
467 02:41:11.918046 100bdlr_step_size ps== 420
468 02:41:11.923525 result report
469 02:41:11.924027 boot times 0Enable ddr reg access
470 02:41:11.930677 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 02:41:11.944201 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 02:41:12.518807 0.0;M3 CHK:0;cm4_sp_mode 0
473 02:41:12.519358 MVN_1=0x00000000
474 02:41:12.524341 MVN_2=0x00000000
475 02:41:12.530253 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 02:41:12.530736 OPS=0x10
477 02:41:12.531181 ring efuse init
478 02:41:12.531614 chipver efuse init
479 02:41:12.535609 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 02:41:12.541341 [0.018961 Inits done]
481 02:41:12.541815 secure task start!
482 02:41:12.542248 high task start!
483 02:41:12.544995 low task start!
484 02:41:12.545475 run into bl31
485 02:41:12.552575 NOTICE: BL31: v1.3(release):4fc40b1
486 02:41:12.559335 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 02:41:12.559815 NOTICE: BL31: G12A normal boot!
488 02:41:12.585770 NOTICE: BL31: BL33 decompress pass
489 02:41:12.590484 ERROR: Error initializing runtime service opteed_fast
490 02:41:13.824419
491 02:41:13.825063
492 02:41:13.831784 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 02:41:13.832315
494 02:41:13.832757 Model: Libre Computer AML-A311D-CC Alta
495 02:41:14.041224 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 02:41:14.064443 DRAM: 2 GiB (effective 3.8 GiB)
497 02:41:14.207481 Core: 408 devices, 31 uclasses, devicetree: separate
498 02:41:14.213279 WDT: Not starting watchdog@f0d0
499 02:41:14.245519 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 02:41:14.257990 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 02:41:14.262971 ** Bad device specification mmc 0 **
502 02:41:14.273383 Card did not respond to voltage select! : -110
503 02:41:14.280964 ** Bad device specification mmc 0 **
504 02:41:14.281430 Couldn't find partition mmc 0
505 02:41:14.289434 Card did not respond to voltage select! : -110
506 02:41:14.294803 ** Bad device specification mmc 0 **
507 02:41:14.295275 Couldn't find partition mmc 0
508 02:41:14.299868 Error: could not access storage.
509 02:41:15.562880 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 02:41:15.563525 bl2_stage_init 0x01
511 02:41:15.564091 bl2_stage_init 0x81
512 02:41:15.568412 hw id: 0x0000 - pwm id 0x01
513 02:41:15.568912 bl2_stage_init 0xc1
514 02:41:15.569372 bl2_stage_init 0x02
515 02:41:15.569821
516 02:41:15.574018 L0:00000000
517 02:41:15.574499 L1:20000703
518 02:41:15.574943 L2:00008067
519 02:41:15.575382 L3:14000000
520 02:41:15.579619 B2:00402000
521 02:41:15.580131 B1:e0f83180
522 02:41:15.580581
523 02:41:15.581025 TE: 58124
524 02:41:15.581463
525 02:41:15.585221 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 02:41:15.585701
527 02:41:15.586151 Board ID = 1
528 02:41:15.590830 Set A53 clk to 24M
529 02:41:15.591301 Set A73 clk to 24M
530 02:41:15.591748 Set clk81 to 24M
531 02:41:15.596424 A53 clk: 1200 MHz
532 02:41:15.596897 A73 clk: 1200 MHz
533 02:41:15.597341 CLK81: 166.6M
534 02:41:15.597779 smccc: 00012a92
535 02:41:15.601993 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 02:41:15.607611 board id: 1
537 02:41:15.612553 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 02:41:15.624168 fw parse done
539 02:41:15.630141 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 02:41:15.672191 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 02:41:15.683643 PIEI prepare done
542 02:41:15.684165 fastboot data load
543 02:41:15.684627 fastboot data verify
544 02:41:15.689311 verify result: 266
545 02:41:15.695043 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 02:41:15.695517 LPDDR4 probe
547 02:41:15.695967 ddr clk to 1584MHz
548 02:41:15.702376 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 02:41:15.740207
550 02:41:15.740708 dmc_version 0001
551 02:41:15.746810 Check phy result
552 02:41:15.752699 INFO : End of CA training
553 02:41:15.753172 INFO : End of initialization
554 02:41:15.758306 INFO : Training has run successfully!
555 02:41:15.758784 Check phy result
556 02:41:15.763918 INFO : End of initialization
557 02:41:15.764428 INFO : End of read enable training
558 02:41:15.769504 INFO : End of fine write leveling
559 02:41:15.775088 INFO : End of Write leveling coarse delay
560 02:41:15.775566 INFO : Training has run successfully!
561 02:41:15.776043 Check phy result
562 02:41:15.780719 INFO : End of initialization
563 02:41:15.781202 INFO : End of read dq deskew training
564 02:41:15.786347 INFO : End of MPR read delay center optimization
565 02:41:15.791973 INFO : End of write delay center optimization
566 02:41:15.797511 INFO : End of read delay center optimization
567 02:41:15.798016 INFO : End of max read latency training
568 02:41:15.803097 INFO : Training has run successfully!
569 02:41:15.803591 1D training succeed
570 02:41:15.812013 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 02:41:15.859888 Check phy result
572 02:41:15.860441 INFO : End of initialization
573 02:41:15.881508 INFO : End of 2D read delay Voltage center optimization
574 02:41:15.900639 INFO : End of 2D read delay Voltage center optimization
575 02:41:15.953599 INFO : End of 2D write delay Voltage center optimization
576 02:41:16.002844 INFO : End of 2D write delay Voltage center optimization
577 02:41:16.008401 INFO : Training has run successfully!
578 02:41:16.008965
579 02:41:16.009441 channel==0
580 02:41:16.013987 RxClkDly_Margin_A0==88 ps 9
581 02:41:16.014521 TxDqDly_Margin_A0==98 ps 10
582 02:41:16.019708 RxClkDly_Margin_A1==88 ps 9
583 02:41:16.020432 TxDqDly_Margin_A1==88 ps 9
584 02:41:16.020896 TrainedVREFDQ_A0==74
585 02:41:16.025301 TrainedVREFDQ_A1==74
586 02:41:16.025920 VrefDac_Margin_A0==25
587 02:41:16.026201 DeviceVref_Margin_A0==40
588 02:41:16.031131 VrefDac_Margin_A1==25
589 02:41:16.031904 DeviceVref_Margin_A1==40
590 02:41:16.032446
591 02:41:16.032907
592 02:41:16.033389 channel==1
593 02:41:16.036438 RxClkDly_Margin_A0==98 ps 10
594 02:41:16.036958 TxDqDly_Margin_A0==88 ps 9
595 02:41:16.042004 RxClkDly_Margin_A1==88 ps 9
596 02:41:16.042346 TxDqDly_Margin_A1==88 ps 9
597 02:41:16.047677 TrainedVREFDQ_A0==77
598 02:41:16.048171 TrainedVREFDQ_A1==77
599 02:41:16.048425 VrefDac_Margin_A0==22
600 02:41:16.053215 DeviceVref_Margin_A0==37
601 02:41:16.053551 VrefDac_Margin_A1==24
602 02:41:16.059063 DeviceVref_Margin_A1==37
603 02:41:16.059614
604 02:41:16.060096 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 02:41:16.060522
606 02:41:16.092360 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 02:41:16.093013 2D training succeed
608 02:41:16.097998 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 02:41:16.103616 auto size-- 65535DDR cs0 size: 2048MB
610 02:41:16.104198 DDR cs1 size: 2048MB
611 02:41:16.109316 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 02:41:16.109852 cs0 DataBus test pass
613 02:41:16.114936 cs1 DataBus test pass
614 02:41:16.115569 cs0 AddrBus test pass
615 02:41:16.116026 cs1 AddrBus test pass
616 02:41:16.116465
617 02:41:16.120442 100bdlr_step_size ps== 420
618 02:41:16.120842 result report
619 02:41:16.125886 boot times 0Enable ddr reg access
620 02:41:16.131089 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 02:41:16.144468 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 02:41:16.716539 0.0;M3 CHK:0;cm4_sp_mode 0
623 02:41:16.717225 MVN_1=0x00000000
624 02:41:16.722110 MVN_2=0x00000000
625 02:41:16.727893 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 02:41:16.728455 OPS=0x10
627 02:41:16.728920 ring efuse init
628 02:41:16.729432 chipver efuse init
629 02:41:16.733398 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 02:41:16.739001 [0.018961 Inits done]
631 02:41:16.739535 secure task start!
632 02:41:16.739940 high task start!
633 02:41:16.743567 low task start!
634 02:41:16.744066 run into bl31
635 02:41:16.750267 NOTICE: BL31: v1.3(release):4fc40b1
636 02:41:16.758004 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 02:41:16.758486 NOTICE: BL31: G12A normal boot!
638 02:41:16.783292 NOTICE: BL31: BL33 decompress pass
639 02:41:16.789048 ERROR: Error initializing runtime service opteed_fast
640 02:41:18.021924
641 02:41:18.022604
642 02:41:18.030582 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 02:41:18.031156
644 02:41:18.031658 Model: Libre Computer AML-A311D-CC Alta
645 02:41:18.238860 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 02:41:18.262273 DRAM: 2 GiB (effective 3.8 GiB)
647 02:41:18.405259 Core: 408 devices, 31 uclasses, devicetree: separate
648 02:41:18.411207 WDT: Not starting watchdog@f0d0
649 02:41:18.443365 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 02:41:18.455844 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 02:41:18.460774 ** Bad device specification mmc 0 **
652 02:41:18.471127 Card did not respond to voltage select! : -110
653 02:41:18.477862 ** Bad device specification mmc 0 **
654 02:41:18.478422 Couldn't find partition mmc 0
655 02:41:18.487094 Card did not respond to voltage select! : -110
656 02:41:18.492632 ** Bad device specification mmc 0 **
657 02:41:18.493174 Couldn't find partition mmc 0
658 02:41:18.497736 Error: could not access storage.
659 02:41:18.840418 Net: eth0: ethernet@ff3f0000
660 02:41:18.840989 starting USB...
661 02:41:19.092259 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 02:41:19.092848 Starting the controller
663 02:41:19.099084 USB XHCI 1.10
664 02:41:20.814072 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 02:41:20.814710 bl2_stage_init 0x01
666 02:41:20.815145 bl2_stage_init 0x81
667 02:41:20.819659 hw id: 0x0000 - pwm id 0x01
668 02:41:20.820183 bl2_stage_init 0xc1
669 02:41:20.820608 bl2_stage_init 0x02
670 02:41:20.821017
671 02:41:20.825297 L0:00000000
672 02:41:20.825775 L1:20000703
673 02:41:20.826187 L2:00008067
674 02:41:20.826587 L3:14000000
675 02:41:20.828105 B2:00402000
676 02:41:20.828568 B1:e0f83180
677 02:41:20.828976
678 02:41:20.829376 TE: 58124
679 02:41:20.829929
680 02:41:20.839150 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 02:41:20.839645
682 02:41:20.840095 Board ID = 1
683 02:41:20.840501 Set A53 clk to 24M
684 02:41:20.840897 Set A73 clk to 24M
685 02:41:20.844810 Set clk81 to 24M
686 02:41:20.845277 A53 clk: 1200 MHz
687 02:41:20.845688 A73 clk: 1200 MHz
688 02:41:20.850309 CLK81: 166.6M
689 02:41:20.850781 smccc: 00012a92
690 02:41:20.856020 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 02:41:20.856498 board id: 1
692 02:41:20.861591 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 02:41:20.875302 fw parse done
694 02:41:20.881411 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 02:41:20.923875 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 02:41:20.934751 PIEI prepare done
697 02:41:20.935241 fastboot data load
698 02:41:20.935658 fastboot data verify
699 02:41:20.940516 verify result: 266
700 02:41:20.946009 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 02:41:20.946491 LPDDR4 probe
702 02:41:20.946902 ddr clk to 1584MHz
703 02:41:20.953927 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 02:41:20.991302
705 02:41:20.991818 dmc_version 0001
706 02:41:20.997959 Check phy result
707 02:41:21.003824 INFO : End of CA training
708 02:41:21.004335 INFO : End of initialization
709 02:41:21.009447 INFO : Training has run successfully!
710 02:41:21.009925 Check phy result
711 02:41:21.015011 INFO : End of initialization
712 02:41:21.015485 INFO : End of read enable training
713 02:41:21.020631 INFO : End of fine write leveling
714 02:41:21.026287 INFO : End of Write leveling coarse delay
715 02:41:21.026780 INFO : Training has run successfully!
716 02:41:21.027194 Check phy result
717 02:41:21.031813 INFO : End of initialization
718 02:41:21.032329 INFO : End of read dq deskew training
719 02:41:21.037460 INFO : End of MPR read delay center optimization
720 02:41:21.043022 INFO : End of write delay center optimization
721 02:41:21.048621 INFO : End of read delay center optimization
722 02:41:21.049090 INFO : End of max read latency training
723 02:41:21.054286 INFO : Training has run successfully!
724 02:41:21.054765 1D training succeed
725 02:41:21.062427 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 02:41:21.111034 Check phy result
727 02:41:21.111554 INFO : End of initialization
728 02:41:21.132811 INFO : End of 2D read delay Voltage center optimization
729 02:41:21.153025 INFO : End of 2D read delay Voltage center optimization
730 02:41:21.205061 INFO : End of 2D write delay Voltage center optimization
731 02:41:21.254619 INFO : End of 2D write delay Voltage center optimization
732 02:41:21.260062 INFO : Training has run successfully!
733 02:41:21.260538
734 02:41:21.260952 channel==0
735 02:41:21.265635 RxClkDly_Margin_A0==88 ps 9
736 02:41:21.266110 TxDqDly_Margin_A0==98 ps 10
737 02:41:21.268936 RxClkDly_Margin_A1==88 ps 9
738 02:41:21.269408 TxDqDly_Margin_A1==88 ps 9
739 02:41:21.274494 TrainedVREFDQ_A0==74
740 02:41:21.275001 TrainedVREFDQ_A1==74
741 02:41:21.275423 VrefDac_Margin_A0==25
742 02:41:21.280059 DeviceVref_Margin_A0==40
743 02:41:21.280542 VrefDac_Margin_A1==25
744 02:41:21.285792 DeviceVref_Margin_A1==40
745 02:41:21.286292
746 02:41:21.286715
747 02:41:21.287125 channel==1
748 02:41:21.287523 RxClkDly_Margin_A0==98 ps 10
749 02:41:21.291383 TxDqDly_Margin_A0==98 ps 10
750 02:41:21.291897 RxClkDly_Margin_A1==88 ps 9
751 02:41:21.296954 TxDqDly_Margin_A1==88 ps 9
752 02:41:21.297435 TrainedVREFDQ_A0==76
753 02:41:21.297847 TrainedVREFDQ_A1==77
754 02:41:21.302524 VrefDac_Margin_A0==22
755 02:41:21.302995 DeviceVref_Margin_A0==38
756 02:41:21.308198 VrefDac_Margin_A1==24
757 02:41:21.308681 DeviceVref_Margin_A1==37
758 02:41:21.309094
759 02:41:21.313723 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 02:41:21.314197
761 02:41:21.341734 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 02:41:21.347440 2D training succeed
763 02:41:21.352794 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 02:41:21.353279 auto size-- 65535DDR cs0 size: 2048MB
765 02:41:21.358425 DDR cs1 size: 2048MB
766 02:41:21.358904 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 02:41:21.364098 cs0 DataBus test pass
768 02:41:21.364604 cs1 DataBus test pass
769 02:41:21.365013 cs0 AddrBus test pass
770 02:41:21.369618 cs1 AddrBus test pass
771 02:41:21.370088
772 02:41:21.370500 100bdlr_step_size ps== 432
773 02:41:21.370909 result report
774 02:41:21.375273 boot times 0Enable ddr reg access
775 02:41:21.382737 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 02:41:21.396221 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 02:41:21.969938 0.0;M3 CHK:0;cm4_sp_mode 0
778 02:41:21.970609 MVN_1=0x00000000
779 02:41:21.975493 MVN_2=0x00000000
780 02:41:21.981171 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 02:41:21.981764 OPS=0x10
782 02:41:21.982172 ring efuse init
783 02:41:21.982564 chipver efuse init
784 02:41:21.986713 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 02:41:21.992370 [0.018961 Inits done]
786 02:41:21.992881 secure task start!
787 02:41:21.993282 high task start!
788 02:41:21.996921 low task start!
789 02:41:21.997436 run into bl31
790 02:41:22.003611 NOTICE: BL31: v1.3(release):4fc40b1
791 02:41:22.011482 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 02:41:22.012022 NOTICE: BL31: G12A normal boot!
793 02:41:22.037453 NOTICE: BL31: BL33 decompress pass
794 02:41:22.043019 ERROR: Error initializing runtime service opteed_fast
795 02:41:23.275951
796 02:41:23.276457
797 02:41:23.284425 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 02:41:23.285086
799 02:41:23.285510 Model: Libre Computer AML-A311D-CC Alta
800 02:41:23.492799 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 02:41:23.516240 DRAM: 2 GiB (effective 3.8 GiB)
802 02:41:23.659213 Core: 408 devices, 31 uclasses, devicetree: separate
803 02:41:23.665152 WDT: Not starting watchdog@f0d0
804 02:41:23.697374 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 02:41:23.709830 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 02:41:23.714819 ** Bad device specification mmc 0 **
807 02:41:23.725159 Card did not respond to voltage select! : -110
808 02:41:23.732822 ** Bad device specification mmc 0 **
809 02:41:23.733265 Couldn't find partition mmc 0
810 02:41:23.741136 Card did not respond to voltage select! : -110
811 02:41:23.746743 ** Bad device specification mmc 0 **
812 02:41:23.747190 Couldn't find partition mmc 0
813 02:41:23.751702 Error: could not access storage.
814 02:41:24.094281 Net: eth0: ethernet@ff3f0000
815 02:41:24.095138 starting USB...
816 02:41:24.345844 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 02:41:24.346626 Starting the controller
818 02:41:24.352776 USB XHCI 1.10
819 02:41:26.512465 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 02:41:26.512993 bl2_stage_init 0x01
821 02:41:26.513292 bl2_stage_init 0x81
822 02:41:26.518172 hw id: 0x0000 - pwm id 0x01
823 02:41:26.518711 bl2_stage_init 0xc1
824 02:41:26.519132 bl2_stage_init 0x02
825 02:41:26.519544
826 02:41:26.523628 L0:00000000
827 02:41:26.524146 L1:20000703
828 02:41:26.524453 L2:00008067
829 02:41:26.524726 L3:14000000
830 02:41:26.529298 B2:00402000
831 02:41:26.529658 B1:e0f83180
832 02:41:26.529927
833 02:41:26.530196 TE: 58167
834 02:41:26.530476
835 02:41:26.534775 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 02:41:26.535325
837 02:41:26.535768 Board ID = 1
838 02:41:26.540369 Set A53 clk to 24M
839 02:41:26.540746 Set A73 clk to 24M
840 02:41:26.541025 Set clk81 to 24M
841 02:41:26.546029 A53 clk: 1200 MHz
842 02:41:26.546568 A73 clk: 1200 MHz
843 02:41:26.546953 CLK81: 166.6M
844 02:41:26.547226 smccc: 00012abe
845 02:41:26.551629 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 02:41:26.557176 board id: 1
847 02:41:26.563099 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 02:41:26.573775 fw parse done
849 02:41:26.579669 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 02:41:26.622388 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 02:41:26.633234 PIEI prepare done
852 02:41:26.633816 fastboot data load
853 02:41:26.634357 fastboot data verify
854 02:41:26.638949 verify result: 266
855 02:41:26.644455 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 02:41:26.645031 LPDDR4 probe
857 02:41:26.645568 ddr clk to 1584MHz
858 02:41:26.652454 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 02:41:26.688770
860 02:41:26.689354 dmc_version 0001
861 02:41:26.696389 Check phy result
862 02:41:26.702234 INFO : End of CA training
863 02:41:26.702786 INFO : End of initialization
864 02:41:26.707833 INFO : Training has run successfully!
865 02:41:26.708540 Check phy result
866 02:41:26.713444 INFO : End of initialization
867 02:41:26.714018 INFO : End of read enable training
868 02:41:26.719086 INFO : End of fine write leveling
869 02:41:26.724642 INFO : End of Write leveling coarse delay
870 02:41:26.725190 INFO : Training has run successfully!
871 02:41:26.725714 Check phy result
872 02:41:26.730224 INFO : End of initialization
873 02:41:26.730776 INFO : End of read dq deskew training
874 02:41:26.735819 INFO : End of MPR read delay center optimization
875 02:41:26.741425 INFO : End of write delay center optimization
876 02:41:26.747071 INFO : End of read delay center optimization
877 02:41:26.747618 INFO : End of max read latency training
878 02:41:26.752652 INFO : Training has run successfully!
879 02:41:26.753203 1D training succeed
880 02:41:26.761844 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 02:41:26.809432 Check phy result
882 02:41:26.810033 INFO : End of initialization
883 02:41:26.831180 INFO : End of 2D read delay Voltage center optimization
884 02:41:26.851446 INFO : End of 2D read delay Voltage center optimization
885 02:41:26.903463 INFO : End of 2D write delay Voltage center optimization
886 02:41:26.952849 INFO : End of 2D write delay Voltage center optimization
887 02:41:26.958438 INFO : Training has run successfully!
888 02:41:26.959027
889 02:41:26.959572 channel==0
890 02:41:26.964081 RxClkDly_Margin_A0==88 ps 9
891 02:41:26.964657 TxDqDly_Margin_A0==98 ps 10
892 02:41:26.967387 RxClkDly_Margin_A1==88 ps 9
893 02:41:26.967944 TxDqDly_Margin_A1==88 ps 9
894 02:41:26.972944 TrainedVREFDQ_A0==74
895 02:41:26.973529 TrainedVREFDQ_A1==74
896 02:41:26.974084 VrefDac_Margin_A0==25
897 02:41:26.978500 DeviceVref_Margin_A0==40
898 02:41:26.979115 VrefDac_Margin_A1==25
899 02:41:26.984222 DeviceVref_Margin_A1==40
900 02:41:26.984815
901 02:41:26.985323
902 02:41:26.985820 channel==1
903 02:41:26.986306 RxClkDly_Margin_A0==98 ps 10
904 02:41:26.987611 TxDqDly_Margin_A0==98 ps 10
905 02:41:26.993144 RxClkDly_Margin_A1==88 ps 9
906 02:41:26.993693 TxDqDly_Margin_A1==98 ps 10
907 02:41:26.994209 TrainedVREFDQ_A0==77
908 02:41:26.998665 TrainedVREFDQ_A1==78
909 02:41:26.999204 VrefDac_Margin_A0==22
910 02:41:27.004401 DeviceVref_Margin_A0==37
911 02:41:27.005000 VrefDac_Margin_A1==24
912 02:41:27.005502 DeviceVref_Margin_A1==36
913 02:41:27.006001
914 02:41:27.009980 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 02:41:27.010529
916 02:41:27.043594 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
917 02:41:27.044407 2D training succeed
918 02:41:27.049192 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 02:41:27.054643 auto size-- 65535DDR cs0 size: 2048MB
920 02:41:27.055230 DDR cs1 size: 2048MB
921 02:41:27.060244 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 02:41:27.060803 cs0 DataBus test pass
923 02:41:27.061313 cs1 DataBus test pass
924 02:41:27.065842 cs0 AddrBus test pass
925 02:41:27.066375 cs1 AddrBus test pass
926 02:41:27.066876
927 02:41:27.071424 100bdlr_step_size ps== 420
928 02:41:27.071977 result report
929 02:41:27.072559 boot times 0Enable ddr reg access
930 02:41:27.081253 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 02:41:27.094743 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 02:41:27.668501 0.0;M3 CHK:0;cm4_sp_mode 0
933 02:41:27.669301 MVN_1=0x00000000
934 02:41:27.673975 MVN_2=0x00000000
935 02:41:27.679619 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 02:41:27.680235 OPS=0x10
937 02:41:27.680780 ring efuse init
938 02:41:27.681299 chipver efuse init
939 02:41:27.685201 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 02:41:27.690853 [0.018961 Inits done]
941 02:41:27.691426 secure task start!
942 02:41:27.691961 high task start!
943 02:41:27.695434 low task start!
944 02:41:27.696006 run into bl31
945 02:41:27.702102 NOTICE: BL31: v1.3(release):4fc40b1
946 02:41:27.709909 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 02:41:27.710480 NOTICE: BL31: G12A normal boot!
948 02:41:27.735313 NOTICE: BL31: BL33 decompress pass
949 02:41:27.741059 ERROR: Error initializing runtime service opteed_fast
950 02:41:28.974050
951 02:41:28.974863
952 02:41:28.982369 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 02:41:28.982965
954 02:41:28.983514 Model: Libre Computer AML-A311D-CC Alta
955 02:41:29.190830 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 02:41:29.214067 DRAM: 2 GiB (effective 3.8 GiB)
957 02:41:29.357103 Core: 408 devices, 31 uclasses, devicetree: separate
958 02:41:29.362925 WDT: Not starting watchdog@f0d0
959 02:41:29.395260 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 02:41:29.407680 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 02:41:29.412714 ** Bad device specification mmc 0 **
962 02:41:29.423063 Card did not respond to voltage select! : -110
963 02:41:29.430613 ** Bad device specification mmc 0 **
964 02:41:29.431204 Couldn't find partition mmc 0
965 02:41:29.438974 Card did not respond to voltage select! : -110
966 02:41:29.444467 ** Bad device specification mmc 0 **
967 02:41:29.445070 Couldn't find partition mmc 0
968 02:41:29.449544 Error: could not access storage.
969 02:41:29.793068 Net: eth0: ethernet@ff3f0000
970 02:41:29.793858 starting USB...
971 02:41:30.045007 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 02:41:30.045809 Starting the controller
973 02:41:30.051786 USB XHCI 1.10
974 02:41:31.606053 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 02:41:31.614179 scanning usb for storage devices... 0 Storage Device(s) found
977 02:41:31.665960 Hit any key to stop autoboot: 1
978 02:41:31.666917 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
979 02:41:31.667659 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
980 02:41:31.668334 Setting prompt string to ['=>']
981 02:41:31.668970 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
982 02:41:31.681743 0
983 02:41:31.682786 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 02:41:31.683425 Sending with 10 millisecond of delay
986 02:41:32.818575 => setenv autoload no
987 02:41:32.829613 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
988 02:41:32.835819 setenv autoload no
989 02:41:32.836720 Sending with 10 millisecond of delay
991 02:41:34.634182 => setenv initrd_high 0xffffffff
992 02:41:34.645159 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
993 02:41:34.646169 setenv initrd_high 0xffffffff
994 02:41:34.647028 Sending with 10 millisecond of delay
996 02:41:36.263796 => setenv fdt_high 0xffffffff
997 02:41:36.274828 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
998 02:41:36.275841 setenv fdt_high 0xffffffff
999 02:41:36.276776 Sending with 10 millisecond of delay
1001 02:41:36.569036 => dhcp
1002 02:41:36.579785 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1003 02:41:36.580475 dhcp
1004 02:41:36.580747 Speed: 1000, full duplex
1005 02:41:36.580994 BOOTP broadcast 1
1006 02:41:36.589928 DHCP client bound to address 192.168.6.27 (10 ms)
1007 02:41:36.590408 Sending with 10 millisecond of delay
1009 02:41:38.266658 => setenv serverip 192.168.6.2
1010 02:41:38.277658 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1011 02:41:38.278757 setenv serverip 192.168.6.2
1012 02:41:38.279606 Sending with 10 millisecond of delay
1014 02:41:42.004038 => tftpboot 0x01080000 956964/tftp-deploy-7qxfifjj/kernel/uImage
1015 02:41:42.015068 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1016 02:41:42.016160 tftpboot 0x01080000 956964/tftp-deploy-7qxfifjj/kernel/uImage
1017 02:41:42.016753 Speed: 1000, full duplex
1018 02:41:42.017293 Using ethernet@ff3f0000 device
1019 02:41:42.017918 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1020 02:41:42.023459 Filename '956964/tftp-deploy-7qxfifjj/kernel/uImage'.
1021 02:41:42.027348 Load address: 0x1080000
1022 02:41:44.353970 Loading: *################################################## 36.1 MiB
1023 02:41:44.354779 15.5 MiB/s
1024 02:41:44.355362 done
1025 02:41:44.358257 Bytes transferred = 37880384 (2420240 hex)
1026 02:41:44.359193 Sending with 10 millisecond of delay
1028 02:41:49.047093 => tftpboot 0x08000000 956964/tftp-deploy-7qxfifjj/ramdisk/ramdisk.cpio.gz.uboot
1029 02:41:49.057893 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1030 02:41:49.058676 tftpboot 0x08000000 956964/tftp-deploy-7qxfifjj/ramdisk/ramdisk.cpio.gz.uboot
1031 02:41:49.059117 Speed: 1000, full duplex
1032 02:41:49.059530 Using ethernet@ff3f0000 device
1033 02:41:49.060545 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1034 02:41:49.069270 Filename '956964/tftp-deploy-7qxfifjj/ramdisk/ramdisk.cpio.gz.uboot'.
1035 02:41:49.069713 Load address: 0x8000000
1036 02:41:55.674755 Loading: *#####T ############################################ UDP wrong checksum 00000005 000050fe
1037 02:42:00.675823 T UDP wrong checksum 00000005 000050fe
1038 02:42:10.678947 T T UDP wrong checksum 00000005 000050fe
1039 02:42:30.683039 T T T T UDP wrong checksum 00000005 000050fe
1040 02:42:45.687166 T T
1041 02:42:45.687968 Retry count exceeded; starting again
1043 02:42:45.689809 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1046 02:42:45.692320 end: 2.4 uboot-commands (duration 00:01:46) [common]
1048 02:42:45.694119 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1050 02:42:45.695361 end: 2 uboot-action (duration 00:01:46) [common]
1052 02:42:45.697352 Cleaning after the job
1053 02:42:45.698053 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/ramdisk
1054 02:42:45.699583 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/kernel
1055 02:42:45.743180 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/dtb
1056 02:42:45.744283 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/nfsrootfs
1057 02:42:45.936232 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956964/tftp-deploy-7qxfifjj/modules
1058 02:42:45.956688 start: 4.1 power-off (timeout 00:00:30) [common]
1059 02:42:45.957344 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1060 02:42:45.989864 >> OK - accepted request
1061 02:42:45.992209 Returned 0 in 0 seconds
1062 02:42:46.093112 end: 4.1 power-off (duration 00:00:00) [common]
1064 02:42:46.094168 start: 4.2 read-feedback (timeout 00:10:00) [common]
1065 02:42:46.094893 Listened to connection for namespace 'common' for up to 1s
1066 02:42:47.095445 Finalising connection for namespace 'common'
1067 02:42:47.095945 Disconnecting from shell: Finalise
1068 02:42:47.096271 =>
1069 02:42:47.197046 end: 4.2 read-feedback (duration 00:00:01) [common]
1070 02:42:47.197747 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/956964
1071 02:42:50.091368 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/956964
1072 02:42:50.092014 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.