Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:50:21.957750 lava-dispatcher, installed at version: 2024.01
2 02:50:21.958552 start: 0 validate
3 02:50:21.959083 Start time: 2024-11-08 02:50:21.959052+00:00 (UTC)
4 02:50:21.959639 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:50:21.960224 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 02:50:22.001283 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:50:22.001827 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 02:50:22.034927 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:50:22.035631 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:50:22.069057 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:50:22.069579 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 02:50:22.102109 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:50:22.102612 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
14 02:50:22.147967 validate duration: 0.19
16 02:50:22.149522 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:50:22.150121 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:50:22.150713 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:50:22.151679 Not decompressing ramdisk as can be used compressed.
20 02:50:22.152500 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 02:50:22.153022 saving as /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/ramdisk/initrd.cpio.gz
22 02:50:22.153540 total size: 5628140 (5 MB)
23 02:50:22.193960 progress 0 % (0 MB)
24 02:50:22.202612 progress 5 % (0 MB)
25 02:50:22.211726 progress 10 % (0 MB)
26 02:50:22.219778 progress 15 % (0 MB)
27 02:50:22.227865 progress 20 % (1 MB)
28 02:50:22.231855 progress 25 % (1 MB)
29 02:50:22.236075 progress 30 % (1 MB)
30 02:50:22.240286 progress 35 % (1 MB)
31 02:50:22.244133 progress 40 % (2 MB)
32 02:50:22.248326 progress 45 % (2 MB)
33 02:50:22.252026 progress 50 % (2 MB)
34 02:50:22.256278 progress 55 % (2 MB)
35 02:50:22.260401 progress 60 % (3 MB)
36 02:50:22.264072 progress 65 % (3 MB)
37 02:50:22.268355 progress 70 % (3 MB)
38 02:50:22.271945 progress 75 % (4 MB)
39 02:50:22.276326 progress 80 % (4 MB)
40 02:50:22.280056 progress 85 % (4 MB)
41 02:50:22.284134 progress 90 % (4 MB)
42 02:50:22.288128 progress 95 % (5 MB)
43 02:50:22.291431 progress 100 % (5 MB)
44 02:50:22.292112 5 MB downloaded in 0.14 s (38.74 MB/s)
45 02:50:22.292676 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:50:22.293564 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:50:22.293857 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:50:22.294130 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:50:22.294612 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/clang-16/kernel/Image
51 02:50:22.294859 saving as /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/kernel/Image
52 02:50:22.295068 total size: 37880320 (36 MB)
53 02:50:22.295278 No compression specified
54 02:50:22.332340 progress 0 % (0 MB)
55 02:50:22.357099 progress 5 % (1 MB)
56 02:50:22.382824 progress 10 % (3 MB)
57 02:50:22.408096 progress 15 % (5 MB)
58 02:50:22.433029 progress 20 % (7 MB)
59 02:50:22.458779 progress 25 % (9 MB)
60 02:50:22.483329 progress 30 % (10 MB)
61 02:50:22.509615 progress 35 % (12 MB)
62 02:50:22.538027 progress 40 % (14 MB)
63 02:50:22.565711 progress 45 % (16 MB)
64 02:50:22.590726 progress 50 % (18 MB)
65 02:50:22.615852 progress 55 % (19 MB)
66 02:50:22.640910 progress 60 % (21 MB)
67 02:50:22.666072 progress 65 % (23 MB)
68 02:50:22.691408 progress 70 % (25 MB)
69 02:50:22.716327 progress 75 % (27 MB)
70 02:50:22.740794 progress 80 % (28 MB)
71 02:50:22.766406 progress 85 % (30 MB)
72 02:50:22.791709 progress 90 % (32 MB)
73 02:50:22.816529 progress 95 % (34 MB)
74 02:50:22.841254 progress 100 % (36 MB)
75 02:50:22.841761 36 MB downloaded in 0.55 s (66.08 MB/s)
76 02:50:22.842245 end: 1.2.1 http-download (duration 00:00:01) [common]
78 02:50:22.843071 end: 1.2 download-retry (duration 00:00:01) [common]
79 02:50:22.843346 start: 1.3 download-retry (timeout 00:09:59) [common]
80 02:50:22.843617 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 02:50:22.844126 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 02:50:22.844411 saving as /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/dtb/meson-g12b-a311d-libretech-cc.dtb
83 02:50:22.844620 total size: 54703 (0 MB)
84 02:50:22.844831 No compression specified
85 02:50:22.887138 progress 59 % (0 MB)
86 02:50:22.888019 progress 100 % (0 MB)
87 02:50:22.888581 0 MB downloaded in 0.04 s (1.19 MB/s)
88 02:50:22.889072 end: 1.3.1 http-download (duration 00:00:00) [common]
90 02:50:22.889888 end: 1.3 download-retry (duration 00:00:00) [common]
91 02:50:22.890152 start: 1.4 download-retry (timeout 00:09:59) [common]
92 02:50:22.890416 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 02:50:22.890871 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 02:50:22.891112 saving as /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/nfsrootfs/full.rootfs.tar
95 02:50:22.891315 total size: 474398908 (452 MB)
96 02:50:22.891525 Using unxz to decompress xz
97 02:50:22.929484 progress 0 % (0 MB)
98 02:50:24.034161 progress 5 % (22 MB)
99 02:50:25.493340 progress 10 % (45 MB)
100 02:50:25.945268 progress 15 % (67 MB)
101 02:50:26.752203 progress 20 % (90 MB)
102 02:50:27.308025 progress 25 % (113 MB)
103 02:50:27.688283 progress 30 % (135 MB)
104 02:50:28.308528 progress 35 % (158 MB)
105 02:50:29.236883 progress 40 % (181 MB)
106 02:50:30.101475 progress 45 % (203 MB)
107 02:50:30.691190 progress 50 % (226 MB)
108 02:50:31.335558 progress 55 % (248 MB)
109 02:50:32.546274 progress 60 % (271 MB)
110 02:50:34.027395 progress 65 % (294 MB)
111 02:50:35.708388 progress 70 % (316 MB)
112 02:50:38.758455 progress 75 % (339 MB)
113 02:50:41.184079 progress 80 % (361 MB)
114 02:50:44.051543 progress 85 % (384 MB)
115 02:50:47.232180 progress 90 % (407 MB)
116 02:50:50.374228 progress 95 % (429 MB)
117 02:50:53.481336 progress 100 % (452 MB)
118 02:50:53.494189 452 MB downloaded in 30.60 s (14.78 MB/s)
119 02:50:53.495172 end: 1.4.1 http-download (duration 00:00:31) [common]
121 02:50:53.497020 end: 1.4 download-retry (duration 00:00:31) [common]
122 02:50:53.497611 start: 1.5 download-retry (timeout 00:09:29) [common]
123 02:50:53.498199 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 02:50:53.499063 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/clang-16/modules.tar.xz
125 02:50:53.499568 saving as /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/modules/modules.tar
126 02:50:53.500061 total size: 11768564 (11 MB)
127 02:50:53.500537 Using unxz to decompress xz
128 02:50:53.544493 progress 0 % (0 MB)
129 02:50:53.611460 progress 5 % (0 MB)
130 02:50:53.685702 progress 10 % (1 MB)
131 02:50:53.780295 progress 15 % (1 MB)
132 02:50:53.875544 progress 20 % (2 MB)
133 02:50:53.954120 progress 25 % (2 MB)
134 02:50:54.030483 progress 30 % (3 MB)
135 02:50:54.110198 progress 35 % (3 MB)
136 02:50:54.189465 progress 40 % (4 MB)
137 02:50:54.264711 progress 45 % (5 MB)
138 02:50:54.350082 progress 50 % (5 MB)
139 02:50:54.431730 progress 55 % (6 MB)
140 02:50:54.517072 progress 60 % (6 MB)
141 02:50:54.598820 progress 65 % (7 MB)
142 02:50:54.681838 progress 70 % (7 MB)
143 02:50:54.766178 progress 75 % (8 MB)
144 02:50:54.850509 progress 80 % (9 MB)
145 02:50:54.931588 progress 85 % (9 MB)
146 02:50:55.015383 progress 90 % (10 MB)
147 02:50:55.093987 progress 95 % (10 MB)
148 02:50:55.171117 progress 100 % (11 MB)
149 02:50:55.181645 11 MB downloaded in 1.68 s (6.67 MB/s)
150 02:50:55.182406 end: 1.5.1 http-download (duration 00:00:02) [common]
152 02:50:55.184345 end: 1.5 download-retry (duration 00:00:02) [common]
153 02:50:55.184955 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 02:50:55.185550 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 02:51:10.575220 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/956999/extract-nfsrootfs-n7etge48
156 02:51:10.575826 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 02:51:10.576154 start: 1.6.2 lava-overlay (timeout 00:09:12) [common]
158 02:51:10.576938 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y
159 02:51:10.577409 makedir: /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin
160 02:51:10.577748 makedir: /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/tests
161 02:51:10.578065 makedir: /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/results
162 02:51:10.578437 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-add-keys
163 02:51:10.579077 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-add-sources
164 02:51:10.579594 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-background-process-start
165 02:51:10.580141 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-background-process-stop
166 02:51:10.580679 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-common-functions
167 02:51:10.581154 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-echo-ipv4
168 02:51:10.581620 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-install-packages
169 02:51:10.582088 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-installed-packages
170 02:51:10.582571 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-os-build
171 02:51:10.583102 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-probe-channel
172 02:51:10.583578 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-probe-ip
173 02:51:10.584149 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-target-ip
174 02:51:10.584636 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-target-mac
175 02:51:10.585100 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-target-storage
176 02:51:10.585569 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-test-case
177 02:51:10.586032 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-test-event
178 02:51:10.586508 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-test-feedback
179 02:51:10.587014 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-test-raise
180 02:51:10.587473 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-test-reference
181 02:51:10.587935 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-test-runner
182 02:51:10.588456 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-test-set
183 02:51:10.588921 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-test-shell
184 02:51:10.589388 Updating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-install-packages (oe)
185 02:51:10.589905 Updating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/bin/lava-installed-packages (oe)
186 02:51:10.590335 Creating /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/environment
187 02:51:10.590690 LAVA metadata
188 02:51:10.590943 - LAVA_JOB_ID=956999
189 02:51:10.591156 - LAVA_DISPATCHER_IP=192.168.6.2
190 02:51:10.591516 start: 1.6.2.1 ssh-authorize (timeout 00:09:12) [common]
191 02:51:10.592483 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 02:51:10.592793 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:12) [common]
193 02:51:10.593004 skipped lava-vland-overlay
194 02:51:10.593246 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 02:51:10.593502 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:12) [common]
196 02:51:10.593720 skipped lava-multinode-overlay
197 02:51:10.593962 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 02:51:10.594213 start: 1.6.2.4 test-definition (timeout 00:09:12) [common]
199 02:51:10.594459 Loading test definitions
200 02:51:10.594735 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:12) [common]
201 02:51:10.594955 Using /lava-956999 at stage 0
202 02:51:10.596122 uuid=956999_1.6.2.4.1 testdef=None
203 02:51:10.596431 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 02:51:10.596693 start: 1.6.2.4.2 test-overlay (timeout 00:09:12) [common]
205 02:51:10.598429 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 02:51:10.599223 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:12) [common]
208 02:51:10.601420 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 02:51:10.602250 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:12) [common]
211 02:51:10.604339 runner path: /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 956999_1.6.2.4.1
212 02:51:10.604910 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 02:51:10.605669 Creating lava-test-runner.conf files
215 02:51:10.605870 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/956999/lava-overlay-9lzqm53y/lava-956999/0 for stage 0
216 02:51:10.606194 - 0_v4l2-decoder-conformance-h264
217 02:51:10.606530 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 02:51:10.606797 start: 1.6.2.5 compress-overlay (timeout 00:09:12) [common]
219 02:51:10.628054 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 02:51:10.628441 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:12) [common]
221 02:51:10.628696 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 02:51:10.628960 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 02:51:10.629255 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:12) [common]
224 02:51:11.242016 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 02:51:11.242581 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 02:51:11.242890 extracting modules file /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956999/extract-nfsrootfs-n7etge48
227 02:51:12.650177 extracting modules file /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/modules/modules.tar to /var/lib/lava/dispatcher/tmp/956999/extract-overlay-ramdisk-f8n_2jmt/ramdisk
228 02:51:14.036913 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 02:51:14.037391 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 02:51:14.037662 [common] Applying overlay to NFS
231 02:51:14.037874 [common] Applying overlay /var/lib/lava/dispatcher/tmp/956999/compress-overlay-1xmjs0_e/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/956999/extract-nfsrootfs-n7etge48
232 02:51:14.066560 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 02:51:14.066940 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 02:51:14.067209 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 02:51:14.067435 Converting downloaded kernel to a uImage
236 02:51:14.067753 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/kernel/Image /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/kernel/uImage
237 02:51:14.477038 output: Image Name:
238 02:51:14.477459 output: Created: Fri Nov 8 02:51:14 2024
239 02:51:14.477671 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 02:51:14.477876 output: Data Size: 37880320 Bytes = 36992.50 KiB = 36.13 MiB
241 02:51:14.478079 output: Load Address: 01080000
242 02:51:14.478280 output: Entry Point: 01080000
243 02:51:14.478478 output:
244 02:51:14.478809 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 02:51:14.479074 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 02:51:14.479342 start: 1.6.7 configure-preseed-file (timeout 00:09:08) [common]
247 02:51:14.479594 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 02:51:14.479850 start: 1.6.8 compress-ramdisk (timeout 00:09:08) [common]
249 02:51:14.480143 Building ramdisk /var/lib/lava/dispatcher/tmp/956999/extract-overlay-ramdisk-f8n_2jmt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/956999/extract-overlay-ramdisk-f8n_2jmt/ramdisk
250 02:51:16.701669 >> 173443 blocks
251 02:51:24.348453 Adding RAMdisk u-boot header.
252 02:51:24.349087 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/956999/extract-overlay-ramdisk-f8n_2jmt/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/956999/extract-overlay-ramdisk-f8n_2jmt/ramdisk.cpio.gz.uboot
253 02:51:24.594125 output: Image Name:
254 02:51:24.594542 output: Created: Fri Nov 8 02:51:24 2024
255 02:51:24.595015 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 02:51:24.595481 output: Data Size: 24148825 Bytes = 23582.84 KiB = 23.03 MiB
257 02:51:24.595937 output: Load Address: 00000000
258 02:51:24.596448 output: Entry Point: 00000000
259 02:51:24.596901 output:
260 02:51:24.597988 rename /var/lib/lava/dispatcher/tmp/956999/extract-overlay-ramdisk-f8n_2jmt/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/ramdisk/ramdisk.cpio.gz.uboot
261 02:51:24.598768 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 02:51:24.599376 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
263 02:51:24.599973 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:58) [common]
264 02:51:24.600532 No LXC device requested
265 02:51:24.601105 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 02:51:24.601682 start: 1.8 deploy-device-env (timeout 00:08:58) [common]
267 02:51:24.602239 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 02:51:24.602703 Checking files for TFTP limit of 4294967296 bytes.
269 02:51:24.605679 end: 1 tftp-deploy (duration 00:01:02) [common]
270 02:51:24.606319 start: 2 uboot-action (timeout 00:05:00) [common]
271 02:51:24.606909 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 02:51:24.607469 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 02:51:24.608110 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 02:51:24.608717 Using kernel file from prepare-kernel: 956999/tftp-deploy-7fo83oil/kernel/uImage
275 02:51:24.609422 substitutions:
276 02:51:24.609875 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 02:51:24.610322 - {DTB_ADDR}: 0x01070000
278 02:51:24.610767 - {DTB}: 956999/tftp-deploy-7fo83oil/dtb/meson-g12b-a311d-libretech-cc.dtb
279 02:51:24.611214 - {INITRD}: 956999/tftp-deploy-7fo83oil/ramdisk/ramdisk.cpio.gz.uboot
280 02:51:24.611655 - {KERNEL_ADDR}: 0x01080000
281 02:51:24.612126 - {KERNEL}: 956999/tftp-deploy-7fo83oil/kernel/uImage
282 02:51:24.612573 - {LAVA_MAC}: None
283 02:51:24.613059 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/956999/extract-nfsrootfs-n7etge48
284 02:51:24.613505 - {NFS_SERVER_IP}: 192.168.6.2
285 02:51:24.613961 - {PRESEED_CONFIG}: None
286 02:51:24.614401 - {PRESEED_LOCAL}: None
287 02:51:24.614840 - {RAMDISK_ADDR}: 0x08000000
288 02:51:24.615272 - {RAMDISK}: 956999/tftp-deploy-7fo83oil/ramdisk/ramdisk.cpio.gz.uboot
289 02:51:24.615702 - {ROOT_PART}: None
290 02:51:24.616181 - {ROOT}: None
291 02:51:24.616631 - {SERVER_IP}: 192.168.6.2
292 02:51:24.617072 - {TEE_ADDR}: 0x83000000
293 02:51:24.617505 - {TEE}: None
294 02:51:24.617939 Parsed boot commands:
295 02:51:24.618362 - setenv autoload no
296 02:51:24.618793 - setenv initrd_high 0xffffffff
297 02:51:24.619225 - setenv fdt_high 0xffffffff
298 02:51:24.619656 - dhcp
299 02:51:24.620114 - setenv serverip 192.168.6.2
300 02:51:24.620548 - tftpboot 0x01080000 956999/tftp-deploy-7fo83oil/kernel/uImage
301 02:51:24.620982 - tftpboot 0x08000000 956999/tftp-deploy-7fo83oil/ramdisk/ramdisk.cpio.gz.uboot
302 02:51:24.621417 - tftpboot 0x01070000 956999/tftp-deploy-7fo83oil/dtb/meson-g12b-a311d-libretech-cc.dtb
303 02:51:24.621850 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/956999/extract-nfsrootfs-n7etge48,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 02:51:24.622292 - bootm 0x01080000 0x08000000 0x01070000
305 02:51:24.622849 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 02:51:24.624621 start: 2.3 connect-device (timeout 00:05:00) [common]
308 02:51:24.625098 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 02:51:24.640310 Setting prompt string to ['lava-test: # ']
310 02:51:24.641919 end: 2.3 connect-device (duration 00:00:00) [common]
311 02:51:24.642588 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 02:51:24.643200 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 02:51:24.643939 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 02:51:24.645279 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 02:51:24.681676 >> OK - accepted request
316 02:51:24.683888 Returned 0 in 0 seconds
317 02:51:24.785174 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 02:51:24.786983 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 02:51:24.787623 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 02:51:24.788255 Setting prompt string to ['Hit any key to stop autoboot']
322 02:51:24.788790 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 02:51:24.790528 Trying 192.168.56.21...
324 02:51:24.791067 Connected to conserv1.
325 02:51:24.791554 Escape character is '^]'.
326 02:51:24.792068
327 02:51:24.792558 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 02:51:24.793043
329 02:51:36.465809 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 02:51:36.466493 bl2_stage_init 0x01
331 02:51:36.466950 bl2_stage_init 0x81
332 02:51:36.471268 hw id: 0x0000 - pwm id 0x01
333 02:51:36.471759 bl2_stage_init 0xc1
334 02:51:36.472316 bl2_stage_init 0x02
335 02:51:36.472762
336 02:51:36.476856 L0:00000000
337 02:51:36.477329 L1:20000703
338 02:51:36.477781 L2:00008067
339 02:51:36.478214 L3:14000000
340 02:51:36.479732 B2:00402000
341 02:51:36.480248 B1:e0f83180
342 02:51:36.480697
343 02:51:36.481136 TE: 58124
344 02:51:36.481573
345 02:51:36.491003 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 02:51:36.491478
347 02:51:36.491920 Board ID = 1
348 02:51:36.492386 Set A53 clk to 24M
349 02:51:36.492818 Set A73 clk to 24M
350 02:51:36.496515 Set clk81 to 24M
351 02:51:36.496999 A53 clk: 1200 MHz
352 02:51:36.497433 A73 clk: 1200 MHz
353 02:51:36.500052 CLK81: 166.6M
354 02:51:36.500522 smccc: 00012a92
355 02:51:36.505547 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 02:51:36.511019 board id: 1
357 02:51:36.516444 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 02:51:36.526868 fw parse done
359 02:51:36.532813 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 02:51:36.575351 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 02:51:36.586393 PIEI prepare done
362 02:51:36.586858 fastboot data load
363 02:51:36.587297 fastboot data verify
364 02:51:36.591955 verify result: 266
365 02:51:36.597532 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 02:51:36.597999 LPDDR4 probe
367 02:51:36.598437 ddr clk to 1584MHz
368 02:51:36.605526 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 02:51:36.642828
370 02:51:36.643302 dmc_version 0001
371 02:51:36.649481 Check phy result
372 02:51:36.655353 INFO : End of CA training
373 02:51:36.655817 INFO : End of initialization
374 02:51:36.660949 INFO : Training has run successfully!
375 02:51:36.661411 Check phy result
376 02:51:36.666650 INFO : End of initialization
377 02:51:36.667116 INFO : End of read enable training
378 02:51:36.669968 INFO : End of fine write leveling
379 02:51:36.675531 INFO : End of Write leveling coarse delay
380 02:51:36.681144 INFO : Training has run successfully!
381 02:51:36.681607 Check phy result
382 02:51:36.682044 INFO : End of initialization
383 02:51:36.686733 INFO : End of read dq deskew training
384 02:51:36.692327 INFO : End of MPR read delay center optimization
385 02:51:36.692796 INFO : End of write delay center optimization
386 02:51:36.697936 INFO : End of read delay center optimization
387 02:51:36.703545 INFO : End of max read latency training
388 02:51:36.704067 INFO : Training has run successfully!
389 02:51:36.709115 1D training succeed
390 02:51:36.715002 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 02:51:36.762466 Check phy result
392 02:51:36.762926 INFO : End of initialization
393 02:51:36.784109 INFO : End of 2D read delay Voltage center optimization
394 02:51:36.804212 INFO : End of 2D read delay Voltage center optimization
395 02:51:36.856131 INFO : End of 2D write delay Voltage center optimization
396 02:51:36.905338 INFO : End of 2D write delay Voltage center optimization
397 02:51:36.910953 INFO : Training has run successfully!
398 02:51:36.911414
399 02:51:36.911858 channel==0
400 02:51:36.916517 RxClkDly_Margin_A0==88 ps 9
401 02:51:36.916997 TxDqDly_Margin_A0==98 ps 10
402 02:51:36.919837 RxClkDly_Margin_A1==88 ps 9
403 02:51:36.920328 TxDqDly_Margin_A1==98 ps 10
404 02:51:36.925353 TrainedVREFDQ_A0==74
405 02:51:36.925819 TrainedVREFDQ_A1==74
406 02:51:36.930955 VrefDac_Margin_A0==25
407 02:51:36.931418 DeviceVref_Margin_A0==40
408 02:51:36.931855 VrefDac_Margin_A1==25
409 02:51:36.936568 DeviceVref_Margin_A1==40
410 02:51:36.937032
411 02:51:36.937470
412 02:51:36.937910 channel==1
413 02:51:36.938344 RxClkDly_Margin_A0==98 ps 10
414 02:51:36.939962 TxDqDly_Margin_A0==88 ps 9
415 02:51:36.945563 RxClkDly_Margin_A1==88 ps 9
416 02:51:36.946023 TxDqDly_Margin_A1==108 ps 11
417 02:51:36.946463 TrainedVREFDQ_A0==76
418 02:51:36.951165 TrainedVREFDQ_A1==78
419 02:51:36.951629 VrefDac_Margin_A0==22
420 02:51:36.956835 DeviceVref_Margin_A0==38
421 02:51:36.957296 VrefDac_Margin_A1==24
422 02:51:36.957732 DeviceVref_Margin_A1==36
423 02:51:36.958164
424 02:51:36.962369 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 02:51:36.962831
426 02:51:36.995963 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 02:51:36.996530 2D training succeed
428 02:51:37.001574 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 02:51:37.007164 auto size-- 65535DDR cs0 size: 2048MB
430 02:51:37.007631 DDR cs1 size: 2048MB
431 02:51:37.012836 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 02:51:37.013301 cs0 DataBus test pass
433 02:51:37.013737 cs1 DataBus test pass
434 02:51:37.018356 cs0 AddrBus test pass
435 02:51:37.018819 cs1 AddrBus test pass
436 02:51:37.019255
437 02:51:37.023969 100bdlr_step_size ps== 420
438 02:51:37.024464 result report
439 02:51:37.024905 boot times 0Enable ddr reg access
440 02:51:37.034027 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 02:51:37.047443 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 02:51:37.619548 0.0;M3 CHK:0;cm4_sp_mode 0
443 02:51:37.620262 MVN_1=0x00000000
444 02:51:37.625050 MVN_2=0x00000000
445 02:51:37.630683 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 02:51:37.631163 OPS=0x10
447 02:51:37.631618 ring efuse init
448 02:51:37.632096 chipver efuse init
449 02:51:37.636296 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 02:51:37.641880 [0.018961 Inits done]
451 02:51:37.642347 secure task start!
452 02:51:37.642796 high task start!
453 02:51:37.646475 low task start!
454 02:51:37.646947 run into bl31
455 02:51:37.653121 NOTICE: BL31: v1.3(release):4fc40b1
456 02:51:37.660961 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 02:51:37.661443 NOTICE: BL31: G12A normal boot!
458 02:51:37.686329 NOTICE: BL31: BL33 decompress pass
459 02:51:37.691969 ERROR: Error initializing runtime service opteed_fast
460 02:51:38.924946
461 02:51:38.925621
462 02:51:38.933278 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 02:51:38.933760
464 02:51:38.934216 Model: Libre Computer AML-A311D-CC Alta
465 02:51:39.141751 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 02:51:39.165063 DRAM: 2 GiB (effective 3.8 GiB)
467 02:51:39.308085 Core: 408 devices, 31 uclasses, devicetree: separate
468 02:51:39.313912 WDT: Not starting watchdog@f0d0
469 02:51:39.346250 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 02:51:39.358634 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 02:51:39.363601 ** Bad device specification mmc 0 **
472 02:51:39.373947 Card did not respond to voltage select! : -110
473 02:51:39.381597 ** Bad device specification mmc 0 **
474 02:51:39.382096 Couldn't find partition mmc 0
475 02:51:39.389956 Card did not respond to voltage select! : -110
476 02:51:39.395488 ** Bad device specification mmc 0 **
477 02:51:39.395967 Couldn't find partition mmc 0
478 02:51:39.400543 Error: could not access storage.
479 02:51:40.665934 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 02:51:40.666581 bl2_stage_init 0x01
481 02:51:40.667046 bl2_stage_init 0x81
482 02:51:40.671528 hw id: 0x0000 - pwm id 0x01
483 02:51:40.672040 bl2_stage_init 0xc1
484 02:51:40.672498 bl2_stage_init 0x02
485 02:51:40.672946
486 02:51:40.677107 L0:00000000
487 02:51:40.677575 L1:20000703
488 02:51:40.678024 L2:00008067
489 02:51:40.678470 L3:14000000
490 02:51:40.682686 B2:00402000
491 02:51:40.683160 B1:e0f83180
492 02:51:40.683609
493 02:51:40.684089 TE: 58124
494 02:51:40.684542
495 02:51:40.688297 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 02:51:40.688772
497 02:51:40.689223 Board ID = 1
498 02:51:40.693892 Set A53 clk to 24M
499 02:51:40.694365 Set A73 clk to 24M
500 02:51:40.694815 Set clk81 to 24M
501 02:51:40.699482 A53 clk: 1200 MHz
502 02:51:40.699950 A73 clk: 1200 MHz
503 02:51:40.700437 CLK81: 166.6M
504 02:51:40.700886 smccc: 00012a92
505 02:51:40.705095 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 02:51:40.710684 board id: 1
507 02:51:40.716565 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 02:51:40.727218 fw parse done
509 02:51:40.733183 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 02:51:40.775830 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 02:51:40.786708 PIEI prepare done
512 02:51:40.787178 fastboot data load
513 02:51:40.787629 fastboot data verify
514 02:51:40.792379 verify result: 266
515 02:51:40.797937 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 02:51:40.798410 LPDDR4 probe
517 02:51:40.798857 ddr clk to 1584MHz
518 02:51:40.805959 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 02:51:40.843213
520 02:51:40.843691 dmc_version 0001
521 02:51:40.849871 Check phy result
522 02:51:40.855759 INFO : End of CA training
523 02:51:40.856263 INFO : End of initialization
524 02:51:40.861380 INFO : Training has run successfully!
525 02:51:40.861852 Check phy result
526 02:51:40.866940 INFO : End of initialization
527 02:51:40.867407 INFO : End of read enable training
528 02:51:40.872553 INFO : End of fine write leveling
529 02:51:40.878152 INFO : End of Write leveling coarse delay
530 02:51:40.878641 INFO : Training has run successfully!
531 02:51:40.879091 Check phy result
532 02:51:40.883742 INFO : End of initialization
533 02:51:40.884255 INFO : End of read dq deskew training
534 02:51:40.889373 INFO : End of MPR read delay center optimization
535 02:51:40.894943 INFO : End of write delay center optimization
536 02:51:40.900553 INFO : End of read delay center optimization
537 02:51:40.901027 INFO : End of max read latency training
538 02:51:40.906141 INFO : Training has run successfully!
539 02:51:40.906630 1D training succeed
540 02:51:40.915322 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 02:51:40.962911 Check phy result
542 02:51:40.963398 INFO : End of initialization
543 02:51:40.984697 INFO : End of 2D read delay Voltage center optimization
544 02:51:41.004892 INFO : End of 2D read delay Voltage center optimization
545 02:51:41.056941 INFO : End of 2D write delay Voltage center optimization
546 02:51:41.106299 INFO : End of 2D write delay Voltage center optimization
547 02:51:41.111887 INFO : Training has run successfully!
548 02:51:41.112425
549 02:51:41.112887 channel==0
550 02:51:41.117548 RxClkDly_Margin_A0==88 ps 9
551 02:51:41.118049 TxDqDly_Margin_A0==98 ps 10
552 02:51:41.123059 RxClkDly_Margin_A1==88 ps 9
553 02:51:41.123545 TxDqDly_Margin_A1==98 ps 10
554 02:51:41.124030 TrainedVREFDQ_A0==74
555 02:51:41.128663 TrainedVREFDQ_A1==74
556 02:51:41.129146 VrefDac_Margin_A0==25
557 02:51:41.129595 DeviceVref_Margin_A0==40
558 02:51:41.134280 VrefDac_Margin_A1==23
559 02:51:41.134747 DeviceVref_Margin_A1==40
560 02:51:41.135194
561 02:51:41.135638
562 02:51:41.139863 channel==1
563 02:51:41.140366 RxClkDly_Margin_A0==98 ps 10
564 02:51:41.140812 TxDqDly_Margin_A0==98 ps 10
565 02:51:41.145540 RxClkDly_Margin_A1==98 ps 10
566 02:51:41.146014 TxDqDly_Margin_A1==88 ps 9
567 02:51:41.151060 TrainedVREFDQ_A0==76
568 02:51:41.151535 TrainedVREFDQ_A1==77
569 02:51:41.152015 VrefDac_Margin_A0==22
570 02:51:41.156676 DeviceVref_Margin_A0==38
571 02:51:41.157147 VrefDac_Margin_A1==22
572 02:51:41.162280 DeviceVref_Margin_A1==37
573 02:51:41.162765
574 02:51:41.163214 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 02:51:41.167855
576 02:51:41.195862 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
577 02:51:41.196410 2D training succeed
578 02:51:41.201555 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 02:51:41.207063 auto size-- 65535DDR cs0 size: 2048MB
580 02:51:41.207542 DDR cs1 size: 2048MB
581 02:51:41.212664 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 02:51:41.213140 cs0 DataBus test pass
583 02:51:41.218277 cs1 DataBus test pass
584 02:51:41.218749 cs0 AddrBus test pass
585 02:51:41.219200 cs1 AddrBus test pass
586 02:51:41.219641
587 02:51:41.223869 100bdlr_step_size ps== 420
588 02:51:41.224402 result report
589 02:51:41.229529 boot times 0Enable ddr reg access
590 02:51:41.234911 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 02:51:41.248405 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 02:51:41.822628 0.0;M3 CHK:0;cm4_sp_mode 0
593 02:51:41.823277 MVN_1=0x00000000
594 02:51:41.827849 MVN_2=0x00000000
595 02:51:41.833548 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 02:51:41.834067 OPS=0x10
597 02:51:41.834525 ring efuse init
598 02:51:41.835004 chipver efuse init
599 02:51:41.839207 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 02:51:41.844885 [0.018961 Inits done]
601 02:51:41.845358 secure task start!
602 02:51:41.845794 high task start!
603 02:51:41.849394 low task start!
604 02:51:41.849857 run into bl31
605 02:51:41.855957 NOTICE: BL31: v1.3(release):4fc40b1
606 02:51:41.863873 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 02:51:41.864381 NOTICE: BL31: G12A normal boot!
608 02:51:41.889891 NOTICE: BL31: BL33 decompress pass
609 02:51:41.895425 ERROR: Error initializing runtime service opteed_fast
610 02:51:43.128476
611 02:51:43.129171
612 02:51:43.136712 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 02:51:43.137241
614 02:51:43.137706 Model: Libre Computer AML-A311D-CC Alta
615 02:51:43.345100 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 02:51:43.368472 DRAM: 2 GiB (effective 3.8 GiB)
617 02:51:43.511653 Core: 408 devices, 31 uclasses, devicetree: separate
618 02:51:43.517500 WDT: Not starting watchdog@f0d0
619 02:51:43.549737 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 02:51:43.562233 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 02:51:43.567248 ** Bad device specification mmc 0 **
622 02:51:43.577291 Card did not respond to voltage select! : -110
623 02:51:43.585113 ** Bad device specification mmc 0 **
624 02:51:43.585602 Couldn't find partition mmc 0
625 02:51:43.593251 Card did not respond to voltage select! : -110
626 02:51:43.599141 ** Bad device specification mmc 0 **
627 02:51:43.599623 Couldn't find partition mmc 0
628 02:51:43.604181 Error: could not access storage.
629 02:51:43.947483 Net: eth0: ethernet@ff3f0000
630 02:51:43.948087 starting USB...
631 02:51:44.199253 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 02:51:44.199798 Starting the controller
633 02:51:44.206227 USB XHCI 1.10
634 02:51:45.916514 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 02:51:45.917173 bl2_stage_init 0x01
636 02:51:45.917640 bl2_stage_init 0x81
637 02:51:45.921863 hw id: 0x0000 - pwm id 0x01
638 02:51:45.922355 bl2_stage_init 0xc1
639 02:51:45.922812 bl2_stage_init 0x02
640 02:51:45.923263
641 02:51:45.927489 L0:00000000
642 02:51:45.927973 L1:20000703
643 02:51:45.928462 L2:00008067
644 02:51:45.928910 L3:14000000
645 02:51:45.933077 B2:00402000
646 02:51:45.933554 B1:e0f83180
647 02:51:45.934000
648 02:51:45.934446 TE: 58124
649 02:51:45.934887
650 02:51:45.938617 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 02:51:45.939114
652 02:51:45.939570 Board ID = 1
653 02:51:45.944364 Set A53 clk to 24M
654 02:51:45.944851 Set A73 clk to 24M
655 02:51:45.945300 Set clk81 to 24M
656 02:51:45.949931 A53 clk: 1200 MHz
657 02:51:45.950403 A73 clk: 1200 MHz
658 02:51:45.950850 CLK81: 166.6M
659 02:51:45.951293 smccc: 00012a92
660 02:51:45.955375 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 02:51:45.961095 board id: 1
662 02:51:45.967077 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 02:51:45.977455 fw parse done
664 02:51:45.983387 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 02:51:46.026026 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 02:51:46.036925 PIEI prepare done
667 02:51:46.037436 fastboot data load
668 02:51:46.037901 fastboot data verify
669 02:51:46.042599 verify result: 266
670 02:51:46.048214 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 02:51:46.048706 LPDDR4 probe
672 02:51:46.049162 ddr clk to 1584MHz
673 02:51:46.056198 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 02:51:46.093416
675 02:51:46.093942 dmc_version 0001
676 02:51:46.100088 Check phy result
677 02:51:46.105982 INFO : End of CA training
678 02:51:46.106481 INFO : End of initialization
679 02:51:46.111568 INFO : Training has run successfully!
680 02:51:46.112095 Check phy result
681 02:51:46.117218 INFO : End of initialization
682 02:51:46.117710 INFO : End of read enable training
683 02:51:46.122740 INFO : End of fine write leveling
684 02:51:46.128356 INFO : End of Write leveling coarse delay
685 02:51:46.128847 INFO : Training has run successfully!
686 02:51:46.129302 Check phy result
687 02:51:46.133940 INFO : End of initialization
688 02:51:46.134423 INFO : End of read dq deskew training
689 02:51:46.139550 INFO : End of MPR read delay center optimization
690 02:51:46.145211 INFO : End of write delay center optimization
691 02:51:46.150747 INFO : End of read delay center optimization
692 02:51:46.151221 INFO : End of max read latency training
693 02:51:46.156341 INFO : Training has run successfully!
694 02:51:46.156824 1D training succeed
695 02:51:46.165548 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 02:51:46.213112 Check phy result
697 02:51:46.213636 INFO : End of initialization
698 02:51:46.234753 INFO : End of 2D read delay Voltage center optimization
699 02:51:46.254850 INFO : End of 2D read delay Voltage center optimization
700 02:51:46.306742 INFO : End of 2D write delay Voltage center optimization
701 02:51:46.356019 INFO : End of 2D write delay Voltage center optimization
702 02:51:46.361560 INFO : Training has run successfully!
703 02:51:46.362043
704 02:51:46.362504 channel==0
705 02:51:46.367265 RxClkDly_Margin_A0==88 ps 9
706 02:51:46.367747 TxDqDly_Margin_A0==98 ps 10
707 02:51:46.372768 RxClkDly_Margin_A1==88 ps 9
708 02:51:46.373254 TxDqDly_Margin_A1==88 ps 9
709 02:51:46.373713 TrainedVREFDQ_A0==74
710 02:51:46.378372 TrainedVREFDQ_A1==74
711 02:51:46.378858 VrefDac_Margin_A0==25
712 02:51:46.379308 DeviceVref_Margin_A0==40
713 02:51:46.383949 VrefDac_Margin_A1==25
714 02:51:46.384456 DeviceVref_Margin_A1==40
715 02:51:46.384914
716 02:51:46.385361
717 02:51:46.385803 channel==1
718 02:51:46.389563 RxClkDly_Margin_A0==98 ps 10
719 02:51:46.390043 TxDqDly_Margin_A0==98 ps 10
720 02:51:46.395241 RxClkDly_Margin_A1==98 ps 10
721 02:51:46.395720 TxDqDly_Margin_A1==88 ps 9
722 02:51:46.400782 TrainedVREFDQ_A0==77
723 02:51:46.401342 TrainedVREFDQ_A1==77
724 02:51:46.401816 VrefDac_Margin_A0==23
725 02:51:46.406358 DeviceVref_Margin_A0==37
726 02:51:46.406851 VrefDac_Margin_A1==22
727 02:51:46.411964 DeviceVref_Margin_A1==37
728 02:51:46.412502
729 02:51:46.412962 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 02:51:46.413410
731 02:51:46.445573 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
732 02:51:46.446112 2D training succeed
733 02:51:46.451264 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 02:51:46.456791 auto size-- 65535DDR cs0 size: 2048MB
735 02:51:46.457281 DDR cs1 size: 2048MB
736 02:51:46.462382 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 02:51:46.462863 cs0 DataBus test pass
738 02:51:46.468012 cs1 DataBus test pass
739 02:51:46.468503 cs0 AddrBus test pass
740 02:51:46.468955 cs1 AddrBus test pass
741 02:51:46.469439
742 02:51:46.473572 100bdlr_step_size ps== 420
743 02:51:46.474075 result report
744 02:51:46.479294 boot times 0Enable ddr reg access
745 02:51:46.484501 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 02:51:46.498072 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 02:51:47.070215 0.0;M3 CHK:0;cm4_sp_mode 0
748 02:51:47.070837 MVN_1=0x00000000
749 02:51:47.075581 MVN_2=0x00000000
750 02:51:47.081427 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 02:51:47.081978 OPS=0x10
752 02:51:47.082423 ring efuse init
753 02:51:47.082852 chipver efuse init
754 02:51:47.086914 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 02:51:47.092487 [0.018961 Inits done]
756 02:51:47.092962 secure task start!
757 02:51:47.093399 high task start!
758 02:51:47.097057 low task start!
759 02:51:47.097532 run into bl31
760 02:51:47.103651 NOTICE: BL31: v1.3(release):4fc40b1
761 02:51:47.111451 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 02:51:47.111929 NOTICE: BL31: G12A normal boot!
763 02:51:47.136862 NOTICE: BL31: BL33 decompress pass
764 02:51:47.142545 ERROR: Error initializing runtime service opteed_fast
765 02:51:48.375659
766 02:51:48.376388
767 02:51:48.383861 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 02:51:48.384423
769 02:51:48.384909 Model: Libre Computer AML-A311D-CC Alta
770 02:51:48.592406 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 02:51:48.615619 DRAM: 2 GiB (effective 3.8 GiB)
772 02:51:48.758711 Core: 408 devices, 31 uclasses, devicetree: separate
773 02:51:48.764624 WDT: Not starting watchdog@f0d0
774 02:51:48.796758 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 02:51:48.809240 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 02:51:48.814206 ** Bad device specification mmc 0 **
777 02:51:48.824555 Card did not respond to voltage select! : -110
778 02:51:48.832207 ** Bad device specification mmc 0 **
779 02:51:48.832718 Couldn't find partition mmc 0
780 02:51:48.840548 Card did not respond to voltage select! : -110
781 02:51:48.846053 ** Bad device specification mmc 0 **
782 02:51:48.846555 Couldn't find partition mmc 0
783 02:51:48.851129 Error: could not access storage.
784 02:51:49.193582 Net: eth0: ethernet@ff3f0000
785 02:51:49.194190 starting USB...
786 02:51:49.445477 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 02:51:49.446127 Starting the controller
788 02:51:49.452352 USB XHCI 1.10
789 02:51:51.617712 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 02:51:51.618346 bl2_stage_init 0x01
791 02:51:51.618780 bl2_stage_init 0x81
792 02:51:51.623353 hw id: 0x0000 - pwm id 0x01
793 02:51:51.623824 bl2_stage_init 0xc1
794 02:51:51.624294 bl2_stage_init 0x02
795 02:51:51.624708
796 02:51:51.628938 L0:00000000
797 02:51:51.629402 L1:20000703
798 02:51:51.629821 L2:00008067
799 02:51:51.630229 L3:14000000
800 02:51:51.634507 B2:00402000
801 02:51:51.634964 B1:e0f83180
802 02:51:51.635378
803 02:51:51.635785 TE: 58167
804 02:51:51.636236
805 02:51:51.640135 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 02:51:51.640597
807 02:51:51.641010 Board ID = 1
808 02:51:51.645615 Set A53 clk to 24M
809 02:51:51.646076 Set A73 clk to 24M
810 02:51:51.646490 Set clk81 to 24M
811 02:51:51.651246 A53 clk: 1200 MHz
812 02:51:51.651703 A73 clk: 1200 MHz
813 02:51:51.652146 CLK81: 166.6M
814 02:51:51.652553 smccc: 00012abe
815 02:51:51.656822 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 02:51:51.662424 board id: 1
817 02:51:51.668307 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 02:51:51.678924 fw parse done
819 02:51:51.684949 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 02:51:51.727552 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 02:51:51.738482 PIEI prepare done
822 02:51:51.738959 fastboot data load
823 02:51:51.739381 fastboot data verify
824 02:51:51.744244 verify result: 266
825 02:51:51.749719 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 02:51:51.750212 LPDDR4 probe
827 02:51:51.750629 ddr clk to 1584MHz
828 02:51:51.757636 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 02:51:51.795009
830 02:51:51.795539 dmc_version 0001
831 02:51:51.801678 Check phy result
832 02:51:51.807484 INFO : End of CA training
833 02:51:51.807963 INFO : End of initialization
834 02:51:51.813137 INFO : Training has run successfully!
835 02:51:51.813616 Check phy result
836 02:51:51.818660 INFO : End of initialization
837 02:51:51.819126 INFO : End of read enable training
838 02:51:51.824295 INFO : End of fine write leveling
839 02:51:51.829924 INFO : End of Write leveling coarse delay
840 02:51:51.830406 INFO : Training has run successfully!
841 02:51:51.830821 Check phy result
842 02:51:51.835504 INFO : End of initialization
843 02:51:51.836016 INFO : End of read dq deskew training
844 02:51:51.841180 INFO : End of MPR read delay center optimization
845 02:51:51.846708 INFO : End of write delay center optimization
846 02:51:51.852341 INFO : End of read delay center optimization
847 02:51:51.852987 INFO : End of max read latency training
848 02:51:51.857937 INFO : Training has run successfully!
849 02:51:51.858413 1D training succeed
850 02:51:51.867064 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 02:51:51.914740 Check phy result
852 02:51:51.915287 INFO : End of initialization
853 02:51:51.937322 INFO : End of 2D read delay Voltage center optimization
854 02:51:51.957594 INFO : End of 2D read delay Voltage center optimization
855 02:51:52.009602 INFO : End of 2D write delay Voltage center optimization
856 02:51:52.059015 INFO : End of 2D write delay Voltage center optimization
857 02:51:52.064504 INFO : Training has run successfully!
858 02:51:52.064993
859 02:51:52.065415 channel==0
860 02:51:52.070116 RxClkDly_Margin_A0==88 ps 9
861 02:51:52.070613 TxDqDly_Margin_A0==98 ps 10
862 02:51:52.073631 RxClkDly_Margin_A1==88 ps 9
863 02:51:52.074128 TxDqDly_Margin_A1==88 ps 9
864 02:51:52.079352 TrainedVREFDQ_A0==74
865 02:51:52.079869 TrainedVREFDQ_A1==74
866 02:51:52.080355 VrefDac_Margin_A0==25
867 02:51:52.084743 DeviceVref_Margin_A0==40
868 02:51:52.085223 VrefDac_Margin_A1==24
869 02:51:52.090369 DeviceVref_Margin_A1==40
870 02:51:52.090847
871 02:51:52.091244
872 02:51:52.091636 channel==1
873 02:51:52.092071 RxClkDly_Margin_A0==98 ps 10
874 02:51:52.095971 TxDqDly_Margin_A0==88 ps 9
875 02:51:52.096479 RxClkDly_Margin_A1==98 ps 10
876 02:51:52.101604 TxDqDly_Margin_A1==88 ps 9
877 02:51:52.102089 TrainedVREFDQ_A0==77
878 02:51:52.102491 TrainedVREFDQ_A1==77
879 02:51:52.107142 VrefDac_Margin_A0==22
880 02:51:52.107618 DeviceVref_Margin_A0==37
881 02:51:52.112701 VrefDac_Margin_A1==22
882 02:51:52.113166 DeviceVref_Margin_A1==37
883 02:51:52.113561
884 02:51:52.118342 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 02:51:52.118819
886 02:51:52.146319 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000017 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000018 dram_vref_reg_value 0x 00000060
887 02:51:52.151873 2D training succeed
888 02:51:52.157420 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 02:51:52.157898 auto size-- 65535DDR cs0 size: 2048MB
890 02:51:52.163028 DDR cs1 size: 2048MB
891 02:51:52.163492 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 02:51:52.168617 cs0 DataBus test pass
893 02:51:52.169080 cs1 DataBus test pass
894 02:51:52.169475 cs0 AddrBus test pass
895 02:51:52.174206 cs1 AddrBus test pass
896 02:51:52.174663
897 02:51:52.175064 100bdlr_step_size ps== 420
898 02:51:52.175462 result report
899 02:51:52.179777 boot times 0Enable ddr reg access
900 02:51:52.187279 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 02:51:52.200719 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 02:51:52.773876 0.0;M3 CHK:0;cm4_sp_mode 0
903 02:51:52.774544 MVN_1=0x00000000
904 02:51:52.779372 MVN_2=0x00000000
905 02:51:52.785072 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 02:51:52.785578 OPS=0x10
907 02:51:52.786002 ring efuse init
908 02:51:52.786413 chipver efuse init
909 02:51:52.790623 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 02:51:52.796236 [0.018960 Inits done]
911 02:51:52.796704 secure task start!
912 02:51:52.797120 high task start!
913 02:51:52.800786 low task start!
914 02:51:52.801242 run into bl31
915 02:51:52.807449 NOTICE: BL31: v1.3(release):4fc40b1
916 02:51:52.815262 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 02:51:52.815722 NOTICE: BL31: G12A normal boot!
918 02:51:52.841165 NOTICE: BL31: BL33 decompress pass
919 02:51:52.846742 ERROR: Error initializing runtime service opteed_fast
920 02:51:54.079689
921 02:51:54.080370
922 02:51:54.088155 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 02:51:54.088668
924 02:51:54.089100 Model: Libre Computer AML-A311D-CC Alta
925 02:51:54.296547 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 02:51:54.319849 DRAM: 2 GiB (effective 3.8 GiB)
927 02:51:54.462892 Core: 408 devices, 31 uclasses, devicetree: separate
928 02:51:54.468712 WDT: Not starting watchdog@f0d0
929 02:51:54.501068 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 02:51:54.513480 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 02:51:54.518479 ** Bad device specification mmc 0 **
932 02:51:54.528779 Card did not respond to voltage select! : -110
933 02:51:54.536548 ** Bad device specification mmc 0 **
934 02:51:54.536973 Couldn't find partition mmc 0
935 02:51:54.544796 Card did not respond to voltage select! : -110
936 02:51:54.550290 ** Bad device specification mmc 0 **
937 02:51:54.550812 Couldn't find partition mmc 0
938 02:51:54.555349 Error: could not access storage.
939 02:51:54.898962 Net: eth0: ethernet@ff3f0000
940 02:51:54.899765 starting USB...
941 02:51:55.150820 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 02:51:55.151548 Starting the controller
943 02:51:55.157753 USB XHCI 1.10
944 02:51:56.711731 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 02:51:56.719975 scanning usb for storage devices... 0 Storage Device(s) found
947 02:51:56.771851 Hit any key to stop autoboot: 1
948 02:51:56.773001 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
949 02:51:56.773827 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
950 02:51:56.774441 Setting prompt string to ['=>']
951 02:51:56.775071 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
952 02:51:56.787304 0
953 02:51:56.788235 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 02:51:56.788734 Sending with 10 millisecond of delay
956 02:51:57.924055 => setenv autoload no
957 02:51:57.934891 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
958 02:51:57.939792 setenv autoload no
959 02:51:57.940550 Sending with 10 millisecond of delay
961 02:51:59.737901 => setenv initrd_high 0xffffffff
962 02:51:59.748693 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
963 02:51:59.749550 setenv initrd_high 0xffffffff
964 02:51:59.750269 Sending with 10 millisecond of delay
966 02:52:01.366806 => setenv fdt_high 0xffffffff
967 02:52:01.377591 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
968 02:52:01.378419 setenv fdt_high 0xffffffff
969 02:52:01.379131 Sending with 10 millisecond of delay
971 02:52:01.671093 => dhcp
972 02:52:01.681881 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
973 02:52:01.682709 dhcp
974 02:52:01.683149 Speed: 1000, full duplex
975 02:52:01.683564 BOOTP broadcast 1
976 02:52:01.851779 DHCP client bound to address 192.168.6.27 (170 ms)
977 02:52:01.852664 Sending with 10 millisecond of delay
979 02:52:03.529329 => setenv serverip 192.168.6.2
980 02:52:03.540155 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
981 02:52:03.541080 setenv serverip 192.168.6.2
982 02:52:03.541816 Sending with 10 millisecond of delay
984 02:52:07.265704 => tftpboot 0x01080000 956999/tftp-deploy-7fo83oil/kernel/uImage
985 02:52:07.276501 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
986 02:52:07.277305 tftpboot 0x01080000 956999/tftp-deploy-7fo83oil/kernel/uImage
987 02:52:07.277758 Speed: 1000, full duplex
988 02:52:07.278178 Using ethernet@ff3f0000 device
989 02:52:07.279412 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
990 02:52:07.284808 Filename '956999/tftp-deploy-7fo83oil/kernel/uImage'.
991 02:52:07.288766 Load address: 0x1080000
992 02:52:09.610696 Loading: *################################################## 36.1 MiB
993 02:52:09.611518 15.5 MiB/s
994 02:52:09.612256 done
995 02:52:09.615009 Bytes transferred = 37880384 (2420240 hex)
996 02:52:09.615734 Sending with 10 millisecond of delay
998 02:52:14.302304 => tftpboot 0x08000000 956999/tftp-deploy-7fo83oil/ramdisk/ramdisk.cpio.gz.uboot
999 02:52:14.313105 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1000 02:52:14.313963 tftpboot 0x08000000 956999/tftp-deploy-7fo83oil/ramdisk/ramdisk.cpio.gz.uboot
1001 02:52:14.314441 Speed: 1000, full duplex
1002 02:52:14.314867 Using ethernet@ff3f0000 device
1003 02:52:14.315871 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1004 02:52:14.327633 Filename '956999/tftp-deploy-7fo83oil/ramdisk/ramdisk.cpio.gz.uboot'.
1005 02:52:14.328175 Load address: 0x8000000
1006 02:52:19.226181 Loading: *## UDP wrong checksum 000000ff 00008271
1007 02:52:19.267467 UDP wrong checksum 000000ff 00000864
1008 02:52:21.594316 T ############################################### UDP wrong checksum 00000005 0000f819
1009 02:52:26.596651 T UDP wrong checksum 00000005 0000f819
1010 02:52:36.598691 T T UDP wrong checksum 00000005 0000f819
1011 02:52:56.602707 T T T T UDP wrong checksum 00000005 0000f819
1012 02:53:11.606838 T T
1013 02:53:11.607528 Retry count exceeded; starting again
1015 02:53:11.609125 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1018 02:53:11.611216 end: 2.4 uboot-commands (duration 00:01:47) [common]
1020 02:53:11.612812 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1022 02:53:11.613933 end: 2 uboot-action (duration 00:01:47) [common]
1024 02:53:11.615592 Cleaning after the job
1025 02:53:11.616214 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/ramdisk
1026 02:53:11.617575 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/kernel
1027 02:53:11.660486 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/dtb
1028 02:53:11.661707 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/nfsrootfs
1029 02:53:11.958863 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/956999/tftp-deploy-7fo83oil/modules
1030 02:53:11.979047 start: 4.1 power-off (timeout 00:00:30) [common]
1031 02:53:11.979683 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1032 02:53:12.012829 >> OK - accepted request
1033 02:53:12.014951 Returned 0 in 0 seconds
1034 02:53:12.115714 end: 4.1 power-off (duration 00:00:00) [common]
1036 02:53:12.116739 start: 4.2 read-feedback (timeout 00:10:00) [common]
1037 02:53:12.117391 Listened to connection for namespace 'common' for up to 1s
1038 02:53:13.118334 Finalising connection for namespace 'common'
1039 02:53:13.118816 Disconnecting from shell: Finalise
1040 02:53:13.119103 =>
1041 02:53:13.219762 end: 4.2 read-feedback (duration 00:00:01) [common]
1042 02:53:13.220136 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/956999
1043 02:53:15.686967 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/956999
1044 02:53:15.687586 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.