Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 03:01:42.308446 lava-dispatcher, installed at version: 2024.01
2 03:01:42.309231 start: 0 validate
3 03:01:42.309701 Start time: 2024-11-08 03:01:42.309671+00:00 (UTC)
4 03:01:42.310238 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:01:42.310776 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 03:01:42.355852 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:01:42.356415 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 03:01:42.391667 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:01:42.392465 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 03:01:42.424948 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:01:42.425487 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 03:01:42.464357 validate duration: 0.15
14 03:01:42.465390 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 03:01:42.465814 start: 1.1 download-retry (timeout 00:10:00) [common]
16 03:01:42.466197 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 03:01:42.466898 Not decompressing ramdisk as can be used compressed.
18 03:01:42.467436 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 03:01:42.467739 saving as /var/lib/lava/dispatcher/tmp/957096/tftp-deploy-ttofvnyy/ramdisk/rootfs.cpio.gz
20 03:01:42.468092 total size: 47897469 (45 MB)
21 03:01:42.505580 progress 0 % (0 MB)
22 03:01:42.536588 progress 5 % (2 MB)
23 03:01:42.567459 progress 10 % (4 MB)
24 03:01:42.598009 progress 15 % (6 MB)
25 03:01:42.628534 progress 20 % (9 MB)
26 03:01:42.658709 progress 25 % (11 MB)
27 03:01:42.688770 progress 30 % (13 MB)
28 03:01:42.718936 progress 35 % (16 MB)
29 03:01:42.749352 progress 40 % (18 MB)
30 03:01:42.779744 progress 45 % (20 MB)
31 03:01:42.810022 progress 50 % (22 MB)
32 03:01:42.840557 progress 55 % (25 MB)
33 03:01:42.871389 progress 60 % (27 MB)
34 03:01:42.901542 progress 65 % (29 MB)
35 03:01:42.932066 progress 70 % (32 MB)
36 03:01:42.962457 progress 75 % (34 MB)
37 03:01:42.992526 progress 80 % (36 MB)
38 03:01:43.023260 progress 85 % (38 MB)
39 03:01:43.054034 progress 90 % (41 MB)
40 03:01:43.084000 progress 95 % (43 MB)
41 03:01:43.113380 progress 100 % (45 MB)
42 03:01:43.114131 45 MB downloaded in 0.65 s (70.71 MB/s)
43 03:01:43.114706 end: 1.1.1 http-download (duration 00:00:01) [common]
45 03:01:43.115634 end: 1.1 download-retry (duration 00:00:01) [common]
46 03:01:43.115954 start: 1.2 download-retry (timeout 00:09:59) [common]
47 03:01:43.116273 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 03:01:43.116750 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/gcc-12/kernel/Image
49 03:01:43.117016 saving as /var/lib/lava/dispatcher/tmp/957096/tftp-deploy-ttofvnyy/kernel/Image
50 03:01:43.117237 total size: 45713920 (43 MB)
51 03:01:43.117461 No compression specified
52 03:01:43.157958 progress 0 % (0 MB)
53 03:01:43.186783 progress 5 % (2 MB)
54 03:01:43.215780 progress 10 % (4 MB)
55 03:01:43.244968 progress 15 % (6 MB)
56 03:01:43.273815 progress 20 % (8 MB)
57 03:01:43.302476 progress 25 % (10 MB)
58 03:01:43.331518 progress 30 % (13 MB)
59 03:01:43.360454 progress 35 % (15 MB)
60 03:01:43.389664 progress 40 % (17 MB)
61 03:01:43.418842 progress 45 % (19 MB)
62 03:01:43.447916 progress 50 % (21 MB)
63 03:01:43.476829 progress 55 % (24 MB)
64 03:01:43.506244 progress 60 % (26 MB)
65 03:01:43.535135 progress 65 % (28 MB)
66 03:01:43.564240 progress 70 % (30 MB)
67 03:01:43.593681 progress 75 % (32 MB)
68 03:01:43.622749 progress 80 % (34 MB)
69 03:01:43.651156 progress 85 % (37 MB)
70 03:01:43.680179 progress 90 % (39 MB)
71 03:01:43.709595 progress 95 % (41 MB)
72 03:01:43.737843 progress 100 % (43 MB)
73 03:01:43.738364 43 MB downloaded in 0.62 s (70.19 MB/s)
74 03:01:43.738848 end: 1.2.1 http-download (duration 00:00:01) [common]
76 03:01:43.739671 end: 1.2 download-retry (duration 00:00:01) [common]
77 03:01:43.739951 start: 1.3 download-retry (timeout 00:09:59) [common]
78 03:01:43.740250 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 03:01:43.740726 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 03:01:43.741004 saving as /var/lib/lava/dispatcher/tmp/957096/tftp-deploy-ttofvnyy/dtb/meson-g12b-a311d-libretech-cc.dtb
81 03:01:43.741215 total size: 54703 (0 MB)
82 03:01:43.741426 No compression specified
83 03:01:43.781848 progress 59 % (0 MB)
84 03:01:43.782703 progress 100 % (0 MB)
85 03:01:43.783247 0 MB downloaded in 0.04 s (1.24 MB/s)
86 03:01:43.783710 end: 1.3.1 http-download (duration 00:00:00) [common]
88 03:01:43.784581 end: 1.3 download-retry (duration 00:00:00) [common]
89 03:01:43.784849 start: 1.4 download-retry (timeout 00:09:59) [common]
90 03:01:43.785114 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 03:01:43.785584 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/gcc-12/modules.tar.xz
92 03:01:43.785832 saving as /var/lib/lava/dispatcher/tmp/957096/tftp-deploy-ttofvnyy/modules/modules.tar
93 03:01:43.786040 total size: 11613712 (11 MB)
94 03:01:43.786253 Using unxz to decompress xz
95 03:01:43.825412 progress 0 % (0 MB)
96 03:01:43.891042 progress 5 % (0 MB)
97 03:01:43.964974 progress 10 % (1 MB)
98 03:01:44.060432 progress 15 % (1 MB)
99 03:01:44.152196 progress 20 % (2 MB)
100 03:01:44.232631 progress 25 % (2 MB)
101 03:01:44.307603 progress 30 % (3 MB)
102 03:01:44.385190 progress 35 % (3 MB)
103 03:01:44.457328 progress 40 % (4 MB)
104 03:01:44.533409 progress 45 % (5 MB)
105 03:01:44.617341 progress 50 % (5 MB)
106 03:01:44.696192 progress 55 % (6 MB)
107 03:01:44.783687 progress 60 % (6 MB)
108 03:01:44.865019 progress 65 % (7 MB)
109 03:01:44.945711 progress 70 % (7 MB)
110 03:01:45.025236 progress 75 % (8 MB)
111 03:01:45.109211 progress 80 % (8 MB)
112 03:01:45.189490 progress 85 % (9 MB)
113 03:01:45.268168 progress 90 % (9 MB)
114 03:01:45.345820 progress 95 % (10 MB)
115 03:01:45.422462 progress 100 % (11 MB)
116 03:01:45.434273 11 MB downloaded in 1.65 s (6.72 MB/s)
117 03:01:45.434887 end: 1.4.1 http-download (duration 00:00:02) [common]
119 03:01:45.435727 end: 1.4 download-retry (duration 00:00:02) [common]
120 03:01:45.436049 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 03:01:45.436603 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 03:01:45.437097 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 03:01:45.437602 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 03:01:45.438583 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd
125 03:01:45.439429 makedir: /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin
126 03:01:45.440099 makedir: /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/tests
127 03:01:45.440730 makedir: /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/results
128 03:01:45.441346 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-add-keys
129 03:01:45.442265 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-add-sources
130 03:01:45.443193 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-background-process-start
131 03:01:45.444177 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-background-process-stop
132 03:01:45.445182 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-common-functions
133 03:01:45.446100 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-echo-ipv4
134 03:01:45.447002 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-install-packages
135 03:01:45.447890 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-installed-packages
136 03:01:45.448870 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-os-build
137 03:01:45.449781 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-probe-channel
138 03:01:45.450665 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-probe-ip
139 03:01:45.451585 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-target-ip
140 03:01:45.452606 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-target-mac
141 03:01:45.453522 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-target-storage
142 03:01:45.454435 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-test-case
143 03:01:45.455360 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-test-event
144 03:01:45.456333 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-test-feedback
145 03:01:45.457250 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-test-raise
146 03:01:45.458130 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-test-reference
147 03:01:45.459050 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-test-runner
148 03:01:45.459971 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-test-set
149 03:01:45.460948 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-test-shell
150 03:01:45.461896 Updating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-install-packages (oe)
151 03:01:45.462866 Updating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/bin/lava-installed-packages (oe)
152 03:01:45.463691 Creating /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/environment
153 03:01:45.464452 LAVA metadata
154 03:01:45.464950 - LAVA_JOB_ID=957096
155 03:01:45.465382 - LAVA_DISPATCHER_IP=192.168.6.2
156 03:01:45.466039 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 03:01:45.467821 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 03:01:45.468464 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 03:01:45.468880 skipped lava-vland-overlay
160 03:01:45.469369 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 03:01:45.469875 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 03:01:45.470297 skipped lava-multinode-overlay
163 03:01:45.470782 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 03:01:45.471284 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 03:01:45.471756 Loading test definitions
166 03:01:45.472356 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 03:01:45.472802 Using /lava-957096 at stage 0
168 03:01:45.474931 uuid=957096_1.5.2.4.1 testdef=None
169 03:01:45.475516 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 03:01:45.476069 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 03:01:45.477943 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 03:01:45.478780 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 03:01:45.480959 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 03:01:45.481824 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 03:01:45.483920 runner path: /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/0/tests/0_igt-gpu-panfrost test_uuid 957096_1.5.2.4.1
178 03:01:45.484561 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 03:01:45.485404 Creating lava-test-runner.conf files
181 03:01:45.485615 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/957096/lava-overlay-mpv984cd/lava-957096/0 for stage 0
182 03:01:45.485958 - 0_igt-gpu-panfrost
183 03:01:45.486324 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 03:01:45.486617 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 03:01:45.510312 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 03:01:45.510741 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 03:01:45.511016 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 03:01:45.511291 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 03:01:45.511564 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 03:01:52.425493 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 03:01:52.425966 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 03:01:52.426216 extracting modules file /var/lib/lava/dispatcher/tmp/957096/tftp-deploy-ttofvnyy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/957096/extract-overlay-ramdisk-p610zedo/ramdisk
193 03:01:53.838662 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 03:01:53.839141 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 03:01:53.839421 [common] Applying overlay /var/lib/lava/dispatcher/tmp/957096/compress-overlay-6ldlrz8y/overlay-1.5.2.5.tar.gz to ramdisk
196 03:01:53.839637 [common] Applying overlay /var/lib/lava/dispatcher/tmp/957096/compress-overlay-6ldlrz8y/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/957096/extract-overlay-ramdisk-p610zedo/ramdisk
197 03:01:53.869528 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 03:01:53.869897 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 03:01:53.870169 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 03:01:53.870394 Converting downloaded kernel to a uImage
201 03:01:53.870699 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/957096/tftp-deploy-ttofvnyy/kernel/Image /var/lib/lava/dispatcher/tmp/957096/tftp-deploy-ttofvnyy/kernel/uImage
202 03:01:54.439127 output: Image Name:
203 03:01:54.439540 output: Created: Fri Nov 8 03:01:53 2024
204 03:01:54.439749 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 03:01:54.439954 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 03:01:54.440199 output: Load Address: 01080000
207 03:01:54.440405 output: Entry Point: 01080000
208 03:01:54.440609 output:
209 03:01:54.440944 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 03:01:54.441211 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 03:01:54.441479 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 03:01:54.441734 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 03:01:54.441991 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 03:01:54.442245 Building ramdisk /var/lib/lava/dispatcher/tmp/957096/extract-overlay-ramdisk-p610zedo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/957096/extract-overlay-ramdisk-p610zedo/ramdisk
215 03:02:00.945867 >> 502412 blocks
216 03:02:21.648413 Adding RAMdisk u-boot header.
217 03:02:21.649112 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/957096/extract-overlay-ramdisk-p610zedo/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/957096/extract-overlay-ramdisk-p610zedo/ramdisk.cpio.gz.uboot
218 03:02:22.303848 output: Image Name:
219 03:02:22.304528 output: Created: Fri Nov 8 03:02:21 2024
220 03:02:22.304962 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 03:02:22.305381 output: Data Size: 65717031 Bytes = 64176.79 KiB = 62.67 MiB
222 03:02:22.305791 output: Load Address: 00000000
223 03:02:22.306196 output: Entry Point: 00000000
224 03:02:22.306596 output:
225 03:02:22.307597 rename /var/lib/lava/dispatcher/tmp/957096/extract-overlay-ramdisk-p610zedo/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/957096/tftp-deploy-ttofvnyy/ramdisk/ramdisk.cpio.gz.uboot
226 03:02:22.308384 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 03:02:22.308940 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 03:02:22.309474 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 03:02:22.309942 No LXC device requested
230 03:02:22.310452 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 03:02:22.310972 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 03:02:22.311471 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 03:02:22.311897 Checking files for TFTP limit of 4294967296 bytes.
234 03:02:22.314576 end: 1 tftp-deploy (duration 00:00:40) [common]
235 03:02:22.315158 start: 2 uboot-action (timeout 00:05:00) [common]
236 03:02:22.315693 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 03:02:22.316231 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 03:02:22.316755 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 03:02:22.317288 Using kernel file from prepare-kernel: 957096/tftp-deploy-ttofvnyy/kernel/uImage
240 03:02:22.317906 substitutions:
241 03:02:22.318325 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 03:02:22.318737 - {DTB_ADDR}: 0x01070000
243 03:02:22.319143 - {DTB}: 957096/tftp-deploy-ttofvnyy/dtb/meson-g12b-a311d-libretech-cc.dtb
244 03:02:22.319547 - {INITRD}: 957096/tftp-deploy-ttofvnyy/ramdisk/ramdisk.cpio.gz.uboot
245 03:02:22.319947 - {KERNEL_ADDR}: 0x01080000
246 03:02:22.320379 - {KERNEL}: 957096/tftp-deploy-ttofvnyy/kernel/uImage
247 03:02:22.320779 - {LAVA_MAC}: None
248 03:02:22.321238 - {PRESEED_CONFIG}: None
249 03:02:22.321645 - {PRESEED_LOCAL}: None
250 03:02:22.322043 - {RAMDISK_ADDR}: 0x08000000
251 03:02:22.322437 - {RAMDISK}: 957096/tftp-deploy-ttofvnyy/ramdisk/ramdisk.cpio.gz.uboot
252 03:02:22.322835 - {ROOT_PART}: None
253 03:02:22.323228 - {ROOT}: None
254 03:02:22.323621 - {SERVER_IP}: 192.168.6.2
255 03:02:22.324047 - {TEE_ADDR}: 0x83000000
256 03:02:22.324453 - {TEE}: None
257 03:02:22.324852 Parsed boot commands:
258 03:02:22.325236 - setenv autoload no
259 03:02:22.325631 - setenv initrd_high 0xffffffff
260 03:02:22.326024 - setenv fdt_high 0xffffffff
261 03:02:22.326414 - dhcp
262 03:02:22.326808 - setenv serverip 192.168.6.2
263 03:02:22.327199 - tftpboot 0x01080000 957096/tftp-deploy-ttofvnyy/kernel/uImage
264 03:02:22.327593 - tftpboot 0x08000000 957096/tftp-deploy-ttofvnyy/ramdisk/ramdisk.cpio.gz.uboot
265 03:02:22.328005 - tftpboot 0x01070000 957096/tftp-deploy-ttofvnyy/dtb/meson-g12b-a311d-libretech-cc.dtb
266 03:02:22.328405 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 03:02:22.328800 - bootm 0x01080000 0x08000000 0x01070000
268 03:02:22.329309 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 03:02:22.330836 start: 2.3 connect-device (timeout 00:05:00) [common]
271 03:02:22.331284 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 03:02:22.346197 Setting prompt string to ['lava-test: # ']
273 03:02:22.347680 end: 2.3 connect-device (duration 00:00:00) [common]
274 03:02:22.348340 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 03:02:22.348904 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 03:02:22.349454 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 03:02:22.350603 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 03:02:22.387714 >> OK - accepted request
279 03:02:22.389974 Returned 0 in 0 seconds
280 03:02:22.491161 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 03:02:22.492906 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 03:02:22.493484 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 03:02:22.493998 Setting prompt string to ['Hit any key to stop autoboot']
285 03:02:22.494468 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 03:02:22.496107 Trying 192.168.56.21...
287 03:02:22.496602 Connected to conserv1.
288 03:02:22.497038 Escape character is '^]'.
289 03:02:22.497468
290 03:02:22.497906 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 03:02:22.498356
292 03:02:33.920058 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 03:02:33.920710 bl2_stage_init 0x01
294 03:02:33.921171 bl2_stage_init 0x81
295 03:02:33.925412 hw id: 0x0000 - pwm id 0x01
296 03:02:33.925931 bl2_stage_init 0xc1
297 03:02:33.926348 bl2_stage_init 0x02
298 03:02:33.926750
299 03:02:33.931039 L0:00000000
300 03:02:33.931479 L1:20000703
301 03:02:33.931871 L2:00008067
302 03:02:33.932294 L3:14000000
303 03:02:33.933930 B2:00402000
304 03:02:33.934349 B1:e0f83180
305 03:02:33.934737
306 03:02:33.935124 TE: 58159
307 03:02:33.935512
308 03:02:33.945099 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 03:02:33.945527
310 03:02:33.945918 Board ID = 1
311 03:02:33.946302 Set A53 clk to 24M
312 03:02:33.946684 Set A73 clk to 24M
313 03:02:33.950859 Set clk81 to 24M
314 03:02:33.951274 A53 clk: 1200 MHz
315 03:02:33.951661 A73 clk: 1200 MHz
316 03:02:33.954292 CLK81: 166.6M
317 03:02:33.954704 smccc: 00012ab5
318 03:02:33.959884 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 03:02:33.965535 board id: 1
320 03:02:33.970545 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 03:02:33.980994 fw parse done
322 03:02:33.986928 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 03:02:34.029589 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 03:02:34.040525 PIEI prepare done
325 03:02:34.040942 fastboot data load
326 03:02:34.041337 fastboot data verify
327 03:02:34.046100 verify result: 266
328 03:02:34.051785 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 03:02:34.052255 LPDDR4 probe
330 03:02:34.052685 ddr clk to 1584MHz
331 03:02:34.059703 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 03:02:34.096944
333 03:02:34.097383 dmc_version 0001
334 03:02:34.103657 Check phy result
335 03:02:34.109540 INFO : End of CA training
336 03:02:34.109967 INFO : End of initialization
337 03:02:34.115121 INFO : Training has run successfully!
338 03:02:34.115550 Check phy result
339 03:02:34.120808 INFO : End of initialization
340 03:02:34.121247 INFO : End of read enable training
341 03:02:34.126312 INFO : End of fine write leveling
342 03:02:34.131902 INFO : End of Write leveling coarse delay
343 03:02:34.132359 INFO : Training has run successfully!
344 03:02:34.132771 Check phy result
345 03:02:34.137439 INFO : End of initialization
346 03:02:34.137868 INFO : End of read dq deskew training
347 03:02:34.143086 INFO : End of MPR read delay center optimization
348 03:02:34.148849 INFO : End of write delay center optimization
349 03:02:34.154342 INFO : End of read delay center optimization
350 03:02:34.154763 INFO : End of max read latency training
351 03:02:34.159885 INFO : Training has run successfully!
352 03:02:34.160344 1D training succeed
353 03:02:34.169098 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 03:02:34.216641 Check phy result
355 03:02:34.217068 INFO : End of initialization
356 03:02:34.239262 INFO : End of 2D read delay Voltage center optimization
357 03:02:34.259506 INFO : End of 2D read delay Voltage center optimization
358 03:02:34.311627 INFO : End of 2D write delay Voltage center optimization
359 03:02:34.361024 INFO : End of 2D write delay Voltage center optimization
360 03:02:34.366522 INFO : Training has run successfully!
361 03:02:34.366946
362 03:02:34.367352 channel==0
363 03:02:34.372135 RxClkDly_Margin_A0==88 ps 9
364 03:02:34.372625 TxDqDly_Margin_A0==98 ps 10
365 03:02:34.377869 RxClkDly_Margin_A1==88 ps 9
366 03:02:34.378547 TxDqDly_Margin_A1==98 ps 10
367 03:02:34.379172 TrainedVREFDQ_A0==74
368 03:02:34.383480 TrainedVREFDQ_A1==74
369 03:02:34.383976 VrefDac_Margin_A0==25
370 03:02:34.384427 DeviceVref_Margin_A0==40
371 03:02:34.389030 VrefDac_Margin_A1==24
372 03:02:34.389458 DeviceVref_Margin_A1==40
373 03:02:34.389859
374 03:02:34.390264
375 03:02:34.394539 channel==1
376 03:02:34.394983 RxClkDly_Margin_A0==98 ps 10
377 03:02:34.395387 TxDqDly_Margin_A0==98 ps 10
378 03:02:34.400160 RxClkDly_Margin_A1==88 ps 9
379 03:02:34.400651 TxDqDly_Margin_A1==98 ps 10
380 03:02:34.406020 TrainedVREFDQ_A0==77
381 03:02:34.406513 TrainedVREFDQ_A1==78
382 03:02:34.406926 VrefDac_Margin_A0==22
383 03:02:34.411520 DeviceVref_Margin_A0==37
384 03:02:34.411963 VrefDac_Margin_A1==24
385 03:02:34.417057 DeviceVref_Margin_A1==36
386 03:02:34.417515
387 03:02:34.417929 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 03:02:34.422589
389 03:02:34.450567 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 03:02:34.451150 2D training succeed
391 03:02:34.456183 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 03:02:34.461922 auto size-- 65535DDR cs0 size: 2048MB
393 03:02:34.462373 DDR cs1 size: 2048MB
394 03:02:34.467400 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 03:02:34.467845 cs0 DataBus test pass
396 03:02:34.473007 cs1 DataBus test pass
397 03:02:34.473455 cs0 AddrBus test pass
398 03:02:34.473860 cs1 AddrBus test pass
399 03:02:34.474257
400 03:02:34.478608 100bdlr_step_size ps== 420
401 03:02:34.479070 result report
402 03:02:34.484190 boot times 0Enable ddr reg access
403 03:02:34.489649 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 03:02:34.503142 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 03:02:35.076376 0.0;M3 CHK:0;cm4_sp_mode 0
406 03:02:35.076978 MVN_1=0x00000000
407 03:02:35.081709 MVN_2=0x00000000
408 03:02:35.087492 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 03:02:35.087932 OPS=0x10
410 03:02:35.088395 ring efuse init
411 03:02:35.088803 chipver efuse init
412 03:02:35.095786 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 03:02:35.096259 [0.018961 Inits done]
414 03:02:35.096671 secure task start!
415 03:02:35.103291 high task start!
416 03:02:35.103721 low task start!
417 03:02:35.104156 run into bl31
418 03:02:35.109791 NOTICE: BL31: v1.3(release):4fc40b1
419 03:02:35.117652 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 03:02:35.118085 NOTICE: BL31: G12A normal boot!
421 03:02:35.143071 NOTICE: BL31: BL33 decompress pass
422 03:02:35.148792 ERROR: Error initializing runtime service opteed_fast
423 03:02:36.381750
424 03:02:36.382411
425 03:02:36.390136 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 03:02:36.390627
427 03:02:36.391048 Model: Libre Computer AML-A311D-CC Alta
428 03:02:36.598645 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 03:02:36.621979 DRAM: 2 GiB (effective 3.8 GiB)
430 03:02:36.764979 Core: 408 devices, 31 uclasses, devicetree: separate
431 03:02:36.770760 WDT: Not starting watchdog@f0d0
432 03:02:36.803008 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 03:02:36.815408 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 03:02:36.820502 ** Bad device specification mmc 0 **
435 03:02:36.830784 Card did not respond to voltage select! : -110
436 03:02:36.838461 ** Bad device specification mmc 0 **
437 03:02:36.838911 Couldn't find partition mmc 0
438 03:02:36.846750 Card did not respond to voltage select! : -110
439 03:02:36.852261 ** Bad device specification mmc 0 **
440 03:02:36.852695 Couldn't find partition mmc 0
441 03:02:36.857351 Error: could not access storage.
442 03:02:38.120224 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 03:02:38.120829 bl2_stage_init 0x01
444 03:02:38.121258 bl2_stage_init 0x81
445 03:02:38.125724 hw id: 0x0000 - pwm id 0x01
446 03:02:38.126162 bl2_stage_init 0xc1
447 03:02:38.126570 bl2_stage_init 0x02
448 03:02:38.126976
449 03:02:38.131432 L0:00000000
450 03:02:38.131860 L1:20000703
451 03:02:38.132321 L2:00008067
452 03:02:38.132726 L3:14000000
453 03:02:38.136878 B2:00402000
454 03:02:38.137302 B1:e0f83180
455 03:02:38.137704
456 03:02:38.138106 TE: 58124
457 03:02:38.138505
458 03:02:38.142575 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 03:02:38.143030
460 03:02:38.143436 Board ID = 1
461 03:02:38.148073 Set A53 clk to 24M
462 03:02:38.148502 Set A73 clk to 24M
463 03:02:38.148906 Set clk81 to 24M
464 03:02:38.153750 A53 clk: 1200 MHz
465 03:02:38.154192 A73 clk: 1200 MHz
466 03:02:38.154599 CLK81: 166.6M
467 03:02:38.154996 smccc: 00012a92
468 03:02:38.159440 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 03:02:38.164849 board id: 1
470 03:02:38.170947 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 03:02:38.181377 fw parse done
472 03:02:38.187408 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 03:02:38.230053 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 03:02:38.240878 PIEI prepare done
475 03:02:38.241308 fastboot data load
476 03:02:38.241720 fastboot data verify
477 03:02:38.246540 verify result: 266
478 03:02:38.252160 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 03:02:38.252600 LPDDR4 probe
480 03:02:38.253008 ddr clk to 1584MHz
481 03:02:38.260138 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 03:02:38.297540
483 03:02:38.298017 dmc_version 0001
484 03:02:38.304186 Check phy result
485 03:02:38.309993 INFO : End of CA training
486 03:02:38.310436 INFO : End of initialization
487 03:02:38.315631 INFO : Training has run successfully!
488 03:02:38.316127 Check phy result
489 03:02:38.321189 INFO : End of initialization
490 03:02:38.321656 INFO : End of read enable training
491 03:02:38.326838 INFO : End of fine write leveling
492 03:02:38.332516 INFO : End of Write leveling coarse delay
493 03:02:38.332971 INFO : Training has run successfully!
494 03:02:38.333382 Check phy result
495 03:02:38.338030 INFO : End of initialization
496 03:02:38.338478 INFO : End of read dq deskew training
497 03:02:38.343684 INFO : End of MPR read delay center optimization
498 03:02:38.349248 INFO : End of write delay center optimization
499 03:02:38.354823 INFO : End of read delay center optimization
500 03:02:38.355287 INFO : End of max read latency training
501 03:02:38.360543 INFO : Training has run successfully!
502 03:02:38.360998 1D training succeed
503 03:02:38.375740 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 03:02:38.417535 Check phy result
505 03:02:38.426710 INFO : End of initialization
506 03:02:38.439002 INFO : End of 2D read delay Voltage center optimization
507 03:02:38.465006 INFO : End of 2D read delay Voltage center optimization
508 03:02:38.511262 INFO : End of 2D write delay Voltage center optimization
509 03:02:38.560701 INFO : End of 2D write delay Voltage center optimization
510 03:02:38.566190 INFO : Training has run successfully!
511 03:02:38.566635
512 03:02:38.566910 channel==0
513 03:02:38.571743 RxClkDly_Margin_A0==88 ps 9
514 03:02:38.572199 TxDqDly_Margin_A0==98 ps 10
515 03:02:38.575034 RxClkDly_Margin_A1==88 ps 9
516 03:02:38.575424 TxDqDly_Margin_A1==98 ps 10
517 03:02:38.580566 TrainedVREFDQ_A0==74
518 03:02:38.580930 TrainedVREFDQ_A1==74
519 03:02:38.586307 VrefDac_Margin_A0==25
520 03:02:38.586784 DeviceVref_Margin_A0==40
521 03:02:38.587002 VrefDac_Margin_A1==25
522 03:02:38.591824 DeviceVref_Margin_A1==40
523 03:02:38.592257
524 03:02:38.592481
525 03:02:38.592692 channel==1
526 03:02:38.592896 RxClkDly_Margin_A0==98 ps 10
527 03:02:38.597243 TxDqDly_Margin_A0==98 ps 10
528 03:02:38.597508 RxClkDly_Margin_A1==88 ps 9
529 03:02:38.602936 TxDqDly_Margin_A1==88 ps 9
530 03:02:38.603303 TrainedVREFDQ_A0==77
531 03:02:38.603659 TrainedVREFDQ_A1==77
532 03:02:38.609153 VrefDac_Margin_A0==22
533 03:02:38.609700 DeviceVref_Margin_A0==37
534 03:02:38.614285 VrefDac_Margin_A1==24
535 03:02:38.615637 DeviceVref_Margin_A1==37
536 03:02:38.616813
537 03:02:38.619719 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 03:02:38.620271
539 03:02:38.647723 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 03:02:38.653350 2D training succeed
541 03:02:38.658916 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 03:02:38.659508 auto size-- 65535DDR cs0 size: 2048MB
543 03:02:38.664564 DDR cs1 size: 2048MB
544 03:02:38.665102 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 03:02:38.670239 cs0 DataBus test pass
546 03:02:38.670890 cs1 DataBus test pass
547 03:02:38.671350 cs0 AddrBus test pass
548 03:02:38.675737 cs1 AddrBus test pass
549 03:02:38.676427
550 03:02:38.676932 100bdlr_step_size ps== 420
551 03:02:38.677425 result report
552 03:02:38.681354 boot times 0Enable ddr reg access
553 03:02:38.689083 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 03:02:38.702622 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 03:02:39.276213 0.0;M3 CHK:0;cm4_sp_mode 0
556 03:02:39.276873 MVN_1=0x00000000
557 03:02:39.281592 MVN_2=0x00000000
558 03:02:39.287512 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 03:02:39.288117 OPS=0x10
560 03:02:39.288629 ring efuse init
561 03:02:39.289115 chipver efuse init
562 03:02:39.292949 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 03:02:39.298525 [0.018961 Inits done]
564 03:02:39.299014 secure task start!
565 03:02:39.299453 high task start!
566 03:02:39.303154 low task start!
567 03:02:39.303629 run into bl31
568 03:02:39.309736 NOTICE: BL31: v1.3(release):4fc40b1
569 03:02:39.317569 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 03:02:39.318073 NOTICE: BL31: G12A normal boot!
571 03:02:39.343016 NOTICE: BL31: BL33 decompress pass
572 03:02:39.348643 ERROR: Error initializing runtime service opteed_fast
573 03:02:40.581671
574 03:02:40.582336
575 03:02:40.589926 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 03:02:40.590430
577 03:02:40.590897 Model: Libre Computer AML-A311D-CC Alta
578 03:02:40.798363 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 03:02:40.821776 DRAM: 2 GiB (effective 3.8 GiB)
580 03:02:40.964746 Core: 408 devices, 31 uclasses, devicetree: separate
581 03:02:40.969633 WDT: Not starting watchdog@f0d0
582 03:02:41.002899 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 03:02:41.015338 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 03:02:41.020287 ** Bad device specification mmc 0 **
585 03:02:41.030741 Card did not respond to voltage select! : -110
586 03:02:41.037400 ** Bad device specification mmc 0 **
587 03:02:41.037897 Couldn't find partition mmc 0
588 03:02:41.046713 Card did not respond to voltage select! : -110
589 03:02:41.052155 ** Bad device specification mmc 0 **
590 03:02:41.052647 Couldn't find partition mmc 0
591 03:02:41.056393 Error: could not access storage.
592 03:02:41.399732 Net: eth0: ethernet@ff3f0000
593 03:02:41.400395 starting USB...
594 03:02:41.651555 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 03:02:41.652214 Starting the controller
596 03:02:41.658030 USB XHCI 1.10
597 03:02:43.370259 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 03:02:43.370941 bl2_stage_init 0x01
599 03:02:43.371418 bl2_stage_init 0x81
600 03:02:43.375807 hw id: 0x0000 - pwm id 0x01
601 03:02:43.376409 bl2_stage_init 0xc1
602 03:02:43.376880 bl2_stage_init 0x02
603 03:02:43.377334
604 03:02:43.381389 L0:00000000
605 03:02:43.381890 L1:20000703
606 03:02:43.382349 L2:00008067
607 03:02:43.382797 L3:14000000
608 03:02:43.384266 B2:00402000
609 03:02:43.384757 B1:e0f83180
610 03:02:43.385210
611 03:02:43.385660 TE: 58124
612 03:02:43.386107
613 03:02:43.395374 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 03:02:43.395885
615 03:02:43.396384 Board ID = 1
616 03:02:43.396833 Set A53 clk to 24M
617 03:02:43.397274 Set A73 clk to 24M
618 03:02:43.401053 Set clk81 to 24M
619 03:02:43.401552 A53 clk: 1200 MHz
620 03:02:43.402010 A73 clk: 1200 MHz
621 03:02:43.406550 CLK81: 166.6M
622 03:02:43.407037 smccc: 00012a91
623 03:02:43.412189 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 03:02:43.412688 board id: 1
625 03:02:43.417828 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 03:02:43.431511 fw parse done
627 03:02:43.437486 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 03:02:43.480190 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 03:02:43.491189 PIEI prepare done
630 03:02:43.491777 fastboot data load
631 03:02:43.492304 fastboot data verify
632 03:02:43.496703 verify result: 266
633 03:02:43.502306 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 03:02:43.502826 LPDDR4 probe
635 03:02:43.503282 ddr clk to 1584MHz
636 03:02:43.510308 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 03:02:43.547571
638 03:02:43.548137 dmc_version 0001
639 03:02:43.554248 Check phy result
640 03:02:43.560192 INFO : End of CA training
641 03:02:43.560681 INFO : End of initialization
642 03:02:43.565685 INFO : Training has run successfully!
643 03:02:43.566180 Check phy result
644 03:02:43.571283 INFO : End of initialization
645 03:02:43.571772 INFO : End of read enable training
646 03:02:43.576870 INFO : End of fine write leveling
647 03:02:43.582437 INFO : End of Write leveling coarse delay
648 03:02:43.582916 INFO : Training has run successfully!
649 03:02:43.583362 Check phy result
650 03:02:43.588153 INFO : End of initialization
651 03:02:43.588634 INFO : End of read dq deskew training
652 03:02:43.593637 INFO : End of MPR read delay center optimization
653 03:02:43.599263 INFO : End of write delay center optimization
654 03:02:43.604843 INFO : End of read delay center optimization
655 03:02:43.605338 INFO : End of max read latency training
656 03:02:43.610468 INFO : Training has run successfully!
657 03:02:43.610954 1D training succeed
658 03:02:43.619631 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 03:02:43.667256 Check phy result
660 03:02:43.667748 INFO : End of initialization
661 03:02:43.689006 INFO : End of 2D read delay Voltage center optimization
662 03:02:43.709219 INFO : End of 2D read delay Voltage center optimization
663 03:02:43.761391 INFO : End of 2D write delay Voltage center optimization
664 03:02:43.810893 INFO : End of 2D write delay Voltage center optimization
665 03:02:43.816291 INFO : Training has run successfully!
666 03:02:43.816776
667 03:02:43.817230 channel==0
668 03:02:43.821950 RxClkDly_Margin_A0==88 ps 9
669 03:02:43.822428 TxDqDly_Margin_A0==98 ps 10
670 03:02:43.827360 RxClkDly_Margin_A1==88 ps 9
671 03:02:43.827846 TxDqDly_Margin_A1==88 ps 9
672 03:02:43.828361 TrainedVREFDQ_A0==74
673 03:02:43.833009 TrainedVREFDQ_A1==74
674 03:02:43.833492 VrefDac_Margin_A0==25
675 03:02:43.833943 DeviceVref_Margin_A0==40
676 03:02:43.838645 VrefDac_Margin_A1==25
677 03:02:43.839116 DeviceVref_Margin_A1==40
678 03:02:43.839563
679 03:02:43.840036
680 03:02:43.840488 channel==1
681 03:02:43.844237 RxClkDly_Margin_A0==98 ps 10
682 03:02:43.844714 TxDqDly_Margin_A0==88 ps 9
683 03:02:43.849867 RxClkDly_Margin_A1==98 ps 10
684 03:02:43.850351 TxDqDly_Margin_A1==88 ps 9
685 03:02:43.855361 TrainedVREFDQ_A0==76
686 03:02:43.855844 TrainedVREFDQ_A1==77
687 03:02:43.856333 VrefDac_Margin_A0==22
688 03:02:43.860954 DeviceVref_Margin_A0==38
689 03:02:43.861432 VrefDac_Margin_A1==22
690 03:02:43.866564 DeviceVref_Margin_A1==37
691 03:02:43.867038
692 03:02:43.867487 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 03:02:43.867935
694 03:02:43.900200 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
695 03:02:43.900721 2D training succeed
696 03:02:43.905793 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 03:02:43.911336 auto size-- 65535DDR cs0 size: 2048MB
698 03:02:43.911813 DDR cs1 size: 2048MB
699 03:02:43.916970 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 03:02:43.917446 cs0 DataBus test pass
701 03:02:43.922628 cs1 DataBus test pass
702 03:02:43.923107 cs0 AddrBus test pass
703 03:02:43.923558 cs1 AddrBus test pass
704 03:02:43.924033
705 03:02:43.928230 100bdlr_step_size ps== 420
706 03:02:43.928723 result report
707 03:02:43.933831 boot times 0Enable ddr reg access
708 03:02:43.939082 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 03:02:43.952555 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 03:02:44.526613 0.0;M3 CHK:0;cm4_sp_mode 0
711 03:02:44.527268 MVN_1=0x00000000
712 03:02:44.531862 MVN_2=0x00000000
713 03:02:44.537717 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 03:02:44.538316 OPS=0x10
715 03:02:44.538776 ring efuse init
716 03:02:44.539206 chipver efuse init
717 03:02:44.545907 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 03:02:44.546421 [0.018961 Inits done]
719 03:02:44.546853 secure task start!
720 03:02:44.553498 high task start!
721 03:02:44.553968 low task start!
722 03:02:44.554394 run into bl31
723 03:02:44.560071 NOTICE: BL31: v1.3(release):4fc40b1
724 03:02:44.567000 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 03:02:44.567487 NOTICE: BL31: G12A normal boot!
726 03:02:44.593140 NOTICE: BL31: BL33 decompress pass
727 03:02:44.598814 ERROR: Error initializing runtime service opteed_fast
728 03:02:45.831751
729 03:02:45.832446
730 03:02:45.840275 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 03:02:45.840782
732 03:02:45.841241 Model: Libre Computer AML-A311D-CC Alta
733 03:02:46.048900 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 03:02:46.072081 DRAM: 2 GiB (effective 3.8 GiB)
735 03:02:46.214894 Core: 408 devices, 31 uclasses, devicetree: separate
736 03:02:46.220738 WDT: Not starting watchdog@f0d0
737 03:02:46.253099 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 03:02:46.265626 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 03:02:46.269758 ** Bad device specification mmc 0 **
740 03:02:46.281194 Card did not respond to voltage select! : -110
741 03:02:46.287716 ** Bad device specification mmc 0 **
742 03:02:46.288261 Couldn't find partition mmc 0
743 03:02:46.296887 Card did not respond to voltage select! : -110
744 03:02:46.302446 ** Bad device specification mmc 0 **
745 03:02:46.302942 Couldn't find partition mmc 0
746 03:02:46.306588 Error: could not access storage.
747 03:02:46.649996 Net: eth0: ethernet@ff3f0000
748 03:02:46.650658 starting USB...
749 03:02:46.901857 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 03:02:46.902490 Starting the controller
751 03:02:46.908814 USB XHCI 1.10
752 03:02:49.070380 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 03:02:49.071039 bl2_stage_init 0x01
754 03:02:49.071513 bl2_stage_init 0x81
755 03:02:49.076008 hw id: 0x0000 - pwm id 0x01
756 03:02:49.076542 bl2_stage_init 0xc1
757 03:02:49.076979 bl2_stage_init 0x02
758 03:02:49.077395
759 03:02:49.081612 L0:00000000
760 03:02:49.082106 L1:20000703
761 03:02:49.082526 L2:00008067
762 03:02:49.082937 L3:14000000
763 03:02:49.084539 B2:00402000
764 03:02:49.085022 B1:e0f83180
765 03:02:49.085438
766 03:02:49.085851 TE: 58159
767 03:02:49.086257
768 03:02:49.095624 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 03:02:49.096193
770 03:02:49.096628 Board ID = 1
771 03:02:49.097048 Set A53 clk to 24M
772 03:02:49.097463 Set A73 clk to 24M
773 03:02:49.101281 Set clk81 to 24M
774 03:02:49.101805 A53 clk: 1200 MHz
775 03:02:49.102227 A73 clk: 1200 MHz
776 03:02:49.104604 CLK81: 166.6M
777 03:02:49.105109 smccc: 00012ab5
778 03:02:49.110215 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 03:02:49.115897 board id: 1
780 03:02:49.121072 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 03:02:49.131738 fw parse done
782 03:02:49.137699 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 03:02:49.180347 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 03:02:49.191366 PIEI prepare done
785 03:02:49.192020 fastboot data load
786 03:02:49.192529 fastboot data verify
787 03:02:49.197019 verify result: 266
788 03:02:49.202533 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 03:02:49.203093 LPDDR4 probe
790 03:02:49.203526 ddr clk to 1584MHz
791 03:02:49.209714 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 03:02:49.247717
793 03:02:49.248329 dmc_version 0001
794 03:02:49.254419 Check phy result
795 03:02:49.260273 INFO : End of CA training
796 03:02:49.260779 INFO : End of initialization
797 03:02:49.266018 INFO : Training has run successfully!
798 03:02:49.266540 Check phy result
799 03:02:49.271501 INFO : End of initialization
800 03:02:49.272103 INFO : End of read enable training
801 03:02:49.277292 INFO : End of fine write leveling
802 03:02:49.282722 INFO : End of Write leveling coarse delay
803 03:02:49.283274 INFO : Training has run successfully!
804 03:02:49.283699 Check phy result
805 03:02:49.288312 INFO : End of initialization
806 03:02:49.288869 INFO : End of read dq deskew training
807 03:02:49.294030 INFO : End of MPR read delay center optimization
808 03:02:49.299492 INFO : End of write delay center optimization
809 03:02:49.305052 INFO : End of read delay center optimization
810 03:02:49.305585 INFO : End of max read latency training
811 03:02:49.310659 INFO : Training has run successfully!
812 03:02:49.311202 1D training succeed
813 03:02:49.318970 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 03:02:49.367520 Check phy result
815 03:02:49.368178 INFO : End of initialization
816 03:02:49.389951 INFO : End of 2D read delay Voltage center optimization
817 03:02:49.410193 INFO : End of 2D read delay Voltage center optimization
818 03:02:49.461924 INFO : End of 2D write delay Voltage center optimization
819 03:02:49.511147 INFO : End of 2D write delay Voltage center optimization
820 03:02:49.516702 INFO : Training has run successfully!
821 03:02:49.517274
822 03:02:49.517761 channel==0
823 03:02:49.522338 RxClkDly_Margin_A0==88 ps 9
824 03:02:49.522909 TxDqDly_Margin_A0==98 ps 10
825 03:02:49.527882 RxClkDly_Margin_A1==88 ps 9
826 03:02:49.528458 TxDqDly_Margin_A1==88 ps 9
827 03:02:49.528919 TrainedVREFDQ_A0==74
828 03:02:49.533527 TrainedVREFDQ_A1==74
829 03:02:49.534092 VrefDac_Margin_A0==25
830 03:02:49.534527 DeviceVref_Margin_A0==40
831 03:02:49.539090 VrefDac_Margin_A1==24
832 03:02:49.539666 DeviceVref_Margin_A1==40
833 03:02:49.540147
834 03:02:49.540561
835 03:02:49.540979 channel==1
836 03:02:49.544697 RxClkDly_Margin_A0==98 ps 10
837 03:02:49.545200 TxDqDly_Margin_A0==98 ps 10
838 03:02:49.550273 RxClkDly_Margin_A1==88 ps 9
839 03:02:49.550803 TxDqDly_Margin_A1==98 ps 10
840 03:02:49.555893 TrainedVREFDQ_A0==77
841 03:02:49.556466 TrainedVREFDQ_A1==77
842 03:02:49.556914 VrefDac_Margin_A0==22
843 03:02:49.561484 DeviceVref_Margin_A0==37
844 03:02:49.562004 VrefDac_Margin_A1==24
845 03:02:49.567053 DeviceVref_Margin_A1==37
846 03:02:49.567546
847 03:02:49.567948 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 03:02:49.568385
849 03:02:49.600676 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
850 03:02:49.601246 2D training succeed
851 03:02:49.606256 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 03:02:49.611886 auto size-- 65535DDR cs0 size: 2048MB
853 03:02:49.612450 DDR cs1 size: 2048MB
854 03:02:49.617455 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 03:02:49.617956 cs0 DataBus test pass
856 03:02:49.623063 cs1 DataBus test pass
857 03:02:49.623550 cs0 AddrBus test pass
858 03:02:49.623949 cs1 AddrBus test pass
859 03:02:49.624385
860 03:02:49.628661 100bdlr_step_size ps== 420
861 03:02:49.629160 result report
862 03:02:49.634270 boot times 0Enable ddr reg access
863 03:02:49.639634 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 03:02:49.652174 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 03:02:50.225185 0.0;M3 CHK:0;cm4_sp_mode 0
866 03:02:50.225814 MVN_1=0x00000000
867 03:02:50.230653 MVN_2=0x00000000
868 03:02:50.236377 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 03:02:50.236870 OPS=0x10
870 03:02:50.237298 ring efuse init
871 03:02:50.237711 chipver efuse init
872 03:02:50.244762 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 03:02:50.245311 [0.018961 Inits done]
874 03:02:50.245766 secure task start!
875 03:02:50.252173 high task start!
876 03:02:50.252702 low task start!
877 03:02:50.253125 run into bl31
878 03:02:50.258743 NOTICE: BL31: v1.3(release):4fc40b1
879 03:02:50.265592 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 03:02:50.266140 NOTICE: BL31: G12A normal boot!
881 03:02:50.291870 NOTICE: BL31: BL33 decompress pass
882 03:02:50.297570 ERROR: Error initializing runtime service opteed_fast
883 03:02:51.530450
884 03:02:51.531075
885 03:02:51.539162 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 03:02:51.539726
887 03:02:51.540229 Model: Libre Computer AML-A311D-CC Alta
888 03:02:51.747283 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 03:02:51.770630 DRAM: 2 GiB (effective 3.8 GiB)
890 03:02:51.913631 Core: 408 devices, 31 uclasses, devicetree: separate
891 03:02:51.919517 WDT: Not starting watchdog@f0d0
892 03:02:51.951729 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 03:02:51.964363 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 03:02:51.969261 ** Bad device specification mmc 0 **
895 03:02:51.980205 Card did not respond to voltage select! : -110
896 03:02:51.987153 ** Bad device specification mmc 0 **
897 03:02:51.987676 Couldn't find partition mmc 0
898 03:02:51.995443 Card did not respond to voltage select! : -110
899 03:02:52.000981 ** Bad device specification mmc 0 **
900 03:02:52.001487 Couldn't find partition mmc 0
901 03:02:52.005609 Error: could not access storage.
902 03:02:52.348537 Net: eth0: ethernet@ff3f0000
903 03:02:52.349118 starting USB...
904 03:02:52.600661 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 03:02:52.601306 Starting the controller
906 03:02:52.607608 USB XHCI 1.10
907 03:02:54.470349 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 03:02:54.471009 bl2_stage_init 0x01
909 03:02:54.471495 bl2_stage_init 0x81
910 03:02:54.475840 hw id: 0x0000 - pwm id 0x01
911 03:02:54.476387 bl2_stage_init 0xc1
912 03:02:54.476855 bl2_stage_init 0x02
913 03:02:54.477311
914 03:02:54.481498 L0:00000000
915 03:02:54.481993 L1:20000703
916 03:02:54.482452 L2:00008067
917 03:02:54.482901 L3:14000000
918 03:02:54.484338 B2:00402000
919 03:02:54.484842 B1:e0f83180
920 03:02:54.485302
921 03:02:54.485758 TE: 58124
922 03:02:54.486203
923 03:02:54.495709 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 03:02:54.496337
925 03:02:54.496811 Board ID = 1
926 03:02:54.497259 Set A53 clk to 24M
927 03:02:54.497709 Set A73 clk to 24M
928 03:02:54.501201 Set clk81 to 24M
929 03:02:54.501756 A53 clk: 1200 MHz
930 03:02:54.502231 A73 clk: 1200 MHz
931 03:02:54.506819 CLK81: 166.6M
932 03:02:54.507323 smccc: 00012a92
933 03:02:54.512311 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 03:02:54.512820 board id: 1
935 03:02:54.521056 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 03:02:54.531623 fw parse done
937 03:02:54.537554 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 03:02:54.580227 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 03:02:54.591028 PIEI prepare done
940 03:02:54.591515 fastboot data load
941 03:02:54.591956 fastboot data verify
942 03:02:54.596698 verify result: 266
943 03:02:54.602317 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 03:02:54.602791 LPDDR4 probe
945 03:02:54.603232 ddr clk to 1584MHz
946 03:02:54.610316 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 03:02:54.647591
948 03:02:54.648110 dmc_version 0001
949 03:02:54.654311 Check phy result
950 03:02:54.660088 INFO : End of CA training
951 03:02:54.660566 INFO : End of initialization
952 03:02:54.665737 INFO : Training has run successfully!
953 03:02:54.666288 Check phy result
954 03:02:54.671351 INFO : End of initialization
955 03:02:54.671864 INFO : End of read enable training
956 03:02:54.676864 INFO : End of fine write leveling
957 03:02:54.682530 INFO : End of Write leveling coarse delay
958 03:02:54.683019 INFO : Training has run successfully!
959 03:02:54.683474 Check phy result
960 03:02:54.688122 INFO : End of initialization
961 03:02:54.688613 INFO : End of read dq deskew training
962 03:02:54.693742 INFO : End of MPR read delay center optimization
963 03:02:54.699328 INFO : End of write delay center optimization
964 03:02:54.704943 INFO : End of read delay center optimization
965 03:02:54.705434 INFO : End of max read latency training
966 03:02:54.710518 INFO : Training has run successfully!
967 03:02:54.711001 1D training succeed
968 03:02:54.719810 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 03:02:54.767330 Check phy result
970 03:02:54.767842 INFO : End of initialization
971 03:02:54.789037 INFO : End of 2D read delay Voltage center optimization
972 03:02:54.809268 INFO : End of 2D read delay Voltage center optimization
973 03:02:54.861327 INFO : End of 2D write delay Voltage center optimization
974 03:02:54.910808 INFO : End of 2D write delay Voltage center optimization
975 03:02:54.916269 INFO : Training has run successfully!
976 03:02:54.916772
977 03:02:54.917231 channel==0
978 03:02:54.921839 RxClkDly_Margin_A0==88 ps 9
979 03:02:54.922327 TxDqDly_Margin_A0==98 ps 10
980 03:02:54.925204 RxClkDly_Margin_A1==88 ps 9
981 03:02:54.925718 TxDqDly_Margin_A1==98 ps 10
982 03:02:54.930617 TrainedVREFDQ_A0==74
983 03:02:54.931118 TrainedVREFDQ_A1==74
984 03:02:54.936229 VrefDac_Margin_A0==25
985 03:02:54.936727 DeviceVref_Margin_A0==40
986 03:02:54.937180 VrefDac_Margin_A1==25
987 03:02:54.941772 DeviceVref_Margin_A1==40
988 03:02:54.942276
989 03:02:54.942736
990 03:02:54.943187 channel==1
991 03:02:54.943633 RxClkDly_Margin_A0==98 ps 10
992 03:02:54.947421 TxDqDly_Margin_A0==88 ps 9
993 03:02:54.947924 RxClkDly_Margin_A1==98 ps 10
994 03:02:54.953032 TxDqDly_Margin_A1==88 ps 9
995 03:02:54.953549 TrainedVREFDQ_A0==76
996 03:02:54.954011 TrainedVREFDQ_A1==77
997 03:02:54.958600 VrefDac_Margin_A0==22
998 03:02:54.959108 DeviceVref_Margin_A0==38
999 03:02:54.964215 VrefDac_Margin_A1==22
1000 03:02:54.964715 DeviceVref_Margin_A1==37
1001 03:02:54.965166
1002 03:02:54.969763 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 03:02:54.970262
1004 03:02:54.997805 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
1005 03:02:55.003350 2D training succeed
1006 03:02:55.008942 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 03:02:55.009452 auto size-- 65535DDR cs0 size: 2048MB
1008 03:02:55.014566 DDR cs1 size: 2048MB
1009 03:02:55.015065 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 03:02:55.020174 cs0 DataBus test pass
1011 03:02:55.020677 cs1 DataBus test pass
1012 03:02:55.021136 cs0 AddrBus test pass
1013 03:02:55.025726 cs1 AddrBus test pass
1014 03:02:55.026232
1015 03:02:55.026692 100bdlr_step_size ps== 420
1016 03:02:55.027152 result report
1017 03:02:55.031366 boot times 0Enable ddr reg access
1018 03:02:55.039183 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 03:02:55.052666 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 03:02:55.626566 0.0;M3 CHK:0;cm4_sp_mode 0
1021 03:02:55.627226 MVN_1=0x00000000
1022 03:02:55.631867 MVN_2=0x00000000
1023 03:02:55.637674 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 03:02:55.638186 OPS=0x10
1025 03:02:55.638650 ring efuse init
1026 03:02:55.639105 chipver efuse init
1027 03:02:55.643270 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 03:02:55.648918 [0.018960 Inits done]
1029 03:02:55.649407 secure task start!
1030 03:02:55.649862 high task start!
1031 03:02:55.653464 low task start!
1032 03:02:55.653945 run into bl31
1033 03:02:55.660196 NOTICE: BL31: v1.3(release):4fc40b1
1034 03:02:55.668041 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 03:02:55.668540 NOTICE: BL31: G12A normal boot!
1036 03:02:55.693914 NOTICE: BL31: BL33 decompress pass
1037 03:02:55.699659 ERROR: Error initializing runtime service opteed_fast
1038 03:02:56.932561
1039 03:02:56.933248
1040 03:02:56.940917 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 03:02:56.941439
1042 03:02:56.941905 Model: Libre Computer AML-A311D-CC Alta
1043 03:02:57.149324 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 03:02:57.172592 DRAM: 2 GiB (effective 3.8 GiB)
1045 03:02:57.315681 Core: 408 devices, 31 uclasses, devicetree: separate
1046 03:02:57.321509 WDT: Not starting watchdog@f0d0
1047 03:02:57.353767 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 03:02:57.366226 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 03:02:57.371279 ** Bad device specification mmc 0 **
1050 03:02:57.381576 Card did not respond to voltage select! : -110
1051 03:02:57.389235 ** Bad device specification mmc 0 **
1052 03:02:57.389754 Couldn't find partition mmc 0
1053 03:02:57.397531 Card did not respond to voltage select! : -110
1054 03:02:57.403138 ** Bad device specification mmc 0 **
1055 03:02:57.403625 Couldn't find partition mmc 0
1056 03:02:57.408329 Error: could not access storage.
1057 03:02:57.751782 Net: eth0: ethernet@ff3f0000
1058 03:02:57.752458 starting USB...
1059 03:02:58.003664 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 03:02:58.004321 Starting the controller
1061 03:02:58.010634 USB XHCI 1.10
1062 03:02:59.564542 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 03:02:59.572859 scanning usb for storage devices... 0 Storage Device(s) found
1065 03:02:59.624461 Hit any key to stop autoboot: 1
1066 03:02:59.625279 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 03:02:59.625949 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 03:02:59.626427 Setting prompt string to ['=>']
1069 03:02:59.626896 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 03:02:59.640243 0
1071 03:02:59.641149 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 03:02:59.641637 Sending with 10 millisecond of delay
1074 03:03:00.776326 => setenv autoload no
1075 03:03:00.787150 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1076 03:03:00.792140 setenv autoload no
1077 03:03:00.792925 Sending with 10 millisecond of delay
1079 03:03:02.590295 => setenv initrd_high 0xffffffff
1080 03:03:02.600901 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 03:03:02.601855 setenv initrd_high 0xffffffff
1082 03:03:02.602587 Sending with 10 millisecond of delay
1084 03:03:04.219916 => setenv fdt_high 0xffffffff
1085 03:03:04.230808 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 03:03:04.231679 setenv fdt_high 0xffffffff
1087 03:03:04.232481 Sending with 10 millisecond of delay
1089 03:03:04.524521 => dhcp
1090 03:03:04.535359 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 03:03:04.536279 dhcp
1092 03:03:04.536761 Speed: 1000, full duplex
1093 03:03:04.537210 BOOTP broadcast 1
1094 03:03:04.703015 DHCP client bound to address 192.168.6.27 (167 ms)
1095 03:03:04.703872 Sending with 10 millisecond of delay
1097 03:03:06.380525 => setenv serverip 192.168.6.2
1098 03:03:06.391308 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 03:03:06.392202 setenv serverip 192.168.6.2
1100 03:03:06.392949 Sending with 10 millisecond of delay
1102 03:03:10.116382 => tftpboot 0x01080000 957096/tftp-deploy-ttofvnyy/kernel/uImage
1103 03:03:10.127242 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 03:03:10.128284 tftpboot 0x01080000 957096/tftp-deploy-ttofvnyy/kernel/uImage
1105 03:03:10.128768 Speed: 1000, full duplex
1106 03:03:10.129212 Using ethernet@ff3f0000 device
1107 03:03:10.129978 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 03:03:10.135534 Filename '957096/tftp-deploy-ttofvnyy/kernel/uImage'.
1109 03:03:10.139506 Load address: 0x1080000
1110 03:03:12.898727 Loading: *################################################## 43.6 MiB
1111 03:03:12.899387 15.8 MiB/s
1112 03:03:12.899856 done
1113 03:03:12.903085 Bytes transferred = 45713984 (2b98a40 hex)
1114 03:03:12.903862 Sending with 10 millisecond of delay
1116 03:03:17.590726 => tftpboot 0x08000000 957096/tftp-deploy-ttofvnyy/ramdisk/ramdisk.cpio.gz.uboot
1117 03:03:17.601533 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1118 03:03:17.602080 tftpboot 0x08000000 957096/tftp-deploy-ttofvnyy/ramdisk/ramdisk.cpio.gz.uboot
1119 03:03:17.602347 Speed: 1000, full duplex
1120 03:03:17.602803 Using ethernet@ff3f0000 device
1121 03:03:17.604412 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 03:03:17.616208 Filename '957096/tftp-deploy-ttofvnyy/ramdisk/ramdisk.cpio.gz.uboot'.
1123 03:03:17.616643 Load address: 0x8000000
1124 03:03:27.394876 Loading: *##########T ####################################### UDP wrong checksum 0000000f 00008851
1125 03:03:32.395349 T UDP wrong checksum 0000000f 00008851
1126 03:03:42.397565 T T UDP wrong checksum 0000000f 00008851
1127 03:04:02.402376 T T T T UDP wrong checksum 0000000f 00008851
1128 03:04:17.406582 T T
1129 03:04:17.407207 Retry count exceeded; starting again
1131 03:04:17.408678 end: 2.4.3 bootloader-commands (duration 00:01:18) [common]
1134 03:04:17.410544 end: 2.4 uboot-commands (duration 00:01:55) [common]
1136 03:04:17.412100 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1138 03:04:17.413141 end: 2 uboot-action (duration 00:01:55) [common]
1140 03:04:17.414645 Cleaning after the job
1141 03:04:17.415197 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957096/tftp-deploy-ttofvnyy/ramdisk
1142 03:04:17.416506 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957096/tftp-deploy-ttofvnyy/kernel
1143 03:04:17.459589 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957096/tftp-deploy-ttofvnyy/dtb
1144 03:04:17.460420 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957096/tftp-deploy-ttofvnyy/modules
1145 03:04:17.479772 start: 4.1 power-off (timeout 00:00:30) [common]
1146 03:04:17.480449 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1147 03:04:17.515889 >> OK - accepted request
1148 03:04:17.517042 Returned 0 in 0 seconds
1149 03:04:17.617750 end: 4.1 power-off (duration 00:00:00) [common]
1151 03:04:17.618706 start: 4.2 read-feedback (timeout 00:10:00) [common]
1152 03:04:17.619362 Listened to connection for namespace 'common' for up to 1s
1153 03:04:18.620353 Finalising connection for namespace 'common'
1154 03:04:18.621109 Disconnecting from shell: Finalise
1155 03:04:18.621634 =>
1156 03:04:18.722614 end: 4.2 read-feedback (duration 00:00:01) [common]
1157 03:04:18.723177 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/957096
1158 03:04:19.334794 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/957096
1159 03:04:19.335419 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.