Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 6
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 03:04:42.454119 lava-dispatcher, installed at version: 2024.01
2 03:04:42.454926 start: 0 validate
3 03:04:42.455414 Start time: 2024-11-08 03:04:42.455385+00:00 (UTC)
4 03:04:42.455957 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:04:42.456540 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 03:04:42.501420 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:04:42.502013 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 03:04:42.537370 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:04:42.538008 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 03:04:42.572317 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:04:42.572850 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 03:04:42.605872 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 03:04:42.606369 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 03:04:42.643439 validate duration: 0.19
16 03:04:42.644495 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 03:04:42.644816 start: 1.1 download-retry (timeout 00:10:00) [common]
18 03:04:42.645121 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 03:04:42.645692 Not decompressing ramdisk as can be used compressed.
20 03:04:42.646131 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 03:04:42.646407 saving as /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/ramdisk/initrd.cpio.gz
22 03:04:42.646672 total size: 5628169 (5 MB)
23 03:04:42.686625 progress 0 % (0 MB)
24 03:04:42.690782 progress 5 % (0 MB)
25 03:04:42.695057 progress 10 % (0 MB)
26 03:04:42.698812 progress 15 % (0 MB)
27 03:04:42.703011 progress 20 % (1 MB)
28 03:04:42.706765 progress 25 % (1 MB)
29 03:04:42.710894 progress 30 % (1 MB)
30 03:04:42.715002 progress 35 % (1 MB)
31 03:04:42.718764 progress 40 % (2 MB)
32 03:04:42.722819 progress 45 % (2 MB)
33 03:04:42.726526 progress 50 % (2 MB)
34 03:04:42.730620 progress 55 % (2 MB)
35 03:04:42.734793 progress 60 % (3 MB)
36 03:04:42.740693 progress 65 % (3 MB)
37 03:04:42.744765 progress 70 % (3 MB)
38 03:04:42.748367 progress 75 % (4 MB)
39 03:04:42.752333 progress 80 % (4 MB)
40 03:04:42.755886 progress 85 % (4 MB)
41 03:04:42.759855 progress 90 % (4 MB)
42 03:04:42.763652 progress 95 % (5 MB)
43 03:04:42.766983 progress 100 % (5 MB)
44 03:04:42.767664 5 MB downloaded in 0.12 s (44.37 MB/s)
45 03:04:42.768277 end: 1.1.1 http-download (duration 00:00:00) [common]
47 03:04:42.769262 end: 1.1 download-retry (duration 00:00:00) [common]
48 03:04:42.769601 start: 1.2 download-retry (timeout 00:10:00) [common]
49 03:04:42.769908 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 03:04:42.770413 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/gcc-12/kernel/Image
51 03:04:42.770692 saving as /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/kernel/Image
52 03:04:42.770925 total size: 45713920 (43 MB)
53 03:04:42.771159 No compression specified
54 03:04:42.812702 progress 0 % (0 MB)
55 03:04:42.841187 progress 5 % (2 MB)
56 03:04:42.870042 progress 10 % (4 MB)
57 03:04:42.899084 progress 15 % (6 MB)
58 03:04:42.928320 progress 20 % (8 MB)
59 03:04:42.956578 progress 25 % (10 MB)
60 03:04:42.989950 progress 30 % (13 MB)
61 03:04:43.024642 progress 35 % (15 MB)
62 03:04:43.059284 progress 40 % (17 MB)
63 03:04:43.093428 progress 45 % (19 MB)
64 03:04:43.128093 progress 50 % (21 MB)
65 03:04:43.162642 progress 55 % (24 MB)
66 03:04:43.196971 progress 60 % (26 MB)
67 03:04:43.230915 progress 65 % (28 MB)
68 03:04:43.265824 progress 70 % (30 MB)
69 03:04:43.300172 progress 75 % (32 MB)
70 03:04:43.334673 progress 80 % (34 MB)
71 03:04:43.368857 progress 85 % (37 MB)
72 03:04:43.403471 progress 90 % (39 MB)
73 03:04:43.438543 progress 95 % (41 MB)
74 03:04:43.472486 progress 100 % (43 MB)
75 03:04:43.473125 43 MB downloaded in 0.70 s (62.09 MB/s)
76 03:04:43.473733 end: 1.2.1 http-download (duration 00:00:01) [common]
78 03:04:43.474780 end: 1.2 download-retry (duration 00:00:01) [common]
79 03:04:43.475123 start: 1.3 download-retry (timeout 00:09:59) [common]
80 03:04:43.475453 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 03:04:43.476094 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 03:04:43.476472 saving as /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/dtb/meson-g12b-a311d-libretech-cc.dtb
83 03:04:43.476734 total size: 54703 (0 MB)
84 03:04:43.476994 No compression specified
85 03:04:43.519841 progress 59 % (0 MB)
86 03:04:43.520750 progress 100 % (0 MB)
87 03:04:43.521325 0 MB downloaded in 0.04 s (1.17 MB/s)
88 03:04:43.521837 end: 1.3.1 http-download (duration 00:00:00) [common]
90 03:04:43.522663 end: 1.3 download-retry (duration 00:00:00) [common]
91 03:04:43.522929 start: 1.4 download-retry (timeout 00:09:59) [common]
92 03:04:43.523193 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 03:04:43.523652 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 03:04:43.523904 saving as /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/nfsrootfs/full.rootfs.tar
95 03:04:43.524143 total size: 120894716 (115 MB)
96 03:04:43.524361 Using unxz to decompress xz
97 03:04:43.563605 progress 0 % (0 MB)
98 03:04:44.357852 progress 5 % (5 MB)
99 03:04:45.197941 progress 10 % (11 MB)
100 03:04:45.992734 progress 15 % (17 MB)
101 03:04:46.737072 progress 20 % (23 MB)
102 03:04:47.327395 progress 25 % (28 MB)
103 03:04:48.149564 progress 30 % (34 MB)
104 03:04:48.942108 progress 35 % (40 MB)
105 03:04:49.284538 progress 40 % (46 MB)
106 03:04:49.655771 progress 45 % (51 MB)
107 03:04:50.373693 progress 50 % (57 MB)
108 03:04:51.256143 progress 55 % (63 MB)
109 03:04:52.035589 progress 60 % (69 MB)
110 03:04:52.796632 progress 65 % (74 MB)
111 03:04:53.579141 progress 70 % (80 MB)
112 03:04:54.406606 progress 75 % (86 MB)
113 03:04:55.235613 progress 80 % (92 MB)
114 03:04:56.076639 progress 85 % (98 MB)
115 03:04:56.929691 progress 90 % (103 MB)
116 03:04:57.705496 progress 95 % (109 MB)
117 03:04:58.536908 progress 100 % (115 MB)
118 03:04:58.549443 115 MB downloaded in 15.03 s (7.67 MB/s)
119 03:04:58.550100 end: 1.4.1 http-download (duration 00:00:15) [common]
121 03:04:58.551000 end: 1.4 download-retry (duration 00:00:15) [common]
122 03:04:58.551311 start: 1.5 download-retry (timeout 00:09:44) [common]
123 03:04:58.551624 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 03:04:58.552234 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/gcc-12/modules.tar.xz
125 03:04:58.552520 saving as /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/modules/modules.tar
126 03:04:58.552754 total size: 11613712 (11 MB)
127 03:04:58.552990 Using unxz to decompress xz
128 03:04:58.597458 progress 0 % (0 MB)
129 03:04:58.664207 progress 5 % (0 MB)
130 03:04:58.738309 progress 10 % (1 MB)
131 03:04:58.834120 progress 15 % (1 MB)
132 03:04:58.927643 progress 20 % (2 MB)
133 03:04:59.007213 progress 25 % (2 MB)
134 03:04:59.082830 progress 30 % (3 MB)
135 03:04:59.160949 progress 35 % (3 MB)
136 03:04:59.232689 progress 40 % (4 MB)
137 03:04:59.310031 progress 45 % (5 MB)
138 03:04:59.394798 progress 50 % (5 MB)
139 03:04:59.471644 progress 55 % (6 MB)
140 03:04:59.556165 progress 60 % (6 MB)
141 03:04:59.637059 progress 65 % (7 MB)
142 03:04:59.716990 progress 70 % (7 MB)
143 03:04:59.794948 progress 75 % (8 MB)
144 03:04:59.878006 progress 80 % (8 MB)
145 03:04:59.957463 progress 85 % (9 MB)
146 03:05:00.035262 progress 90 % (9 MB)
147 03:05:00.112550 progress 95 % (10 MB)
148 03:05:00.188799 progress 100 % (11 MB)
149 03:05:00.200541 11 MB downloaded in 1.65 s (6.72 MB/s)
150 03:05:00.201397 end: 1.5.1 http-download (duration 00:00:02) [common]
152 03:05:00.202967 end: 1.5 download-retry (duration 00:00:02) [common]
153 03:05:00.203474 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 03:05:00.204016 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 03:05:16.625855 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/957122/extract-nfsrootfs-o26e1drq
156 03:05:16.626467 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 03:05:16.626754 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 03:05:16.627371 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j
159 03:05:16.627800 makedir: /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin
160 03:05:16.628179 makedir: /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/tests
161 03:05:16.628502 makedir: /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/results
162 03:05:16.628834 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-add-keys
163 03:05:16.629362 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-add-sources
164 03:05:16.629871 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-background-process-start
165 03:05:16.630411 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-background-process-stop
166 03:05:16.631012 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-common-functions
167 03:05:16.631526 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-echo-ipv4
168 03:05:16.632075 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-install-packages
169 03:05:16.632583 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-installed-packages
170 03:05:16.633059 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-os-build
171 03:05:16.633532 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-probe-channel
172 03:05:16.634074 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-probe-ip
173 03:05:16.634558 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-target-ip
174 03:05:16.635030 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-target-mac
175 03:05:16.635505 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-target-storage
176 03:05:16.636012 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-test-case
177 03:05:16.636508 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-test-event
178 03:05:16.636979 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-test-feedback
179 03:05:16.637449 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-test-raise
180 03:05:16.637914 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-test-reference
181 03:05:16.638416 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-test-runner
182 03:05:16.638927 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-test-set
183 03:05:16.639414 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-test-shell
184 03:05:16.639899 Updating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-add-keys (debian)
185 03:05:16.640470 Updating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-add-sources (debian)
186 03:05:16.640993 Updating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-install-packages (debian)
187 03:05:16.641495 Updating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-installed-packages (debian)
188 03:05:16.641986 Updating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/bin/lava-os-build (debian)
189 03:05:16.642415 Creating /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/environment
190 03:05:16.642781 LAVA metadata
191 03:05:16.643037 - LAVA_JOB_ID=957122
192 03:05:16.643252 - LAVA_DISPATCHER_IP=192.168.6.2
193 03:05:16.643605 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 03:05:16.644596 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 03:05:16.644909 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 03:05:16.645117 skipped lava-vland-overlay
197 03:05:16.645358 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 03:05:16.645612 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 03:05:16.645829 skipped lava-multinode-overlay
200 03:05:16.646071 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 03:05:16.646319 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 03:05:16.646565 Loading test definitions
203 03:05:16.646839 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 03:05:16.647057 Using /lava-957122 at stage 0
205 03:05:16.648156 uuid=957122_1.6.2.4.1 testdef=None
206 03:05:16.648460 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 03:05:16.648723 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 03:05:16.650278 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 03:05:16.651061 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 03:05:16.652978 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 03:05:16.653796 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 03:05:16.655594 runner path: /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/0/tests/0_timesync-off test_uuid 957122_1.6.2.4.1
215 03:05:16.656165 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 03:05:16.656976 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 03:05:16.657214 Using /lava-957122 at stage 0
219 03:05:16.657565 Fetching tests from https://github.com/kernelci/test-definitions.git
220 03:05:16.657852 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/0/tests/1_kselftest-alsa'
221 03:05:20.193518 Running '/usr/bin/git checkout kernelci.org
222 03:05:20.459885 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 03:05:20.461381 uuid=957122_1.6.2.4.5 testdef=None
224 03:05:20.461735 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 03:05:20.462498 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 03:05:20.465632 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 03:05:20.466459 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 03:05:20.470169 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 03:05:20.471017 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 03:05:20.474556 runner path: /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/0/tests/1_kselftest-alsa test_uuid 957122_1.6.2.4.5
234 03:05:20.474838 BOARD='meson-g12b-a311d-libretech-cc'
235 03:05:20.475043 BRANCH='mainline'
236 03:05:20.475240 SKIPFILE='/dev/null'
237 03:05:20.475438 SKIP_INSTALL='True'
238 03:05:20.475633 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 03:05:20.475832 TST_CASENAME=''
240 03:05:20.476049 TST_CMDFILES='alsa'
241 03:05:20.476586 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 03:05:20.477375 Creating lava-test-runner.conf files
244 03:05:20.477581 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/957122/lava-overlay-jgb4l32j/lava-957122/0 for stage 0
245 03:05:20.477924 - 0_timesync-off
246 03:05:20.478162 - 1_kselftest-alsa
247 03:05:20.478490 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 03:05:20.478771 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 03:05:43.777698 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 03:05:43.778145 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 03:05:43.778408 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 03:05:43.778676 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 03:05:43.778940 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 03:05:44.444243 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 03:05:44.444741 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 03:05:44.445030 extracting modules file /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/957122/extract-nfsrootfs-o26e1drq
257 03:05:45.824682 extracting modules file /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/957122/extract-overlay-ramdisk-j5ew213p/ramdisk
258 03:05:47.474601 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 03:05:47.475184 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 03:05:47.475525 [common] Applying overlay to NFS
261 03:05:47.475794 [common] Applying overlay /var/lib/lava/dispatcher/tmp/957122/compress-overlay-3eyvl17u/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/957122/extract-nfsrootfs-o26e1drq
262 03:05:50.803920 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 03:05:50.804515 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 03:05:50.804850 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 03:05:50.805135 Converting downloaded kernel to a uImage
266 03:05:50.805514 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/kernel/Image /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/kernel/uImage
267 03:05:51.283728 output: Image Name:
268 03:05:51.284191 output: Created: Fri Nov 8 03:05:50 2024
269 03:05:51.284409 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 03:05:51.284615 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 03:05:51.284819 output: Load Address: 01080000
272 03:05:51.285021 output: Entry Point: 01080000
273 03:05:51.285220 output:
274 03:05:51.285553 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 03:05:51.285822 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 03:05:51.286094 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 03:05:51.286348 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 03:05:51.286606 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 03:05:51.286863 Building ramdisk /var/lib/lava/dispatcher/tmp/957122/extract-overlay-ramdisk-j5ew213p/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/957122/extract-overlay-ramdisk-j5ew213p/ramdisk
280 03:05:53.400448 >> 166825 blocks
281 03:06:01.094190 Adding RAMdisk u-boot header.
282 03:06:01.094851 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/957122/extract-overlay-ramdisk-j5ew213p/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/957122/extract-overlay-ramdisk-j5ew213p/ramdisk.cpio.gz.uboot
283 03:06:01.331467 output: Image Name:
284 03:06:01.331885 output: Created: Fri Nov 8 03:06:01 2024
285 03:06:01.332355 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 03:06:01.332777 output: Data Size: 23431296 Bytes = 22882.12 KiB = 22.35 MiB
287 03:06:01.333186 output: Load Address: 00000000
288 03:06:01.333586 output: Entry Point: 00000000
289 03:06:01.333991 output:
290 03:06:01.335120 rename /var/lib/lava/dispatcher/tmp/957122/extract-overlay-ramdisk-j5ew213p/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/ramdisk/ramdisk.cpio.gz.uboot
291 03:06:01.335839 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 03:06:01.336427 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 03:06:01.336967 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 03:06:01.337427 No LXC device requested
295 03:06:01.337935 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 03:06:01.338450 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 03:06:01.338952 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 03:06:01.339365 Checking files for TFTP limit of 4294967296 bytes.
299 03:06:01.342042 end: 1 tftp-deploy (duration 00:01:19) [common]
300 03:06:01.342622 start: 2 uboot-action (timeout 00:05:00) [common]
301 03:06:01.343160 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 03:06:01.343664 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 03:06:01.344215 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 03:06:01.344752 Using kernel file from prepare-kernel: 957122/tftp-deploy-1g181j3g/kernel/uImage
305 03:06:01.345384 substitutions:
306 03:06:01.345795 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 03:06:01.346204 - {DTB_ADDR}: 0x01070000
308 03:06:01.346607 - {DTB}: 957122/tftp-deploy-1g181j3g/dtb/meson-g12b-a311d-libretech-cc.dtb
309 03:06:01.347012 - {INITRD}: 957122/tftp-deploy-1g181j3g/ramdisk/ramdisk.cpio.gz.uboot
310 03:06:01.347414 - {KERNEL_ADDR}: 0x01080000
311 03:06:01.347810 - {KERNEL}: 957122/tftp-deploy-1g181j3g/kernel/uImage
312 03:06:01.348244 - {LAVA_MAC}: None
313 03:06:01.348687 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/957122/extract-nfsrootfs-o26e1drq
314 03:06:01.349097 - {NFS_SERVER_IP}: 192.168.6.2
315 03:06:01.349496 - {PRESEED_CONFIG}: None
316 03:06:01.349888 - {PRESEED_LOCAL}: None
317 03:06:01.350283 - {RAMDISK_ADDR}: 0x08000000
318 03:06:01.350673 - {RAMDISK}: 957122/tftp-deploy-1g181j3g/ramdisk/ramdisk.cpio.gz.uboot
319 03:06:01.351063 - {ROOT_PART}: None
320 03:06:01.351453 - {ROOT}: None
321 03:06:01.351841 - {SERVER_IP}: 192.168.6.2
322 03:06:01.352261 - {TEE_ADDR}: 0x83000000
323 03:06:01.352653 - {TEE}: None
324 03:06:01.353045 Parsed boot commands:
325 03:06:01.353424 - setenv autoload no
326 03:06:01.353809 - setenv initrd_high 0xffffffff
327 03:06:01.354194 - setenv fdt_high 0xffffffff
328 03:06:01.354578 - dhcp
329 03:06:01.354962 - setenv serverip 192.168.6.2
330 03:06:01.355351 - tftpboot 0x01080000 957122/tftp-deploy-1g181j3g/kernel/uImage
331 03:06:01.355745 - tftpboot 0x08000000 957122/tftp-deploy-1g181j3g/ramdisk/ramdisk.cpio.gz.uboot
332 03:06:01.356196 - tftpboot 0x01070000 957122/tftp-deploy-1g181j3g/dtb/meson-g12b-a311d-libretech-cc.dtb
333 03:06:01.356594 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/957122/extract-nfsrootfs-o26e1drq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 03:06:01.356994 - bootm 0x01080000 0x08000000 0x01070000
335 03:06:01.357500 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 03:06:01.359001 start: 2.3 connect-device (timeout 00:05:00) [common]
338 03:06:01.359430 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 03:06:01.375045 Setting prompt string to ['lava-test: # ']
340 03:06:01.376606 end: 2.3 connect-device (duration 00:00:00) [common]
341 03:06:01.377256 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 03:06:01.377837 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 03:06:01.378384 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 03:06:01.379537 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 03:06:01.419357 >> OK - accepted request
346 03:06:01.421161 Returned 0 in 0 seconds
347 03:06:01.522202 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 03:06:01.523263 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 03:06:01.523592 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 03:06:01.523884 Setting prompt string to ['Hit any key to stop autoboot']
352 03:06:01.524202 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 03:06:01.525172 Trying 192.168.56.21...
354 03:06:01.525481 Connected to conserv1.
355 03:06:01.525721 Escape character is '^]'.
356 03:06:01.525955
357 03:06:01.526195 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 03:06:01.526427
359 03:06:12.921524 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 03:06:12.922139 bl2_stage_init 0x01
361 03:06:12.922560 bl2_stage_init 0x81
362 03:06:12.927064 hw id: 0x0000 - pwm id 0x01
363 03:06:12.927513 bl2_stage_init 0xc1
364 03:06:12.927921 bl2_stage_init 0x02
365 03:06:12.928418
366 03:06:12.932636 L0:00000000
367 03:06:12.933096 L1:20000703
368 03:06:12.933510 L2:00008067
369 03:06:12.933915 L3:14000000
370 03:06:12.938265 B2:00402000
371 03:06:12.938699 B1:e0f83180
372 03:06:12.939104
373 03:06:12.939493 TE: 58124
374 03:06:12.939881
375 03:06:12.943938 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 03:06:12.944391
377 03:06:12.944782 Board ID = 1
378 03:06:12.949552 Set A53 clk to 24M
379 03:06:12.949968 Set A73 clk to 24M
380 03:06:12.950355 Set clk81 to 24M
381 03:06:12.955029 A53 clk: 1200 MHz
382 03:06:12.955445 A73 clk: 1200 MHz
383 03:06:12.955830 CLK81: 166.6M
384 03:06:12.956244 smccc: 00012a91
385 03:06:12.960594 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 03:06:12.966216 board id: 1
387 03:06:12.972280 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 03:06:12.982740 fw parse done
389 03:06:12.988642 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 03:06:13.031303 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 03:06:13.042150 PIEI prepare done
392 03:06:13.042577 fastboot data load
393 03:06:13.042971 fastboot data verify
394 03:06:13.047906 verify result: 266
395 03:06:13.053385 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 03:06:13.053832 LPDDR4 probe
397 03:06:13.054226 ddr clk to 1584MHz
398 03:06:13.061409 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 03:06:13.098718
400 03:06:13.099157 dmc_version 0001
401 03:06:13.105420 Check phy result
402 03:06:13.111276 INFO : End of CA training
403 03:06:13.111693 INFO : End of initialization
404 03:06:13.116879 INFO : Training has run successfully!
405 03:06:13.117296 Check phy result
406 03:06:13.122459 INFO : End of initialization
407 03:06:13.122872 INFO : End of read enable training
408 03:06:13.128061 INFO : End of fine write leveling
409 03:06:13.133654 INFO : End of Write leveling coarse delay
410 03:06:13.134078 INFO : Training has run successfully!
411 03:06:13.134472 Check phy result
412 03:06:13.139264 INFO : End of initialization
413 03:06:13.139678 INFO : End of read dq deskew training
414 03:06:13.144832 INFO : End of MPR read delay center optimization
415 03:06:13.150420 INFO : End of write delay center optimization
416 03:06:13.156067 INFO : End of read delay center optimization
417 03:06:13.156493 INFO : End of max read latency training
418 03:06:13.161653 INFO : Training has run successfully!
419 03:06:13.162064 1D training succeed
420 03:06:13.170878 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 03:06:13.218386 Check phy result
422 03:06:13.218834 INFO : End of initialization
423 03:06:13.240835 INFO : End of 2D read delay Voltage center optimization
424 03:06:13.260905 INFO : End of 2D read delay Voltage center optimization
425 03:06:13.312863 INFO : End of 2D write delay Voltage center optimization
426 03:06:13.362159 INFO : End of 2D write delay Voltage center optimization
427 03:06:13.367726 INFO : Training has run successfully!
428 03:06:13.368196
429 03:06:13.368598 channel==0
430 03:06:13.373372 RxClkDly_Margin_A0==88 ps 9
431 03:06:13.373791 TxDqDly_Margin_A0==98 ps 10
432 03:06:13.376669 RxClkDly_Margin_A1==88 ps 9
433 03:06:13.377096 TxDqDly_Margin_A1==98 ps 10
434 03:06:13.382237 TrainedVREFDQ_A0==74
435 03:06:13.382659 TrainedVREFDQ_A1==74
436 03:06:13.387804 VrefDac_Margin_A0==24
437 03:06:13.388256 DeviceVref_Margin_A0==40
438 03:06:13.388649 VrefDac_Margin_A1==24
439 03:06:13.393353 DeviceVref_Margin_A1==40
440 03:06:13.393767
441 03:06:13.394160
442 03:06:13.394549 channel==1
443 03:06:13.394936 RxClkDly_Margin_A0==98 ps 10
444 03:06:13.396749 TxDqDly_Margin_A0==88 ps 9
445 03:06:13.402387 RxClkDly_Margin_A1==98 ps 10
446 03:06:13.402883 TxDqDly_Margin_A1==88 ps 9
447 03:06:13.403281 TrainedVREFDQ_A0==77
448 03:06:13.407939 TrainedVREFDQ_A1==77
449 03:06:13.408419 VrefDac_Margin_A0==22
450 03:06:13.413633 DeviceVref_Margin_A0==37
451 03:06:13.414168 VrefDac_Margin_A1==22
452 03:06:13.414608 DeviceVref_Margin_A1==37
453 03:06:13.415039
454 03:06:13.422484 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 03:06:13.422944
456 03:06:13.450464 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 03:06:13.450987 2D training succeed
458 03:06:13.461677 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 03:06:13.462125 auto size-- 65535DDR cs0 size: 2048MB
460 03:06:13.462519 DDR cs1 size: 2048MB
461 03:06:13.467283 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 03:06:13.467732 cs0 DataBus test pass
463 03:06:13.472915 cs1 DataBus test pass
464 03:06:13.473343 cs0 AddrBus test pass
465 03:06:13.478480 cs1 AddrBus test pass
466 03:06:13.478900
467 03:06:13.479293 100bdlr_step_size ps== 420
468 03:06:13.479688 result report
469 03:06:13.484180 boot times 0Enable ddr reg access
470 03:06:13.490587 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 03:06:13.504110 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 03:06:14.076114 0.0;M3 CHK:0;cm4_sp_mode 0
473 03:06:14.076748 MVN_1=0x00000000
474 03:06:14.081460 MVN_2=0x00000000
475 03:06:14.087235 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 03:06:14.087676 OPS=0x10
477 03:06:14.088124 ring efuse init
478 03:06:14.088536 chipver efuse init
479 03:06:14.092819 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 03:06:14.098442 [0.018961 Inits done]
481 03:06:14.098869 secure task start!
482 03:06:14.099279 high task start!
483 03:06:14.103010 low task start!
484 03:06:14.103457 run into bl31
485 03:06:14.109692 NOTICE: BL31: v1.3(release):4fc40b1
486 03:06:14.117448 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 03:06:14.117880 NOTICE: BL31: G12A normal boot!
488 03:06:14.142830 NOTICE: BL31: BL33 decompress pass
489 03:06:14.148524 ERROR: Error initializing runtime service opteed_fast
490 03:06:15.381586
491 03:06:15.382222
492 03:06:15.389960 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 03:06:15.390432
494 03:06:15.390847 Model: Libre Computer AML-A311D-CC Alta
495 03:06:15.598517 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 03:06:15.621694 DRAM: 2 GiB (effective 3.8 GiB)
497 03:06:15.764818 Core: 408 devices, 31 uclasses, devicetree: separate
498 03:06:15.770562 WDT: Not starting watchdog@f0d0
499 03:06:15.802957 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 03:06:15.815271 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 03:06:15.820247 ** Bad device specification mmc 0 **
502 03:06:15.830588 Card did not respond to voltage select! : -110
503 03:06:15.838271 ** Bad device specification mmc 0 **
504 03:06:15.838735 Couldn't find partition mmc 0
505 03:06:15.846574 Card did not respond to voltage select! : -110
506 03:06:15.852123 ** Bad device specification mmc 0 **
507 03:06:15.852556 Couldn't find partition mmc 0
508 03:06:15.857173 Error: could not access storage.
509 03:06:17.122084 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 03:06:17.122769 bl2_stage_init 0x01
511 03:06:17.123246 bl2_stage_init 0x81
512 03:06:17.127411 hw id: 0x0000 - pwm id 0x01
513 03:06:17.127909 bl2_stage_init 0xc1
514 03:06:17.128383 bl2_stage_init 0x02
515 03:06:17.128805
516 03:06:17.133035 L0:00000000
517 03:06:17.133500 L1:20000703
518 03:06:17.133921 L2:00008067
519 03:06:17.134330 L3:14000000
520 03:06:17.138696 B2:00402000
521 03:06:17.139290 B1:e0f83180
522 03:06:17.139691
523 03:06:17.139916 TE: 58167
524 03:06:17.140174
525 03:06:17.144273 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 03:06:17.144656
527 03:06:17.145124 Board ID = 1
528 03:06:17.149864 Set A53 clk to 24M
529 03:06:17.150249 Set A73 clk to 24M
530 03:06:17.150466 Set clk81 to 24M
531 03:06:17.155571 A53 clk: 1200 MHz
532 03:06:17.156179 A73 clk: 1200 MHz
533 03:06:17.156552 CLK81: 166.6M
534 03:06:17.156803 smccc: 00012abd
535 03:06:17.161039 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 03:06:17.166737 board id: 1
537 03:06:17.172564 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 03:06:17.183178 fw parse done
539 03:06:17.189145 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 03:06:17.231831 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 03:06:17.242711 PIEI prepare done
542 03:06:17.243512 fastboot data load
543 03:06:17.243799 fastboot data verify
544 03:06:17.248342 verify result: 266
545 03:06:17.253986 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 03:06:17.254396 LPDDR4 probe
547 03:06:17.254653 ddr clk to 1584MHz
548 03:06:17.261819 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 03:06:17.299278
550 03:06:17.299896 dmc_version 0001
551 03:06:17.305937 Check phy result
552 03:06:17.311777 INFO : End of CA training
553 03:06:17.312342 INFO : End of initialization
554 03:06:17.317349 INFO : Training has run successfully!
555 03:06:17.317858 Check phy result
556 03:06:17.322963 INFO : End of initialization
557 03:06:17.323477 INFO : End of read enable training
558 03:06:17.328565 INFO : End of fine write leveling
559 03:06:17.334245 INFO : End of Write leveling coarse delay
560 03:06:17.334783 INFO : Training has run successfully!
561 03:06:17.335208 Check phy result
562 03:06:17.339753 INFO : End of initialization
563 03:06:17.340297 INFO : End of read dq deskew training
564 03:06:17.345342 INFO : End of MPR read delay center optimization
565 03:06:17.350953 INFO : End of write delay center optimization
566 03:06:17.356574 INFO : End of read delay center optimization
567 03:06:17.357112 INFO : End of max read latency training
568 03:06:17.362165 INFO : Training has run successfully!
569 03:06:17.362672 1D training succeed
570 03:06:17.371499 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 03:06:17.419070 Check phy result
572 03:06:17.419501 INFO : End of initialization
573 03:06:17.442203 INFO : End of 2D read delay Voltage center optimization
574 03:06:17.461727 INFO : End of 2D read delay Voltage center optimization
575 03:06:17.513796 INFO : End of 2D write delay Voltage center optimization
576 03:06:17.564488 INFO : End of 2D write delay Voltage center optimization
577 03:06:17.568658 INFO : Training has run successfully!
578 03:06:17.568968
579 03:06:17.569182 channel==0
580 03:06:17.574362 RxClkDly_Margin_A0==88 ps 9
581 03:06:17.575038 TxDqDly_Margin_A0==98 ps 10
582 03:06:17.580095 RxClkDly_Margin_A1==88 ps 9
583 03:06:17.580776 TxDqDly_Margin_A1==98 ps 10
584 03:06:17.581249 TrainedVREFDQ_A0==74
585 03:06:17.585621 TrainedVREFDQ_A1==76
586 03:06:17.586225 VrefDac_Margin_A0==25
587 03:06:17.586697 DeviceVref_Margin_A0==40
588 03:06:17.591140 VrefDac_Margin_A1==24
589 03:06:17.591524 DeviceVref_Margin_A1==38
590 03:06:17.591739
591 03:06:17.591951
592 03:06:17.596668 channel==1
593 03:06:17.597088 RxClkDly_Margin_A0==98 ps 10
594 03:06:17.597303 TxDqDly_Margin_A0==88 ps 9
595 03:06:17.602265 RxClkDly_Margin_A1==88 ps 9
596 03:06:17.602677 TxDqDly_Margin_A1==88 ps 9
597 03:06:17.607822 TrainedVREFDQ_A0==75
598 03:06:17.608222 TrainedVREFDQ_A1==77
599 03:06:17.608444 VrefDac_Margin_A0==22
600 03:06:17.613416 DeviceVref_Margin_A0==39
601 03:06:17.613736 VrefDac_Margin_A1==24
602 03:06:17.618991 DeviceVref_Margin_A1==37
603 03:06:17.619324
604 03:06:17.619534 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 03:06:17.619742
606 03:06:17.652682 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
607 03:06:17.653308 2D training succeed
608 03:06:17.658278 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 03:06:17.663925 auto size-- 65535DDR cs0 size: 2048MB
610 03:06:17.664602 DDR cs1 size: 2048MB
611 03:06:17.669591 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 03:06:17.670021 cs0 DataBus test pass
613 03:06:17.675085 cs1 DataBus test pass
614 03:06:17.675489 cs0 AddrBus test pass
615 03:06:17.675705 cs1 AddrBus test pass
616 03:06:17.675912
617 03:06:17.680636 100bdlr_step_size ps== 420
618 03:06:17.681028 result report
619 03:06:17.686262 boot times 0Enable ddr reg access
620 03:06:17.691544 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 03:06:17.704995 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 03:06:18.278768 0.0;M3 CHK:0;cm4_sp_mode 0
623 03:06:18.279391 MVN_1=0x00000000
624 03:06:18.284241 MVN_2=0x00000000
625 03:06:18.289860 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 03:06:18.290162 OPS=0x10
627 03:06:18.290377 ring efuse init
628 03:06:18.290589 chipver efuse init
629 03:06:18.295461 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 03:06:18.301086 [0.018960 Inits done]
631 03:06:18.301371 secure task start!
632 03:06:18.301582 high task start!
633 03:06:18.305673 low task start!
634 03:06:18.305966 run into bl31
635 03:06:18.312333 NOTICE: BL31: v1.3(release):4fc40b1
636 03:06:18.320150 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 03:06:18.320435 NOTICE: BL31: G12A normal boot!
638 03:06:18.345600 NOTICE: BL31: BL33 decompress pass
639 03:06:18.351295 ERROR: Error initializing runtime service opteed_fast
640 03:06:19.584385
641 03:06:19.585066
642 03:06:19.592620 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 03:06:19.593143
644 03:06:19.593615 Model: Libre Computer AML-A311D-CC Alta
645 03:06:19.801194 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 03:06:19.824575 DRAM: 2 GiB (effective 3.8 GiB)
647 03:06:19.967543 Core: 408 devices, 31 uclasses, devicetree: separate
648 03:06:19.973388 WDT: Not starting watchdog@f0d0
649 03:06:20.005536 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 03:06:20.018120 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 03:06:20.023115 ** Bad device specification mmc 0 **
652 03:06:20.033325 Card did not respond to voltage select! : -110
653 03:06:20.041050 ** Bad device specification mmc 0 **
654 03:06:20.041556 Couldn't find partition mmc 0
655 03:06:20.049359 Card did not respond to voltage select! : -110
656 03:06:20.054821 ** Bad device specification mmc 0 **
657 03:06:20.055362 Couldn't find partition mmc 0
658 03:06:20.059852 Error: could not access storage.
659 03:06:20.403583 Net: eth0: ethernet@ff3f0000
660 03:06:20.404258 starting USB...
661 03:06:20.655397 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 03:06:20.656073 Starting the controller
663 03:06:20.662197 USB XHCI 1.10
664 03:06:22.372327 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
665 03:06:22.373041 bl2_stage_init 0x81
666 03:06:22.377694 hw id: 0x0000 - pwm id 0x01
667 03:06:22.378217 bl2_stage_init 0xc1
668 03:06:22.378686 bl2_stage_init 0x02
669 03:06:22.379141
670 03:06:22.383259 L0:00000000
671 03:06:22.383752 L1:20000703
672 03:06:22.384266 L2:00008067
673 03:06:22.384727 L3:14000000
674 03:06:22.385170 B2:00402000
675 03:06:22.389018 B1:e0f83180
676 03:06:22.389522
677 03:06:22.389985 TE: 58150
678 03:06:22.390441
679 03:06:22.394406 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 03:06:22.394907
681 03:06:22.395374 Board ID = 1
682 03:06:22.400079 Set A53 clk to 24M
683 03:06:22.400574 Set A73 clk to 24M
684 03:06:22.401032 Set clk81 to 24M
685 03:06:22.405584 A53 clk: 1200 MHz
686 03:06:22.406072 A73 clk: 1200 MHz
687 03:06:22.406528 CLK81: 166.6M
688 03:06:22.406973 smccc: 00012aab
689 03:06:22.411190 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 03:06:22.416798 board id: 1
691 03:06:22.422701 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 03:06:22.433325 fw parse done
693 03:06:22.439214 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 03:06:22.481845 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 03:06:22.492709 PIEI prepare done
696 03:06:22.493239 fastboot data load
697 03:06:22.493703 fastboot data verify
698 03:06:22.498283 verify result: 266
699 03:06:22.504045 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 03:06:22.504565 LPDDR4 probe
701 03:06:22.505024 ddr clk to 1584MHz
702 03:06:22.511893 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 03:06:22.549324
704 03:06:22.549942 dmc_version 0001
705 03:06:22.555823 Check phy result
706 03:06:22.561718 INFO : End of CA training
707 03:06:22.562228 INFO : End of initialization
708 03:06:22.567281 INFO : Training has run successfully!
709 03:06:22.567801 Check phy result
710 03:06:22.572903 INFO : End of initialization
711 03:06:22.573401 INFO : End of read enable training
712 03:06:22.578469 INFO : End of fine write leveling
713 03:06:22.584079 INFO : End of Write leveling coarse delay
714 03:06:22.584577 INFO : Training has run successfully!
715 03:06:22.585034 Check phy result
716 03:06:22.589648 INFO : End of initialization
717 03:06:22.590137 INFO : End of read dq deskew training
718 03:06:22.595278 INFO : End of MPR read delay center optimization
719 03:06:22.600852 INFO : End of write delay center optimization
720 03:06:22.606459 INFO : End of read delay center optimization
721 03:06:22.606947 INFO : End of max read latency training
722 03:06:22.612097 INFO : Training has run successfully!
723 03:06:22.612584 1D training succeed
724 03:06:22.621350 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 03:06:22.668938 Check phy result
726 03:06:22.669442 INFO : End of initialization
727 03:06:22.690731 INFO : End of 2D read delay Voltage center optimization
728 03:06:22.710985 INFO : End of 2D read delay Voltage center optimization
729 03:06:22.763096 INFO : End of 2D write delay Voltage center optimization
730 03:06:22.812403 INFO : End of 2D write delay Voltage center optimization
731 03:06:22.817971 INFO : Training has run successfully!
732 03:06:22.818460
733 03:06:22.818922 channel==0
734 03:06:22.823540 RxClkDly_Margin_A0==88 ps 9
735 03:06:22.824093 TxDqDly_Margin_A0==108 ps 11
736 03:06:22.826883 RxClkDly_Margin_A1==88 ps 9
737 03:06:22.827373 TxDqDly_Margin_A1==98 ps 10
738 03:06:22.832403 TrainedVREFDQ_A0==74
739 03:06:22.832898 TrainedVREFDQ_A1==74
740 03:06:22.837995 VrefDac_Margin_A0==25
741 03:06:22.838491 DeviceVref_Margin_A0==40
742 03:06:22.838945 VrefDac_Margin_A1==25
743 03:06:22.843596 DeviceVref_Margin_A1==40
744 03:06:22.844110
745 03:06:22.844573
746 03:06:22.845023 channel==1
747 03:06:22.845469 RxClkDly_Margin_A0==98 ps 10
748 03:06:22.849117 TxDqDly_Margin_A0==98 ps 10
749 03:06:22.849608 RxClkDly_Margin_A1==98 ps 10
750 03:06:22.854765 TxDqDly_Margin_A1==108 ps 11
751 03:06:22.855254 TrainedVREFDQ_A0==77
752 03:06:22.855715 TrainedVREFDQ_A1==78
753 03:06:22.860380 VrefDac_Margin_A0==22
754 03:06:22.860870 DeviceVref_Margin_A0==37
755 03:06:22.865870 VrefDac_Margin_A1==22
756 03:06:22.866355 DeviceVref_Margin_A1==36
757 03:06:22.866811
758 03:06:22.871598 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 03:06:22.872118
760 03:06:22.899589 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
761 03:06:22.905185 2D training succeed
762 03:06:22.910616 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 03:06:22.911106 auto size-- 65535DDR cs0 size: 2048MB
764 03:06:22.916230 DDR cs1 size: 2048MB
765 03:06:22.916715 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 03:06:22.921892 cs0 DataBus test pass
767 03:06:22.922374 cs1 DataBus test pass
768 03:06:22.922826 cs0 AddrBus test pass
769 03:06:22.927428 cs1 AddrBus test pass
770 03:06:22.927912
771 03:06:22.928413 100bdlr_step_size ps== 426
772 03:06:22.933031 result report
773 03:06:22.933536 boot times 0Enable ddr reg access
774 03:06:22.941131 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 03:06:22.954586 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 03:06:23.528340 0.0;M3 CHK:0;cm4_sp_mode 0
777 03:06:23.529000 MVN_1=0x00000000
778 03:06:23.533687 MVN_2=0x00000000
779 03:06:23.539509 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 03:06:23.539842 OPS=0x10
781 03:06:23.540162 ring efuse init
782 03:06:23.540579 chipver efuse init
783 03:06:23.545334 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 03:06:23.550833 [0.018961 Inits done]
785 03:06:23.551338 secure task start!
786 03:06:23.551739 high task start!
787 03:06:23.555406 low task start!
788 03:06:23.555900 run into bl31
789 03:06:23.562058 NOTICE: BL31: v1.3(release):4fc40b1
790 03:06:23.569901 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 03:06:23.570417 NOTICE: BL31: G12A normal boot!
792 03:06:23.595251 NOTICE: BL31: BL33 decompress pass
793 03:06:23.600945 ERROR: Error initializing runtime service opteed_fast
794 03:06:24.833809
795 03:06:24.834445
796 03:06:24.842191 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 03:06:24.842708
798 03:06:24.843146 Model: Libre Computer AML-A311D-CC Alta
799 03:06:25.050679 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 03:06:25.073978 DRAM: 2 GiB (effective 3.8 GiB)
801 03:06:25.217005 Core: 408 devices, 31 uclasses, devicetree: separate
802 03:06:25.222865 WDT: Not starting watchdog@f0d0
803 03:06:25.255155 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 03:06:25.267548 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 03:06:25.272581 ** Bad device specification mmc 0 **
806 03:06:25.282896 Card did not respond to voltage select! : -110
807 03:06:25.290590 ** Bad device specification mmc 0 **
808 03:06:25.291089 Couldn't find partition mmc 0
809 03:06:25.298894 Card did not respond to voltage select! : -110
810 03:06:25.304405 ** Bad device specification mmc 0 **
811 03:06:25.304904 Couldn't find partition mmc 0
812 03:06:25.309465 Error: could not access storage.
813 03:06:25.652015 Net: eth0: ethernet@ff3f0000
814 03:06:25.652645 starting USB...
815 03:06:25.903764 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 03:06:25.904381 Starting the controller
817 03:06:25.910739 USB XHCI 1.10
818 03:06:28.072397 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 03:06:28.073043 bl2_stage_init 0x01
820 03:06:28.073487 bl2_stage_init 0x81
821 03:06:28.078041 hw id: 0x0000 - pwm id 0x01
822 03:06:28.078541 bl2_stage_init 0xc1
823 03:06:28.078971 bl2_stage_init 0x02
824 03:06:28.079386
825 03:06:28.083540 L0:00000000
826 03:06:28.084068 L1:20000703
827 03:06:28.084498 L2:00008067
828 03:06:28.084909 L3:14000000
829 03:06:28.086471 B2:00402000
830 03:06:28.086957 B1:e0f83180
831 03:06:28.087374
832 03:06:28.087781 TE: 58167
833 03:06:28.088233
834 03:06:28.097584 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 03:06:28.098081
836 03:06:28.098505 Board ID = 1
837 03:06:28.098910 Set A53 clk to 24M
838 03:06:28.099312 Set A73 clk to 24M
839 03:06:28.103206 Set clk81 to 24M
840 03:06:28.103694 A53 clk: 1200 MHz
841 03:06:28.104147 A73 clk: 1200 MHz
842 03:06:28.106723 CLK81: 166.6M
843 03:06:28.107208 smccc: 00012abe
844 03:06:28.112204 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 03:06:28.117827 board id: 1
846 03:06:28.123039 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 03:06:28.133633 fw parse done
848 03:06:28.139698 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 03:06:28.182081 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 03:06:28.193035 PIEI prepare done
851 03:06:28.193523 fastboot data load
852 03:06:28.193946 fastboot data verify
853 03:06:28.198640 verify result: 266
854 03:06:28.204253 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 03:06:28.204743 LPDDR4 probe
856 03:06:28.205159 ddr clk to 1584MHz
857 03:06:28.212229 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 03:06:28.249461
859 03:06:28.249972 dmc_version 0001
860 03:06:28.256158 Check phy result
861 03:06:28.262010 INFO : End of CA training
862 03:06:28.262498 INFO : End of initialization
863 03:06:28.267612 INFO : Training has run successfully!
864 03:06:28.268138 Check phy result
865 03:06:28.273212 INFO : End of initialization
866 03:06:28.273694 INFO : End of read enable training
867 03:06:28.278804 INFO : End of fine write leveling
868 03:06:28.284397 INFO : End of Write leveling coarse delay
869 03:06:28.284883 INFO : Training has run successfully!
870 03:06:28.285304 Check phy result
871 03:06:28.290005 INFO : End of initialization
872 03:06:28.290488 INFO : End of read dq deskew training
873 03:06:28.295588 INFO : End of MPR read delay center optimization
874 03:06:28.301215 INFO : End of write delay center optimization
875 03:06:28.306803 INFO : End of read delay center optimization
876 03:06:28.307292 INFO : End of max read latency training
877 03:06:28.312406 INFO : Training has run successfully!
878 03:06:28.312891 1D training succeed
879 03:06:28.321547 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 03:06:28.369179 Check phy result
881 03:06:28.369686 INFO : End of initialization
882 03:06:28.390990 INFO : End of 2D read delay Voltage center optimization
883 03:06:28.411226 INFO : End of 2D read delay Voltage center optimization
884 03:06:28.463258 INFO : End of 2D write delay Voltage center optimization
885 03:06:28.512596 INFO : End of 2D write delay Voltage center optimization
886 03:06:28.518173 INFO : Training has run successfully!
887 03:06:28.518678
888 03:06:28.519105 channel==0
889 03:06:28.523780 RxClkDly_Margin_A0==88 ps 9
890 03:06:28.524328 TxDqDly_Margin_A0==98 ps 10
891 03:06:28.529365 RxClkDly_Margin_A1==88 ps 9
892 03:06:28.529868 TxDqDly_Margin_A1==88 ps 9
893 03:06:28.530315 TrainedVREFDQ_A0==74
894 03:06:28.535062 TrainedVREFDQ_A1==74
895 03:06:28.535589 VrefDac_Margin_A0==25
896 03:06:28.536051 DeviceVref_Margin_A0==40
897 03:06:28.540560 VrefDac_Margin_A1==25
898 03:06:28.541073 DeviceVref_Margin_A1==40
899 03:06:28.541467
900 03:06:28.541856
901 03:06:28.542243 channel==1
902 03:06:28.546254 RxClkDly_Margin_A0==98 ps 10
903 03:06:28.546818 TxDqDly_Margin_A0==98 ps 10
904 03:06:28.551805 RxClkDly_Margin_A1==88 ps 9
905 03:06:28.552362 TxDqDly_Margin_A1==88 ps 9
906 03:06:28.557372 TrainedVREFDQ_A0==77
907 03:06:28.557894 TrainedVREFDQ_A1==77
908 03:06:28.558301 VrefDac_Margin_A0==22
909 03:06:28.562988 DeviceVref_Margin_A0==37
910 03:06:28.563475 VrefDac_Margin_A1==24
911 03:06:28.568547 DeviceVref_Margin_A1==37
912 03:06:28.569031
913 03:06:28.569437 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 03:06:28.569836
915 03:06:28.602080 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
916 03:06:28.602627 2D training succeed
917 03:06:28.607716 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 03:06:28.613328 auto size-- 65535DDR cs0 size: 2048MB
919 03:06:28.613807 DDR cs1 size: 2048MB
920 03:06:28.618995 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 03:06:28.619477 cs0 DataBus test pass
922 03:06:28.624517 cs1 DataBus test pass
923 03:06:28.624984 cs0 AddrBus test pass
924 03:06:28.625376 cs1 AddrBus test pass
925 03:06:28.625766
926 03:06:28.630111 100bdlr_step_size ps== 420
927 03:06:28.630597 result report
928 03:06:28.635719 boot times 0Enable ddr reg access
929 03:06:28.641042 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 03:06:28.654452 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 03:06:29.228166 0.0;M3 CHK:0;cm4_sp_mode 0
932 03:06:29.228789 MVN_1=0x00000000
933 03:06:29.233643 MVN_2=0x00000000
934 03:06:29.239367 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 03:06:29.239860 OPS=0x10
936 03:06:29.240328 ring efuse init
937 03:06:29.240744 chipver efuse init
938 03:06:29.245007 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 03:06:29.250647 [0.018961 Inits done]
940 03:06:29.251151 secure task start!
941 03:06:29.251579 high task start!
942 03:06:29.255202 low task start!
943 03:06:29.255687 run into bl31
944 03:06:29.261815 NOTICE: BL31: v1.3(release):4fc40b1
945 03:06:29.269615 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 03:06:29.270103 NOTICE: BL31: G12A normal boot!
947 03:06:29.295001 NOTICE: BL31: BL33 decompress pass
948 03:06:29.300627 ERROR: Error initializing runtime service opteed_fast
949 03:06:30.533560
950 03:06:30.534004
951 03:06:30.542070 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 03:06:30.542497
953 03:06:30.542799 Model: Libre Computer AML-A311D-CC Alta
954 03:06:30.750555 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 03:06:30.773818 DRAM: 2 GiB (effective 3.8 GiB)
956 03:06:30.916745 Core: 408 devices, 31 uclasses, devicetree: separate
957 03:06:30.922543 WDT: Not starting watchdog@f0d0
958 03:06:30.954837 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 03:06:30.967275 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 03:06:30.972271 ** Bad device specification mmc 0 **
961 03:06:30.982602 Card did not respond to voltage select! : -110
962 03:06:30.990297 ** Bad device specification mmc 0 **
963 03:06:30.990683 Couldn't find partition mmc 0
964 03:06:30.998564 Card did not respond to voltage select! : -110
965 03:06:31.004104 ** Bad device specification mmc 0 **
966 03:06:31.004584 Couldn't find partition mmc 0
967 03:06:31.009164 Error: could not access storage.
968 03:06:31.351625 Net: eth0: ethernet@ff3f0000
969 03:06:31.352205 starting USB...
970 03:06:31.603553 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 03:06:31.604167 Starting the controller
972 03:06:31.610394 USB XHCI 1.10
973 03:06:33.164701 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
974 03:06:33.172931 scanning usb for storage devices... 0 Storage Device(s) found
976 03:06:33.224561 Hit any key to stop autoboot: 1
977 03:06:33.225378 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
978 03:06:33.225999 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
979 03:06:33.226493 Setting prompt string to ['=>']
980 03:06:33.226995 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
981 03:06:33.240519 0
982 03:06:33.241443 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
983 03:06:33.241967 Sending with 10 millisecond of delay
985 03:06:34.376476 => setenv autoload no
986 03:06:34.387278 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
987 03:06:34.392186 setenv autoload no
988 03:06:34.392934 Sending with 10 millisecond of delay
990 03:06:36.189272 => setenv initrd_high 0xffffffff
991 03:06:36.200052 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
992 03:06:36.200874 setenv initrd_high 0xffffffff
993 03:06:36.201591 Sending with 10 millisecond of delay
995 03:06:37.817545 => setenv fdt_high 0xffffffff
996 03:06:37.828317 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
997 03:06:37.829116 setenv fdt_high 0xffffffff
998 03:06:37.829835 Sending with 10 millisecond of delay
1000 03:06:38.121629 => dhcp
1001 03:06:38.132388 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1002 03:06:38.133197 dhcp
1003 03:06:38.133634 Speed: 1000, full duplex
1004 03:06:38.134044 BOOTP broadcast 1
1005 03:06:38.319905 DHCP client bound to address 192.168.6.27 (187 ms)
1006 03:06:38.320710 Sending with 10 millisecond of delay
1008 03:06:39.997192 => setenv serverip 192.168.6.2
1009 03:06:40.008503 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1010 03:06:40.009420 setenv serverip 192.168.6.2
1011 03:06:40.010122 Sending with 10 millisecond of delay
1013 03:06:43.735435 => tftpboot 0x01080000 957122/tftp-deploy-1g181j3g/kernel/uImage
1014 03:06:43.746515 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1015 03:06:43.747641 tftpboot 0x01080000 957122/tftp-deploy-1g181j3g/kernel/uImage
1016 03:06:43.748289 Speed: 1000, full duplex
1017 03:06:43.748855 Using ethernet@ff3f0000 device
1018 03:06:43.749494 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1019 03:06:43.754861 Filename '957122/tftp-deploy-1g181j3g/kernel/uImage'.
1020 03:06:43.758832 Load address: 0x1080000
1021 03:06:46.853025 Loading: *################################################## 43.6 MiB
1022 03:06:46.853459 14.1 MiB/s
1023 03:06:46.853681 done
1024 03:06:46.857515 Bytes transferred = 45713984 (2b98a40 hex)
1025 03:06:46.858392 Sending with 10 millisecond of delay
1027 03:06:51.547176 => tftpboot 0x08000000 957122/tftp-deploy-1g181j3g/ramdisk/ramdisk.cpio.gz.uboot
1028 03:06:51.558049 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1029 03:06:51.559011 tftpboot 0x08000000 957122/tftp-deploy-1g181j3g/ramdisk/ramdisk.cpio.gz.uboot
1030 03:06:51.559502 Speed: 1000, full duplex
1031 03:06:51.559970 Using ethernet@ff3f0000 device
1032 03:06:51.560895 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1033 03:06:51.572709 Filename '957122/tftp-deploy-1g181j3g/ramdisk/ramdisk.cpio.gz.uboot'.
1034 03:06:51.573306 Load address: 0x8000000
1035 03:06:58.620461 Loading: *#############T ##################################### 22.3 MiB
1036 03:06:58.621129 3.2 MiB/s
1037 03:06:58.621605 done
1038 03:06:58.624517 Bytes transferred = 23431360 (16588c0 hex)
1039 03:06:58.625298 Sending with 10 millisecond of delay
1041 03:07:03.795256 => tftpboot 0x01070000 957122/tftp-deploy-1g181j3g/dtb/meson-g12b-a311d-libretech-cc.dtb
1042 03:07:03.805864 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
1043 03:07:03.806509 tftpboot 0x01070000 957122/tftp-deploy-1g181j3g/dtb/meson-g12b-a311d-libretech-cc.dtb
1044 03:07:03.806759 Speed: 1000, full duplex
1045 03:07:03.806979 Using ethernet@ff3f0000 device
1046 03:07:03.810938 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1047 03:07:03.818281 Filename '957122/tftp-deploy-1g181j3g/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1048 03:07:03.828949 Load address: 0x1070000
1049 03:07:03.838873 Loading: *################################################## 53.4 KiB
1050 03:07:03.839405 3.3 MiB/s
1051 03:07:03.839661 done
1052 03:07:03.845048 Bytes transferred = 54703 (d5af hex)
1053 03:07:03.845653 Sending with 10 millisecond of delay
1055 03:07:17.146223 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/957122/extract-nfsrootfs-o26e1drq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1056 03:07:17.157054 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:44)
1057 03:07:17.157924 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/957122/extract-nfsrootfs-o26e1drq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1058 03:07:17.158626 Sending with 10 millisecond of delay
1060 03:07:19.497447 => bootm 0x01080000 0x08000000 0x01070000
1061 03:07:19.508245 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1062 03:07:19.508633 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:42)
1063 03:07:19.509231 bootm 0x01080000 0x08000000 0x01070000
1064 03:07:19.509483 ## Booting kernel from Legacy Image at 01080000 ...
1065 03:07:19.513463 Image Name:
1066 03:07:19.519051 Image Type: AArch64 Linux Kernel Image (uncompressed)
1067 03:07:19.519459 Data Size: 45713920 Bytes = 43.6 MiB
1068 03:07:19.521078 Load Address: 01080000
1069 03:07:19.527280 Entry Point: 01080000
1070 03:07:19.719506 Verifying Checksum ... OK
1071 03:07:19.720174 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1072 03:07:19.724740 Image Name:
1073 03:07:19.730225 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1074 03:07:19.730663 Data Size: 23431296 Bytes = 22.3 MiB
1075 03:07:19.732557 Load Address: 00000000
1076 03:07:19.739712 Entry Point: 00000000
1077 03:07:19.837965 Verifying Checksum ... OK
1078 03:07:19.838522 ## Flattened Device Tree blob at 01070000
1079 03:07:19.843268 Booting using the fdt blob at 0x1070000
1080 03:07:19.843707 Working FDT set to 1070000
1081 03:07:19.847866 Loading Kernel Image
1082 03:07:19.892443 Loading Ramdisk to 7e9a7000, end 7ffff880 ... OK
1083 03:07:19.900610 Loading Device Tree to 000000007e996000, end 000000007e9a65ae ... OK
1084 03:07:19.901075 Working FDT set to 7e996000
1085 03:07:19.901492
1086 03:07:19.902388 end: 2.4.3 bootloader-commands (duration 00:00:47) [common]
1087 03:07:19.902980 start: 2.4.4 auto-login-action (timeout 00:03:41) [common]
1088 03:07:19.903447 Setting prompt string to ['Linux version [0-9]']
1089 03:07:19.903905 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1090 03:07:19.904420 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1091 03:07:19.905443 Starting kernel ...
1092 03:07:19.905890
1093 03:07:19.940856 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1094 03:07:19.941745 start: 2.4.4.1 login-action (timeout 00:03:41) [common]
1095 03:07:19.942260 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1096 03:07:19.942718 Setting prompt string to []
1097 03:07:19.943194 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1098 03:07:19.943647 Using line separator: #'\n'#
1099 03:07:19.944134 No login prompt set.
1100 03:07:19.944632 Parsing kernel messages
1101 03:07:19.945043 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1102 03:07:19.945837 [login-action] Waiting for messages, (timeout 00:03:41)
1103 03:07:19.946291 Waiting using forced prompt support (timeout 00:01:51)
1104 03:07:19.961120 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j367745-arm64-gcc-12-defconfig-76rmc) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Fri Nov 8 01:13:42 UTC 2024
1105 03:07:19.961624 [ 0.000000] KASLR disabled due to lack of seed
1106 03:07:19.966591 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1107 03:07:19.970279 [ 0.000000] efi: UEFI not found.
1108 03:07:19.981261 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1109 03:07:19.986749 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1110 03:07:19.996054 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1111 03:07:20.007011 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1112 03:07:20.012553 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1113 03:07:20.023706 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1114 03:07:20.034707 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1115 03:07:20.040115 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1116 03:07:20.045609 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1117 03:07:20.051107 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1118 03:07:20.051542 [ 0.000000] Zone ranges:
1119 03:07:20.056644 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1120 03:07:20.062168 [ 0.000000] DMA32 empty
1121 03:07:20.062601 [ 0.000000] Normal empty
1122 03:07:20.067693 [ 0.000000] Movable zone start for each node
1123 03:07:20.073166 [ 0.000000] Early memory node ranges
1124 03:07:20.078672 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1125 03:07:20.084203 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1126 03:07:20.089734 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1127 03:07:20.098398 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1128 03:07:20.122760 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1129 03:07:20.128268 [ 0.000000] psci: probing for conduit method from DT.
1130 03:07:20.128703 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1131 03:07:20.133798 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1132 03:07:20.139314 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1133 03:07:20.144859 [ 0.000000] psci: SMC Calling Convention v1.1
1134 03:07:20.150346 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1135 03:07:20.155894 [ 0.000000] Detected VIPT I-cache on CPU0
1136 03:07:20.161380 [ 0.000000] CPU features: detected: ARM erratum 845719
1137 03:07:20.166914 [ 0.000000] alternatives: applying boot alternatives
1138 03:07:20.183527 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/957122/extract-nfsrootfs-o26e1drq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1139 03:07:20.194587 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1140 03:07:20.200068 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1141 03:07:20.205597 <6>[ 0.000000] Fallback order for Node 0: 0
1142 03:07:20.211110 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1143 03:07:20.216593 <6>[ 0.000000] Policy zone: DMA
1144 03:07:20.222097 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1145 03:07:20.227604 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1146 03:07:20.233160 <6>[ 0.000000] software IO TLB: area num 8.
1147 03:07:20.242159 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1148 03:07:20.288825 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1149 03:07:20.294336 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1150 03:07:20.299817 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1151 03:07:20.305368 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1152 03:07:20.310967 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1153 03:07:20.316411 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1154 03:07:20.322031 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1155 03:07:20.327461 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1156 03:07:20.338520 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1157 03:07:20.349550 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1158 03:07:20.355015 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1159 03:07:20.360569 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1160 03:07:20.360997 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1161 03:07:20.370488 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1162 03:07:20.383163 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1163 03:07:20.394209 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1164 03:07:20.399689 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1165 03:07:20.405200 <6>[ 0.008791] Console: colour dummy device 80x25
1166 03:07:20.416252 <6>[ 0.012941] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1167 03:07:20.421748 <6>[ 0.023295] pid_max: default: 32768 minimum: 301
1168 03:07:20.427316 <6>[ 0.028190] LSM: initializing lsm=capability
1169 03:07:20.432824 <6>[ 0.032731] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1170 03:07:20.438391 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1171 03:07:20.443876 <6>[ 0.052301] rcu: Hierarchical SRCU implementation.
1172 03:07:20.449379 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1173 03:07:20.460397 <6>[ 0.058887] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1174 03:07:20.468821 <6>[ 0.071601] EFI services will not be available.
1175 03:07:20.469265 <6>[ 0.075248] smp: Bringing up secondary CPUs ...
1176 03:07:20.485133 <6>[ 0.077142] Detected VIPT I-cache on CPU1
1177 03:07:20.490677 <6>[ 0.077261] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1178 03:07:20.496169 <6>[ 0.078608] CPU features: detected: Spectre-v2
1179 03:07:20.501694 <6>[ 0.078622] CPU features: detected: Spectre-v4
1180 03:07:20.507196 <6>[ 0.078627] CPU features: detected: Spectre-BHB
1181 03:07:20.512705 <6>[ 0.078632] CPU features: detected: ARM erratum 858921
1182 03:07:20.518211 <6>[ 0.078641] Detected VIPT I-cache on CPU2
1183 03:07:20.523728 <6>[ 0.078715] arch_timer: Enabling local workaround for ARM erratum 858921
1184 03:07:20.529295 <6>[ 0.078732] arch_timer: CPU2: Trapping CNTVCT access
1185 03:07:20.534834 <6>[ 0.078742] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1186 03:07:20.540320 <6>[ 0.083684] Detected VIPT I-cache on CPU3
1187 03:07:20.545824 <6>[ 0.083729] arch_timer: Enabling local workaround for ARM erratum 858921
1188 03:07:20.551341 <6>[ 0.083738] arch_timer: CPU3: Trapping CNTVCT access
1189 03:07:20.556932 <6>[ 0.083746] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1190 03:07:20.562381 <6>[ 0.087639] Detected VIPT I-cache on CPU4
1191 03:07:20.568005 <6>[ 0.087685] arch_timer: Enabling local workaround for ARM erratum 858921
1192 03:07:20.573517 <6>[ 0.087695] arch_timer: CPU4: Trapping CNTVCT access
1193 03:07:20.584515 <6>[ 0.087702] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1194 03:07:20.584819 <6>[ 0.095665] Detected VIPT I-cache on CPU5
1195 03:07:20.595554 <6>[ 0.095712] arch_timer: Enabling local workaround for ARM erratum 858921
1196 03:07:20.595885 <6>[ 0.095722] arch_timer: CPU5: Trapping CNTVCT access
1197 03:07:20.606671 <6>[ 0.095729] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1198 03:07:20.607173 <6>[ 0.095850] smp: Brought up 1 node, 6 CPUs
1199 03:07:20.612259 <6>[ 0.217087] SMP: Total of 6 processors activated.
1200 03:07:20.617757 <6>[ 0.221990] CPU: All CPU(s) started at EL2
1201 03:07:20.623288 <6>[ 0.226333] CPU features: detected: 32-bit EL0 Support
1202 03:07:20.628796 <6>[ 0.231648] CPU features: detected: 32-bit EL1 Support
1203 03:07:20.634324 <6>[ 0.236997] CPU features: detected: CRC32 instructions
1204 03:07:20.639833 <6>[ 0.242398] alternatives: applying system-wide alternatives
1205 03:07:20.657699 <6>[ 0.249603] Memory: 3557436K/4012396K available (17280K kernel code, 4898K rwdata, 11876K rodata, 10432K init, 742K bss, 187796K reserved, 262144K cma-reserved)
1206 03:07:20.658219 <6>[ 0.263938] devtmpfs: initialized
1207 03:07:20.668737 <6>[ 0.273072] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1208 03:07:20.674302 <6>[ 0.277423] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1209 03:07:20.679811 <6>[ 0.288228] 21392 pages in range for non-PLT usage
1210 03:07:20.685344 <6>[ 0.288239] 512912 pages in range for PLT usage
1211 03:07:20.690862 <6>[ 0.289782] pinctrl core: initialized pinctrl subsystem
1212 03:07:20.696391 <6>[ 0.301861] DMI not present or invalid.
1213 03:07:20.701919 <6>[ 0.306166] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1214 03:07:20.707425 <6>[ 0.310895] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1215 03:07:20.718413 <6>[ 0.317673] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1216 03:07:20.724016 <6>[ 0.325773] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1217 03:07:20.729532 <6>[ 0.333255] audit: initializing netlink subsys (disabled)
1218 03:07:20.740502 <5>[ 0.338996] audit: type=2000 audit(0.260:1): state=initialized audit_enabled=0 res=1
1219 03:07:20.746069 <6>[ 0.340408] thermal_sys: Registered thermal governor 'step_wise'
1220 03:07:20.751580 <6>[ 0.346761] thermal_sys: Registered thermal governor 'power_allocator'
1221 03:07:20.757090 <6>[ 0.353021] cpuidle: using governor menu
1222 03:07:20.762644 <6>[ 0.364062] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1223 03:07:20.768220 <6>[ 0.370936] ASID allocator initialised with 65536 entries
1224 03:07:20.776365 <6>[ 0.378511] Serial: AMBA PL011 UART driver
1225 03:07:20.784274 <6>[ 0.389020] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1226 03:07:20.799271 <6>[ 0.404366] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1227 03:07:20.810283 <6>[ 0.407030] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1228 03:07:20.815852 <6>[ 0.420128] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1229 03:07:20.821391 <6>[ 0.423407] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1230 03:07:20.832372 <6>[ 0.431827] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1231 03:07:20.837952 <6>[ 0.439456] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1232 03:07:20.848945 <6>[ 0.453031] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1233 03:07:20.854510 <6>[ 0.455277] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1234 03:07:20.860043 <6>[ 0.461759] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1235 03:07:20.865560 <6>[ 0.468735] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1236 03:07:20.876554 <6>[ 0.475204] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1237 03:07:20.882105 <6>[ 0.482190] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1238 03:07:20.887638 <6>[ 0.488659] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1239 03:07:20.893197 <6>[ 0.495644] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1240 03:07:20.898681 <6>[ 0.503669] ACPI: Interpreter disabled.
1241 03:07:20.904236 <6>[ 0.509067] iommu: Default domain type: Translated
1242 03:07:20.909713 <6>[ 0.511177] iommu: DMA domain TLB invalidation policy: strict mode
1243 03:07:20.915235 <5>[ 0.517884] SCSI subsystem initialized
1244 03:07:20.920748 <6>[ 0.521822] usbcore: registered new interface driver usbfs
1245 03:07:20.926249 <6>[ 0.527235] usbcore: registered new interface driver hub
1246 03:07:20.931780 <6>[ 0.532751] usbcore: registered new device driver usb
1247 03:07:20.937287 <6>[ 0.539014] pps_core: LinuxPPS API ver. 1 registered
1248 03:07:20.942813 <6>[ 0.543171] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1249 03:07:20.948369 <6>[ 0.552492] PTP clock support registered
1250 03:07:20.953858 <6>[ 0.556732] EDAC MC: Ver: 3.0.0
1251 03:07:20.959429 <6>[ 0.560388] scmi_core: SCMI protocol bus registered
1252 03:07:20.959939 <6>[ 0.566041] FPGA manager framework
1253 03:07:20.964913 <6>[ 0.568751] Advanced Linux Sound Architecture Driver Initialized.
1254 03:07:20.970432 <6>[ 0.575721] vgaarb: loaded
1255 03:07:20.975954 <6>[ 0.578259] clocksource: Switched to clocksource arch_sys_counter
1256 03:07:20.981467 <5>[ 0.584393] VFS: Disk quotas dquot_6.6.0
1257 03:07:20.986966 <6>[ 0.588385] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1258 03:07:20.992486 <6>[ 0.595598] pnp: PnP ACPI: disabled
1259 03:07:20.998019 <6>[ 0.604016] NET: Registered PF_INET protocol family
1260 03:07:21.003530 <6>[ 0.604414] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1261 03:07:21.014536 <6>[ 0.614589] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1262 03:07:21.020215 <6>[ 0.620590] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1263 03:07:21.031291 <6>[ 0.628482] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1264 03:07:21.036660 <6>[ 0.636723] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1265 03:07:21.042226 <6>[ 0.644522] TCP: Hash tables configured (established 32768 bind 32768)
1266 03:07:21.047707 <6>[ 0.650994] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1267 03:07:21.058697 <6>[ 0.657839] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1268 03:07:21.064272 <6>[ 0.665269] NET: Registered PF_UNIX/PF_LOCAL protocol family
1269 03:07:21.069770 <6>[ 0.671368] RPC: Registered named UNIX socket transport module.
1270 03:07:21.075289 <6>[ 0.677130] RPC: Registered udp transport module.
1271 03:07:21.080823 <6>[ 0.682034] RPC: Registered tcp transport module.
1272 03:07:21.086382 <6>[ 0.686948] RPC: Registered tcp-with-tls transport module.
1273 03:07:21.091861 <6>[ 0.692642] RPC: Registered tcp NFSv4.1 backchannel transport module.
1274 03:07:21.097374 <6>[ 0.699290] PCI: CLS 0 bytes, default 64
1275 03:07:21.097871 <6>[ 0.703609] Unpacking initramfs...
1276 03:07:21.102903 <6>[ 0.709802] kvm [1]: nv: 554 coarse grained trap handlers
1277 03:07:21.108417 <6>[ 0.712973] kvm [1]: IPA Size Limit: 40 bits
1278 03:07:21.113936 <6>[ 0.718588] kvm [1]: vgic interrupt IRQ9
1279 03:07:21.119458 <6>[ 0.721300] kvm [1]: Hyp nVHE mode initialized successfully
1280 03:07:21.124981 <5>[ 0.728711] Initialise system trusted keyrings
1281 03:07:21.130490 <6>[ 0.731953] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1282 03:07:21.136060 <6>[ 0.738585] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1283 03:07:21.141548 <5>[ 0.744693] NFS: Registering the id_resolver key type
1284 03:07:21.147085 <5>[ 0.749679] Key type id_resolver registered
1285 03:07:21.152605 <5>[ 0.754054] Key type id_legacy registered
1286 03:07:21.158108 <6>[ 0.758292] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1287 03:07:21.163636 <6>[ 0.765179] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1288 03:07:21.171035 <6>[ 0.772993] 9p: Installing v9fs 9p2000 file system support
1289 03:07:21.209101 <5>[ 0.819646] Key type asymmetric registered
1290 03:07:21.214592 <5>[ 0.819683] Asymmetric key parser 'x509' registered
1291 03:07:21.225582 <6>[ 0.823553] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1292 03:07:21.226106 <6>[ 0.831075] io scheduler mq-deadline registered
1293 03:07:21.231184 <6>[ 0.835823] io scheduler kyber registered
1294 03:07:21.236667 <6>[ 0.840086] io scheduler bfq registered
1295 03:07:21.243104 <6>[ 0.847985] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1296 03:07:21.259283 <6>[ 0.866081] ledtrig-cpu: registered to indicate activity on CPUs
1297 03:07:21.291453 <6>[ 0.897121] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1298 03:07:21.311192 <6>[ 0.910533] Serial: 8250/16550 driver, 4 por�<6>[ 0.915083] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1299 03:07:21.314519 <6>[ 0.924714] printk: legacy console [ttyAML0] enabled
1300 03:07:21.320050 <6>[ 0.924714] printk: legacy console [ttyAML0] enabled
1301 03:07:21.325579 <6>[ 0.929514] printk: legacy bootconsole [meson0] disabled
1302 03:07:21.331112 <6>[ 0.929514] printk: legacy bootconsole [meson0] disabled
1303 03:07:21.334613 <6>[ 0.943057] msm_serial: driver initialized
1304 03:07:21.340185 <6>[ 0.945448] SuperH (H)SCI(F) driver initialized
1305 03:07:21.345705 <6>[ 0.949984] STM32 USART driver initialized
1306 03:07:21.351257 <5>[ 0.956198] random: crng init done
1307 03:07:21.351752 <6>[ 0.961822] loop: module loaded
1308 03:07:21.355517 <6>[ 0.963134] megasas: 07.727.03.00-rc1
1309 03:07:21.361468 <6>[ 0.972042] tun: Universal TUN/TAP device driver, 1.6
1310 03:07:21.367023 <6>[ 0.973256] thunder_xcv, ver 1.0
1311 03:07:21.372567 <6>[ 0.975242] thunder_bgx, ver 1.0
1312 03:07:21.373073 <6>[ 0.978680] nicpf, ver 1.0
1313 03:07:21.383593 <6>[ 0.983252] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1314 03:07:21.389356 <6>[ 0.989062] hns3: Copyright (c) 2017 Huawei Corporation.
1315 03:07:21.389879 <6>[ 0.994651] hclge is initializing
1316 03:07:21.394769 <6>[ 0.998181] e1000: Intel(R) PRO/1000 Network Driver
1317 03:07:21.400317 <6>[ 1.003273] e1000: Copyright (c) 1999-2006 Intel Corporation.
1318 03:07:21.405892 <6>[ 1.009293] e1000e: Intel(R) PRO/1000 Network Driver
1319 03:07:21.411439 <6>[ 1.014449] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1320 03:07:21.416996 <6>[ 1.020630] igb: Intel(R) Gigabit Ethernet Network Driver
1321 03:07:21.422525 <6>[ 1.026237] igb: Copyright (c) 2007-2014 Intel Corporation.
1322 03:07:21.428080 <6>[ 1.032069] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1323 03:07:21.439080 <6>[ 1.038542] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1324 03:07:21.439595 <6>[ 1.045304] sky2: driver version 1.30
1325 03:07:21.444681 <6>[ 1.050541] VFIO - User Level meta-driver version: 0.3
1326 03:07:21.450272 <6>[ 1.057897] usbcore: registered new interface driver usb-storage
1327 03:07:21.457421 <6>[ 1.063988] i2c_dev: i2c /dev entries driver
1328 03:07:21.470036 <6>[ 1.075105] sdhci: Secure Digital Host Controller Interface driver
1329 03:07:21.470547 <6>[ 1.075906] sdhci: Copyright(c) Pierre Ossman
1330 03:07:21.481143 <6>[ 1.081646] Synopsys Designware Multimedia Card Interface Driver
1331 03:07:21.486774 <6>[ 1.088155] sdhci-pltfm: SDHCI platform and OF driver helper
1332 03:07:21.487289 <6>[ 1.095803] meson-sm: secure-monitor enabled
1333 03:07:21.499590 <6>[ 1.098334] usbcore: registered new interface driver usbhid
1334 03:07:21.500151 <6>[ 1.102958] usbhid: USB HID core driver
1335 03:07:21.507220 <6>[ 1.117688] NET: Registered PF_PACKET protocol family
1336 03:07:21.512699 <6>[ 1.117779] 9pnet: Installing 9P2000 support
1337 03:07:21.519780 <5>[ 1.121950] Key type dns_resolver registered
1338 03:07:21.525347 <6>[ 1.133554] registered taskstats version 1
1339 03:07:21.530897 <5>[ 1.133712] Loading compiled-in X.509 certificates
1340 03:07:21.534481 <6>[ 1.142367] Demotion targets for Node 0: null
1341 03:07:21.575072 <6>[ 1.185578] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1342 03:07:21.580577 <6>[ 1.185623] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1343 03:07:21.591600 <4>[ 1.195800] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1344 03:07:21.597206 <4>[ 1.198403] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1345 03:07:21.602754 <6>[ 1.205956] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1346 03:07:21.608338 <6>[ 1.215202] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1347 03:07:21.619333 <6>[ 1.218660] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1348 03:07:21.630424 <6>[ 1.226646] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1349 03:07:21.636045 <6>[ 1.236182] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1350 03:07:21.641624 <6>[ 1.242407] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1351 03:07:21.647158 <6>[ 1.248031] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1352 03:07:21.652726 <6>[ 1.255915] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1353 03:07:21.658414 <6>[ 1.263175] hub 1-0:1.0: USB hub found
1354 03:07:21.663875 <6>[ 1.266683] hub 1-0:1.0: 2 ports detected
1355 03:07:21.669467 <6>[ 1.272754] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1356 03:07:21.674971 <6>[ 1.279651] hub 2-0:1.0: USB hub found
1357 03:07:21.680027 <6>[ 1.283228] hub 2-0:1.0: 1 port detected
1358 03:07:21.699954 <6>[ 1.307794] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1359 03:07:21.715285 <6>[ 1.322612] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1360 03:07:21.751335 <6>[ 1.358222] Trying to probe devices needed for running init ...
1361 03:07:21.912067 <6>[ 1.518296] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1362 03:07:22.052569 <6>[ 1.657604] mmc0: new ultra high speed SDR104 SDXC card at address e624
1363 03:07:22.058657 <6>[ 1.659386] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1364 03:07:22.059168 <6>[ 1.664956] mmcblk0: p1
1365 03:07:22.062534 <6>[ 1.672299] Freeing initrd memory: 22880K
1366 03:07:22.100485 <6>[ 1.711023] hub 1-1:1.0: USB hub found
1367 03:07:22.106222 <6>[ 1.711328] hub 1-1:1.0: 4 ports detected
1368 03:07:22.168213 <6>[ 1.774411] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1369 03:07:22.213097 <6>[ 1.823668] hub 2-1:1.0: USB hub found
1370 03:07:22.218779 <6>[ 1.824496] hub 2-1:1.0: 4 ports detected
1371 03:07:34.036110 <6>[ 13.646318] clk: Disabling unused clocks
1372 03:07:34.041452 <6>[ 13.646484] PM: genpd: Disabling unused power domains
1373 03:07:34.049691 <6>[ 13.650181] ALSA device list:
1374 03:07:34.050206 <6>[ 13.653379] No soundcards found.
1375 03:07:34.055124 <6>[ 13.665273] Freeing unused kernel memory: 10432K
1376 03:07:34.061024 <6>[ 13.665375] Run /init as init process
1377 03:07:34.067788 Loading, please wait...
1378 03:07:34.099218 Starting systemd-udevd version 252.22-1~deb12u1
1379 03:07:34.534402 <6>[ 14.144711] mc: Linux media interface: v0.10
1380 03:07:34.541977 <6>[ 14.148723] videodev: Linux video capture interface: v2.00
1381 03:07:34.566681 <6>[ 14.171769] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1382 03:07:34.574617 <4>[ 14.173264] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1383 03:07:34.592380 <6>[ 14.197354] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1384 03:07:34.597841 <6>[ 14.198624] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1385 03:07:34.601318 <6>[ 14.205051] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1386 03:07:34.606884 <6>[ 14.211338] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1387 03:07:34.617987 <6>[ 14.222054] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1388 03:07:34.621592 <6>[ 14.225816] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1389 03:07:34.632647 <6>[ 14.230295] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1390 03:07:34.638154 <6>[ 14.233274] panfrost ffe40000.gpu: clock rate = 24000000
1391 03:07:34.643805 <6>[ 14.237949] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1392 03:07:34.649372 <6>[ 14.237955] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1393 03:07:34.654886 <6>[ 14.237960] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1394 03:07:34.660458 <6>[ 14.237964] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1395 03:07:34.671449 <6>[ 14.238063] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1396 03:07:34.682506 <3>[ 14.243560] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1397 03:07:34.688082 <6>[ 14.267402] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1398 03:07:34.693619 <6>[ 14.272431] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1399 03:07:34.704707 <4>[ 14.286711] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1400 03:07:34.710254 <6>[ 14.290944] Registered IR keymap rc-empty
1401 03:07:34.715823 <6>[ 14.291050] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1402 03:07:34.726879 <6>[ 14.291671] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1403 03:07:34.732464 <3>[ 14.291795] meson-drm ff900000.vpu: DSI transceiver device is disabled
1404 03:07:34.737957 <6>[ 14.292299] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 0
1405 03:07:34.749049 <6>[ 14.293648] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1406 03:07:34.760159 <6>[ 14.293660] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1407 03:07:34.765678 <6>[ 14.293670] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1408 03:07:34.771222 <6>[ 14.295866] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1409 03:07:34.782299 <6>[ 14.295875] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1410 03:07:34.787854 <3>[ 14.336346] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1411 03:07:34.798959 <6>[ 14.340829] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1412 03:07:34.804503 <6>[ 14.342168] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 1
1413 03:07:34.810072 <6>[ 14.345310] meson-vrtc ff8000a8.rtc: registered as rtc0
1414 03:07:34.815565 <6>[ 14.345338] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1415 03:07:34.826681 <6>[ 14.395610] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1416 03:07:34.832243 <6>[ 14.398238] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1417 03:07:34.839211 <6>[ 14.398428] usbcore: registered new device driver onboard-usb-dev
1418 03:07:35.019605 <6>[ 14.447151] rc rc0: sw decoder init
1419 03:07:35.025084 <6>[ 14.447196] meson-ir ff808000.ir: receiver initialized
1420 03:07:35.030609 <6>[ 14.611113] Console: switching to colour frame buffer device 128x48
1421 03:07:35.039901 <6>[ 14.640062] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1422 03:07:35.054675 <6>[ 14.656853] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1423 03:07:35.284455 <6>[ 14.894986] hub 1-1:1.0: USB hub found
1424 03:07:35.289839 <6>[ 14.895324] hub 1-1:1.0: 4 ports detected
1425 03:07:35.296313 <6>[ 14.900005] onboard-usb-dev 1-1: USB disconnect, device number 2
1426 03:07:35.631827 <4>[ 15.242287] rc rc0: two consecutive events of type space
1427 03:07:35.663865 <6>[ 15.270278] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1428 03:07:35.860496 <6>[ 15.471079] hub 1-1:1.0: USB hub found
1429 03:07:35.866202 <6>[ 15.471414] hub 1-1:1.0: 4 ports detected
1430 03:07:35.876196 Begin: Loading essential drivers ... done.
1431 03:07:35.881693 Begin: Running /scripts/init-premount ... done.
1432 03:07:35.887243 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1433 03:07:35.900988 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1434 03:07:35.901487 Device /sys/class/net/end0 found
1435 03:07:35.901950 done.
1436 03:07:35.916862 Begin: Waiting up to 180 secs for any network device to become available ... done.
1437 03:07:35.962784 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.564177] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1438 03:07:35.963306
1439 03:07:36.049297 <6>[ 15.654376] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=31)
1440 03:07:36.060365 <6>[ 15.662988] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1441 03:07:36.065909 <6>[ 15.670288] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1442 03:07:36.071454 <6>[ 15.674168] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1443 03:07:36.081713 <6>[ 15.681817] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1444 03:07:36.312757 <6>[ 15.918968] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1445 03:07:37.236688 IP-Config: no response after 2 secs - giving up
1446 03:07:37.298923 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1447 03:07:39.039221 <6>[ 18.643697] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1448 03:07:39.510280 IP-Config: end0 guessed broadcast address 192.168.6.255
1449 03:07:39.515681 IP-Config: end0 complete (dhcp from 192.168.6.1):
1450 03:07:39.521174 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1451 03:07:39.532256 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1452 03:07:39.532763 rootserver: 192.168.6.1 rootpath:
1453 03:07:39.535701 filename :
1454 03:07:39.649255 done.
1455 03:07:39.659735 Begin: Running /scripts/nfs-bottom ... done.
1456 03:07:39.674234 Begin: Running /scripts/init-bottom ... done.
1457 03:07:39.982251 <30>[ 19.588130] systemd[1]: System time before build time, advancing clock.
1458 03:07:40.032031 <6>[ 19.642341] NET: Registered PF_INET6 protocol family
1459 03:07:40.037386 <6>[ 19.643865] Segment Routing with IPv6
1460 03:07:40.042607 <6>[ 19.645846] In-situ OAM (IOAM) with IPv6
1461 03:07:40.115949 <30>[ 19.698618] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1462 03:07:40.121356 <30>[ 19.726124] systemd[1]: Detected architecture arm64.
1463 03:07:40.121852
1464 03:07:40.128783 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1465 03:07:40.129266
1466 03:07:40.141172 <30>[ 19.747822] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1467 03:07:40.806770 <30>[ 20.412340] systemd[1]: Queued start job for default target graphical.target.
1468 03:07:40.839665 <30>[ 20.444642] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1469 03:07:40.848215 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1470 03:07:40.859254 <30>[ 20.463255] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1471 03:07:40.866609 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1472 03:07:40.878437 <30>[ 20.483370] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1473 03:07:40.887422 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1474 03:07:40.898283 <30>[ 20.503024] systemd[1]: Created slice user.slice - User and Session Slice.
1475 03:07:40.904715 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1476 03:07:40.918735 <30>[ 20.518537] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1477 03:07:40.924625 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1478 03:07:40.935694 <30>[ 20.538460] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1479 03:07:40.941252 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1480 03:07:40.964463 <30>[ 20.558463] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1481 03:07:40.970015 <30>[ 20.572532] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1482 03:07:40.983186 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1483 03:07:40.988742 <30>[ 20.594358] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1484 03:07:40.997454 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1485 03:07:41.013256 <30>[ 20.618373] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1486 03:07:41.022376 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1487 03:07:41.033363 <30>[ 20.638390] systemd[1]: Reached target paths.target - Path Units.
1488 03:07:41.041791 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1489 03:07:41.047314 <30>[ 20.654361] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1490 03:07:41.059093 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1491 03:07:41.064638 <30>[ 20.670354] systemd[1]: Reached target slices.target - Slice Units.
1492 03:07:41.072795 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1493 03:07:41.078324 <30>[ 20.686368] systemd[1]: Reached target swap.target - Swaps.
1494 03:07:41.085280 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1495 03:07:41.097267 <30>[ 20.702383] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1496 03:07:41.106119 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1497 03:07:41.121427 <30>[ 20.726555] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1498 03:07:41.130755 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1499 03:07:41.142586 <30>[ 20.747690] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1500 03:07:41.151405 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1501 03:07:41.166131 <30>[ 20.771253] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1502 03:07:41.175540 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1503 03:07:41.189584 <30>[ 20.794685] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1504 03:07:41.196429 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1505 03:07:41.207520 <30>[ 20.811315] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1506 03:07:41.215435 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1507 03:07:41.227154 <30>[ 20.832294] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1508 03:07:41.232711 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1509 03:07:41.245515 <30>[ 20.850608] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1510 03:07:41.254034 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1511 03:07:41.293389 <30>[ 20.898456] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1512 03:07:41.300178 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1513 03:07:41.315315 <30>[ 20.920433] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1514 03:07:41.322862 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1515 03:07:41.338611 <30>[ 20.943725] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1516 03:07:41.346047 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1517 03:07:41.364042 <30>[ 20.963004] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1518 03:07:41.372540 <30>[ 20.978695] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1519 03:07:41.382231 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1520 03:07:41.398403 <30>[ 21.003462] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1521 03:07:41.406326 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1522 03:07:41.422482 <30>[ 21.027565] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1523 03:07:41.430085 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1524 03:07:41.447511 <30>[ 21.052628] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1525 03:07:41.458603 Starting [0;1;39mmodprobe@drm.service<6>[ 21.059505] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1526 03:07:41.463559 [0m - Load Kernel Module drm...
1527 03:07:41.505554 <30>[ 21.110635] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1528 03:07:41.513840 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1529 03:07:41.528144 <30>[ 21.133207] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1530 03:07:41.535369 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1531 03:07:41.551186 <30>[ 21.156288] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1532 03:07:41.560679 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel M<6>[ 21.165825] fuse: init (API version 7.41)
1533 03:07:41.561192 odule loop...
1534 03:07:41.579134 <30>[ 21.184241] systemd[1]: Starting systemd-journald.service - Journal Service...
1535 03:07:41.585549 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1536 03:07:41.611277 <30>[ 21.216373] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1537 03:07:41.618788 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1538 03:07:41.635302 <30>[ 21.240424] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1539 03:07:41.644653 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1540 03:07:41.666018 <30>[ 21.271023] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1541 03:07:41.674708 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1542 03:07:41.689581 <30>[ 21.294643] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1543 03:07:41.697647 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1544 03:07:41.727204 <30>[ 21.332305] systemd[1]: Started systemd-journald.service - Journal Service.
1545 03:07:41.734071 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1546 03:07:41.748753 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1547 03:07:41.762458 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1548 03:07:41.782495 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1549 03:07:41.799132 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1550 03:07:41.812270 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1551 03:07:41.824220 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1552 03:07:41.836003 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1553 03:07:41.848197 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1554 03:07:41.860096 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1555 03:07:41.872104 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1556 03:07:41.883616 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1557 03:07:41.895349 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1558 03:07:41.907230 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1559 03:07:41.920208 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1560 03:07:41.963403 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1561 03:07:41.975176 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1562 03:07:41.993353 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1563 03:07:42.011607 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1564 03:07:42.037344 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Ker<46>[ 21.635168] systemd-journald[229]: Received client request to flush runtime journal.
1565 03:07:42.037885 nel Variables...
1566 03:07:42.058753 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1567 03:07:42.077862 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1568 03:07:42.084311 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1569 03:07:42.102123 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1570 03:07:42.118636 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1571 03:07:42.130397 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1572 03:07:42.213843 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1573 03:07:42.265545 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1574 03:07:42.350959 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1575 03:07:42.381517 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1576 03:07:42.387925 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1577 03:07:42.404978 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1578 03:07:42.461013 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1579 03:07:42.475765 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1580 03:07:42.711367 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1581 03:07:42.723590 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1582 03:07:42.773362 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1583 03:07:42.799720 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1584 03:07:42.815167 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1585 03:07:42.897577 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1586 03:07:42.914760 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1587 03:07:42.966956 <5>[ 22.571921] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1588 03:07:43.008083 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1589 03:07:43.013651 <5>[ 22.616457] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1590 03:07:43.019376 <5>[ 22.622275] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1591 03:07:43.030332 <4>[ 22.629768] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1592 03:07:43.035442 <6>[ 22.638950] cfg80211: failed to load regulatory.db
1593 03:07:43.049538 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1594 03:07:43.065817 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1595 03:07:43.089457 <46>[ 22.683480] systemd-journald[229]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1596 03:07:43.103227 <46>[ 22.696540] systemd-journald[229]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1597 03:07:43.113289 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1598 03:07:43.209846 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1599 03:07:43.233817 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1600 03:07:43.241195 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1601 03:07:43.279778 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1602 03:07:43.293693 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1603 03:07:43.300544 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1604 03:07:43.341475 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1605 03:07:43.348334 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1606 03:07:43.356852 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1607 03:07:43.400339 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1608 03:07:43.414819 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1609 03:07:43.486776 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1610 03:07:43.494161 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1611 03:07:43.514055 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1612 03:07:43.520567 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1613 03:07:43.569728 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1614 03:07:43.581697 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1615 03:07:43.597930 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1616 03:07:43.644608 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1617 03:07:43.651132 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1618 03:07:43.666767 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1619 03:07:43.678897 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1620 03:07:43.691355 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1621 03:07:43.701261 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1622 03:07:43.749148 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1623 03:07:43.765409 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1624 03:07:43.782821 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1625 03:07:43.789482 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1626 03:07:43.805486 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1627 03:07:43.849427 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1628 03:07:43.890217 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1629 03:07:43.952697
1630 03:07:43.953238 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1631 03:07:43.953706
1632 03:07:43.959839 debian-bookworm-arm64 login: root (automatic login)
1633 03:07:43.960382
1634 03:07:44.088349 Linux debian-bookworm-arm64 6.12.0-rc6 #1 SMP PREEMPT Fri Nov 8 01:13:42 UTC 2024 aarch64
1635 03:07:44.088751
1636 03:07:44.093831 The programs included with the Debian GNU/Linux system are free software;
1637 03:07:44.102845 the exact distribution terms for each program are described in the
1638 03:07:44.103191 individual files in /usr/share/doc/*/copyright.
1639 03:07:44.103417
1640 03:07:44.108369 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1641 03:07:44.113626 permitted by applicable law.
1642 03:07:44.836393 Matched prompt #10: / #
1644 03:07:44.837312 Setting prompt string to ['/ #']
1645 03:07:44.837626 end: 2.4.4.1 login-action (duration 00:00:25) [common]
1647 03:07:44.838328 end: 2.4.4 auto-login-action (duration 00:00:25) [common]
1648 03:07:44.838620 start: 2.4.5 expect-shell-connection (timeout 00:03:17) [common]
1649 03:07:44.838851 Setting prompt string to ['/ #']
1650 03:07:44.839061 Forcing a shell prompt, looking for ['/ #']
1652 03:07:44.889738 / #
1653 03:07:44.890164 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1654 03:07:44.890416 Waiting using forced prompt support (timeout 00:02:30)
1655 03:07:44.895456
1656 03:07:44.896008 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1657 03:07:44.896335 start: 2.4.6 export-device-env (timeout 00:03:16) [common]
1658 03:07:44.896587 Sending with 10 millisecond of delay
1660 03:07:49.886392 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/957122/extract-nfsrootfs-o26e1drq'
1661 03:07:49.897294 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/957122/extract-nfsrootfs-o26e1drq'
1662 03:07:49.898071 Sending with 10 millisecond of delay
1664 03:07:51.995518 / # export NFS_SERVER_IP='192.168.6.2'
1665 03:07:52.006477 export NFS_SERVER_IP='192.168.6.2'
1666 03:07:52.007324 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1667 03:07:52.007911 end: 2.4 uboot-commands (duration 00:01:51) [common]
1668 03:07:52.008530 end: 2 uboot-action (duration 00:01:51) [common]
1669 03:07:52.009131 start: 3 lava-test-retry (timeout 00:06:51) [common]
1670 03:07:52.009716 start: 3.1 lava-test-shell (timeout 00:06:51) [common]
1671 03:07:52.010190 Using namespace: common
1673 03:07:52.111331 / # #
1674 03:07:52.111936 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1675 03:07:52.117310 #
1676 03:07:52.118027 Using /lava-957122
1678 03:07:52.219107 / # export SHELL=/bin/bash
1679 03:07:52.224875 export SHELL=/bin/bash
1681 03:07:52.326213 / # . /lava-957122/environment
1682 03:07:52.330070 . /lava-957122/environment
1684 03:07:52.436600 / # /lava-957122/bin/lava-test-runner /lava-957122/0
1685 03:07:52.437254 Test shell timeout: 10s (minimum of the action and connection timeout)
1686 03:07:52.441470 /lava-957122/bin/lava-test-runner /lava-957122/0
1687 03:07:52.638277 + export TESTRUN_ID=0_timesync-off
1688 03:07:52.645031 + TESTRUN_ID=0_timesync-off
1689 03:07:52.645556 + cd /lava-957122/0/tests/0_timesync-off
1690 03:07:52.646047 ++ cat uuid
1691 03:07:52.650658 + UUID=957122_1.6.2.4.1
1692 03:07:52.651174 + set +x
1693 03:07:52.658432 <LAVA_SIGNAL_STARTRUN 0_timesync-off 957122_1.6.2.4.1>
1694 03:07:52.658947 + systemctl stop systemd-timesyncd
1695 03:07:52.659763 Received signal: <STARTRUN> 0_timesync-off 957122_1.6.2.4.1
1696 03:07:52.660311 Starting test lava.0_timesync-off (957122_1.6.2.4.1)
1697 03:07:52.660923 Skipping test definition patterns.
1698 03:07:52.702186 + set +x
1699 03:07:52.702680 <LAVA_SIGNAL_ENDRUN 0_timesync-off 957122_1.6.2.4.1>
1700 03:07:52.703347 Received signal: <ENDRUN> 0_timesync-off 957122_1.6.2.4.1
1701 03:07:52.703861 Ending use of test pattern.
1702 03:07:52.704320 Ending test lava.0_timesync-off (957122_1.6.2.4.1), duration 0.04
1704 03:07:52.806393 + export TESTRUN_ID=1_kselftest-alsa
1705 03:07:52.814790 + TESTRUN_ID=1_kselftest-alsa
1706 03:07:52.815298 + cd /lava-957122/0/tests/1_kselftest-alsa
1707 03:07:52.815736 ++ cat uuid
1708 03:07:52.822821 + UUID=957122_1.6.2.4.5
1709 03:07:52.823327 + set +x
1710 03:07:52.828387 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 957122_1.6.2.4.5>
1711 03:07:52.828888 + cd ./automated/linux/kselftest/
1712 03:07:52.829575 Received signal: <STARTRUN> 1_kselftest-alsa 957122_1.6.2.4.5
1713 03:07:52.830004 Starting test lava.1_kselftest-alsa (957122_1.6.2.4.5)
1714 03:07:52.830491 Skipping test definition patterns.
1715 03:07:52.857205 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1716 03:07:52.888309 INFO: install_deps skipped
1717 03:07:53.009750 --2024-11-08 03:07:52-- http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/gcc-12/kselftest.tar.xz
1718 03:07:53.275353 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1719 03:07:53.420102 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1720 03:07:53.566047 HTTP request sent, awaiting response... 200 OK
1721 03:07:53.566668 Length: 6928748 (6.6M) [application/octet-stream]
1722 03:07:53.571386 Saving to: 'kselftest_armhf.tar.gz'
1723 03:07:53.571869
1724 03:07:54.888219
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 49.92K 175KB/s
kselftest_armhf.tar 3%[ ] 216.29K 379KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.02MB/s
kselftest_armhf.tar 53%[=========> ] 3.51M 3.07MB/s
kselftest_armhf.tar 100%[===================>] 6.61M 5.02MB/s in 1.3s
1725 03:07:54.888897
1726 03:07:54.988862 2024-11-08 03:07:54 (5.02 MB/s) - 'kselftest_armhf.tar.gz' saved [6928748/6928748]
1727 03:07:54.989466
1728 03:08:04.423278 skiplist:
1729 03:08:04.423916 ========================================
1730 03:08:04.428767 ========================================
1731 03:08:04.468490 alsa:mixer-test
1732 03:08:04.468940 alsa:pcm-test
1733 03:08:04.469343 alsa:test-pcmtest-driver
1734 03:08:04.472542 alsa:utimer-test
1735 03:08:04.482776 ============== Tests to run ===============
1736 03:08:04.483206 alsa:mixer-test
1737 03:08:04.488324 alsa:pcm-test
1738 03:08:04.488739 alsa:test-pcmtest-driver
1739 03:08:04.489134 alsa:utimer-test
1740 03:08:04.496508 ===========End Tests to run ===============
1741 03:08:04.496926 shardfile-alsa pass
1742 03:08:04.604842 <12>[ 44.214287] kselftest: Running tests in alsa
1743 03:08:04.609406 TAP version 13
1744 03:08:04.616427 1..4
1745 03:08:04.642372 # timeout set to 45
1746 03:08:04.642803 # selftests: alsa: mixer-test
1747 03:08:04.832733 # TAP version 13
1748 03:08:04.833199 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1749 03:08:04.838168 # 1..427
1750 03:08:04.838603 # ok 1 get_value.LCALTA.60
1751 03:08:04.838998 # # LCALTA.60 TDMOUT_A SRC SEL
1752 03:08:04.843717 # ok 2 name.LCALTA.60
1753 03:08:04.844171 # ok 3 write_default.LCALTA.60
1754 03:08:04.849255 # ok 4 write_valid.LCALTA.60
1755 03:08:04.849671 # ok 5 write_invalid.LCALTA.60
1756 03:08:04.854809 # ok 6 event_missing.LCALTA.60
1757 03:08:04.855223 # ok 7 event_spurious.LCALTA.60
1758 03:08:04.860440 # ok 8 get_value.LCALTA.59
1759 03:08:04.860853 # # LCALTA.59 TDMOUT_B SRC SEL
1760 03:08:04.865969 # ok 9 name.LCALTA.59
1761 03:08:04.866380 # ok 10 write_default.LCALTA.59
1762 03:08:04.871495 # ok 11 write_valid.LCALTA.59
1763 03:08:04.871913 # ok 12 write_invalid.LCALTA.59
1764 03:08:04.877069 # ok 13 event_missing.LCALTA.59
1765 03:08:04.877485 # ok 14 event_spurious.LCALTA.59
1766 03:08:04.882602 # ok 15 get_value.LCALTA.58
1767 03:08:04.883011 # # LCALTA.58 TDMOUT_C SRC SEL
1768 03:08:04.888200 # ok 16 name.LCALTA.58
1769 03:08:04.888610 # ok 17 write_default.LCALTA.58
1770 03:08:04.893711 # ok 18 write_valid.LCALTA.58
1771 03:08:04.894126 # ok 19 write_invalid.LCALTA.58
1772 03:08:04.899252 # ok 20 event_missing.LCALTA.58
1773 03:08:04.899669 # ok 21 event_spurious.LCALTA.58
1774 03:08:04.904848 # ok 22 get_value.LCALTA.57
1775 03:08:04.905269 # # LCALTA.57 TDMIN_A SRC SEL
1776 03:08:04.905667 # ok 23 name.LCALTA.57
1777 03:08:04.910360 # ok 24 write_default.LCALTA.57
1778 03:08:04.910773 # ok 25 write_valid.LCALTA.57
1779 03:08:04.915876 # ok 26 write_invalid.LCALTA.57
1780 03:08:04.916319 # ok 27 event_missing.LCALTA.57
1781 03:08:04.921438 # ok 28 event_spurious.LCALTA.57
1782 03:08:04.921851 # ok 29 get_value.LCALTA.56
1783 03:08:04.927017 # # LCALTA.56 TDMIN_B SRC SEL
1784 03:08:04.927434 # ok 30 name.LCALTA.56
1785 03:08:04.932546 # ok 31 write_default.LCALTA.56
1786 03:08:04.932961 # ok 32 write_valid.LCALTA.56
1787 03:08:04.938080 # ok 33 write_invalid.LCALTA.56
1788 03:08:04.938492 # ok 34 event_missing.LCALTA.56
1789 03:08:04.943597 # ok 35 event_spurious.LCALTA.56
1790 03:08:04.944038 # ok 36 get_value.LCALTA.55
1791 03:08:04.949314 # # LCALTA.55 TDMIN_C SRC SEL
1792 03:08:04.960256 # ok 37 name.LCAL<3>[ 44.558627] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1793 03:08:04.960680 TA.55
1794 03:08:04.965795 # ok 38 write_default.LCALTA.55
1795 03:08:04.966205 # ok 39 write_valid.LCALTA.55
1796 03:08:04.971401 # ok 40 write_invalid.LCALTA.55
1797 03:08:04.971817 # ok 41 event_missing.LCALTA.55
1798 03:08:04.976927 # ok 42 event_spurious.LCALTA.55
1799 03:08:04.977345 # ok 43 get_value.LCALTA.54
1800 03:08:04.982460 # # LCALTA.54 ACODEC Left DAC Sel
1801 03:08:04.982872 # ok 44 name.LCALTA.54
1802 03:08:04.988029 # ok 45 write_default.LCALTA.54
1803 03:08:04.988441 # ok 46 write_valid.LCALTA.54
1804 03:08:04.993553 # ok 47 write_invalid.LCALTA.54
1805 03:08:04.993964 # ok 48 event_missing.LCALTA.54
1806 03:08:04.999109 # ok 49 event_spurious.LCALTA.54
1807 03:08:04.999520 # ok 50 get_value.LCALTA.53
1808 03:08:05.004635 # # LCALTA.53 ACODEC Right DAC Sel
1809 03:08:05.005057 # ok 51 name.LCALTA.53
1810 03:08:05.010209 # ok 52 write_default.LCALTA.53
1811 03:08:05.010621 # ok 53 write_valid.LCALTA.53
1812 03:08:05.015747 # ok 54 write_invalid.LCALTA.53
1813 03:08:05.016182 # ok 55 event_missing.LCALTA.53
1814 03:08:05.021291 # ok 56 event_spurious.LCALTA.53
1815 03:08:05.021719 # ok 57 get_value.LCALTA.52
1816 03:08:05.026848 # # LCALTA.52 TOACODEC OUT EN Switch
1817 03:08:05.027270 # ok 58 name.LCALTA.52
1818 03:08:05.032379 # ok 59 write_default.LCALTA.52
1819 03:08:05.032801 # ok 60 write_valid.LCALTA.52
1820 03:08:05.037916 # ok 61 write_invalid.LCALTA.52
1821 03:08:05.038326 # ok 62 event_missing.LCALTA.52
1822 03:08:05.043462 # ok 63 event_spurious.LCALTA.52
1823 03:08:05.043866 # ok 64 get_value.LCALTA.51
1824 03:08:05.049014 # # LCALTA.51 TOACODEC SRC
1825 03:08:05.049420 # ok 65 name.LCALTA.51
1826 03:08:05.054608 # ok 66 write_default.LCALTA.51
1827 03:08:05.055062 # ok 67 write_valid.LCALTA.51
1828 03:08:05.060233 # ok 68 write_invalid.LCALTA.51
1829 03:08:05.060716 # ok 69 event_missing.LCALTA.51
1830 03:08:05.065664 # ok 70 event_spurious.LCALTA.51
1831 03:08:05.066102 # ok 71 get_value.LCALTA.50
1832 03:08:05.071223 # # LCALTA.50 TOHDMITX SPDIF SRC
1833 03:08:05.071634 # ok 72 name.LCALTA.50
1834 03:08:05.072056 # ok 73 write_default.LCALTA.50
1835 03:08:05.076742 # ok 74 write_valid.LCALTA.50
1836 03:08:05.077152 # ok 75 write_invalid.LCALTA.50
1837 03:08:05.082280 # ok 76 event_missing.LCALTA.50
1838 03:08:05.087843 # ok 77 event_spurious.LCALTA.50
1839 03:08:05.088278 # ok 78 get_value.LCALTA.49
1840 03:08:05.088668 # # LCALTA.49 TOHDMITX Switch
1841 03:08:05.093401 # ok 79 name.LCALTA.49
1842 03:08:05.093812 # ok 80 write_default.LCALTA.49
1843 03:08:05.098943 # ok 81 write_valid.LCALTA.49
1844 03:08:05.099353 # ok 82 write_invalid.LCALTA.49
1845 03:08:05.104505 # ok 83 event_missing.LCALTA.49
1846 03:08:05.104916 # ok 84 event_spurious.LCALTA.49
1847 03:08:05.110030 # ok 85 get_value.LCALTA.48
1848 03:08:05.110444 # # LCALTA.48 TOHDMITX I2S SRC
1849 03:08:05.115590 # ok 86 name.LCALTA.48
1850 03:08:05.116026 # ok 87 write_default.LCALTA.48
1851 03:08:05.121128 # ok 88 write_valid.LCALTA.48
1852 03:08:05.121542 # ok 89 write_invalid.LCALTA.48
1853 03:08:05.126675 # ok 90 event_missing.LCALTA.48
1854 03:08:05.127089 # ok 91 event_spurious.LCALTA.48
1855 03:08:05.132229 # ok 92 get_value.LCALTA.47
1856 03:08:05.132642 # # LCALTA.47 TODDR_C SRC SEL
1857 03:08:05.137774 # ok 93 name.LCALTA.47
1858 03:08:05.138189 # ok 94 write_default.LCALTA.47
1859 03:08:05.143316 # ok 95 write_valid.LCALTA.47
1860 03:08:05.143727 # ok 96 write_invalid.LCALTA.47
1861 03:08:05.148857 # ok 97 event_missing.LCALTA.47
1862 03:08:05.149271 # ok 98 event_spurious.LCALTA.47
1863 03:08:05.154383 # ok 99 get_value.LCALTA.46
1864 03:08:05.154793 # # LCALTA.46 TODDR_B SRC SEL
1865 03:08:05.155184 # ok 100 name.LCALTA.46
1866 03:08:05.159935 # ok 101 write_default.LCALTA.46
1867 03:08:05.165498 # ok 102 write_valid.LCALTA.46
1868 03:08:05.165912 # ok 103 write_invalid.LCALTA.46
1869 03:08:05.171045 # ok 104 event_missing.LCALTA.46
1870 03:08:05.171464 # ok 105 event_spurious.LCALTA.46
1871 03:08:05.176603 # ok 106 get_value.LCALTA.45
1872 03:08:05.177015 # # LCALTA.45 TODDR_A SRC SEL
1873 03:08:05.177407 # ok 107 name.LCALTA.45
1874 03:08:05.182132 # ok 108 write_default.LCALTA.45
1875 03:08:05.187663 # ok 109 write_valid.LCALTA.45
1876 03:08:05.188105 # ok 110 write_invalid.LCALTA.45
1877 03:08:05.193198 # ok 111 event_missing.LCALTA.45
1878 03:08:05.193608 # ok 112 event_spurious.LCALTA.45
1879 03:08:05.198767 # ok 113 get_value.LCALTA.44
1880 03:08:05.199178 # # LCALTA.44 FRDDR_C SINK 3 SEL
1881 03:08:05.204320 # ok 114 name.LCALTA.44
1882 03:08:05.204735 # ok 115 write_default.LCALTA.44
1883 03:08:05.209858 # ok 116 write_valid.LCALTA.44
1884 03:08:05.210267 # ok 117 write_invalid.LCALTA.44
1885 03:08:05.215396 # ok 118 event_missing.LCALTA.44
1886 03:08:05.215811 # ok 119 event_spurious.LCALTA.44
1887 03:08:05.220988 # ok 120 get_value.LCALTA.43
1888 03:08:05.221404 # # LCALTA.43 FRDDR_C SINK 2 SEL
1889 03:08:05.226500 # ok 121 name.LCALTA.43
1890 03:08:05.226914 # ok 122 write_default.LCALTA.43
1891 03:08:05.232046 # ok 123 write_valid.LCALTA.43
1892 03:08:05.232452 # ok 124 write_invalid.LCALTA.43
1893 03:08:05.237593 # ok 125 event_missing.LCALTA.43
1894 03:08:05.238006 # ok 126 event_spurious.LCALTA.43
1895 03:08:05.243167 # ok 127 get_value.LCALTA.42
1896 03:08:05.243590 # # LCALTA.42 FRDDR_C SINK 1 SEL
1897 03:08:05.248701 # ok 128 name.LCALTA.42
1898 03:08:05.249127 # ok 129 write_default.LCALTA.42
1899 03:08:05.254258 # ok 130 write_valid.LCALTA.42
1900 03:08:05.254689 # ok 131 write_invalid.LCALTA.42
1901 03:08:05.259798 # ok 132 event_missing.LCALTA.42
1902 03:08:05.260249 # ok 133 event_spurious.LCALTA.42
1903 03:08:05.265516 # ok 134 get_value.LCALTA.41
1904 03:08:05.265945 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1905 03:08:05.270953 # ok 135 name.LCALTA.41
1906 03:08:05.271391 # ok 136 write_default.LCALTA.41
1907 03:08:05.276415 # ok 137 write_valid.LCALTA.41
1908 03:08:05.276854 # ok 138 write_invalid.LCALTA.41
1909 03:08:05.281969 # ok 139 event_missing.LCALTA.41
1910 03:08:05.282402 # ok 140 event_spurious.LCALTA.41
1911 03:08:05.287509 # ok 141 get_value.LCALTA.40
1912 03:08:05.287950 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1913 03:08:05.293044 # ok 142 name.LCALTA.40
1914 03:08:05.293477 # ok 143 write_default.LCALTA.40
1915 03:08:05.298603 # ok 144 write_valid.LCALTA.40
1916 03:08:05.299047 # ok 145 write_invalid.LCALTA.40
1917 03:08:05.304191 # ok 146 event_missing.LCALTA.40
1918 03:08:05.304625 # ok 147 event_spurious.LCALTA.40
1919 03:08:05.309691 # ok 148 get_value.LCALTA.39
1920 03:08:05.315279 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1921 03:08:05.315704 # ok 149 name.LCALTA.39
1922 03:08:05.316128 # ok 150 write_default.LCALTA.39
1923 03:08:05.320818 # ok 151 write_valid.LCALTA.39
1924 03:08:05.321236 # ok 152 write_invalid.LCALTA.39
1925 03:08:05.326320 # ok 153 event_missing.LCALTA.39
1926 03:08:05.331868 # ok 154 event_spurious.LCALTA.39
1927 03:08:05.332315 # ok 155 get_value.LCALTA.38
1928 03:08:05.337432 # # LCALTA.38 FRDDR_B SINK 3 SEL
1929 03:08:05.337848 # ok 156 name.LCALTA.38
1930 03:08:05.338242 # ok 157 write_default.LCALTA.38
1931 03:08:05.342999 # ok 158 write_valid.LCALTA.38
1932 03:08:05.343413 # ok 159 write_invalid.LCALTA.38
1933 03:08:05.348553 # ok 160 event_missing.LCALTA.38
1934 03:08:05.354109 # ok 161 event_spurious.LCALTA.38
1935 03:08:05.354525 # ok 162 get_value.LCALTA.37
1936 03:08:05.359629 # # LCALTA.37 FRDDR_B SINK 2 SEL
1937 03:08:05.360066 # ok 163 name.LCALTA.37
1938 03:08:05.360461 # ok 164 write_default.LCALTA.37
1939 03:08:05.365247 # ok 165 write_valid.LCALTA.37
1940 03:08:05.370763 # ok 166 write_invalid.LCALTA.37
1941 03:08:05.371184 # ok 167 event_missing.LCALTA.37
1942 03:08:05.376397 # ok 168 event_spurious.LCALTA.37
1943 03:08:05.376818 # ok 169 get_value.LCALTA.36
1944 03:08:05.381914 # # LCALTA.36 FRDDR_B SINK 1 SEL
1945 03:08:05.382338 # ok 170 name.LCALTA.36
1946 03:08:05.387487 # ok 171 write_default.LCALTA.36
1947 03:08:05.387907 # ok 172 write_valid.LCALTA.36
1948 03:08:05.392931 # ok 173 write_invalid.LCALTA.36
1949 03:08:05.393349 # ok 174 event_missing.LCALTA.36
1950 03:08:05.398470 # ok 175 event_spurious.LCALTA.36
1951 03:08:05.398888 # ok 176 get_value.LCALTA.35
1952 03:08:05.404035 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1953 03:08:05.404464 # ok 177 name.LCALTA.35
1954 03:08:05.409599 # ok 178 write_default.LCALTA.35
1955 03:08:05.410020 # ok 179 write_valid.LCALTA.35
1956 03:08:05.415124 # ok 180 write_invalid.LCALTA.35
1957 03:08:05.415559 # ok 181 event_missing.LCALTA.35
1958 03:08:05.420632 # ok 182 event_spurious.LCALTA.35
1959 03:08:05.421050 # ok 183 get_value.LCALTA.34
1960 03:08:05.426277 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1961 03:08:05.426703 # ok 184 name.LCALTA.34
1962 03:08:05.431775 # ok 185 write_default.LCALTA.34
1963 03:08:05.432244 # ok 186 write_valid.LCALTA.34
1964 03:08:05.437340 # ok 187 write_invalid.LCALTA.34
1965 03:08:05.437768 # ok 188 event_missing.LCALTA.34
1966 03:08:05.442849 # ok 189 event_spurious.LCALTA.34
1967 03:08:05.443280 # ok 190 get_value.LCALTA.33
1968 03:08:05.448398 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1969 03:08:05.448829 # ok 191 name.LCALTA.33
1970 03:08:05.453891 # ok 192 write_default.LCALTA.33
1971 03:08:05.454314 # ok 193 write_valid.LCALTA.33
1972 03:08:05.459479 # ok 194 write_invalid.LCALTA.33
1973 03:08:05.459902 # ok 195 event_missing.LCALTA.33
1974 03:08:05.465053 # ok 196 event_spurious.LCALTA.33
1975 03:08:05.465489 # ok 197 get_value.LCALTA.32
1976 03:08:05.470604 # # LCALTA.32 FRDDR_A SINK 3 SEL
1977 03:08:05.471032 # ok 198 name.LCALTA.32
1978 03:08:05.476145 # ok 199 write_default.LCALTA.32
1979 03:08:05.476573 # ok 200 write_valid.LCALTA.32
1980 03:08:05.481648 # ok 201 write_invalid.LCALTA.32
1981 03:08:05.482072 # ok 202 event_missing.LCALTA.32
1982 03:08:05.487250 # ok 203 event_spurious.LCALTA.32
1983 03:08:05.487674 # ok 204 get_value.LCALTA.31
1984 03:08:05.492830 # # LCALTA.31 FRDDR_A SINK 2 SEL
1985 03:08:05.493262 # ok 205 name.LCALTA.31
1986 03:08:05.498369 # ok 206 write_default.LCALTA.31
1987 03:08:05.498803 # ok 207 write_valid.LCALTA.31
1988 03:08:05.503855 # ok 208 write_invalid.LCALTA.31
1989 03:08:05.504332 # ok 209 event_missing.LCALTA.31
1990 03:08:05.509413 # ok 210 event_spurious.LCALTA.31
1991 03:08:05.509847 # ok 211 get_value.LCALTA.30
1992 03:08:05.514954 # # LCALTA.30 FRDDR_A SINK 1 SEL
1993 03:08:05.515393 # ok 212 name.LCALTA.30
1994 03:08:05.520539 # ok 213 write_default.LCALTA.30
1995 03:08:05.520981 # ok 214 write_valid.LCALTA.30
1996 03:08:05.526119 # ok 215 write_invalid.LCALTA.30
1997 03:08:05.531588 # ok 216 event_missing.LCALTA.30
1998 03:08:05.532051 # ok 217 event_spurious.LCALTA.30
1999 03:08:05.537137 # ok 218 get_value.LCALTA.29
2000 03:08:05.537578 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2001 03:08:05.542741 # ok 219 name.LCALTA.29
2002 03:08:05.543187 # ok 220 write_default.LCALTA.29
2003 03:08:05.548326 # ok 221 write_valid.LCALTA.29
2004 03:08:05.548767 # ok 222 write_invalid.LCALTA.29
2005 03:08:05.553786 # ok 223 event_missing.LCALTA.29
2006 03:08:05.554223 # ok 224 event_spurious.LCALTA.29
2007 03:08:05.559376 # ok 225 get_value.LCALTA.28
2008 03:08:05.559811 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2009 03:08:05.564866 # ok 226 name.LCALTA.28
2010 03:08:05.565306 # ok 227 write_default.LCALTA.28
2011 03:08:05.570438 # ok 228 write_valid.LCALTA.28
2012 03:08:05.570888 # ok 229 write_invalid.LCALTA.28
2013 03:08:05.575957 # ok 230 event_missing.LCALTA.28
2014 03:08:05.576411 # ok 231 event_spurious.LCALTA.28
2015 03:08:05.581676 # ok 232 get_value.LCALTA.27
2016 03:08:05.582103 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2017 03:08:05.587169 # ok 233 name.LCALTA.27
2018 03:08:05.587595 # ok 234 write_default.LCALTA.27
2019 03:08:05.592796 # ok 235 write_valid.LCALTA.27
2020 03:08:05.593222 # ok 236 write_invalid.LCALTA.27
2021 03:08:05.598340 # ok 237 event_missing.LCALTA.27
2022 03:08:05.598770 # ok 238 event_spurious.LCALTA.27
2023 03:08:05.603877 # ok 239 get_value.LCALTA.26
2024 03:08:05.604332 # # LCALTA.26 ELD
2025 03:08:05.610149 # ok 240 name.LCALTA.26
2026 03:08:05.610575 # # ELD is not writeable
2027 03:08:05.615049 # ok 241 # SKIP write_default.LCALTA.26
2028 03:08:05.615477 # # ELD is not writeable
2029 03:08:05.620507 # ok 242 # SKIP write_valid.LCALTA.26
2030 03:08:05.620942 # # ELD is not writeable
2031 03:08:05.626037 # ok 243 # SKIP write_invalid.LCALTA.26
2032 03:08:05.626467 # ok 244 event_missing.LCALTA.26
2033 03:08:05.632055 # ok 245 event_spurious.LCALTA.26
2034 03:08:05.632490 # ok 246 get_value.LCALTA.25
2035 03:08:05.637102 # # LCALTA.25 IEC958 Playback Default
2036 03:08:05.637529 # ok 247 name.LCALTA.25
2037 03:08:05.642815 # ok 248 write_default.LCALTA.25
2038 03:08:05.643241 # ok 249 # SKIP write_valid.LCALTA.25
2039 03:08:05.648209 # ok 250 # SKIP write_invalid.LCALTA.25
2040 03:08:05.653843 # ok 251 event_missing.LCALTA.25
2041 03:08:05.654269 # ok 252 event_spurious.LCALTA.25
2042 03:08:05.659227 # ok 253 get_value.LCALTA.24
2043 03:08:05.659656 # # LCALTA.24 IEC958 Playback Mask
2044 03:08:05.660107 # ok 254 name.LCALTA.24
2045 03:08:05.664958 # # IEC958 Playback Mask is not writeable
2046 03:08:05.670506 # ok 255 # SKIP write_default.LCALTA.24
2047 03:08:05.670933 # # IEC958 Playback Mask is not writeable
2048 03:08:05.676069 # ok 256 # SKIP write_valid.LCALTA.24
2049 03:08:05.681343 # # IEC958 Playback Mask is not writeable
2050 03:08:05.681774 # ok 257 # SKIP write_invalid.LCALTA.24
2051 03:08:05.687031 # ok 258 event_missing.LCALTA.24
2052 03:08:05.687455 # ok 259 event_spurious.LCALTA.24
2053 03:08:05.692594 # ok 260 get_value.LCALTA.23
2054 03:08:05.693027 # # LCALTA.23 Playback Channel Map
2055 03:08:05.698153 # ok 261 name.LCALTA.23
2056 03:08:05.703542 # # Playback Channel Map is not writeable
2057 03:08:05.703976 # ok 262 # SKIP write_default.LCALTA.23
2058 03:08:05.709078 # # Playback Channel Map is not writeable
2059 03:08:05.709505 # ok 263 # SKIP write_valid.LCALTA.23
2060 03:08:05.714659 # # Playback Channel Map is not writeable
2061 03:08:05.720175 # ok 264 # SKIP write_invalid.LCALTA.23
2062 03:08:05.720608 # ok 265 event_missing.LCALTA.23
2063 03:08:05.725709 # ok 266 event_spurious.LCALTA.23
2064 03:08:05.726143 # ok 267 get_value.LCALTA.22
2065 03:08:05.731296 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2066 03:08:05.731726 # ok 268 name.LCALTA.22
2067 03:08:05.736780 # ok 269 write_default.LCALTA.22
2068 03:08:05.737213 # ok 270 write_valid.LCALTA.22
2069 03:08:05.742354 # ok 271 write_invalid.LCALTA.22
2070 03:08:05.742797 # ok 272 event_missing.LCALTA.22
2071 03:08:05.747878 # ok 273 event_spurious.LCALTA.22
2072 03:08:05.753494 # ok 274 get_value.LCALTA.21
2073 03:08:05.753925 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2074 03:08:05.754328 # ok 275 name.LCALTA.21
2075 03:08:05.758979 # ok 276 write_default.LCALTA.21
2076 03:08:05.764546 # ok 277 write_valid.LCALTA.21
2077 03:08:05.764974 # ok 278 write_invalid.LCALTA.21
2078 03:08:05.770073 # ok 279 event_missing.LCALTA.21
2079 03:08:05.770500 # ok 280 event_spurious.LCALTA.21
2080 03:08:05.775620 # ok 281 get_value.LCALTA.20
2081 03:08:05.776083 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2082 03:08:05.781186 # ok 282 name.LCALTA.20
2083 03:08:05.781611 # ok 283 write_default.LCALTA.20
2084 03:08:05.786743 # ok 284 write_valid.LCALTA.20
2085 03:08:05.787169 # ok 285 write_invalid.LCALTA.20
2086 03:08:05.792365 # ok 286 event_missing.LCALTA.20
2087 03:08:05.792789 # ok 287 event_spurious.LCALTA.20
2088 03:08:05.797824 # ok 288 get_value.LCALTA.19
2089 03:08:05.798244 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2090 03:08:05.803369 # ok 289 name.LCALTA.19
2091 03:08:05.803791 # ok 290 write_default.LCALTA.19
2092 03:08:05.808924 # ok 291 write_valid.LCALTA.19
2093 03:08:05.809350 # ok 292 write_invalid.LCALTA.19
2094 03:08:05.814469 # ok 293 event_missing.LCALTA.19
2095 03:08:05.814897 # ok 294 event_spurious.LCALTA.19
2096 03:08:05.820031 # ok 295 get_value.LCALTA.18
2097 03:08:05.820460 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2098 03:08:05.825587 # ok 296 name.LCALTA.18
2099 03:08:05.826013 # ok 297 write_default.LCALTA.18
2100 03:08:05.831120 # ok 298 write_valid.LCALTA.18
2101 03:08:05.831548 # ok 299 write_invalid.LCALTA.18
2102 03:08:05.836658 # ok 300 event_missing.LCALTA.18
2103 03:08:05.837087 # ok 301 event_spurious.LCALTA.18
2104 03:08:05.842212 # ok 302 get_value.LCALTA.17
2105 03:08:05.847747 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2106 03:08:05.848204 # ok 303 name.LCALTA.17
2107 03:08:05.848609 # ok 304 write_default.LCALTA.17
2108 03:08:05.853348 # ok 305 write_valid.LCALTA.17
2109 03:08:05.858844 # ok 306 write_invalid.LCALTA.17
2110 03:08:05.859271 # ok 307 event_missing.LCALTA.17
2111 03:08:05.864406 # ok 308 event_spurious.LCALTA.17
2112 03:08:05.864835 # ok 309 get_value.LCALTA.16
2113 03:08:05.869946 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2114 03:08:05.870378 # ok 310 name.LCALTA.16
2115 03:08:05.875474 # ok 311 write_default.LCALTA.16
2116 03:08:05.875899 # ok 312 write_valid.LCALTA.16
2117 03:08:05.881014 # ok 313 write_invalid.LCALTA.16
2118 03:08:05.881444 # ok 314 event_missing.LCALTA.16
2119 03:08:05.886611 # ok 315 event_spurious.LCALTA.16
2120 03:08:05.887041 # ok 316 get_value.LCALTA.15
2121 03:08:05.892125 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2122 03:08:05.892552 # ok 317 name.LCALTA.15
2123 03:08:05.897667 # ok 318 write_default.LCALTA.15
2124 03:08:05.898093 # ok 319 write_valid.LCALTA.15
2125 03:08:05.903254 # ok 320 write_invalid.LCALTA.15
2126 03:08:05.903685 # ok 321 event_missing.LCALTA.15
2127 03:08:05.908774 # ok 322 event_spurious.LCALTA.15
2128 03:08:05.909202 # ok 323 get_value.LCALTA.14
2129 03:08:05.914358 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2130 03:08:05.914787 # ok 324 name.LCALTA.14
2131 03:08:05.919864 # ok 325 write_default.LCALTA.14
2132 03:08:05.920320 # ok 326 write_valid.LCALTA.14
2133 03:08:05.925413 # ok 327 write_invalid.LCALTA.14
2134 03:08:05.925839 # ok 328 event_missing.LCALTA.14
2135 03:08:05.930962 # ok 329 event_spurious.LCALTA.14
2136 03:08:05.931390 # ok 330 get_value.LCALTA.13
2137 03:08:05.936471 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2138 03:08:05.936896 # ok 331 name.LCALTA.13
2139 03:08:05.942051 # ok 332 write_default.LCALTA.13
2140 03:08:05.942479 # ok 333 write_valid.LCALTA.13
2141 03:08:05.947585 # ok 334 write_invalid.LCALTA.13
2142 03:08:05.948036 # ok 335 event_missing.LCALTA.13
2143 03:08:05.953138 # ok 336 event_spurious.LCALTA.13
2144 03:08:05.953560 # ok 337 get_value.LCALTA.12
2145 03:08:05.958682 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2146 03:08:05.959113 # ok 338 name.LCALTA.12
2147 03:08:05.964236 # ok 339 write_default.LCALTA.12
2148 03:08:05.969778 # ok 340 write_valid.LCALTA.12
2149 03:08:05.970203 # ok 341 write_invalid.LCALTA.12
2150 03:08:05.975368 # ok 342 event_missing.LCALTA.12
2151 03:08:05.975793 # ok 343 event_spurious.LCALTA.12
2152 03:08:05.980901 # ok 344 get_value.LCALTA.11
2153 03:08:05.981327 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2154 03:08:05.986405 # ok 345 name.LCALTA.11
2155 03:08:05.986830 # ok 346 write_default.LCALTA.11
2156 03:08:05.991958 # ok 347 write_valid.LCALTA.11
2157 03:08:05.992408 # ok 348 write_invalid.LCALTA.11
2158 03:08:05.997503 # ok 349 event_missing.LCALTA.11
2159 03:08:05.997924 # ok 350 event_spurious.LCALTA.11
2160 03:08:06.003052 # ok 351 get_value.LCALTA.10
2161 03:08:06.003481 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2162 03:08:06.008611 # ok 352 name.LCALTA.10
2163 03:08:06.009046 # ok 353 write_default.LCALTA.10
2164 03:08:06.014126 # ok 354 write_valid.LCALTA.10
2165 03:08:06.014554 # ok 355 write_invalid.LCALTA.10
2166 03:08:06.019701 # ok 356 event_missing.LCALTA.10
2167 03:08:06.020162 # ok 357 event_spurious.LCALTA.10
2168 03:08:06.025263 # ok 358 get_value.LCALTA.9
2169 03:08:06.025712 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2170 03:08:06.030776 # ok 359 name.LCALTA.9
2171 03:08:06.031213 # ok 360 write_default.LCALTA.9
2172 03:08:06.036372 # ok 361 write_valid.LCALTA.9
2173 03:08:06.036805 # ok 362 write_invalid.LCALTA.9
2174 03:08:06.041876 # ok 363 event_missing.LCALTA.9
2175 03:08:06.042305 # ok 364 event_spurious.LCALTA.9
2176 03:08:06.047415 # ok 365 get_value.LCALTA.8
2177 03:08:06.047843 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2178 03:08:06.052984 # ok 366 name.LCALTA.8
2179 03:08:06.053416 # ok 367 write_default.LCALTA.8
2180 03:08:06.058540 # ok 368 write_valid.LCALTA.8
2181 03:08:06.058968 # ok 369 write_invalid.LCALTA.8
2182 03:08:06.064088 # ok 370 event_missing.LCALTA.8
2183 03:08:06.064546 # ok 371 event_spurious.LCALTA.8
2184 03:08:06.069630 # ok 372 get_value.LCALTA.7
2185 03:08:06.070064 # # LCALTA.7 ACODEC Unmute Ramp Switch
2186 03:08:06.075149 # ok 373 name.LCALTA.7
2187 03:08:06.075574 # ok 374 write_default.LCALTA.7
2188 03:08:06.080695 # ok 375 write_valid.LCALTA.7
2189 03:08:06.081127 # ok 376 write_invalid.LCALTA.7
2190 03:08:06.086236 # ok 377 event_missing.LCALTA.7
2191 03:08:06.086664 # ok 378 event_spurious.LCALTA.7
2192 03:08:06.091797 # ok 379 get_value.LCALTA.6
2193 03:08:06.092253 # # LCALTA.6 ACODEC Mute Ramp Switch
2194 03:08:06.097407 # ok 380 name.LCALTA.6
2195 03:08:06.097839 # ok 381 write_default.LCALTA.6
2196 03:08:06.102893 # ok 382 write_valid.LCALTA.6
2197 03:08:06.103321 # ok 383 write_invalid.LCALTA.6
2198 03:08:06.108435 # ok 384 event_missing.LCALTA.6
2199 03:08:06.108865 # ok 385 event_spurious.LCALTA.6
2200 03:08:06.114002 # ok 386 get_value.LCALTA.5
2201 03:08:06.114427 # # LCALTA.5 ACODEC Volume Ramp Switch
2202 03:08:06.119525 # ok 387 name.LCALTA.5
2203 03:08:06.119949 # ok 388 write_default.LCALTA.5
2204 03:08:06.125079 # ok 389 write_valid.LCALTA.5
2205 03:08:06.125507 # ok 390 write_invalid.LCALTA.5
2206 03:08:06.130623 # ok 391 event_missing.LCALTA.5
2207 03:08:06.131045 # ok 392 event_spurious.LCALTA.5
2208 03:08:06.136215 # ok 393 get_value.LCALTA.4
2209 03:08:06.136641 # # LCALTA.4 ACODEC Ramp Rate
2210 03:08:06.141749 # ok 394 name.LCALTA.4
2211 03:08:06.142184 # ok 395 write_default.LCALTA.4
2212 03:08:06.147271 # ok 396 write_valid.LCALTA.4
2213 03:08:06.147698 # ok 397 write_invalid.LCALTA.4
2214 03:08:06.152821 # ok 398 event_missing.LCALTA.4
2215 03:08:06.153250 # ok 399 event_spurious.LCALTA.4
2216 03:08:06.158383 # ok 400 get_value.LCALTA.3
2217 03:08:06.158808 # # LCALTA.3 ACODEC Playback Volume
2218 03:08:06.163904 # ok 401 name.LCALTA.3
2219 03:08:06.164354 # ok 402 write_default.LCALTA.3
2220 03:08:06.169458 # ok 403 write_valid.LCALTA.3
2221 03:08:06.169885 # ok 404 write_invalid.LCALTA.3
2222 03:08:06.175006 # ok 405 event_missing.LCALTA.3
2223 03:08:06.175432 # ok 406 event_spurious.LCALTA.3
2224 03:08:06.180541 # ok 407 get_value.LCALTA.2
2225 03:08:06.180972 # # LCALTA.2 ACODEC Playback Switch
2226 03:08:06.186094 # ok 408 name.LCALTA.2
2227 03:08:06.186520 # ok 409 write_default.LCALTA.2
2228 03:08:06.191650 # ok 410 write_valid.LCALTA.2
2229 03:08:06.192109 # ok 411 write_invalid.LCALTA.2
2230 03:08:06.197185 # ok 412 event_missing.LCALTA.2
2231 03:08:06.197611 # ok 413 event_spurious.LCALTA.2
2232 03:08:06.202745 # ok 414 get_value.LCALTA.1
2233 03:08:06.203168 # # LCALTA.1 ACODEC Playback Channel Mode
2234 03:08:06.208308 # ok 415 name.LCALTA.1
2235 03:08:06.208738 # ok 416 write_default.LCALTA.1
2236 03:08:06.213829 # ok 417 write_valid.LCALTA.1
2237 03:08:06.214252 # ok 418 write_invalid.LCALTA.1
2238 03:08:06.219393 # ok 419 event_missing.LCALTA.1
2239 03:08:06.219818 # ok 420 event_spurious.LCALTA.1
2240 03:08:06.224925 # ok 421 get_value.LCALTA.0
2241 03:08:06.225355 # # LCALTA.0 TOACODEC Lane Select
2242 03:08:06.230433 # ok 422 name.LCALTA.0
2243 03:08:06.230856 # ok 423 write_default.LCALTA.0
2244 03:08:06.235962 # ok 424 write_valid.LCALTA.0
2245 03:08:06.236409 # ok 425 write_invalid.LCALTA.0
2246 03:08:06.241516 # ok 426 event_missing.LCALTA.0
2247 03:08:06.241947 # ok 427 event_spurious.LCALTA.0
2248 03:08:06.247123 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2249 03:08:06.252630 ok 1 selftests: alsa: mixer-test
2250 03:08:06.253068 # timeout set to 45
2251 03:08:06.253470 # selftests: alsa: pcm-test
2252 03:08:06.258243 # TAP version 13
2253 03:08:06.258670 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2254 03:08:06.263769 # # LCALTA.0 - fe.dai-link-0 (*)
2255 03:08:06.264269 # # LCALTA.0 - fe.dai-link-1 (*)
2256 03:08:06.269286 # # LCALTA.0 - fe.dai-link-2 (*)
2257 03:08:06.269712 # # LCALTA.0 - fe.dai-link-3 (*)
2258 03:08:06.274836 # # LCALTA.0 - fe.dai-link-4 (*)
2259 03:08:06.275259 # # LCALTA.0 - fe.dai-link-5 (*)
2260 03:08:06.280380 # 1..42
2261 03:08:06.285957 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2262 03:08:06.286387 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2263 03:08:06.291479 # # snd_pcm_hw_params: Invalid argument
2264 03:08:06.297032 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2265 03:08:06.302571 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2266 03:08:06.303003 # # snd_pcm_hw_params: Invalid argument
2267 03:08:06.308184 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2268 03:08:06.313666 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2269 03:08:06.319200 # # snd_pcm_hw_params: Invalid argument
2270 03:08:06.324813 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2271 03:08:06.330316 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2272 03:08:06.330749 # # snd_pcm_hw_params: Invalid argument
2273 03:08:06.335858 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2274 03:08:06.341401 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2275 03:08:06.346942 # # snd_pcm_hw_params: Invalid argument
2276 03:08:06.352492 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2277 03:08:06.358029 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2278 03:08:06.358456 # # snd_pcm_hw_params: Invalid argument
2279 03:08:06.363594 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2280 03:08:06.369124 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2281 03:08:06.374764 # # snd_pcm_hw_params: Invalid argument
2282 03:08:06.380350 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2283 03:08:06.380789 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2284 03:08:06.385866 # # snd_pcm_hw_params: Invalid argument
2285 03:08:06.391298 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2286 03:08:06.396851 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2287 03:08:06.397280 # # snd_pcm_hw_params: Invalid argument
2288 03:08:06.407943 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2289 03:08:06.408408 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2290 03:08:06.413525 # # snd_pcm_hw_params: Invalid argument
2291 03:08:06.419046 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2292 03:08:06.424594 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2293 03:08:06.425027 # # snd_pcm_hw_params: Invalid argument
2294 03:08:06.430160 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2295 03:08:06.435704 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2296 03:08:06.441273 # # snd_pcm_hw_params: Invalid argument
2297 03:08:06.446794 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2298 03:08:06.452358 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2299 03:08:06.452789 # # snd_pcm_hw_params: Invalid argument
2300 03:08:06.457898 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2301 03:08:06.463377 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2302 03:08:06.468923 # # snd_pcm_hw_params: Invalid argument
2303 03:08:06.474535 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2304 03:08:06.480074 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2305 03:08:06.480503 # # snd_pcm_hw_params: Invalid argument
2306 03:08:06.485558 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2307 03:08:06.491231 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2308 03:08:06.496734 # # snd_pcm_hw_params: Invalid argument
2309 03:08:06.502229 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2310 03:08:06.502683 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2311 03:08:06.507783 # # snd_pcm_hw_params: Invalid argument
2312 03:08:06.513387 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2313 03:08:06.518926 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2314 03:08:06.524490 # # snd_pcm_hw_params: Invalid argument
2315 03:08:06.529996 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2316 03:08:06.530431 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2317 03:08:06.535540 # # snd_pcm_hw_params: Invalid argument
2318 03:08:06.541084 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2319 03:08:06.546629 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2320 03:08:06.552192 # # snd_pcm_hw_params: Invalid argument
2321 03:08:06.557749 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2322 03:08:06.558193 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2323 03:08:06.563255 # # snd_pcm_hw_params: Invalid argument
2324 03:08:06.568796 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2325 03:08:06.574435 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2326 03:08:06.574867 # # snd_pcm_hw_params: Invalid argument
2327 03:08:06.579895 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2328 03:08:06.585501 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2329 03:08:06.591011 # # snd_pcm_hw_params: Invalid argument
2330 03:08:06.596565 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2331 03:08:06.602072 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2332 03:08:06.602503 # # snd_pcm_hw_params: Invalid argument
2333 03:08:06.607627 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2334 03:08:06.613230 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2335 03:08:06.618717 # # snd_pcm_hw_params: Invalid argument
2336 03:08:06.624273 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2337 03:08:06.629823 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2338 03:08:06.630251 # # snd_pcm_hw_params: Invalid argument
2339 03:08:06.635488 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2340 03:08:06.640922 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2341 03:08:06.646464 # # snd_pcm_hw_params: Invalid argument
2342 03:08:06.652040 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2343 03:08:06.657564 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2344 03:08:06.657991 # # snd_pcm_hw_params: Invalid argument
2345 03:08:06.663107 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2346 03:08:06.668652 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2347 03:08:06.674223 # # snd_pcm_hw_params: Invalid argument
2348 03:08:06.679743 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2349 03:08:06.685317 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2350 03:08:06.685743 # # snd_pcm_hw_params: Invalid argument
2351 03:08:06.690838 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2352 03:08:06.696460 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2353 03:08:06.701934 # # snd_pcm_hw_params: Invalid argument
2354 03:08:06.707505 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2355 03:08:06.713050 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2356 03:08:06.713479 # # snd_pcm_hw_params: Invalid argument
2357 03:08:06.718582 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2358 03:08:06.724167 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2359 03:08:06.729616 # # snd_pcm_hw_params: Invalid argument
2360 03:08:06.735155 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2361 03:08:06.740706 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2362 03:08:06.740979 # # snd_pcm_hw_params: Invalid argument
2363 03:08:06.746331 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2364 03:08:06.751837 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2365 03:08:06.757438 # # snd_pcm_hw_params: Invalid argument
2366 03:08:06.762912 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2367 03:08:06.768442 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2368 03:08:06.768721 # # snd_pcm_hw_params: Invalid argument
2369 03:08:06.773984 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2370 03:08:06.779534 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2371 03:08:06.785102 # # snd_pcm_hw_params: Invalid argument
2372 03:08:06.790635 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2373 03:08:06.796185 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2374 03:08:06.796452 # # snd_pcm_hw_params: Invalid argument
2375 03:08:06.801735 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2376 03:08:06.807288 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2377 03:08:06.812821 # # snd_pcm_hw_params: Invalid argument
2378 03:08:06.818444 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2379 03:08:06.823927 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2380 03:08:06.824220 # # snd_pcm_hw_params: Invalid argument
2381 03:08:06.829475 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2382 03:08:06.835014 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2383 03:08:06.840555 # # snd_pcm_hw_params: Invalid argument
2384 03:08:06.846096 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2385 03:08:06.851665 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2386 03:08:06.851934 # # snd_pcm_hw_params: Invalid argument
2387 03:08:06.857207 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2388 03:08:06.862760 ok 2 selftests: alsa: pcm-test
2389 03:08:06.863026 # timeout set to 45
2390 03:08:06.868298 # selftests: alsa: test-pcmtest-driver
2391 03:08:06.868558 # TAP version 13
2392 03:08:06.868793 # 1..5
2393 03:08:06.873827 # # Starting 5 tests from 1 test cases.
2394 03:08:06.874110 # # RUN pcmtest.playback ...
2395 03:08:06.879462 # # SKIP Can't read patterns. Probably, module isn't loaded
2396 03:08:06.884932 # # OK pcmtest.playback
2397 03:08:06.890483 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2398 03:08:06.896045 # # RUN pcmtest.capture ...
2399 03:08:06.901588 # # SKIP Can't read patterns. Probably, module isn't loaded
2400 03:08:06.907119 # # OK pcmtest.capture
2401 03:08:06.912679 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2402 03:08:06.918204 # # RUN pcmtest.ni_capture ...
2403 03:08:06.923747 # # SKIP Can't read patterns. Probably, module isn't loaded
2404 03:08:06.924050 # # OK pcmtest.ni_capture
2405 03:08:06.934863 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2406 03:08:06.935160 # # RUN pcmtest.ni_playback ...
2407 03:08:06.940486 # # SKIP Can't read patterns. Probably, module isn't loaded
2408 03:08:06.945948 # # OK pcmtest.ni_playback
2409 03:08:06.951493 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2410 03:08:06.957108 # # RUN pcmtest.reset_ioctl ...
2411 03:08:06.962638 # # SKIP Can't read patterns. Probably, module isn't loaded
2412 03:08:06.968341 # # OK pcmtest.reset_ioctl
2413 03:08:06.973737 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2414 03:08:06.979306 # # PASSED: 5 / 5 tests passed.
2415 03:08:06.984829 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2416 03:08:06.985119 ok 3 selftests: alsa: test-pcmtest-driver
2417 03:08:06.990305 # timeout set to 45
2418 03:08:06.990579 # selftests: alsa: utimer-test
2419 03:08:06.990817 # TAP version 13
2420 03:08:06.991050 # 1..2
2421 03:08:06.995954 # # Starting 2 tests from 2 test cases.
2422 03:08:07.001518 # # RUN global.wrong_timers_test ...
2423 03:08:07.006961 # # OK global.wrong_timers_test
2424 03:08:07.007231 # ok 1 global.wrong_timers_test
2425 03:08:07.012496 # # RUN timer_f.utimer ...
2426 03:08:07.018111 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2427 03:08:07.023637 # # utimer: Test terminated by assertion
2428 03:08:07.029183 # # FAIL timer_f.utimer
2429 03:08:07.029642 # not ok 2 timer_f.utimer
2430 03:08:07.034759 # # FAILED: 1 / 2 tests passed.
2431 03:08:07.042162 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2432 03:08:07.042600 not ok 4 selftests: alsa: utimer-test # exit=1
2433 03:08:07.572906 alsa_mixer-test_get_value_LCALTA_60 pass
2434 03:08:07.578272 alsa_mixer-test_name_LCALTA_60 pass
2435 03:08:07.578720 alsa_mixer-test_write_default_LCALTA_60 pass
2436 03:08:07.583804 alsa_mixer-test_write_valid_LCALTA_60 pass
2437 03:08:07.589351 alsa_mixer-test_write_invalid_LCALTA_60 pass
2438 03:08:07.594818 alsa_mixer-test_event_missing_LCALTA_60 pass
2439 03:08:07.595249 alsa_mixer-test_event_spurious_LCALTA_60 pass
2440 03:08:07.600369 alsa_mixer-test_get_value_LCALTA_59 pass
2441 03:08:07.605903 alsa_mixer-test_name_LCALTA_59 pass
2442 03:08:07.606333 alsa_mixer-test_write_default_LCALTA_59 pass
2443 03:08:07.611504 alsa_mixer-test_write_valid_LCALTA_59 pass
2444 03:08:07.617081 alsa_mixer-test_write_invalid_LCALTA_59 pass
2445 03:08:07.617522 alsa_mixer-test_event_missing_LCALTA_59 pass
2446 03:08:07.622623 alsa_mixer-test_event_spurious_LCALTA_59 pass
2447 03:08:07.628173 alsa_mixer-test_get_value_LCALTA_58 pass
2448 03:08:07.628605 alsa_mixer-test_name_LCALTA_58 pass
2449 03:08:07.633718 alsa_mixer-test_write_default_LCALTA_58 pass
2450 03:08:07.639259 alsa_mixer-test_write_valid_LCALTA_58 pass
2451 03:08:07.639709 alsa_mixer-test_write_invalid_LCALTA_58 pass
2452 03:08:07.644825 alsa_mixer-test_event_missing_LCALTA_58 pass
2453 03:08:07.650351 alsa_mixer-test_event_spurious_LCALTA_58 pass
2454 03:08:07.655900 alsa_mixer-test_get_value_LCALTA_57 pass
2455 03:08:07.656358 alsa_mixer-test_name_LCALTA_57 pass
2456 03:08:07.661457 alsa_mixer-test_write_default_LCALTA_57 pass
2457 03:08:07.666992 alsa_mixer-test_write_valid_LCALTA_57 pass
2458 03:08:07.667418 alsa_mixer-test_write_invalid_LCALTA_57 pass
2459 03:08:07.672589 alsa_mixer-test_event_missing_LCALTA_57 pass
2460 03:08:07.678092 alsa_mixer-test_event_spurious_LCALTA_57 pass
2461 03:08:07.678522 alsa_mixer-test_get_value_LCALTA_56 pass
2462 03:08:07.683639 alsa_mixer-test_name_LCALTA_56 pass
2463 03:08:07.689206 alsa_mixer-test_write_default_LCALTA_56 pass
2464 03:08:07.689641 alsa_mixer-test_write_valid_LCALTA_56 pass
2465 03:08:07.694727 alsa_mixer-test_write_invalid_LCALTA_56 pass
2466 03:08:07.700274 alsa_mixer-test_event_missing_LCALTA_56 pass
2467 03:08:07.705834 alsa_mixer-test_event_spurious_LCALTA_56 pass
2468 03:08:07.706261 alsa_mixer-test_get_value_LCALTA_55 pass
2469 03:08:07.711374 alsa_mixer-test_name_LCALTA_55 pass
2470 03:08:07.716923 alsa_mixer-test_write_default_LCALTA_55 pass
2471 03:08:07.717356 alsa_mixer-test_write_valid_LCALTA_55 pass
2472 03:08:07.722466 alsa_mixer-test_write_invalid_LCALTA_55 pass
2473 03:08:07.728036 alsa_mixer-test_event_missing_LCALTA_55 pass
2474 03:08:07.728465 alsa_mixer-test_event_spurious_LCALTA_55 pass
2475 03:08:07.733597 alsa_mixer-test_get_value_LCALTA_54 pass
2476 03:08:07.739089 alsa_mixer-test_name_LCALTA_54 pass
2477 03:08:07.739515 alsa_mixer-test_write_default_LCALTA_54 pass
2478 03:08:07.744625 alsa_mixer-test_write_valid_LCALTA_54 pass
2479 03:08:07.750225 alsa_mixer-test_write_invalid_LCALTA_54 pass
2480 03:08:07.750655 alsa_mixer-test_event_missing_LCALTA_54 pass
2481 03:08:07.755747 alsa_mixer-test_event_spurious_LCALTA_54 pass
2482 03:08:07.761295 alsa_mixer-test_get_value_LCALTA_53 pass
2483 03:08:07.761720 alsa_mixer-test_name_LCALTA_53 pass
2484 03:08:07.766843 alsa_mixer-test_write_default_LCALTA_53 pass
2485 03:08:07.772381 alsa_mixer-test_write_valid_LCALTA_53 pass
2486 03:08:07.777920 alsa_mixer-test_write_invalid_LCALTA_53 pass
2487 03:08:07.778344 alsa_mixer-test_event_missing_LCALTA_53 pass
2488 03:08:07.783460 alsa_mixer-test_event_spurious_LCALTA_53 pass
2489 03:08:07.789028 alsa_mixer-test_get_value_LCALTA_52 pass
2490 03:08:07.789460 alsa_mixer-test_name_LCALTA_52 pass
2491 03:08:07.794616 alsa_mixer-test_write_default_LCALTA_52 pass
2492 03:08:07.800133 alsa_mixer-test_write_valid_LCALTA_52 pass
2493 03:08:07.800557 alsa_mixer-test_write_invalid_LCALTA_52 pass
2494 03:08:07.805658 alsa_mixer-test_event_missing_LCALTA_52 pass
2495 03:08:07.811214 alsa_mixer-test_event_spurious_LCALTA_52 pass
2496 03:08:07.811637 alsa_mixer-test_get_value_LCALTA_51 pass
2497 03:08:07.816776 alsa_mixer-test_name_LCALTA_51 pass
2498 03:08:07.822303 alsa_mixer-test_write_default_LCALTA_51 pass
2499 03:08:07.822726 alsa_mixer-test_write_valid_LCALTA_51 pass
2500 03:08:07.827848 alsa_mixer-test_write_invalid_LCALTA_51 pass
2501 03:08:07.833404 alsa_mixer-test_event_missing_LCALTA_51 pass
2502 03:08:07.838950 alsa_mixer-test_event_spurious_LCALTA_51 pass
2503 03:08:07.839377 alsa_mixer-test_get_value_LCALTA_50 pass
2504 03:08:07.844461 alsa_mixer-test_name_LCALTA_50 pass
2505 03:08:07.850031 alsa_mixer-test_write_default_LCALTA_50 pass
2506 03:08:07.850460 alsa_mixer-test_write_valid_LCALTA_50 pass
2507 03:08:07.855613 alsa_mixer-test_write_invalid_LCALTA_50 pass
2508 03:08:07.861117 alsa_mixer-test_event_missing_LCALTA_50 pass
2509 03:08:07.861540 alsa_mixer-test_event_spurious_LCALTA_50 pass
2510 03:08:07.866661 alsa_mixer-test_get_value_LCALTA_49 pass
2511 03:08:07.872230 alsa_mixer-test_name_LCALTA_49 pass
2512 03:08:07.872664 alsa_mixer-test_write_default_LCALTA_49 pass
2513 03:08:07.877797 alsa_mixer-test_write_valid_LCALTA_49 pass
2514 03:08:07.883301 alsa_mixer-test_write_invalid_LCALTA_49 pass
2515 03:08:07.888861 alsa_mixer-test_event_missing_LCALTA_49 pass
2516 03:08:07.889288 alsa_mixer-test_event_spurious_LCALTA_49 pass
2517 03:08:07.894432 alsa_mixer-test_get_value_LCALTA_48 pass
2518 03:08:07.894857 alsa_mixer-test_name_LCALTA_48 pass
2519 03:08:07.900002 alsa_mixer-test_write_default_LCALTA_48 pass
2520 03:08:07.905503 alsa_mixer-test_write_valid_LCALTA_48 pass
2521 03:08:07.911052 alsa_mixer-test_write_invalid_LCALTA_48 pass
2522 03:08:07.911476 alsa_mixer-test_event_missing_LCALTA_48 pass
2523 03:08:07.916608 alsa_mixer-test_event_spurious_LCALTA_48 pass
2524 03:08:07.922151 alsa_mixer-test_get_value_LCALTA_47 pass
2525 03:08:07.922581 alsa_mixer-test_name_LCALTA_47 pass
2526 03:08:07.927688 alsa_mixer-test_write_default_LCALTA_47 pass
2527 03:08:07.933253 alsa_mixer-test_write_valid_LCALTA_47 pass
2528 03:08:07.933687 alsa_mixer-test_write_invalid_LCALTA_47 pass
2529 03:08:07.938777 alsa_mixer-test_event_missing_LCALTA_47 pass
2530 03:08:07.944352 alsa_mixer-test_event_spurious_LCALTA_47 pass
2531 03:08:07.949865 alsa_mixer-test_get_value_LCALTA_46 pass
2532 03:08:07.950292 alsa_mixer-test_name_LCALTA_46 pass
2533 03:08:07.955409 alsa_mixer-test_write_default_LCALTA_46 pass
2534 03:08:07.960979 alsa_mixer-test_write_valid_LCALTA_46 pass
2535 03:08:07.961418 alsa_mixer-test_write_invalid_LCALTA_46 pass
2536 03:08:07.966523 alsa_mixer-test_event_missing_LCALTA_46 pass
2537 03:08:07.972083 alsa_mixer-test_event_spurious_LCALTA_46 pass
2538 03:08:07.972539 alsa_mixer-test_get_value_LCALTA_45 pass
2539 03:08:07.977620 alsa_mixer-test_name_LCALTA_45 pass
2540 03:08:07.983151 alsa_mixer-test_write_default_LCALTA_45 pass
2541 03:08:07.983613 alsa_mixer-test_write_valid_LCALTA_45 pass
2542 03:08:07.988709 alsa_mixer-test_write_invalid_LCALTA_45 pass
2543 03:08:07.994266 alsa_mixer-test_event_missing_LCALTA_45 pass
2544 03:08:07.994734 alsa_mixer-test_event_spurious_LCALTA_45 pass
2545 03:08:07.999811 alsa_mixer-test_get_value_LCALTA_44 pass
2546 03:08:08.005371 alsa_mixer-test_name_LCALTA_44 pass
2547 03:08:08.005839 alsa_mixer-test_write_default_LCALTA_44 pass
2548 03:08:08.010884 alsa_mixer-test_write_valid_LCALTA_44 pass
2549 03:08:08.016433 alsa_mixer-test_write_invalid_LCALTA_44 pass
2550 03:08:08.021993 alsa_mixer-test_event_missing_LCALTA_44 pass
2551 03:08:08.022437 alsa_mixer-test_event_spurious_LCALTA_44 pass
2552 03:08:08.027524 alsa_mixer-test_get_value_LCALTA_43 pass
2553 03:08:08.033085 alsa_mixer-test_name_LCALTA_43 pass
2554 03:08:08.033530 alsa_mixer-test_write_default_LCALTA_43 pass
2555 03:08:08.038627 alsa_mixer-test_write_valid_LCALTA_43 pass
2556 03:08:08.044197 alsa_mixer-test_write_invalid_LCALTA_43 pass
2557 03:08:08.044627 alsa_mixer-test_event_missing_LCALTA_43 pass
2558 03:08:08.049702 alsa_mixer-test_event_spurious_LCALTA_43 pass
2559 03:08:08.055251 alsa_mixer-test_get_value_LCALTA_42 pass
2560 03:08:08.055681 alsa_mixer-test_name_LCALTA_42 pass
2561 03:08:08.060805 alsa_mixer-test_write_default_LCALTA_42 pass
2562 03:08:08.066344 alsa_mixer-test_write_valid_LCALTA_42 pass
2563 03:08:08.066778 alsa_mixer-test_write_invalid_LCALTA_42 pass
2564 03:08:08.071885 alsa_mixer-test_event_missing_LCALTA_42 pass
2565 03:08:08.077434 alsa_mixer-test_event_spurious_LCALTA_42 pass
2566 03:08:08.083006 alsa_mixer-test_get_value_LCALTA_41 pass
2567 03:08:08.083433 alsa_mixer-test_name_LCALTA_41 pass
2568 03:08:08.088534 alsa_mixer-test_write_default_LCALTA_41 pass
2569 03:08:08.094097 alsa_mixer-test_write_valid_LCALTA_41 pass
2570 03:08:08.094526 alsa_mixer-test_write_invalid_LCALTA_41 pass
2571 03:08:08.099630 alsa_mixer-test_event_missing_LCALTA_41 pass
2572 03:08:08.105195 alsa_mixer-test_event_spurious_LCALTA_41 pass
2573 03:08:08.105620 alsa_mixer-test_get_value_LCALTA_40 pass
2574 03:08:08.110767 alsa_mixer-test_name_LCALTA_40 pass
2575 03:08:08.116250 alsa_mixer-test_write_default_LCALTA_40 pass
2576 03:08:08.116677 alsa_mixer-test_write_valid_LCALTA_40 pass
2577 03:08:08.121817 alsa_mixer-test_write_invalid_LCALTA_40 pass
2578 03:08:08.127372 alsa_mixer-test_event_missing_LCALTA_40 pass
2579 03:08:08.132918 alsa_mixer-test_event_spurious_LCALTA_40 pass
2580 03:08:08.133345 alsa_mixer-test_get_value_LCALTA_39 pass
2581 03:08:08.138461 alsa_mixer-test_name_LCALTA_39 pass
2582 03:08:08.144034 alsa_mixer-test_write_default_LCALTA_39 pass
2583 03:08:08.144462 alsa_mixer-test_write_valid_LCALTA_39 pass
2584 03:08:08.149562 alsa_mixer-test_write_invalid_LCALTA_39 pass
2585 03:08:08.155108 alsa_mixer-test_event_missing_LCALTA_39 pass
2586 03:08:08.155534 alsa_mixer-test_event_spurious_LCALTA_39 pass
2587 03:08:08.160651 alsa_mixer-test_get_value_LCALTA_38 pass
2588 03:08:08.166190 alsa_mixer-test_name_LCALTA_38 pass
2589 03:08:08.166615 alsa_mixer-test_write_default_LCALTA_38 pass
2590 03:08:08.171742 alsa_mixer-test_write_valid_LCALTA_38 pass
2591 03:08:08.177281 alsa_mixer-test_write_invalid_LCALTA_38 pass
2592 03:08:08.177705 alsa_mixer-test_event_missing_LCALTA_38 pass
2593 03:08:08.182814 alsa_mixer-test_event_spurious_LCALTA_38 pass
2594 03:08:08.188387 alsa_mixer-test_get_value_LCALTA_37 pass
2595 03:08:08.188819 alsa_mixer-test_name_LCALTA_37 pass
2596 03:08:08.193926 alsa_mixer-test_write_default_LCALTA_37 pass
2597 03:08:08.199460 alsa_mixer-test_write_valid_LCALTA_37 pass
2598 03:08:08.205030 alsa_mixer-test_write_invalid_LCALTA_37 pass
2599 03:08:08.205457 alsa_mixer-test_event_missing_LCALTA_37 pass
2600 03:08:08.210585 alsa_mixer-test_event_spurious_LCALTA_37 pass
2601 03:08:08.216136 alsa_mixer-test_get_value_LCALTA_36 pass
2602 03:08:08.216565 alsa_mixer-test_name_LCALTA_36 pass
2603 03:08:08.221702 alsa_mixer-test_write_default_LCALTA_36 pass
2604 03:08:08.227209 alsa_mixer-test_write_valid_LCALTA_36 pass
2605 03:08:08.227643 alsa_mixer-test_write_invalid_LCALTA_36 pass
2606 03:08:08.232758 alsa_mixer-test_event_missing_LCALTA_36 pass
2607 03:08:08.238282 alsa_mixer-test_event_spurious_LCALTA_36 pass
2608 03:08:08.238708 alsa_mixer-test_get_value_LCALTA_35 pass
2609 03:08:08.243819 alsa_mixer-test_name_LCALTA_35 pass
2610 03:08:08.249411 alsa_mixer-test_write_default_LCALTA_35 pass
2611 03:08:08.249848 alsa_mixer-test_write_valid_LCALTA_35 pass
2612 03:08:08.254929 alsa_mixer-test_write_invalid_LCALTA_35 pass
2613 03:08:08.260498 alsa_mixer-test_event_missing_LCALTA_35 pass
2614 03:08:08.266010 alsa_mixer-test_event_spurious_LCALTA_35 pass
2615 03:08:08.266437 alsa_mixer-test_get_value_LCALTA_34 pass
2616 03:08:08.271680 alsa_mixer-test_name_LCALTA_34 pass
2617 03:08:08.277141 alsa_mixer-test_write_default_LCALTA_34 pass
2618 03:08:08.277572 alsa_mixer-test_write_valid_LCALTA_34 pass
2619 03:08:08.282677 alsa_mixer-test_write_invalid_LCALTA_34 pass
2620 03:08:08.288226 alsa_mixer-test_event_missing_LCALTA_34 pass
2621 03:08:08.288649 alsa_mixer-test_event_spurious_LCALTA_34 pass
2622 03:08:08.293790 alsa_mixer-test_get_value_LCALTA_33 pass
2623 03:08:08.299314 alsa_mixer-test_name_LCALTA_33 pass
2624 03:08:08.299744 alsa_mixer-test_write_default_LCALTA_33 pass
2625 03:08:08.304862 alsa_mixer-test_write_valid_LCALTA_33 pass
2626 03:08:08.310415 alsa_mixer-test_write_invalid_LCALTA_33 pass
2627 03:08:08.315951 alsa_mixer-test_event_missing_LCALTA_33 pass
2628 03:08:08.316403 alsa_mixer-test_event_spurious_LCALTA_33 pass
2629 03:08:08.321497 alsa_mixer-test_get_value_LCALTA_32 pass
2630 03:08:08.321922 alsa_mixer-test_name_LCALTA_32 pass
2631 03:08:08.327047 alsa_mixer-test_write_default_LCALTA_32 pass
2632 03:08:08.332666 alsa_mixer-test_write_valid_LCALTA_32 pass
2633 03:08:08.338147 alsa_mixer-test_write_invalid_LCALTA_32 pass
2634 03:08:08.338575 alsa_mixer-test_event_missing_LCALTA_32 pass
2635 03:08:08.343713 alsa_mixer-test_event_spurious_LCALTA_32 pass
2636 03:08:08.349241 alsa_mixer-test_get_value_LCALTA_31 pass
2637 03:08:08.349669 alsa_mixer-test_name_LCALTA_31 pass
2638 03:08:08.354777 alsa_mixer-test_write_default_LCALTA_31 pass
2639 03:08:08.360314 alsa_mixer-test_write_valid_LCALTA_31 pass
2640 03:08:08.360743 alsa_mixer-test_write_invalid_LCALTA_31 pass
2641 03:08:08.365874 alsa_mixer-test_event_missing_LCALTA_31 pass
2642 03:08:08.371520 alsa_mixer-test_event_spurious_LCALTA_31 pass
2643 03:08:08.377063 alsa_mixer-test_get_value_LCALTA_30 pass
2644 03:08:08.377496 alsa_mixer-test_name_LCALTA_30 pass
2645 03:08:08.382632 alsa_mixer-test_write_default_LCALTA_30 pass
2646 03:08:08.388196 alsa_mixer-test_write_valid_LCALTA_30 pass
2647 03:08:08.388627 alsa_mixer-test_write_invalid_LCALTA_30 pass
2648 03:08:08.393713 alsa_mixer-test_event_missing_LCALTA_30 pass
2649 03:08:08.399170 alsa_mixer-test_event_spurious_LCALTA_30 pass
2650 03:08:08.399597 alsa_mixer-test_get_value_LCALTA_29 pass
2651 03:08:08.404738 alsa_mixer-test_name_LCALTA_29 pass
2652 03:08:08.410245 alsa_mixer-test_write_default_LCALTA_29 pass
2653 03:08:08.410683 alsa_mixer-test_write_valid_LCALTA_29 pass
2654 03:08:08.415805 alsa_mixer-test_write_invalid_LCALTA_29 pass
2655 03:08:08.421359 alsa_mixer-test_event_missing_LCALTA_29 pass
2656 03:08:08.421792 alsa_mixer-test_event_spurious_LCALTA_29 pass
2657 03:08:08.426901 alsa_mixer-test_get_value_LCALTA_28 pass
2658 03:08:08.432445 alsa_mixer-test_name_LCALTA_28 pass
2659 03:08:08.432879 alsa_mixer-test_write_default_LCALTA_28 pass
2660 03:08:08.437988 alsa_mixer-test_write_valid_LCALTA_28 pass
2661 03:08:08.443541 alsa_mixer-test_write_invalid_LCALTA_28 pass
2662 03:08:08.449082 alsa_mixer-test_event_missing_LCALTA_28 pass
2663 03:08:08.449511 alsa_mixer-test_event_spurious_LCALTA_28 pass
2664 03:08:08.454706 alsa_mixer-test_get_value_LCALTA_27 pass
2665 03:08:08.460202 alsa_mixer-test_name_LCALTA_27 pass
2666 03:08:08.460630 alsa_mixer-test_write_default_LCALTA_27 pass
2667 03:08:08.465736 alsa_mixer-test_write_valid_LCALTA_27 pass
2668 03:08:08.471284 alsa_mixer-test_write_invalid_LCALTA_27 pass
2669 03:08:08.471712 alsa_mixer-test_event_missing_LCALTA_27 pass
2670 03:08:08.476798 alsa_mixer-test_event_spurious_LCALTA_27 pass
2671 03:08:08.482358 alsa_mixer-test_get_value_LCALTA_26 pass
2672 03:08:08.482784 alsa_mixer-test_name_LCALTA_26 pass
2673 03:08:08.487888 alsa_mixer-test_write_default_LCALTA_26 skip
2674 03:08:08.493539 alsa_mixer-test_write_valid_LCALTA_26 skip
2675 03:08:08.493971 alsa_mixer-test_write_invalid_LCALTA_26 skip
2676 03:08:08.499035 alsa_mixer-test_event_missing_LCALTA_26 pass
2677 03:08:08.504650 alsa_mixer-test_event_spurious_LCALTA_26 pass
2678 03:08:08.510118 alsa_mixer-test_get_value_LCALTA_25 pass
2679 03:08:08.510598 alsa_mixer-test_name_LCALTA_25 pass
2680 03:08:08.516050 alsa_mixer-test_write_default_LCALTA_25 pass
2681 03:08:08.521237 alsa_mixer-test_write_valid_LCALTA_25 skip
2682 03:08:08.521651 alsa_mixer-test_write_invalid_LCALTA_25 skip
2683 03:08:08.526781 alsa_mixer-test_event_missing_LCALTA_25 pass
2684 03:08:08.532714 alsa_mixer-test_event_spurious_LCALTA_25 pass
2685 03:08:08.533105 alsa_mixer-test_get_value_LCALTA_24 pass
2686 03:08:08.538027 alsa_mixer-test_name_LCALTA_24 pass
2687 03:08:08.543538 alsa_mixer-test_write_default_LCALTA_24 skip
2688 03:08:08.543957 alsa_mixer-test_write_valid_LCALTA_24 skip
2689 03:08:08.549217 alsa_mixer-test_write_invalid_LCALTA_24 skip
2690 03:08:08.554695 alsa_mixer-test_event_missing_LCALTA_24 pass
2691 03:08:08.560137 alsa_mixer-test_event_spurious_LCALTA_24 pass
2692 03:08:08.560772 alsa_mixer-test_get_value_LCALTA_23 pass
2693 03:08:08.565777 alsa_mixer-test_name_LCALTA_23 pass
2694 03:08:08.571353 alsa_mixer-test_write_default_LCALTA_23 skip
2695 03:08:08.572109 alsa_mixer-test_write_valid_LCALTA_23 skip
2696 03:08:08.576799 alsa_mixer-test_write_invalid_LCALTA_23 skip
2697 03:08:08.582214 alsa_mixer-test_event_missing_LCALTA_23 pass
2698 03:08:08.582615 alsa_mixer-test_event_spurious_LCALTA_23 pass
2699 03:08:08.587900 alsa_mixer-test_get_value_LCALTA_22 pass
2700 03:08:08.593431 alsa_mixer-test_name_LCALTA_22 pass
2701 03:08:08.594025 alsa_mixer-test_write_default_LCALTA_22 pass
2702 03:08:08.598996 alsa_mixer-test_write_valid_LCALTA_22 pass
2703 03:08:08.604460 alsa_mixer-test_write_invalid_LCALTA_22 pass
2704 03:08:08.604851 alsa_mixer-test_event_missing_LCALTA_22 pass
2705 03:08:08.610130 alsa_mixer-test_event_spurious_LCALTA_22 pass
2706 03:08:08.615617 alsa_mixer-test_get_value_LCALTA_21 pass
2707 03:08:08.616211 alsa_mixer-test_name_LCALTA_21 pass
2708 03:08:08.621109 alsa_mixer-test_write_default_LCALTA_21 pass
2709 03:08:08.626650 alsa_mixer-test_write_valid_LCALTA_21 pass
2710 03:08:08.632315 alsa_mixer-test_write_invalid_LCALTA_21 pass
2711 03:08:08.632849 alsa_mixer-test_event_missing_LCALTA_21 pass
2712 03:08:08.637827 alsa_mixer-test_event_spurious_LCALTA_21 pass
2713 03:08:08.643284 alsa_mixer-test_get_value_LCALTA_20 pass
2714 03:08:08.643790 alsa_mixer-test_name_LCALTA_20 pass
2715 03:08:08.648882 alsa_mixer-test_write_default_LCALTA_20 pass
2716 03:08:08.654455 alsa_mixer-test_write_valid_LCALTA_20 pass
2717 03:08:08.654972 alsa_mixer-test_write_invalid_LCALTA_20 pass
2718 03:08:08.659977 alsa_mixer-test_event_missing_LCALTA_20 pass
2719 03:08:08.665515 alsa_mixer-test_event_spurious_LCALTA_20 pass
2720 03:08:08.666016 alsa_mixer-test_get_value_LCALTA_19 pass
2721 03:08:08.671069 alsa_mixer-test_name_LCALTA_19 pass
2722 03:08:08.676587 alsa_mixer-test_write_default_LCALTA_19 pass
2723 03:08:08.677094 alsa_mixer-test_write_valid_LCALTA_19 pass
2724 03:08:08.682189 alsa_mixer-test_write_invalid_LCALTA_19 pass
2725 03:08:08.687748 alsa_mixer-test_event_missing_LCALTA_19 pass
2726 03:08:08.693295 alsa_mixer-test_event_spurious_LCALTA_19 pass
2727 03:08:08.693808 alsa_mixer-test_get_value_LCALTA_18 pass
2728 03:08:08.698919 alsa_mixer-test_name_LCALTA_18 pass
2729 03:08:08.704324 alsa_mixer-test_write_default_LCALTA_18 pass
2730 03:08:08.704834 alsa_mixer-test_write_valid_LCALTA_18 pass
2731 03:08:08.709890 alsa_mixer-test_write_invalid_LCALTA_18 pass
2732 03:08:08.715418 alsa_mixer-test_event_missing_LCALTA_18 pass
2733 03:08:08.715929 alsa_mixer-test_event_spurious_LCALTA_18 pass
2734 03:08:08.720989 alsa_mixer-test_get_value_LCALTA_17 pass
2735 03:08:08.726544 alsa_mixer-test_name_LCALTA_17 pass
2736 03:08:08.727058 alsa_mixer-test_write_default_LCALTA_17 pass
2737 03:08:08.732090 alsa_mixer-test_write_valid_LCALTA_17 pass
2738 03:08:08.737612 alsa_mixer-test_write_invalid_LCALTA_17 pass
2739 03:08:08.743140 alsa_mixer-test_event_missing_LCALTA_17 pass
2740 03:08:08.743650 alsa_mixer-test_event_spurious_LCALTA_17 pass
2741 03:08:08.748717 alsa_mixer-test_get_value_LCALTA_16 pass
2742 03:08:08.749230 alsa_mixer-test_name_LCALTA_16 pass
2743 03:08:08.754261 alsa_mixer-test_write_default_LCALTA_16 pass
2744 03:08:08.759906 alsa_mixer-test_write_valid_LCALTA_16 pass
2745 03:08:08.765360 alsa_mixer-test_write_invalid_LCALTA_16 pass
2746 03:08:08.765869 alsa_mixer-test_event_missing_LCALTA_16 pass
2747 03:08:08.770892 alsa_mixer-test_event_spurious_LCALTA_16 pass
2748 03:08:08.776435 alsa_mixer-test_get_value_LCALTA_15 pass
2749 03:08:08.776941 alsa_mixer-test_name_LCALTA_15 pass
2750 03:08:08.781961 alsa_mixer-test_write_default_LCALTA_15 pass
2751 03:08:08.787524 alsa_mixer-test_write_valid_LCALTA_15 pass
2752 03:08:08.788059 alsa_mixer-test_write_invalid_LCALTA_15 pass
2753 03:08:08.793137 alsa_mixer-test_event_missing_LCALTA_15 pass
2754 03:08:08.798637 alsa_mixer-test_event_spurious_LCALTA_15 pass
2755 03:08:08.804232 alsa_mixer-test_get_value_LCALTA_14 pass
2756 03:08:08.804736 alsa_mixer-test_name_LCALTA_14 pass
2757 03:08:08.809708 alsa_mixer-test_write_default_LCALTA_14 pass
2758 03:08:08.815280 alsa_mixer-test_write_valid_LCALTA_14 pass
2759 03:08:08.815785 alsa_mixer-test_write_invalid_LCALTA_14 pass
2760 03:08:08.820869 alsa_mixer-test_event_missing_LCALTA_14 pass
2761 03:08:08.826358 alsa_mixer-test_event_spurious_LCALTA_14 pass
2762 03:08:08.826864 alsa_mixer-test_get_value_LCALTA_13 pass
2763 03:08:08.831918 alsa_mixer-test_name_LCALTA_13 pass
2764 03:08:08.837465 alsa_mixer-test_write_default_LCALTA_13 pass
2765 03:08:08.837976 alsa_mixer-test_write_valid_LCALTA_13 pass
2766 03:08:08.842987 alsa_mixer-test_write_invalid_LCALTA_13 pass
2767 03:08:08.848546 alsa_mixer-test_event_missing_LCALTA_13 pass
2768 03:08:08.849053 alsa_mixer-test_event_spurious_LCALTA_13 pass
2769 03:08:08.854103 alsa_mixer-test_get_value_LCALTA_12 pass
2770 03:08:08.859644 alsa_mixer-test_name_LCALTA_12 pass
2771 03:08:08.860183 alsa_mixer-test_write_default_LCALTA_12 pass
2772 03:08:08.865191 alsa_mixer-test_write_valid_LCALTA_12 pass
2773 03:08:08.870745 alsa_mixer-test_write_invalid_LCALTA_12 pass
2774 03:08:08.876284 alsa_mixer-test_event_missing_LCALTA_12 pass
2775 03:08:08.876784 alsa_mixer-test_event_spurious_LCALTA_12 pass
2776 03:08:08.881883 alsa_mixer-test_get_value_LCALTA_11 pass
2777 03:08:08.887362 alsa_mixer-test_name_LCALTA_11 pass
2778 03:08:08.887864 alsa_mixer-test_write_default_LCALTA_11 pass
2779 03:08:08.892931 alsa_mixer-test_write_valid_LCALTA_11 pass
2780 03:08:08.898473 alsa_mixer-test_write_invalid_LCALTA_11 pass
2781 03:08:08.898978 alsa_mixer-test_event_missing_LCALTA_11 pass
2782 03:08:08.904053 alsa_mixer-test_event_spurious_LCALTA_11 pass
2783 03:08:08.909563 alsa_mixer-test_get_value_LCALTA_10 pass
2784 03:08:08.910064 alsa_mixer-test_name_LCALTA_10 pass
2785 03:08:08.915094 alsa_mixer-test_write_default_LCALTA_10 pass
2786 03:08:08.920654 alsa_mixer-test_write_valid_LCALTA_10 pass
2787 03:08:08.921162 alsa_mixer-test_write_invalid_LCALTA_10 pass
2788 03:08:08.926217 alsa_mixer-test_event_missing_LCALTA_10 pass
2789 03:08:08.931743 alsa_mixer-test_event_spurious_LCALTA_10 pass
2790 03:08:08.937303 alsa_mixer-test_get_value_LCALTA_9 pass
2791 03:08:08.937806 alsa_mixer-test_name_LCALTA_9 pass
2792 03:08:08.942879 alsa_mixer-test_write_default_LCALTA_9 pass
2793 03:08:08.948387 alsa_mixer-test_write_valid_LCALTA_9 pass
2794 03:08:08.948891 alsa_mixer-test_write_invalid_LCALTA_9 pass
2795 03:08:08.953931 alsa_mixer-test_event_missing_LCALTA_9 pass
2796 03:08:08.959457 alsa_mixer-test_event_spurious_LCALTA_9 pass
2797 03:08:08.959960 alsa_mixer-test_get_value_LCALTA_8 pass
2798 03:08:08.964994 alsa_mixer-test_name_LCALTA_8 pass
2799 03:08:08.970594 alsa_mixer-test_write_default_LCALTA_8 pass
2800 03:08:08.971102 alsa_mixer-test_write_valid_LCALTA_8 pass
2801 03:08:08.976121 alsa_mixer-test_write_invalid_LCALTA_8 pass
2802 03:08:08.981681 alsa_mixer-test_event_missing_LCALTA_8 pass
2803 03:08:08.982188 alsa_mixer-test_event_spurious_LCALTA_8 pass
2804 03:08:08.987203 alsa_mixer-test_get_value_LCALTA_7 pass
2805 03:08:08.992753 alsa_mixer-test_name_LCALTA_7 pass
2806 03:08:08.993262 alsa_mixer-test_write_default_LCALTA_7 pass
2807 03:08:08.998309 alsa_mixer-test_write_valid_LCALTA_7 pass
2808 03:08:09.003888 alsa_mixer-test_write_invalid_LCALTA_7 pass
2809 03:08:09.004422 alsa_mixer-test_event_missing_LCALTA_7 pass
2810 03:08:09.009413 alsa_mixer-test_event_spurious_LCALTA_7 pass
2811 03:08:09.014930 alsa_mixer-test_get_value_LCALTA_6 pass
2812 03:08:09.015434 alsa_mixer-test_name_LCALTA_6 pass
2813 03:08:09.020485 alsa_mixer-test_write_default_LCALTA_6 pass
2814 03:08:09.026062 alsa_mixer-test_write_valid_LCALTA_6 pass
2815 03:08:09.026586 alsa_mixer-test_write_invalid_LCALTA_6 pass
2816 03:08:09.031602 alsa_mixer-test_event_missing_LCALTA_6 pass
2817 03:08:09.037206 alsa_mixer-test_event_spurious_LCALTA_6 pass
2818 03:08:09.037746 alsa_mixer-test_get_value_LCALTA_5 pass
2819 03:08:09.042739 alsa_mixer-test_name_LCALTA_5 pass
2820 03:08:09.048259 alsa_mixer-test_write_default_LCALTA_5 pass
2821 03:08:09.048787 alsa_mixer-test_write_valid_LCALTA_5 pass
2822 03:08:09.053809 alsa_mixer-test_write_invalid_LCALTA_5 pass
2823 03:08:09.059359 alsa_mixer-test_event_missing_LCALTA_5 pass
2824 03:08:09.059881 alsa_mixer-test_event_spurious_LCALTA_5 pass
2825 03:08:09.064900 alsa_mixer-test_get_value_LCALTA_4 pass
2826 03:08:09.070428 alsa_mixer-test_name_LCALTA_4 pass
2827 03:08:09.070953 alsa_mixer-test_write_default_LCALTA_4 pass
2828 03:08:09.075925 alsa_mixer-test_write_valid_LCALTA_4 pass
2829 03:08:09.081463 alsa_mixer-test_write_invalid_LCALTA_4 pass
2830 03:08:09.081947 alsa_mixer-test_event_missing_LCALTA_4 pass
2831 03:08:09.087009 alsa_mixer-test_event_spurious_LCALTA_4 pass
2832 03:08:09.092580 alsa_mixer-test_get_value_LCALTA_3 pass
2833 03:08:09.093069 alsa_mixer-test_name_LCALTA_3 pass
2834 03:08:09.098127 alsa_mixer-test_write_default_LCALTA_3 pass
2835 03:08:09.103682 alsa_mixer-test_write_valid_LCALTA_3 pass
2836 03:08:09.104205 alsa_mixer-test_write_invalid_LCALTA_3 pass
2837 03:08:09.109552 alsa_mixer-test_event_missing_LCALTA_3 pass
2838 03:08:09.114770 alsa_mixer-test_event_spurious_LCALTA_3 pass
2839 03:08:09.115258 alsa_mixer-test_get_value_LCALTA_2 pass
2840 03:08:09.120312 alsa_mixer-test_name_LCALTA_2 pass
2841 03:08:09.125882 alsa_mixer-test_write_default_LCALTA_2 pass
2842 03:08:09.126369 alsa_mixer-test_write_valid_LCALTA_2 pass
2843 03:08:09.131409 alsa_mixer-test_write_invalid_LCALTA_2 pass
2844 03:08:09.136952 alsa_mixer-test_event_missing_LCALTA_2 pass
2845 03:08:09.142502 alsa_mixer-test_event_spurious_LCALTA_2 pass
2846 03:08:09.142991 alsa_mixer-test_get_value_LCALTA_1 pass
2847 03:08:09.148085 alsa_mixer-test_name_LCALTA_1 pass
2848 03:08:09.148583 alsa_mixer-test_write_default_LCALTA_1 pass
2849 03:08:09.153610 alsa_mixer-test_write_valid_LCALTA_1 pass
2850 03:08:09.159138 alsa_mixer-test_write_invalid_LCALTA_1 pass
2851 03:08:09.164688 alsa_mixer-test_event_missing_LCALTA_1 pass
2852 03:08:09.165172 alsa_mixer-test_event_spurious_LCALTA_1 pass
2853 03:08:09.170279 alsa_mixer-test_get_value_LCALTA_0 pass
2854 03:08:09.170790 alsa_mixer-test_name_LCALTA_0 pass
2855 03:08:09.175787 alsa_mixer-test_write_default_LCALTA_0 pass
2856 03:08:09.181348 alsa_mixer-test_write_valid_LCALTA_0 pass
2857 03:08:09.186866 alsa_mixer-test_write_invalid_LCALTA_0 pass
2858 03:08:09.187349 alsa_mixer-test_event_missing_LCALTA_0 pass
2859 03:08:09.192438 alsa_mixer-test_event_spurious_LCALTA_0 pass
2860 03:08:09.192932 alsa_mixer-test pass
2861 03:08:09.197961 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2862 03:08:09.203515 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2863 03:08:09.209051 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2864 03:08:09.214629 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2865 03:08:09.215122 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2866 03:08:09.220186 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2867 03:08:09.225691 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2868 03:08:09.231254 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2869 03:08:09.236779 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2870 03:08:09.242325 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2871 03:08:09.242807 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2872 03:08:09.247873 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2873 03:08:09.253456 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2874 03:08:09.258992 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2875 03:08:09.264523 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2876 03:08:09.270089 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2877 03:08:09.270577 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2878 03:08:09.275620 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2879 03:08:09.281167 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2880 03:08:09.286729 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2881 03:08:09.292260 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2882 03:08:09.297815 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2883 03:08:09.298300 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2884 03:08:09.303379 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2885 03:08:09.308945 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2886 03:08:09.314451 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2887 03:08:09.320027 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2888 03:08:09.325568 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2889 03:08:09.326059 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2890 03:08:09.331093 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2891 03:08:09.336659 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2892 03:08:09.342200 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2893 03:08:09.347764 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2894 03:08:09.353302 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2895 03:08:09.358938 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2896 03:08:09.359435 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2897 03:08:09.364357 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2898 03:08:09.369930 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2899 03:08:09.375543 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2900 03:08:09.381099 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2901 03:08:09.386613 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2902 03:08:09.387153 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2903 03:08:09.392148 alsa_pcm-test pass
2904 03:08:09.397680 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2905 03:08:09.408679 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2906 03:08:09.414340 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2907 03:08:09.425370 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2908 03:08:09.430995 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2909 03:08:09.436504 alsa_test-pcmtest-driver pass
2910 03:08:09.442061 alsa_utimer-test_global_wrong_timers_test pass
2911 03:08:09.442562 alsa_utimer-test_timer_f_utimer fail
2912 03:08:09.447579 alsa_utimer-test fail
2913 03:08:09.448116 + ../../utils/send-to-lava.sh ./output/result.txt
2914 03:08:09.453102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2915 03:08:09.454055 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2917 03:08:09.464191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2918 03:08:09.464971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2920 03:08:09.470009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2921 03:08:09.470768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2923 03:08:09.526363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2924 03:08:09.527219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2926 03:08:09.576612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2927 03:08:09.577424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2929 03:08:09.620740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2930 03:08:09.621539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2932 03:08:09.681991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2933 03:08:09.682759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2935 03:08:09.733337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2936 03:08:09.734173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2938 03:08:09.776705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2939 03:08:09.777535 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2941 03:08:09.833457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2942 03:08:09.834258 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2944 03:08:09.884149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2945 03:08:09.884912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2947 03:08:09.938978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2948 03:08:09.939747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2950 03:08:09.989094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2951 03:08:09.989850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2953 03:08:10.052518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2954 03:08:10.053384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2956 03:08:10.097061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2957 03:08:10.097843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2959 03:08:10.151529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2960 03:08:10.152369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2962 03:08:10.196325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2963 03:08:10.197127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2965 03:08:10.245358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2966 03:08:10.246168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2968 03:08:10.297400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2969 03:08:10.298209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2971 03:08:10.355925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2972 03:08:10.356768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2974 03:08:10.401530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2975 03:08:10.402363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2977 03:08:10.446251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2978 03:08:10.447091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2980 03:08:10.491887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2981 03:08:10.492721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2983 03:08:10.540375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2984 03:08:10.541218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2986 03:08:10.592267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2987 03:08:10.593089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2989 03:08:10.652474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2990 03:08:10.653262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2992 03:08:10.705614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
2993 03:08:10.706371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
2995 03:08:10.765890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
2996 03:08:10.766660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
2998 03:08:10.812913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
2999 03:08:10.813668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3001 03:08:10.869079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3002 03:08:10.869839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3004 03:08:10.921439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3005 03:08:10.922218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3007 03:08:10.977568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3008 03:08:10.978320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3010 03:08:11.033614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3011 03:08:11.034392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3013 03:08:11.085247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3014 03:08:11.086006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3016 03:08:11.140312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3017 03:08:11.141067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3019 03:08:11.191763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3020 03:08:11.192550 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3022 03:08:11.250945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3023 03:08:11.251709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3025 03:08:11.305500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3026 03:08:11.306258 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3028 03:08:11.373045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3029 03:08:11.373903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3031 03:08:11.417497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3032 03:08:11.418338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3034 03:08:11.466340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3035 03:08:11.467108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3037 03:08:11.516837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3038 03:08:11.517630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3040 03:08:11.570177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3041 03:08:11.570951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3043 03:08:11.627860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3044 03:08:11.628664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3046 03:08:11.684524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3047 03:08:11.685281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3049 03:08:11.738960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3050 03:08:11.739715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3052 03:08:11.791063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3053 03:08:11.791811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3055 03:08:11.853623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3056 03:08:11.854370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3058 03:08:11.898143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3059 03:08:11.898888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3061 03:08:11.949229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3062 03:08:11.949973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3064 03:08:11.993145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3065 03:08:11.993889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3067 03:08:12.045766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3068 03:08:12.046523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3070 03:08:12.098357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3071 03:08:12.099101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3073 03:08:12.150560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3074 03:08:12.151304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3076 03:08:12.204992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3077 03:08:12.205733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3079 03:08:12.259748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3080 03:08:12.260573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3082 03:08:12.313461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3083 03:08:12.314220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3085 03:08:12.364565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3086 03:08:12.365322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3088 03:08:12.424459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3089 03:08:12.425295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3091 03:08:12.470294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3092 03:08:12.471040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3094 03:08:12.525872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3095 03:08:12.526695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3097 03:08:12.576813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3098 03:08:12.577577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3100 03:08:12.636322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3101 03:08:12.637083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3103 03:08:12.690915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3104 03:08:12.691660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3106 03:08:12.743057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3107 03:08:12.743801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3109 03:08:12.804199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3110 03:08:12.804954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3112 03:08:12.857677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3113 03:08:12.858430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3115 03:08:12.909698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3116 03:08:12.910437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3118 03:08:12.966430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3119 03:08:12.967167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3121 03:08:13.032506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3122 03:08:13.033290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3124 03:08:13.084531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3125 03:08:13.085279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3127 03:08:13.139638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3128 03:08:13.140415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3130 03:08:13.191899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3131 03:08:13.192669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3133 03:08:13.249193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3134 03:08:13.249940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3136 03:08:13.305484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3137 03:08:13.306234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3139 03:08:13.363743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3140 03:08:13.364547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3142 03:08:13.423676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3143 03:08:13.424538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3145 03:08:13.470493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3146 03:08:13.471246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3148 03:08:13.522405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3149 03:08:13.523219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3151 03:08:13.574055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3152 03:08:13.574852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3154 03:08:13.627774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3155 03:08:13.628576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3157 03:08:13.673532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3158 03:08:13.674282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3160 03:08:13.719162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3161 03:08:13.719902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3163 03:08:13.765607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3164 03:08:13.766363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3166 03:08:13.811153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3167 03:08:13.811933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3169 03:08:13.856255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3170 03:08:13.857006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3172 03:08:13.902192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3173 03:08:13.902939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3175 03:08:13.948574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3176 03:08:13.949312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3178 03:08:13.994344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3179 03:08:13.995088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3181 03:08:14.041828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3182 03:08:14.042607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3184 03:08:14.090778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3185 03:08:14.091553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3187 03:08:14.143010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3188 03:08:14.143746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3190 03:08:14.188834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3191 03:08:14.189560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3193 03:08:14.233493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3194 03:08:14.234215 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3196 03:08:14.286827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3197 03:08:14.287569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3199 03:08:14.332611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3200 03:08:14.333334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3202 03:08:14.379587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3203 03:08:14.380488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3205 03:08:14.425458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3206 03:08:14.426298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3208 03:08:14.471783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3209 03:08:14.472602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3211 03:08:14.519509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3212 03:08:14.520376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3214 03:08:14.576111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3215 03:08:14.576940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3217 03:08:14.624022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3218 03:08:14.624833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3220 03:08:14.683063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3221 03:08:14.683851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3223 03:08:14.736832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3224 03:08:14.737608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3226 03:08:14.799054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3227 03:08:14.799844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3229 03:08:14.855199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3230 03:08:14.856009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3232 03:08:14.911430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3233 03:08:14.912210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3235 03:08:14.964324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3236 03:08:14.965129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3238 03:08:15.020120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3239 03:08:15.020918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3241 03:08:15.065983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3242 03:08:15.066794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3244 03:08:15.111066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3245 03:08:15.111846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3247 03:08:15.170989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3248 03:08:15.171761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3250 03:08:15.219018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3251 03:08:15.219791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3253 03:08:15.271935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3254 03:08:15.272754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3256 03:08:15.333469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3257 03:08:15.334240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3259 03:08:15.380206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3260 03:08:15.381103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3262 03:08:15.426750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3263 03:08:15.427648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3265 03:08:15.484607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3266 03:08:15.485468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3268 03:08:15.534251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3269 03:08:15.535119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3271 03:08:15.592672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3272 03:08:15.593500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3274 03:08:15.637755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3275 03:08:15.638635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3277 03:08:15.688374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3278 03:08:15.689252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3280 03:08:15.755667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3281 03:08:15.757211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3283 03:08:15.811153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3284 03:08:15.812081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3286 03:08:15.857960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3287 03:08:15.858744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3289 03:08:15.908979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3290 03:08:15.909743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3292 03:08:15.957679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3293 03:08:15.958428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3295 03:08:16.011113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3296 03:08:16.011868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3298 03:08:16.067566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3299 03:08:16.068357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3301 03:08:16.120234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3302 03:08:16.121010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3304 03:08:16.172431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3305 03:08:16.173174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3307 03:08:16.229522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3308 03:08:16.230294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3310 03:08:16.280827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3311 03:08:16.281566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3313 03:08:16.337883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3314 03:08:16.338647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3316 03:08:16.393422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3317 03:08:16.394231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3319 03:08:16.447634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3320 03:08:16.448506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3322 03:08:16.492843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3323 03:08:16.493593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3325 03:08:16.545434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3326 03:08:16.546201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3328 03:08:16.590690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3329 03:08:16.591444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3331 03:08:16.642680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3332 03:08:16.643424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3334 03:08:16.694224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3335 03:08:16.695004 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3337 03:08:16.739153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3338 03:08:16.739902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3340 03:08:16.797347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3341 03:08:16.798081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3343 03:08:16.843309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3344 03:08:16.844085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3346 03:08:16.895121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3347 03:08:16.895857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3349 03:08:16.942692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3350 03:08:16.943431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3352 03:08:16.992927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3353 03:08:16.993668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3355 03:08:17.046534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3356 03:08:17.047281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3358 03:08:17.092276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3359 03:08:17.093015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3361 03:08:17.151420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3362 03:08:17.152158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3364 03:08:17.207816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3365 03:08:17.208611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3367 03:08:17.264510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3368 03:08:17.265256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3370 03:08:17.315555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3371 03:08:17.316339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3373 03:08:17.359466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3374 03:08:17.360282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3376 03:08:17.413344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3377 03:08:17.414167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3379 03:08:17.466327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3380 03:08:17.467074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3382 03:08:17.517354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3383 03:08:17.518112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3385 03:08:17.572387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3386 03:08:17.573144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3388 03:08:17.622191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3389 03:08:17.622934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3391 03:08:17.668919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3392 03:08:17.669660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3394 03:08:17.716306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3395 03:08:17.717041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3397 03:08:17.760822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3398 03:08:17.761593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3400 03:08:17.806887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3401 03:08:17.807649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3403 03:08:17.854471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3404 03:08:17.855249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3406 03:08:17.914621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3407 03:08:17.915396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3409 03:08:17.958752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3410 03:08:17.959517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3412 03:08:18.012285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3413 03:08:18.013072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3415 03:08:18.060168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3416 03:08:18.060953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3418 03:08:18.264458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3419 03:08:18.265264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3421 03:08:18.310158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3422 03:08:18.310921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3424 03:08:18.362966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3425 03:08:18.363762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3427 03:08:18.417312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3428 03:08:18.418130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3430 03:08:18.460956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3431 03:08:18.461708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3433 03:08:18.506936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3434 03:08:18.507718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3436 03:08:18.557698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3437 03:08:18.558485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3439 03:08:18.608485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3440 03:08:18.609260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3442 03:08:18.653749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3443 03:08:18.654508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3445 03:08:18.706653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3446 03:08:18.707395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3448 03:08:18.760745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3449 03:08:18.761507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3451 03:08:18.806923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3452 03:08:18.807683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3454 03:08:18.864521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3455 03:08:18.865278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3457 03:08:18.914917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3458 03:08:18.915660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3460 03:08:18.966874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3461 03:08:18.967616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3463 03:08:19.014130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3464 03:08:19.014876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3466 03:08:19.062479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3467 03:08:19.063260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3469 03:08:19.115269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3470 03:08:19.116092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3472 03:08:19.159944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3473 03:08:19.160724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3475 03:08:19.216212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3476 03:08:19.216936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3478 03:08:19.269103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3479 03:08:19.269849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3481 03:08:19.324806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3482 03:08:19.325545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3484 03:08:19.381324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3485 03:08:19.382150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3487 03:08:19.434490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3488 03:08:19.435305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3490 03:08:19.480086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3491 03:08:19.480850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3493 03:08:19.538079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3494 03:08:19.538862 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3496 03:08:19.593528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3497 03:08:19.594326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3499 03:08:19.641672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3500 03:08:19.642428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3502 03:08:19.695090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3503 03:08:19.695840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3505 03:08:19.739938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3506 03:08:19.740738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3508 03:08:19.795280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3509 03:08:19.796074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3511 03:08:19.855528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3512 03:08:19.856323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3514 03:08:19.906970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3515 03:08:19.907729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3517 03:08:19.957917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3518 03:08:19.958667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3520 03:08:20.010796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3521 03:08:20.011566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3523 03:08:20.061409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3524 03:08:20.062185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3526 03:08:20.105419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3527 03:08:20.106180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3529 03:08:20.161075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3530 03:08:20.161835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3532 03:08:20.212236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3533 03:08:20.212988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3535 03:08:20.264891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3536 03:08:20.265656 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3538 03:08:20.319696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3539 03:08:20.320533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3541 03:08:20.374452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3542 03:08:20.375260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3544 03:08:20.426180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3545 03:08:20.426996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3547 03:08:20.478369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3548 03:08:20.479136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3550 03:08:20.538641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3551 03:08:20.539435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3553 03:08:20.585483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3554 03:08:20.586268 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3556 03:08:20.631697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3557 03:08:20.632500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3559 03:08:20.677578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3560 03:08:20.678330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3562 03:08:20.723722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3563 03:08:20.724528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3565 03:08:20.771629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3566 03:08:20.772421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3568 03:08:20.818675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3569 03:08:20.819425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3571 03:08:20.867179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3572 03:08:20.867946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3574 03:08:20.914141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3575 03:08:20.914893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3577 03:08:20.961639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3578 03:08:20.962391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3580 03:08:21.007301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3581 03:08:21.008087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3583 03:08:21.057997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3584 03:08:21.058763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3586 03:08:21.103836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3587 03:08:21.104634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3589 03:08:21.150597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3590 03:08:21.151348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3592 03:08:21.200212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3593 03:08:21.200964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3595 03:08:21.254624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3596 03:08:21.255380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3598 03:08:21.304073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3599 03:08:21.304850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3601 03:08:21.348901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3602 03:08:21.349695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3604 03:08:21.400197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3605 03:08:21.400958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3607 03:08:21.448337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3608 03:08:21.449150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3610 03:08:21.492903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3611 03:08:21.493663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3613 03:08:21.539437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3614 03:08:21.540224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3616 03:08:21.587778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3617 03:08:21.588619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3619 03:08:21.633226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3620 03:08:21.633987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3622 03:08:21.678560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3623 03:08:21.679309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3625 03:08:21.723012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3626 03:08:21.723766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3628 03:08:21.770751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3629 03:08:21.771515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3631 03:08:21.815495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3632 03:08:21.816282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3634 03:08:21.863865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3635 03:08:21.864672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3637 03:08:21.911317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3638 03:08:21.912066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3640 03:08:21.958197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3641 03:08:21.958944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3643 03:08:22.004405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3644 03:08:22.005162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3646 03:08:22.050060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3647 03:08:22.050821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3649 03:08:22.097149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3650 03:08:22.097957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3652 03:08:22.142715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3653 03:08:22.143464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3655 03:08:22.187633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3656 03:08:22.188474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3658 03:08:22.237496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3659 03:08:22.238246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3661 03:08:22.288276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3662 03:08:22.289030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3664 03:08:22.339850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3665 03:08:22.340650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3667 03:08:22.386200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3668 03:08:22.386993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3670 03:08:22.431644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3671 03:08:22.432479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3673 03:08:22.479370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3674 03:08:22.480120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3676 03:08:22.523868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3677 03:08:22.524701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3679 03:08:22.568923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3680 03:08:22.569709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3682 03:08:22.615024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3683 03:08:22.615777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3685 03:08:22.662535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3686 03:08:22.663289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3688 03:08:22.711091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3689 03:08:22.711841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3691 03:08:22.759404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3692 03:08:22.760162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3694 03:08:22.814526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3695 03:08:22.815278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3697 03:08:22.861222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3698 03:08:22.861971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3700 03:08:22.907951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3701 03:08:22.908734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3703 03:08:22.953378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3704 03:08:22.954120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3706 03:08:23.002946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3707 03:08:23.003701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3709 03:08:23.071846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3710 03:08:23.072637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3712 03:08:23.120939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3713 03:08:23.121681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3715 03:08:23.166437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3716 03:08:23.167184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3718 03:08:23.216038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3719 03:08:23.216788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3721 03:08:23.270997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3722 03:08:23.271750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3724 03:08:23.330655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3725 03:08:23.331403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3727 03:08:23.377943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3728 03:08:23.378730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3730 03:08:23.428247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3731 03:08:23.429055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3733 03:08:23.473894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3734 03:08:23.474644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3736 03:08:23.523046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3737 03:08:23.523827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3739 03:08:23.568641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3740 03:08:23.569432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3742 03:08:23.614548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3743 03:08:23.615294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3745 03:08:23.668301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3746 03:08:23.669045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3748 03:08:23.721425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3749 03:08:23.722173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3751 03:08:23.767743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3752 03:08:23.768541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3754 03:08:23.825651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3755 03:08:23.826397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3757 03:08:23.870641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3758 03:08:23.871390 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3760 03:08:23.923149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3761 03:08:23.923889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3763 03:08:23.980429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3764 03:08:23.981176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3766 03:08:24.035110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3767 03:08:24.035881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3769 03:08:24.080171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3770 03:08:24.080926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3772 03:08:24.125114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3773 03:08:24.125925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3775 03:08:24.172068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3776 03:08:24.172796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3778 03:08:24.223119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3779 03:08:24.223836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3781 03:08:24.270451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3782 03:08:24.271188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3784 03:08:24.315533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3785 03:08:24.316302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3787 03:08:24.368254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3788 03:08:24.369027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3790 03:08:24.419313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3791 03:08:24.420361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3793 03:08:24.465868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3794 03:08:24.466627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3796 03:08:24.513158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3797 03:08:24.513943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3799 03:08:24.558692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3800 03:08:24.559479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3802 03:08:24.606142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3803 03:08:24.606912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3805 03:08:24.654644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3806 03:08:24.655403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3808 03:08:24.702846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3809 03:08:24.703596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3811 03:08:24.752944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3812 03:08:24.753695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3814 03:08:24.798801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3815 03:08:24.799538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3817 03:08:24.851912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3818 03:08:24.852714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3820 03:08:24.904227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3821 03:08:24.904972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3823 03:08:24.955863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3824 03:08:24.956659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3826 03:08:25.004974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3827 03:08:25.005724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3829 03:08:25.054633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3830 03:08:25.055375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3832 03:08:25.103744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3833 03:08:25.104528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3835 03:08:25.149898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3836 03:08:25.150646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3838 03:08:25.196602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3839 03:08:25.197355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3841 03:08:25.244741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3842 03:08:25.245491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3844 03:08:25.298322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3845 03:08:25.299074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3847 03:08:25.345612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3848 03:08:25.346452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3850 03:08:25.401740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3851 03:08:25.402501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3853 03:08:25.454262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3854 03:08:25.455064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3856 03:08:25.513920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3857 03:08:25.514696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3859 03:08:25.559311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3860 03:08:25.560111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3862 03:08:25.617076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3863 03:08:25.617842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3865 03:08:25.661004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3866 03:08:25.661754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3868 03:08:25.709841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3869 03:08:25.710582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3871 03:08:25.755650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3872 03:08:25.756447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3874 03:08:25.801270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3875 03:08:25.802010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3877 03:08:25.852427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3878 03:08:25.853170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3880 03:08:25.901472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3881 03:08:25.902209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3883 03:08:25.958939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3884 03:08:25.959675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3886 03:08:26.006261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3887 03:08:26.007003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3889 03:08:26.052894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3890 03:08:26.053642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3892 03:08:26.098309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3893 03:08:26.099052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3895 03:08:26.149916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3896 03:08:26.150662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3898 03:08:26.202097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3899 03:08:26.202845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3901 03:08:26.253539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3902 03:08:26.254291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3904 03:08:26.296893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3905 03:08:26.297645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3907 03:08:26.347049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3908 03:08:26.347831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3910 03:08:26.407965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3911 03:08:26.408830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3913 03:08:26.458576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3914 03:08:26.459386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3916 03:08:26.504223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3917 03:08:26.504999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3919 03:08:26.556206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3920 03:08:26.556994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3922 03:08:26.603640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3923 03:08:26.604443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3925 03:08:26.655363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3926 03:08:26.656119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3928 03:08:26.700218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3929 03:08:26.700968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3931 03:08:26.745519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3932 03:08:26.746263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3934 03:08:26.793055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3935 03:08:26.793794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3937 03:08:26.855077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3938 03:08:26.855825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3940 03:08:26.906390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3941 03:08:26.907129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3943 03:08:26.956208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3944 03:08:26.956954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3946 03:08:27.015472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3947 03:08:27.016211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3949 03:08:27.063267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3950 03:08:27.064062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3952 03:08:27.109358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3953 03:08:27.110100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3955 03:08:27.157539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3956 03:08:27.158289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3958 03:08:27.201648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3959 03:08:27.202387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3961 03:08:27.251667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3962 03:08:27.252464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3964 03:08:27.296774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3965 03:08:27.297518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3967 03:08:27.350098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3968 03:08:27.350872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3970 03:08:27.397064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3971 03:08:27.397824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3973 03:08:27.442781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3974 03:08:27.443593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3976 03:08:27.486715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3977 03:08:27.487470 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3979 03:08:27.533429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3980 03:08:27.534203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3982 03:08:27.582735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3983 03:08:27.583508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3985 03:08:27.630202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3986 03:08:27.630957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3988 03:08:27.673297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3989 03:08:27.674043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3991 03:08:27.719434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3992 03:08:27.720175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
3994 03:08:27.766830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
3995 03:08:27.767575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
3997 03:08:27.816790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
3998 03:08:27.817530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4000 03:08:27.863537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4001 03:08:27.864325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4003 03:08:27.910125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4004 03:08:27.910867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4006 03:08:27.957276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4007 03:08:27.958024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4009 03:08:28.002045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4010 03:08:28.002782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4012 03:08:28.047351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4013 03:08:28.048118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4015 03:08:28.092312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4016 03:08:28.093046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4018 03:08:28.135235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4019 03:08:28.135974 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4021 03:08:28.179142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4022 03:08:28.179877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4024 03:08:28.224233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4025 03:08:28.224964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4027 03:08:28.268523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4028 03:08:28.269274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4030 03:08:28.313218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4031 03:08:28.313962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4033 03:08:28.358212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4034 03:08:28.358982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4036 03:08:28.408880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4037 03:08:28.409642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4039 03:08:28.454544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4040 03:08:28.455353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4042 03:08:28.498056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4043 03:08:28.498804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4045 03:08:28.548042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4046 03:08:28.548840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4048 03:08:28.595563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4049 03:08:28.596364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4051 03:08:28.640784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4052 03:08:28.641539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4054 03:08:28.686378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4055 03:08:28.687121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4057 03:08:28.734369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4058 03:08:28.735112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4060 03:08:28.779294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4061 03:08:28.780074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4063 03:08:28.823966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4064 03:08:28.824745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4066 03:08:28.870341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4067 03:08:28.871096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4069 03:08:28.914787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4070 03:08:28.915534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4072 03:08:28.959604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4073 03:08:28.960388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4075 03:08:29.007678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4076 03:08:29.008449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4078 03:08:29.061906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4079 03:08:29.062662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4081 03:08:29.107629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4082 03:08:29.108409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4084 03:08:29.153464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4085 03:08:29.154265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4087 03:08:29.200974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4088 03:08:29.201707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4090 03:08:29.246558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4091 03:08:29.247292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4093 03:08:29.295483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4094 03:08:29.296209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4096 03:08:29.340933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4097 03:08:29.341666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4099 03:08:29.389130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4100 03:08:29.389898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4102 03:08:29.433347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4103 03:08:29.434127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4105 03:08:29.485798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4106 03:08:29.486539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4108 03:08:29.530044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4109 03:08:29.530814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4111 03:08:29.575336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4112 03:08:29.576126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4114 03:08:29.620335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4115 03:08:29.621081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4117 03:08:29.664501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4118 03:08:29.665245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4120 03:08:29.712069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4121 03:08:29.712809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4123 03:08:29.755046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4124 03:08:29.755786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4126 03:08:29.801587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4127 03:08:29.802322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4129 03:08:29.846116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4130 03:08:29.846869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4132 03:08:29.893017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4133 03:08:29.893762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4135 03:08:29.936539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4136 03:08:29.937284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4138 03:08:29.980254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4139 03:08:29.980995 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4141 03:08:30.029407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4142 03:08:30.030158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4144 03:08:30.076105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4145 03:08:30.076865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4147 03:08:30.126403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4148 03:08:30.127150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4150 03:08:30.176290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4151 03:08:30.177039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4153 03:08:30.221874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4154 03:08:30.222609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4156 03:08:30.268241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4157 03:08:30.268841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4159 03:08:30.313547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4160 03:08:30.314464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4162 03:08:30.367701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4163 03:08:30.368517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4165 03:08:30.417529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4166 03:08:30.418364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4168 03:08:30.462318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4169 03:08:30.463202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4171 03:08:30.508566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4172 03:08:30.509433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4174 03:08:30.554680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4175 03:08:30.555548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4177 03:08:30.598877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4178 03:08:30.599691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4180 03:08:30.643204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4181 03:08:30.644034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4183 03:08:30.696265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4184 03:08:30.697048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4186 03:08:30.740306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4187 03:08:30.741081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4189 03:08:30.784307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4190 03:08:30.785130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4192 03:08:30.828109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4193 03:08:30.828948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4195 03:08:30.877421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4196 03:08:30.878234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4198 03:08:30.920483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4200 03:08:30.923409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4201 03:08:30.971071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4202 03:08:30.971840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4204 03:08:31.018390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4205 03:08:31.019191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4207 03:08:31.064707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4208 03:08:31.065516 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4210 03:08:31.114439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4211 03:08:31.115248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4213 03:08:31.159722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4214 03:08:31.160553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4216 03:08:31.207946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4217 03:08:31.208789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4219 03:08:31.257188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4220 03:08:31.258014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4222 03:08:31.304458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4223 03:08:31.305249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4225 03:08:31.348168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4226 03:08:31.348953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4228 03:08:31.398297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4229 03:08:31.399127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4231 03:08:31.443465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4232 03:08:31.444279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4234 03:08:31.489206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4235 03:08:31.490006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4237 03:08:31.540127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4238 03:08:31.540978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4240 03:08:31.585167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4241 03:08:31.585973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4243 03:08:31.629109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4244 03:08:31.629880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4246 03:08:31.680908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4247 03:08:31.681697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4249 03:08:31.726381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4250 03:08:31.727137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4252 03:08:31.771204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4253 03:08:31.771962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4255 03:08:31.817125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4256 03:08:31.817892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4258 03:08:31.860454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4259 03:08:31.861208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4261 03:08:31.907273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4262 03:08:31.908074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4264 03:08:31.955799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4265 03:08:31.956580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4267 03:08:32.000231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4268 03:08:32.001001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4270 03:08:32.044992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4271 03:08:32.045780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4273 03:08:32.090662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4274 03:08:32.091447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4276 03:08:32.137035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4277 03:08:32.137874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4279 03:08:32.181235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4280 03:08:32.182102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4282 03:08:32.225310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4283 03:08:32.226072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4285 03:08:32.271258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4286 03:08:32.272058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4288 03:08:32.316901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4289 03:08:32.317643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4291 03:08:32.363413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4292 03:08:32.364170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4294 03:08:32.414148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4295 03:08:32.414965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4297 03:08:32.460527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4298 03:08:32.461275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4300 03:08:32.506837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4301 03:08:32.507633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4303 03:08:32.552100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4304 03:08:32.552896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4306 03:08:32.602509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4307 03:08:32.603283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4309 03:08:32.647637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4310 03:08:32.648440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4312 03:08:32.693092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4313 03:08:32.693840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4315 03:08:32.737774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4316 03:08:32.738513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4318 03:08:32.783754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4319 03:08:32.784553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4321 03:08:32.829366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4322 03:08:32.830113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4324 03:08:32.876279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4325 03:08:32.877021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4327 03:08:32.919783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4328 03:08:32.920562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4330 03:08:32.970011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4331 03:08:32.970754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4333 03:08:33.016302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4334 03:08:33.017062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4336 03:08:33.062756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4337 03:08:33.063514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4339 03:08:33.109959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4340 03:08:33.110711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4342 03:08:33.165535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4343 03:08:33.166294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4345 03:08:33.203626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4346 03:08:33.204417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4348 03:08:33.250403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4349 03:08:33.251149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4351 03:08:33.296081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4352 03:08:33.296834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4354 03:08:33.336891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4356 03:08:33.342264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4357 03:08:33.342754 + set +x
4358 03:08:33.348099 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 957122_1.6.2.4.5>
4359 03:08:33.348589 <LAVA_TEST_RUNNER EXIT>
4360 03:08:33.349257 Received signal: <ENDRUN> 1_kselftest-alsa 957122_1.6.2.4.5
4361 03:08:33.349711 Ending use of test pattern.
4362 03:08:33.350126 Ending test lava.1_kselftest-alsa (957122_1.6.2.4.5), duration 40.52
4364 03:08:33.351625 ok: lava_test_shell seems to have completed
4365 03:08:33.373681 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4366 03:08:33.375595 end: 3.1 lava-test-shell (duration 00:00:41) [common]
4367 03:08:33.376241 end: 3 lava-test-retry (duration 00:00:41) [common]
4368 03:08:33.376838 start: 4 finalize (timeout 00:06:09) [common]
4369 03:08:33.377438 start: 4.1 power-off (timeout 00:00:30) [common]
4370 03:08:33.378402 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4371 03:08:33.412228 >> OK - accepted request
4372 03:08:33.414339 Returned 0 in 0 seconds
4373 03:08:33.515416 end: 4.1 power-off (duration 00:00:00) [common]
4375 03:08:33.517244 start: 4.2 read-feedback (timeout 00:06:09) [common]
4376 03:08:33.518393 Listened to connection for namespace 'common' for up to 1s
4377 03:08:34.518538 Finalising connection for namespace 'common'
4378 03:08:34.519324 Disconnecting from shell: Finalise
4379 03:08:34.519887 / #
4380 03:08:34.621056 end: 4.2 read-feedback (duration 00:00:01) [common]
4381 03:08:34.621841 end: 4 finalize (duration 00:00:01) [common]
4382 03:08:34.622484 Cleaning after the job
4383 03:08:34.623057 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/ramdisk
4384 03:08:34.636792 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/kernel
4385 03:08:34.678885 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/dtb
4386 03:08:34.679758 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/nfsrootfs
4387 03:08:34.856601 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957122/tftp-deploy-1g181j3g/modules
4388 03:08:34.878108 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/957122
4389 03:08:38.045330 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/957122
4390 03:08:38.045964 Job finished correctly