Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 03:53:24.269453 lava-dispatcher, installed at version: 2024.01
2 03:53:24.270227 start: 0 validate
3 03:53:24.270697 Start time: 2024-11-08 03:53:24.270667+00:00 (UTC)
4 03:53:24.271236 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:53:24.271776 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 03:53:24.316152 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:53:24.316709 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 03:53:24.345456 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:53:24.346094 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 03:53:24.376945 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:53:24.377431 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 03:53:24.409364 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 03:53:24.409854 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-169-g906bd684e4b1e%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 03:53:24.444758 validate duration: 0.17
16 03:53:24.445638 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 03:53:24.445989 start: 1.1 download-retry (timeout 00:10:00) [common]
18 03:53:24.446305 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 03:53:24.446921 Not decompressing ramdisk as can be used compressed.
20 03:53:24.447398 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 03:53:24.447690 saving as /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/ramdisk/initrd.cpio.gz
22 03:53:24.447999 total size: 5628140 (5 MB)
23 03:53:24.483792 progress 0 % (0 MB)
24 03:53:24.488048 progress 5 % (0 MB)
25 03:53:24.492376 progress 10 % (0 MB)
26 03:53:24.496474 progress 15 % (0 MB)
27 03:53:24.500786 progress 20 % (1 MB)
28 03:53:24.504573 progress 25 % (1 MB)
29 03:53:24.508812 progress 30 % (1 MB)
30 03:53:24.513160 progress 35 % (1 MB)
31 03:53:24.517019 progress 40 % (2 MB)
32 03:53:24.521091 progress 45 % (2 MB)
33 03:53:24.524899 progress 50 % (2 MB)
34 03:53:24.529106 progress 55 % (2 MB)
35 03:53:24.533364 progress 60 % (3 MB)
36 03:53:24.537080 progress 65 % (3 MB)
37 03:53:24.541298 progress 70 % (3 MB)
38 03:53:24.545124 progress 75 % (4 MB)
39 03:53:24.549323 progress 80 % (4 MB)
40 03:53:24.553021 progress 85 % (4 MB)
41 03:53:24.557296 progress 90 % (4 MB)
42 03:53:24.561352 progress 95 % (5 MB)
43 03:53:24.564677 progress 100 % (5 MB)
44 03:53:24.565340 5 MB downloaded in 0.12 s (45.74 MB/s)
45 03:53:24.565918 end: 1.1.1 http-download (duration 00:00:00) [common]
47 03:53:24.566849 end: 1.1 download-retry (duration 00:00:00) [common]
48 03:53:24.567172 start: 1.2 download-retry (timeout 00:10:00) [common]
49 03:53:24.567524 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 03:53:24.568056 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/gcc-12/kernel/Image
51 03:53:24.568349 saving as /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/kernel/Image
52 03:53:24.568574 total size: 45713920 (43 MB)
53 03:53:24.568797 No compression specified
54 03:53:24.606851 progress 0 % (0 MB)
55 03:53:24.634688 progress 5 % (2 MB)
56 03:53:24.662796 progress 10 % (4 MB)
57 03:53:24.691228 progress 15 % (6 MB)
58 03:53:24.719199 progress 20 % (8 MB)
59 03:53:24.746830 progress 25 % (10 MB)
60 03:53:24.774806 progress 30 % (13 MB)
61 03:53:24.803199 progress 35 % (15 MB)
62 03:53:24.831254 progress 40 % (17 MB)
63 03:53:24.859014 progress 45 % (19 MB)
64 03:53:24.887467 progress 50 % (21 MB)
65 03:53:24.915586 progress 55 % (24 MB)
66 03:53:24.943740 progress 60 % (26 MB)
67 03:53:24.971578 progress 65 % (28 MB)
68 03:53:24.999770 progress 70 % (30 MB)
69 03:53:25.028152 progress 75 % (32 MB)
70 03:53:25.056182 progress 80 % (34 MB)
71 03:53:25.084170 progress 85 % (37 MB)
72 03:53:25.112285 progress 90 % (39 MB)
73 03:53:25.140420 progress 95 % (41 MB)
74 03:53:25.168055 progress 100 % (43 MB)
75 03:53:25.168591 43 MB downloaded in 0.60 s (72.66 MB/s)
76 03:53:25.169089 end: 1.2.1 http-download (duration 00:00:01) [common]
78 03:53:25.169944 end: 1.2 download-retry (duration 00:00:01) [common]
79 03:53:25.170243 start: 1.3 download-retry (timeout 00:09:59) [common]
80 03:53:25.170530 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 03:53:25.171003 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
82 03:53:25.171285 saving as /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/dtb/meson-sm1-s905d3-libretech-cc.dtb
83 03:53:25.171506 total size: 53209 (0 MB)
84 03:53:25.171725 No compression specified
85 03:53:25.214728 progress 61 % (0 MB)
86 03:53:25.215741 progress 100 % (0 MB)
87 03:53:25.216444 0 MB downloaded in 0.04 s (1.13 MB/s)
88 03:53:25.217058 end: 1.3.1 http-download (duration 00:00:00) [common]
90 03:53:25.218036 end: 1.3 download-retry (duration 00:00:00) [common]
91 03:53:25.218357 start: 1.4 download-retry (timeout 00:09:59) [common]
92 03:53:25.218677 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 03:53:25.219216 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 03:53:25.219510 saving as /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/nfsrootfs/full.rootfs.tar
95 03:53:25.219756 total size: 474398908 (452 MB)
96 03:53:25.220031 Using unxz to decompress xz
97 03:53:25.258069 progress 0 % (0 MB)
98 03:53:26.430317 progress 5 % (22 MB)
99 03:53:27.943862 progress 10 % (45 MB)
100 03:53:28.398186 progress 15 % (67 MB)
101 03:53:29.200416 progress 20 % (90 MB)
102 03:53:29.754624 progress 25 % (113 MB)
103 03:53:30.129489 progress 30 % (135 MB)
104 03:53:30.746011 progress 35 % (158 MB)
105 03:53:31.697645 progress 40 % (181 MB)
106 03:53:32.586829 progress 45 % (203 MB)
107 03:53:33.340512 progress 50 % (226 MB)
108 03:53:33.997004 progress 55 % (248 MB)
109 03:53:35.225409 progress 60 % (271 MB)
110 03:53:36.722529 progress 65 % (294 MB)
111 03:53:38.375887 progress 70 % (316 MB)
112 03:53:41.463237 progress 75 % (339 MB)
113 03:53:43.903022 progress 80 % (361 MB)
114 03:53:46.800884 progress 85 % (384 MB)
115 03:53:49.945279 progress 90 % (407 MB)
116 03:53:53.115202 progress 95 % (429 MB)
117 03:53:56.286984 progress 100 % (452 MB)
118 03:53:56.300461 452 MB downloaded in 31.08 s (14.56 MB/s)
119 03:53:56.301148 end: 1.4.1 http-download (duration 00:00:31) [common]
121 03:53:56.301982 end: 1.4 download-retry (duration 00:00:31) [common]
122 03:53:56.302252 start: 1.5 download-retry (timeout 00:09:28) [common]
123 03:53:56.302514 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 03:53:56.303044 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-169-g906bd684e4b1e/arm64/defconfig/gcc-12/modules.tar.xz
125 03:53:56.303299 saving as /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/modules/modules.tar
126 03:53:56.303560 total size: 11613712 (11 MB)
127 03:53:56.304103 Using unxz to decompress xz
128 03:53:56.371130 progress 0 % (0 MB)
129 03:53:56.443439 progress 5 % (0 MB)
130 03:53:56.536437 progress 10 % (1 MB)
131 03:53:56.633466 progress 15 % (1 MB)
132 03:53:56.725381 progress 20 % (2 MB)
133 03:53:56.804961 progress 25 % (2 MB)
134 03:53:56.880596 progress 30 % (3 MB)
135 03:53:56.959891 progress 35 % (3 MB)
136 03:53:57.032743 progress 40 % (4 MB)
137 03:53:57.109501 progress 45 % (5 MB)
138 03:53:57.193152 progress 50 % (5 MB)
139 03:53:57.269858 progress 55 % (6 MB)
140 03:53:57.354742 progress 60 % (6 MB)
141 03:53:57.436983 progress 65 % (7 MB)
142 03:53:57.520531 progress 70 % (7 MB)
143 03:53:57.600274 progress 75 % (8 MB)
144 03:53:57.683500 progress 80 % (8 MB)
145 03:53:57.762967 progress 85 % (9 MB)
146 03:53:57.841141 progress 90 % (9 MB)
147 03:53:57.918316 progress 95 % (10 MB)
148 03:53:57.994445 progress 100 % (11 MB)
149 03:53:58.006254 11 MB downloaded in 1.70 s (6.50 MB/s)
150 03:53:58.007162 end: 1.5.1 http-download (duration 00:00:02) [common]
152 03:53:58.008814 end: 1.5 download-retry (duration 00:00:02) [common]
153 03:53:58.009331 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 03:53:58.009839 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 03:54:13.357819 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/957111/extract-nfsrootfs-772nx614
156 03:54:13.358385 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 03:54:13.358668 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 03:54:13.359279 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup
159 03:54:13.359703 makedir: /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin
160 03:54:13.360067 makedir: /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/tests
161 03:54:13.360395 makedir: /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/results
162 03:54:13.360747 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-add-keys
163 03:54:13.361304 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-add-sources
164 03:54:13.361811 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-background-process-start
165 03:54:13.362304 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-background-process-stop
166 03:54:13.362828 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-common-functions
167 03:54:13.363319 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-echo-ipv4
168 03:54:13.363800 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-install-packages
169 03:54:13.364339 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-installed-packages
170 03:54:13.364829 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-os-build
171 03:54:13.365307 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-probe-channel
172 03:54:13.365780 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-probe-ip
173 03:54:13.366252 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-target-ip
174 03:54:13.366765 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-target-mac
175 03:54:13.367247 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-target-storage
176 03:54:13.367758 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-test-case
177 03:54:13.368300 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-test-event
178 03:54:13.368782 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-test-feedback
179 03:54:13.369250 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-test-raise
180 03:54:13.369718 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-test-reference
181 03:54:13.370191 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-test-runner
182 03:54:13.370668 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-test-set
183 03:54:13.371139 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-test-shell
184 03:54:13.371662 Updating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-install-packages (oe)
185 03:54:13.372293 Updating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/bin/lava-installed-packages (oe)
186 03:54:13.372767 Creating /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/environment
187 03:54:13.373140 LAVA metadata
188 03:54:13.373394 - LAVA_JOB_ID=957111
189 03:54:13.373605 - LAVA_DISPATCHER_IP=192.168.6.2
190 03:54:13.373959 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 03:54:13.374909 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 03:54:13.375222 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 03:54:13.375431 skipped lava-vland-overlay
194 03:54:13.375670 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 03:54:13.375919 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 03:54:13.376176 skipped lava-multinode-overlay
197 03:54:13.376419 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 03:54:13.376670 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 03:54:13.376918 Loading test definitions
200 03:54:13.377195 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 03:54:13.377413 Using /lava-957111 at stage 0
202 03:54:13.378583 uuid=957111_1.6.2.4.1 testdef=None
203 03:54:13.378886 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 03:54:13.379142 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 03:54:13.380907 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 03:54:13.381697 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 03:54:13.383874 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 03:54:13.384748 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 03:54:13.386805 runner path: /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 957111_1.6.2.4.1
212 03:54:13.387379 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 03:54:13.388179 Creating lava-test-runner.conf files
215 03:54:13.388383 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/957111/lava-overlay-208bgnup/lava-957111/0 for stage 0
216 03:54:13.388721 - 0_v4l2-decoder-conformance-vp9
217 03:54:13.389079 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 03:54:13.389353 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 03:54:13.411003 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 03:54:13.411380 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 03:54:13.411655 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 03:54:13.411922 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 03:54:13.412212 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 03:54:14.026851 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 03:54:14.027310 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 03:54:14.027560 extracting modules file /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/957111/extract-nfsrootfs-772nx614
227 03:54:15.411144 extracting modules file /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/957111/extract-overlay-ramdisk-iw2t8krr/ramdisk
228 03:54:16.798703 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 03:54:16.799147 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 03:54:16.799422 [common] Applying overlay to NFS
231 03:54:16.799634 [common] Applying overlay /var/lib/lava/dispatcher/tmp/957111/compress-overlay-wu8xembn/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/957111/extract-nfsrootfs-772nx614
232 03:54:16.828444 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 03:54:16.828811 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 03:54:16.829082 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 03:54:16.829309 Converting downloaded kernel to a uImage
236 03:54:16.829614 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/kernel/Image /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/kernel/uImage
237 03:54:17.284496 output: Image Name:
238 03:54:17.284882 output: Created: Fri Nov 8 03:54:16 2024
239 03:54:17.285092 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 03:54:17.285295 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 03:54:17.285496 output: Load Address: 01080000
242 03:54:17.285695 output: Entry Point: 01080000
243 03:54:17.285890 output:
244 03:54:17.286222 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 03:54:17.286485 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 03:54:17.286751 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 03:54:17.287002 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 03:54:17.287258 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 03:54:17.287560 Building ramdisk /var/lib/lava/dispatcher/tmp/957111/extract-overlay-ramdisk-iw2t8krr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/957111/extract-overlay-ramdisk-iw2t8krr/ramdisk
250 03:54:19.433954 >> 166825 blocks
251 03:54:27.134065 Adding RAMdisk u-boot header.
252 03:54:27.134511 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/957111/extract-overlay-ramdisk-iw2t8krr/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/957111/extract-overlay-ramdisk-iw2t8krr/ramdisk.cpio.gz.uboot
253 03:54:27.391493 output: Image Name:
254 03:54:27.391918 output: Created: Fri Nov 8 03:54:27 2024
255 03:54:27.392373 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 03:54:27.392785 output: Data Size: 23431453 Bytes = 22882.28 KiB = 22.35 MiB
257 03:54:27.393199 output: Load Address: 00000000
258 03:54:27.393591 output: Entry Point: 00000000
259 03:54:27.393981 output:
260 03:54:27.394997 rename /var/lib/lava/dispatcher/tmp/957111/extract-overlay-ramdisk-iw2t8krr/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/ramdisk/ramdisk.cpio.gz.uboot
261 03:54:27.395704 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 03:54:27.396282 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
263 03:54:27.396805 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 03:54:27.397266 No LXC device requested
265 03:54:27.397758 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 03:54:27.398260 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 03:54:27.398748 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 03:54:27.399155 Checking files for TFTP limit of 4294967296 bytes.
269 03:54:27.401827 end: 1 tftp-deploy (duration 00:01:03) [common]
270 03:54:27.402405 start: 2 uboot-action (timeout 00:05:00) [common]
271 03:54:27.402922 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 03:54:27.403411 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 03:54:27.403901 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 03:54:27.404505 Using kernel file from prepare-kernel: 957111/tftp-deploy-mwcsjtbd/kernel/uImage
275 03:54:27.405132 substitutions:
276 03:54:27.405535 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 03:54:27.405932 - {DTB_ADDR}: 0x01070000
278 03:54:27.406324 - {DTB}: 957111/tftp-deploy-mwcsjtbd/dtb/meson-sm1-s905d3-libretech-cc.dtb
279 03:54:27.406717 - {INITRD}: 957111/tftp-deploy-mwcsjtbd/ramdisk/ramdisk.cpio.gz.uboot
280 03:54:27.407107 - {KERNEL_ADDR}: 0x01080000
281 03:54:27.407492 - {KERNEL}: 957111/tftp-deploy-mwcsjtbd/kernel/uImage
282 03:54:27.407877 - {LAVA_MAC}: None
283 03:54:27.408369 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/957111/extract-nfsrootfs-772nx614
284 03:54:27.408770 - {NFS_SERVER_IP}: 192.168.6.2
285 03:54:27.409155 - {PRESEED_CONFIG}: None
286 03:54:27.409540 - {PRESEED_LOCAL}: None
287 03:54:27.409927 - {RAMDISK_ADDR}: 0x08000000
288 03:54:27.410310 - {RAMDISK}: 957111/tftp-deploy-mwcsjtbd/ramdisk/ramdisk.cpio.gz.uboot
289 03:54:27.410694 - {ROOT_PART}: None
290 03:54:27.411078 - {ROOT}: None
291 03:54:27.411461 - {SERVER_IP}: 192.168.6.2
292 03:54:27.411843 - {TEE_ADDR}: 0x83000000
293 03:54:27.412259 - {TEE}: None
294 03:54:27.412645 Parsed boot commands:
295 03:54:27.413017 - setenv autoload no
296 03:54:27.413397 - setenv initrd_high 0xffffffff
297 03:54:27.413778 - setenv fdt_high 0xffffffff
298 03:54:27.414159 - dhcp
299 03:54:27.414539 - setenv serverip 192.168.6.2
300 03:54:27.414921 - tftpboot 0x01080000 957111/tftp-deploy-mwcsjtbd/kernel/uImage
301 03:54:27.415302 - tftpboot 0x08000000 957111/tftp-deploy-mwcsjtbd/ramdisk/ramdisk.cpio.gz.uboot
302 03:54:27.415680 - tftpboot 0x01070000 957111/tftp-deploy-mwcsjtbd/dtb/meson-sm1-s905d3-libretech-cc.dtb
303 03:54:27.416087 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/957111/extract-nfsrootfs-772nx614,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 03:54:27.416485 - bootm 0x01080000 0x08000000 0x01070000
305 03:54:27.416989 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 03:54:27.418451 start: 2.3 connect-device (timeout 00:05:00) [common]
308 03:54:27.418864 [common] connect-device Connecting to device using 'telnet conserv1 3008'
309 03:54:27.434083 Setting prompt string to ['lava-test: # ']
310 03:54:27.435566 end: 2.3 connect-device (duration 00:00:00) [common]
311 03:54:27.436191 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 03:54:27.436728 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 03:54:27.437248 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 03:54:27.438386 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
315 03:54:27.474205 >> OK - accepted request
316 03:54:27.476433 Returned 0 in 0 seconds
317 03:54:27.577518 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 03:54:27.579110 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 03:54:27.579677 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 03:54:27.580237 Setting prompt string to ['Hit any key to stop autoboot']
322 03:54:27.580700 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 03:54:27.582262 Trying 192.168.56.21...
324 03:54:27.582731 Connected to conserv1.
325 03:54:27.583147 Escape character is '^]'.
326 03:54:27.583557
327 03:54:27.583969 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 03:54:27.584421
329 03:54:35.104922 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
330 03:54:35.105525 bl2_stage_init 0x01
331 03:54:35.105938 bl2_stage_init 0x81
332 03:54:35.110421 hw id: 0x0000 - pwm id 0x01
333 03:54:35.110860 bl2_stage_init 0xc1
334 03:54:35.115461 bl2_stage_init 0x02
335 03:54:35.115885
336 03:54:35.116339 L0:00000000
337 03:54:35.116748 L1:00000703
338 03:54:35.117137 L2:00008067
339 03:54:35.120917 L3:15000000
340 03:54:35.121354 S1:00000000
341 03:54:35.121757 B2:20282000
342 03:54:35.122152 B1:a0f83180
343 03:54:35.122541
344 03:54:35.122931 TE: 69551
345 03:54:35.123322
346 03:54:35.132126 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
347 03:54:35.132560
348 03:54:35.132957 Board ID = 1
349 03:54:35.133345 Set cpu clk to 24M
350 03:54:35.133733 Set clk81 to 24M
351 03:54:35.137782 Use GP1_pll as DSU clk.
352 03:54:35.138204 DSU clk: 1200 Mhz
353 03:54:35.138595 CPU clk: 1200 MHz
354 03:54:35.143387 Set clk81 to 166.6M
355 03:54:35.148911 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
356 03:54:35.149337 board id: 1
357 03:54:35.156797 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 03:54:35.167719 fw parse done
359 03:54:35.173766 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 03:54:35.216640 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 03:54:35.227898 PIEI prepare done
362 03:54:35.228365 fastboot data load
363 03:54:35.228763 fastboot data verify
364 03:54:35.233398 verify result: 266
365 03:54:35.238985 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
366 03:54:35.239406 LPDDR4 probe
367 03:54:35.239795 ddr clk to 1584MHz
368 03:54:35.246964 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 03:54:35.284752
370 03:54:35.285178 dmc_version 0001
371 03:54:35.291753 Check phy result
372 03:54:35.297700 INFO : End of CA training
373 03:54:35.298122 INFO : End of initialization
374 03:54:35.303315 INFO : Training has run successfully!
375 03:54:35.303729 Check phy result
376 03:54:35.308927 INFO : End of initialization
377 03:54:35.309343 INFO : End of read enable training
378 03:54:35.314612 INFO : End of fine write leveling
379 03:54:35.320205 INFO : End of Write leveling coarse delay
380 03:54:35.320618 INFO : Training has run successfully!
381 03:54:35.321008 Check phy result
382 03:54:35.325732 INFO : End of initialization
383 03:54:35.326145 INFO : End of read dq deskew training
384 03:54:35.331296 INFO : End of MPR read delay center optimization
385 03:54:35.336899 INFO : End of write delay center optimization
386 03:54:35.342613 INFO : End of read delay center optimization
387 03:54:35.343029 INFO : End of max read latency training
388 03:54:35.348141 INFO : Training has run successfully!
389 03:54:35.348558 1D training succeed
390 03:54:35.357321 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 03:54:35.405622 Check phy result
392 03:54:35.406077 INFO : End of initialization
393 03:54:35.433059 INFO : End of 2D read delay Voltage center optimization
394 03:54:35.457257 INFO : End of 2D read delay Voltage center optimization
395 03:54:35.513939 INFO : End of 2D write delay Voltage center optimization
396 03:54:35.567937 INFO : End of 2D write delay Voltage center optimization
397 03:54:35.573497 INFO : Training has run successfully!
398 03:54:35.573750
399 03:54:35.573966 channel==0
400 03:54:35.579019 RxClkDly_Margin_A0==78 ps 8
401 03:54:35.579244 TxDqDly_Margin_A0==88 ps 9
402 03:54:35.584607 RxClkDly_Margin_A1==88 ps 9
403 03:54:35.584830 TxDqDly_Margin_A1==88 ps 9
404 03:54:35.585034 TrainedVREFDQ_A0==74
405 03:54:35.590236 TrainedVREFDQ_A1==74
406 03:54:35.590466 VrefDac_Margin_A0==23
407 03:54:35.590669 DeviceVref_Margin_A0==40
408 03:54:35.595803 VrefDac_Margin_A1==23
409 03:54:35.596035 DeviceVref_Margin_A1==40
410 03:54:35.596236
411 03:54:35.596434
412 03:54:35.596689 channel==1
413 03:54:35.601397 RxClkDly_Margin_A0==78 ps 8
414 03:54:35.601622 TxDqDly_Margin_A0==98 ps 10
415 03:54:35.606985 RxClkDly_Margin_A1==78 ps 8
416 03:54:35.607252 TxDqDly_Margin_A1==78 ps 8
417 03:54:35.612699 TrainedVREFDQ_A0==78
418 03:54:35.613132 TrainedVREFDQ_A1==77
419 03:54:35.613529 VrefDac_Margin_A0==22
420 03:54:35.618317 DeviceVref_Margin_A0==36
421 03:54:35.618792 VrefDac_Margin_A1==20
422 03:54:35.619241 DeviceVref_Margin_A1==37
423 03:54:35.623854
424 03:54:35.624357 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 03:54:35.624793
426 03:54:35.657459 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
427 03:54:35.658017 2D training succeed
428 03:54:35.663026 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 03:54:35.668689 auto size-- 65535DDR cs0 size: 2048MB
430 03:54:35.669210 DDR cs1 size: 2048MB
431 03:54:35.674253 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 03:54:35.674725 cs0 DataBus test pass
433 03:54:35.679854 cs1 DataBus test pass
434 03:54:35.680379 cs0 AddrBus test pass
435 03:54:35.680815 cs1 AddrBus test pass
436 03:54:35.681242
437 03:54:35.685450 100bdlr_step_size ps== 478
438 03:54:35.685931 result report
439 03:54:35.691055 boot times 0Enable ddr reg access
440 03:54:35.696180 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 03:54:35.710042 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
442 03:54:36.369457 bl2z: ptr: 05129330, size: 00001e40
443 03:54:36.377968 0.0;M3 CHK:0;cm4_sp_mode 0
444 03:54:36.378528 MVN_1=0x00000000
445 03:54:36.378988 MVN_2=0x00000000
446 03:54:36.389470 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
447 03:54:36.390038 OPS=0x04
448 03:54:36.390481 ring efuse init
449 03:54:36.392350 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
450 03:54:36.398282 [0.017354 Inits done]
451 03:54:36.398742 secure task start!
452 03:54:36.399175 high task start!
453 03:54:36.399603 low task start!
454 03:54:36.402653 run into bl31
455 03:54:36.411263 NOTICE: BL31: v1.3(release):4fc40b1
456 03:54:36.419074 NOTICE: BL31: Built : 15:57:33, May 22 2019
457 03:54:36.419564 NOTICE: BL31: G12A normal boot!
458 03:54:36.434719 NOTICE: BL31: BL33 decompress pass
459 03:54:36.440372 ERROR: Error initializing runtime service opteed_fast
460 03:54:37.657232 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
461 03:54:37.657930 bl2_stage_init 0x01
462 03:54:37.658413 bl2_stage_init 0x81
463 03:54:37.662902 hw id: 0x0000 - pwm id 0x01
464 03:54:37.663425 bl2_stage_init 0xc1
465 03:54:37.668405 bl2_stage_init 0x02
466 03:54:37.668947
467 03:54:37.669396 L0:00000000
468 03:54:37.669828 L1:00000703
469 03:54:37.670260 L2:00008067
470 03:54:37.670687 L3:15000000
471 03:54:37.674010 S1:00000000
472 03:54:37.674485 B2:20282000
473 03:54:37.674916 B1:a0f83180
474 03:54:37.675339
475 03:54:37.675766 TE: 70594
476 03:54:37.676254
477 03:54:37.679591 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
478 03:54:37.680088
479 03:54:37.685181 Board ID = 1
480 03:54:37.685636 Set cpu clk to 24M
481 03:54:37.686067 Set clk81 to 24M
482 03:54:37.690869 Use GP1_pll as DSU clk.
483 03:54:37.691329 DSU clk: 1200 Mhz
484 03:54:37.691758 CPU clk: 1200 MHz
485 03:54:37.696360 Set clk81 to 166.6M
486 03:54:37.702006 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
487 03:54:37.702473 board id: 1
488 03:54:37.709147 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
489 03:54:37.719922 fw parse done
490 03:54:37.725867 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
491 03:54:37.768555 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
492 03:54:37.779455 PIEI prepare done
493 03:54:37.780043 fastboot data load
494 03:54:37.780492 fastboot data verify
495 03:54:37.784995 verify result: 266
496 03:54:37.790598 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
497 03:54:37.791067 LPDDR4 probe
498 03:54:37.791498 ddr clk to 1584MHz
499 03:54:39.156454 Load ddrfw from SPI, src: 0x0001 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
500 03:54:39.156868 bl2_stage_init 0x01
501 03:54:39.157086 bl2_stage_init 0x81
502 03:54:39.162041 hw id: 0x0000 - pwm id 0x01
503 03:54:39.162335 bl2_stage_init 0xc1
504 03:54:39.167574 bl2_stage_init 0x02
505 03:54:39.167959
506 03:54:39.168230 L0:00000000
507 03:54:39.168435 L1:00000703
508 03:54:39.168646 L2:00008067
509 03:54:39.168848 L3:15000000
510 03:54:39.173215 S1:00000000
511 03:54:39.173499 B2:20282000
512 03:54:39.173710 B1:a0f83180
513 03:54:39.173910
514 03:54:39.174124 TE: 71455
515 03:54:39.174327
516 03:54:39.178784 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
517 03:54:39.179070
518 03:54:39.184378 Board ID = 1
519 03:54:39.184665 Set cpu clk to 24M
520 03:54:39.184877 Set clk81 to 24M
521 03:54:39.190048 Use GP1_pll as DSU clk.
522 03:54:39.190330 DSU clk: 1200 Mhz
523 03:54:39.190534 CPU clk: 1200 MHz
524 03:54:39.195565 Set clk81 to 166.6M
525 03:54:39.201202 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
526 03:54:39.201486 board id: 1
527 03:54:39.208402 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
528 03:54:39.219096 fw parse done
529 03:54:39.225011 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
530 03:54:39.267642 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
531 03:54:39.278629 PIEI prepare done
532 03:54:39.278936 fastboot data load
533 03:54:39.279156 fastboot data verify
534 03:54:39.284220 verify result: 266
535 03:54:39.289785 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
536 03:54:39.290068 LPDDR4 probe
537 03:54:39.290277 ddr clk to 1584MHz
538 03:54:39.297774 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 03:54:39.335115
540 03:54:39.335622 dmc_version 0001
541 03:54:39.342020 Check phy result
542 03:54:39.347744 INFO : End of CA training
543 03:54:39.348387 INFO : End of initialization
544 03:54:39.353293 INFO : Training has run successfully!
545 03:54:39.353897 Check phy result
546 03:54:39.358846 INFO : End of initialization
547 03:54:39.359457 INFO : End of read enable training
548 03:54:39.364478 INFO : End of fine write leveling
549 03:54:39.370079 INFO : End of Write leveling coarse delay
550 03:54:39.370709 INFO : Training has run successfully!
551 03:54:39.371280 Check phy result
552 03:54:39.375649 INFO : End of initialization
553 03:54:39.376361 INFO : End of read dq deskew training
554 03:54:39.381210 INFO : End of MPR read delay center optimization
555 03:54:39.386813 INFO : End of write delay center optimization
556 03:54:39.392447 INFO : End of read delay center optimization
557 03:54:39.393061 INFO : End of max read latency training
558 03:54:39.397993 INFO : Training has run successfully!
559 03:54:39.398575 1D training succeed
560 03:54:39.407209 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
561 03:54:39.454801 Check phy result
562 03:54:39.455172 INFO : End of initialization
563 03:54:39.477370 INFO : End of 2D read delay Voltage center optimization
564 03:54:39.496445 INFO : End of 2D read delay Voltage center optimization
565 03:54:39.548270 INFO : End of 2D write delay Voltage center optimization
566 03:54:39.597405 INFO : End of 2D write delay Voltage center optimization
567 03:54:39.602968 INFO : Training has run successfully!
568 03:54:39.603483
569 03:54:39.603914 channel==0
570 03:54:39.608609 RxClkDly_Margin_A0==69 ps 7
571 03:54:39.609136 TxDqDly_Margin_A0==98 ps 10
572 03:54:39.614301 RxClkDly_Margin_A1==78 ps 8
573 03:54:39.614799 TxDqDly_Margin_A1==88 ps 9
574 03:54:39.615224 TrainedVREFDQ_A0==74
575 03:54:39.619780 TrainedVREFDQ_A1==74
576 03:54:39.620309 VrefDac_Margin_A0==23
577 03:54:39.620732 DeviceVref_Margin_A0==40
578 03:54:39.625391 VrefDac_Margin_A1==22
579 03:54:39.625894 DeviceVref_Margin_A1==40
580 03:54:39.626322
581 03:54:39.626745
582 03:54:39.627155 channel==1
583 03:54:39.630994 RxClkDly_Margin_A0==88 ps 9
584 03:54:39.631490 TxDqDly_Margin_A0==98 ps 10
585 03:54:39.636589 RxClkDly_Margin_A1==88 ps 9
586 03:54:39.637085 TxDqDly_Margin_A1==88 ps 9
587 03:54:39.642276 TrainedVREFDQ_A0==78
588 03:54:39.642779 TrainedVREFDQ_A1==77
589 03:54:39.643205 VrefDac_Margin_A0==22
590 03:54:39.647794 DeviceVref_Margin_A0==36
591 03:54:39.648320 VrefDac_Margin_A1==22
592 03:54:39.653404 DeviceVref_Margin_A1==37
593 03:54:39.653908
594 03:54:39.654330 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
595 03:54:39.654743
596 03:54:39.686935 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000060
597 03:54:39.687486 2D training succeed
598 03:54:39.692599 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
599 03:54:39.698289 auto size-- 65535DDR cs0 size: 2048MB
600 03:54:39.698804 DDR cs1 size: 2048MB
601 03:54:39.703783 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
602 03:54:39.704331 cs0 DataBus test pass
603 03:54:39.709399 cs1 DataBus test pass
604 03:54:39.709916 cs0 AddrBus test pass
605 03:54:39.710337 cs1 AddrBus test pass
606 03:54:39.710741
607 03:54:39.714986 100bdlr_step_size ps== 478
608 03:54:39.715499 result report
609 03:54:39.720583 boot times 0Enable ddr reg access
610 03:54:39.725808 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
611 03:54:39.739569 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
612 03:54:40.395007 bl2z: ptr: 05129330, size: 00001e40
613 03:54:40.402144 0.0;M3 CHK:0;cm4_sp_mode 0
614 03:54:40.402682 MVN_1=0x00000000
615 03:54:40.403111 MVN_2=0x00000000
616 03:54:40.413697 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
617 03:54:40.414213 OPS=0x04
618 03:54:40.414641 ring efuse init
619 03:54:40.419483 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
620 03:54:40.419974 [0.017310 Inits done]
621 03:54:40.420435 secure task start!
622 03:54:40.426860 high task start!
623 03:54:40.427337 low task start!
624 03:54:40.427752 run into bl31
625 03:54:40.435432 NOTICE: BL31: v1.3(release):4fc40b1
626 03:54:40.443304 NOTICE: BL31: Built : 15:57:33, May 22 2019
627 03:54:40.443780 NOTICE: BL31: G12A normal boot!
628 03:54:40.458722 NOTICE: BL31: BL33 decompress pass
629 03:54:40.464515 ERROR: Error initializing runtime service opteed_fast
630 03:54:41.707048 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
631 03:54:41.707654 bl2_stage_init 0x01
632 03:54:41.708135 bl2_stage_init 0x81
633 03:54:41.712605 hw id: 0x0000 - pwm id 0x01
634 03:54:41.713071 bl2_stage_init 0xc1
635 03:54:41.716608 bl2_stage_init 0x02
636 03:54:41.717072
637 03:54:41.717500 L0:00000000
638 03:54:41.717909 L1:00000703
639 03:54:41.722169 L2:00008067
640 03:54:41.722623 L3:15000000
641 03:54:41.723040 S1:00000000
642 03:54:41.723444 B2:20282000
643 03:54:41.723843 B1:a0f83180
644 03:54:41.724298
645 03:54:41.727680 TE: 71673
646 03:54:41.728160
647 03:54:41.733357 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
648 03:54:41.733815
649 03:54:41.734225 Board ID = 1
650 03:54:41.734627 Set cpu clk to 24M
651 03:54:41.738839 Set clk81 to 24M
652 03:54:41.739299 Use GP1_pll as DSU clk.
653 03:54:41.739719 DSU clk: 1200 Mhz
654 03:54:41.744551 CPU clk: 1200 MHz
655 03:54:41.745007 Set clk81 to 166.6M
656 03:54:41.750070 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
657 03:54:41.750525 board id: 1
658 03:54:41.759016 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
659 03:54:41.769645 fw parse done
660 03:54:41.775628 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
661 03:54:41.818290 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
662 03:54:41.829165 PIEI prepare done
663 03:54:41.829635 fastboot data load
664 03:54:41.830058 fastboot data verify
665 03:54:41.834760 verify result: 266
666 03:54:41.840358 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
667 03:54:41.840832 LPDDR4 probe
668 03:54:41.841249 ddr clk to 1584MHz
669 03:54:41.848332 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
670 03:54:41.885699
671 03:54:41.886195 dmc_version 0001
672 03:54:41.892303 Check phy result
673 03:54:41.898202 INFO : End of CA training
674 03:54:41.898671 INFO : End of initialization
675 03:54:41.903793 INFO : Training has run successfully!
676 03:54:41.904306 Check phy result
677 03:54:41.909460 INFO : End of initialization
678 03:54:41.909928 INFO : End of read enable training
679 03:54:41.912717 INFO : End of fine write leveling
680 03:54:41.918243 INFO : End of Write leveling coarse delay
681 03:54:41.923888 INFO : Training has run successfully!
682 03:54:41.924395 Check phy result
683 03:54:41.924813 INFO : End of initialization
684 03:54:41.929480 INFO : End of read dq deskew training
685 03:54:41.935060 INFO : End of MPR read delay center optimization
686 03:54:41.935535 INFO : End of write delay center optimization
687 03:54:41.940672 INFO : End of read delay center optimization
688 03:54:41.946325 INFO : End of max read latency training
689 03:54:41.946798 INFO : Training has run successfully!
690 03:54:41.951896 1D training succeed
691 03:54:41.957859 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
692 03:54:42.005394 Check phy result
693 03:54:42.005869 INFO : End of initialization
694 03:54:42.027789 INFO : End of 2D read delay Voltage center optimization
695 03:54:42.046959 INFO : End of 2D read delay Voltage center optimization
696 03:54:42.098828 INFO : End of 2D write delay Voltage center optimization
697 03:54:42.148085 INFO : End of 2D write delay Voltage center optimization
698 03:54:42.153694 INFO : Training has run successfully!
699 03:54:42.154167
700 03:54:42.154581 channel==0
701 03:54:42.159201 RxClkDly_Margin_A0==78 ps 8
702 03:54:42.159684 TxDqDly_Margin_A0==98 ps 10
703 03:54:42.164775 RxClkDly_Margin_A1==69 ps 7
704 03:54:42.165249 TxDqDly_Margin_A1==88 ps 9
705 03:54:42.165665 TrainedVREFDQ_A0==74
706 03:54:42.170345 TrainedVREFDQ_A1==74
707 03:54:42.170816 VrefDac_Margin_A0==24
708 03:54:42.171230 DeviceVref_Margin_A0==40
709 03:54:42.176066 VrefDac_Margin_A1==23
710 03:54:42.176544 DeviceVref_Margin_A1==40
711 03:54:42.176956
712 03:54:42.177360
713 03:54:42.177759 channel==1
714 03:54:42.181703 RxClkDly_Margin_A0==78 ps 8
715 03:54:42.182171 TxDqDly_Margin_A0==98 ps 10
716 03:54:42.187219 RxClkDly_Margin_A1==78 ps 8
717 03:54:42.187689 TxDqDly_Margin_A1==88 ps 9
718 03:54:42.192898 TrainedVREFDQ_A0==78
719 03:54:42.193378 TrainedVREFDQ_A1==75
720 03:54:42.193794 VrefDac_Margin_A0==22
721 03:54:42.198435 DeviceVref_Margin_A0==36
722 03:54:42.198906 VrefDac_Margin_A1==22
723 03:54:42.204067 DeviceVref_Margin_A1==38
724 03:54:42.204539
725 03:54:42.204954 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
726 03:54:42.205361
727 03:54:42.237546 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000016 dram_vref_reg_value 0x 00000061
728 03:54:42.238052 2D training succeed
729 03:54:42.243104 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
730 03:54:42.248690 auto size-- 65535DDR cs0 size: 2048MB
731 03:54:42.249162 DDR cs1 size: 2048MB
732 03:54:42.254283 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
733 03:54:42.254755 cs0 DataBus test pass
734 03:54:42.259861 cs1 DataBus test pass
735 03:54:42.260369 cs0 AddrBus test pass
736 03:54:42.260789 cs1 AddrBus test pass
737 03:54:42.261192
738 03:54:42.265583 100bdlr_step_size ps== 478
739 03:54:42.266064 result report
740 03:54:42.271075 boot times 0Enable ddr reg access
741 03:54:42.276278 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
742 03:54:42.290049 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
743 03:54:42.945045 bl2z: ptr: 05129330, size: 00001e40
744 03:54:42.951072 0.0;M3 CHK:0;cm4_sp_mode 0
745 03:54:42.951588 MVN_1=0x00000000
746 03:54:42.952027 MVN_2=0x00000000
747 03:54:42.962635 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
748 03:54:42.963158 OPS=0x04
749 03:54:42.963556 ring efuse init
750 03:54:42.968154 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
751 03:54:42.968610 [0.017319 Inits done]
752 03:54:42.968999 secure task start!
753 03:54:42.976170 high task start!
754 03:54:42.976605 low task start!
755 03:54:42.976990 run into bl31
756 03:54:42.984787 NOTICE: BL31: v1.3(release):4fc40b1
757 03:54:42.992664 NOTICE: BL31: Built : 15:57:33, May 22 2019
758 03:54:42.993109 NOTICE: BL31: G12A normal boot!
759 03:54:43.008048 NOTICE: BL31: BL33 decompress pass
760 03:54:43.013726 ERROR: Error initializing runtime service opteed_fast
761 03:54:43.809243
762 03:54:43.809866
763 03:54:43.814611 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
764 03:54:43.815141
765 03:54:43.818106 Model: Libre Computer AML-S905D3-CC Solitude
766 03:54:43.965231 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
767 03:54:43.980547 DRAM: 2 GiB (effective 3.8 GiB)
768 03:54:44.081527 Core: 406 devices, 33 uclasses, devicetree: separate
769 03:54:44.087372 WDT: Not starting watchdog@f0d0
770 03:54:44.112523 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
771 03:54:44.124820 Loading Environment from FAT... Card did not respond to voltage select! : -110
772 03:54:44.129636 ** Bad device specification mmc 0 **
773 03:54:44.139748 Card did not respond to voltage select! : -110
774 03:54:44.147328 ** Bad device specification mmc 0 **
775 03:54:44.147844 Couldn't find partition mmc 0
776 03:54:44.155814 Card did not respond to voltage select! : -110
777 03:54:44.161347 ** Bad device specification mmc 0 **
778 03:54:44.161915 Couldn't find partition mmc 0
779 03:54:44.166284 Error: could not access storage.
780 03:54:44.462627 Net: eth0: ethernet@ff3f0000
781 03:54:44.463188 starting USB...
782 03:54:44.707397 Bus usb@ff500000: Register 3000140 NbrPorts 3
783 03:54:44.708062 Starting the controller
784 03:54:44.714254 USB XHCI 1.10
785 03:54:46.268468 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
786 03:54:46.276736 scanning usb for storage devices... 0 Storage Device(s) found
788 03:54:46.328197 Hit any key to stop autoboot: 1
789 03:54:46.328983 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
790 03:54:46.329572 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
791 03:54:46.330051 Setting prompt string to ['=>']
792 03:54:46.330537 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
793 03:54:46.342767 0
794 03:54:46.343623 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
796 03:54:46.444871 => setenv autoload no
797 03:54:46.445594 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
798 03:54:46.450376 setenv autoload no
800 03:54:46.551817 => setenv initrd_high 0xffffffff
801 03:54:46.552558 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
802 03:54:46.556880 setenv initrd_high 0xffffffff
804 03:54:46.658354 => setenv fdt_high 0xffffffff
805 03:54:46.659074 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
806 03:54:46.663329 setenv fdt_high 0xffffffff
808 03:54:46.764782 => dhcp
809 03:54:46.765403 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
810 03:54:46.769371 dhcp
811 03:54:47.675483 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
812 03:54:47.676115 Speed: 1000, full duplex
813 03:54:47.676546 BOOTP broadcast 1
814 03:54:47.684521 DHCP client bound to address 192.168.6.21 (9 ms)
816 03:54:47.785899 => setenv serverip 192.168.6.2
817 03:54:47.786516 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
818 03:54:47.790996 setenv serverip 192.168.6.2
820 03:54:47.892404 => tftpboot 0x01080000 957111/tftp-deploy-mwcsjtbd/kernel/uImage
821 03:54:47.893040 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
822 03:54:47.899694 tftpboot 0x01080000 957111/tftp-deploy-mwcsjtbd/kernel/uImage
823 03:54:47.900190 Speed: 1000, full duplex
824 03:54:47.900607 Using ethernet@ff3f0000 device
825 03:54:47.905223 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
826 03:54:47.910768 Filename '957111/tftp-deploy-mwcsjtbd/kernel/uImage'.
827 03:54:47.914611 Load address: 0x1080000
828 03:54:50.905764 Loading: *################################################## 43.6 MiB
829 03:54:50.906447 14.6 MiB/s
830 03:54:50.906933 done
831 03:54:50.910109 Bytes transferred = 45713984 (2b98a40 hex)
833 03:54:51.011803 => tftpboot 0x08000000 957111/tftp-deploy-mwcsjtbd/ramdisk/ramdisk.cpio.gz.uboot
834 03:54:51.012673 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
835 03:54:51.019418 tftpboot 0x08000000 957111/tftp-deploy-mwcsjtbd/ramdisk/ramdisk.cpio.gz.uboot
836 03:54:51.019936 Speed: 1000, full duplex
837 03:54:51.020414 Using ethernet@ff3f0000 device
838 03:54:51.025022 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
839 03:54:51.034790 Filename '957111/tftp-deploy-mwcsjtbd/ramdisk/ramdisk.cpio.gz.uboot'.
840 03:54:51.035379 Load address: 0x8000000
841 03:54:52.453808 Loading: *################################################# UDP wrong checksum 00000005 0000d423
842 03:54:57.455328 T UDP wrong checksum 00000005 0000d423
843 03:55:06.921650 T UDP wrong checksum 000000ff 00009078
844 03:55:07.012242 UDP wrong checksum 000000ff 00002b6b
845 03:55:07.457308 T UDP wrong checksum 00000005 0000d423
846 03:55:19.483234 T T UDP wrong checksum 000000ff 0000a0da
847 03:55:19.533643 UDP wrong checksum 000000ff 00002bcd
848 03:55:27.460604 T UDP wrong checksum 00000005 0000d423
849 03:55:47.466080 T T T T
850 03:55:47.466755 Retry count exceeded; starting again
852 03:55:47.468372 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
855 03:55:47.470427 end: 2.4 uboot-commands (duration 00:01:20) [common]
857 03:55:47.471959 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
859 03:55:47.473175 end: 2 uboot-action (duration 00:01:20) [common]
861 03:55:47.474839 Cleaning after the job
862 03:55:47.475437 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/ramdisk
863 03:55:47.476884 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/kernel
864 03:55:47.527770 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/dtb
865 03:55:47.528781 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/nfsrootfs
866 03:55:47.881285 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957111/tftp-deploy-mwcsjtbd/modules
867 03:55:47.906155 start: 4.1 power-off (timeout 00:00:30) [common]
868 03:55:47.906963 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
869 03:55:47.941275 >> OK - accepted request
870 03:55:47.943449 Returned 0 in 0 seconds
871 03:55:48.044402 end: 4.1 power-off (duration 00:00:00) [common]
873 03:55:48.045432 start: 4.2 read-feedback (timeout 00:10:00) [common]
874 03:55:48.046105 Listened to connection for namespace 'common' for up to 1s
875 03:55:49.047040 Finalising connection for namespace 'common'
876 03:55:49.047535 Disconnecting from shell: Finalise
877 03:55:49.047835 =>
878 03:55:49.148604 end: 4.2 read-feedback (duration 00:00:01) [common]
879 03:55:49.149038 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/957111
880 03:55:51.870813 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/957111
881 03:55:51.871439 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.