Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:45:02.725813 lava-dispatcher, installed at version: 2024.01
2 20:45:02.726693 start: 0 validate
3 20:45:02.727186 Start time: 2024-11-08 20:45:02.727154+00:00 (UTC)
4 20:45:02.727826 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:45:02.728487 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 20:45:02.769520 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:45:02.770127 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-225-g50643bbc9eb6%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 20:45:02.805919 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:45:02.806584 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-225-g50643bbc9eb6%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 20:45:02.838770 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:45:02.839585 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-225-g50643bbc9eb6%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
12 20:45:02.882886 validate duration: 0.16
14 20:45:02.883797 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:45:02.884146 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:45:02.884476 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:45:02.885130 Not decompressing ramdisk as can be used compressed.
18 20:45:02.885609 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 20:45:02.885880 saving as /var/lib/lava/dispatcher/tmp/962349/tftp-deploy-dqplgg23/ramdisk/rootfs.cpio.gz
20 20:45:02.886149 total size: 47897469 (45 MB)
21 20:45:02.920412 progress 0 % (0 MB)
22 20:45:02.955888 progress 5 % (2 MB)
23 20:45:02.990473 progress 10 % (4 MB)
24 20:45:03.022244 progress 15 % (6 MB)
25 20:45:03.052750 progress 20 % (9 MB)
26 20:45:03.083050 progress 25 % (11 MB)
27 20:45:03.112843 progress 30 % (13 MB)
28 20:45:03.144373 progress 35 % (16 MB)
29 20:45:03.174300 progress 40 % (18 MB)
30 20:45:03.204133 progress 45 % (20 MB)
31 20:45:03.233911 progress 50 % (22 MB)
32 20:45:03.264150 progress 55 % (25 MB)
33 20:45:03.294593 progress 60 % (27 MB)
34 20:45:03.324252 progress 65 % (29 MB)
35 20:45:03.353427 progress 70 % (32 MB)
36 20:45:03.382905 progress 75 % (34 MB)
37 20:45:03.412107 progress 80 % (36 MB)
38 20:45:03.441729 progress 85 % (38 MB)
39 20:45:03.470988 progress 90 % (41 MB)
40 20:45:03.500488 progress 95 % (43 MB)
41 20:45:03.529266 progress 100 % (45 MB)
42 20:45:03.530033 45 MB downloaded in 0.64 s (70.94 MB/s)
43 20:45:03.530579 end: 1.1.1 http-download (duration 00:00:01) [common]
45 20:45:03.531462 end: 1.1 download-retry (duration 00:00:01) [common]
46 20:45:03.531750 start: 1.2 download-retry (timeout 00:09:59) [common]
47 20:45:03.532041 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 20:45:03.532555 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-225-g50643bbc9eb6/arm64/defconfig/clang-16/kernel/Image
49 20:45:03.532809 saving as /var/lib/lava/dispatcher/tmp/962349/tftp-deploy-dqplgg23/kernel/Image
50 20:45:03.533020 total size: 37812736 (36 MB)
51 20:45:03.533234 No compression specified
52 20:45:03.579176 progress 0 % (0 MB)
53 20:45:03.603115 progress 5 % (1 MB)
54 20:45:03.627218 progress 10 % (3 MB)
55 20:45:03.651155 progress 15 % (5 MB)
56 20:45:03.674468 progress 20 % (7 MB)
57 20:45:03.698225 progress 25 % (9 MB)
58 20:45:03.721900 progress 30 % (10 MB)
59 20:45:03.745058 progress 35 % (12 MB)
60 20:45:03.768513 progress 40 % (14 MB)
61 20:45:03.792271 progress 45 % (16 MB)
62 20:45:03.815618 progress 50 % (18 MB)
63 20:45:03.838921 progress 55 % (19 MB)
64 20:45:03.862909 progress 60 % (21 MB)
65 20:45:03.886427 progress 65 % (23 MB)
66 20:45:03.909406 progress 70 % (25 MB)
67 20:45:03.933364 progress 75 % (27 MB)
68 20:45:03.956898 progress 80 % (28 MB)
69 20:45:03.979839 progress 85 % (30 MB)
70 20:45:04.003773 progress 90 % (32 MB)
71 20:45:04.027417 progress 95 % (34 MB)
72 20:45:04.050591 progress 100 % (36 MB)
73 20:45:04.051360 36 MB downloaded in 0.52 s (69.57 MB/s)
74 20:45:04.051840 end: 1.2.1 http-download (duration 00:00:01) [common]
76 20:45:04.052703 end: 1.2 download-retry (duration 00:00:01) [common]
77 20:45:04.052978 start: 1.3 download-retry (timeout 00:09:59) [common]
78 20:45:04.053243 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 20:45:04.053719 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-225-g50643bbc9eb6/arm64/defconfig/clang-16/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 20:45:04.053991 saving as /var/lib/lava/dispatcher/tmp/962349/tftp-deploy-dqplgg23/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 20:45:04.054200 total size: 53209 (0 MB)
82 20:45:04.054409 No compression specified
83 20:45:04.094866 progress 61 % (0 MB)
84 20:45:04.095701 progress 100 % (0 MB)
85 20:45:04.096255 0 MB downloaded in 0.04 s (1.21 MB/s)
86 20:45:04.096718 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:45:04.097521 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:45:04.097778 start: 1.4 download-retry (timeout 00:09:59) [common]
90 20:45:04.098038 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 20:45:04.098489 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-225-g50643bbc9eb6/arm64/defconfig/clang-16/modules.tar.xz
92 20:45:04.098729 saving as /var/lib/lava/dispatcher/tmp/962349/tftp-deploy-dqplgg23/modules/modules.tar
93 20:45:04.098933 total size: 11766788 (11 MB)
94 20:45:04.099144 Using unxz to decompress xz
95 20:45:04.134307 progress 0 % (0 MB)
96 20:45:04.202635 progress 5 % (0 MB)
97 20:45:04.279382 progress 10 % (1 MB)
98 20:45:04.378734 progress 15 % (1 MB)
99 20:45:04.475308 progress 20 % (2 MB)
100 20:45:04.555213 progress 25 % (2 MB)
101 20:45:04.633217 progress 30 % (3 MB)
102 20:45:04.714121 progress 35 % (3 MB)
103 20:45:04.794172 progress 40 % (4 MB)
104 20:45:04.870355 progress 45 % (5 MB)
105 20:45:04.955880 progress 50 % (5 MB)
106 20:45:05.038258 progress 55 % (6 MB)
107 20:45:05.123705 progress 60 % (6 MB)
108 20:45:05.206689 progress 65 % (7 MB)
109 20:45:05.289009 progress 70 % (7 MB)
110 20:45:05.372795 progress 75 % (8 MB)
111 20:45:05.457489 progress 80 % (9 MB)
112 20:45:05.545914 progress 85 % (9 MB)
113 20:45:05.634024 progress 90 % (10 MB)
114 20:45:05.714596 progress 95 % (10 MB)
115 20:45:05.795283 progress 100 % (11 MB)
116 20:45:05.806557 11 MB downloaded in 1.71 s (6.57 MB/s)
117 20:45:05.807110 end: 1.4.1 http-download (duration 00:00:02) [common]
119 20:45:05.807933 end: 1.4 download-retry (duration 00:00:02) [common]
120 20:45:05.808486 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 20:45:05.809058 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 20:45:05.809602 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:45:05.810154 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 20:45:05.811207 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j
125 20:45:05.812276 makedir: /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin
126 20:45:05.813004 makedir: /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/tests
127 20:45:05.813669 makedir: /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/results
128 20:45:05.814327 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-add-keys
129 20:45:05.815311 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-add-sources
130 20:45:05.816335 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-background-process-start
131 20:45:05.817344 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-background-process-stop
132 20:45:05.818380 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-common-functions
133 20:45:05.819342 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-echo-ipv4
134 20:45:05.820345 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-install-packages
135 20:45:05.821311 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-installed-packages
136 20:45:05.822253 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-os-build
137 20:45:05.823203 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-probe-channel
138 20:45:05.824172 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-probe-ip
139 20:45:05.825126 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-target-ip
140 20:45:05.826074 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-target-mac
141 20:45:05.827004 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-target-storage
142 20:45:05.828071 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-test-case
143 20:45:05.829062 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-test-event
144 20:45:05.830012 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-test-feedback
145 20:45:05.830961 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-test-raise
146 20:45:05.831902 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-test-reference
147 20:45:05.832926 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-test-runner
148 20:45:05.833877 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-test-set
149 20:45:05.834880 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-test-shell
150 20:45:05.835883 Updating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-install-packages (oe)
151 20:45:05.837018 Updating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/bin/lava-installed-packages (oe)
152 20:45:05.837951 Creating /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/environment
153 20:45:05.838760 LAVA metadata
154 20:45:05.839298 - LAVA_JOB_ID=962349
155 20:45:05.839788 - LAVA_DISPATCHER_IP=192.168.6.2
156 20:45:05.840599 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 20:45:05.842571 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 20:45:05.843217 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 20:45:05.843671 skipped lava-vland-overlay
160 20:45:05.844255 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 20:45:05.844774 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 20:45:05.845199 skipped lava-multinode-overlay
163 20:45:05.845679 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 20:45:05.846175 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 20:45:05.846644 Loading test definitions
166 20:45:05.847181 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 20:45:05.847616 Using /lava-962349 at stage 0
168 20:45:05.849719 uuid=962349_1.5.2.4.1 testdef=None
169 20:45:05.850279 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 20:45:05.850787 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 20:45:05.853106 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 20:45:05.853910 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 20:45:05.856035 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 20:45:05.856862 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 20:45:05.858915 runner path: /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/0/tests/0_igt-gpu-panfrost test_uuid 962349_1.5.2.4.1
178 20:45:05.859475 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 20:45:05.860312 Creating lava-test-runner.conf files
181 20:45:05.860524 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/962349/lava-overlay-0bdw723j/lava-962349/0 for stage 0
182 20:45:05.860855 - 0_igt-gpu-panfrost
183 20:45:05.861198 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 20:45:05.861472 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 20:45:05.884548 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 20:45:05.884931 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 20:45:05.885199 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 20:45:05.885466 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 20:45:05.885730 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 20:45:12.900600 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 20:45:12.901042 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 20:45:12.901288 extracting modules file /var/lib/lava/dispatcher/tmp/962349/tftp-deploy-dqplgg23/modules/modules.tar to /var/lib/lava/dispatcher/tmp/962349/extract-overlay-ramdisk-0d82sybb/ramdisk
193 20:45:14.332839 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 20:45:14.333289 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 20:45:14.333564 [common] Applying overlay /var/lib/lava/dispatcher/tmp/962349/compress-overlay-9rxnud8i/overlay-1.5.2.5.tar.gz to ramdisk
196 20:45:14.333777 [common] Applying overlay /var/lib/lava/dispatcher/tmp/962349/compress-overlay-9rxnud8i/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/962349/extract-overlay-ramdisk-0d82sybb/ramdisk
197 20:45:14.363489 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 20:45:14.363857 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 20:45:14.364169 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 20:45:14.364401 Converting downloaded kernel to a uImage
201 20:45:14.364702 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/962349/tftp-deploy-dqplgg23/kernel/Image /var/lib/lava/dispatcher/tmp/962349/tftp-deploy-dqplgg23/kernel/uImage
202 20:45:14.744061 output: Image Name:
203 20:45:14.744464 output: Created: Fri Nov 8 20:45:14 2024
204 20:45:14.744676 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 20:45:14.744883 output: Data Size: 37812736 Bytes = 36926.50 KiB = 36.06 MiB
206 20:45:14.745086 output: Load Address: 01080000
207 20:45:14.745288 output: Entry Point: 01080000
208 20:45:14.745486 output:
209 20:45:14.745811 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 20:45:14.746073 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 20:45:14.746337 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 20:45:14.746586 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 20:45:14.746841 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 20:45:14.747092 Building ramdisk /var/lib/lava/dispatcher/tmp/962349/extract-overlay-ramdisk-0d82sybb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/962349/extract-overlay-ramdisk-0d82sybb/ramdisk
215 20:45:21.519910 >> 509031 blocks
216 20:45:42.295867 Adding RAMdisk u-boot header.
217 20:45:42.296396 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/962349/extract-overlay-ramdisk-0d82sybb/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/962349/extract-overlay-ramdisk-0d82sybb/ramdisk.cpio.gz.uboot
218 20:45:43.003277 output: Image Name:
219 20:45:43.003685 output: Created: Fri Nov 8 20:45:42 2024
220 20:45:43.003896 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 20:45:43.004263 output: Data Size: 66431629 Bytes = 64874.64 KiB = 63.35 MiB
222 20:45:43.004672 output: Load Address: 00000000
223 20:45:43.005070 output: Entry Point: 00000000
224 20:45:43.005463 output:
225 20:45:43.006437 rename /var/lib/lava/dispatcher/tmp/962349/extract-overlay-ramdisk-0d82sybb/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/962349/tftp-deploy-dqplgg23/ramdisk/ramdisk.cpio.gz.uboot
226 20:45:43.007146 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 20:45:43.007685 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 20:45:43.008259 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 20:45:43.008727 No LXC device requested
230 20:45:43.009225 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 20:45:43.009729 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 20:45:43.010217 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 20:45:43.010639 Checking files for TFTP limit of 4294967296 bytes.
234 20:45:43.013320 end: 1 tftp-deploy (duration 00:00:40) [common]
235 20:45:43.013914 start: 2 uboot-action (timeout 00:05:00) [common]
236 20:45:43.014433 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 20:45:43.014931 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 20:45:43.015430 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 20:45:43.015961 Using kernel file from prepare-kernel: 962349/tftp-deploy-dqplgg23/kernel/uImage
240 20:45:43.016605 substitutions:
241 20:45:43.017014 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 20:45:43.017414 - {DTB_ADDR}: 0x01070000
243 20:45:43.017812 - {DTB}: 962349/tftp-deploy-dqplgg23/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 20:45:43.018212 - {INITRD}: 962349/tftp-deploy-dqplgg23/ramdisk/ramdisk.cpio.gz.uboot
245 20:45:43.018608 - {KERNEL_ADDR}: 0x01080000
246 20:45:43.019003 - {KERNEL}: 962349/tftp-deploy-dqplgg23/kernel/uImage
247 20:45:43.019397 - {LAVA_MAC}: None
248 20:45:43.019831 - {PRESEED_CONFIG}: None
249 20:45:43.020264 - {PRESEED_LOCAL}: None
250 20:45:43.020658 - {RAMDISK_ADDR}: 0x08000000
251 20:45:43.021048 - {RAMDISK}: 962349/tftp-deploy-dqplgg23/ramdisk/ramdisk.cpio.gz.uboot
252 20:45:43.021441 - {ROOT_PART}: None
253 20:45:43.021830 - {ROOT}: None
254 20:45:43.022226 - {SERVER_IP}: 192.168.6.2
255 20:45:43.022619 - {TEE_ADDR}: 0x83000000
256 20:45:43.023010 - {TEE}: None
257 20:45:43.023397 Parsed boot commands:
258 20:45:43.023774 - setenv autoload no
259 20:45:43.024190 - setenv initrd_high 0xffffffff
260 20:45:43.024582 - setenv fdt_high 0xffffffff
261 20:45:43.024969 - dhcp
262 20:45:43.025356 - setenv serverip 192.168.6.2
263 20:45:43.025743 - tftpboot 0x01080000 962349/tftp-deploy-dqplgg23/kernel/uImage
264 20:45:43.026132 - tftpboot 0x08000000 962349/tftp-deploy-dqplgg23/ramdisk/ramdisk.cpio.gz.uboot
265 20:45:43.026523 - tftpboot 0x01070000 962349/tftp-deploy-dqplgg23/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 20:45:43.026912 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 20:45:43.027310 - bootm 0x01080000 0x08000000 0x01070000
268 20:45:43.027815 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 20:45:43.029381 start: 2.3 connect-device (timeout 00:05:00) [common]
271 20:45:43.029822 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 20:45:43.045416 Setting prompt string to ['lava-test: # ']
273 20:45:43.046929 end: 2.3 connect-device (duration 00:00:00) [common]
274 20:45:43.047523 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 20:45:43.048116 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 20:45:43.048655 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 20:45:43.049793 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 20:45:43.089043 >> OK - accepted request
279 20:45:43.091105 Returned 0 in 0 seconds
280 20:45:43.192111 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 20:45:43.193963 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 20:45:43.194590 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 20:45:43.195169 Setting prompt string to ['Hit any key to stop autoboot']
285 20:45:43.195675 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 20:45:43.197500 Trying 192.168.56.21...
287 20:45:43.198042 Connected to conserv1.
288 20:45:43.198504 Escape character is '^]'.
289 20:45:43.198961
290 20:45:43.199434 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 20:45:43.199906
292 20:45:50.807281 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 20:45:50.807672 bl2_stage_init 0x01
294 20:45:50.807908 bl2_stage_init 0x81
295 20:45:50.812764 hw id: 0x0000 - pwm id 0x01
296 20:45:50.813031 bl2_stage_init 0xc1
297 20:45:50.818227 bl2_stage_init 0x02
298 20:45:50.818473
299 20:45:50.818686 L0:00000000
300 20:45:50.818894 L1:00000703
301 20:45:50.819098 L2:00008067
302 20:45:50.819300 L3:15000000
303 20:45:50.823947 S1:00000000
304 20:45:50.824222 B2:20282000
305 20:45:50.824434 B1:a0f83180
306 20:45:50.824639
307 20:45:50.824844 TE: 67898
308 20:45:50.825050
309 20:45:50.829477 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 20:45:50.829767
311 20:45:50.835077 Board ID = 1
312 20:45:50.835356 Set cpu clk to 24M
313 20:45:50.835586 Set clk81 to 24M
314 20:45:50.838462 Use GP1_pll as DSU clk.
315 20:45:50.838731 DSU clk: 1200 Mhz
316 20:45:50.844045 CPU clk: 1200 MHz
317 20:45:50.844320 Set clk81 to 166.6M
318 20:45:50.849596 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 20:45:50.849873 board id: 1
320 20:45:50.858194 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 20:45:50.869752 fw parse done
322 20:45:50.875742 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 20:45:50.918344 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 20:45:50.929209 PIEI prepare done
325 20:45:50.929500 fastboot data load
326 20:45:50.929741 fastboot data verify
327 20:45:50.934755 verify result: 266
328 20:45:50.940356 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 20:45:50.940636 LPDDR4 probe
330 20:45:50.940879 ddr clk to 1584MHz
331 20:45:50.948342 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 20:45:50.985031
333 20:45:50.985616 dmc_version 0001
334 20:45:50.992333 Check phy result
335 20:45:50.998238 INFO : End of CA training
336 20:45:50.998717 INFO : End of initialization
337 20:45:51.003870 INFO : Training has run successfully!
338 20:45:51.004386 Check phy result
339 20:45:51.009474 INFO : End of initialization
340 20:45:51.009943 INFO : End of read enable training
341 20:45:51.015024 INFO : End of fine write leveling
342 20:45:51.020637 INFO : End of Write leveling coarse delay
343 20:45:51.021162 INFO : Training has run successfully!
344 20:45:51.021599 Check phy result
345 20:45:51.026228 INFO : End of initialization
346 20:45:51.026725 INFO : End of read dq deskew training
347 20:45:51.031821 INFO : End of MPR read delay center optimization
348 20:45:51.037399 INFO : End of write delay center optimization
349 20:45:51.043031 INFO : End of read delay center optimization
350 20:45:51.043510 INFO : End of max read latency training
351 20:45:51.048634 INFO : Training has run successfully!
352 20:45:51.049094 1D training succeed
353 20:45:51.056990 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 20:45:51.105490 Check phy result
355 20:45:51.106013 INFO : End of initialization
356 20:45:51.127851 INFO : End of 2D read delay Voltage center optimization
357 20:45:51.146063 INFO : End of 2D read delay Voltage center optimization
358 20:45:51.198845 INFO : End of 2D write delay Voltage center optimization
359 20:45:51.248168 INFO : End of 2D write delay Voltage center optimization
360 20:45:51.253770 INFO : Training has run successfully!
361 20:45:51.254190
362 20:45:51.254412 channel==0
363 20:45:51.259398 RxClkDly_Margin_A0==78 ps 8
364 20:45:51.259793 TxDqDly_Margin_A0==98 ps 10
365 20:45:51.264897 RxClkDly_Margin_A1==78 ps 8
366 20:45:51.265286 TxDqDly_Margin_A1==98 ps 10
367 20:45:51.265509 TrainedVREFDQ_A0==74
368 20:45:51.270520 TrainedVREFDQ_A1==74
369 20:45:51.270891 VrefDac_Margin_A0==24
370 20:45:51.271130 DeviceVref_Margin_A0==40
371 20:45:51.276144 VrefDac_Margin_A1==23
372 20:45:51.276507 DeviceVref_Margin_A1==40
373 20:45:51.276725
374 20:45:51.276945
375 20:45:51.281687 channel==1
376 20:45:51.282066 RxClkDly_Margin_A0==88 ps 9
377 20:45:51.282289 TxDqDly_Margin_A0==98 ps 10
378 20:45:51.287366 RxClkDly_Margin_A1==78 ps 8
379 20:45:51.287698 TxDqDly_Margin_A1==78 ps 8
380 20:45:51.293089 TrainedVREFDQ_A0==78
381 20:45:51.293435 TrainedVREFDQ_A1==75
382 20:45:51.293657 VrefDac_Margin_A0==22
383 20:45:51.298458 DeviceVref_Margin_A0==36
384 20:45:51.298793 VrefDac_Margin_A1==22
385 20:45:51.305233 DeviceVref_Margin_A1==39
386 20:45:51.305647
387 20:45:51.305882 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 20:45:51.306099
389 20:45:51.337833 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 20:45:51.338325 2D training succeed
391 20:45:51.343428 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 20:45:51.348945 auto size-- 65535DDR cs0 size: 2048MB
393 20:45:51.349332 DDR cs1 size: 2048MB
394 20:45:51.354493 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 20:45:51.354853 cs0 DataBus test pass
396 20:45:51.360257 cs1 DataBus test pass
397 20:45:51.360640 cs0 AddrBus test pass
398 20:45:51.360860 cs1 AddrBus test pass
399 20:45:51.361068
400 20:45:51.365689 100bdlr_step_size ps== 478
401 20:45:51.366041 result report
402 20:45:51.371439 boot times 0Enable ddr reg access
403 20:45:51.376606 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 20:45:51.390054 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 20:45:52.045327 bl2z: ptr: 05129330, size: 00001e40
406 20:45:52.053354 0.0;M3 CHK:0;cm4_sp_mode 0
407 20:45:52.053884 MVN_1=0x00000000
408 20:45:52.054140 MVN_2=0x00000000
409 20:45:52.064790 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 20:45:52.065158 OPS=0x04
411 20:45:52.065374 ring efuse init
412 20:45:52.070469 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 20:45:52.070823 [0.017319 Inits done]
414 20:45:52.071042 secure task start!
415 20:45:52.078503 high task start!
416 20:45:52.078866 low task start!
417 20:45:52.079082 run into bl31
418 20:45:52.087109 NOTICE: BL31: v1.3(release):4fc40b1
419 20:45:52.094384 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 20:45:52.094691 NOTICE: BL31: G12A normal boot!
421 20:45:52.110535 NOTICE: BL31: BL33 decompress pass
422 20:45:52.116224 ERROR: Error initializing runtime service opteed_fast
423 20:45:53.361056 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 20:45:53.361460 bl2_stage_init 0x01
425 20:45:53.361680 bl2_stage_init 0x81
426 20:45:53.366647 hw id: 0x0000 - pwm id 0x01
427 20:45:53.366958 bl2_stage_init 0xc1
428 20:45:53.372240 bl2_stage_init 0x02
429 20:45:53.372546
430 20:45:53.372761 L0:00000000
431 20:45:53.372965 L1:00000703
432 20:45:53.373165 L2:00008067
433 20:45:53.373365 L3:15000000
434 20:45:53.377917 S1:00000000
435 20:45:53.378235 B2:20282000
436 20:45:53.378445 B1:a0f83180
437 20:45:53.378658
438 20:45:53.378862 TE: 70333
439 20:45:53.379062
440 20:45:53.383420 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 20:45:53.383732
442 20:45:53.388992 Board ID = 1
443 20:45:53.389290 Set cpu clk to 24M
444 20:45:53.389524 Set clk81 to 24M
445 20:45:53.394633 Use GP1_pll as DSU clk.
446 20:45:53.394920 DSU clk: 1200 Mhz
447 20:45:53.395127 CPU clk: 1200 MHz
448 20:45:53.400231 Set clk81 to 166.6M
449 20:45:53.405831 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 20:45:53.406134 board id: 1
451 20:45:53.413029 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 20:45:53.423915 fw parse done
453 20:45:53.429847 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 20:45:53.472973 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 20:45:53.484204 PIEI prepare done
456 20:45:53.484495 fastboot data load
457 20:45:53.484701 fastboot data verify
458 20:45:53.489741 verify result: 266
459 20:45:53.495349 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 20:45:53.495626 LPDDR4 probe
461 20:45:53.495834 ddr clk to 1584MHz
462 20:45:54.858339 Load ddrfw from SPI, src: SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 20:45:54.858759 bl2_stage_init 0x01
464 20:45:54.858983 bl2_stage_init 0x81
465 20:45:54.863871 hw id: 0x0000 - pwm id 0x01
466 20:45:54.864202 bl2_stage_init 0xc1
467 20:45:54.869535 bl2_stage_init 0x02
468 20:45:54.869853
469 20:45:54.870070 L0:00000000
470 20:45:54.870285 L1:00000703
471 20:45:54.870495 L2:00008067
472 20:45:54.870701 L3:15000000
473 20:45:54.875087 S1:00000000
474 20:45:54.875382 B2:20282000
475 20:45:54.875592 B1:a0f83180
476 20:45:54.875802
477 20:45:54.876036 TE: 69186
478 20:45:54.876257
479 20:45:54.880697 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 20:45:54.880987
481 20:45:54.886274 Board ID = 1
482 20:45:54.886566 Set cpu clk to 24M
483 20:45:54.886773 Set clk81 to 24M
484 20:45:54.891842 Use GP1_pll as DSU clk.
485 20:45:54.892150 DSU clk: 1200 Mhz
486 20:45:54.892356 CPU clk: 1200 MHz
487 20:45:54.897468 Set clk81 to 166.6M
488 20:45:54.903052 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 20:45:54.903327 board id: 1
490 20:45:54.910228 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 20:45:54.921162 fw parse done
492 20:45:54.927107 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 20:45:54.970238 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 20:45:54.981426 PIEI prepare done
495 20:45:54.981731 fastboot data load
496 20:45:54.981946 fastboot data verify
497 20:45:54.987002 verify result: 266
498 20:45:54.992707 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 20:45:54.993000 LPDDR4 probe
500 20:45:54.993210 ddr clk to 1584MHz
501 20:45:55.000678 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 20:45:55.038337
503 20:45:55.038708 dmc_version 0001
504 20:45:55.045353 Check phy result
505 20:45:55.051338 INFO : End of CA training
506 20:45:55.051629 INFO : End of initialization
507 20:45:55.057039 INFO : Training has run successfully!
508 20:45:55.057556 Check phy result
509 20:45:55.062542 INFO : End of initialization
510 20:45:55.062989 INFO : End of read enable training
511 20:45:55.068186 INFO : End of fine write leveling
512 20:45:55.073778 INFO : End of Write leveling coarse delay
513 20:45:55.074275 INFO : Training has run successfully!
514 20:45:55.074697 Check phy result
515 20:45:55.079305 INFO : End of initialization
516 20:45:55.079785 INFO : End of read dq deskew training
517 20:45:55.084930 INFO : End of MPR read delay center optimization
518 20:45:55.090559 INFO : End of write delay center optimization
519 20:45:55.096180 INFO : End of read delay center optimization
520 20:45:55.096692 INFO : End of max read latency training
521 20:45:55.101767 INFO : Training has run successfully!
522 20:45:55.102276 1D training succeed
523 20:45:55.110899 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 20:45:55.159261 Check phy result
525 20:45:55.159799 INFO : End of initialization
526 20:45:55.186592 INFO : End of 2D read delay Voltage center optimization
527 20:45:55.210789 INFO : End of 2D read delay Voltage center optimization
528 20:45:55.267509 INFO : End of 2D write delay Voltage center optimization
529 20:45:55.321464 INFO : End of 2D write delay Voltage center optimization
530 20:45:55.326994 INFO : Training has run successfully!
531 20:45:55.327518
532 20:45:55.327948 channel==0
533 20:45:55.332588 RxClkDly_Margin_A0==78 ps 8
534 20:45:55.333091 TxDqDly_Margin_A0==98 ps 10
535 20:45:55.338154 RxClkDly_Margin_A1==88 ps 9
536 20:45:55.338613 TxDqDly_Margin_A1==98 ps 10
537 20:45:55.339033 TrainedVREFDQ_A0==74
538 20:45:55.343800 TrainedVREFDQ_A1==74
539 20:45:55.344343 VrefDac_Margin_A0==24
540 20:45:55.344770 DeviceVref_Margin_A0==40
541 20:45:55.349360 VrefDac_Margin_A1==23
542 20:45:55.349863 DeviceVref_Margin_A1==40
543 20:45:55.350285
544 20:45:55.350694
545 20:45:55.354979 channel==1
546 20:45:55.355456 RxClkDly_Margin_A0==78 ps 8
547 20:45:55.355872 TxDqDly_Margin_A0==98 ps 10
548 20:45:55.360669 RxClkDly_Margin_A1==78 ps 8
549 20:45:55.361192 TxDqDly_Margin_A1==88 ps 9
550 20:45:55.366167 TrainedVREFDQ_A0==78
551 20:45:55.366708 TrainedVREFDQ_A1==77
552 20:45:55.367260 VrefDac_Margin_A0==22
553 20:45:55.371876 DeviceVref_Margin_A0==36
554 20:45:55.372407 VrefDac_Margin_A1==22
555 20:45:55.377493 DeviceVref_Margin_A1==37
556 20:45:55.378069
557 20:45:55.378529 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 20:45:55.378953
559 20:45:55.411026 soc_vref_reg_value 0x 00000019 00000018 00000019 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
560 20:45:55.411618 2D training succeed
561 20:45:55.416607 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 20:45:55.422158 auto size-- 65535DDR cs0 size: 2048MB
563 20:45:55.422622 DDR cs1 size: 2048MB
564 20:45:55.427766 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 20:45:55.428264 cs0 DataBus test pass
566 20:45:55.433398 cs1 DataBus test pass
567 20:45:55.433911 cs0 AddrBus test pass
568 20:45:55.434332 cs1 AddrBus test pass
569 20:45:55.434740
570 20:45:55.438982 100bdlr_step_size ps== 478
571 20:45:55.439495 result report
572 20:45:55.444583 boot times 0Enable ddr reg access
573 20:45:55.449864 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 20:45:55.463814 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 20:45:56.123340 bl2z: ptr: 05129330, size: 00001e40
576 20:45:56.130785 0.0;M3 CHK:0;cm4_sp_mode 0
577 20:45:56.131105 MVN_1=0x00000000
578 20:45:56.131317 MVN_2=0x00000000
579 20:45:56.142268 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 20:45:56.142593 OPS=0x04
581 20:45:56.142804 ring efuse init
582 20:45:56.145278 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 20:45:56.151248 [0.017354 Inits done]
584 20:45:56.151514 secure task start!
585 20:45:56.151721 high task start!
586 20:45:56.151918 low task start!
587 20:45:56.155480 run into bl31
588 20:45:56.164281 NOTICE: BL31: v1.3(release):4fc40b1
589 20:45:56.172086 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 20:45:56.172792 NOTICE: BL31: G12A normal boot!
591 20:45:56.187395 NOTICE: BL31: BL33 decompress pass
592 20:45:56.193072 ERROR: Error initializing runtime service opteed_fast
593 20:45:57.409818 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 20:45:57.410242 bl2_stage_init 0x01
595 20:45:57.410464 bl2_stage_init 0x81
596 20:45:57.415266 hw id: 0x0000 - pwm id 0x01
597 20:45:57.415775 bl2_stage_init 0xc1
598 20:45:57.420813 bl2_stage_init 0x02
599 20:45:57.421243
600 20:45:57.421592 L0:00000000
601 20:45:57.421832 L1:00000703
602 20:45:57.422040 L2:00008067
603 20:45:57.422249 L3:15000000
604 20:45:57.426733 S1:00000000
605 20:45:57.427189 B2:20282000
606 20:45:57.427554 B1:a0f83180
607 20:45:57.427928
608 20:45:57.428296 TE: 70139
609 20:45:57.428632
610 20:45:57.432307 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 20:45:57.432676
612 20:45:57.437752 Board ID = 1
613 20:45:57.438270 Set cpu clk to 24M
614 20:45:57.438603 Set clk81 to 24M
615 20:45:57.443378 Use GP1_pll as DSU clk.
616 20:45:57.443771 DSU clk: 1200 Mhz
617 20:45:57.444018 CPU clk: 1200 MHz
618 20:45:57.448900 Set clk81 to 166.6M
619 20:45:57.454608 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 20:45:57.455013 board id: 1
621 20:45:57.461655 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 20:45:57.472500 fw parse done
623 20:45:57.478373 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 20:45:57.520860 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 20:45:57.531783 PIEI prepare done
626 20:45:57.532231 fastboot data load
627 20:45:57.532454 fastboot data verify
628 20:45:57.537365 verify result: 266
629 20:45:57.542989 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 20:45:57.543531 LPDDR4 probe
631 20:45:57.543808 ddr clk to 1584MHz
632 20:45:57.551037 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 20:45:57.588296
634 20:45:57.588706 dmc_version 0001
635 20:45:57.594868 Check phy result
636 20:45:57.600759 INFO : End of CA training
637 20:45:57.601116 INFO : End of initialization
638 20:45:57.606356 INFO : Training has run successfully!
639 20:45:57.606707 Check phy result
640 20:45:57.612016 INFO : End of initialization
641 20:45:57.612382 INFO : End of read enable training
642 20:45:57.617544 INFO : End of fine write leveling
643 20:45:57.623154 INFO : End of Write leveling coarse delay
644 20:45:57.623893 INFO : Training has run successfully!
645 20:45:57.624185 Check phy result
646 20:45:57.628751 INFO : End of initialization
647 20:45:57.629083 INFO : End of read dq deskew training
648 20:45:57.634353 INFO : End of MPR read delay center optimization
649 20:45:57.639966 INFO : End of write delay center optimization
650 20:45:57.645555 INFO : End of read delay center optimization
651 20:45:57.645914 INFO : End of max read latency training
652 20:45:57.651157 INFO : Training has run successfully!
653 20:45:57.651485 1D training succeed
654 20:45:57.660316 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 20:45:57.707940 Check phy result
656 20:45:57.708634 INFO : End of initialization
657 20:45:57.730397 INFO : End of 2D read delay Voltage center optimization
658 20:45:57.749487 INFO : End of 2D read delay Voltage center optimization
659 20:45:57.801451 INFO : End of 2D write delay Voltage center optimization
660 20:45:57.850584 INFO : End of 2D write delay Voltage center optimization
661 20:45:57.856234 INFO : Training has run successfully!
662 20:45:57.856745
663 20:45:57.857193 channel==0
664 20:45:57.861652 RxClkDly_Margin_A0==78 ps 8
665 20:45:57.862134 TxDqDly_Margin_A0==98 ps 10
666 20:45:57.867290 RxClkDly_Margin_A1==88 ps 9
667 20:45:57.867778 TxDqDly_Margin_A1==98 ps 10
668 20:45:57.868268 TrainedVREFDQ_A0==75
669 20:45:57.872848 TrainedVREFDQ_A1==75
670 20:45:57.873353 VrefDac_Margin_A0==24
671 20:45:57.873789 DeviceVref_Margin_A0==39
672 20:45:57.878476 VrefDac_Margin_A1==22
673 20:45:57.878965 DeviceVref_Margin_A1==39
674 20:45:57.879399
675 20:45:57.879832
676 20:45:57.884218 channel==1
677 20:45:57.884685 RxClkDly_Margin_A0==88 ps 9
678 20:45:57.885143 TxDqDly_Margin_A0==98 ps 10
679 20:45:57.889630 RxClkDly_Margin_A1==78 ps 8
680 20:45:57.890107 TxDqDly_Margin_A1==78 ps 8
681 20:45:57.895285 TrainedVREFDQ_A0==78
682 20:45:57.895759 TrainedVREFDQ_A1==75
683 20:45:57.896237 VrefDac_Margin_A0==23
684 20:45:57.900852 DeviceVref_Margin_A0==36
685 20:45:57.901324 VrefDac_Margin_A1==22
686 20:45:57.906469 DeviceVref_Margin_A1==39
687 20:45:57.906939
688 20:45:57.907374 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 20:45:57.907804
690 20:45:57.940214 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
691 20:45:57.940750 2D training succeed
692 20:45:57.945643 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 20:45:57.951171 auto size-- 65535DDR cs0 size: 2048MB
694 20:45:57.951642 DDR cs1 size: 2048MB
695 20:45:57.956849 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 20:45:57.957323 cs0 DataBus test pass
697 20:45:57.962446 cs1 DataBus test pass
698 20:45:57.962913 cs0 AddrBus test pass
699 20:45:57.963345 cs1 AddrBus test pass
700 20:45:57.963771
701 20:45:57.968199 100bdlr_step_size ps== 478
702 20:45:57.968688 result report
703 20:45:57.973823 boot times 0Enable ddr reg access
704 20:45:57.979015 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 20:45:57.992773 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 20:45:58.647494 bl2z: ptr: 05129330, size: 00001e40
707 20:45:58.654723 0.0;M3 CHK:0;cm4_sp_mode 0
708 20:45:58.655055 MVN_1=0x00000000
709 20:45:58.655271 MVN_2=0x00000000
710 20:45:58.666296 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 20:45:58.666596 OPS=0x04
712 20:45:58.666812 ring efuse init
713 20:45:58.669263 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 20:45:58.675689 [0.017319 Inits done]
715 20:45:58.675937 secure task start!
716 20:45:58.676214 high task start!
717 20:45:58.676423 low task start!
718 20:45:58.679881 run into bl31
719 20:45:58.688482 NOTICE: BL31: v1.3(release):4fc40b1
720 20:45:58.696295 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 20:45:58.696541 NOTICE: BL31: G12A normal boot!
722 20:45:58.711997 NOTICE: BL31: BL33 decompress pass
723 20:45:58.717632 ERROR: Error initializing runtime service opteed_fast
724 20:45:59.511916
725 20:45:59.512618
726 20:45:59.517379 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 20:45:59.517926
728 20:45:59.520738 Model: Libre Computer AML-S905D3-CC Solitude
729 20:45:59.667593 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 20:45:59.683065 DRAM: 2 GiB (effective 3.8 GiB)
731 20:45:59.783967 Core: 406 devices, 33 uclasses, devicetree: separate
732 20:45:59.789847 WDT: Not starting watchdog@f0d0
733 20:45:59.814943 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 20:45:59.827148 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 20:45:59.832201 ** Bad device specification mmc 0 **
736 20:45:59.842231 Card did not respond to voltage select! : -110
737 20:45:59.849823 ** Bad device specification mmc 0 **
738 20:45:59.850354 Couldn't find partition mmc 0
739 20:45:59.858129 Card did not respond to voltage select! : -110
740 20:45:59.863658 ** Bad device specification mmc 0 **
741 20:45:59.864205 Couldn't find partition mmc 0
742 20:45:59.868230 Error: could not access storage.
743 20:46:00.166101 Net: eth0: ethernet@ff3f0000
744 20:46:00.166742 starting USB...
745 20:46:00.410791 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 20:46:00.411444 Starting the controller
747 20:46:00.417841 USB XHCI 1.10
748 20:46:01.971518 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 20:46:01.979036 scanning usb for storage devices... 0 Storage Device(s) found
751 20:46:02.030764 Hit any key to stop autoboot: 1
752 20:46:02.031774 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 20:46:02.032504 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 20:46:02.033041 Setting prompt string to ['=>']
755 20:46:02.033572 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 20:46:02.045968 0
757 20:46:02.046934 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 20:46:02.148258 => setenv autoload no
760 20:46:02.149280 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 20:46:02.154973 setenv autoload no
763 20:46:02.256640 => setenv initrd_high 0xffffffff
764 20:46:02.257378 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 20:46:02.261574 setenv initrd_high 0xffffffff
767 20:46:02.362639 => setenv fdt_high 0xffffffff
768 20:46:02.363141 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 20:46:02.367461 setenv fdt_high 0xffffffff
771 20:46:02.468534 => dhcp
772 20:46:02.469180 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 20:46:02.473051 dhcp
774 20:46:03.028705 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
775 20:46:03.029374 Speed: 1000, full duplex
776 20:46:03.029830 BOOTP broadcast 1
777 20:46:03.038970 DHCP client bound to address 192.168.6.21 (9 ms)
779 20:46:03.140590 => setenv serverip 192.168.6.2
780 20:46:03.141380 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
781 20:46:03.146016 setenv serverip 192.168.6.2
783 20:46:03.247540 => tftpboot 0x01080000 962349/tftp-deploy-dqplgg23/kernel/uImage
784 20:46:03.248372 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
785 20:46:03.255114 tftpboot 0x01080000 962349/tftp-deploy-dqplgg23/kernel/uImage
786 20:46:03.255629 Speed: 1000, full duplex
787 20:46:03.256108 Using ethernet@ff3f0000 device
788 20:46:03.260677 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
789 20:46:03.266242 Filename '962349/tftp-deploy-dqplgg23/kernel/uImage'.
790 20:46:03.270148 Load address: 0x1080000
791 20:46:05.573281 Loading: *################################################## 36.1 MiB
792 20:46:05.573911 15.6 MiB/s
793 20:46:05.574357 done
794 20:46:05.577870 Bytes transferred = 37812800 (240fa40 hex)
796 20:46:05.679449 => tftpboot 0x08000000 962349/tftp-deploy-dqplgg23/ramdisk/ramdisk.cpio.gz.uboot
797 20:46:05.680218 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
798 20:46:05.687018 tftpboot 0x08000000 962349/tftp-deploy-dqplgg23/ramdisk/ramdisk.cpio.gz.uboot
799 20:46:05.687536 Speed: 1000, full duplex
800 20:46:05.687976 Using ethernet@ff3f0000 device
801 20:46:05.692629 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
802 20:46:05.702427 Filename '962349/tftp-deploy-dqplgg23/ramdisk/ramdisk.cpio.gz.uboot'.
803 20:46:05.702943 Load address: 0x8000000
804 20:46:10.003413 Loading: *################################################# UDP wrong checksum 0000000f 0000d802
805 20:46:15.005247 T UDP wrong checksum 0000000f 0000d802
806 20:46:25.006056 T T UDP wrong checksum 0000000f 0000d802
807 20:46:38.084329 T T UDP wrong checksum 000000ff 00009794
808 20:46:38.094366 UDP wrong checksum 000000ff 0000f01a
809 20:46:45.011722 T T UDP wrong checksum 0000000f 0000d802
810 20:47:05.016051 T T T
811 20:47:05.016697 Retry count exceeded; starting again
813 20:47:05.018119 end: 2.4.3 bootloader-commands (duration 00:01:03) [common]
816 20:47:05.020044 end: 2.4 uboot-commands (duration 00:01:22) [common]
818 20:47:05.021431 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
820 20:47:05.022525 end: 2 uboot-action (duration 00:01:22) [common]
822 20:47:05.024057 Cleaning after the job
823 20:47:05.024619 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962349/tftp-deploy-dqplgg23/ramdisk
824 20:47:05.026088 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962349/tftp-deploy-dqplgg23/kernel
825 20:47:05.032460 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962349/tftp-deploy-dqplgg23/dtb
826 20:47:05.033558 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962349/tftp-deploy-dqplgg23/modules
827 20:47:05.039738 start: 4.1 power-off (timeout 00:00:30) [common]
828 20:47:05.040780 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
829 20:47:05.079086 >> OK - accepted request
830 20:47:05.081249 Returned 0 in 0 seconds
831 20:47:05.182385 end: 4.1 power-off (duration 00:00:00) [common]
833 20:47:05.184085 start: 4.2 read-feedback (timeout 00:10:00) [common]
834 20:47:05.185209 Listened to connection for namespace 'common' for up to 1s
835 20:47:06.186028 Finalising connection for namespace 'common'
836 20:47:06.186739 Disconnecting from shell: Finalise
837 20:47:06.187247 =>
838 20:47:06.288414 end: 4.2 read-feedback (duration 00:00:01) [common]
839 20:47:06.289056 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/962349
840 20:47:06.931476 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/962349
841 20:47:06.932127 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.