Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:11:43.692980 lava-dispatcher, installed at version: 2024.01
2 21:11:43.693797 start: 0 validate
3 21:11:43.694266 Start time: 2024-11-08 21:11:43.694235+00:00 (UTC)
4 21:11:43.694817 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:11:43.695360 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 21:11:43.731445 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:11:43.732015 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-225-g50643bbc9eb6%2Farm64%2Fdefconfig%2Fclang-16%2Fkernel%2FImage exists
8 21:11:43.763411 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:11:43.764055 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-225-g50643bbc9eb6%2Farm64%2Fdefconfig%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:11:43.793392 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:11:43.794007 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 21:11:43.823866 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 21:11:43.824399 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-225-g50643bbc9eb6%2Farm64%2Fdefconfig%2Fclang-16%2Fmodules.tar.xz exists
14 21:11:43.861049 validate duration: 0.17
16 21:11:43.861886 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 21:11:43.862222 start: 1.1 download-retry (timeout 00:10:00) [common]
18 21:11:43.862547 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 21:11:43.863132 Not decompressing ramdisk as can be used compressed.
20 21:11:43.863583 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 21:11:43.863874 saving as /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/ramdisk/initrd.cpio.gz
22 21:11:43.864178 total size: 5628169 (5 MB)
23 21:11:43.897965 progress 0 % (0 MB)
24 21:11:43.902278 progress 5 % (0 MB)
25 21:11:43.906555 progress 10 % (0 MB)
26 21:11:43.910254 progress 15 % (0 MB)
27 21:11:43.914409 progress 20 % (1 MB)
28 21:11:43.918080 progress 25 % (1 MB)
29 21:11:43.922182 progress 30 % (1 MB)
30 21:11:43.926282 progress 35 % (1 MB)
31 21:11:43.929977 progress 40 % (2 MB)
32 21:11:43.934105 progress 45 % (2 MB)
33 21:11:43.938427 progress 50 % (2 MB)
34 21:11:43.942468 progress 55 % (2 MB)
35 21:11:43.946573 progress 60 % (3 MB)
36 21:11:43.950200 progress 65 % (3 MB)
37 21:11:43.954260 progress 70 % (3 MB)
38 21:11:43.957896 progress 75 % (4 MB)
39 21:11:43.961969 progress 80 % (4 MB)
40 21:11:43.965681 progress 85 % (4 MB)
41 21:11:43.969650 progress 90 % (4 MB)
42 21:11:43.973332 progress 95 % (5 MB)
43 21:11:43.976652 progress 100 % (5 MB)
44 21:11:43.977317 5 MB downloaded in 0.11 s (47.45 MB/s)
45 21:11:43.977877 end: 1.1.1 http-download (duration 00:00:00) [common]
47 21:11:43.978821 end: 1.1 download-retry (duration 00:00:00) [common]
48 21:11:43.979143 start: 1.2 download-retry (timeout 00:10:00) [common]
49 21:11:43.979441 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 21:11:43.979938 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-225-g50643bbc9eb6/arm64/defconfig/clang-16/kernel/Image
51 21:11:43.980230 saving as /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/kernel/Image
52 21:11:43.980461 total size: 37812736 (36 MB)
53 21:11:43.980686 No compression specified
54 21:11:44.016921 progress 0 % (0 MB)
55 21:11:44.040779 progress 5 % (1 MB)
56 21:11:44.065299 progress 10 % (3 MB)
57 21:11:44.089584 progress 15 % (5 MB)
58 21:11:44.112919 progress 20 % (7 MB)
59 21:11:44.137020 progress 25 % (9 MB)
60 21:11:44.160798 progress 30 % (10 MB)
61 21:11:44.184157 progress 35 % (12 MB)
62 21:11:44.207840 progress 40 % (14 MB)
63 21:11:44.231687 progress 45 % (16 MB)
64 21:11:44.255427 progress 50 % (18 MB)
65 21:11:44.279440 progress 55 % (19 MB)
66 21:11:44.303358 progress 60 % (21 MB)
67 21:11:44.327312 progress 65 % (23 MB)
68 21:11:44.351078 progress 70 % (25 MB)
69 21:11:44.374952 progress 75 % (27 MB)
70 21:11:44.399260 progress 80 % (28 MB)
71 21:11:44.423056 progress 85 % (30 MB)
72 21:11:44.447394 progress 90 % (32 MB)
73 21:11:44.471797 progress 95 % (34 MB)
74 21:11:44.494593 progress 100 % (36 MB)
75 21:11:44.495360 36 MB downloaded in 0.51 s (70.04 MB/s)
76 21:11:44.495872 end: 1.2.1 http-download (duration 00:00:01) [common]
78 21:11:44.496769 end: 1.2 download-retry (duration 00:00:01) [common]
79 21:11:44.497068 start: 1.3 download-retry (timeout 00:09:59) [common]
80 21:11:44.497359 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 21:11:44.497845 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-225-g50643bbc9eb6/arm64/defconfig/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 21:11:44.498132 saving as /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/dtb/meson-g12b-a311d-libretech-cc.dtb
83 21:11:44.498360 total size: 54703 (0 MB)
84 21:11:44.498586 No compression specified
85 21:11:44.534156 progress 59 % (0 MB)
86 21:11:44.535037 progress 100 % (0 MB)
87 21:11:44.535628 0 MB downloaded in 0.04 s (1.40 MB/s)
88 21:11:44.536177 end: 1.3.1 http-download (duration 00:00:00) [common]
90 21:11:44.537049 end: 1.3 download-retry (duration 00:00:00) [common]
91 21:11:44.537335 start: 1.4 download-retry (timeout 00:09:59) [common]
92 21:11:44.537617 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 21:11:44.538097 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 21:11:44.538354 saving as /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/nfsrootfs/full.rootfs.tar
95 21:11:44.538576 total size: 120894716 (115 MB)
96 21:11:44.538797 Using unxz to decompress xz
97 21:11:44.573544 progress 0 % (0 MB)
98 21:11:45.359379 progress 5 % (5 MB)
99 21:11:46.190117 progress 10 % (11 MB)
100 21:11:46.979667 progress 15 % (17 MB)
101 21:11:47.711613 progress 20 % (23 MB)
102 21:11:48.301003 progress 25 % (28 MB)
103 21:11:49.120724 progress 30 % (34 MB)
104 21:11:49.905710 progress 35 % (40 MB)
105 21:11:50.275272 progress 40 % (46 MB)
106 21:11:50.691670 progress 45 % (51 MB)
107 21:11:51.411796 progress 50 % (57 MB)
108 21:11:52.295748 progress 55 % (63 MB)
109 21:11:53.078566 progress 60 % (69 MB)
110 21:11:53.833887 progress 65 % (74 MB)
111 21:11:54.614083 progress 70 % (80 MB)
112 21:11:55.444455 progress 75 % (86 MB)
113 21:11:56.237143 progress 80 % (92 MB)
114 21:11:56.996890 progress 85 % (98 MB)
115 21:11:57.848988 progress 90 % (103 MB)
116 21:11:58.621854 progress 95 % (109 MB)
117 21:11:59.453847 progress 100 % (115 MB)
118 21:11:59.466258 115 MB downloaded in 14.93 s (7.72 MB/s)
119 21:11:59.466999 end: 1.4.1 http-download (duration 00:00:15) [common]
121 21:11:59.468686 end: 1.4 download-retry (duration 00:00:15) [common]
122 21:11:59.469230 start: 1.5 download-retry (timeout 00:09:44) [common]
123 21:11:59.469762 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 21:11:59.470603 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-225-g50643bbc9eb6/arm64/defconfig/clang-16/modules.tar.xz
125 21:11:59.471079 saving as /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/modules/modules.tar
126 21:11:59.471499 total size: 11766788 (11 MB)
127 21:11:59.471924 Using unxz to decompress xz
128 21:11:59.520049 progress 0 % (0 MB)
129 21:11:59.589067 progress 5 % (0 MB)
130 21:11:59.664126 progress 10 % (1 MB)
131 21:11:59.759827 progress 15 % (1 MB)
132 21:11:59.856109 progress 20 % (2 MB)
133 21:11:59.935410 progress 25 % (2 MB)
134 21:12:00.012459 progress 30 % (3 MB)
135 21:12:00.092881 progress 35 % (3 MB)
136 21:12:00.172862 progress 40 % (4 MB)
137 21:12:00.249210 progress 45 % (5 MB)
138 21:12:00.335216 progress 50 % (5 MB)
139 21:12:00.418798 progress 55 % (6 MB)
140 21:12:00.504962 progress 60 % (6 MB)
141 21:12:00.587400 progress 65 % (7 MB)
142 21:12:00.669728 progress 70 % (7 MB)
143 21:12:00.753932 progress 75 % (8 MB)
144 21:12:00.838270 progress 80 % (9 MB)
145 21:12:00.919512 progress 85 % (9 MB)
146 21:12:01.003732 progress 90 % (10 MB)
147 21:12:01.083622 progress 95 % (10 MB)
148 21:12:01.161692 progress 100 % (11 MB)
149 21:12:01.172087 11 MB downloaded in 1.70 s (6.60 MB/s)
150 21:12:01.173027 end: 1.5.1 http-download (duration 00:00:02) [common]
152 21:12:01.174844 end: 1.5 download-retry (duration 00:00:02) [common]
153 21:12:01.175420 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 21:12:01.176031 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 21:12:17.952664 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/962423/extract-nfsrootfs-ys985ssr
156 21:12:17.953282 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 21:12:17.953572 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 21:12:17.954352 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8
159 21:12:17.954819 makedir: /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin
160 21:12:17.955149 makedir: /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/tests
161 21:12:17.955471 makedir: /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/results
162 21:12:17.955804 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-add-keys
163 21:12:17.956406 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-add-sources
164 21:12:17.956990 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-background-process-start
165 21:12:17.957500 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-background-process-stop
166 21:12:17.958029 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-common-functions
167 21:12:17.958597 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-echo-ipv4
168 21:12:17.959153 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-install-packages
169 21:12:17.959692 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-installed-packages
170 21:12:17.960212 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-os-build
171 21:12:17.960728 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-probe-channel
172 21:12:17.961229 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-probe-ip
173 21:12:17.961710 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-target-ip
174 21:12:17.962184 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-target-mac
175 21:12:17.962664 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-target-storage
176 21:12:17.963157 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-test-case
177 21:12:17.963648 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-test-event
178 21:12:17.964163 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-test-feedback
179 21:12:17.964672 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-test-raise
180 21:12:17.965159 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-test-reference
181 21:12:17.965637 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-test-runner
182 21:12:17.966121 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-test-set
183 21:12:17.966593 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-test-shell
184 21:12:17.967083 Updating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-add-keys (debian)
185 21:12:17.967617 Updating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-add-sources (debian)
186 21:12:17.968151 Updating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-install-packages (debian)
187 21:12:17.968665 Updating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-installed-packages (debian)
188 21:12:17.969163 Updating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/bin/lava-os-build (debian)
189 21:12:17.969618 Creating /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/environment
190 21:12:17.970006 LAVA metadata
191 21:12:17.970270 - LAVA_JOB_ID=962423
192 21:12:17.970486 - LAVA_DISPATCHER_IP=192.168.6.2
193 21:12:17.970852 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 21:12:17.971808 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 21:12:17.972175 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 21:12:17.972390 skipped lava-vland-overlay
197 21:12:17.972631 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 21:12:17.972885 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 21:12:17.973103 skipped lava-multinode-overlay
200 21:12:17.973347 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 21:12:17.973600 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 21:12:17.973851 Loading test definitions
203 21:12:17.974128 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 21:12:17.974350 Using /lava-962423 at stage 0
205 21:12:17.975456 uuid=962423_1.6.2.4.1 testdef=None
206 21:12:17.975765 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 21:12:17.976050 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 21:12:17.977620 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 21:12:17.978413 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 21:12:17.980376 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 21:12:17.981209 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 21:12:17.983044 runner path: /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/0/tests/0_timesync-off test_uuid 962423_1.6.2.4.1
215 21:12:17.983594 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 21:12:17.984450 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 21:12:17.984679 Using /lava-962423 at stage 0
219 21:12:17.985040 Fetching tests from https://github.com/kernelci/test-definitions.git
220 21:12:17.985334 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/0/tests/1_kselftest-alsa'
221 21:12:21.408240 Running '/usr/bin/git checkout kernelci.org
222 21:12:21.759084 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 21:12:21.760565 uuid=962423_1.6.2.4.5 testdef=None
224 21:12:21.760920 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 21:12:21.761693 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 21:12:21.764551 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 21:12:21.765389 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 21:12:21.769125 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 21:12:21.770002 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 21:12:21.773608 runner path: /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/0/tests/1_kselftest-alsa test_uuid 962423_1.6.2.4.5
234 21:12:21.773892 BOARD='meson-g12b-a311d-libretech-cc'
235 21:12:21.774110 BRANCH='mainline'
236 21:12:21.774315 SKIPFILE='/dev/null'
237 21:12:21.774518 SKIP_INSTALL='True'
238 21:12:21.774719 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-225-g50643bbc9eb6/arm64/defconfig/clang-16/kselftest.tar.xz'
239 21:12:21.774925 TST_CASENAME=''
240 21:12:21.775128 TST_CMDFILES='alsa'
241 21:12:21.775686 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 21:12:21.776500 Creating lava-test-runner.conf files
244 21:12:21.776717 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/962423/lava-overlay-jehxibj8/lava-962423/0 for stage 0
245 21:12:21.777082 - 0_timesync-off
246 21:12:21.777328 - 1_kselftest-alsa
247 21:12:21.777672 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 21:12:21.777962 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 21:12:45.201805 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 21:12:45.202247 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 21:12:45.202513 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 21:12:45.202785 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 21:12:45.203053 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 21:12:45.843229 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 21:12:45.843712 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 21:12:45.843968 extracting modules file /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/962423/extract-nfsrootfs-ys985ssr
257 21:12:47.239560 extracting modules file /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/962423/extract-overlay-ramdisk-zc2mj0h9/ramdisk
258 21:12:48.675064 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 21:12:48.675565 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 21:12:48.675854 [common] Applying overlay to NFS
261 21:12:48.676104 [common] Applying overlay /var/lib/lava/dispatcher/tmp/962423/compress-overlay-8v4lp0da/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/962423/extract-nfsrootfs-ys985ssr
262 21:12:51.423966 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 21:12:51.424458 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 21:12:51.424733 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 21:12:51.424970 Converting downloaded kernel to a uImage
266 21:12:51.425282 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/kernel/Image /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/kernel/uImage
267 21:12:51.872601 output: Image Name:
268 21:12:51.873020 output: Created: Fri Nov 8 21:12:51 2024
269 21:12:51.873228 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 21:12:51.873432 output: Data Size: 37812736 Bytes = 36926.50 KiB = 36.06 MiB
271 21:12:51.873635 output: Load Address: 01080000
272 21:12:51.873835 output: Entry Point: 01080000
273 21:12:51.874033 output:
274 21:12:51.874374 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 21:12:51.874640 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 21:12:51.874908 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 21:12:51.875161 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 21:12:51.875419 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 21:12:51.875687 Building ramdisk /var/lib/lava/dispatcher/tmp/962423/extract-overlay-ramdisk-zc2mj0h9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/962423/extract-overlay-ramdisk-zc2mj0h9/ramdisk
280 21:12:54.238733 >> 173443 blocks
281 21:13:01.952888 Adding RAMdisk u-boot header.
282 21:13:01.953598 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/962423/extract-overlay-ramdisk-zc2mj0h9/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/962423/extract-overlay-ramdisk-zc2mj0h9/ramdisk.cpio.gz.uboot
283 21:13:02.202380 output: Image Name:
284 21:13:02.202878 output: Created: Fri Nov 8 21:13:01 2024
285 21:13:02.203503 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 21:13:02.204104 output: Data Size: 24151745 Bytes = 23585.69 KiB = 23.03 MiB
287 21:13:02.204654 output: Load Address: 00000000
288 21:13:02.205175 output: Entry Point: 00000000
289 21:13:02.205705 output:
290 21:13:02.207088 rename /var/lib/lava/dispatcher/tmp/962423/extract-overlay-ramdisk-zc2mj0h9/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/ramdisk/ramdisk.cpio.gz.uboot
291 21:13:02.208077 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 21:13:02.208823 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 21:13:02.209565 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 21:13:02.210163 No LXC device requested
295 21:13:02.210832 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 21:13:02.211507 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 21:13:02.212193 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 21:13:02.212746 Checking files for TFTP limit of 4294967296 bytes.
299 21:13:02.216250 end: 1 tftp-deploy (duration 00:01:18) [common]
300 21:13:02.217001 start: 2 uboot-action (timeout 00:05:00) [common]
301 21:13:02.217697 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 21:13:02.218363 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 21:13:02.219032 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 21:13:02.219721 Using kernel file from prepare-kernel: 962423/tftp-deploy-uwqvqwgh/kernel/uImage
305 21:13:02.220578 substitutions:
306 21:13:02.221122 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 21:13:02.221658 - {DTB_ADDR}: 0x01070000
308 21:13:02.222176 - {DTB}: 962423/tftp-deploy-uwqvqwgh/dtb/meson-g12b-a311d-libretech-cc.dtb
309 21:13:02.222708 - {INITRD}: 962423/tftp-deploy-uwqvqwgh/ramdisk/ramdisk.cpio.gz.uboot
310 21:13:02.223227 - {KERNEL_ADDR}: 0x01080000
311 21:13:02.223739 - {KERNEL}: 962423/tftp-deploy-uwqvqwgh/kernel/uImage
312 21:13:02.224341 - {LAVA_MAC}: None
313 21:13:02.224935 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/962423/extract-nfsrootfs-ys985ssr
314 21:13:02.225472 - {NFS_SERVER_IP}: 192.168.6.2
315 21:13:02.225986 - {PRESEED_CONFIG}: None
316 21:13:02.226509 - {PRESEED_LOCAL}: None
317 21:13:02.227022 - {RAMDISK_ADDR}: 0x08000000
318 21:13:02.227535 - {RAMDISK}: 962423/tftp-deploy-uwqvqwgh/ramdisk/ramdisk.cpio.gz.uboot
319 21:13:02.228097 - {ROOT_PART}: None
320 21:13:02.228638 - {ROOT}: None
321 21:13:02.229164 - {SERVER_IP}: 192.168.6.2
322 21:13:02.229680 - {TEE_ADDR}: 0x83000000
323 21:13:02.230202 - {TEE}: None
324 21:13:02.230727 Parsed boot commands:
325 21:13:02.231234 - setenv autoload no
326 21:13:02.231756 - setenv initrd_high 0xffffffff
327 21:13:02.232307 - setenv fdt_high 0xffffffff
328 21:13:02.232828 - dhcp
329 21:13:02.233338 - setenv serverip 192.168.6.2
330 21:13:02.233860 - tftpboot 0x01080000 962423/tftp-deploy-uwqvqwgh/kernel/uImage
331 21:13:02.234383 - tftpboot 0x08000000 962423/tftp-deploy-uwqvqwgh/ramdisk/ramdisk.cpio.gz.uboot
332 21:13:02.234897 - tftpboot 0x01070000 962423/tftp-deploy-uwqvqwgh/dtb/meson-g12b-a311d-libretech-cc.dtb
333 21:13:02.235423 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/962423/extract-nfsrootfs-ys985ssr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 21:13:02.235946 - bootm 0x01080000 0x08000000 0x01070000
335 21:13:02.236655 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 21:13:02.238596 start: 2.3 connect-device (timeout 00:05:00) [common]
338 21:13:02.239151 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 21:13:02.255789 Setting prompt string to ['lava-test: # ']
340 21:13:02.257690 end: 2.3 connect-device (duration 00:00:00) [common]
341 21:13:02.258533 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 21:13:02.259472 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 21:13:02.260329 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 21:13:02.261813 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 21:13:02.300767 >> OK - accepted request
346 21:13:02.302904 Returned 0 in 0 seconds
347 21:13:02.404368 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 21:13:02.406477 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 21:13:02.407217 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 21:13:02.407902 Setting prompt string to ['Hit any key to stop autoboot']
352 21:13:02.408573 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 21:13:02.410662 Trying 192.168.56.21...
354 21:13:02.411305 Connected to conserv1.
355 21:13:02.411869 Escape character is '^]'.
356 21:13:02.412472
357 21:13:02.413040 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 21:13:02.413595
359 21:13:14.331218 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 21:13:14.331838 bl2_stage_init 0x01
361 21:13:14.332349 bl2_stage_init 0x81
362 21:13:14.336820 hw id: 0x0000 - pwm id 0x01
363 21:13:14.337305 bl2_stage_init 0xc1
364 21:13:14.337725 bl2_stage_init 0x02
365 21:13:14.338129
366 21:13:14.342298 L0:00000000
367 21:13:14.342742 L1:20000703
368 21:13:14.343147 L2:00008067
369 21:13:14.343548 L3:14000000
370 21:13:14.347757 B2:00402000
371 21:13:14.348217 B1:e0f83180
372 21:13:14.348610
373 21:13:14.348998 TE: 58159
374 21:13:14.349384
375 21:13:14.353405 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 21:13:14.353821
377 21:13:14.354209 Board ID = 1
378 21:13:14.359004 Set A53 clk to 24M
379 21:13:14.359417 Set A73 clk to 24M
380 21:13:14.359803 Set clk81 to 24M
381 21:13:14.364701 A53 clk: 1200 MHz
382 21:13:14.365118 A73 clk: 1200 MHz
383 21:13:14.365501 CLK81: 166.6M
384 21:13:14.365882 smccc: 00012ab5
385 21:13:14.370272 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 21:13:14.375771 board id: 1
387 21:13:14.381750 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 21:13:14.392539 fw parse done
389 21:13:14.398473 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 21:13:14.441121 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 21:13:14.452049 PIEI prepare done
392 21:13:14.452609 fastboot data load
393 21:13:14.453014 fastboot data verify
394 21:13:14.457661 verify result: 266
395 21:13:14.463119 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 21:13:14.463586 LPDDR4 probe
397 21:13:14.464021 ddr clk to 1584MHz
398 21:13:14.471119 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 21:13:14.508489
400 21:13:14.509125 dmc_version 0001
401 21:13:14.515067 Check phy result
402 21:13:14.520913 INFO : End of CA training
403 21:13:14.521382 INFO : End of initialization
404 21:13:14.526814 INFO : Training has run successfully!
405 21:13:14.527273 Check phy result
406 21:13:14.532148 INFO : End of initialization
407 21:13:14.532583 INFO : End of read enable training
408 21:13:14.537686 INFO : End of fine write leveling
409 21:13:14.543308 INFO : End of Write leveling coarse delay
410 21:13:14.543747 INFO : Training has run successfully!
411 21:13:14.544178 Check phy result
412 21:13:14.548934 INFO : End of initialization
413 21:13:14.549374 INFO : End of read dq deskew training
414 21:13:14.554548 INFO : End of MPR read delay center optimization
415 21:13:14.560096 INFO : End of write delay center optimization
416 21:13:14.565653 INFO : End of read delay center optimization
417 21:13:14.566082 INFO : End of max read latency training
418 21:13:14.571347 INFO : Training has run successfully!
419 21:13:14.571791 1D training succeed
420 21:13:14.580417 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 21:13:14.628316 Check phy result
422 21:13:14.628758 INFO : End of initialization
423 21:13:14.649947 INFO : End of 2D read delay Voltage center optimization
424 21:13:14.669273 INFO : End of 2D read delay Voltage center optimization
425 21:13:14.721268 INFO : End of 2D write delay Voltage center optimization
426 21:13:14.770566 INFO : End of 2D write delay Voltage center optimization
427 21:13:14.776160 INFO : Training has run successfully!
428 21:13:14.776591
429 21:13:14.776992 channel==0
430 21:13:14.781737 RxClkDly_Margin_A0==88 ps 9
431 21:13:14.782160 TxDqDly_Margin_A0==98 ps 10
432 21:13:14.787293 RxClkDly_Margin_A1==88 ps 9
433 21:13:14.787706 TxDqDly_Margin_A1==98 ps 10
434 21:13:14.788150 TrainedVREFDQ_A0==74
435 21:13:14.792923 TrainedVREFDQ_A1==75
436 21:13:14.793347 VrefDac_Margin_A0==24
437 21:13:14.793740 DeviceVref_Margin_A0==40
438 21:13:14.798632 VrefDac_Margin_A1==25
439 21:13:14.799045 DeviceVref_Margin_A1==39
440 21:13:14.799435
441 21:13:14.799825
442 21:13:14.804254 channel==1
443 21:13:14.804667 RxClkDly_Margin_A0==88 ps 9
444 21:13:14.805056 TxDqDly_Margin_A0==98 ps 10
445 21:13:14.809770 RxClkDly_Margin_A1==88 ps 9
446 21:13:14.810187 TxDqDly_Margin_A1==88 ps 9
447 21:13:14.815324 TrainedVREFDQ_A0==77
448 21:13:14.815739 TrainedVREFDQ_A1==77
449 21:13:14.816164 VrefDac_Margin_A0==23
450 21:13:14.820940 DeviceVref_Margin_A0==37
451 21:13:14.821357 VrefDac_Margin_A1==23
452 21:13:14.826541 DeviceVref_Margin_A1==37
453 21:13:14.826951
454 21:13:14.827347 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 21:13:14.827732
456 21:13:14.860085 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000017 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000018 00000018 00000019 00000019 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000061
457 21:13:14.860572 2D training succeed
458 21:13:14.865722 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 21:13:14.871336 auto size-- 65535DDR cs0 size: 2048MB
460 21:13:14.871750 DDR cs1 size: 2048MB
461 21:13:14.876978 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 21:13:14.877395 cs0 DataBus test pass
463 21:13:14.882532 cs1 DataBus test pass
464 21:13:14.882950 cs0 AddrBus test pass
465 21:13:14.883339 cs1 AddrBus test pass
466 21:13:14.883726
467 21:13:14.888159 100bdlr_step_size ps== 420
468 21:13:14.888585 result report
469 21:13:14.893735 boot times 0Enable ddr reg access
470 21:13:14.899024 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 21:13:14.912471 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 21:13:15.486176 0.0;M3 CHK:0;cm4_sp_mode 0
473 21:13:15.486793 MVN_1=0x00000000
474 21:13:15.491656 MVN_2=0x00000000
475 21:13:15.497424 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 21:13:15.497879 OPS=0x10
477 21:13:15.498277 ring efuse init
478 21:13:15.498667 chipver efuse init
479 21:13:15.503006 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 21:13:15.508608 [0.018961 Inits done]
481 21:13:15.509032 secure task start!
482 21:13:15.509421 high task start!
483 21:13:15.513184 low task start!
484 21:13:15.513611 run into bl31
485 21:13:15.519840 NOTICE: BL31: v1.3(release):4fc40b1
486 21:13:15.527635 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 21:13:15.528094 NOTICE: BL31: G12A normal boot!
488 21:13:15.553649 NOTICE: BL31: BL33 decompress pass
489 21:13:15.559218 ERROR: Error initializing runtime service opteed_fast
490 21:13:16.792160
491 21:13:16.792753
492 21:13:16.800605 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 21:13:16.801042
494 21:13:16.801453 Model: Libre Computer AML-A311D-CC Alta
495 21:13:17.008843 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 21:13:17.032279 DRAM: 2 GiB (effective 3.8 GiB)
497 21:13:17.175225 Core: 408 devices, 31 uclasses, devicetree: separate
498 21:13:17.181115 WDT: Not starting watchdog@f0d0
499 21:13:17.213388 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 21:13:17.225832 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 21:13:17.230828 ** Bad device specification mmc 0 **
502 21:13:17.241204 Card did not respond to voltage select! : -110
503 21:13:17.248810 ** Bad device specification mmc 0 **
504 21:13:17.249232 Couldn't find partition mmc 0
505 21:13:17.257185 Card did not respond to voltage select! : -110
506 21:13:17.262695 ** Bad device specification mmc 0 **
507 21:13:17.263120 Couldn't find partition mmc 0
508 21:13:17.267742 Error: could not access storage.
509 21:13:18.531151 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 21:13:18.531772 bl2_stage_init 0x01
511 21:13:18.532255 bl2_stage_init 0x81
512 21:13:18.536687 hw id: 0x0000 - pwm id 0x01
513 21:13:18.537136 bl2_stage_init 0xc1
514 21:13:18.537541 bl2_stage_init 0x02
515 21:13:18.537938
516 21:13:18.542322 L0:00000000
517 21:13:18.542763 L1:20000703
518 21:13:18.543170 L2:00008067
519 21:13:18.543571 L3:14000000
520 21:13:18.547886 B2:00402000
521 21:13:18.548358 B1:e0f83180
522 21:13:18.548763
523 21:13:18.549164 TE: 58124
524 21:13:18.549564
525 21:13:18.553494 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 21:13:18.553931
527 21:13:18.554337 Board ID = 1
528 21:13:18.559097 Set A53 clk to 24M
529 21:13:18.559527 Set A73 clk to 24M
530 21:13:18.559929 Set clk81 to 24M
531 21:13:18.564714 A53 clk: 1200 MHz
532 21:13:18.565149 A73 clk: 1200 MHz
533 21:13:18.565551 CLK81: 166.6M
534 21:13:18.565948 smccc: 00012a91
535 21:13:18.570321 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 21:13:18.575878 board id: 1
537 21:13:18.581773 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 21:13:18.592438 fw parse done
539 21:13:18.598386 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 21:13:18.641024 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 21:13:18.651893 PIEI prepare done
542 21:13:18.652363 fastboot data load
543 21:13:18.652776 fastboot data verify
544 21:13:18.657547 verify result: 266
545 21:13:18.663140 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 21:13:18.663563 LPDDR4 probe
547 21:13:18.663962 ddr clk to 1584MHz
548 21:13:18.671121 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 21:13:18.708412
550 21:13:18.708844 dmc_version 0001
551 21:13:18.715109 Check phy result
552 21:13:18.721015 INFO : End of CA training
553 21:13:18.721442 INFO : End of initialization
554 21:13:18.726564 INFO : Training has run successfully!
555 21:13:18.726992 Check phy result
556 21:13:18.732249 INFO : End of initialization
557 21:13:18.732674 INFO : End of read enable training
558 21:13:18.737883 INFO : End of fine write leveling
559 21:13:18.743365 INFO : End of Write leveling coarse delay
560 21:13:18.743788 INFO : Training has run successfully!
561 21:13:18.744223 Check phy result
562 21:13:18.748946 INFO : End of initialization
563 21:13:18.749368 INFO : End of read dq deskew training
564 21:13:18.754521 INFO : End of MPR read delay center optimization
565 21:13:18.760137 INFO : End of write delay center optimization
566 21:13:18.765739 INFO : End of read delay center optimization
567 21:13:18.766157 INFO : End of max read latency training
568 21:13:18.771397 INFO : Training has run successfully!
569 21:13:18.771819 1D training succeed
570 21:13:18.780517 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 21:13:18.828136 Check phy result
572 21:13:18.828569 INFO : End of initialization
573 21:13:18.849892 INFO : End of 2D read delay Voltage center optimization
574 21:13:18.869251 INFO : End of 2D read delay Voltage center optimization
575 21:13:18.921296 INFO : End of 2D write delay Voltage center optimization
576 21:13:18.970682 INFO : End of 2D write delay Voltage center optimization
577 21:13:18.976231 INFO : Training has run successfully!
578 21:13:18.976679
579 21:13:18.977096 channel==0
580 21:13:18.981951 RxClkDly_Margin_A0==88 ps 9
581 21:13:18.982396 TxDqDly_Margin_A0==98 ps 10
582 21:13:18.987454 RxClkDly_Margin_A1==78 ps 8
583 21:13:18.987918 TxDqDly_Margin_A1==98 ps 10
584 21:13:18.988386 TrainedVREFDQ_A0==74
585 21:13:18.993028 TrainedVREFDQ_A1==74
586 21:13:18.993472 VrefDac_Margin_A0==25
587 21:13:18.993878 DeviceVref_Margin_A0==40
588 21:13:18.998616 VrefDac_Margin_A1==25
589 21:13:18.999054 DeviceVref_Margin_A1==40
590 21:13:18.999467
591 21:13:18.999876
592 21:13:19.004210 channel==1
593 21:13:19.004649 RxClkDly_Margin_A0==88 ps 9
594 21:13:19.005062 TxDqDly_Margin_A0==88 ps 9
595 21:13:19.009858 RxClkDly_Margin_A1==88 ps 9
596 21:13:19.010299 TxDqDly_Margin_A1==88 ps 9
597 21:13:19.015401 TrainedVREFDQ_A0==77
598 21:13:19.015859 TrainedVREFDQ_A1==77
599 21:13:19.016314 VrefDac_Margin_A0==23
600 21:13:19.021024 DeviceVref_Margin_A0==37
601 21:13:19.021474 VrefDac_Margin_A1==23
602 21:13:19.026612 DeviceVref_Margin_A1==37
603 21:13:19.027066
604 21:13:19.027479 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 21:13:19.027894
606 21:13:19.060225 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000017 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000061
607 21:13:19.060717 2D training succeed
608 21:13:19.065842 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 21:13:19.071405 auto size-- 65535DDR cs0 size: 2048MB
610 21:13:19.071838 DDR cs1 size: 2048MB
611 21:13:19.077010 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 21:13:19.077435 cs0 DataBus test pass
613 21:13:19.082607 cs1 DataBus test pass
614 21:13:19.083051 cs0 AddrBus test pass
615 21:13:19.083456 cs1 AddrBus test pass
616 21:13:19.083853
617 21:13:19.088190 100bdlr_step_size ps== 420
618 21:13:19.088631 result report
619 21:13:19.093871 boot times 0Enable ddr reg access
620 21:13:19.099013 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 21:13:19.112498 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 21:13:19.686487 0.0;M3 CHK:0;cm4_sp_mode 0
623 21:13:19.687076 MVN_1=0x00000000
624 21:13:19.691796 MVN_2=0x00000000
625 21:13:19.697708 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 21:13:19.698193 OPS=0x10
627 21:13:19.698633 ring efuse init
628 21:13:19.699033 chipver efuse init
629 21:13:19.706216 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 21:13:19.706660 [0.018960 Inits done]
631 21:13:19.707049 secure task start!
632 21:13:19.713445 high task start!
633 21:13:19.713868 low task start!
634 21:13:19.714255 run into bl31
635 21:13:19.720069 NOTICE: BL31: v1.3(release):4fc40b1
636 21:13:19.727742 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 21:13:19.728195 NOTICE: BL31: G12A normal boot!
638 21:13:19.753220 NOTICE: BL31: BL33 decompress pass
639 21:13:19.758848 ERROR: Error initializing runtime service opteed_fast
640 21:13:20.992013
641 21:13:20.992613
642 21:13:21.000182 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 21:13:21.000639
644 21:13:21.001059 Model: Libre Computer AML-A311D-CC Alta
645 21:13:21.208574 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 21:13:21.231974 DRAM: 2 GiB (effective 3.8 GiB)
647 21:13:21.375012 Core: 408 devices, 31 uclasses, devicetree: separate
648 21:13:21.380856 WDT: Not starting watchdog@f0d0
649 21:13:21.413010 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 21:13:21.425636 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 21:13:21.430577 ** Bad device specification mmc 0 **
652 21:13:21.440955 Card did not respond to voltage select! : -110
653 21:13:21.448498 ** Bad device specification mmc 0 **
654 21:13:21.448958 Couldn't find partition mmc 0
655 21:13:21.457018 Card did not respond to voltage select! : -110
656 21:13:21.462484 ** Bad device specification mmc 0 **
657 21:13:21.462913 Couldn't find partition mmc 0
658 21:13:21.467443 Error: could not access storage.
659 21:13:21.809932 Net: eth0: ethernet@ff3f0000
660 21:13:21.810485 starting USB...
661 21:13:22.061822 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 21:13:22.062374 Starting the controller
663 21:13:22.068619 USB XHCI 1.10
664 21:13:23.783133 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 21:13:23.783775 bl2_stage_init 0x01
666 21:13:23.784271 bl2_stage_init 0x81
667 21:13:23.788783 hw id: 0x0000 - pwm id 0x01
668 21:13:23.789256 bl2_stage_init 0xc1
669 21:13:23.789675 bl2_stage_init 0x02
670 21:13:23.790084
671 21:13:23.794770 L0:00000000
672 21:13:23.795260 L1:20000703
673 21:13:23.795672 L2:00008067
674 21:13:23.796112 L3:14000000
675 21:13:23.797205 B2:00402000
676 21:13:23.797632 B1:e0f83180
677 21:13:23.798037
678 21:13:23.798446 TE: 58159
679 21:13:23.798850
680 21:13:23.808247 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 21:13:23.808757
682 21:13:23.809194 Board ID = 1
683 21:13:23.809603 Set A53 clk to 24M
684 21:13:23.810002 Set A73 clk to 24M
685 21:13:23.813926 Set clk81 to 24M
686 21:13:23.814374 A53 clk: 1200 MHz
687 21:13:23.814784 A73 clk: 1200 MHz
688 21:13:23.819363 CLK81: 166.6M
689 21:13:23.819811 smccc: 00012ab5
690 21:13:23.825127 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 21:13:23.825566 board id: 1
692 21:13:23.833887 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 21:13:23.844233 fw parse done
694 21:13:23.850073 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 21:13:23.892822 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 21:13:23.903694 PIEI prepare done
697 21:13:23.904186 fastboot data load
698 21:13:23.904607 fastboot data verify
699 21:13:23.909343 verify result: 266
700 21:13:23.914856 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 21:13:23.915299 LPDDR4 probe
702 21:13:23.915703 ddr clk to 1584MHz
703 21:13:23.922869 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 21:13:23.960115
705 21:13:23.960598 dmc_version 0001
706 21:13:23.966779 Check phy result
707 21:13:23.972651 INFO : End of CA training
708 21:13:23.973082 INFO : End of initialization
709 21:13:23.978214 INFO : Training has run successfully!
710 21:13:23.978648 Check phy result
711 21:13:23.983825 INFO : End of initialization
712 21:13:23.984292 INFO : End of read enable training
713 21:13:23.989528 INFO : End of fine write leveling
714 21:13:23.995067 INFO : End of Write leveling coarse delay
715 21:13:23.995496 INFO : Training has run successfully!
716 21:13:23.995902 Check phy result
717 21:13:24.000667 INFO : End of initialization
718 21:13:24.001105 INFO : End of read dq deskew training
719 21:13:24.006229 INFO : End of MPR read delay center optimization
720 21:13:24.011847 INFO : End of write delay center optimization
721 21:13:24.017545 INFO : End of read delay center optimization
722 21:13:24.017988 INFO : End of max read latency training
723 21:13:24.023077 INFO : Training has run successfully!
724 21:13:24.023534 1D training succeed
725 21:13:24.032250 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 21:13:24.079841 Check phy result
727 21:13:24.080408 INFO : End of initialization
728 21:13:24.101375 INFO : End of 2D read delay Voltage center optimization
729 21:13:24.120675 INFO : End of 2D read delay Voltage center optimization
730 21:13:24.172559 INFO : End of 2D write delay Voltage center optimization
731 21:13:24.221865 INFO : End of 2D write delay Voltage center optimization
732 21:13:24.227281 INFO : Training has run successfully!
733 21:13:24.227741
734 21:13:24.228207 channel==0
735 21:13:24.232976 RxClkDly_Margin_A0==88 ps 9
736 21:13:24.233424 TxDqDly_Margin_A0==98 ps 10
737 21:13:24.238597 RxClkDly_Margin_A1==88 ps 9
738 21:13:24.239034 TxDqDly_Margin_A1==98 ps 10
739 21:13:24.239442 TrainedVREFDQ_A0==74
740 21:13:24.244241 TrainedVREFDQ_A1==75
741 21:13:24.244726 VrefDac_Margin_A0==25
742 21:13:24.245136 DeviceVref_Margin_A0==40
743 21:13:24.249752 VrefDac_Margin_A1==24
744 21:13:24.250211 DeviceVref_Margin_A1==39
745 21:13:24.250631
746 21:13:24.251073
747 21:13:24.255357 channel==1
748 21:13:24.255812 RxClkDly_Margin_A0==88 ps 9
749 21:13:24.256269 TxDqDly_Margin_A0==88 ps 9
750 21:13:24.261004 RxClkDly_Margin_A1==78 ps 8
751 21:13:24.261447 TxDqDly_Margin_A1==88 ps 9
752 21:13:24.266613 TrainedVREFDQ_A0==77
753 21:13:24.267063 TrainedVREFDQ_A1==77
754 21:13:24.267475 VrefDac_Margin_A0==23
755 21:13:24.272227 DeviceVref_Margin_A0==37
756 21:13:24.272671 VrefDac_Margin_A1==24
757 21:13:24.277740 DeviceVref_Margin_A1==37
758 21:13:24.278188
759 21:13:24.278602 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 21:13:24.279004
761 21:13:24.311374 soc_vref_reg_value 0x 00000019 00000019 00000017 00000018 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000017 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000061
762 21:13:24.311897 2D training succeed
763 21:13:24.316984 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 21:13:24.322586 auto size-- 65535DDR cs0 size: 2048MB
765 21:13:24.323028 DDR cs1 size: 2048MB
766 21:13:24.328258 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 21:13:24.328720 cs0 DataBus test pass
768 21:13:24.333764 cs1 DataBus test pass
769 21:13:24.334211 cs0 AddrBus test pass
770 21:13:24.334621 cs1 AddrBus test pass
771 21:13:24.335022
772 21:13:24.339353 100bdlr_step_size ps== 420
773 21:13:24.339813 result report
774 21:13:24.344963 boot times 0Enable ddr reg access
775 21:13:24.350166 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 21:13:24.363663 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 21:13:24.935638 0.0;M3 CHK:0;cm4_sp_mode 0
778 21:13:24.936267 MVN_1=0x00000000
779 21:13:24.941077 MVN_2=0x00000000
780 21:13:24.946830 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 21:13:24.947323 OPS=0x10
782 21:13:24.947725 ring efuse init
783 21:13:24.948149 chipver efuse init
784 21:13:24.952392 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 21:13:24.958000 [0.018961 Inits done]
786 21:13:24.958414 secure task start!
787 21:13:24.958808 high task start!
788 21:13:24.962675 low task start!
789 21:13:24.963096 run into bl31
790 21:13:24.969251 NOTICE: BL31: v1.3(release):4fc40b1
791 21:13:24.977060 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 21:13:24.977493 NOTICE: BL31: G12A normal boot!
793 21:13:25.002566 NOTICE: BL31: BL33 decompress pass
794 21:13:25.008220 ERROR: Error initializing runtime service opteed_fast
795 21:13:26.241126
796 21:13:26.241758
797 21:13:26.249387 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 21:13:26.249846
799 21:13:26.250267 Model: Libre Computer AML-A311D-CC Alta
800 21:13:26.457857 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 21:13:26.481206 DRAM: 2 GiB (effective 3.8 GiB)
802 21:13:26.624244 Core: 408 devices, 31 uclasses, devicetree: separate
803 21:13:26.630044 WDT: Not starting watchdog@f0d0
804 21:13:26.662332 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 21:13:26.674861 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 21:13:26.679723 ** Bad device specification mmc 0 **
807 21:13:26.690090 Card did not respond to voltage select! : -110
808 21:13:26.697711 ** Bad device specification mmc 0 **
809 21:13:26.698164 Couldn't find partition mmc 0
810 21:13:26.706050 Card did not respond to voltage select! : -110
811 21:13:26.711643 ** Bad device specification mmc 0 **
812 21:13:26.712144 Couldn't find partition mmc 0
813 21:13:26.716672 Error: could not access storage.
814 21:13:27.060192 Net: eth0: ethernet@ff3f0000
815 21:13:27.060785 starting USB...
816 21:13:27.312083 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 21:13:27.312637 Starting the controller
818 21:13:27.319000 USB XHCI 1.10
819 21:13:29.481923 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 21:13:29.482552 bl2_stage_init 0x01
821 21:13:29.482976 bl2_stage_init 0x81
822 21:13:29.487124 hw id: 0x0000 - pwm id 0x01
823 21:13:29.487565 bl2_stage_init 0xc1
824 21:13:29.487976 bl2_stage_init 0x02
825 21:13:29.488448
826 21:13:29.492948 L0:00000000
827 21:13:29.493380 L1:20000703
828 21:13:29.493784 L2:00008067
829 21:13:29.494185 L3:14000000
830 21:13:29.498263 B2:00402000
831 21:13:29.498701 B1:e0f83180
832 21:13:29.499108
833 21:13:29.499510 TE: 58159
834 21:13:29.499914
835 21:13:29.504160 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 21:13:29.504603
837 21:13:29.505010 Board ID = 1
838 21:13:29.509904 Set A53 clk to 24M
839 21:13:29.510344 Set A73 clk to 24M
840 21:13:29.510747 Set clk81 to 24M
841 21:13:29.515082 A53 clk: 1200 MHz
842 21:13:29.515509 A73 clk: 1200 MHz
843 21:13:29.515914 CLK81: 166.6M
844 21:13:29.516348 smccc: 00012ab5
845 21:13:29.520760 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 21:13:29.526358 board id: 1
847 21:13:29.532271 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 21:13:29.542612 fw parse done
849 21:13:29.548568 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 21:13:29.591305 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 21:13:29.602078 PIEI prepare done
852 21:13:29.602522 fastboot data load
853 21:13:29.602928 fastboot data verify
854 21:13:29.607763 verify result: 266
855 21:13:29.613382 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 21:13:29.613819 LPDDR4 probe
857 21:13:29.614227 ddr clk to 1584MHz
858 21:13:29.621392 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 21:13:29.658556
860 21:13:29.658990 dmc_version 0001
861 21:13:29.665384 Check phy result
862 21:13:29.671112 INFO : End of CA training
863 21:13:29.671543 INFO : End of initialization
864 21:13:29.676706 INFO : Training has run successfully!
865 21:13:29.677132 Check phy result
866 21:13:29.682314 INFO : End of initialization
867 21:13:29.682737 INFO : End of read enable training
868 21:13:29.687920 INFO : End of fine write leveling
869 21:13:29.693546 INFO : End of Write leveling coarse delay
870 21:13:29.693971 INFO : Training has run successfully!
871 21:13:29.694375 Check phy result
872 21:13:29.699141 INFO : End of initialization
873 21:13:29.699568 INFO : End of read dq deskew training
874 21:13:29.704728 INFO : End of MPR read delay center optimization
875 21:13:29.710317 INFO : End of write delay center optimization
876 21:13:29.715948 INFO : End of read delay center optimization
877 21:13:29.716406 INFO : End of max read latency training
878 21:13:29.721545 INFO : Training has run successfully!
879 21:13:29.721972 1D training succeed
880 21:13:29.730757 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 21:13:29.778508 Check phy result
882 21:13:29.778944 INFO : End of initialization
883 21:13:29.799943 INFO : End of 2D read delay Voltage center optimization
884 21:13:29.819185 INFO : End of 2D read delay Voltage center optimization
885 21:13:29.871066 INFO : End of 2D write delay Voltage center optimization
886 21:13:29.920356 INFO : End of 2D write delay Voltage center optimization
887 21:13:29.925868 INFO : Training has run successfully!
888 21:13:29.926292
889 21:13:29.926698 channel==0
890 21:13:29.931468 RxClkDly_Margin_A0==78 ps 8
891 21:13:29.931895 TxDqDly_Margin_A0==98 ps 10
892 21:13:29.937045 RxClkDly_Margin_A1==88 ps 9
893 21:13:29.937468 TxDqDly_Margin_A1==98 ps 10
894 21:13:29.937893 TrainedVREFDQ_A0==74
895 21:13:29.942699 TrainedVREFDQ_A1==76
896 21:13:29.943182 VrefDac_Margin_A0==25
897 21:13:29.943598 DeviceVref_Margin_A0==40
898 21:13:29.948365 VrefDac_Margin_A1==25
899 21:13:29.948814 DeviceVref_Margin_A1==38
900 21:13:29.949198
901 21:13:29.949584
902 21:13:29.953869 channel==1
903 21:13:29.954302 RxClkDly_Margin_A0==88 ps 9
904 21:13:29.954691 TxDqDly_Margin_A0==98 ps 10
905 21:13:29.959471 RxClkDly_Margin_A1==88 ps 9
906 21:13:29.959893 TxDqDly_Margin_A1==88 ps 9
907 21:13:29.965063 TrainedVREFDQ_A0==77
908 21:13:29.965481 TrainedVREFDQ_A1==77
909 21:13:29.965866 VrefDac_Margin_A0==23
910 21:13:29.970667 DeviceVref_Margin_A0==37
911 21:13:29.971074 VrefDac_Margin_A1==23
912 21:13:29.976352 DeviceVref_Margin_A1==37
913 21:13:29.976763
914 21:13:29.977151 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 21:13:29.977539
916 21:13:30.009878 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000017 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000061
917 21:13:30.010344 2D training succeed
918 21:13:30.015479 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 21:13:30.021078 auto size-- 65535DDR cs0 size: 2048MB
920 21:13:30.021507 DDR cs1 size: 2048MB
921 21:13:30.026669 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 21:13:30.027088 cs0 DataBus test pass
923 21:13:30.032358 cs1 DataBus test pass
924 21:13:30.032767 cs0 AddrBus test pass
925 21:13:30.033153 cs1 AddrBus test pass
926 21:13:30.033534
927 21:13:30.037900 100bdlr_step_size ps== 420
928 21:13:30.038324 result report
929 21:13:30.043473 boot times 0Enable ddr reg access
930 21:13:30.048721 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 21:13:30.062199 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 21:13:30.634228 0.0;M3 CHK:0;cm4_sp_mode 0
933 21:13:30.634851 MVN_1=0x00000000
934 21:13:30.639672 MVN_2=0x00000000
935 21:13:30.645437 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 21:13:30.645873 OPS=0x10
937 21:13:30.646280 ring efuse init
938 21:13:30.646676 chipver efuse init
939 21:13:30.651011 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 21:13:30.656612 [0.018961 Inits done]
941 21:13:30.657057 secure task start!
942 21:13:30.657458 high task start!
943 21:13:30.661227 low task start!
944 21:13:30.661647 run into bl31
945 21:13:30.667853 NOTICE: BL31: v1.3(release):4fc40b1
946 21:13:30.675665 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 21:13:30.676122 NOTICE: BL31: G12A normal boot!
948 21:13:30.701032 NOTICE: BL31: BL33 decompress pass
949 21:13:30.706726 ERROR: Error initializing runtime service opteed_fast
950 21:13:31.939821
951 21:13:31.940494
952 21:13:31.948019 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 21:13:31.948466
954 21:13:31.948874 Model: Libre Computer AML-A311D-CC Alta
955 21:13:32.156415 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 21:13:32.179828 DRAM: 2 GiB (effective 3.8 GiB)
957 21:13:32.322813 Core: 408 devices, 31 uclasses, devicetree: separate
958 21:13:32.328698 WDT: Not starting watchdog@f0d0
959 21:13:32.360920 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 21:13:32.373381 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 21:13:32.378365 ** Bad device specification mmc 0 **
962 21:13:32.388706 Card did not respond to voltage select! : -110
963 21:13:32.396407 ** Bad device specification mmc 0 **
964 21:13:32.396842 Couldn't find partition mmc 0
965 21:13:32.404689 Card did not respond to voltage select! : -110
966 21:13:32.410250 ** Bad device specification mmc 0 **
967 21:13:32.410698 Couldn't find partition mmc 0
968 21:13:32.415393 Error: could not access storage.
969 21:13:32.757833 Net: eth0: ethernet@ff3f0000
970 21:13:32.758438 starting USB...
971 21:13:33.009564 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 21:13:33.010075 Starting the controller
973 21:13:33.016537 USB XHCI 1.10
974 21:13:34.571145 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 21:13:34.579347 scanning usb for storage devices... 0 Storage Device(s) found
977 21:13:34.630849 Hit any key to stop autoboot: 1
978 21:13:34.631614 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
979 21:13:34.632234 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
980 21:13:34.632713 Setting prompt string to ['=>']
981 21:13:34.633193 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
982 21:13:34.646776 0
983 21:13:34.647604 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 21:13:34.648141 Sending with 10 millisecond of delay
986 21:13:35.782615 => setenv autoload no
987 21:13:35.793450 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
988 21:13:35.798320 setenv autoload no
989 21:13:35.799023 Sending with 10 millisecond of delay
991 21:13:37.595694 => setenv initrd_high 0xffffffff
992 21:13:37.606516 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
993 21:13:37.607361 setenv initrd_high 0xffffffff
994 21:13:37.608082 Sending with 10 millisecond of delay
996 21:13:39.225585 => setenv fdt_high 0xffffffff
997 21:13:39.236355 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
998 21:13:39.237142 setenv fdt_high 0xffffffff
999 21:13:39.237844 Sending with 10 millisecond of delay
1001 21:13:39.529665 => dhcp
1002 21:13:39.540448 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1003 21:13:39.541292 dhcp
1004 21:13:39.541731 Speed: 1000, full duplex
1005 21:13:39.542142 BOOTP broadcast 1
1006 21:13:39.549660 DHCP client bound to address 192.168.6.27 (9 ms)
1007 21:13:39.550363 Sending with 10 millisecond of delay
1009 21:13:41.226473 => setenv serverip 192.168.6.2
1010 21:13:41.237256 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1011 21:13:41.238117 setenv serverip 192.168.6.2
1012 21:13:41.238802 Sending with 10 millisecond of delay
1014 21:13:44.962586 => tftpboot 0x01080000 962423/tftp-deploy-uwqvqwgh/kernel/uImage
1015 21:13:44.973424 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1016 21:13:44.974322 tftpboot 0x01080000 962423/tftp-deploy-uwqvqwgh/kernel/uImage
1017 21:13:44.974819 Speed: 1000, full duplex
1018 21:13:44.975277 Using ethernet@ff3f0000 device
1019 21:13:44.976179 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1020 21:13:44.981725 Filename '962423/tftp-deploy-uwqvqwgh/kernel/uImage'.
1021 21:13:44.985820 Load address: 0x1080000
1022 21:13:47.162036 Loading: *############################################# UDP wrong checksum 000000ff 0000a23c
1023 21:13:47.174556 UDP wrong checksum 000000ff 0000382f
1024 21:13:47.377885 ##### 36.1 MiB
1025 21:13:47.378571 15.1 MiB/s
1026 21:13:47.379046 done
1027 21:13:47.381633 Bytes transferred = 37812800 (240fa40 hex)
1028 21:13:47.382484 Sending with 10 millisecond of delay
1030 21:13:52.070708 => tftpboot 0x08000000 962423/tftp-deploy-uwqvqwgh/ramdisk/ramdisk.cpio.gz.uboot
1031 21:13:52.081566 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1032 21:13:52.082476 tftpboot 0x08000000 962423/tftp-deploy-uwqvqwgh/ramdisk/ramdisk.cpio.gz.uboot
1033 21:13:52.082965 Speed: 1000, full duplex
1034 21:13:52.083432 Using ethernet@ff3f0000 device
1035 21:13:52.084423 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1036 21:13:52.096295 Filename '962423/tftp-deploy-uwqvqwgh/ramdisk/ramdisk.cpio.gz.uboot'.
1037 21:13:52.096803 Load address: 0x8000000
1038 21:13:58.956733 Loading: *###############################T ################## UDP wrong checksum 00000005 0000fba6
1039 21:14:03.956788 T UDP wrong checksum 00000005 0000fba6
1040 21:14:12.377506 T UDP wrong checksum 000000ff 00001d79
1041 21:14:12.426063 UDP wrong checksum 000000ff 0000a96b
1042 21:14:13.958057 T UDP wrong checksum 00000005 0000fba6
1043 21:14:32.567141 T T T UDP wrong checksum 000000ff 00001118
1044 21:14:32.606900 UDP wrong checksum 000000ff 0000aa0a
1045 21:14:33.962853 T UDP wrong checksum 00000005 0000fba6
1046 21:14:48.967161 T T
1047 21:14:48.967971 Retry count exceeded; starting again
1049 21:14:48.969858 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1052 21:14:48.972378 end: 2.4 uboot-commands (duration 00:01:47) [common]
1054 21:14:48.974236 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1056 21:14:48.975571 end: 2 uboot-action (duration 00:01:47) [common]
1058 21:14:48.977555 Cleaning after the job
1059 21:14:48.978261 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/ramdisk
1060 21:14:48.979937 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/kernel
1061 21:14:49.025895 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/dtb
1062 21:14:49.026946 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/nfsrootfs
1063 21:14:49.068016 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/962423/tftp-deploy-uwqvqwgh/modules
1064 21:14:49.074882 start: 4.1 power-off (timeout 00:00:30) [common]
1065 21:14:49.075584 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1066 21:14:49.110292 >> OK - accepted request
1067 21:14:49.112466 Returned 0 in 0 seconds
1068 21:14:49.213315 end: 4.1 power-off (duration 00:00:00) [common]
1070 21:14:49.214424 start: 4.2 read-feedback (timeout 00:10:00) [common]
1071 21:14:49.215227 Listened to connection for namespace 'common' for up to 1s
1072 21:14:50.216158 Finalising connection for namespace 'common'
1073 21:14:50.216665 Disconnecting from shell: Finalise
1074 21:14:50.216959 =>
1075 21:14:50.317772 end: 4.2 read-feedback (duration 00:00:01) [common]
1076 21:14:50.318369 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/962423
1077 21:14:53.515074 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/962423
1078 21:14:53.515690 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.