Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 22:25:00.113779 lava-dispatcher, installed at version: 2023.08
2 22:25:00.114091 start: 0 validate
3 22:25:00.114276 Start time: 2024-11-08 22:25:00.114265+00:00 (UTC)
4 22:25:00.114502 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 22:25:00.864172 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-15/kernel/zImage exists
6 22:25:00.978470 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb exists
7 22:25:01.093203 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 22:25:01.207764 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-15/modules.tar.xz exists
9 22:25:01.326517 validate duration: 1.21
11 22:25:01.327294 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 22:25:01.327638 start: 1.1 download-retry (timeout 00:10:00) [common]
13 22:25:01.327954 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 22:25:01.328423 Not decompressing ramdisk as can be used compressed.
15 22:25:01.328750 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 22:25:01.329002 saving as /var/lib/lava/dispatcher/tmp/1219904/tftp-deploy-u6vbidi_/ramdisk/initrd.cpio.gz
17 22:25:01.329247 total size: 4775763 (4 MB)
18 22:25:01.555842 progress 0 % (0 MB)
19 22:25:01.892512 progress 5 % (0 MB)
20 22:25:02.003911 progress 10 % (0 MB)
21 22:25:02.296664 progress 15 % (0 MB)
22 22:25:02.302122 progress 20 % (0 MB)
23 22:25:02.341814 progress 25 % (1 MB)
24 22:25:02.347512 progress 30 % (1 MB)
25 22:25:02.354117 progress 35 % (1 MB)
26 22:25:02.409410 progress 40 % (1 MB)
27 22:25:02.464043 progress 45 % (2 MB)
28 22:25:02.518987 progress 50 % (2 MB)
29 22:25:02.575872 progress 55 % (2 MB)
30 22:25:02.630318 progress 60 % (2 MB)
31 22:25:02.682804 progress 65 % (2 MB)
32 22:25:02.741572 progress 70 % (3 MB)
33 22:25:02.793512 progress 75 % (3 MB)
34 22:25:02.826546 progress 80 % (3 MB)
35 22:25:02.901239 progress 85 % (3 MB)
36 22:25:02.934231 progress 90 % (4 MB)
37 22:25:03.011342 progress 95 % (4 MB)
38 22:25:03.039671 progress 100 % (4 MB)
39 22:25:03.040515 4 MB downloaded in 1.71 s (2.66 MB/s)
40 22:25:03.041037 end: 1.1.1 http-download (duration 00:00:02) [common]
42 22:25:03.041891 end: 1.1 download-retry (duration 00:00:02) [common]
43 22:25:03.042188 start: 1.2 download-retry (timeout 00:09:58) [common]
44 22:25:03.042477 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 22:25:03.042890 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-15/kernel/zImage
46 22:25:03.043120 saving as /var/lib/lava/dispatcher/tmp/1219904/tftp-deploy-u6vbidi_/kernel/zImage
47 22:25:03.043339 total size: 12050944 (11 MB)
48 22:25:03.043560 No compression specified
49 22:25:03.160555 progress 0 % (0 MB)
50 22:25:03.501973 progress 5 % (0 MB)
51 22:25:03.729330 progress 10 % (1 MB)
52 22:25:03.948113 progress 15 % (1 MB)
53 22:25:04.176411 progress 20 % (2 MB)
54 22:25:04.406848 progress 25 % (2 MB)
55 22:25:04.635286 progress 30 % (3 MB)
56 22:25:04.859717 progress 35 % (4 MB)
57 22:25:05.087175 progress 40 % (4 MB)
58 22:25:05.311268 progress 45 % (5 MB)
59 22:25:05.532498 progress 50 % (5 MB)
60 22:25:05.757216 progress 55 % (6 MB)
61 22:25:05.977698 progress 60 % (6 MB)
62 22:25:06.200730 progress 65 % (7 MB)
63 22:25:06.419142 progress 70 % (8 MB)
64 22:25:06.641712 progress 75 % (8 MB)
65 22:25:06.866032 progress 80 % (9 MB)
66 22:25:07.084529 progress 85 % (9 MB)
67 22:25:07.296910 progress 90 % (10 MB)
68 22:25:07.518032 progress 95 % (10 MB)
69 22:25:07.678673 progress 100 % (11 MB)
70 22:25:07.679458 11 MB downloaded in 4.64 s (2.48 MB/s)
71 22:25:07.679919 end: 1.2.1 http-download (duration 00:00:05) [common]
73 22:25:07.680772 end: 1.2 download-retry (duration 00:00:05) [common]
74 22:25:07.681075 start: 1.3 download-retry (timeout 00:09:54) [common]
75 22:25:07.681367 start: 1.3.1 http-download (timeout 00:09:54) [common]
76 22:25:07.681777 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
77 22:25:07.682010 saving as /var/lib/lava/dispatcher/tmp/1219904/tftp-deploy-u6vbidi_/dtb/am335x-boneblack.dtb
78 22:25:07.682230 total size: 70568 (0 MB)
79 22:25:07.682453 No compression specified
80 22:25:07.801213 progress 46 % (0 MB)
81 22:25:07.804027 progress 92 % (0 MB)
82 22:25:07.805037 progress 100 % (0 MB)
83 22:25:07.805432 0 MB downloaded in 0.12 s (0.55 MB/s)
84 22:25:07.805837 end: 1.3.1 http-download (duration 00:00:00) [common]
86 22:25:07.806640 end: 1.3 download-retry (duration 00:00:00) [common]
87 22:25:07.806925 start: 1.4 download-retry (timeout 00:09:54) [common]
88 22:25:07.807213 start: 1.4.1 http-download (timeout 00:09:54) [common]
89 22:25:07.807572 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 22:25:07.807799 saving as /var/lib/lava/dispatcher/tmp/1219904/tftp-deploy-u6vbidi_/nfsrootfs/full.rootfs.tar
91 22:25:07.808013 total size: 117747780 (112 MB)
92 22:25:07.808236 Using unxz to decompress xz
93 22:25:07.924671 progress 0 % (0 MB)
94 22:25:10.417316 progress 5 % (5 MB)
95 22:25:12.544514 progress 10 % (11 MB)
96 22:25:14.653135 progress 15 % (16 MB)
97 22:25:16.680193 progress 20 % (22 MB)
98 22:25:18.579568 progress 25 % (28 MB)
99 22:25:20.152278 progress 30 % (33 MB)
100 22:25:21.406280 progress 35 % (39 MB)
101 22:25:22.436490 progress 40 % (44 MB)
102 22:25:23.323102 progress 45 % (50 MB)
103 22:25:24.082099 progress 50 % (56 MB)
104 22:25:24.716783 progress 55 % (61 MB)
105 22:25:25.315117 progress 60 % (67 MB)
106 22:25:25.833252 progress 65 % (73 MB)
107 22:25:26.461170 progress 70 % (78 MB)
108 22:25:26.967301 progress 75 % (84 MB)
109 22:25:27.554895 progress 80 % (89 MB)
110 22:25:28.116291 progress 85 % (95 MB)
111 22:25:28.775300 progress 90 % (101 MB)
112 22:25:29.499374 progress 95 % (106 MB)
113 22:25:30.188176 progress 100 % (112 MB)
114 22:25:30.192332 112 MB downloaded in 22.38 s (5.02 MB/s)
115 22:25:30.192740 end: 1.4.1 http-download (duration 00:00:22) [common]
117 22:25:30.193420 end: 1.4 download-retry (duration 00:00:22) [common]
118 22:25:30.193655 start: 1.5 download-retry (timeout 00:09:31) [common]
119 22:25:30.193886 start: 1.5.1 http-download (timeout 00:09:31) [common]
120 22:25:30.194228 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-15/modules.tar.xz
121 22:25:30.194404 saving as /var/lib/lava/dispatcher/tmp/1219904/tftp-deploy-u6vbidi_/modules/modules.tar
122 22:25:30.194581 total size: 6916636 (6 MB)
123 22:25:30.194762 Using unxz to decompress xz
124 22:25:30.310679 progress 0 % (0 MB)
125 22:25:30.646231 progress 5 % (0 MB)
126 22:25:30.879582 progress 10 % (0 MB)
127 22:25:30.908362 progress 15 % (1 MB)
128 22:25:30.991188 progress 20 % (1 MB)
129 22:25:31.018659 progress 25 % (1 MB)
130 22:25:31.094154 progress 30 % (2 MB)
131 22:25:31.125037 progress 35 % (2 MB)
132 22:25:31.225667 progress 40 % (2 MB)
133 22:25:31.322785 progress 45 % (2 MB)
134 22:25:31.368417 progress 50 % (3 MB)
135 22:25:31.456809 progress 55 % (3 MB)
136 22:25:31.554166 progress 60 % (3 MB)
137 22:25:31.650150 progress 65 % (4 MB)
138 22:25:31.682061 progress 70 % (4 MB)
139 22:25:31.781020 progress 75 % (4 MB)
140 22:25:31.873793 progress 80 % (5 MB)
141 22:25:31.912585 progress 85 % (5 MB)
142 22:25:32.004218 progress 90 % (5 MB)
143 22:25:32.099015 progress 95 % (6 MB)
144 22:25:32.131960 progress 100 % (6 MB)
145 22:25:32.134966 6 MB downloaded in 1.94 s (3.40 MB/s)
146 22:25:32.135302 end: 1.5.1 http-download (duration 00:00:02) [common]
148 22:25:32.135907 end: 1.5 download-retry (duration 00:00:02) [common]
149 22:25:32.136121 start: 1.6 prepare-tftp-overlay (timeout 00:09:29) [common]
150 22:25:32.136335 start: 1.6.1 extract-nfsrootfs (timeout 00:09:29) [common]
151 22:25:37.713982 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1219904/extract-nfsrootfs-n430qnyz
152 22:25:37.714321 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 22:25:37.714472 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
154 22:25:37.714769 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv
155 22:25:37.714960 makedir: /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin
156 22:25:37.715106 makedir: /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/tests
157 22:25:37.715258 makedir: /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/results
158 22:25:37.715420 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-add-keys
159 22:25:37.715647 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-add-sources
160 22:25:37.715829 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-background-process-start
161 22:25:37.716015 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-background-process-stop
162 22:25:37.716219 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-common-functions
163 22:25:37.716403 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-echo-ipv4
164 22:25:37.716580 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-install-packages
165 22:25:37.716907 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-installed-packages
166 22:25:37.717082 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-os-build
167 22:25:37.717256 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-probe-channel
168 22:25:37.717429 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-probe-ip
169 22:25:37.717605 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-target-ip
170 22:25:37.717780 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-target-mac
171 22:25:37.717953 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-target-storage
172 22:25:37.718130 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-test-case
173 22:25:37.718303 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-test-event
174 22:25:37.718474 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-test-feedback
175 22:25:37.718646 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-test-raise
176 22:25:37.718819 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-test-reference
177 22:25:37.718991 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-test-runner
178 22:25:37.719164 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-test-set
179 22:25:37.719336 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-test-shell
180 22:25:37.719511 Updating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-add-keys (debian)
181 22:25:37.719736 Updating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-add-sources (debian)
182 22:25:37.719932 Updating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-install-packages (debian)
183 22:25:37.720127 Updating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-installed-packages (debian)
184 22:25:37.720321 Updating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/bin/lava-os-build (debian)
185 22:25:37.720492 Creating /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/environment
186 22:25:37.720625 LAVA metadata
187 22:25:37.720749 - LAVA_JOB_ID=1219904
188 22:25:37.720847 - LAVA_DISPATCHER_IP=192.168.11.5
189 22:25:37.720993 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
190 22:25:37.721324 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 22:25:37.721449 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
192 22:25:37.721543 skipped lava-vland-overlay
193 22:25:37.721657 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 22:25:37.721777 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
195 22:25:37.721875 skipped lava-multinode-overlay
196 22:25:37.721989 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 22:25:37.722106 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
198 22:25:37.722208 Loading test definitions
199 22:25:37.722333 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
200 22:25:37.722434 Using /lava-1219904 at stage 0
201 22:25:37.722845 uuid=1219904_1.6.2.4.1 testdef=None
202 22:25:37.722969 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 22:25:37.723089 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
204 22:25:37.723704 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 22:25:37.724040 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
207 22:25:37.724962 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 22:25:37.725342 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
210 22:25:37.726123 runner path: /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/0/tests/0_timesync-off test_uuid 1219904_1.6.2.4.1
211 22:25:37.726341 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 22:25:37.726714 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
214 22:25:37.726817 Using /lava-1219904 at stage 0
215 22:25:37.726960 Fetching tests from https://github.com/kernelci/test-definitions.git
216 22:25:37.727068 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/0/tests/1_kselftest-dt'
217 22:25:42.377914 Running '/usr/bin/git checkout kernelci.org
218 22:25:42.596454 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 22:25:42.597479 uuid=1219904_1.6.2.4.5 testdef=None
220 22:25:42.597746 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 22:25:42.598350 start: 1.6.2.4.6 test-overlay (timeout 00:09:19) [common]
223 22:25:42.600401 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 22:25:42.601400 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:19) [common]
226 22:25:42.604218 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 22:25:42.604905 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:19) [common]
229 22:25:42.607607 runner path: /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/0/tests/1_kselftest-dt test_uuid 1219904_1.6.2.4.5
230 22:25:42.607823 BOARD='beaglebone-black'
231 22:25:42.607996 BRANCH='mainline'
232 22:25:42.608165 SKIPFILE='/dev/null'
233 22:25:42.608332 SKIP_INSTALL='True'
234 22:25:42.608496 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
235 22:25:42.608663 TST_CASENAME=''
236 22:25:42.608828 TST_CMDFILES='dt'
237 22:25:42.609024 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 22:25:42.609347 Creating lava-test-runner.conf files
240 22:25:42.609437 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1219904/lava-overlay-obwsxavv/lava-1219904/0 for stage 0
241 22:25:42.609562 - 0_timesync-off
242 22:25:42.609656 - 1_kselftest-dt
243 22:25:42.609789 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 22:25:42.609907 start: 1.6.2.5 compress-overlay (timeout 00:09:19) [common]
245 22:25:51.074677 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 22:25:51.074886 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
247 22:25:51.075033 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 22:25:51.075180 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
249 22:25:51.075325 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
250 22:25:51.198815 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 22:25:51.199123 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
252 22:25:51.199300 extracting modules file /var/lib/lava/dispatcher/tmp/1219904/tftp-deploy-u6vbidi_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1219904/extract-nfsrootfs-n430qnyz
253 22:25:51.506605 extracting modules file /var/lib/lava/dispatcher/tmp/1219904/tftp-deploy-u6vbidi_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1219904/extract-overlay-ramdisk-tcvzcw16/ramdisk
254 22:25:51.817172 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 22:25:51.817410 start: 1.6.5 apply-overlay-tftp (timeout 00:09:10) [common]
256 22:25:51.817545 [common] Applying overlay to NFS
257 22:25:51.817652 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1219904/compress-overlay-vgd8p8xk/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1219904/extract-nfsrootfs-n430qnyz
258 22:25:53.000833 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 22:25:53.001048 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
260 22:25:53.001176 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
261 22:25:53.001305 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 22:25:53.001425 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 22:25:53.001546 start: 1.6.7 configure-preseed-file (timeout 00:09:08) [common]
264 22:25:53.001662 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 22:25:53.001779 start: 1.6.8 compress-ramdisk (timeout 00:09:08) [common]
266 22:25:53.001880 Building ramdisk /var/lib/lava/dispatcher/tmp/1219904/extract-overlay-ramdisk-tcvzcw16/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1219904/extract-overlay-ramdisk-tcvzcw16/ramdisk
267 22:25:53.321986 >> 79013 blocks
268 22:25:55.459764 Adding RAMdisk u-boot header.
269 22:25:55.460040 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1219904/extract-overlay-ramdisk-tcvzcw16/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1219904/extract-overlay-ramdisk-tcvzcw16/ramdisk.cpio.gz.uboot
270 22:25:55.616001 output: Image Name:
271 22:25:55.616366 output: Created: Fri Nov 8 22:25:55 2024
272 22:25:55.616562 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 22:25:55.616778 output: Data Size: 15351952 Bytes = 14992.14 KiB = 14.64 MiB
274 22:25:55.616975 output: Load Address: 00000000
275 22:25:55.617164 output: Entry Point: 00000000
276 22:25:55.617352 output:
277 22:25:55.617657 rename /var/lib/lava/dispatcher/tmp/1219904/extract-overlay-ramdisk-tcvzcw16/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1219904/tftp-deploy-u6vbidi_/ramdisk/ramdisk.cpio.gz.uboot
278 22:25:55.618011 end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
279 22:25:55.618303 end: 1.6 prepare-tftp-overlay (duration 00:00:23) [common]
280 22:25:55.618591 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:06) [common]
281 22:25:55.618803 No LXC device requested
282 22:25:55.619059 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 22:25:55.619334 start: 1.8 deploy-device-env (timeout 00:09:06) [common]
284 22:25:55.619600 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 22:25:55.619811 Checking files for TFTP limit of 4294967296 bytes.
286 22:25:55.621103 end: 1 tftp-deploy (duration 00:00:54) [common]
287 22:25:55.621389 start: 2 uboot-action (timeout 00:05:00) [common]
288 22:25:55.621677 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 22:25:55.621949 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 22:25:55.622226 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 22:25:55.622635 substitutions:
292 22:25:55.622843 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 22:25:55.623064 - {DTB_ADDR}: 0x88000000
294 22:25:55.623281 - {DTB}: 1219904/tftp-deploy-u6vbidi_/dtb/am335x-boneblack.dtb
295 22:25:55.623498 - {INITRD}: 1219904/tftp-deploy-u6vbidi_/ramdisk/ramdisk.cpio.gz.uboot
296 22:25:55.623714 - {KERNEL_ADDR}: 0x82000000
297 22:25:55.623928 - {KERNEL}: 1219904/tftp-deploy-u6vbidi_/kernel/zImage
298 22:25:55.624142 - {LAVA_MAC}: None
299 22:25:55.624375 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1219904/extract-nfsrootfs-n430qnyz
300 22:25:55.624582 - {NFS_SERVER_IP}: 192.168.11.5
301 22:25:55.624820 - {PRESEED_CONFIG}: None
302 22:25:55.625072 - {PRESEED_LOCAL}: None
303 22:25:55.625305 - {RAMDISK_ADDR}: 0x83000000
304 22:25:55.625516 - {RAMDISK}: 1219904/tftp-deploy-u6vbidi_/ramdisk/ramdisk.cpio.gz.uboot
305 22:25:55.625725 - {ROOT_PART}: None
306 22:25:55.625933 - {ROOT}: None
307 22:25:55.626198 - {SERVER_IP}: 192.168.11.5
308 22:25:55.626409 - {TEE_ADDR}: 0x83000000
309 22:25:55.626616 - {TEE}: None
310 22:25:55.626824 Parsed boot commands:
311 22:25:55.627028 - setenv autoload no
312 22:25:55.627235 - setenv initrd_high 0xffffffff
313 22:25:55.627441 - setenv fdt_high 0xffffffff
314 22:25:55.627647 - dhcp
315 22:25:55.627853 - setenv serverip 192.168.11.5
316 22:25:55.628058 - tftp 0x82000000 1219904/tftp-deploy-u6vbidi_/kernel/zImage
317 22:25:55.628267 - tftp 0x83000000 1219904/tftp-deploy-u6vbidi_/ramdisk/ramdisk.cpio.gz.uboot
318 22:25:55.628479 - setenv initrd_size ${filesize}
319 22:25:55.628684 - tftp 0x88000000 1219904/tftp-deploy-u6vbidi_/dtb/am335x-boneblack.dtb
320 22:25:55.628862 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219904/extract-nfsrootfs-n430qnyz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 22:25:55.628953 - bootz 0x82000000 0x83000000 0x88000000
322 22:25:55.629066 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 22:25:55.629391 start: 2.3 connect-device (timeout 00:05:00) [common]
325 22:25:55.629484 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 22:25:55.988495 Setting prompt string to ['lava-test: # ']
327 22:25:55.988934 end: 2.3 connect-device (duration 00:00:00) [common]
328 22:25:55.989105 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 22:25:55.989281 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 22:25:55.989415 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 22:25:55.989756 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 22:25:56.355867 Returned 0 in 0 seconds
333 22:25:56.456763 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 22:25:56.457657 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 22:25:56.457976 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 22:25:56.458257 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 22:25:56.458507 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 22:25:56.459238 Trying 127.0.0.1...
340 22:25:56.459472 Connected to 127.0.0.1.
341 22:25:56.459693 Escape character is '^]'.
342 22:26:01.398817
343 22:26:01.402472 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 22:26:01.459067 Trying to boot from MMC2
345 22:26:01.507354 Loading Environment from EXT4... Card did not respond to voltage select!
346 22:26:01.574955
347 22:26:01.575284
348 22:26:01.580530 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 22:26:01.580815
350 22:26:01.585456 CPU : AM335X-GP rev 2.1
351 22:26:01.639488 I2C: ready
352 22:26:01.639838 DRAM: 512 MiB
353 22:26:01.693950 No match for driver 'omap_hsmmc'
354 22:26:01.699536 No match for driver 'omap_hsmmc'
355 22:26:01.699866 Some drivers were not found
356 22:26:01.705759 Reset Source: Power-on reset has occurred.
357 22:26:01.706042 RTC 32KCLK Source: External.
358 22:26:01.713327 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 22:26:01.726631 Loading Environment from EXT4... Card did not respond to voltage select!
360 22:26:01.791185 Board: BeagleBone Black
361 22:26:01.794975 <ethaddr> not set. Validating first E-fuse MAC
362 22:26:01.851755 BeagleBone Black:
363 22:26:01.852052 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 22:26:01.857397 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 22:26:01.863232 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 22:26:01.863513 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 22:26:01.868188 Net: eth0: MII MODE
368 22:26:01.877596 cpsw, usb_ether
369 22:26:01.877875 Press SPACE to abort autoboot in 2 seconds
370 22:26:01.928663 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 22:26:01.929033 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 22:26:01.929302 Setting prompt string to ['=> ']
373 22:26:01.929562 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 22:26:01.932848 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 22:26:01.933122 Sending with 10 millisecond of delay
377 22:26:03.067717 => setenv autoload no
378 22:26:03.078226 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 22:26:03.080565 setenv autoload no
380 22:26:03.081054 Sending with 10 millisecond of delay
382 22:26:04.878086 => setenv initrd_high 0xffffffff
383 22:26:04.888577 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 22:26:04.889064 setenv initrd_high 0xffffffff
385 22:26:04.889514 Sending with 10 millisecond of delay
387 22:26:06.505746 => setenv fdt_high 0xffffffff
388 22:26:06.516249 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 22:26:06.516736 setenv fdt_high 0xffffffff
390 22:26:06.517193 Sending with 10 millisecond of delay
392 22:26:06.808650 => dhcp
393 22:26:06.819146 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 22:26:06.819608 dhcp
395 22:26:06.819842 link up on port 0, speed 100, full duplex
396 22:26:06.820064 BOOTP broadcast 1
397 22:26:06.827483 DHCP client bound to address 192.168.11.3 (3 ms)
398 22:26:06.827972 Sending with 10 millisecond of delay
400 22:26:08.564445 => setenv serverip 192.168.11.5
401 22:26:08.575000 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 22:26:08.575458 setenv serverip 192.168.11.5
403 22:26:08.575921 Sending with 10 millisecond of delay
405 22:26:12.119187 => tftp 0x82000000 1219904/tftp-deploy-u6vbidi_/kernel/zImage
406 22:26:12.129722 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:43)
407 22:26:12.130197 tftp 0x82000000 1219904/tftp-deploy-u6vbidi_/kernel/zImage
408 22:26:12.130427 link up on port 0, speed 100, full duplex
409 22:26:12.130639 Using cpsw device
410 22:26:12.134090 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
411 22:26:12.139579 Filename '1219904/tftp-deploy-u6vbidi_/kernel/zImage'.
412 22:26:12.237164 Load address: 0x82000000
413 22:26:12.324286 Loading: *#################################################################
414 22:26:12.569899 #################################################################
415 22:26:12.679545 #################################################################
416 22:26:12.848938 #################################################################
417 22:26:13.025924 #################################################################
418 22:26:13.195043 #################################################################
419 22:26:13.364419 #################################################################
420 22:26:13.533644 #################################################################
421 22:26:13.704524 #################################################################
422 22:26:13.874012 #################################################################
423 22:26:14.048509 #################################################################
424 22:26:14.238668 #################################################################
425 22:26:14.331137 #########################################
426 22:26:14.331466 5.3 MiB/s
427 22:26:14.331690 done
428 22:26:14.334537 Bytes transferred = 12050944 (b7e200 hex)
429 22:26:14.335062 Sending with 10 millisecond of delay
431 22:26:18.841725 => tftp 0x83000000 1219904/tftp-deploy-u6vbidi_/ramdisk/ramdisk.cpio.gz.uboot
432 22:26:18.852212 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
433 22:26:18.852763 tftp 0x83000000 1219904/tftp-deploy-u6vbidi_/ramdisk/ramdisk.cpio.gz.uboot
434 22:26:18.853028 link up on port 0, speed 100, full duplex
435 22:26:18.853283 Using cpsw device
436 22:26:18.856637 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
437 22:26:18.870543 Filename '1219904/tftp-deploy-u6vbidi_/ramdisk/ramdisk.cpio.gz.uboot'.
438 22:26:18.870835 Load address: 0x83000000
439 22:26:19.050606 Loading: *#################################################################
440 22:26:19.215980 #################################################################
441 22:26:19.387348 #################################################################
442 22:26:19.562045 #################################################################
443 22:26:19.736703 #################################################################
444 22:26:19.933674 #################################################################
445 22:26:20.104658 #################################################################
446 22:26:20.269910 #################################################################
447 22:26:20.441961 #################################################################
448 22:26:20.616527 #################################################################
449 22:26:20.805676 #################################################################
450 22:26:20.979647 #################################################################
451 22:26:21.140613 #################################################################
452 22:26:21.326491 #################################################################
453 22:26:21.491801 #################################################################
454 22:26:21.659615 #################################################################
455 22:26:21.672459 ######
456 22:26:21.672753 5.2 MiB/s
457 22:26:21.672982 done
458 22:26:21.676168 Bytes transferred = 15352016 (ea40d0 hex)
459 22:26:21.676725 Sending with 10 millisecond of delay
461 22:26:23.533989 => setenv initrd_size ${filesize}
462 22:26:23.544498 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
463 22:26:23.544972 setenv initrd_size ${filesize}
464 22:26:23.545420 Sending with 10 millisecond of delay
466 22:26:27.751027 => tftp 0x88000000 1219904/tftp-deploy-u6vbidi_/dtb/am335x-boneblack.dtb
467 22:26:27.761513 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
468 22:26:27.761970 tftp 0x88000000 1219904/tftp-deploy-u6vbidi_/dtb/am335x-boneblack.dtb
469 22:26:27.762202 link up on port 0, speed 100, full duplex
470 22:26:27.762415 Using cpsw device
471 22:26:27.765842 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
472 22:26:27.779358 Filename '1219904/tftp-deploy-u6vbidi_/dtb/am335x-boneblack.dtb'.
473 22:26:27.779708 Load address: 0x88000000
474 22:26:27.794889 Loading: *#####
475 22:26:27.795171 4.5 MiB/s
476 22:26:27.795390 done
477 22:26:27.795597 Bytes transferred = 70568 (113a8 hex)
478 22:26:27.798412 Sending with 10 millisecond of delay
480 22:26:41.097124 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219904/extract-nfsrootfs-n430qnyz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 22:26:41.107657 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
482 22:26:41.108119 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219904/extract-nfsrootfs-n430qnyz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
483 22:26:41.108576 Sending with 10 millisecond of delay
485 22:26:43.447553 => bootz 0x82000000 0x83000000 0x88000000
486 22:26:43.458045 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
487 22:26:43.458366 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
488 22:26:43.458898 bootz 0x82000000 0x83000000 0x88000000
489 22:26:43.459140 ## Loading init Ramdisk from Legacy Image at 83000000 ...
490 22:26:43.459635 Image Name:
491 22:26:43.459925 Created: 2024-11-08 22:25:55 UTC
492 22:26:43.465281 Image Type: ARM Linux RAMDisk Image (uncompressed)
493 22:26:43.470760 Data Size: 15351952 Bytes = 14.6 MiB
494 22:26:43.470998 Load Address: 00000000
495 22:26:43.478082 Entry Point: 00000000
496 22:26:43.620447 Verifying Checksum ... OK
497 22:26:43.620771 ## Flattened Device Tree blob at 88000000
498 22:26:43.627043 Booting using the fdt blob at 0x88000000
499 22:26:43.631856 Using Device Tree in place at 88000000, end 880143a7
500 22:26:43.639510
501 22:26:43.639791 Starting kernel ...
502 22:26:43.640018
503 22:26:43.640556 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
504 22:26:43.640886 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
505 22:26:43.641138 Setting prompt string to ['Linux version [0-9]']
506 22:26:43.641384 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
507 22:26:43.641634 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
508 22:26:44.532307 [ 0.000000] Booting Linux on physical CPU 0x0
509 22:26:44.538204 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
510 22:26:44.538514 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 22:26:44.538775 Setting prompt string to []
512 22:26:44.539036 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 22:26:44.539286 Using line separator: #'\n'#
514 22:26:44.539502 No login prompt set.
515 22:26:44.539728 Parsing kernel messages
516 22:26:44.539934 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 22:26:44.540324 [login-action] Waiting for messages, (timeout 00:04:11)
518 22:26:44.549342 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j370017-arm-clang-15-multi-v7-defconfig-69vm9) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Fri Nov 8 21:58:42 UTC 2024
519 22:26:44.554970 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
520 22:26:44.566470 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
521 22:26:44.572222 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
522 22:26:44.577984 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
523 22:26:44.583713 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
524 22:26:44.590463 [ 0.000000] Memory policy: Data cache writeback
525 22:26:44.590743 [ 0.000000] efi: UEFI not found.
526 22:26:44.598066 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
527 22:26:44.603772 [ 0.000000] Zone ranges:
528 22:26:44.609425 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
529 22:26:44.615204 [ 0.000000] Normal empty
530 22:26:44.615459 [ 0.000000] HighMem empty
531 22:26:44.620953 [ 0.000000] Movable zone start for each node
532 22:26:44.621196 [ 0.000000] Early memory node ranges
533 22:26:44.632463 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
534 22:26:44.637742 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
535 22:26:44.656011 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 22:26:44.661523 [ 0.000000] AM335X ES2.1 (sgx neon)
537 22:26:44.673501 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
538 22:26:44.691212 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219904/extract-nfsrootfs-n430qnyz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 22:26:44.702679 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
540 22:26:44.708422 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
541 22:26:44.714155 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
542 22:26:44.724473 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
543 22:26:44.753718 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
544 22:26:44.759713 <6>[ 0.000000] trace event string verifier disabled
545 22:26:44.759957 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
546 22:26:44.765497 <6>[ 0.000000] rcu: RCU event tracing is enabled.
547 22:26:44.776837 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
548 22:26:44.782621 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
549 22:26:44.789891 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
550 22:26:44.804945 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
551 22:26:44.823211 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
552 22:26:44.829889 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
553 22:26:44.933647 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
554 22:26:44.945144 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
555 22:26:44.951896 <6>[ 0.008340] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
556 22:26:44.964939 <6>[ 0.019247] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
557 22:26:44.973036 <6>[ 0.034600] Console: colour dummy device 80x30
558 22:26:44.978956 Matched prompt #6: WARNING:
559 22:26:44.979248 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
560 22:26:44.984391 <3>[ 0.039596] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
561 22:26:44.990265 <3>[ 0.046584] This ensures that you still see kernel messages. Please
562 22:26:44.993449 <3>[ 0.053310] update your kernel commandline.
563 22:26:45.033516 <6>[ 0.057926] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
564 22:26:45.039263 <6>[ 0.096258] CPU: Testing write buffer coherency: ok
565 22:26:45.045310 <6>[ 0.101632] CPU0: Spectre v2: using BPIALL workaround
566 22:26:45.045591 <6>[ 0.107097] pid_max: default: 32768 minimum: 301
567 22:26:45.056777 <6>[ 0.112291] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 22:26:45.063635 <6>[ 0.120115] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 22:26:45.070886 <6>[ 0.129503] CPU0: thread -1, cpu 0, socket -1, mpidr 0
570 22:26:45.079385 <6>[ 0.136556] Setting up static identity map for 0x80300000 - 0x803000ac
571 22:26:45.085274 <6>[ 0.146395] rcu: Hierarchical SRCU implementation.
572 22:26:45.092822 <6>[ 0.151680] rcu: Max phase no-delay instances is 1000.
573 22:26:45.101899 <6>[ 0.163353] EFI services will not be available.
574 22:26:45.107758 <6>[ 0.168644] smp: Bringing up secondary CPUs ...
575 22:26:45.113493 <6>[ 0.173705] smp: Brought up 1 node, 1 CPU
576 22:26:45.119348 <6>[ 0.178105] SMP: Total of 1 processors activated (996.14 BogoMIPS).
577 22:26:45.125224 <6>[ 0.184875] CPU: All CPU(s) started in SVC mode.
578 22:26:45.145514 <6>[ 0.190079] Memory: 404428K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50620K reserved, 65536K cma-reserved, 0K highmem)
579 22:26:45.145767 <6>[ 0.206384] devtmpfs: initialized
580 22:26:45.168829 <6>[ 0.224498] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
581 22:26:45.180351 <6>[ 0.233115] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
582 22:26:45.186250 <6>[ 0.243579] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
583 22:26:45.197034 <6>[ 0.255872] pinctrl core: initialized pinctrl subsystem
584 22:26:45.206839 <6>[ 0.266937] DMI not present or invalid.
585 22:26:45.215237 <6>[ 0.272839] NET: Registered PF_NETLINK/PF_ROUTE protocol family
586 22:26:45.224652 <6>[ 0.281834] DMA: preallocated 256 KiB pool for atomic coherent allocations
587 22:26:45.240019 <6>[ 0.293544] thermal_sys: Registered thermal governor 'step_wise'
588 22:26:45.240254 <6>[ 0.293746] cpuidle: using governor menu
589 22:26:45.267756 <6>[ 0.329396] No ATAGs?
590 22:26:45.273873 <6>[ 0.332139] hw-breakpoint: debug architecture 0x4 unsupported.
591 22:26:45.284419 <6>[ 0.344395] Serial: AMBA PL011 UART driver
592 22:26:45.314596 <6>[ 0.376075] iommu: Default domain type: Translated
593 22:26:45.323514 <6>[ 0.381426] iommu: DMA domain TLB invalidation policy: strict mode
594 22:26:45.350317 <5>[ 0.410610] SCSI subsystem initialized
595 22:26:45.363997 <6>[ 0.420036] usbcore: registered new interface driver usbfs
596 22:26:45.370963 <6>[ 0.425994] usbcore: registered new interface driver hub
597 22:26:45.371210 <6>[ 0.431839] usbcore: registered new device driver usb
598 22:26:45.376689 <6>[ 0.438406] pps_core: LinuxPPS API ver. 1 registered
599 22:26:45.388185 <6>[ 0.443841] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
600 22:26:45.397010 <6>[ 0.453557] PTP clock support registered
601 22:26:45.397247 <6>[ 0.458006] EDAC MC: Ver: 3.0.0
602 22:26:45.451852 <6>[ 0.510744] scmi_core: SCMI protocol bus registered
603 22:26:45.457510 <6>[ 0.518917] vgaarb: loaded
604 22:26:45.469886 <6>[ 0.531680] clocksource: Switched to clocksource dmtimer
605 22:26:45.497624 <6>[ 0.558977] NET: Registered PF_INET protocol family
606 22:26:45.510351 <6>[ 0.564704] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
607 22:26:45.516192 <6>[ 0.573705] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
608 22:26:45.527580 <6>[ 0.582632] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
609 22:26:45.533330 <6>[ 0.590877] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
610 22:26:45.544953 <6>[ 0.599165] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
611 22:26:45.550815 <6>[ 0.606885] TCP: Hash tables configured (established 4096 bind 4096)
612 22:26:45.556563 <6>[ 0.613805] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
613 22:26:45.562433 <6>[ 0.620821] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
614 22:26:45.570029 <6>[ 0.628439] NET: Registered PF_UNIX/PF_LOCAL protocol family
615 22:26:45.662987 <6>[ 0.719054] RPC: Registered named UNIX socket transport module.
616 22:26:45.663293 <6>[ 0.725502] RPC: Registered udp transport module.
617 22:26:45.668826 <6>[ 0.730610] RPC: Registered tcp transport module.
618 22:26:45.674576 <6>[ 0.735737] RPC: Registered tcp-with-tls transport module.
619 22:26:45.687624 <6>[ 0.741666] RPC: Registered tcp NFSv4.1 backchannel transport module.
620 22:26:45.687862 <6>[ 0.748577] PCI: CLS 0 bytes, default 64
621 22:26:45.694781 <5>[ 0.754455] Initialise system trusted keyrings
622 22:26:45.716873 <6>[ 0.775508] Trying to unpack rootfs image as initramfs...
623 22:26:45.776469 <6>[ 0.832018] workingset: timestamp_bits=30 max_order=17 bucket_order=0
624 22:26:45.781259 <6>[ 0.839528] squashfs: version 4.0 (2009/01/31) Phillip Lougher
625 22:26:45.820965 <5>[ 0.882646] NFS: Registering the id_resolver key type
626 22:26:45.826836 <5>[ 0.888237] Key type id_resolver registered
627 22:26:45.832583 <5>[ 0.892929] Key type id_legacy registered
628 22:26:45.838328 <6>[ 0.897367] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
629 22:26:45.847874 <6>[ 0.904583] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
630 22:26:45.933464 <5>[ 0.995276] Key type asymmetric registered
631 22:26:45.939452 <5>[ 0.999803] Asymmetric key parser 'x509' registered
632 22:26:45.947938 <6>[ 1.005340] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
633 22:26:45.953697 <6>[ 1.013298] io scheduler mq-deadline registered
634 22:26:45.962376 <6>[ 1.018230] io scheduler kyber registered
635 22:26:45.962656 <6>[ 1.022703] io scheduler bfq registered
636 22:26:46.073980 <6>[ 1.131908] ledtrig-cpu: registered to indicate activity on CPUs
637 22:26:46.361981 <6>[ 1.419804] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
638 22:26:46.396308 <6>[ 1.457520] msm_serial: driver initialized
639 22:26:46.402168 <6>[ 1.462609] SuperH (H)SCI(F) driver initialized
640 22:26:46.408165 <6>[ 1.467746] STMicroelectronics ASC driver initialized
641 22:26:46.413345 <6>[ 1.473425] STM32 USART driver initialized
642 22:26:46.541427 <6>[ 1.602512] brd: module loaded
643 22:26:46.583730 <6>[ 1.644818] loop: module loaded
644 22:26:46.640048 <6>[ 1.700798] CAN device driver interface
645 22:26:46.646780 <6>[ 1.706103] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
646 22:26:46.652530 <6>[ 1.713222] e1000e: Intel(R) PRO/1000 Network Driver
647 22:26:46.658281 <6>[ 1.718611] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
648 22:26:46.664158 <6>[ 1.725079] igb: Intel(R) Gigabit Ethernet Network Driver
649 22:26:46.672406 <6>[ 1.730902] igb: Copyright (c) 2007-2014 Intel Corporation.
650 22:26:46.684408 <6>[ 1.740371] pegasus: Pegasus/Pegasus II USB Ethernet driver
651 22:26:46.690188 <6>[ 1.746545] usbcore: registered new interface driver pegasus
652 22:26:46.695919 <6>[ 1.752706] usbcore: registered new interface driver asix
653 22:26:46.701667 <6>[ 1.758560] usbcore: registered new interface driver ax88179_178a
654 22:26:46.707545 <6>[ 1.765149] usbcore: registered new interface driver cdc_ether
655 22:26:46.713309 <6>[ 1.771449] usbcore: registered new interface driver smsc75xx
656 22:26:46.719173 <6>[ 1.777679] usbcore: registered new interface driver smsc95xx
657 22:26:46.724833 <6>[ 1.783940] usbcore: registered new interface driver net1080
658 22:26:46.730714 <6>[ 1.790064] usbcore: registered new interface driver cdc_subset
659 22:26:46.736418 <6>[ 1.796487] usbcore: registered new interface driver zaurus
660 22:26:46.744109 <6>[ 1.802553] usbcore: registered new interface driver cdc_ncm
661 22:26:46.754308 <6>[ 1.812355] usbcore: registered new interface driver usb-storage
662 22:26:46.763736 <6>[ 1.823661] i2c_dev: i2c /dev entries driver
663 22:26:46.788736 <5>[ 1.842394] cpuidle: enable-method property 'ti,am3352' found operations
664 22:26:46.794428 <6>[ 1.851962] sdhci: Secure Digital Host Controller Interface driver
665 22:26:46.801918 <6>[ 1.858621] sdhci: Copyright(c) Pierre Ossman
666 22:26:46.809172 <6>[ 1.865117] Synopsys Designware Multimedia Card Interface Driver
667 22:26:46.814595 <6>[ 1.873117] sdhci-pltfm: SDHCI platform and OF driver helper
668 22:26:46.828732 <6>[ 1.883077] usbcore: registered new interface driver usbhid
669 22:26:46.829018 <6>[ 1.889108] usbhid: USB HID core driver
670 22:26:46.841481 <6>[ 1.900614] NET: Registered PF_INET6 protocol family
671 22:26:47.292021 <6>[ 2.353815] Segment Routing with IPv6
672 22:26:47.298014 <6>[ 2.357962] In-situ OAM (IOAM) with IPv6
673 22:26:47.304636 <6>[ 2.362516] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
674 22:26:47.310503 <6>[ 2.369813] NET: Registered PF_PACKET protocol family
675 22:26:47.316421 <6>[ 2.375400] can: controller area network core
676 22:26:47.322140 <6>[ 2.380226] NET: Registered PF_CAN protocol family
677 22:26:47.322420 <6>[ 2.385458] can: raw protocol
678 22:26:47.327878 <6>[ 2.388786] can: broadcast manager protocol
679 22:26:47.334384 <6>[ 2.393383] can: netlink gateway - max_hops=1
680 22:26:47.340503 <5>[ 2.398912] Key type dns_resolver registered
681 22:26:47.346880 <6>[ 2.403987] ThumbEE CPU extension supported.
682 22:26:47.347159 <5>[ 2.408679] Registering SWP/SWPB emulation handler
683 22:26:47.356550 <3>[ 2.414388] omap_voltage_late_init: Voltage driver support not added
684 22:26:47.572896 <5>[ 2.632354] Loading compiled-in X.509 certificates
685 22:26:47.712486 <6>[ 2.761289] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
686 22:26:47.719668 <6>[ 2.778037] pinctrl-single 44e10800.pinmux: 142 pins, size 568
687 22:26:47.746793 <3>[ 2.802585] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
688 22:26:47.947407 <3>[ 3.003112] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
689 22:26:48.152441 <6>[ 3.212599] OMAP GPIO hardware version 0.1
690 22:26:48.173901 <6>[ 3.231940] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
691 22:26:48.265895 <4>[ 3.323756] at24 2-0054: supply vcc not found, using dummy regulator
692 22:26:48.299651 <4>[ 3.357502] at24 2-0055: supply vcc not found, using dummy regulator
693 22:26:48.347425 <4>[ 3.405184] at24 2-0056: supply vcc not found, using dummy regulator
694 22:26:48.388560 <4>[ 3.446390] at24 2-0057: supply vcc not found, using dummy regulator
695 22:26:48.426931 <6>[ 3.485511] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
696 22:26:48.483902 <3>[ 3.538466] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
697 22:26:48.508875 <6>[ 3.559850] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 22:26:48.530526 <4>[ 3.587137] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
699 22:26:48.545647 <4>[ 3.602237] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
700 22:26:48.611611 <6>[ 3.672357] Freeing initrd memory: 14996K
701 22:26:48.619937 <6>[ 3.677894] omap_rng 48310000.rng: Random Number Generator ver. 20
702 22:26:48.644222 <5>[ 3.704925] random: crng init done
703 22:26:48.695131 <6>[ 3.751674] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
704 22:26:48.748584 <6>[ 3.804153] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
705 22:26:48.754328 <6>[ 3.814480] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
706 22:26:48.766198 <6>[ 3.821821] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
707 22:26:48.772076 <6>[ 3.829294] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
708 22:26:48.783449 <6>[ 3.837435] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
709 22:26:48.791100 <6>[ 3.849077] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
710 22:26:48.804178 <5>[ 3.858206] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
711 22:26:48.832701 <3>[ 3.888823] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
712 22:26:48.838499 <6>[ 3.897426] edma 49000000.dma: TI EDMA DMA engine driver
713 22:26:48.912178 <3>[ 3.967540] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
714 22:26:48.927547 <6>[ 3.982512] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
715 22:26:48.940394 <3>[ 3.999645] l3-aon-clkctrl:0000:0: failed to disable
716 22:26:48.994322 <6>[ 4.050308] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
717 22:26:49.000070 <6>[ 4.059827] printk: legacy console [ttyS0] enabled
718 22:26:49.005693 <6>[ 4.059827] printk: legacy console [ttyS0] enabled
719 22:26:49.011317 <6>[ 4.070162] printk: legacy bootconsole [omap8250] disabled
720 22:26:49.017295 <6>[ 4.070162] printk: legacy bootconsole [omap8250] disabled
721 22:26:49.047446 <4>[ 4.102529] tps65217-pmic: Failed to locate of_node [id: -1]
722 22:26:49.051138 <4>[ 4.109936] tps65217-bl: Failed to locate of_node [id: -1]
723 22:26:49.068215 <6>[ 4.130297] tps65217 0-0024: TPS65217 ID 0xe version 1.2
724 22:26:49.086687 <6>[ 4.137316] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
725 22:26:49.098435 <6>[ 4.151018] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
726 22:26:49.104238 <6>[ 4.162922] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
727 22:26:49.127335 <6>[ 4.183686] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
728 22:26:49.133227 <6>[ 4.192880] sdhci-omap 48060000.mmc: Got CD GPIO
729 22:26:49.141239 <4>[ 4.198033] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
730 22:26:49.156067 <4>[ 4.211816] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
731 22:26:49.162473 <4>[ 4.220472] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
732 22:26:49.172449 <4>[ 4.229139] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
733 22:26:49.271878 <6>[ 4.329332] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
734 22:26:49.311001 <6>[ 4.367586] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
735 22:26:49.356188 <6>[ 4.411880] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
736 22:26:49.362857 <6>[ 4.420716] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
737 22:26:49.431552 <6>[ 4.483060] mmc1: new high speed MMC card at address 0001
738 22:26:49.431679 <6>[ 4.491531] mmcblk1: mmc1:0001 M62704 3.56 GiB
739 22:26:49.443381 <6>[ 4.502836] mmcblk1: p1
740 22:26:49.451436 <6>[ 4.508169] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
741 22:26:49.463088 <6>[ 4.515927] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
742 22:26:49.467606 <6>[ 4.527170] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
743 22:26:49.485005 <6>[ 4.543095] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
744 22:26:52.656422 <6>[ 7.712721] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
745 22:26:52.729945 <5>[ 7.751770] Sending DHCP requests ., OK
746 22:26:52.741299 <6>[ 7.796191] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.3
747 22:26:52.741577 <6>[ 7.804424] IP-Config: Complete:
748 22:26:52.752546 <6>[ 7.807962] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.3, mask=255.255.255.0, gw=192.168.11.1
749 22:26:52.758286 <6>[ 7.818585] host=192.168.11.3, domain=usen.ad.jp, nis-domain=(none)
750 22:26:52.770576 <6>[ 7.825674] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
751 22:26:52.770853 <6>[ 7.825710] nameserver0=192.168.11.1
752 22:26:52.776784 <6>[ 7.838037] clk: Disabling unused clocks
753 22:26:52.783335 <6>[ 7.842813] PM: genpd: Disabling unused power domains
754 22:26:52.801410 <6>[ 7.859960] Freeing unused kernel image (initmem) memory: 2048K
755 22:26:52.808966 <6>[ 7.869791] Run /init as init process
756 22:26:52.832404 Loading, please wait...
757 22:26:52.910004 Starting systemd-udevd version 252.22-1~deb12u1
758 22:26:55.978858 <4>[ 11.033725] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
759 22:26:56.146263 <4>[ 11.201121] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 22:26:56.304820 <6>[ 11.367176] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
761 22:26:56.315715 <6>[ 11.373009] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
762 22:26:56.581476 <6>[ 11.642254] hub 1-0:1.0: USB hub found
763 22:26:56.601124 <6>[ 11.661885] hub 1-0:1.0: 1 port detected
764 22:26:56.723185 <6>[ 11.783730] tda998x 0-0070: found TDA19988
765 22:26:59.819333 Begin: Loading essential drivers ... done.
766 22:26:59.825841 Begin: Running /scripts/init-premount ... done.
767 22:26:59.837068 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
768 22:26:59.842656 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
769 22:26:59.846946 Device /sys/class/net/eth0 found
770 22:26:59.847178 done.
771 22:26:59.920671 Begin: Waiting up to 180 secs for any network device to become available ... done.
772 22:27:00.005560 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
773 22:27:00.005893 IP-Config: eth0 guessed broadcast address 192.168.11.255
774 22:27:00.011201 IP-Config: eth0 complete (dhcp from 192.168.11.1):
775 22:27:00.022315 address: 192.168.11.3 broadcast: 192.168.11.255 netmask: 255.255.255.0
776 22:27:00.027894 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
777 22:27:00.033523 domain : usen.ad.jp
778 22:27:00.038423 rootserver: 192.168.11.1 rootpath:
779 22:27:00.038701 filename :
780 22:27:00.122678 done.
781 22:27:00.132329 Begin: Running /scripts/nfs-bottom ... done.
782 22:27:00.203066 Begin: Running /scripts/init-bottom ... done.
783 22:27:01.730006 <30>[ 16.788233] systemd[1]: System time before build time, advancing clock.
784 22:27:01.889971 <30>[ 16.921999] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 22:27:01.898496 <30>[ 16.958505] systemd[1]: Detected architecture arm.
786 22:27:01.910812
787 22:27:01.911090 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 22:27:01.911320
789 22:27:01.932423 <30>[ 16.991207] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 22:27:04.214577 <30>[ 19.272370] systemd[1]: Queued start job for default target graphical.target.
791 22:27:04.231881 <30>[ 19.287452] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 22:27:04.239430 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 22:27:04.272788 <30>[ 19.327736] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 22:27:04.280058 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 22:27:04.309797 <30>[ 19.364479] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 22:27:04.317097 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 22:27:04.350393 <30>[ 19.405497] systemd[1]: Created slice user.slice - User and Session Slice.
798 22:27:04.357069 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 22:27:04.382545 <30>[ 19.432932] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 22:27:04.388608 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 22:27:04.406572 <30>[ 19.462808] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 22:27:04.415610 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 22:27:04.447437 <30>[ 19.492794] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 22:27:04.454008 <30>[ 19.513277] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 22:27:04.462487 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 22:27:04.485691 <30>[ 19.542159] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 22:27:04.493875 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 22:27:04.516437 <30>[ 19.572522] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 22:27:04.524824 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 22:27:04.546188 <30>[ 19.602605] systemd[1]: Reached target paths.target - Path Units.
811 22:27:04.551231 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 22:27:04.576114 <30>[ 19.632433] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 22:27:04.583553 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 22:27:04.605827 <30>[ 19.662193] systemd[1]: Reached target slices.target - Slice Units.
815 22:27:04.611242 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 22:27:04.636103 <30>[ 19.692475] systemd[1]: Reached target swap.target - Swaps.
817 22:27:04.640168 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 22:27:04.666990 <30>[ 19.723572] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 22:27:04.679476 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 22:27:04.706948 <30>[ 19.763125] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 22:27:04.715318 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 22:27:04.798597 <30>[ 19.850068] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 22:27:04.811537 <30>[ 19.867557] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 22:27:04.819949 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 22:27:04.848088 <30>[ 19.903477] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 22:27:04.855363 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 22:27:04.879442 <30>[ 19.935380] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 22:27:04.887595 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 22:27:04.911096 <30>[ 19.966910] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 22:27:04.916594 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 22:27:04.950386 <30>[ 20.005150] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 22:27:04.957777 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 22:27:04.983153 <30>[ 20.033476] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 22:27:04.999698 <30>[ 20.049983] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 22:27:05.050621 <30>[ 20.107658] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 22:27:05.076609 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 22:27:05.125636 <30>[ 20.182553] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 22:27:05.150034 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 22:27:05.226891 <30>[ 20.282929] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 22:27:05.248705 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 22:27:05.307006 <30>[ 20.363556] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 22:27:05.327251 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 22:27:05.386110 <30>[ 20.443137] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 22:27:05.414015 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 22:27:05.466586 <30>[ 20.522946] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 22:27:05.473536 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 22:27:05.509587 <30>[ 20.565867] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 22:27:05.537887 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 22:27:05.598132 <30>[ 20.655468] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 22:27:05.618222 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 22:27:05.677163 <30>[ 20.734455] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 22:27:05.706097 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 22:27:05.732095 <28>[ 20.784160] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 22:27:05.745222 <28>[ 20.801462] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 22:27:05.777457 <30>[ 20.835280] systemd[1]: Starting systemd-journald.service - Journal Service...
856 22:27:05.794748 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 22:27:05.866223 <30>[ 20.923267] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 22:27:05.886982 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 22:27:05.937664 <30>[ 20.994871] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 22:27:05.984984 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 22:27:06.049224 <30>[ 21.104955] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 22:27:06.096106 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 22:27:06.152454 <30>[ 21.209004] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 22:27:06.207676 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 22:27:06.287097 <30>[ 21.344512] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 22:27:06.335543 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 22:27:06.346932 <30>[ 21.404253] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 22:27:06.385700 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 22:27:06.409969 <30>[ 21.466111] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 22:27:06.465217 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 22:27:06.587835 <30>[ 21.645852] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 22:27:06.625478 <30>[ 21.682353] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 22:27:06.654835 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 22:27:06.676483 <30>[ 21.734612] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
875 22:27:06.706236 <30>[ 21.763431] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
876 22:27:06.735713 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 22:27:06.757189 <30>[ 21.813544] systemd[1]: Started systemd-journald.service - Journal Service.
878 22:27:06.763973 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
879 22:27:06.796857 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
880 22:27:06.828454 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
881 22:27:06.857079 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
882 22:27:06.881699 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
883 22:27:06.915992 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
884 22:27:06.939321 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
885 22:27:06.958460 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
886 22:27:06.985587 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
887 22:27:07.045592 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
888 22:27:07.116873 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
889 22:27:07.154842 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
890 22:27:07.228465 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
891 22:27:07.329204 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
892 22:27:07.458444 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
893 22:27:07.490583 <46>[ 22.547825] systemd-journald[162]: Received client request to flush runtime journal.
894 22:27:07.600894 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
895 22:27:08.456390 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
896 22:27:08.536629 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
897 22:27:08.607661 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
898 22:27:09.319752 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
899 22:27:09.418747 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
900 22:27:09.448214 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
901 22:27:09.465597 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
902 22:27:09.536042 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
903 22:27:09.595302 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
904 22:27:10.577576 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
905 22:27:10.647767 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
906 22:27:10.894683 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
907 22:27:10.985754 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
908 22:27:11.053634 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
909 22:27:13.090868 <5>[ 28.148472] cfg80211: Loading compiled-in X.509 certificates for regulatory database
910 22:27:13.126222 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
911 22:27:13.526217 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
912 22:27:14.551548 <5>[ 29.611333] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
913 22:27:14.631625 <5>[ 29.686624] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
914 22:27:14.637498 <4>[ 29.696794] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
915 22:27:14.645262 <6>[ 29.705948] cfg80211: failed to load regulatory.db
916 22:27:14.684633 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
917 22:27:16.233411 <46>[ 31.277550] systemd-journald[162]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
918 22:27:16.240343 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
919 22:27:16.264156 <46>[ 31.313830] systemd-journald[162]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
920 22:27:16.273809 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
921 22:27:25.068324 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
922 22:27:25.096548 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
923 22:27:25.117403 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
924 22:27:25.140387 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
925 22:27:25.205572 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
926 22:27:25.257794 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
927 22:27:25.318046 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
928 22:27:25.377775 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
929 22:27:25.432291 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
930 22:27:25.464744 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
931 22:27:25.492160 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
932 22:27:25.520956 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
933 22:27:25.562103 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
934 22:27:25.615602 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
935 22:27:25.649249 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
936 22:27:25.683364 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
937 22:27:25.719226 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
938 22:27:25.763528 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
939 22:27:25.786946 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
940 22:27:25.805820 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
941 22:27:25.835879 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
942 22:27:25.855900 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
943 22:27:25.878181 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
944 22:27:25.956506 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
945 22:27:25.996048 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
946 22:27:26.081601 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
947 22:27:26.179766 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
948 22:27:26.245019 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
949 22:27:26.279884 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
950 22:27:26.299507 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
951 22:27:26.498347 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
952 22:27:26.565214 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
953 22:27:26.627767 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
954 22:27:26.645867 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
955 22:27:26.674125 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
956 22:27:26.901975 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
957 22:27:27.276452 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
958 22:27:27.328146 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
959 22:27:27.371374 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
960 22:27:27.464776 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
961 22:27:27.636043 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
962 22:27:27.767898
963 22:27:27.768220 Debian GNU/Linux 12 deb
964 22:27:27.768479
965 22:27:27.772848 debian-bookworm-armhf login: root (automatic login)
966 22:27:27.773082
967 22:27:28.078107 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Fri Nov 8 21:58:42 UTC 2024 armv7l
968 22:27:28.078460
969 22:27:28.083720 The programs included with the Debian GNU/Linux system are free software;
970 22:27:28.089344 the exact distribution terms for each program are described in the
971 22:27:28.095001 individual files in /usr/share/doc/*/copyright.
972 22:27:28.095257
973 22:27:28.102931 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
974 22:27:28.103167 permitted by applicable law.
975 22:27:32.740343 Unable to match end of the kernel message
977 22:27:32.741169 Setting prompt string to ['/ #']
978 22:27:32.741476 end: 2.4.4.1 login-action (duration 00:00:48) [common]
980 22:27:32.742173 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
981 22:27:32.742468 start: 2.4.5 expect-shell-connection (timeout 00:03:23) [common]
982 22:27:32.742710 Setting prompt string to ['/ #']
983 22:27:32.742927 Forcing a shell prompt, looking for ['/ #']
985 22:27:32.793463 / #
986 22:27:32.793844 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
987 22:27:32.794097 Waiting using forced prompt support (timeout 00:02:30)
988 22:27:32.801447
989 22:27:32.801984 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
990 22:27:32.802289 start: 2.4.6 export-device-env (timeout 00:03:23) [common]
991 22:27:32.802544 Sending with 10 millisecond of delay
993 22:27:37.851084 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1219904/extract-nfsrootfs-n430qnyz'
994 22:27:37.861671 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1219904/extract-nfsrootfs-n430qnyz'
995 22:27:37.862370 Sending with 10 millisecond of delay
997 22:27:40.020600 / # export NFS_SERVER_IP='192.168.11.5'
998 22:27:40.031193 export NFS_SERVER_IP='192.168.11.5'
999 22:27:40.031787 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1000 22:27:40.032102 end: 2.4 uboot-commands (duration 00:01:44) [common]
1001 22:27:40.032413 end: 2 uboot-action (duration 00:01:44) [common]
1002 22:27:40.032736 start: 3 lava-test-retry (timeout 00:07:21) [common]
1003 22:27:40.033062 start: 3.1 lava-test-shell (timeout 00:07:21) [common]
1004 22:27:40.033311 Using namespace: common
1006 22:27:40.134026 / # #
1007 22:27:40.134403 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1008 22:27:40.138792 #
1009 22:27:40.144642 Using /lava-1219904
1011 22:27:40.245396 / # export SHELL=/bin/bash
1012 22:27:40.256356 export SHELL=/bin/bash
1014 22:27:40.369638 / # . /lava-1219904/environment
1015 22:27:40.374475 . /lava-1219904/environment
1017 22:27:40.487973 / # /lava-1219904/bin/lava-test-runner /lava-1219904/0
1018 22:27:40.488442 Test shell timeout: 10s (minimum of the action and connection timeout)
1019 22:27:40.492900 /lava-1219904/bin/lava-test-runner /lava-1219904/0
1020 22:27:40.915700 + export TESTRUN_ID=0_timesync-off
1021 22:27:40.923701 + TESTRUN_ID=0_timesync-off
1022 22:27:40.923987 + cd /lava-1219904/0/tests/0_timesync-off
1023 22:27:40.924220 ++ cat uuid
1024 22:27:40.941046 + UUID=1219904_1.6.2.4.1
1025 22:27:40.941327 + set +x
1026 22:27:40.946644 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1219904_1.6.2.4.1>
1027 22:27:40.947151 Received signal: <STARTRUN> 0_timesync-off 1219904_1.6.2.4.1
1028 22:27:40.947397 Starting test lava.0_timesync-off (1219904_1.6.2.4.1)
1029 22:27:40.947676 Skipping test definition patterns.
1030 22:27:40.949734 + systemctl stop systemd-timesyncd
1031 22:27:41.265199 + set +x
1032 22:27:41.265691 Received signal: <ENDRUN> 0_timesync-off 1219904_1.6.2.4.1
1033 22:27:41.265958 Ending use of test pattern.
1034 22:27:41.266182 Ending test lava.0_timesync-off (1219904_1.6.2.4.1), duration 0.32
1036 22:27:41.268330 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1219904_1.6.2.4.1>
1037 22:27:41.436617 + export TESTRUN_ID=1_kselftest-dt
1038 22:27:41.444639 + TESTRUN_ID=1_kselftest-dt
1039 22:27:41.444941 + cd /lava-1219904/0/tests/1_kselftest-dt
1040 22:27:41.445174 ++ cat uuid
1041 22:27:41.462372 + UUID=1219904_1.6.2.4.5
1042 22:27:41.462682 + set +x
1043 22:27:41.468131 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1219904_1.6.2.4.5>
1044 22:27:41.468500 + cd ./automated/linux/kselftest/
1045 22:27:41.469010 Received signal: <STARTRUN> 1_kselftest-dt 1219904_1.6.2.4.5
1046 22:27:41.469278 Starting test lava.1_kselftest-dt (1219904_1.6.2.4.5)
1047 22:27:41.469598 Skipping test definition patterns.
1048 22:27:41.496678 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1049 22:27:41.623800 INFO: install_deps skipped
1050 22:27:42.284150 --2024-11-08 22:27:42-- http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1051 22:27:42.304073 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1052 22:27:42.418764 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1053 22:27:42.530523 HTTP request sent, awaiting response... 200 OK
1054 22:27:42.530885 Length: 2542152 (2.4M) [application/octet-stream]
1055 22:27:42.536012 Saving to: 'kselftest_armhf.tar.gz'
1056 22:27:42.536264
1057 22:27:44.280586 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 2%[ ] 49.92K 224KB/s kselftest_armhf.tar 7%[> ] 194.76K 431KB/s kselftest_armhf.tar 26%[====> ] 656.01K 734KB/s kselftest_armhf.tar 83%[===============> ] 2.03M 1.76MB/s kselftest_armhf.tar 94%[=================> ] 2.29M 1.63MB/s kselftest_armhf.tar 95%[==================> ] 2.32M 1.42MB/s kselftest_armhf.tar 100%[===================>] 2.42M 1.39MB/s in 1.7s
1058 22:27:44.280964
1059 22:27:44.596416 2024-11-08 22:27:44 (1.39 MB/s) - 'kselftest_armhf.tar.gz' saved [2542152/2542152]
1060 22:27:44.596823
1061 22:28:05.178660 skiplist:
1062 22:28:05.179035 ========================================
1063 22:28:05.184414 ========================================
1064 22:28:05.296869 dt:test_unprobed_devices.sh
1065 22:28:05.330454 ============== Tests to run ===============
1066 22:28:05.340532 dt:test_unprobed_devices.sh
1067 22:28:05.344427 ===========End Tests to run ===============
1068 22:28:05.354586 shardfile-dt pass
1069 22:28:05.586133 <12>[ 80.649499] kselftest: Running tests in dt
1070 22:28:05.615595 TAP version 13
1071 22:28:05.638876 1..1
1072 22:28:05.695395 # timeout set to 45
1073 22:28:05.695672 # selftests: dt: test_unprobed_devices.sh
1074 22:28:06.488304 # TAP version 13
1075 22:28:32.500564 # 1..257
1076 22:28:32.683163 # ok 1 / # SKIP
1077 22:28:32.706120 # ok 2 /clk_mcasp0
1078 22:28:32.789292 # ok 3 /clk_mcasp0_fixed # SKIP
1079 22:28:32.864828 # ok 4 /cpus/cpu@0 # SKIP
1080 22:28:32.936725 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1081 22:28:32.962360 # ok 6 /fixedregulator0
1082 22:28:32.979783 # ok 7 /leds
1083 22:28:33.003944 # ok 8 /ocp
1084 22:28:33.032443 # ok 9 /ocp/interconnect@44c00000
1085 22:28:33.052222 # ok 10 /ocp/interconnect@44c00000/segment@0
1086 22:28:33.081557 # ok 11 /ocp/interconnect@44c00000/segment@100000
1087 22:28:33.107543 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1088 22:28:33.179703 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1089 22:28:33.204686 # ok 14 /ocp/interconnect@44c00000/segment@200000
1090 22:28:33.233852 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1091 22:28:33.340417 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1092 22:28:33.417420 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1093 22:28:33.494128 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1094 22:28:33.569768 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1095 22:28:33.646255 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1096 22:28:33.726371 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1097 22:28:33.801241 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1098 22:28:33.874507 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1099 22:28:33.950110 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1100 22:28:34.026792 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1101 22:28:34.102729 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1102 22:28:34.179472 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1103 22:28:34.256375 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1104 22:28:34.336136 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1105 22:28:34.407343 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1106 22:28:34.484609 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1107 22:28:34.560831 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1108 22:28:34.636843 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1109 22:28:34.717229 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1110 22:28:34.791636 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1111 22:28:34.865575 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1112 22:28:34.942591 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1113 22:28:35.018969 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1114 22:28:35.095471 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1115 22:28:35.171815 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1116 22:28:35.247311 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1117 22:28:35.325817 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1118 22:28:35.401701 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1119 22:28:35.478562 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1120 22:28:35.554553 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1121 22:28:35.630428 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1122 22:28:35.707186 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1123 22:28:35.787541 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1124 22:28:35.859666 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1125 22:28:35.936840 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1126 22:28:36.013566 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1127 22:28:36.090912 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1128 22:28:36.169342 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1129 22:28:36.249402 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1130 22:28:36.325022 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1131 22:28:36.401146 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1132 22:28:36.477289 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1133 22:28:36.552572 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1134 22:28:36.627832 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1135 22:28:36.703261 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1136 22:28:36.778765 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1137 22:28:36.855232 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1138 22:28:36.930697 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1139 22:28:37.007219 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1140 22:28:37.082276 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1141 22:28:37.158871 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1142 22:28:37.235493 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1143 22:28:37.308993 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1144 22:28:37.384289 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1145 22:28:37.459518 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1146 22:28:37.535710 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1147 22:28:37.611197 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1148 22:28:37.687063 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1149 22:28:37.767678 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1150 22:28:37.839530 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1151 22:28:37.916262 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1152 22:28:37.996475 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1153 22:28:38.068906 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1154 22:28:38.145206 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1155 22:28:38.221079 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1156 22:28:38.299199 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1157 22:28:38.375195 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1158 22:28:38.452942 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1159 22:28:38.526834 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1160 22:28:38.603983 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1161 22:28:38.680141 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1162 22:28:38.756407 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1163 22:28:38.832255 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1164 22:28:38.910210 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1165 22:28:38.987856 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1166 22:28:39.062231 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1167 22:28:39.140066 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1168 22:28:39.216383 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1169 22:28:39.293671 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1170 22:28:39.314411 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1171 22:28:39.340570 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1172 22:28:39.365182 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1173 22:28:39.396673 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1174 22:28:39.419710 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1175 22:28:39.445063 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1176 22:28:39.466753 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1177 22:28:39.494864 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1178 22:28:39.606871 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1179 22:28:39.630350 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1180 22:28:39.653417 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1181 22:28:39.677692 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1182 22:28:39.791483 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1183 22:28:39.869147 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1184 22:28:39.946147 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1185 22:28:40.025533 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1186 22:28:40.098770 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1187 22:28:40.176443 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1188 22:28:40.254760 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1189 22:28:40.330084 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1190 22:28:40.406776 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1191 22:28:40.485427 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1192 22:28:40.559680 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1193 22:28:40.637070 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1194 22:28:40.714207 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1195 22:28:40.791016 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1196 22:28:40.871398 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1197 22:28:40.944277 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1198 22:28:40.970001 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1199 22:28:41.041292 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1200 22:28:41.113522 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1201 22:28:41.189269 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1202 22:28:41.216900 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1203 22:28:41.289734 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1204 22:28:41.311740 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1205 22:28:41.386970 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1206 22:28:41.410608 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1207 22:28:41.439212 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1208 22:28:41.459116 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1209 22:28:41.484551 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1210 22:28:41.507414 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1211 22:28:41.537469 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1212 22:28:41.560843 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1213 22:28:41.642656 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1214 22:28:41.660371 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1215 22:28:41.689259 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1216 22:28:41.765084 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1217 22:28:41.836615 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1218 22:28:41.864011 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1219 22:28:41.966498 # not ok 144 /ocp/interconnect@47c00000
1220 22:28:42.043033 # not ok 145 /ocp/interconnect@47c00000/segment@0
1221 22:28:42.064908 # ok 146 /ocp/interconnect@48000000
1222 22:28:42.088358 # ok 147 /ocp/interconnect@48000000/segment@0
1223 22:28:42.116191 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1224 22:28:42.144987 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1225 22:28:42.168181 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1226 22:28:42.189164 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1227 22:28:42.213531 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1228 22:28:42.238202 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1229 22:28:42.260631 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1230 22:28:42.336500 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1231 22:28:42.413631 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1232 22:28:42.436327 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1233 22:28:42.466068 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1234 22:28:42.488235 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1235 22:28:42.510834 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1236 22:28:42.538203 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1237 22:28:42.564971 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1238 22:28:42.588210 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1239 22:28:42.611898 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1240 22:28:42.638436 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1241 22:28:42.659973 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1242 22:28:42.683916 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1243 22:28:42.715701 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1244 22:28:42.733719 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1245 22:28:42.761112 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1246 22:28:42.787082 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1247 22:28:42.809208 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1248 22:28:42.836461 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1249 22:28:42.859244 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1250 22:28:42.884215 # ok 175 /ocp/interconnect@48000000/segment@100000
1251 22:28:42.908733 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1252 22:28:42.931401 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1253 22:28:43.007468 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1254 22:28:43.084989 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1255 22:28:43.159462 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1256 22:28:43.237441 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1257 22:28:43.313599 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1258 22:28:43.391392 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1259 22:28:43.466728 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1260 22:28:43.549906 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1261 22:28:43.566387 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1262 22:28:43.591030 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1263 22:28:43.615323 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1264 22:28:43.644365 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1265 22:28:43.665268 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1266 22:28:43.691103 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1267 22:28:43.718650 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1268 22:28:43.741126 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1269 22:28:43.765263 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1270 22:28:43.794395 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1271 22:28:43.815261 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1272 22:28:43.845407 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1273 22:28:43.866890 # ok 198 /ocp/interconnect@48000000/segment@200000
1274 22:28:43.892145 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1275 22:28:43.966196 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1276 22:28:43.987515 # ok 201 /ocp/interconnect@48000000/segment@300000
1277 22:28:44.013592 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1278 22:28:44.038539 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1279 22:28:44.068136 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1280 22:28:44.088526 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1281 22:28:44.116838 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1282 22:28:44.138507 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1283 22:28:44.213977 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1284 22:28:44.233148 # ok 209 /ocp/interconnect@4a000000
1285 22:28:44.262520 # ok 210 /ocp/interconnect@4a000000/segment@0
1286 22:28:44.288377 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1287 22:28:44.314294 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1288 22:28:44.336385 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1289 22:28:44.358914 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1290 22:28:44.439251 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1291 22:28:44.546967 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1292 22:28:44.623994 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1293 22:28:44.738660 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1294 22:28:44.810389 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1295 22:28:44.884078 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1296 22:28:44.990104 # not ok 221 /ocp/interconnect@4b140000
1297 22:28:45.066912 # not ok 222 /ocp/interconnect@4b140000/segment@0
1298 22:28:45.146860 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1299 22:28:45.164831 # ok 224 /ocp/target-module@40300000
1300 22:28:45.189364 # ok 225 /ocp/target-module@40300000/sram@0
1301 22:28:45.272474 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1302 22:28:45.343914 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1303 22:28:45.370631 # ok 228 /ocp/target-module@47400000
1304 22:28:45.396382 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1305 22:28:45.416780 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1306 22:28:45.444130 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1307 22:28:45.466504 # ok 232 /ocp/target-module@47400000/usb@1400
1308 22:28:45.487127 # ok 233 /ocp/target-module@47400000/usb@1800
1309 22:28:45.509876 # ok 234 /ocp/target-module@47810000
1310 22:28:45.533126 # ok 235 /ocp/target-module@49000000
1311 22:28:45.557749 # ok 236 /ocp/target-module@49000000/dma@0
1312 22:28:45.584959 # ok 237 /ocp/target-module@49800000
1313 22:28:45.606123 # ok 238 /ocp/target-module@49800000/dma@0
1314 22:28:45.632500 # ok 239 /ocp/target-module@49900000
1315 22:28:45.656129 # ok 240 /ocp/target-module@49900000/dma@0
1316 22:28:45.681247 # ok 241 /ocp/target-module@49a00000
1317 22:28:45.704623 # ok 242 /ocp/target-module@49a00000/dma@0
1318 22:28:45.725904 # ok 243 /ocp/target-module@4c000000
1319 22:28:45.800956 # not ok 244 /ocp/target-module@4c000000/emif@0
1320 22:28:45.823365 # ok 245 /ocp/target-module@50000000
1321 22:28:45.847239 # ok 246 /ocp/target-module@53100000
1322 22:28:45.926607 # not ok 247 /ocp/target-module@53100000/sham@0
1323 22:28:45.945859 # ok 248 /ocp/target-module@53500000
1324 22:28:46.026518 # not ok 249 /ocp/target-module@53500000/aes@0
1325 22:28:46.044868 # ok 250 /ocp/target-module@56000000
1326 22:28:46.163242 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1327 22:28:46.230850 # ok 252 /opp-table # SKIP
1328 22:28:46.310474 # ok 253 /soc # SKIP
1329 22:28:46.332917 # ok 254 /sound
1330 22:28:46.351970 # ok 255 /target-module@4b000000
1331 22:28:46.383591 # ok 256 /target-module@4b000000/target-module@140000
1332 22:28:46.401049 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1333 22:28:46.409336 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1334 22:28:46.418008 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1335 22:28:48.588372 dt_test_unprobed_devices_sh_ skip
1336 22:28:48.593916 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1337 22:28:48.599501 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1338 22:28:48.599772 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1339 22:28:48.605050 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1340 22:28:48.610642 dt_test_unprobed_devices_sh_fixedregulator0 pass
1341 22:28:48.616253 dt_test_unprobed_devices_sh_leds pass
1342 22:28:48.616524 dt_test_unprobed_devices_sh_ocp pass
1343 22:28:48.621876 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1344 22:28:48.627530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1345 22:28:48.633154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1346 22:28:48.644389 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1347 22:28:48.649880 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1348 22:28:48.655683 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1349 22:28:48.666778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1350 22:28:48.672374 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1351 22:28:48.683633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1352 22:28:48.694759 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1353 22:28:48.706009 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1354 22:28:48.711727 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1355 22:28:48.722865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1356 22:28:48.734000 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1357 22:28:48.745254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1358 22:28:48.756497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1359 22:28:48.762125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1360 22:28:48.773241 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1361 22:28:48.784491 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1362 22:28:48.795743 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1363 22:28:48.806866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1364 22:28:48.812495 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1365 22:28:48.823603 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1366 22:28:48.834856 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1367 22:28:48.846006 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1368 22:28:48.851598 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1369 22:28:48.862881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1370 22:28:48.874002 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1371 22:28:48.885251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1372 22:28:48.896372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1373 22:28:48.902004 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1374 22:28:48.913252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1375 22:28:48.924372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1376 22:28:48.935626 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1377 22:28:48.946873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1378 22:28:48.957998 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1379 22:28:48.969250 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1380 22:28:48.980344 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1381 22:28:48.991620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1382 22:28:49.002745 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1383 22:28:49.013997 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1384 22:28:49.025122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1385 22:28:49.036371 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1386 22:28:49.047620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1387 22:28:49.058745 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1388 22:28:49.070042 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1389 22:28:49.081121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1390 22:28:49.092368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1391 22:28:49.103617 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1392 22:28:49.114867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1393 22:28:49.125994 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1394 22:28:49.137241 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1395 22:28:49.148488 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1396 22:28:49.159741 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1397 22:28:49.170864 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1398 22:28:49.182114 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1399 22:28:49.187740 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1400 22:28:49.198990 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1401 22:28:49.210154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1402 22:28:49.221348 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1403 22:28:49.232551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1404 22:28:49.243677 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1405 22:28:49.254925 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1406 22:28:49.266175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1407 22:28:49.277295 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1408 22:28:49.288588 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1409 22:28:49.299724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1410 22:28:49.310978 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1411 22:28:49.322099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1412 22:28:49.333347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1413 22:28:49.344632 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1414 22:28:49.355746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1415 22:28:49.366993 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1416 22:28:49.378127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1417 22:28:49.383788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1418 22:28:49.395011 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1419 22:28:49.406130 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1420 22:28:49.417382 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1421 22:28:49.428642 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1422 22:28:49.434121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1423 22:28:49.450909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1424 22:28:49.462160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1425 22:28:49.467754 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1426 22:28:49.484536 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1427 22:28:49.495784 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1428 22:28:49.506908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1429 22:28:49.512502 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1430 22:28:49.523657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1431 22:28:49.534876 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1432 22:28:49.540503 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1433 22:28:49.551657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1434 22:28:49.562909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1435 22:28:49.568497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1436 22:28:49.579655 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1437 22:28:49.585277 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1438 22:28:49.596405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1439 22:28:49.607650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1440 22:28:49.618903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1441 22:28:49.630029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1442 22:28:49.641274 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1443 22:28:49.652406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1444 22:28:49.663661 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1445 22:28:49.674748 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1446 22:28:49.685997 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1447 22:28:49.697121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1448 22:28:49.708401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1449 22:28:49.719653 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1450 22:28:49.736363 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1451 22:28:49.747645 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1452 22:28:49.758742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1453 22:28:49.769905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1454 22:28:49.781148 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1455 22:28:49.797901 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1456 22:28:49.809152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1457 22:28:49.820277 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1458 22:28:49.831523 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1459 22:28:49.837160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1460 22:28:49.848273 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1461 22:28:49.859521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1462 22:28:49.865027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1463 22:28:49.876275 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1464 22:28:49.881900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1465 22:28:49.893025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1466 22:28:49.898649 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1467 22:28:49.909899 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1468 22:28:49.915395 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1469 22:28:49.926645 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1470 22:28:49.932272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1471 22:28:49.943394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1472 22:28:49.954647 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1473 22:28:49.965771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1474 22:28:49.977021 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1475 22:28:49.988143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1476 22:28:49.993770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1477 22:28:50.005020 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1478 22:28:50.010643 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1479 22:28:50.016144 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1480 22:28:50.021770 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1481 22:28:50.027390 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1482 22:28:50.033019 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1483 22:28:50.044144 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1484 22:28:50.049765 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1485 22:28:50.055392 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1486 22:28:50.066641 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1487 22:28:50.072160 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1488 22:28:50.083336 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1489 22:28:50.088851 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1490 22:28:50.100083 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1491 22:28:50.105708 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1492 22:28:50.116848 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1493 22:28:50.122586 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1494 22:28:50.133711 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1495 22:28:50.139208 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1496 22:28:50.150456 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1497 22:28:50.156081 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1498 22:28:50.167206 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1499 22:28:50.172841 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1500 22:28:50.178457 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1501 22:28:50.189581 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1502 22:28:50.195203 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1503 22:28:50.206457 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1504 22:28:50.211956 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1505 22:28:50.223203 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1506 22:28:50.228849 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1507 22:28:50.239963 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1508 22:28:50.245583 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1509 22:28:50.251207 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1510 22:28:50.262355 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1511 22:28:50.267959 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1512 22:28:50.279203 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1513 22:28:50.290330 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1514 22:28:50.301578 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1515 22:28:50.312702 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1516 22:28:50.323948 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1517 22:28:50.335076 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1518 22:28:50.346324 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1519 22:28:50.357578 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1520 22:28:50.363073 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1521 22:28:50.374302 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1522 22:28:50.379901 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1523 22:28:50.391017 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1524 22:28:50.396644 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1525 22:28:50.407921 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1526 22:28:50.413536 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1527 22:28:50.424638 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1528 22:28:50.430263 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1529 22:28:50.441546 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1530 22:28:50.447015 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1531 22:28:50.458154 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1532 22:28:50.463763 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1533 22:28:50.475009 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1534 22:28:50.480641 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1535 22:28:50.486154 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1536 22:28:50.497418 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1537 22:28:50.503014 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1538 22:28:50.514162 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1539 22:28:50.519759 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1540 22:28:50.531002 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1541 22:28:50.536503 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1542 22:28:50.547743 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1543 22:28:50.553414 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1544 22:28:50.558925 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1545 22:28:50.564509 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1546 22:28:50.575753 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1547 22:28:50.586910 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1548 22:28:50.592519 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1549 22:28:50.598125 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1550 22:28:50.609320 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1551 22:28:50.620527 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1552 22:28:50.631741 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1553 22:28:50.642879 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1554 22:28:50.648493 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1555 22:28:50.654156 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1556 22:28:50.659803 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1557 22:28:50.665645 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1558 22:28:50.671113 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1559 22:28:50.676730 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1560 22:28:50.687983 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1561 22:28:50.693621 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1562 22:28:50.699113 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1563 22:28:50.704787 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1564 22:28:50.710367 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1565 22:28:50.721617 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1566 22:28:50.727110 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1567 22:28:50.732729 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1568 22:28:50.738382 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1569 22:28:50.743987 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1570 22:28:50.749624 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1571 22:28:50.755118 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1572 22:28:50.760738 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1573 22:28:50.766376 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1574 22:28:50.771981 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1575 22:28:50.777611 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1576 22:28:50.783107 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1577 22:28:50.788754 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1578 22:28:50.794618 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1579 22:28:50.800098 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1580 22:28:50.805711 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1581 22:28:50.811235 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1582 22:28:50.816879 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1583 22:28:50.822610 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1584 22:28:50.828108 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1585 22:28:50.833731 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1586 22:28:50.834042 dt_test_unprobed_devices_sh_opp-table skip
1587 22:28:50.839217 dt_test_unprobed_devices_sh_soc skip
1588 22:28:50.844919 dt_test_unprobed_devices_sh_sound pass
1589 22:28:50.850595 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1590 22:28:50.856071 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1591 22:28:50.861693 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1592 22:28:50.867345 dt_test_unprobed_devices_sh fail
1593 22:28:50.867645 + ../../utils/send-to-lava.sh ./output/result.txt
1594 22:28:50.875123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1595 22:28:50.875768 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1597 22:28:50.900943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1598 22:28:50.901454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1600 22:28:51.002969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1601 22:28:51.003453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1603 22:28:51.107212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1604 22:28:51.107793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1606 22:28:51.211981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1607 22:28:51.212476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1609 22:28:51.316148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1610 22:28:51.316666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1612 22:28:51.416864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1613 22:28:51.417351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1615 22:28:51.521363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1616 22:28:51.521847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1618 22:28:51.625739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1619 22:28:51.626255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1621 22:28:51.730105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1622 22:28:51.730658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1624 22:28:51.834908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1625 22:28:51.835397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1627 22:28:51.937586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1628 22:28:51.938076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1630 22:28:52.039092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1631 22:28:52.039577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1633 22:28:52.137094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1634 22:28:52.137650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1636 22:28:52.236580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1637 22:28:52.237101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1639 22:28:52.335952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1640 22:28:52.336438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1642 22:28:52.436075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1643 22:28:52.436561 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1645 22:28:52.538325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1646 22:28:52.538813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1648 22:28:52.648596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1649 22:28:52.649116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1651 22:28:52.750892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1652 22:28:52.751441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1654 22:28:52.852855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1655 22:28:52.853330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1657 22:28:52.953349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1658 22:28:52.953826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1660 22:28:53.058900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1661 22:28:53.059389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1663 22:28:53.168290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1664 22:28:53.168849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1666 22:28:53.270955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1667 22:28:53.271451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1669 22:28:53.370230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1670 22:28:53.370713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1672 22:28:53.468785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1673 22:28:53.469279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1675 22:28:53.572652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1676 22:28:53.573167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1678 22:28:53.678540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1679 22:28:53.679103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1681 22:28:53.780273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1682 22:28:53.780773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1684 22:28:53.880910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1685 22:28:53.881396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1687 22:28:53.979300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1688 22:28:53.979784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1690 22:28:54.076564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1691 22:28:54.077068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1693 22:28:54.177671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1694 22:28:54.178223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1696 22:28:54.279006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1697 22:28:54.279495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1699 22:28:54.381792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1700 22:28:54.382309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1702 22:28:54.482657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1703 22:28:54.483151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1705 22:28:54.588153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1706 22:28:54.588640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1708 22:28:54.690908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1709 22:28:54.691461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1711 22:28:54.797083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1712 22:28:54.797569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1714 22:28:54.908482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1715 22:28:54.908999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1717 22:28:55.027850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1718 22:28:55.028376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1720 22:28:55.136593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1721 22:28:55.137174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1723 22:28:55.239754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1724 22:28:55.240242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1726 22:28:55.342123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1727 22:28:55.342612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1729 22:28:55.444740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1730 22:28:55.445235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1732 22:28:55.549355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1733 22:28:55.549849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1735 22:28:55.652462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1736 22:28:55.652976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1738 22:28:55.757741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1739 22:28:55.758307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1741 22:28:55.860606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1742 22:28:55.861126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1744 22:28:55.963599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1745 22:28:55.964112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1747 22:28:56.069599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1748 22:28:56.070102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1750 22:28:56.173499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1751 22:28:56.174055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1753 22:28:56.278685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1754 22:28:56.279182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1756 22:28:56.379910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1757 22:28:56.380406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1759 22:28:56.481543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1760 22:28:56.482058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1762 22:28:56.584047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1763 22:28:56.584545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1765 22:28:56.686045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1766 22:28:56.686605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1768 22:28:56.790411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1769 22:28:56.790902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1771 22:28:56.894808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1772 22:28:56.895297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1774 22:28:56.998662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1775 22:28:56.999154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1777 22:28:57.101408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1778 22:28:57.101964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1780 22:28:57.207585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1781 22:28:57.208091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1783 22:28:57.310174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1784 22:28:57.310665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1786 22:28:57.412698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1787 22:28:57.413219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1789 22:28:57.512336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1790 22:28:57.512836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1792 22:28:57.617262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1793 22:28:57.617754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1795 22:28:57.720195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1796 22:28:57.720777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1798 22:28:57.821414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1799 22:28:57.821904 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1801 22:28:57.927653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1802 22:28:57.928170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1804 22:28:58.028536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1805 22:28:58.029050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1807 22:28:58.131479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1808 22:28:58.132084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1810 22:28:58.234102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1811 22:28:58.234589 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1813 22:28:58.338345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1814 22:28:58.338840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1816 22:28:58.438071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1817 22:28:58.438552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1819 22:28:58.539564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1820 22:28:58.540045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1822 22:28:58.643349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1823 22:28:58.643835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1825 22:28:58.749089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1826 22:28:58.749636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1828 22:28:58.851310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1829 22:28:58.851788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1831 22:28:58.958962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1832 22:28:58.959438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1834 22:28:59.061527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1835 22:28:59.062003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1837 22:28:59.165017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1838 22:28:59.165561 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1840 22:28:59.269312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1841 22:28:59.269794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1843 22:28:59.370040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1844 22:28:59.370532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1846 22:28:59.477539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1847 22:28:59.478017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1849 22:28:59.578779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1850 22:28:59.579267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1852 22:28:59.681163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1853 22:28:59.681643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1855 22:28:59.781595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1856 22:28:59.781974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1858 22:28:59.876353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1859 22:28:59.876759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1861 22:28:59.976471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1862 22:28:59.976849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1864 22:29:00.079944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1865 22:29:00.080517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1867 22:29:00.176160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1868 22:29:00.176525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1870 22:29:00.278022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1871 22:29:00.278392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1873 22:29:00.375516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1874 22:29:00.375889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1876 22:29:00.479198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1877 22:29:00.479713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1879 22:29:00.577622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1880 22:29:00.578123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1882 22:29:00.676532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1883 22:29:00.677051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1885 22:29:00.776791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1886 22:29:00.777346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1888 22:29:00.879309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1889 22:29:00.879824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1891 22:29:00.978250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1892 22:29:00.978750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1894 22:29:01.077928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1895 22:29:01.078421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1897 22:29:01.177672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1898 22:29:01.178203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1900 22:29:01.275271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1901 22:29:01.275762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1903 22:29:01.376242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1904 22:29:01.376770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1906 22:29:01.479250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1907 22:29:01.479759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1909 22:29:01.582163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1910 22:29:01.582652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1912 22:29:01.684364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1913 22:29:01.684874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1915 22:29:01.786925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1916 22:29:01.787479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1918 22:29:01.892897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1919 22:29:01.893391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1921 22:29:01.993155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1922 22:29:01.993663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1924 22:29:02.092512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1925 22:29:02.093022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1927 22:29:02.189196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1928 22:29:02.189743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1930 22:29:02.287198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1931 22:29:02.287704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1933 22:29:02.388513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1934 22:29:02.389095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1936 22:29:02.489071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1937 22:29:02.489640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1939 22:29:02.587777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1940 22:29:02.588281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1942 22:29:02.690253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1943 22:29:02.690749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1945 22:29:02.792817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1946 22:29:02.793370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1948 22:29:02.896893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1949 22:29:02.897398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1951 22:29:03.003528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1952 22:29:03.004025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1954 22:29:03.104010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1956 22:29:03.107055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1957 22:29:03.206926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1959 22:29:03.210018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1960 22:29:03.307921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1962 22:29:03.310935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1963 22:29:03.410152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1964 22:29:03.410665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1966 22:29:03.510250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1967 22:29:03.510754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1969 22:29:03.615119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1970 22:29:03.615550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1972 22:29:03.716253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1973 22:29:03.716778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1975 22:29:03.815898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1976 22:29:03.816405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1978 22:29:03.918780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1979 22:29:03.919291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1981 22:29:04.018377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1982 22:29:04.018867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1984 22:29:04.119087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1985 22:29:04.119630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1987 22:29:04.219628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1988 22:29:04.220124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1990 22:29:04.324571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1991 22:29:04.325103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1993 22:29:04.422046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1994 22:29:04.422543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1996 22:29:04.522539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1997 22:29:04.523036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1999 22:29:04.621181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2000 22:29:04.621680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2002 22:29:04.723445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2003 22:29:04.724001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2005 22:29:04.825120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2006 22:29:04.825633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2008 22:29:04.928474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2009 22:29:04.929016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2011 22:29:05.026862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2012 22:29:05.027360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2014 22:29:05.127382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2015 22:29:05.127947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2017 22:29:05.226542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2018 22:29:05.227047 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2020 22:29:05.325550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2021 22:29:05.326067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2023 22:29:05.425073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2024 22:29:05.425681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2026 22:29:05.523178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2027 22:29:05.523728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2029 22:29:05.626685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2030 22:29:05.627250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2032 22:29:05.725307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2033 22:29:05.725855 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2035 22:29:05.828342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2036 22:29:05.828914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2038 22:29:05.927813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2039 22:29:05.928310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2041 22:29:06.028035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2042 22:29:06.028535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2044 22:29:06.129163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2045 22:29:06.129713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2047 22:29:06.228292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2048 22:29:06.228771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2050 22:29:06.327506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2051 22:29:06.328032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2053 22:29:06.427511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2054 22:29:06.428006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2056 22:29:06.528115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2057 22:29:06.528674 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2059 22:29:06.627247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2060 22:29:06.627796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2062 22:29:06.728237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2063 22:29:06.728787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2065 22:29:06.828516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2066 22:29:06.829009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2068 22:29:06.924366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2069 22:29:06.924859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2071 22:29:07.024341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2072 22:29:07.024837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2074 22:29:07.123342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2075 22:29:07.124063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2077 22:29:07.225109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2078 22:29:07.225594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2080 22:29:07.323868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2081 22:29:07.324368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2083 22:29:07.427241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2084 22:29:07.427730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2086 22:29:07.526992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2087 22:29:07.527485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2089 22:29:07.626110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2090 22:29:07.626614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2092 22:29:07.725599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2093 22:29:07.726157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2095 22:29:07.823995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2096 22:29:07.824490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2098 22:29:07.925297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2099 22:29:07.925813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2101 22:29:08.026663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2102 22:29:08.027197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2104 22:29:08.128493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2105 22:29:08.129095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2107 22:29:08.228095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2108 22:29:08.228579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2110 22:29:08.330485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2111 22:29:08.331001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2113 22:29:08.434603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2114 22:29:08.435115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2116 22:29:08.535307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2117 22:29:08.535805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2119 22:29:08.632214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2120 22:29:08.632739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2122 22:29:08.732206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2123 22:29:08.732776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2125 22:29:08.832890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2126 22:29:08.833447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2128 22:29:08.939625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2129 22:29:08.940149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2131 22:29:09.041311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2132 22:29:09.041800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2134 22:29:09.139952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2135 22:29:09.140641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2137 22:29:09.241343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2138 22:29:09.241871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2140 22:29:09.340611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2141 22:29:09.341149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2143 22:29:09.438661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2144 22:29:09.439168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2146 22:29:09.536428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2147 22:29:09.537063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2149 22:29:09.641118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2150 22:29:09.641619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2152 22:29:09.737487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2153 22:29:09.738046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2155 22:29:09.838462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2156 22:29:09.838979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2158 22:29:09.938491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2159 22:29:09.938987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2161 22:29:10.037838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2162 22:29:10.038325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2164 22:29:10.137844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2165 22:29:10.138412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2167 22:29:10.238728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2168 22:29:10.239218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2170 22:29:10.338907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2171 22:29:10.339402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2173 22:29:10.439565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2174 22:29:10.440127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2176 22:29:10.536183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2177 22:29:10.536703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2179 22:29:10.634771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2180 22:29:10.635265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2182 22:29:10.735923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2183 22:29:10.736473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2185 22:29:10.834878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2186 22:29:10.835364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2188 22:29:10.934000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2189 22:29:10.934496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2191 22:29:11.035596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2192 22:29:11.036094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2194 22:29:11.135735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2195 22:29:11.136280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2197 22:29:11.230608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2198 22:29:11.231101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2200 22:29:11.330740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2201 22:29:11.331243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2203 22:29:11.433943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2204 22:29:11.434432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2206 22:29:11.534441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2207 22:29:11.534935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2209 22:29:11.633829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2210 22:29:11.634332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2212 22:29:11.731193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2213 22:29:11.731816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2215 22:29:11.831196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2216 22:29:11.831631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2218 22:29:11.934976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2219 22:29:11.935476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2221 22:29:12.031335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2222 22:29:12.031828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2224 22:29:12.132126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2225 22:29:12.132704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2227 22:29:12.237286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2228 22:29:12.237786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2230 22:29:12.342532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2231 22:29:12.343019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2233 22:29:12.443824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2234 22:29:12.444315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2236 22:29:12.544889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2237 22:29:12.545502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2239 22:29:12.644978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2240 22:29:12.645512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2242 22:29:12.745944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2243 22:29:12.746494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2245 22:29:12.848651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2246 22:29:12.849294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2248 22:29:12.951079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2249 22:29:12.951703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2251 22:29:13.050013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2252 22:29:13.050574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2254 22:29:13.149506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2255 22:29:13.150079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2257 22:29:13.244466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2258 22:29:13.244983 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2260 22:29:13.345330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2261 22:29:13.345831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2263 22:29:13.446274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2264 22:29:13.446775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2266 22:29:13.544924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2267 22:29:13.545413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2269 22:29:13.645430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2270 22:29:13.645930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2272 22:29:13.746643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2273 22:29:13.747124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2275 22:29:13.844271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2277 22:29:13.847237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2278 22:29:13.947396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2279 22:29:13.947892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2281 22:29:14.048782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2282 22:29:14.049277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2284 22:29:14.147720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2285 22:29:14.148269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2287 22:29:14.246485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2288 22:29:14.246967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2290 22:29:14.345443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2291 22:29:14.345938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2293 22:29:14.445211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2294 22:29:14.445778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2296 22:29:14.544350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2297 22:29:14.544820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2299 22:29:14.645385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2300 22:29:14.645911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2302 22:29:14.745099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2303 22:29:14.745806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2305 22:29:14.844253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2306 22:29:14.844852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2308 22:29:14.942842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2309 22:29:14.943321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2311 22:29:15.042712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2312 22:29:15.043362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2314 22:29:15.142912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2315 22:29:15.143524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2317 22:29:15.239834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2318 22:29:15.240336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2320 22:29:15.340352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2321 22:29:15.340857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2323 22:29:15.441214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2324 22:29:15.441709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2326 22:29:15.549683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2327 22:29:15.550166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2329 22:29:15.662121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2330 22:29:15.662633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2332 22:29:15.766327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2333 22:29:15.766849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2335 22:29:15.863871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2336 22:29:15.864320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2338 22:29:15.961878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2339 22:29:15.962429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2341 22:29:16.063091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2342 22:29:16.063594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2344 22:29:16.163320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2345 22:29:16.163862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2347 22:29:16.265812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2348 22:29:16.266328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2350 22:29:16.363697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2351 22:29:16.364211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2353 22:29:16.462419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2354 22:29:16.462930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2356 22:29:16.562692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2357 22:29:16.563194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2359 22:29:16.664634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2360 22:29:16.665173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2362 22:29:16.765024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2363 22:29:16.765558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2365 22:29:16.867242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2366 22:29:16.867776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2368 22:29:16.961244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2369 22:29:16.961633 + set +x
2370 22:29:16.962191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2372 22:29:16.965484 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1219904_1.6.2.4.5>
2373 22:29:16.965922 Received signal: <ENDRUN> 1_kselftest-dt 1219904_1.6.2.4.5
2374 22:29:16.966217 Ending use of test pattern.
2375 22:29:16.966473 Ending test lava.1_kselftest-dt (1219904_1.6.2.4.5), duration 95.50
2377 22:29:16.973675 <LAVA_TEST_RUNNER EXIT>
2378 22:29:16.974160 ok: lava_test_shell seems to have completed
2379 22:29:16.980191 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2380 22:29:16.981285 end: 3.1 lava-test-shell (duration 00:01:37) [common]
2381 22:29:16.981587 end: 3 lava-test-retry (duration 00:01:37) [common]
2382 22:29:16.981883 start: 4 finalize (timeout 00:05:44) [common]
2383 22:29:16.982182 start: 4.1 power-off (timeout 00:00:30) [common]
2384 22:29:16.982566 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2385 22:29:17.373271 Returned 0 in 0 seconds
2386 22:29:17.474244 end: 4.1 power-off (duration 00:00:00) [common]
2388 22:29:17.475484 start: 4.2 read-feedback (timeout 00:05:44) [common]
2389 22:29:17.476283 Listened to connection for namespace 'common' for up to 1s
2390 22:29:17.476963 Listened to connection for namespace 'common' for up to 1s
2391 22:29:18.477054 Finalising connection for namespace 'common'
2392 22:29:18.477298 Disconnecting from shell: Finalise
2393 22:29:18.477424 / #
2394 22:29:18.577785 end: 4.2 read-feedback (duration 00:00:01) [common]
2395 22:29:18.578110 end: 4 finalize (duration 00:00:02) [common]
2396 22:29:18.578442 Cleaning after the job
2397 22:29:18.578747 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219904/tftp-deploy-u6vbidi_/ramdisk
2398 22:29:18.582196 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219904/tftp-deploy-u6vbidi_/kernel
2399 22:29:18.584909 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219904/tftp-deploy-u6vbidi_/dtb
2400 22:29:18.585126 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219904/tftp-deploy-u6vbidi_/nfsrootfs
2401 22:29:18.638159 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219904/tftp-deploy-u6vbidi_/modules
2402 22:29:18.641789 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1219904
2403 22:29:19.351164 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1219904
2404 22:29:19.351434 Job finished correctly