Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 23:26:08.676440 lava-dispatcher, installed at version: 2024.01
2 23:26:08.677236 start: 0 validate
3 23:26:08.677717 Start time: 2024-11-08 23:26:08.677687+00:00 (UTC)
4 23:26:08.678259 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:26:08.678816 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 23:26:08.724911 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:26:08.725457 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fkernel%2FzImage exists
8 23:26:08.758696 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:26:08.759332 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 23:26:08.794210 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:26:08.794728 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 23:26:08.829042 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 23:26:08.829555 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fmodules.tar.xz exists
14 23:26:08.870154 validate duration: 0.19
16 23:26:08.871065 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:26:08.871406 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:26:08.871719 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:26:08.872320 Not decompressing ramdisk as can be used compressed.
20 23:26:08.872718 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 23:26:08.872988 saving as /var/lib/lava/dispatcher/tmp/963448/tftp-deploy-opvjh0od/ramdisk/initrd.cpio.gz
22 23:26:08.873266 total size: 4775763 (4 MB)
23 23:26:08.915721 progress 0 % (0 MB)
24 23:26:08.921760 progress 5 % (0 MB)
25 23:26:08.928037 progress 10 % (0 MB)
26 23:26:08.934311 progress 15 % (0 MB)
27 23:26:08.940843 progress 20 % (0 MB)
28 23:26:08.944818 progress 25 % (1 MB)
29 23:26:08.948011 progress 30 % (1 MB)
30 23:26:08.951611 progress 35 % (1 MB)
31 23:26:08.954910 progress 40 % (1 MB)
32 23:26:08.958133 progress 45 % (2 MB)
33 23:26:08.961353 progress 50 % (2 MB)
34 23:26:08.964972 progress 55 % (2 MB)
35 23:26:08.968166 progress 60 % (2 MB)
36 23:26:08.971472 progress 65 % (2 MB)
37 23:26:08.975077 progress 70 % (3 MB)
38 23:26:08.978250 progress 75 % (3 MB)
39 23:26:08.981476 progress 80 % (3 MB)
40 23:26:08.984652 progress 85 % (3 MB)
41 23:26:08.988124 progress 90 % (4 MB)
42 23:26:08.991046 progress 95 % (4 MB)
43 23:26:08.993979 progress 100 % (4 MB)
44 23:26:08.994627 4 MB downloaded in 0.12 s (37.53 MB/s)
45 23:26:08.995157 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:26:08.996056 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:26:08.996356 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:26:08.996626 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:26:08.997094 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/kernel/zImage
51 23:26:08.997339 saving as /var/lib/lava/dispatcher/tmp/963448/tftp-deploy-opvjh0od/kernel/zImage
52 23:26:08.997545 total size: 12042752 (11 MB)
53 23:26:08.997756 No compression specified
54 23:26:09.036737 progress 0 % (0 MB)
55 23:26:09.044831 progress 5 % (0 MB)
56 23:26:09.052347 progress 10 % (1 MB)
57 23:26:09.060329 progress 15 % (1 MB)
58 23:26:09.068050 progress 20 % (2 MB)
59 23:26:09.075485 progress 25 % (2 MB)
60 23:26:09.083382 progress 30 % (3 MB)
61 23:26:09.090820 progress 35 % (4 MB)
62 23:26:09.098685 progress 40 % (4 MB)
63 23:26:09.106119 progress 45 % (5 MB)
64 23:26:09.113555 progress 50 % (5 MB)
65 23:26:09.121331 progress 55 % (6 MB)
66 23:26:09.128759 progress 60 % (6 MB)
67 23:26:09.136248 progress 65 % (7 MB)
68 23:26:09.144055 progress 70 % (8 MB)
69 23:26:09.151412 progress 75 % (8 MB)
70 23:26:09.159162 progress 80 % (9 MB)
71 23:26:09.166863 progress 85 % (9 MB)
72 23:26:09.174512 progress 90 % (10 MB)
73 23:26:09.182221 progress 95 % (10 MB)
74 23:26:09.189063 progress 100 % (11 MB)
75 23:26:09.189633 11 MB downloaded in 0.19 s (59.79 MB/s)
76 23:26:09.190100 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:26:09.190915 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:26:09.191189 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:26:09.191455 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:26:09.191917 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/dtbs/ti/omap/am335x-boneblack.dtb
82 23:26:09.192214 saving as /var/lib/lava/dispatcher/tmp/963448/tftp-deploy-opvjh0od/dtb/am335x-boneblack.dtb
83 23:26:09.192423 total size: 70568 (0 MB)
84 23:26:09.192630 No compression specified
85 23:26:09.231620 progress 46 % (0 MB)
86 23:26:09.232479 progress 92 % (0 MB)
87 23:26:09.233167 progress 100 % (0 MB)
88 23:26:09.233551 0 MB downloaded in 0.04 s (1.64 MB/s)
89 23:26:09.233997 end: 1.3.1 http-download (duration 00:00:00) [common]
91 23:26:09.234803 end: 1.3 download-retry (duration 00:00:00) [common]
92 23:26:09.235067 start: 1.4 download-retry (timeout 00:10:00) [common]
93 23:26:09.235330 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 23:26:09.235776 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 23:26:09.236048 saving as /var/lib/lava/dispatcher/tmp/963448/tftp-deploy-opvjh0od/nfsrootfs/full.rootfs.tar
96 23:26:09.236257 total size: 117747780 (112 MB)
97 23:26:09.236467 Using unxz to decompress xz
98 23:26:09.275312 progress 0 % (0 MB)
99 23:26:09.993376 progress 5 % (5 MB)
100 23:26:10.723047 progress 10 % (11 MB)
101 23:26:11.499313 progress 15 % (16 MB)
102 23:26:12.214169 progress 20 % (22 MB)
103 23:26:12.822286 progress 25 % (28 MB)
104 23:26:13.642878 progress 30 % (33 MB)
105 23:26:14.442453 progress 35 % (39 MB)
106 23:26:14.781342 progress 40 % (44 MB)
107 23:26:15.128345 progress 45 % (50 MB)
108 23:26:15.786377 progress 50 % (56 MB)
109 23:26:16.592899 progress 55 % (61 MB)
110 23:26:17.320590 progress 60 % (67 MB)
111 23:26:18.033228 progress 65 % (73 MB)
112 23:26:18.791663 progress 70 % (78 MB)
113 23:26:19.542384 progress 75 % (84 MB)
114 23:26:20.271002 progress 80 % (89 MB)
115 23:26:20.968673 progress 85 % (95 MB)
116 23:26:21.922178 progress 90 % (101 MB)
117 23:26:22.921262 progress 95 % (106 MB)
118 23:26:23.739053 progress 100 % (112 MB)
119 23:26:23.751389 112 MB downloaded in 14.52 s (7.74 MB/s)
120 23:26:23.752398 end: 1.4.1 http-download (duration 00:00:15) [common]
122 23:26:23.754208 end: 1.4 download-retry (duration 00:00:15) [common]
123 23:26:23.754791 start: 1.5 download-retry (timeout 00:09:45) [common]
124 23:26:23.755370 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 23:26:23.756329 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/modules.tar.xz
126 23:26:23.756865 saving as /var/lib/lava/dispatcher/tmp/963448/tftp-deploy-opvjh0od/modules/modules.tar
127 23:26:23.757328 total size: 6911472 (6 MB)
128 23:26:23.757799 Using unxz to decompress xz
129 23:26:23.801497 progress 0 % (0 MB)
130 23:26:23.839203 progress 5 % (0 MB)
131 23:26:23.888292 progress 10 % (0 MB)
132 23:26:23.934356 progress 15 % (1 MB)
133 23:26:23.988513 progress 20 % (1 MB)
134 23:26:24.035817 progress 25 % (1 MB)
135 23:26:24.085382 progress 30 % (2 MB)
136 23:26:24.129083 progress 35 % (2 MB)
137 23:26:24.177240 progress 40 % (2 MB)
138 23:26:24.222560 progress 45 % (2 MB)
139 23:26:24.271442 progress 50 % (3 MB)
140 23:26:24.318677 progress 55 % (3 MB)
141 23:26:24.365156 progress 60 % (3 MB)
142 23:26:24.412356 progress 65 % (4 MB)
143 23:26:24.459581 progress 70 % (4 MB)
144 23:26:24.509967 progress 75 % (4 MB)
145 23:26:24.553942 progress 80 % (5 MB)
146 23:26:24.602837 progress 85 % (5 MB)
147 23:26:24.647125 progress 90 % (5 MB)
148 23:26:24.695021 progress 95 % (6 MB)
149 23:26:24.739015 progress 100 % (6 MB)
150 23:26:24.753900 6 MB downloaded in 1.00 s (6.61 MB/s)
151 23:26:24.754487 end: 1.5.1 http-download (duration 00:00:01) [common]
153 23:26:24.755320 end: 1.5 download-retry (duration 00:00:01) [common]
154 23:26:24.755587 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 23:26:24.755854 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 23:26:41.073428 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/963448/extract-nfsrootfs-dk0u5zii
157 23:26:41.074037 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 23:26:41.074324 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 23:26:41.074962 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth
160 23:26:41.075389 makedir: /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin
161 23:26:41.075719 makedir: /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/tests
162 23:26:41.076086 makedir: /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/results
163 23:26:41.076445 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-add-keys
164 23:26:41.076982 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-add-sources
165 23:26:41.077489 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-background-process-start
166 23:26:41.077989 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-background-process-stop
167 23:26:41.078517 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-common-functions
168 23:26:41.079014 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-echo-ipv4
169 23:26:41.079511 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-install-packages
170 23:26:41.080044 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-installed-packages
171 23:26:41.080550 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-os-build
172 23:26:41.081036 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-probe-channel
173 23:26:41.081536 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-probe-ip
174 23:26:41.082042 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-target-ip
175 23:26:41.082519 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-target-mac
176 23:26:41.082997 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-target-storage
177 23:26:41.083474 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-test-case
178 23:26:41.084062 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-test-event
179 23:26:41.084575 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-test-feedback
180 23:26:41.085058 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-test-raise
181 23:26:41.085551 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-test-reference
182 23:26:41.086050 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-test-runner
183 23:26:41.086530 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-test-set
184 23:26:41.087006 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-test-shell
185 23:26:41.087492 Updating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-add-keys (debian)
186 23:26:41.088034 Updating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-add-sources (debian)
187 23:26:41.088564 Updating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-install-packages (debian)
188 23:26:41.089087 Updating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-installed-packages (debian)
189 23:26:41.089591 Updating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/bin/lava-os-build (debian)
190 23:26:41.090024 Creating /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/environment
191 23:26:41.090393 LAVA metadata
192 23:26:41.090650 - LAVA_JOB_ID=963448
193 23:26:41.090861 - LAVA_DISPATCHER_IP=192.168.6.2
194 23:26:41.091211 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 23:26:41.092202 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 23:26:41.092518 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 23:26:41.092723 skipped lava-vland-overlay
198 23:26:41.092963 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 23:26:41.093214 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 23:26:41.093429 skipped lava-multinode-overlay
201 23:26:41.093670 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 23:26:41.093919 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 23:26:41.094161 Loading test definitions
204 23:26:41.094436 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 23:26:41.094653 Using /lava-963448 at stage 0
206 23:26:41.095720 uuid=963448_1.6.2.4.1 testdef=None
207 23:26:41.096065 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 23:26:41.096341 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 23:26:41.097897 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 23:26:41.098675 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 23:26:41.100613 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 23:26:41.101436 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 23:26:41.103240 runner path: /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/0/tests/0_timesync-off test_uuid 963448_1.6.2.4.1
216 23:26:41.103796 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 23:26:41.104631 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 23:26:41.104853 Using /lava-963448 at stage 0
220 23:26:41.105204 Fetching tests from https://github.com/kernelci/test-definitions.git
221 23:26:41.105492 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/0/tests/1_kselftest-dt'
222 23:26:44.560384 Running '/usr/bin/git checkout kernelci.org
223 23:26:45.003951 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 23:26:45.006423 uuid=963448_1.6.2.4.5 testdef=None
225 23:26:45.007024 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 23:26:45.008519 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 23:26:45.013895 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 23:26:45.014763 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 23:26:45.021951 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 23:26:45.023667 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 23:26:45.030963 runner path: /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/0/tests/1_kselftest-dt test_uuid 963448_1.6.2.4.5
235 23:26:45.031553 BOARD='beaglebone-black'
236 23:26:45.031958 BRANCH='mainline'
237 23:26:45.032385 SKIPFILE='/dev/null'
238 23:26:45.032794 SKIP_INSTALL='True'
239 23:26:45.033196 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz'
240 23:26:45.033596 TST_CASENAME=''
241 23:26:45.033984 TST_CMDFILES='dt'
242 23:26:45.035091 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 23:26:45.036737 Creating lava-test-runner.conf files
245 23:26:45.037146 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/963448/lava-overlay-rwn59jth/lava-963448/0 for stage 0
246 23:26:45.037832 - 0_timesync-off
247 23:26:45.038307 - 1_kselftest-dt
248 23:26:45.039008 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 23:26:45.039579 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 23:27:08.989944 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 23:27:08.990409 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 23:27:08.990705 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 23:27:08.991021 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 23:27:08.991317 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 23:27:09.378742 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 23:27:09.379343 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
257 23:27:09.379649 extracting modules file /var/lib/lava/dispatcher/tmp/963448/tftp-deploy-opvjh0od/modules/modules.tar to /var/lib/lava/dispatcher/tmp/963448/extract-nfsrootfs-dk0u5zii
258 23:27:10.305028 extracting modules file /var/lib/lava/dispatcher/tmp/963448/tftp-deploy-opvjh0od/modules/modules.tar to /var/lib/lava/dispatcher/tmp/963448/extract-overlay-ramdisk-e35va694/ramdisk
259 23:27:11.375671 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 23:27:11.376282 start: 1.6.5 apply-overlay-tftp (timeout 00:08:57) [common]
261 23:27:11.376640 [common] Applying overlay to NFS
262 23:27:11.376904 [common] Applying overlay /var/lib/lava/dispatcher/tmp/963448/compress-overlay-y78ptq_d/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/963448/extract-nfsrootfs-dk0u5zii
263 23:27:14.125838 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 23:27:14.126312 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 23:27:14.126585 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 23:27:14.126860 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 23:27:14.127110 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 23:27:14.127367 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 23:27:14.127612 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 23:27:14.127862 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 23:27:14.128158 Building ramdisk /var/lib/lava/dispatcher/tmp/963448/extract-overlay-ramdisk-e35va694/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/963448/extract-overlay-ramdisk-e35va694/ramdisk
272 23:27:15.356707 >> 78983 blocks
273 23:27:20.423443 Adding RAMdisk u-boot header.
274 23:27:20.424188 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/963448/extract-overlay-ramdisk-e35va694/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/963448/extract-overlay-ramdisk-e35va694/ramdisk.cpio.gz.uboot
275 23:27:20.605128 output: Image Name:
276 23:27:20.605542 output: Created: Fri Nov 8 23:27:20 2024
277 23:27:20.606004 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 23:27:20.606462 output: Data Size: 15347068 Bytes = 14987.37 KiB = 14.64 MiB
279 23:27:20.606912 output: Load Address: 00000000
280 23:27:20.607355 output: Entry Point: 00000000
281 23:27:20.607797 output:
282 23:27:20.608956 rename /var/lib/lava/dispatcher/tmp/963448/extract-overlay-ramdisk-e35va694/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/963448/tftp-deploy-opvjh0od/ramdisk/ramdisk.cpio.gz.uboot
283 23:27:20.609733 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 23:27:20.610338 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 23:27:20.610925 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
286 23:27:20.611436 No LXC device requested
287 23:27:20.612028 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 23:27:20.612608 start: 1.8 deploy-device-env (timeout 00:08:48) [common]
289 23:27:20.613163 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 23:27:20.613622 Checking files for TFTP limit of 4294967296 bytes.
291 23:27:20.616551 end: 1 tftp-deploy (duration 00:01:12) [common]
292 23:27:20.617186 start: 2 uboot-action (timeout 00:05:00) [common]
293 23:27:20.617776 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 23:27:20.618335 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 23:27:20.618899 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 23:27:20.619730 substitutions:
297 23:27:20.620235 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 23:27:20.620691 - {DTB_ADDR}: 0x88000000
299 23:27:20.621137 - {DTB}: 963448/tftp-deploy-opvjh0od/dtb/am335x-boneblack.dtb
300 23:27:20.621579 - {INITRD}: 963448/tftp-deploy-opvjh0od/ramdisk/ramdisk.cpio.gz.uboot
301 23:27:20.622019 - {KERNEL_ADDR}: 0x82000000
302 23:27:20.622453 - {KERNEL}: 963448/tftp-deploy-opvjh0od/kernel/zImage
303 23:27:20.622892 - {LAVA_MAC}: None
304 23:27:20.623369 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/963448/extract-nfsrootfs-dk0u5zii
305 23:27:20.623813 - {NFS_SERVER_IP}: 192.168.6.2
306 23:27:20.624287 - {PRESEED_CONFIG}: None
307 23:27:20.624727 - {PRESEED_LOCAL}: None
308 23:27:20.625160 - {RAMDISK_ADDR}: 0x83000000
309 23:27:20.625595 - {RAMDISK}: 963448/tftp-deploy-opvjh0od/ramdisk/ramdisk.cpio.gz.uboot
310 23:27:20.626034 - {ROOT_PART}: None
311 23:27:20.626463 - {ROOT}: None
312 23:27:20.626891 - {SERVER_IP}: 192.168.6.2
313 23:27:20.627322 - {TEE_ADDR}: 0x83000000
314 23:27:20.627748 - {TEE}: None
315 23:27:20.628215 Parsed boot commands:
316 23:27:20.628637 - setenv autoload no
317 23:27:20.629068 - setenv initrd_high 0xffffffff
318 23:27:20.629496 - setenv fdt_high 0xffffffff
319 23:27:20.629921 - dhcp
320 23:27:20.630346 - setenv serverip 192.168.6.2
321 23:27:20.630773 - tftp 0x82000000 963448/tftp-deploy-opvjh0od/kernel/zImage
322 23:27:20.631200 - tftp 0x83000000 963448/tftp-deploy-opvjh0od/ramdisk/ramdisk.cpio.gz.uboot
323 23:27:20.631630 - setenv initrd_size ${filesize}
324 23:27:20.632084 - tftp 0x88000000 963448/tftp-deploy-opvjh0od/dtb/am335x-boneblack.dtb
325 23:27:20.632519 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/963448/extract-nfsrootfs-dk0u5zii,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 23:27:20.632958 - bootz 0x82000000 0x83000000 0x88000000
327 23:27:20.633510 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 23:27:20.635142 start: 2.3 connect-device (timeout 00:05:00) [common]
330 23:27:20.635608 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 23:27:20.652693 Setting prompt string to ['lava-test: # ']
332 23:27:20.654297 end: 2.3 connect-device (duration 00:00:00) [common]
333 23:27:20.654977 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 23:27:20.655702 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 23:27:20.656404 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 23:27:20.657748 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 23:27:20.694713 >> OK - accepted request
338 23:27:20.697577 Returned 0 in 0 seconds
339 23:27:20.798789 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 23:27:20.800664 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 23:27:20.801312 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 23:27:20.801886 Setting prompt string to ['Hit any key to stop autoboot']
344 23:27:20.802401 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 23:27:20.804125 Trying 192.168.56.21...
346 23:27:20.804677 Connected to conserv1.
347 23:27:20.805152 Escape character is '^]'.
348 23:27:20.805622
349 23:27:20.806088 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 23:27:20.806559
351 23:27:28.719293
352 23:27:28.719971 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 23:27:28.724226 Trying to boot from MMC1
354 23:27:29.296601
355 23:27:29.297286
356 23:27:29.297760 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 23:27:29.298224
358 23:27:29.301841 CPU : AM335X-GP rev 2.1
359 23:27:29.302364 Model: TI AM335x BeagleBone Black
360 23:27:29.306093 DRAM: 512 MiB
361 23:27:29.389013 Core: 160 devices, 18 uclasses, devicetree: separate
362 23:27:29.398423 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 23:27:32.769173 7[r[999;999H[6n8NAND:
364 23:27:32.769842 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 23:27:32.774209 Trying to boot from MMC1
366 23:27:33.346438
367 23:27:33.347063
368 23:27:33.347476 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 23:27:33.347883
370 23:27:33.351691 CPU : AM335X-GP rev 2.1
371 23:27:33.352155 Model: TI AM335x BeagleBone Black
372 23:27:33.355826 DRAM: 512 MiB
373 23:27:33.438667 Core: 160 devices, 18 uclasses, devicetree: separate
374 23:27:33.448221 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 23:27:35.470239 7[r[999;999H[6n8NAND:
376 23:27:35.470656 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 23:27:35.475326 Trying to boot from MMC1
378 23:27:36.050705
379 23:27:36.051135
380 23:27:36.051354 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 23:27:36.051563
382 23:27:36.056093 CPU : AM335X-GP rev 2.1
383 23:27:36.056411 Model: TI AM335x BeagleBone Black
384 23:27:36.060134 DRAM: 512 MiB
385 23:27:36.143448 Core: 160 devices, 18 uclasses, devicetree: separate
386 23:27:36.153055 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 23:27:36.658116 7[r[999;999H[6n8NAND: 0 MiB
388 23:27:36.668355 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 23:27:36.741170 Loading Environment from FAT... Unable to use mmc 0:1...
390 23:27:36.762559 <ethaddr> not set. Validating first E-fuse MAC
391 23:27:36.792905 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 23:27:36.851556 Hit any key to stop autoboot: 2
394 23:27:36.852440 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 23:27:36.853204 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 23:27:36.853697 Setting prompt string to ['=>']
397 23:27:36.854191 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 23:27:36.861433 0
399 23:27:36.862345 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 23:27:36.862841 Sending with 10 millisecond of delay
402 23:27:37.997965 => setenv autoload no
403 23:27:38.008793 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 23:27:38.013745 setenv autoload no
405 23:27:38.014484 Sending with 10 millisecond of delay
407 23:27:39.811574 => setenv initrd_high 0xffffffff
408 23:27:39.822405 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 23:27:39.823295 setenv initrd_high 0xffffffff
410 23:27:39.824059 Sending with 10 millisecond of delay
412 23:27:41.440731 => setenv fdt_high 0xffffffff
413 23:27:41.451504 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 23:27:41.452444 setenv fdt_high 0xffffffff
415 23:27:41.453159 Sending with 10 millisecond of delay
417 23:27:41.745088 => dhcp
418 23:27:41.755864 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 23:27:41.756773 dhcp
420 23:27:41.757944 link up on port 0, speed 100, full duplex
421 23:27:41.758420 BOOTP broadcast 1
422 23:27:41.779445 DHCP client bound to address 192.168.6.12 (18 ms)
423 23:27:41.780199 Sending with 10 millisecond of delay
425 23:27:43.457187 => setenv serverip 192.168.6.2
426 23:27:43.468054 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
427 23:27:43.468980 setenv serverip 192.168.6.2
428 23:27:43.469693 Sending with 10 millisecond of delay
430 23:27:46.953376 => tftp 0x82000000 963448/tftp-deploy-opvjh0od/kernel/zImage
431 23:27:46.964075 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
432 23:27:46.964603 tftp 0x82000000 963448/tftp-deploy-opvjh0od/kernel/zImage
433 23:27:46.964847 link up on port 0, speed 100, full duplex
434 23:27:46.968390 Using ethernet@4a100000 device
435 23:27:46.974020 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 23:27:46.981348 Filename '963448/tftp-deploy-opvjh0od/kernel/zImage'.
437 23:27:46.981911 Load address: 0x82000000
438 23:27:49.404188 Loading: *################################################## 11.5 MiB
439 23:27:49.404822 4.7 MiB/s
440 23:27:49.405257 done
441 23:27:49.408431 Bytes transferred = 12042752 (b7c200 hex)
442 23:27:49.409246 Sending with 10 millisecond of delay
444 23:27:53.858082 => tftp 0x83000000 963448/tftp-deploy-opvjh0od/ramdisk/ramdisk.cpio.gz.uboot
445 23:27:53.868903 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 23:27:53.869784 tftp 0x83000000 963448/tftp-deploy-opvjh0od/ramdisk/ramdisk.cpio.gz.uboot
447 23:27:53.870262 link up on port 0, speed 100, full duplex
448 23:27:53.873855 Using ethernet@4a100000 device
449 23:27:53.879449 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 23:27:53.882820 Filename '963448/tftp-deploy-opvjh0od/ramdisk/ramdisk.cpio.gz.uboot'.
451 23:27:53.887961 Load address: 0x83000000
452 23:27:56.875630 Loading: *################################################## 14.6 MiB
453 23:27:56.876490 4.9 MiB/s
454 23:27:56.877084 done
455 23:27:56.879818 Bytes transferred = 15347132 (ea2dbc hex)
456 23:27:56.880845 Sending with 10 millisecond of delay
458 23:27:58.739578 => setenv initrd_size ${filesize}
459 23:27:58.750466 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
460 23:27:58.751336 setenv initrd_size ${filesize}
461 23:27:58.752090 Sending with 10 millisecond of delay
463 23:28:02.904116 => tftp 0x88000000 963448/tftp-deploy-opvjh0od/dtb/am335x-boneblack.dtb
464 23:28:02.914770 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 23:28:02.915750 tftp 0x88000000 963448/tftp-deploy-opvjh0od/dtb/am335x-boneblack.dtb
466 23:28:02.916248 link up on port 0, speed 100, full duplex
467 23:28:02.919537 Using ethernet@4a100000 device
468 23:28:02.925137 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 23:28:02.933296 Filename '963448/tftp-deploy-opvjh0od/dtb/am335x-boneblack.dtb'.
470 23:28:02.933617 Load address: 0x88000000
471 23:28:02.962314 Loading: *################################################## 68.9 KiB
472 23:28:02.972167 2.1 MiB/s
473 23:28:02.972775 done
474 23:28:02.973176 Bytes transferred = 70568 (113a8 hex)
475 23:28:02.973862 Sending with 10 millisecond of delay
477 23:28:16.157677 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/963448/extract-nfsrootfs-dk0u5zii,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 23:28:16.168712 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
479 23:28:16.169820 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/963448/extract-nfsrootfs-dk0u5zii,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 23:28:16.170682 Sending with 10 millisecond of delay
482 23:28:18.510097 => bootz 0x82000000 0x83000000 0x88000000
483 23:28:18.521160 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 23:28:18.521945 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
485 23:28:18.523236 bootz 0x82000000 0x83000000 0x88000000
486 23:28:18.523840 Kernel image @ 0x82000000 [ 0x000000 - 0xb7c200 ]
487 23:28:18.524560 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 23:28:18.528997 Image Name:
489 23:28:18.529502 Created: 2024-11-08 23:27:20 UTC
490 23:28:18.537905 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 23:28:18.538620 Data Size: 15347068 Bytes = 14.6 MiB
492 23:28:18.545336 Load Address: 00000000
493 23:28:18.546023 Entry Point: 00000000
494 23:28:18.720927 Verifying Checksum ... OK
495 23:28:18.721329 ## Flattened Device Tree blob at 88000000
496 23:28:18.727355 Booting using the fdt blob at 0x88000000
497 23:28:18.731725 Using Device Tree in place at 88000000, end 880143a7
498 23:28:18.745866
499 23:28:18.746445 Starting kernel ...
500 23:28:18.746688
501 23:28:18.747266 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 23:28:18.747609 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
503 23:28:18.747878 Setting prompt string to ['Linux version [0-9]']
504 23:28:18.748165 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 23:28:18.748428 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 23:28:19.647036 [ 0.000000] Booting Linux on physical CPU 0x0
507 23:28:19.653228 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
508 23:28:19.653825 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 23:28:19.654279 Setting prompt string to []
510 23:28:19.654752 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 23:28:19.655201 Using line separator: #'\n'#
512 23:28:19.655602 No login prompt set.
513 23:28:19.656078 Parsing kernel messages
514 23:28:19.656483 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 23:28:19.657271 [login-action] Waiting for messages, (timeout 00:04:01)
516 23:28:19.657917 Waiting using forced prompt support (timeout 00:02:00)
517 23:28:19.668358 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j370111-arm-clang-16-multi-v7-defconfig-5q2kc) (Debian clang version 16.0.6 (15~deb12u1), Debian LLD 16.0.6) #1 SMP Fri Nov 8 22:26:11 UTC 2024
518 23:28:19.672706 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 23:28:19.681452 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 23:28:19.687279 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 23:28:19.692988 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 23:28:19.698706 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 23:28:19.701697 [ 0.000000] Memory policy: Data cache writeback
524 23:28:19.708320 [ 0.000000] efi: UEFI not found.
525 23:28:19.713106 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 23:28:19.722551 [ 0.000000] Zone ranges:
527 23:28:19.726468 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 23:28:19.731447 [ 0.000000] Normal empty
529 23:28:19.731865 [ 0.000000] HighMem empty
530 23:28:19.737157 [ 0.000000] Movable zone start for each node
531 23:28:19.737762 [ 0.000000] Early memory node ranges
532 23:28:19.748535 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 23:28:19.752853 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 23:28:19.772073 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 23:28:19.777767 [ 0.000000] AM335X ES2.1 (sgx neon)
536 23:28:19.789595 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
537 23:28:19.807303 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/963448/extract-nfsrootfs-dk0u5zii,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 23:28:19.818706 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 23:28:19.824466 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 23:28:19.831530 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 23:28:19.840520 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 23:28:19.869491 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 23:28:19.875878 <6>[ 0.000000] trace event string verifier disabled
544 23:28:19.876950 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 23:28:19.881319 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 23:28:19.894308 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 23:28:19.900052 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 23:28:19.905734 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 23:28:19.922476 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 23:28:19.938684 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 23:28:19.944919 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 23:28:20.045430 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 23:28:20.054095 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 23:28:20.066684 <6>[ 0.008339] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 23:28:20.074057 <6>[ 0.019193] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 23:28:20.084350 <6>[ 0.034235] Console: colour dummy device 80x30
557 23:28:20.090199 Matched prompt #6: WARNING:
558 23:28:20.090628 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 23:28:20.095817 <3>[ 0.039135] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 23:28:20.099437 <3>[ 0.046212] This ensures that you still see kernel messages. Please
561 23:28:20.104476 <3>[ 0.052939] update your kernel commandline.
562 23:28:20.145364 <6>[ 0.057556] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 23:28:20.151005 <6>[ 0.096200] CPU: Testing write buffer coherency: ok
564 23:28:20.154117 <6>[ 0.101567] CPU0: Spectre v2: using BPIALL workaround
565 23:28:20.159737 <6>[ 0.107033] pid_max: default: 32768 minimum: 301
566 23:28:20.166241 <6>[ 0.112227] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 23:28:20.178067 <6>[ 0.120054] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 23:28:20.185161 <6>[ 0.129439] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 23:28:20.190020 <6>[ 0.136464] Setting up static identity map for 0x80300000 - 0x803000ac
570 23:28:20.196282 <6>[ 0.146178] rcu: Hierarchical SRCU implementation.
571 23:28:20.203375 <6>[ 0.151471] rcu: Max phase no-delay instances is 1000.
572 23:28:20.213177 <6>[ 0.162864] EFI services will not be available.
573 23:28:20.219020 <6>[ 0.168157] smp: Bringing up secondary CPUs ...
574 23:28:20.224805 <6>[ 0.173218] smp: Brought up 1 node, 1 CPU
575 23:28:20.232986 <6>[ 0.177620] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 23:28:20.238890 <6>[ 0.184394] CPU: All CPU(s) started in SVC mode.
577 23:28:20.251165 <6>[ 0.189604] Memory: 404436K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50612K reserved, 65536K cma-reserved, 0K highmem)
578 23:28:20.256884 <6>[ 0.205910] devtmpfs: initialized
579 23:28:20.279844 <6>[ 0.223792] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 23:28:20.288076 <6>[ 0.232410] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 23:28:20.297298 <6>[ 0.242870] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 23:28:20.307156 <6>[ 0.255258] pinctrl core: initialized pinctrl subsystem
583 23:28:20.317773 <6>[ 0.266115] DMI not present or invalid.
584 23:28:20.326032 <6>[ 0.272029] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 23:28:20.335498 <6>[ 0.281024] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 23:28:20.350815 <6>[ 0.292736] thermal_sys: Registered thermal governor 'step_wise'
587 23:28:20.351364 <6>[ 0.292931] cpuidle: using governor menu
588 23:28:20.378574 <6>[ 0.328410] No ATAGs?
589 23:28:20.385651 <6>[ 0.331149] hw-breakpoint: debug architecture 0x4 unsupported.
590 23:28:20.395181 <6>[ 0.343324] Serial: AMBA PL011 UART driver
591 23:28:20.425491 <6>[ 0.375433] iommu: Default domain type: Translated
592 23:28:20.435440 <6>[ 0.380783] iommu: DMA domain TLB invalidation policy: strict mode
593 23:28:20.461499 <5>[ 0.410643] SCSI subsystem initialized
594 23:28:20.473071 <6>[ 0.415560] usbcore: registered new interface driver usbfs
595 23:28:20.473569 <6>[ 0.421628] usbcore: registered new interface driver hub
596 23:28:20.479891 <6>[ 0.427423] usbcore: registered new device driver usb
597 23:28:20.485573 <6>[ 0.434001] pps_core: LinuxPPS API ver. 1 registered
598 23:28:20.497070 <6>[ 0.439391] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 23:28:20.504479 <6>[ 0.449123] PTP clock support registered
600 23:28:20.504917 <6>[ 0.453609] EDAC MC: Ver: 3.0.0
601 23:28:20.557557 <6>[ 0.505778] scmi_core: SCMI protocol bus registered
602 23:28:20.573199 <6>[ 0.522464] vgaarb: loaded
603 23:28:20.578367 <6>[ 0.526259] clocksource: Switched to clocksource dmtimer
604 23:28:20.614217 <6>[ 0.563860] NET: Registered PF_INET protocol family
605 23:28:20.626990 <6>[ 0.569569] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 23:28:20.634345 <6>[ 0.578582] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 23:28:20.644265 <6>[ 0.587513] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 23:28:20.649905 <6>[ 0.595758] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 23:28:20.661460 <6>[ 0.604047] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 23:28:20.667320 <6>[ 0.611775] TCP: Hash tables configured (established 4096 bind 4096)
611 23:28:20.673104 <6>[ 0.618694] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 23:28:20.679010 <6>[ 0.625706] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 23:28:20.687463 <6>[ 0.633311] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 23:28:20.779003 <6>[ 0.723354] RPC: Registered named UNIX socket transport module.
615 23:28:20.779430 <6>[ 0.729809] RPC: Registered udp transport module.
616 23:28:20.784740 <6>[ 0.734916] RPC: Registered tcp transport module.
617 23:28:20.793436 <6>[ 0.740036] RPC: Registered tcp-with-tls transport module.
618 23:28:20.799050 <6>[ 0.745949] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 23:28:20.806425 <6>[ 0.752871] PCI: CLS 0 bytes, default 64
620 23:28:20.809656 <5>[ 0.758760] Initialise system trusted keyrings
621 23:28:20.828084 <6>[ 0.776135] Trying to unpack rootfs image as initramfs...
622 23:28:20.902932 <6>[ 0.846629] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 23:28:20.906963 <6>[ 0.854157] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 23:28:20.943694 <5>[ 0.893565] NFS: Registering the id_resolver key type
625 23:28:20.949399 <5>[ 0.899230] Key type id_resolver registered
626 23:28:20.955159 <5>[ 0.903809] Key type id_legacy registered
627 23:28:20.964021 <6>[ 0.908276] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 23:28:20.970010 <6>[ 0.915446] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 23:28:21.029513 <5>[ 0.979236] Key type asymmetric registered
630 23:28:21.037802 <5>[ 0.983761] Asymmetric key parser 'x509' registered
631 23:28:21.046780 <6>[ 0.989256] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 23:28:21.047377 <6>[ 0.997179] io scheduler mq-deadline registered
633 23:28:21.053593 <6>[ 1.002107] io scheduler kyber registered
634 23:28:21.058101 <6>[ 1.006577] io scheduler bfq registered
635 23:28:21.180351 <6>[ 1.126753] ledtrig-cpu: registered to indicate activity on CPUs
636 23:28:21.450477 <6>[ 1.396618] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 23:28:21.492080 <6>[ 1.441734] msm_serial: driver initialized
638 23:28:21.497844 <6>[ 1.446742] SuperH (H)SCI(F) driver initialized
639 23:28:21.503813 <6>[ 1.451864] STMicroelectronics ASC driver initialized
640 23:28:21.508962 <6>[ 1.457542] STM32 USART driver initialized
641 23:28:21.620873 <6>[ 1.570373] brd: module loaded
642 23:28:21.660251 <6>[ 1.610725] loop: module loaded
643 23:28:21.704647 <6>[ 1.653961] CAN device driver interface
644 23:28:21.711245 <6>[ 1.659175] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 23:28:21.717068 <6>[ 1.666153] e1000e: Intel(R) PRO/1000 Network Driver
646 23:28:21.722842 <6>[ 1.671602] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 23:28:21.728545 <6>[ 1.678071] igb: Intel(R) Gigabit Ethernet Network Driver
648 23:28:21.736850 <6>[ 1.683894] igb: Copyright (c) 2007-2014 Intel Corporation.
649 23:28:21.748853 <6>[ 1.693203] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 23:28:21.754570 <6>[ 1.699386] usbcore: registered new interface driver pegasus
651 23:28:21.757287 <6>[ 1.705515] usbcore: registered new interface driver asix
652 23:28:21.762999 <6>[ 1.711405] usbcore: registered new interface driver ax88179_178a
653 23:28:21.768842 <6>[ 1.717998] usbcore: registered new interface driver cdc_ether
654 23:28:21.774539 <6>[ 1.724296] usbcore: registered new interface driver smsc75xx
655 23:28:21.783091 <6>[ 1.730540] usbcore: registered new interface driver smsc95xx
656 23:28:21.788931 <6>[ 1.736782] usbcore: registered new interface driver net1080
657 23:28:21.794676 <6>[ 1.742905] usbcore: registered new interface driver cdc_subset
658 23:28:21.800454 <6>[ 1.749320] usbcore: registered new interface driver zaurus
659 23:28:21.807458 <6>[ 1.755371] usbcore: registered new interface driver cdc_ncm
660 23:28:21.817692 <6>[ 1.764901] usbcore: registered new interface driver usb-storage
661 23:28:21.827556 <6>[ 1.776098] i2c_dev: i2c /dev entries driver
662 23:28:21.852536 <5>[ 1.794717] cpuidle: enable-method property 'ti,am3352' found operations
663 23:28:21.858372 <6>[ 1.804307] sdhci: Secure Digital Host Controller Interface driver
664 23:28:21.866222 <6>[ 1.811085] sdhci: Copyright(c) Pierre Ossman
665 23:28:21.873290 <6>[ 1.817627] Synopsys Designware Multimedia Card Interface Driver
666 23:28:21.877551 <6>[ 1.825438] sdhci-pltfm: SDHCI platform and OF driver helper
667 23:28:21.891699 <6>[ 1.835402] usbcore: registered new interface driver usbhid
668 23:28:21.892202 <6>[ 1.841532] usbhid: USB HID core driver
669 23:28:21.904662 <6>[ 1.853203] NET: Registered PF_INET6 protocol family
670 23:28:22.349106 <6>[ 2.299255] Segment Routing with IPv6
671 23:28:22.354926 <6>[ 2.303406] In-situ OAM (IOAM) with IPv6
672 23:28:22.361701 <6>[ 2.307955] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 23:28:22.368991 <6>[ 2.315318] NET: Registered PF_PACKET protocol family
674 23:28:22.374873 <6>[ 2.320880] can: controller area network core
675 23:28:22.375315 <6>[ 2.325715] NET: Registered PF_CAN protocol family
676 23:28:22.380611 <6>[ 2.330962] can: raw protocol
677 23:28:22.383425 <6>[ 2.334288] can: broadcast manager protocol
678 23:28:22.389883 <6>[ 2.338899] can: netlink gateway - max_hops=1
679 23:28:22.396027 <5>[ 2.344408] Key type dns_resolver registered
680 23:28:22.401765 <6>[ 2.349489] ThumbEE CPU extension supported.
681 23:28:22.403591 <5>[ 2.354182] Registering SWP/SWPB emulation handler
682 23:28:22.412662 <3>[ 2.359881] omap_voltage_late_init: Voltage driver support not added
683 23:28:22.623862 <5>[ 2.572588] Loading compiled-in X.509 certificates
684 23:28:22.774346 <6>[ 2.711639] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 23:28:22.780604 <6>[ 2.728368] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 23:28:22.807379 <3>[ 2.752480] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 23:28:23.001574 <3>[ 2.946727] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 23:28:23.197516 <6>[ 3.146950] OMAP GPIO hardware version 0.1
689 23:28:23.219391 <6>[ 3.165943] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 23:28:23.301833 <4>[ 3.248137] at24 2-0054: supply vcc not found, using dummy regulator
691 23:28:23.336122 <4>[ 3.282322] at24 2-0055: supply vcc not found, using dummy regulator
692 23:28:23.374185 <4>[ 3.320486] at24 2-0056: supply vcc not found, using dummy regulator
693 23:28:23.413920 <4>[ 3.360099] at24 2-0057: supply vcc not found, using dummy regulator
694 23:28:23.452436 <6>[ 3.399468] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 23:28:23.510457 <3>[ 3.453406] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 23:28:23.535280 <6>[ 3.474626] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 23:28:23.557863 <4>[ 3.501643] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 23:28:23.565707 <4>[ 3.510607] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 23:28:23.649785 <6>[ 3.598906] Freeing initrd memory: 14988K
700 23:28:23.658054 <6>[ 3.604395] omap_rng 48310000.rng: Random Number Generator ver. 20
701 23:28:23.682189 <5>[ 3.631300] random: crng init done
702 23:28:23.731390 <6>[ 3.676253] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 23:28:23.784707 <6>[ 3.728714] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 23:28:23.790579 <6>[ 3.739055] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 23:28:23.802367 <6>[ 3.746392] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 23:28:23.808206 <6>[ 3.753866] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 23:28:23.819761 <6>[ 3.761996] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 23:28:23.827218 <6>[ 3.773644] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
709 23:28:23.839416 <5>[ 3.782753] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 23:28:23.868641 <3>[ 3.813152] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 23:28:23.874456 <6>[ 3.821753] edma 49000000.dma: TI EDMA DMA engine driver
712 23:28:23.947056 <3>[ 3.890943] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 23:28:23.961884 <6>[ 3.905445] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 23:28:23.975010 <3>[ 3.922719] l3-aon-clkctrl:0000:0: failed to disable
715 23:28:24.030548 <6>[ 3.975033] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 23:28:24.036257 <6>[ 3.984556] printk: legacy console [ttyS0] enabled
717 23:28:24.039033 <6>[ 3.984556] printk: legacy console [ttyS0] enabled
718 23:28:24.044571 <6>[ 3.994896] printk: legacy bootconsole [omap8250] disabled
719 23:28:24.052501 <6>[ 3.994896] printk: legacy bootconsole [omap8250] disabled
720 23:28:24.083585 <4>[ 4.027081] tps65217-pmic: Failed to locate of_node [id: -1]
721 23:28:24.086243 <4>[ 4.034494] tps65217-bl: Failed to locate of_node [id: -1]
722 23:28:24.104115 <6>[ 4.054609] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 23:28:24.124423 <6>[ 4.061630] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 23:28:24.136176 <6>[ 4.075323] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 23:28:24.138669 <6>[ 4.087207] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 23:28:24.162598 <6>[ 4.107406] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 23:28:24.168447 <6>[ 4.116607] sdhci-omap 48060000.mmc: Got CD GPIO
728 23:28:24.176523 <4>[ 4.121759] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 23:28:24.191593 <4>[ 4.135647] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 23:28:24.197919 <4>[ 4.144449] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 23:28:24.207865 <4>[ 4.153078] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 23:28:24.307243 <6>[ 4.253222] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 23:28:24.346862 <6>[ 4.291966] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 23:28:24.367399 <6>[ 4.311465] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 23:28:24.374099 <6>[ 4.320445] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 23:28:24.415875 <6>[ 4.356344] mmc0: new high speed SDHC card at address 1234
737 23:28:24.416537 <6>[ 4.364262] mmcblk0: mmc0:1234 SA32G 29.1 GiB
738 23:28:24.422156 <6>[ 4.373431] mmcblk0: p1
739 23:28:24.455312 <6>[ 4.397549] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
740 23:28:24.478833 <6>[ 4.420074] mmc1: new high speed MMC card at address 0001
741 23:28:24.479311 <6>[ 4.427236] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
742 23:28:24.487264 <6>[ 4.435047] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
743 23:28:24.495518 <6>[ 4.443075] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
744 23:28:24.501157 <6>[ 4.450883] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
745 23:28:26.572696 <6>[ 6.517313] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 23:28:26.636802 <5>[ 6.546272] Sending DHCP requests ., OK
747 23:28:26.647393 <6>[ 6.590807] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
748 23:28:26.647913 <6>[ 6.599006] IP-Config: Complete:
749 23:28:26.659736 <6>[ 6.602546] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
750 23:28:26.665102 <6>[ 6.613068] host=192.168.6.12, domain=, nis-domain=(none)
751 23:28:26.676773 <6>[ 6.619282] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
752 23:28:26.677087 <6>[ 6.619319] nameserver0=10.255.253.1
753 23:28:26.683420 <6>[ 6.631947] clk: Disabling unused clocks
754 23:28:26.691894 <6>[ 6.636700] PM: genpd: Disabling unused power domains
755 23:28:26.706423 <6>[ 6.653461] Freeing unused kernel image (initmem) memory: 2048K
756 23:28:26.713981 <6>[ 6.663325] Run /init as init process
757 23:28:26.740713 Loading, please wait...
758 23:28:26.818501 Starting systemd-udevd version 252.22-1~deb12u1
759 23:28:29.988445 <4>[ 9.931432] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 23:28:30.183928 <4>[ 10.127204] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 23:28:30.332406 <6>[ 10.283040] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
762 23:28:30.343350 <6>[ 10.288877] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
763 23:28:30.598860 <6>[ 10.547872] hub 1-0:1.0: USB hub found
764 23:28:30.639402 <6>[ 10.588112] tda998x 0-0070: found TDA19988
765 23:28:30.667532 <6>[ 10.616484] hub 1-0:1.0: 1 port detected
766 23:28:33.521074 Begin: Loading essential drivers ... done.
767 23:28:33.526718 Begin: Running /scripts/init-premount ... done.
768 23:28:33.532138 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
769 23:28:33.546057 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
770 23:28:33.546442 Device /sys/class/net/eth0 found
771 23:28:33.546678 done.
772 23:28:33.627187 Begin: Waiting up to 180 secs for any network device to become available ... done.
773 23:28:33.698610 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
774 23:28:33.742722 IP-Config: eth0 guessed broadcast address 192.168.6.255
775 23:28:33.748146 IP-Config: eth0 complete (dhcp from 192.168.6.1):
776 23:28:33.753683 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
777 23:28:33.764947 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
778 23:28:33.765474 rootserver: 192.168.6.1 rootpath:
779 23:28:33.768397 filename :
780 23:28:33.888953 done.
781 23:28:33.906211 Begin: Running /scripts/nfs-bottom ... done.
782 23:28:33.970933 Begin: Running /scripts/init-bottom ... done.
783 23:28:35.562561 <30>[ 15.509086] systemd[1]: System time before build time, advancing clock.
784 23:28:35.748058 <30>[ 15.668477] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 23:28:35.756870 <30>[ 15.705231] systemd[1]: Detected architecture arm.
786 23:28:35.769625
787 23:28:35.769979 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 23:28:35.770196
789 23:28:35.799250 <30>[ 15.747109] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 23:28:38.057970 <30>[ 18.004309] systemd[1]: Queued start job for default target graphical.target.
791 23:28:38.075179 <30>[ 18.019435] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 23:28:38.082763 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 23:28:38.104748 <30>[ 18.049304] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 23:28:38.113207 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 23:28:38.135241 <30>[ 18.079694] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 23:28:38.143562 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 23:28:38.163722 <30>[ 18.108287] systemd[1]: Created slice user.slice - User and Session Slice.
798 23:28:38.170357 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 23:28:38.198895 <30>[ 18.137657] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 23:28:38.204944 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 23:28:38.222799 <30>[ 18.167431] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 23:28:38.233731 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 23:28:38.264011 <30>[ 18.197655] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 23:28:38.271154 <30>[ 18.218286] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 23:28:38.279645 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 23:28:38.301790 <30>[ 18.246755] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 23:28:38.310044 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 23:28:38.332612 <30>[ 18.277192] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 23:28:38.341086 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 23:28:38.362599 <30>[ 18.307488] systemd[1]: Reached target paths.target - Path Units.
811 23:28:38.367696 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 23:28:38.392212 <30>[ 18.337110] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 23:28:38.399616 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 23:28:38.421967 <30>[ 18.366854] systemd[1]: Reached target slices.target - Slice Units.
815 23:28:38.427397 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 23:28:38.452153 <30>[ 18.397057] systemd[1]: Reached target swap.target - Swaps.
817 23:28:38.456196 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 23:28:38.482317 <30>[ 18.426999] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 23:28:38.490357 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 23:28:38.513432 <30>[ 18.457867] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 23:28:38.521745 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 23:28:38.604427 <30>[ 18.544207] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 23:28:38.617353 <30>[ 18.561895] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 23:28:38.625859 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 23:28:38.654190 <30>[ 18.598056] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 23:28:38.661548 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 23:28:38.685778 <30>[ 18.630120] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 23:28:38.693990 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 23:28:38.717230 <30>[ 18.661560] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 23:28:38.722927 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 23:28:38.754331 <30>[ 18.699674] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 23:28:38.767447 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 23:28:38.799629 <30>[ 18.738078] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 23:28:38.816230 <30>[ 18.754777] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 23:28:38.866442 <30>[ 18.811854] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 23:28:38.892229 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 23:28:38.934366 <30>[ 18.879689] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 23:28:38.959328 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 23:28:39.004479 <30>[ 18.948843] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 23:28:39.021128 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 23:28:39.092443 <30>[ 19.037436] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 23:28:39.121994 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 23:28:39.172803 <30>[ 19.118198] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 23:28:39.191732 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 23:28:39.254560 <30>[ 19.200456] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 23:28:39.280078 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 23:28:39.332806 <30>[ 19.277519] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 23:28:39.354599 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 23:28:39.404215 <30>[ 19.349934] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 23:28:39.431836 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 23:28:39.487877 <30>[ 19.433615] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 23:28:39.509162 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 23:28:39.541046 <28>[ 19.478764] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 23:28:39.549615 <28>[ 19.494342] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 23:28:39.593695 <30>[ 19.539824] systemd[1]: Starting systemd-journald.service - Journal Service...
856 23:28:39.612067 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 23:28:39.681957 <30>[ 19.627451] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 23:28:39.701591 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 23:28:39.725147 <30>[ 19.670865] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 23:28:39.774522 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 23:28:39.845506 <30>[ 19.789741] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 23:28:39.891869 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 23:28:39.954671 <30>[ 19.899835] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 23:28:40.013654 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 23:28:40.106560 <30>[ 20.052838] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 23:28:40.152794 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 23:28:40.182867 <30>[ 20.128594] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 23:28:40.206458 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 23:28:40.237691 <30>[ 20.182516] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 23:28:40.264675 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 23:28:40.392614 <30>[ 20.339546] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 23:28:40.431674 <30>[ 20.376997] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 23:28:40.461121 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 23:28:40.492614 <30>[ 20.439187] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
875 23:28:40.521575 <30>[ 20.468093] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
876 23:28:40.541663 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 23:28:40.562984 <30>[ 20.507998] systemd[1]: Started systemd-journald.service - Journal Service.
878 23:28:40.569857 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
879 23:28:40.603405 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
880 23:28:40.633397 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
881 23:28:40.657836 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
882 23:28:40.693049 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
883 23:28:40.723631 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
884 23:28:40.745306 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
885 23:28:40.773960 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
886 23:28:40.795766 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
887 23:28:40.861566 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
888 23:28:40.913737 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
889 23:28:40.973838 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
890 23:28:41.062096 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
891 23:28:41.123322 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
892 23:28:41.274094 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
893 23:28:41.382066 <46>[ 21.328610] systemd-journald[163]: Received client request to flush runtime journal.
894 23:28:41.465106 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
895 23:28:41.555036 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
896 23:28:42.363718 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
897 23:28:42.434057 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
898 23:28:43.132069 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
899 23:28:43.294175 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
900 23:28:43.322681 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
901 23:28:43.341586 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
902 23:28:43.412263 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
903 23:28:43.462090 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
904 23:28:44.482063 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
905 23:28:44.554191 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
906 23:28:44.661535 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
907 23:28:44.723223 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
908 23:28:44.772466 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
909 23:28:45.697766 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
910 23:28:47.252736 <5>[ 27.198905] cfg80211: Loading compiled-in X.509 certificates for regulatory database
911 23:28:47.709992 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
912 23:28:48.400124 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
913 23:28:48.872971 <5>[ 28.821100] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
914 23:28:48.951264 <5>[ 28.898099] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
915 23:28:48.986683 <4>[ 28.932691] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
916 23:28:48.992570 <6>[ 28.941850] cfg80211: failed to load regulatory.db
917 23:28:49.388382 <46>[ 29.324540] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
918 23:28:49.499030 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
919 23:28:49.567250 <46>[ 29.506481] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
920 23:28:50.230999 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
921 23:28:58.984828 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
922 23:28:59.012463 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
923 23:28:59.032766 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
924 23:28:59.056297 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
925 23:28:59.121482 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
926 23:28:59.173421 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
927 23:28:59.222468 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
928 23:28:59.263226 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
929 23:28:59.336810 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
930 23:28:59.368157 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
931 23:28:59.396267 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
932 23:28:59.438792 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
933 23:28:59.478082 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
934 23:28:59.514330 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
935 23:28:59.548860 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
936 23:28:59.582300 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
937 23:28:59.612363 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
938 23:28:59.637035 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
939 23:28:59.662706 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
940 23:28:59.684279 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
941 23:28:59.733949 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
942 23:28:59.749974 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
943 23:28:59.774211 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
944 23:28:59.851925 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
945 23:28:59.920901 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
946 23:29:00.016534 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
947 23:29:00.113655 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
948 23:29:00.174079 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
949 23:29:00.249053 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
950 23:29:00.271824 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
951 23:29:00.461484 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
952 23:29:00.512496 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
953 23:29:00.583216 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
954 23:29:00.601909 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
955 23:29:00.622984 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
956 23:29:00.871664 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
957 23:29:01.208236 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
958 23:29:01.263905 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
959 23:29:01.306614 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
960 23:29:01.401167 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
961 23:29:01.582388 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
962 23:29:01.738023
963 23:29:01.741789 Debian GNU/Linux 12 debiaworm-armhf login: root (automatic login)
964 23:29:01.742135
965 23:29:02.132495 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Fri Nov 8 22:26:11 UTC 2024 armv7l
966 23:29:02.133075
967 23:29:02.138063 The programs included with the Debian GNU/Linux system are free software;
968 23:29:02.144019 the exact distribution terms for each program are described in the
969 23:29:02.149327 individual files in /usr/share/doc/*/copyright.
970 23:29:02.149662
971 23:29:02.157706 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
972 23:29:02.158064 permitted by applicable law.
973 23:29:06.988147 Unable to match end of the kernel message
975 23:29:06.989061 Setting prompt string to ['/ #']
976 23:29:06.989369 end: 2.4.4.1 login-action (duration 00:00:47) [common]
978 23:29:06.990084 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
979 23:29:06.990361 start: 2.4.5 expect-shell-connection (timeout 00:03:14) [common]
980 23:29:06.990586 Setting prompt string to ['/ #']
981 23:29:06.990793 Forcing a shell prompt, looking for ['/ #']
983 23:29:07.041551 / #
984 23:29:07.042196 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
985 23:29:07.042481 Waiting using forced prompt support (timeout 00:02:30)
986 23:29:07.045847
987 23:29:07.055870 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
988 23:29:07.056283 start: 2.4.6 export-device-env (timeout 00:03:14) [common]
989 23:29:07.056544 Sending with 10 millisecond of delay
991 23:29:12.046921 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/963448/extract-nfsrootfs-dk0u5zii'
992 23:29:12.057958 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/963448/extract-nfsrootfs-dk0u5zii'
993 23:29:12.058838 Sending with 10 millisecond of delay
995 23:29:14.159068 / # export NFS_SERVER_IP='192.168.6.2'
996 23:29:14.170059 export NFS_SERVER_IP='192.168.6.2'
997 23:29:14.171033 end: 2.4.6 export-device-env (duration 00:00:07) [common]
998 23:29:14.171676 end: 2.4 uboot-commands (duration 00:01:54) [common]
999 23:29:14.172098 end: 2 uboot-action (duration 00:01:54) [common]
1000 23:29:14.172428 start: 3 lava-test-retry (timeout 00:06:55) [common]
1001 23:29:14.172738 start: 3.1 lava-test-shell (timeout 00:06:55) [common]
1002 23:29:14.172986 Using namespace: common
1004 23:29:14.274283 / # #
1005 23:29:14.274857 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1006 23:29:14.279172 #
1007 23:29:14.285496 Using /lava-963448
1009 23:29:14.386318 / # export SHELL=/bin/bash
1010 23:29:14.391371 export SHELL=/bin/bash
1012 23:29:14.498041 / # . /lava-963448/environment
1013 23:29:14.503675 . /lava-963448/environment
1015 23:29:14.617731 / # /lava-963448/bin/lava-test-runner /lava-963448/0
1016 23:29:14.618450 Test shell timeout: 10s (minimum of the action and connection timeout)
1017 23:29:14.622831 /lava-963448/bin/lava-test-runner /lava-963448/0
1018 23:29:15.077241 + export TESTRUN_ID=0_timesync-off
1019 23:29:15.085498 + TESTRUN_ID=0_timesync-off
1020 23:29:15.085862 + cd /lava-963448/0/tests/0_timesync-off
1021 23:29:15.086102 ++ cat uuid
1022 23:29:15.101345 + UUID=963448_1.6.2.4.1
1023 23:29:15.101882 + set +x
1024 23:29:15.109907 <LAVA_SIGNAL_STARTRUN 0_timesync-off 963448_1.6.2.4.1>
1025 23:29:15.110361 + systemctl stop systemd-timesyncd
1026 23:29:15.110854 Received signal: <STARTRUN> 0_timesync-off 963448_1.6.2.4.1
1027 23:29:15.111131 Starting test lava.0_timesync-off (963448_1.6.2.4.1)
1028 23:29:15.111408 Skipping test definition patterns.
1029 23:29:15.377618 + set +x
1030 23:29:15.378051 <LAVA_SIGNAL_ENDRUN 0_timesync-off 963448_1.6.2.4.1>
1031 23:29:15.378499 Received signal: <ENDRUN> 0_timesync-off 963448_1.6.2.4.1
1032 23:29:15.378785 Ending use of test pattern.
1033 23:29:15.378996 Ending test lava.0_timesync-off (963448_1.6.2.4.1), duration 0.27
1035 23:29:15.587081 + export TESTRUN_ID=1_kselftest-dt
1036 23:29:15.594981 + TESTRUN_ID=1_kselftest-dt
1037 23:29:15.595442 + cd /lava-963448/0/tests/1_kselftest-dt
1038 23:29:15.595703 ++ cat uuid
1039 23:29:15.611799 + UUID=963448_1.6.2.4.5
1040 23:29:15.612350 + set +x
1041 23:29:15.617359 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 963448_1.6.2.4.5>
1042 23:29:15.617675 + cd ./automated/linux/kselftest/
1043 23:29:15.618162 Received signal: <STARTRUN> 1_kselftest-dt 963448_1.6.2.4.5
1044 23:29:15.618544 Starting test lava.1_kselftest-dt (963448_1.6.2.4.5)
1045 23:29:15.618926 Skipping test definition patterns.
1046 23:29:15.645847 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1047 23:29:15.751689 INFO: install_deps skipped
1048 23:29:16.361643 --2024-11-08 23:29:16-- http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz
1049 23:29:16.394208 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1050 23:29:16.535931 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1051 23:29:16.680435 HTTP request sent, awaiting response... 200 OK
1052 23:29:16.681002 Length: 2557756 (2.4M) [application/octet-stream]
1053 23:29:16.685851 Saving to: 'kselftest_armhf.tar.gz'
1054 23:29:16.686155
1055 23:29:17.911325
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 181KB/s
kselftest_armhf.tar 8%[> ] 218.67K 394KB/s
kselftest_armhf.tar 35%[======> ] 893.67K 1.05MB/s
kselftest_armhf.tar 69%[============> ] 1.69M 1.59MB/s
kselftest_armhf.tar 100%[===================>] 2.44M 1.99MB/s in 1.2s
1056 23:29:17.911761
1057 23:29:18.224208 2024-11-08 23:29:17 (1.99 MB/s) - 'kselftest_armhf.tar.gz' saved [2557756/2557756]
1058 23:29:18.224852
1059 23:29:29.256522 skiplist:
1060 23:29:29.256956 ========================================
1061 23:29:29.261346 ========================================
1062 23:29:29.362014 dt:test_unprobed_devices.sh
1063 23:29:29.394746 ============== Tests to run ===============
1064 23:29:29.403235 dt:test_unprobed_devices.sh
1065 23:29:29.407227 ===========End Tests to run ===============
1066 23:29:29.417779 shardfile-dt pass
1067 23:29:29.650532 <12>[ 69.602409] kselftest: Running tests in dt
1068 23:29:29.679731 TAP version 13
1069 23:29:29.704929 1..1
1070 23:29:29.760732 # timeout set to 45
1071 23:29:29.761102 # selftests: dt: test_unprobed_devices.sh
1072 23:29:30.596203 # TAP version 13
1073 23:29:56.231058 # 1..257
1074 23:29:56.424586 # ok 1 / # SKIP
1075 23:29:56.449850 # ok 2 /clk_mcasp0
1076 23:29:56.525234 # ok 3 /clk_mcasp0_fixed # SKIP
1077 23:29:56.597633 # ok 4 /cpus/cpu@0 # SKIP
1078 23:29:56.671649 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1079 23:29:56.697037 # ok 6 /fixedregulator0
1080 23:29:56.711470 # ok 7 /leds
1081 23:29:56.737624 # ok 8 /ocp
1082 23:29:56.757450 # ok 9 /ocp/interconnect@44c00000
1083 23:29:56.786461 # ok 10 /ocp/interconnect@44c00000/segment@0
1084 23:29:56.806287 # ok 11 /ocp/interconnect@44c00000/segment@100000
1085 23:29:56.833698 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1086 23:29:56.908818 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1087 23:29:56.924871 # ok 14 /ocp/interconnect@44c00000/segment@200000
1088 23:29:56.950326 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1089 23:29:57.064445 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1090 23:29:57.138032 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1091 23:29:57.212631 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1092 23:29:57.293559 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1093 23:29:57.362123 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1094 23:29:57.437350 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1095 23:29:57.512564 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1096 23:29:57.585667 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1097 23:29:57.661310 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1098 23:29:57.741724 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1099 23:29:57.815763 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1100 23:29:57.886692 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1101 23:29:57.964282 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1102 23:29:58.036708 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1103 23:29:58.109739 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1104 23:29:58.183186 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1105 23:29:58.262066 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1106 23:29:58.337116 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1107 23:29:58.412300 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1108 23:29:58.486420 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1109 23:29:58.556520 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1110 23:29:58.629379 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1111 23:29:58.703588 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1112 23:29:58.780236 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1113 23:29:58.851490 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1114 23:29:58.925457 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1115 23:29:59.004782 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1116 23:29:59.078216 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1117 23:29:59.153796 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1118 23:29:59.223875 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1119 23:29:59.300594 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1120 23:29:59.371965 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1121 23:29:59.447017 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1122 23:29:59.522048 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1123 23:29:59.596008 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1124 23:29:59.669897 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1125 23:29:59.744137 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1126 23:29:59.825699 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1127 23:29:59.895936 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1128 23:29:59.970286 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1129 23:30:00.044834 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1130 23:30:00.122958 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1131 23:30:00.194194 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1132 23:30:00.269808 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1133 23:30:00.347117 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1134 23:30:00.423588 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1135 23:30:00.500479 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1136 23:30:00.576464 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1137 23:30:00.647775 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1138 23:30:00.720681 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1139 23:30:00.795552 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1140 23:30:00.870698 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1141 23:30:00.943902 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1142 23:30:01.021815 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1143 23:30:01.097811 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1144 23:30:01.174980 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1145 23:30:01.242928 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1146 23:30:01.321882 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1147 23:30:01.397146 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1148 23:30:01.469726 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1149 23:30:01.542119 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1150 23:30:01.618288 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1151 23:30:01.691102 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1152 23:30:01.765575 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1153 23:30:01.844532 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1154 23:30:01.914542 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1155 23:30:01.988632 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1156 23:30:02.061663 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1157 23:30:02.142881 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1158 23:30:02.216308 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1159 23:30:02.287801 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1160 23:30:02.361952 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1161 23:30:02.436542 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1162 23:30:02.512961 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1163 23:30:02.588517 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1164 23:30:02.660686 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1165 23:30:02.736802 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1166 23:30:02.810851 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1167 23:30:02.884542 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1168 23:30:02.911101 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1169 23:30:02.935445 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1170 23:30:02.957375 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1171 23:30:02.985088 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1172 23:30:03.011034 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1173 23:30:03.035298 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1174 23:30:03.057002 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1175 23:30:03.080721 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1176 23:30:03.193868 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1177 23:30:03.215924 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1178 23:30:03.240132 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1179 23:30:03.265771 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1180 23:30:03.373781 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1181 23:30:03.451061 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1182 23:30:03.524659 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1183 23:30:03.599733 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1184 23:30:03.674305 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1185 23:30:03.751299 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1186 23:30:03.822153 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1187 23:30:03.898323 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1188 23:30:03.972248 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1189 23:30:04.047304 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1190 23:30:04.121743 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1191 23:30:04.195916 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1192 23:30:04.273976 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1193 23:30:04.349959 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1194 23:30:04.422995 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1195 23:30:04.497421 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1196 23:30:04.519779 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1197 23:30:04.592373 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1198 23:30:04.663914 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1199 23:30:04.739036 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1200 23:30:04.761649 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1201 23:30:04.836073 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1202 23:30:04.859045 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1203 23:30:04.932411 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1204 23:30:04.956405 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1205 23:30:04.984814 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1206 23:30:05.004665 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1207 23:30:05.029727 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1208 23:30:05.054190 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1209 23:30:05.078055 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1210 23:30:05.104226 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1211 23:30:05.181191 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1212 23:30:05.204249 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1213 23:30:05.227762 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1214 23:30:05.304329 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1215 23:30:05.377485 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1216 23:30:05.399570 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1217 23:30:05.503816 # not ok 144 /ocp/interconnect@47c00000
1218 23:30:05.577863 # not ok 145 /ocp/interconnect@47c00000/segment@0
1219 23:30:05.601218 # ok 146 /ocp/interconnect@48000000
1220 23:30:05.623748 # ok 147 /ocp/interconnect@48000000/segment@0
1221 23:30:05.653375 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1222 23:30:05.672614 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1223 23:30:05.701037 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1224 23:30:05.723801 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1225 23:30:05.744608 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1226 23:30:05.769381 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1227 23:30:05.792364 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1228 23:30:05.866672 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1229 23:30:05.941030 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1230 23:30:05.968083 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1231 23:30:05.992866 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1232 23:30:06.015538 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1233 23:30:06.036751 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1234 23:30:06.063895 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1235 23:30:06.085936 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1236 23:30:06.113727 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1237 23:30:06.141589 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1238 23:30:06.162987 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1239 23:30:06.187062 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1240 23:30:06.208293 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1241 23:30:06.232623 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1242 23:30:06.255886 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1243 23:30:06.284423 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1244 23:30:06.313054 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1245 23:30:06.329099 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1246 23:30:06.352416 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1247 23:30:06.382360 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1248 23:30:06.402775 # ok 175 /ocp/interconnect@48000000/segment@100000
1249 23:30:06.429970 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1250 23:30:06.451703 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1251 23:30:06.531865 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1252 23:30:06.607774 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1253 23:30:06.678702 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1254 23:30:06.753497 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1255 23:30:06.825810 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1256 23:30:06.901839 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1257 23:30:06.974275 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1258 23:30:07.050756 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1259 23:30:07.070578 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1260 23:30:07.096693 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1261 23:30:07.122999 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1262 23:30:07.145006 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1263 23:30:07.173200 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1264 23:30:07.194932 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1265 23:30:07.222130 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1266 23:30:07.244894 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1267 23:30:07.266400 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1268 23:30:07.289832 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1269 23:30:07.315968 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1270 23:30:07.343216 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1271 23:30:07.362487 # ok 198 /ocp/interconnect@48000000/segment@200000
1272 23:30:07.385806 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1273 23:30:07.465106 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1274 23:30:07.486177 # ok 201 /ocp/interconnect@48000000/segment@300000
1275 23:30:07.512326 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1276 23:30:07.534326 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1277 23:30:07.557288 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1278 23:30:07.580330 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1279 23:30:07.609154 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1280 23:30:07.628573 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1281 23:30:07.703531 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1282 23:30:07.726865 # ok 209 /ocp/interconnect@4a000000
1283 23:30:07.746594 # ok 210 /ocp/interconnect@4a000000/segment@0
1284 23:30:07.773948 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1285 23:30:07.797153 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1286 23:30:07.822402 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1287 23:30:07.844598 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1288 23:30:07.918600 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1289 23:30:08.032299 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1290 23:30:08.106744 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1291 23:30:08.213263 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1292 23:30:08.285323 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1293 23:30:08.357425 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1294 23:30:08.457995 # not ok 221 /ocp/interconnect@4b140000
1295 23:30:08.533928 # not ok 222 /ocp/interconnect@4b140000/segment@0
1296 23:30:08.608040 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1297 23:30:08.629267 # ok 224 /ocp/target-module@40300000
1298 23:30:08.653384 # ok 225 /ocp/target-module@40300000/sram@0
1299 23:30:08.733003 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1300 23:30:08.803030 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1301 23:30:08.828322 # ok 228 /ocp/target-module@47400000
1302 23:30:08.852977 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1303 23:30:08.877202 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1304 23:30:08.901243 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1305 23:30:08.921985 # ok 232 /ocp/target-module@47400000/usb@1400
1306 23:30:08.943397 # ok 233 /ocp/target-module@47400000/usb@1800
1307 23:30:08.969766 # ok 234 /ocp/target-module@47810000
1308 23:30:08.991275 # ok 235 /ocp/target-module@49000000
1309 23:30:09.012141 # ok 236 /ocp/target-module@49000000/dma@0
1310 23:30:09.038906 # ok 237 /ocp/target-module@49800000
1311 23:30:09.061769 # ok 238 /ocp/target-module@49800000/dma@0
1312 23:30:09.086936 # ok 239 /ocp/target-module@49900000
1313 23:30:09.104833 # ok 240 /ocp/target-module@49900000/dma@0
1314 23:30:09.128030 # ok 241 /ocp/target-module@49a00000
1315 23:30:09.156608 # ok 242 /ocp/target-module@49a00000/dma@0
1316 23:30:09.178831 # ok 243 /ocp/target-module@4c000000
1317 23:30:09.252218 # not ok 244 /ocp/target-module@4c000000/emif@0
1318 23:30:09.276292 # ok 245 /ocp/target-module@50000000
1319 23:30:09.295714 # ok 246 /ocp/target-module@53100000
1320 23:30:09.372284 # not ok 247 /ocp/target-module@53100000/sham@0
1321 23:30:09.391856 # ok 248 /ocp/target-module@53500000
1322 23:30:09.470229 # not ok 249 /ocp/target-module@53500000/aes@0
1323 23:30:09.491151 # ok 250 /ocp/target-module@56000000
1324 23:30:09.600511 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1325 23:30:09.670164 # ok 252 /opp-table # SKIP
1326 23:30:09.745601 # ok 253 /soc # SKIP
1327 23:30:09.767495 # ok 254 /sound
1328 23:30:09.787076 # ok 255 /target-module@4b000000
1329 23:30:09.813014 # ok 256 /target-module@4b000000/target-module@140000
1330 23:30:09.834460 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1331 23:30:09.842868 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1332 23:30:09.850664 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1333 23:30:12.084934 dt_test_unprobed_devices_sh_ skip
1334 23:30:12.090427 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1335 23:30:12.095952 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1336 23:30:12.096497 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1337 23:30:12.101622 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1338 23:30:12.107226 dt_test_unprobed_devices_sh_fixedregulator0 pass
1339 23:30:12.112840 dt_test_unprobed_devices_sh_leds pass
1340 23:30:12.113389 dt_test_unprobed_devices_sh_ocp pass
1341 23:30:12.118376 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1342 23:30:12.123976 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1343 23:30:12.129620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1344 23:30:12.140793 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1345 23:30:12.146405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1346 23:30:12.152063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1347 23:30:12.163263 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1348 23:30:12.168884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1349 23:30:12.180105 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1350 23:30:12.191393 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1351 23:30:12.202593 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1352 23:30:12.208153 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1353 23:30:12.219353 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1354 23:30:12.230611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1355 23:30:12.241808 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1356 23:30:12.253084 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1357 23:30:12.258644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1358 23:30:12.269867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1359 23:30:12.281082 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1360 23:30:12.292262 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1361 23:30:12.303487 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1362 23:30:12.309042 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1363 23:30:12.320292 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1364 23:30:12.331516 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1365 23:30:12.342639 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1366 23:30:12.348274 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1367 23:30:12.359452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1368 23:30:12.370616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1369 23:30:12.381878 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1370 23:30:12.393123 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1371 23:30:12.398626 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1372 23:30:12.409992 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1373 23:30:12.421063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1374 23:30:12.432215 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1375 23:30:12.443440 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1376 23:30:12.454587 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1377 23:30:12.465731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1378 23:30:12.477068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1379 23:30:12.488238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1380 23:30:12.499327 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1381 23:30:12.510529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1382 23:30:12.521774 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1383 23:30:12.532910 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1384 23:30:12.544164 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1385 23:30:12.555416 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1386 23:30:12.566633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1387 23:30:12.577787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1388 23:30:12.589005 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1389 23:30:12.600211 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1390 23:30:12.611441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1391 23:30:12.622565 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1392 23:30:12.633732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1393 23:30:12.645035 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1394 23:30:12.656207 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1395 23:30:12.667347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1396 23:30:12.678542 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1397 23:30:12.684139 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1398 23:30:12.695254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1399 23:30:12.706551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1400 23:30:12.717695 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1401 23:30:12.728941 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1402 23:30:12.740103 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1403 23:30:12.751267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1404 23:30:12.762444 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1405 23:30:12.773664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1406 23:30:12.784883 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1407 23:30:12.796142 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1408 23:30:12.807254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1409 23:30:12.818503 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1410 23:30:12.829629 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1411 23:30:12.840880 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1412 23:30:12.852068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1413 23:30:12.863243 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1414 23:30:12.874404 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1415 23:30:12.880091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1416 23:30:12.891223 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1417 23:30:12.902460 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1418 23:30:12.913588 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1419 23:30:12.924735 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1420 23:30:12.930348 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1421 23:30:12.947157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1422 23:30:12.958312 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1423 23:30:12.963961 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1424 23:30:12.980739 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1425 23:30:12.991953 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1426 23:30:13.003103 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1427 23:30:13.008712 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1428 23:30:13.019942 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1429 23:30:13.031109 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1430 23:30:13.036788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1431 23:30:13.047908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1432 23:30:13.059085 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1433 23:30:13.064689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1434 23:30:13.075860 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1435 23:30:13.081458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1436 23:30:13.092713 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1437 23:30:13.103858 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1438 23:30:13.115048 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1439 23:30:13.126251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1440 23:30:13.137560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1441 23:30:13.148634 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1442 23:30:13.159853 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1443 23:30:13.171090 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1444 23:30:13.182291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1445 23:30:13.193586 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1446 23:30:13.204692 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1447 23:30:13.216001 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1448 23:30:13.232762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1449 23:30:13.243903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1450 23:30:13.255047 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1451 23:30:13.266265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1452 23:30:13.277413 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1453 23:30:13.294256 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1454 23:30:13.305432 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1455 23:30:13.316613 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1456 23:30:13.327890 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1457 23:30:13.333597 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1458 23:30:13.344568 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1459 23:30:13.355839 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1460 23:30:13.361489 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1461 23:30:13.372701 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1462 23:30:13.378240 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1463 23:30:13.389485 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1464 23:30:13.395160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1465 23:30:13.406287 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1466 23:30:13.411938 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1467 23:30:13.423004 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1468 23:30:13.428518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1469 23:30:13.439684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1470 23:30:13.450983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1471 23:30:13.462226 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1472 23:30:13.473357 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1473 23:30:13.484578 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1474 23:30:13.490213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1475 23:30:13.501330 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1476 23:30:13.506982 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1477 23:30:13.512560 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1478 23:30:13.518098 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1479 23:30:13.524167 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1480 23:30:13.529342 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1481 23:30:13.540452 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1482 23:30:13.546103 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1483 23:30:13.551688 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1484 23:30:13.562903 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1485 23:30:13.568591 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1486 23:30:13.579765 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1487 23:30:13.585272 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1488 23:30:13.596485 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1489 23:30:13.602090 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1490 23:30:13.613277 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1491 23:30:13.618870 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1492 23:30:13.630092 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1493 23:30:13.635733 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1494 23:30:13.646914 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1495 23:30:13.652490 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1496 23:30:13.663819 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1497 23:30:13.669379 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1498 23:30:13.674992 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1499 23:30:13.686251 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1500 23:30:13.691835 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1501 23:30:13.703143 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1502 23:30:13.708672 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1503 23:30:13.719816 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1504 23:30:13.725370 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1505 23:30:13.736566 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1506 23:30:13.742478 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1507 23:30:13.747904 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1508 23:30:13.759159 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1509 23:30:13.764728 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1510 23:30:13.775968 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1511 23:30:13.787174 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1512 23:30:13.798316 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1513 23:30:13.809510 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1514 23:30:13.820734 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1515 23:30:13.831926 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1516 23:30:13.843180 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1517 23:30:13.854407 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1518 23:30:13.860132 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1519 23:30:13.871250 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1520 23:30:13.876804 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1521 23:30:13.887909 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1522 23:30:13.893737 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1523 23:30:13.904835 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1524 23:30:13.910401 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1525 23:30:13.921609 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1526 23:30:13.927209 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1527 23:30:13.938356 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1528 23:30:13.943914 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1529 23:30:13.955171 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1530 23:30:13.960770 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1531 23:30:13.971944 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1532 23:30:13.977564 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1533 23:30:13.983148 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1534 23:30:13.994337 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1535 23:30:13.999923 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1536 23:30:14.011089 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1537 23:30:14.016769 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1538 23:30:14.027928 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1539 23:30:14.033552 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1540 23:30:14.044733 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1541 23:30:14.050264 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1542 23:30:14.055915 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1543 23:30:14.061508 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1544 23:30:14.072589 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1545 23:30:14.083760 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1546 23:30:14.089480 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1547 23:30:14.094977 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1548 23:30:14.106210 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1549 23:30:14.117325 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1550 23:30:14.128698 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1551 23:30:14.139833 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1552 23:30:14.145529 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1553 23:30:14.151092 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1554 23:30:14.156660 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1555 23:30:14.162347 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1556 23:30:14.167892 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1557 23:30:14.173504 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1558 23:30:14.184683 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1559 23:30:14.190420 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1560 23:30:14.195871 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1561 23:30:14.201503 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1562 23:30:14.207105 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1563 23:30:14.218375 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1564 23:30:14.223951 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1565 23:30:14.229559 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1566 23:30:14.235125 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1567 23:30:14.240770 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1568 23:30:14.246367 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1569 23:30:14.252031 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1570 23:30:14.257563 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1571 23:30:14.263030 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1572 23:30:14.268604 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1573 23:30:14.274261 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1574 23:30:14.282682 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1575 23:30:14.285561 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1576 23:30:14.291159 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1577 23:30:14.296862 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1578 23:30:14.302333 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1579 23:30:14.308420 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1580 23:30:14.313860 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1581 23:30:14.319478 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1582 23:30:14.322772 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1583 23:30:14.328332 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1584 23:30:14.333980 dt_test_unprobed_devices_sh_opp-table skip
1585 23:30:14.334424 dt_test_unprobed_devices_sh_soc skip
1586 23:30:14.339578 dt_test_unprobed_devices_sh_sound pass
1587 23:30:14.345200 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1588 23:30:14.350803 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1589 23:30:14.356387 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1590 23:30:14.361974 dt_test_unprobed_devices_sh fail
1591 23:30:14.367662 + ../../utils/send-to-lava.sh ./output/result.txt
1592 23:30:14.374636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1593 23:30:14.375652 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1595 23:30:14.379161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1596 23:30:14.379865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1598 23:30:14.469504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1599 23:30:14.470347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1601 23:30:14.562672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1602 23:30:14.563515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1604 23:30:14.650626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1605 23:30:14.651449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1607 23:30:14.741056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1608 23:30:14.741854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1610 23:30:14.834223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1611 23:30:14.835049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1613 23:30:14.921856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1614 23:30:14.922669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1616 23:30:15.011207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1617 23:30:15.011801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1619 23:30:15.108697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1620 23:30:15.109292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1622 23:30:15.202671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1623 23:30:15.203268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1625 23:30:15.292323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1626 23:30:15.292911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1628 23:30:15.383275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1629 23:30:15.383868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1631 23:30:15.477714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1632 23:30:15.478320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1634 23:30:15.568416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1635 23:30:15.569035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1637 23:30:15.657740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1638 23:30:15.658333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1640 23:30:15.752913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1641 23:30:15.753819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1643 23:30:15.842606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1644 23:30:15.843516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1646 23:30:15.936911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1647 23:30:15.937792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1649 23:30:16.026337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1650 23:30:16.027294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1652 23:30:16.121321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1653 23:30:16.122335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1655 23:30:16.210629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1656 23:30:16.211570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1658 23:30:16.299479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1659 23:30:16.300506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1661 23:30:16.394619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1662 23:30:16.395575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1664 23:30:16.488930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1665 23:30:16.489861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1667 23:30:16.583704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1668 23:30:16.585490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1670 23:30:16.672527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1671 23:30:16.673412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1673 23:30:16.767030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1674 23:30:16.767901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1676 23:30:16.862758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1677 23:30:16.863623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1679 23:30:16.957457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1680 23:30:16.958601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1682 23:30:17.055549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1683 23:30:17.056777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1685 23:30:17.153077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1686 23:30:17.153923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1688 23:30:17.247820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1689 23:30:17.248457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1691 23:30:17.342838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1692 23:30:17.343425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1694 23:30:17.431570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1695 23:30:17.432236 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1697 23:30:17.523586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1698 23:30:17.524233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1700 23:30:17.616400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1701 23:30:17.616989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1703 23:30:17.710985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1704 23:30:17.711574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1706 23:30:17.801159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1707 23:30:17.801757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1709 23:30:17.896875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1710 23:30:17.897500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1712 23:30:17.986010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1713 23:30:17.986594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1715 23:30:18.080292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1716 23:30:18.080876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1718 23:30:18.185503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1719 23:30:18.186107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1721 23:30:18.274162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1722 23:30:18.274757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1724 23:30:18.369639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1725 23:30:18.370247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1727 23:30:18.464738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1728 23:30:18.465325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1730 23:30:18.560244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1731 23:30:18.560839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1733 23:30:18.648587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1734 23:30:18.649199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1736 23:30:18.736250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1737 23:30:18.736856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1739 23:30:18.829535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1740 23:30:18.830197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1742 23:30:18.919391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1743 23:30:18.920062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1745 23:30:19.008029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1746 23:30:19.008632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1748 23:30:19.103201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1749 23:30:19.103800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1751 23:30:19.197883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1752 23:30:19.198474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1754 23:30:19.287605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1755 23:30:19.288244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1757 23:30:19.376248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1758 23:30:19.376839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1760 23:30:19.472120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1761 23:30:19.472754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1763 23:30:19.559221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1764 23:30:19.559826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1766 23:30:19.655147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1767 23:30:19.655725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1769 23:30:19.753331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1770 23:30:19.753897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1772 23:30:19.846031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1773 23:30:19.846593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1775 23:30:19.941046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1776 23:30:19.941607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1778 23:30:20.030562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1779 23:30:20.031151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1781 23:30:20.119874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1782 23:30:20.120472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1784 23:30:20.215774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1785 23:30:20.216349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1787 23:30:20.309586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1788 23:30:20.310148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1790 23:30:20.401631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1791 23:30:20.402255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1793 23:30:20.498911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1794 23:30:20.499729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1796 23:30:20.596305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1797 23:30:20.597108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1799 23:30:20.693703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1800 23:30:20.694494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1802 23:30:20.798226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1803 23:30:20.799128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1805 23:30:20.895006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1806 23:30:20.895794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1808 23:30:20.984705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1809 23:30:20.985469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1811 23:30:21.080509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1812 23:30:21.081308 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1814 23:30:21.175394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1815 23:30:21.176202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1817 23:30:21.273517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1818 23:30:21.274375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1820 23:30:21.369163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1821 23:30:21.369974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1823 23:30:21.460188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1824 23:30:21.461204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1826 23:30:21.555212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1827 23:30:21.556135 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1829 23:30:21.645203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1830 23:30:21.646034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1832 23:30:21.740378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1833 23:30:21.741218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1835 23:30:21.837138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1836 23:30:21.837888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1838 23:30:21.931127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1839 23:30:21.931854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1841 23:30:22.026483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1842 23:30:22.027509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1844 23:30:22.114936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1845 23:30:22.115843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1847 23:30:22.205224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1848 23:30:22.206157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1850 23:30:22.299669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1851 23:30:22.300707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1853 23:30:22.389928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1854 23:30:22.390844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1856 23:30:22.484058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1857 23:30:22.485013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1859 23:30:22.577715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1860 23:30:22.578694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1862 23:30:22.672570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1863 23:30:22.673549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1865 23:30:22.765546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1866 23:30:22.766468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1868 23:30:22.855697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1869 23:30:22.856619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1871 23:30:22.943847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1872 23:30:22.944683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1874 23:30:23.035045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1875 23:30:23.035897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1877 23:30:23.124985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1878 23:30:23.125791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1880 23:30:23.214174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1881 23:30:23.215002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1883 23:30:23.308371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1884 23:30:23.309189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1886 23:30:23.396077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1887 23:30:23.396940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1889 23:30:23.491474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1890 23:30:23.492355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1892 23:30:23.585396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1893 23:30:23.586014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1895 23:30:23.681594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1896 23:30:23.682372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1898 23:30:23.775147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1899 23:30:23.775958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1901 23:30:23.869577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1902 23:30:23.870375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1904 23:30:23.959454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1905 23:30:23.960273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1907 23:30:24.048648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1908 23:30:24.049444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1910 23:30:24.142556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1911 23:30:24.143318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1913 23:30:24.230851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1914 23:30:24.231648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1916 23:30:24.329064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1917 23:30:24.329857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1919 23:30:24.418020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1920 23:30:24.418830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1922 23:30:24.511762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1923 23:30:24.512401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1925 23:30:24.608754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1926 23:30:24.609583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1928 23:30:24.698001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1929 23:30:24.698750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1931 23:30:24.792808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1932 23:30:24.793588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1934 23:30:24.889000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1935 23:30:24.889786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1937 23:30:24.983633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1938 23:30:24.984532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1940 23:30:25.078921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1941 23:30:25.079749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1943 23:30:25.167357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1944 23:30:25.168162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1946 23:30:25.263864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1947 23:30:25.264729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1949 23:30:25.351801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1950 23:30:25.352872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1952 23:30:25.445784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1954 23:30:25.448934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1955 23:30:25.535882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1957 23:30:25.538976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1958 23:30:25.631249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1960 23:30:25.633442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1961 23:30:25.721200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1962 23:30:25.721951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1964 23:30:25.808165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1965 23:30:25.809045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1967 23:30:25.903614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1968 23:30:25.904438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1970 23:30:25.999089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1971 23:30:25.999869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1973 23:30:26.087832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1974 23:30:26.088643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1976 23:30:26.182704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1977 23:30:26.183463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1979 23:30:26.271576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1980 23:30:26.272369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1982 23:30:26.365310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1983 23:30:26.366050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1985 23:30:26.454788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1986 23:30:26.455571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1988 23:30:26.544296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1989 23:30:26.544922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1991 23:30:26.637677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1992 23:30:26.638508 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1994 23:30:26.727627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1995 23:30:26.728393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1997 23:30:26.816084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1998 23:30:26.816839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2000 23:30:26.911423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2001 23:30:26.912163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2003 23:30:27.001886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2004 23:30:27.002622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2006 23:30:27.098596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2007 23:30:27.099433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2009 23:30:27.185881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2010 23:30:27.186656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2012 23:30:27.280619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2013 23:30:27.281369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2015 23:30:27.370998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2016 23:30:27.371772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2018 23:30:27.462015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2019 23:30:27.462794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2021 23:30:27.553872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2022 23:30:27.554536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2024 23:30:27.640789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2025 23:30:27.641597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2027 23:30:27.736011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2028 23:30:27.736754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2030 23:30:27.824096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2031 23:30:27.824861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2033 23:30:27.914305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2034 23:30:27.915070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2036 23:30:28.011597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2037 23:30:28.012433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2039 23:30:28.106604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2040 23:30:28.107392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2042 23:30:28.201789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2043 23:30:28.202553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2045 23:30:28.306475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2046 23:30:28.307453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2048 23:30:28.430427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2049 23:30:28.431327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2051 23:30:28.529103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2052 23:30:28.529767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2054 23:30:28.624758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2055 23:30:28.625600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2057 23:30:28.719932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2058 23:30:28.720817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2060 23:30:28.815862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2061 23:30:28.816706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2063 23:30:28.909396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2064 23:30:28.910213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2066 23:30:29.003325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2067 23:30:29.004268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2069 23:30:29.093330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2070 23:30:29.094168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2072 23:30:29.182579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2073 23:30:29.183380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2075 23:30:29.276607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2076 23:30:29.277458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2078 23:30:29.366144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2079 23:30:29.366919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2081 23:30:29.454751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2082 23:30:29.455760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2084 23:30:29.549592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2085 23:30:29.550627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2087 23:30:29.638127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2088 23:30:29.639032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2090 23:30:29.728328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2091 23:30:29.729285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2093 23:30:29.822933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2094 23:30:29.824041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2096 23:30:29.913468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2097 23:30:29.914344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2099 23:30:30.006438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2100 23:30:30.007347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2102 23:30:30.096288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2103 23:30:30.097197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2105 23:30:30.190452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2106 23:30:30.191320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2108 23:30:30.281481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2109 23:30:30.282368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2111 23:30:30.374833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2112 23:30:30.375687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2114 23:30:30.464836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2115 23:30:30.465802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2117 23:30:30.556635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2118 23:30:30.557506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2120 23:30:30.655490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2121 23:30:30.656475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2123 23:30:30.750387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2124 23:30:30.751277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2126 23:30:30.840518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2127 23:30:30.841326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2129 23:30:30.930933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2130 23:30:30.931815 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2132 23:30:31.024626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2133 23:30:31.025532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2135 23:30:31.120933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2136 23:30:31.121823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2138 23:30:31.214697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2139 23:30:31.215609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2141 23:30:31.310034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2142 23:30:31.310938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2144 23:30:31.398983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2145 23:30:31.400113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2147 23:30:31.489830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2148 23:30:31.490790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2150 23:30:31.581475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2151 23:30:31.582409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2153 23:30:31.675330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2154 23:30:31.676295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2156 23:30:31.765393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2157 23:30:31.766277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2159 23:30:31.855126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2160 23:30:31.855957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2162 23:30:31.950626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2163 23:30:31.951515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2165 23:30:32.044890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2166 23:30:32.045796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2168 23:30:32.138966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2169 23:30:32.139842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2171 23:30:32.228978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2172 23:30:32.229877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2174 23:30:32.324164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2175 23:30:32.325026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2177 23:30:32.413518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2178 23:30:32.414447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2180 23:30:32.507435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2181 23:30:32.508319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2183 23:30:32.604091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2184 23:30:32.604997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2186 23:30:32.696083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2187 23:30:32.696941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2189 23:30:32.786235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2190 23:30:32.787055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2192 23:30:32.876076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2193 23:30:32.876888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2195 23:30:32.973055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2196 23:30:32.973861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2198 23:30:33.070339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2199 23:30:33.071298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2201 23:30:33.164144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2202 23:30:33.164961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2204 23:30:33.260747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2205 23:30:33.261647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2207 23:30:33.359061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2208 23:30:33.359885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2210 23:30:33.451382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2211 23:30:33.452381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2213 23:30:33.539319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2214 23:30:33.540298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2216 23:30:33.627792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2217 23:30:33.628694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2219 23:30:33.714495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2220 23:30:33.715349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2222 23:30:33.811054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2223 23:30:33.811853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2225 23:30:33.908216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2226 23:30:33.909008 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2228 23:30:33.997920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2229 23:30:33.998720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2231 23:30:34.088213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2232 23:30:34.089087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2234 23:30:34.180499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2235 23:30:34.181300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2237 23:30:34.270707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2238 23:30:34.271516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2240 23:30:34.366057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2241 23:30:34.366859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2243 23:30:34.457730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2244 23:30:34.458550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2246 23:30:34.552822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2247 23:30:34.553662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2249 23:30:34.646090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2250 23:30:34.646876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2252 23:30:34.735842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2253 23:30:34.736627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2255 23:30:34.821517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2256 23:30:34.822265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2258 23:30:34.910973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2259 23:30:34.911754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2261 23:30:35.005064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2262 23:30:35.005815 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2264 23:30:35.093647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2265 23:30:35.094424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2267 23:30:35.183380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2268 23:30:35.184183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2270 23:30:35.280693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2271 23:30:35.281504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2273 23:30:35.371738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2274 23:30:35.372586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2276 23:30:35.461515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2277 23:30:35.462404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2279 23:30:35.552712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2280 23:30:35.553579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2282 23:30:35.647105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2283 23:30:35.647880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2285 23:30:35.742405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2286 23:30:35.743149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2288 23:30:35.836555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2289 23:30:35.837299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2291 23:30:35.926058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2292 23:30:35.926810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2294 23:30:36.021651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2295 23:30:36.022435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2297 23:30:36.110435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2298 23:30:36.111203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2300 23:30:36.205691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2301 23:30:36.206445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2303 23:30:36.294653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2304 23:30:36.295405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2306 23:30:36.384267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2307 23:30:36.385093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2309 23:30:36.478480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2310 23:30:36.479399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2312 23:30:36.573998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2313 23:30:36.574652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2315 23:30:36.663046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2316 23:30:36.663687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2318 23:30:36.752737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2319 23:30:36.753550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2321 23:30:36.847650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2322 23:30:36.848358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2324 23:30:36.942267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2325 23:30:36.943129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2327 23:30:37.036290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2328 23:30:37.037023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2330 23:30:37.131731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2331 23:30:37.132489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2333 23:30:37.226627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2334 23:30:37.227326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2336 23:30:37.314996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2337 23:30:37.315699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2339 23:30:37.409790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2340 23:30:37.410541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2342 23:30:37.500892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2343 23:30:37.501704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2345 23:30:37.597758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2346 23:30:37.598452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2348 23:30:37.690125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2349 23:30:37.690896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2351 23:30:37.777294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2352 23:30:37.777988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2354 23:30:37.867902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2355 23:30:37.868648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2357 23:30:37.963351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2358 23:30:37.964098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2360 23:30:38.054631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2361 23:30:38.055369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2363 23:30:38.143911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2364 23:30:38.144658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2366 23:30:38.235230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2367 23:30:38.235693 + set +x
2368 23:30:38.236391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2370 23:30:38.244140 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 963448_1.6.2.4.5>
2371 23:30:38.244574 <LAVA_TEST_RUNNER EXIT>
2372 23:30:38.245213 Received signal: <ENDRUN> 1_kselftest-dt 963448_1.6.2.4.5
2373 23:30:38.245650 Ending use of test pattern.
2374 23:30:38.246050 Ending test lava.1_kselftest-dt (963448_1.6.2.4.5), duration 82.63
2376 23:30:38.247517 ok: lava_test_shell seems to have completed
2377 23:30:38.259867 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2378 23:30:38.261770 end: 3.1 lava-test-shell (duration 00:01:24) [common]
2379 23:30:38.262323 end: 3 lava-test-retry (duration 00:01:24) [common]
2380 23:30:38.262890 start: 4 finalize (timeout 00:05:31) [common]
2381 23:30:38.263433 start: 4.1 power-off (timeout 00:00:30) [common]
2382 23:30:38.264382 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2383 23:30:38.299669 >> OK - accepted request
2384 23:30:38.301918 Returned 0 in 0 seconds
2385 23:30:38.403174 end: 4.1 power-off (duration 00:00:00) [common]
2387 23:30:38.404983 start: 4.2 read-feedback (timeout 00:05:30) [common]
2388 23:30:38.406250 Listened to connection for namespace 'common' for up to 1s
2389 23:30:38.407149 Listened to connection for namespace 'common' for up to 1s
2390 23:30:39.406929 Finalising connection for namespace 'common'
2391 23:30:39.407690 Disconnecting from shell: Finalise
2392 23:30:39.408290 / #
2393 23:30:39.509323 end: 4.2 read-feedback (duration 00:00:01) [common]
2394 23:30:39.510058 end: 4 finalize (duration 00:00:01) [common]
2395 23:30:39.510770 Cleaning after the job
2396 23:30:39.511482 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963448/tftp-deploy-opvjh0od/ramdisk
2397 23:30:39.514058 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963448/tftp-deploy-opvjh0od/kernel
2398 23:30:39.516023 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963448/tftp-deploy-opvjh0od/dtb
2399 23:30:39.517188 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963448/tftp-deploy-opvjh0od/nfsrootfs
2400 23:30:39.554671 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963448/tftp-deploy-opvjh0od/modules
2401 23:30:39.561379 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/963448
2402 23:30:42.590541 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/963448
2403 23:30:42.591131 Job finished correctly