Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 22:49:40.160184 lava-dispatcher, installed at version: 2023.08
2 22:49:40.160494 start: 0 validate
3 22:49:40.160679 Start time: 2024-11-08 22:49:40.160668+00:00 (UTC)
4 22:49:40.160921 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 22:49:40.416809 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/kernel/zImage exists
6 22:49:40.531134 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/dtbs/ti/omap/am335x-boneblack.dtb exists
7 22:49:40.649323 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 22:49:40.763215 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/modules.tar.xz exists
9 22:49:40.882201 validate duration: 0.72
11 22:49:40.882994 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 22:49:40.883331 start: 1.1 download-retry (timeout 00:10:00) [common]
13 22:49:40.883644 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 22:49:40.884103 Not decompressing ramdisk as can be used compressed.
15 22:49:40.884405 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 22:49:40.884648 saving as /var/lib/lava/dispatcher/tmp/1219960/tftp-deploy-y24xrdmw/ramdisk/initrd.cpio.gz
17 22:49:40.884930 total size: 4775763 (4 MB)
18 22:49:41.112586 progress 0 % (0 MB)
19 22:49:41.450178 progress 5 % (0 MB)
20 22:49:41.562472 progress 10 % (0 MB)
21 22:49:41.700644 progress 15 % (0 MB)
22 22:49:41.730231 progress 20 % (0 MB)
23 22:49:41.828244 progress 25 % (1 MB)
24 22:49:41.834740 progress 30 % (1 MB)
25 22:49:41.898174 progress 35 % (1 MB)
26 22:49:41.922047 progress 40 % (1 MB)
27 22:49:42.009036 progress 45 % (2 MB)
28 22:49:42.032581 progress 50 % (2 MB)
29 22:49:42.123169 progress 55 % (2 MB)
30 22:49:42.145533 progress 60 % (2 MB)
31 22:49:42.230281 progress 65 % (2 MB)
32 22:49:42.258657 progress 70 % (3 MB)
33 22:49:42.341322 progress 75 % (3 MB)
34 22:49:42.366277 progress 80 % (3 MB)
35 22:49:42.393233 progress 85 % (3 MB)
36 22:49:42.477248 progress 90 % (4 MB)
37 22:49:42.503363 progress 95 % (4 MB)
38 22:49:42.583584 progress 100 % (4 MB)
39 22:49:42.584366 4 MB downloaded in 1.70 s (2.68 MB/s)
40 22:49:42.584888 end: 1.1.1 http-download (duration 00:00:02) [common]
42 22:49:42.585657 end: 1.1 download-retry (duration 00:00:02) [common]
43 22:49:42.585923 start: 1.2 download-retry (timeout 00:09:58) [common]
44 22:49:42.586181 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 22:49:42.586549 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/kernel/zImage
46 22:49:42.586755 saving as /var/lib/lava/dispatcher/tmp/1219960/tftp-deploy-y24xrdmw/kernel/zImage
47 22:49:42.586949 total size: 12042752 (11 MB)
48 22:49:42.587145 No compression specified
49 22:49:42.703256 progress 0 % (0 MB)
50 22:49:42.989316 progress 5 % (0 MB)
51 22:49:43.154051 progress 10 % (1 MB)
52 22:49:43.291315 progress 15 % (1 MB)
53 22:49:43.496835 progress 20 % (2 MB)
54 22:49:43.630782 progress 25 % (2 MB)
55 22:49:43.835202 progress 30 % (3 MB)
56 22:49:43.970060 progress 35 % (4 MB)
57 22:49:44.171112 progress 40 % (4 MB)
58 22:49:44.304195 progress 45 % (5 MB)
59 22:49:44.500833 progress 50 % (5 MB)
60 22:49:44.635777 progress 55 % (6 MB)
61 22:49:44.839527 progress 60 % (6 MB)
62 22:49:44.965596 progress 65 % (7 MB)
63 22:49:45.110005 progress 70 % (8 MB)
64 22:49:45.294918 progress 75 % (8 MB)
65 22:49:45.425636 progress 80 % (9 MB)
66 22:49:45.620100 progress 85 % (9 MB)
67 22:49:45.748794 progress 90 % (10 MB)
68 22:49:45.877999 progress 95 % (10 MB)
69 22:49:46.072089 progress 100 % (11 MB)
70 22:49:46.072752 11 MB downloaded in 3.49 s (3.29 MB/s)
71 22:49:46.073194 end: 1.2.1 http-download (duration 00:00:03) [common]
73 22:49:46.074007 end: 1.2 download-retry (duration 00:00:03) [common]
74 22:49:46.074305 start: 1.3 download-retry (timeout 00:09:55) [common]
75 22:49:46.074590 start: 1.3.1 http-download (timeout 00:09:55) [common]
76 22:49:46.074993 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/dtbs/ti/omap/am335x-boneblack.dtb
77 22:49:46.075227 saving as /var/lib/lava/dispatcher/tmp/1219960/tftp-deploy-y24xrdmw/dtb/am335x-boneblack.dtb
78 22:49:46.075443 total size: 70568 (0 MB)
79 22:49:46.075661 No compression specified
80 22:49:46.192099 progress 46 % (0 MB)
81 22:49:46.194893 progress 92 % (0 MB)
82 22:49:46.195882 progress 100 % (0 MB)
83 22:49:46.196286 0 MB downloaded in 0.12 s (0.56 MB/s)
84 22:49:46.196740 end: 1.3.1 http-download (duration 00:00:00) [common]
86 22:49:46.197545 end: 1.3 download-retry (duration 00:00:00) [common]
87 22:49:46.197832 start: 1.4 download-retry (timeout 00:09:55) [common]
88 22:49:46.198119 start: 1.4.1 http-download (timeout 00:09:55) [common]
89 22:49:46.198516 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 22:49:46.198744 saving as /var/lib/lava/dispatcher/tmp/1219960/tftp-deploy-y24xrdmw/nfsrootfs/full.rootfs.tar
91 22:49:46.198960 total size: 117747780 (112 MB)
92 22:49:46.199182 Using unxz to decompress xz
93 22:49:46.315418 progress 0 % (0 MB)
94 22:49:48.353797 progress 5 % (5 MB)
95 22:49:50.143986 progress 10 % (11 MB)
96 22:49:51.923325 progress 15 % (16 MB)
97 22:49:53.634358 progress 20 % (22 MB)
98 22:49:55.375333 progress 25 % (28 MB)
99 22:49:56.860576 progress 30 % (33 MB)
100 22:49:58.198357 progress 35 % (39 MB)
101 22:49:59.323875 progress 40 % (44 MB)
102 22:50:00.300251 progress 45 % (50 MB)
103 22:50:01.110097 progress 50 % (56 MB)
104 22:50:01.813036 progress 55 % (61 MB)
105 22:50:02.449632 progress 60 % (67 MB)
106 22:50:03.014121 progress 65 % (73 MB)
107 22:50:03.530260 progress 70 % (78 MB)
108 22:50:04.160758 progress 75 % (84 MB)
109 22:50:04.679874 progress 80 % (89 MB)
110 22:50:05.261896 progress 85 % (95 MB)
111 22:50:05.822266 progress 90 % (101 MB)
112 22:50:06.354259 progress 95 % (106 MB)
113 22:50:06.868043 progress 100 % (112 MB)
114 22:50:06.871548 112 MB downloaded in 20.67 s (5.43 MB/s)
115 22:50:06.871892 end: 1.4.1 http-download (duration 00:00:21) [common]
117 22:50:06.872499 end: 1.4 download-retry (duration 00:00:21) [common]
118 22:50:06.872729 start: 1.5 download-retry (timeout 00:09:34) [common]
119 22:50:06.872956 start: 1.5.1 http-download (timeout 00:09:34) [common]
120 22:50:06.873287 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/modules.tar.xz
121 22:50:06.873456 saving as /var/lib/lava/dispatcher/tmp/1219960/tftp-deploy-y24xrdmw/modules/modules.tar
122 22:50:06.873627 total size: 6911472 (6 MB)
123 22:50:06.873801 Using unxz to decompress xz
124 22:50:06.989743 progress 0 % (0 MB)
125 22:50:07.233982 progress 5 % (0 MB)
126 22:50:07.548625 progress 10 % (0 MB)
127 22:50:07.577001 progress 15 % (1 MB)
128 22:50:07.682734 progress 20 % (1 MB)
129 22:50:07.708588 progress 25 % (1 MB)
130 22:50:07.735648 progress 30 % (2 MB)
131 22:50:07.772474 progress 35 % (2 MB)
132 22:50:07.996195 progress 40 % (2 MB)
133 22:50:08.026835 progress 45 % (2 MB)
134 22:50:08.053999 progress 50 % (3 MB)
135 22:50:08.079980 progress 55 % (3 MB)
136 22:50:08.131577 progress 60 % (3 MB)
137 22:50:08.233460 progress 65 % (4 MB)
138 22:50:08.269687 progress 70 % (4 MB)
139 22:50:08.373648 progress 75 % (4 MB)
140 22:50:08.465556 progress 80 % (5 MB)
141 22:50:08.568018 progress 85 % (5 MB)
142 22:50:08.605401 progress 90 % (5 MB)
143 22:50:08.701022 progress 95 % (6 MB)
144 22:50:08.799206 progress 100 % (6 MB)
145 22:50:08.802889 6 MB downloaded in 1.93 s (3.42 MB/s)
146 22:50:08.803267 end: 1.5.1 http-download (duration 00:00:02) [common]
148 22:50:08.804064 end: 1.5 download-retry (duration 00:00:02) [common]
149 22:50:08.804367 start: 1.6 prepare-tftp-overlay (timeout 00:09:32) [common]
150 22:50:08.804664 start: 1.6.1 extract-nfsrootfs (timeout 00:09:32) [common]
151 22:50:14.399290 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1219960/extract-nfsrootfs-7hjuqjro
152 22:50:14.399595 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 22:50:14.399747 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
154 22:50:14.400044 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s
155 22:50:14.400233 makedir: /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin
156 22:50:14.400379 makedir: /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/tests
157 22:50:14.400528 makedir: /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/results
158 22:50:14.400689 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-add-keys
159 22:50:14.400922 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-add-sources
160 22:50:14.401110 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-background-process-start
161 22:50:14.401302 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-background-process-stop
162 22:50:14.401502 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-common-functions
163 22:50:14.401686 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-echo-ipv4
164 22:50:14.401875 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-install-packages
165 22:50:14.402056 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-installed-packages
166 22:50:14.402227 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-os-build
167 22:50:14.402400 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-probe-channel
168 22:50:14.402574 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-probe-ip
169 22:50:14.402748 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-target-ip
170 22:50:14.402920 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-target-mac
171 22:50:14.403091 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-target-storage
172 22:50:14.403266 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-test-case
173 22:50:14.403438 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-test-event
174 22:50:14.403608 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-test-feedback
175 22:50:14.403778 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-test-raise
176 22:50:14.403949 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-test-reference
177 22:50:14.404122 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-test-runner
178 22:50:14.404296 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-test-set
179 22:50:14.404466 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-test-shell
180 22:50:14.404640 Updating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-add-keys (debian)
181 22:50:14.405006 Updating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-add-sources (debian)
182 22:50:14.405202 Updating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-install-packages (debian)
183 22:50:14.405397 Updating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-installed-packages (debian)
184 22:50:14.405590 Updating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/bin/lava-os-build (debian)
185 22:50:14.405760 Creating /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/environment
186 22:50:14.405894 LAVA metadata
187 22:50:14.405995 - LAVA_JOB_ID=1219960
188 22:50:14.406094 - LAVA_DISPATCHER_IP=192.168.11.5
189 22:50:14.406238 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
190 22:50:14.406567 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 22:50:14.406702 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
192 22:50:14.406806 skipped lava-vland-overlay
193 22:50:14.406921 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 22:50:14.407042 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
195 22:50:14.407139 skipped lava-multinode-overlay
196 22:50:14.407254 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 22:50:14.407370 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
198 22:50:14.407472 Loading test definitions
199 22:50:14.407595 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
200 22:50:14.407695 Using /lava-1219960 at stage 0
201 22:50:14.408102 uuid=1219960_1.6.2.4.1 testdef=None
202 22:50:14.408226 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 22:50:14.408347 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
204 22:50:14.408965 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 22:50:14.409299 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
207 22:50:14.410068 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 22:50:14.410417 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
210 22:50:14.411159 runner path: /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/0/tests/0_timesync-off test_uuid 1219960_1.6.2.4.1
211 22:50:14.411370 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 22:50:14.411730 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
214 22:50:14.411848 Using /lava-1219960 at stage 0
215 22:50:14.412005 Fetching tests from https://github.com/kernelci/test-definitions.git
216 22:50:14.412110 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/0/tests/1_kselftest-dt'
217 22:50:19.078316 Running '/usr/bin/git checkout kernelci.org
218 22:50:19.182880 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 22:50:19.183820 uuid=1219960_1.6.2.4.5 testdef=None
220 22:50:19.184062 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 22:50:19.184609 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
223 22:50:19.186432 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 22:50:19.187003 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
226 22:50:19.189539 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 22:50:19.190136 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
229 22:50:19.192554 runner path: /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/0/tests/1_kselftest-dt test_uuid 1219960_1.6.2.4.5
230 22:50:19.192769 BOARD='beaglebone-black'
231 22:50:19.192883 BRANCH='mainline'
232 22:50:19.192972 SKIPFILE='/dev/null'
233 22:50:19.193060 SKIP_INSTALL='True'
234 22:50:19.193146 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz'
235 22:50:19.193234 TST_CASENAME=''
236 22:50:19.193320 TST_CMDFILES='dt'
237 22:50:19.193511 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 22:50:19.193819 Creating lava-test-runner.conf files
240 22:50:19.193908 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1219960/lava-overlay-lix93p6s/lava-1219960/0 for stage 0
241 22:50:19.194030 - 0_timesync-off
242 22:50:19.194123 - 1_kselftest-dt
243 22:50:19.194256 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 22:50:19.194373 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
245 22:50:27.727257 end: 1.6.2.5 compress-overlay (duration 00:00:09) [common]
246 22:50:27.727462 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:13) [common]
247 22:50:27.727608 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 22:50:27.727756 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
249 22:50:27.727901 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:13) [common]
250 22:50:27.851543 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 22:50:27.851836 start: 1.6.4 extract-modules (timeout 00:09:13) [common]
252 22:50:27.852012 extracting modules file /var/lib/lava/dispatcher/tmp/1219960/tftp-deploy-y24xrdmw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1219960/extract-nfsrootfs-7hjuqjro
253 22:50:28.161602 extracting modules file /var/lib/lava/dispatcher/tmp/1219960/tftp-deploy-y24xrdmw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1219960/extract-overlay-ramdisk-4yfskb2z/ramdisk
254 22:50:28.473725 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 22:50:28.473942 start: 1.6.5 apply-overlay-tftp (timeout 00:09:12) [common]
256 22:50:28.474078 [common] Applying overlay to NFS
257 22:50:28.474186 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1219960/compress-overlay-qsvw5m6k/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1219960/extract-nfsrootfs-7hjuqjro
258 22:50:29.666691 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 22:50:29.666906 start: 1.6.6 prepare-kernel (timeout 00:09:11) [common]
260 22:50:29.667035 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:11) [common]
261 22:50:29.667164 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 22:50:29.667281 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 22:50:29.667401 start: 1.6.7 configure-preseed-file (timeout 00:09:11) [common]
264 22:50:29.667517 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 22:50:29.667635 start: 1.6.8 compress-ramdisk (timeout 00:09:11) [common]
266 22:50:29.667736 Building ramdisk /var/lib/lava/dispatcher/tmp/1219960/extract-overlay-ramdisk-4yfskb2z/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1219960/extract-overlay-ramdisk-4yfskb2z/ramdisk
267 22:50:29.986431 >> 78983 blocks
268 22:50:32.119791 Adding RAMdisk u-boot header.
269 22:50:32.120078 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1219960/extract-overlay-ramdisk-4yfskb2z/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1219960/extract-overlay-ramdisk-4yfskb2z/ramdisk.cpio.gz.uboot
270 22:50:32.275828 output: Image Name:
271 22:50:32.276088 output: Created: Fri Nov 8 22:50:32 2024
272 22:50:32.276232 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 22:50:32.276369 output: Data Size: 15342781 Bytes = 14983.18 KiB = 14.63 MiB
274 22:50:32.276501 output: Load Address: 00000000
275 22:50:32.276630 output: Entry Point: 00000000
276 22:50:32.276815 output:
277 22:50:32.277093 rename /var/lib/lava/dispatcher/tmp/1219960/extract-overlay-ramdisk-4yfskb2z/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1219960/tftp-deploy-y24xrdmw/ramdisk/ramdisk.cpio.gz.uboot
278 22:50:32.277392 end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
279 22:50:32.277630 end: 1.6 prepare-tftp-overlay (duration 00:00:23) [common]
280 22:50:32.277865 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:09) [common]
281 22:50:32.278039 No LXC device requested
282 22:50:32.278251 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 22:50:32.278479 start: 1.8 deploy-device-env (timeout 00:09:09) [common]
284 22:50:32.278683 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 22:50:32.278857 Checking files for TFTP limit of 4294967296 bytes.
286 22:50:32.279903 end: 1 tftp-deploy (duration 00:00:51) [common]
287 22:50:32.280143 start: 2 uboot-action (timeout 00:05:00) [common]
288 22:50:32.280379 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 22:50:32.280599 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 22:50:32.280864 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 22:50:32.281190 substitutions:
292 22:50:32.281360 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 22:50:32.281541 - {DTB_ADDR}: 0x88000000
294 22:50:32.281716 - {DTB}: 1219960/tftp-deploy-y24xrdmw/dtb/am335x-boneblack.dtb
295 22:50:32.281893 - {INITRD}: 1219960/tftp-deploy-y24xrdmw/ramdisk/ramdisk.cpio.gz.uboot
296 22:50:32.282067 - {KERNEL_ADDR}: 0x82000000
297 22:50:32.282243 - {KERNEL}: 1219960/tftp-deploy-y24xrdmw/kernel/zImage
298 22:50:32.282416 - {LAVA_MAC}: None
299 22:50:32.282599 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1219960/extract-nfsrootfs-7hjuqjro
300 22:50:32.282770 - {NFS_SERVER_IP}: 192.168.11.5
301 22:50:32.282940 - {PRESEED_CONFIG}: None
302 22:50:32.283110 - {PRESEED_LOCAL}: None
303 22:50:32.283280 - {RAMDISK_ADDR}: 0x83000000
304 22:50:32.283450 - {RAMDISK}: 1219960/tftp-deploy-y24xrdmw/ramdisk/ramdisk.cpio.gz.uboot
305 22:50:32.283620 - {ROOT_PART}: None
306 22:50:32.283787 - {ROOT}: None
307 22:50:32.283954 - {SERVER_IP}: 192.168.11.5
308 22:50:32.284121 - {TEE_ADDR}: 0x83000000
309 22:50:32.284290 - {TEE}: None
310 22:50:32.284457 Parsed boot commands:
311 22:50:32.284622 - setenv autoload no
312 22:50:32.284817 - setenv initrd_high 0xffffffff
313 22:50:32.284985 - setenv fdt_high 0xffffffff
314 22:50:32.285153 - dhcp
315 22:50:32.285322 - setenv serverip 192.168.11.5
316 22:50:32.285489 - tftp 0x82000000 1219960/tftp-deploy-y24xrdmw/kernel/zImage
317 22:50:32.285659 - tftp 0x83000000 1219960/tftp-deploy-y24xrdmw/ramdisk/ramdisk.cpio.gz.uboot
318 22:50:32.285830 - setenv initrd_size ${filesize}
319 22:50:32.285998 - tftp 0x88000000 1219960/tftp-deploy-y24xrdmw/dtb/am335x-boneblack.dtb
320 22:50:32.286168 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219960/extract-nfsrootfs-7hjuqjro,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 22:50:32.286344 - bootz 0x82000000 0x83000000 0x88000000
322 22:50:32.286573 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 22:50:32.287169 start: 2.3 connect-device (timeout 00:05:00) [common]
325 22:50:32.287335 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 22:50:32.646012 Setting prompt string to ['lava-test: # ']
327 22:50:32.646459 end: 2.3 connect-device (duration 00:00:00) [common]
328 22:50:32.646628 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 22:50:32.646802 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 22:50:32.646951 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 22:50:32.647269 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 22:50:33.013005 Returned 0 in 0 seconds
333 22:50:33.113855 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 22:50:33.114757 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 22:50:33.115066 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 22:50:33.115345 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 22:50:33.115590 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 22:50:33.116331 Trying 127.0.0.1...
340 22:50:33.116563 Connected to 127.0.0.1.
341 22:50:33.116807 Escape character is '^]'.
342 22:50:38.031353
343 22:50:38.034980 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 22:50:38.091552 Trying to boot from MMC2
345 22:50:38.140068 Loading Environment from EXT4... Card did not respond to voltage select!
346 22:50:38.207650
347 22:50:38.207920
348 22:50:38.213146 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 22:50:38.213422
350 22:50:38.218064 CPU : AM335X-GP rev 2.1
351 22:50:38.272025 I2C: ready
352 22:50:38.272372 DRAM: 512 MiB
353 22:50:38.326494 No match for driver 'omap_hsmmc'
354 22:50:38.331983 No match for driver 'omap_hsmmc'
355 22:50:38.332270 Some drivers were not found
356 22:50:38.338372 Reset Source: Power-on reset has occurred.
357 22:50:38.338656 RTC 32KCLK Source: External.
358 22:50:38.345820 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 22:50:38.359165 Loading Environment from EXT4... Card did not respond to voltage select!
360 22:50:38.423611 Board: BeagleBone Black
361 22:50:38.427594 <ethaddr> not set. Validating first E-fuse MAC
362 22:50:38.484148 BeagleBone Black:
363 22:50:38.484432 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 22:50:38.489735 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 22:50:38.495738 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 22:50:38.496012 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 22:50:38.500664 Net: eth0: MII MODE
368 22:50:38.510050 cpsw, usb_ether
369 22:50:38.510326 Press SPACE to abort autoboot in 2 seconds
370 22:50:38.561150 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 22:50:38.561497 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 22:50:38.561765 Setting prompt string to ['=> ']
373 22:50:38.562025 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 22:50:38.565306 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 22:50:38.565612 Sending with 10 millisecond of delay
377 22:50:39.700287 => setenv autoload no
378 22:50:39.710806 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 22:50:39.713192 setenv autoload no
380 22:50:39.713659 Sending with 10 millisecond of delay
382 22:50:41.510635 => setenv initrd_high 0xffffffff
383 22:50:41.521118 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 22:50:41.521594 setenv initrd_high 0xffffffff
385 22:50:41.522040 Sending with 10 millisecond of delay
387 22:50:43.138235 => setenv fdt_high 0xffffffff
388 22:50:43.148676 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 22:50:43.149028 setenv fdt_high 0xffffffff
390 22:50:43.149371 Sending with 10 millisecond of delay
392 22:50:43.440728 => dhcp
393 22:50:43.451222 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 22:50:43.451690 dhcp
395 22:50:43.451919 link up on port 0, speed 100, full duplex
396 22:50:43.452138 BOOTP broadcast 1
397 22:50:43.459820 DHCP client bound to address 192.168.11.3 (4 ms)
398 22:50:43.460308 Sending with 10 millisecond of delay
400 22:50:45.196756 => setenv serverip 192.168.11.5
401 22:50:45.207246 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 22:50:45.207721 setenv serverip 192.168.11.5
403 22:50:45.208172 Sending with 10 millisecond of delay
405 22:50:48.751647 => tftp 0x82000000 1219960/tftp-deploy-y24xrdmw/kernel/zImage
406 22:50:48.762141 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 22:50:48.762663 tftp 0x82000000 1219960/tftp-deploy-y24xrdmw/kernel/zImage
408 22:50:48.762942 link up on port 0, speed 100, full duplex
409 22:50:48.763195 Using cpsw device
410 22:50:48.766369 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
411 22:50:48.771975 Filename '1219960/tftp-deploy-y24xrdmw/kernel/zImage'.
412 22:50:48.871304 Load address: 0x82000000
413 22:50:48.959846 Loading: *#################################################################
414 22:50:49.133343 #################################################################
415 22:50:49.307008 #################################################################
416 22:50:49.503634 #################################################################
417 22:50:49.661439 #################################################################
418 22:50:49.833107 #################################################################
419 22:50:50.006912 #################################################################
420 22:50:50.180868 #################################################################
421 22:50:50.376822 #################################################################
422 22:50:50.549580 #################################################################
423 22:50:50.723551 #################################################################
424 22:50:50.895052 #################################################################
425 22:50:51.001531 #########################################
426 22:50:51.001852 5.2 MiB/s
427 22:50:51.002112 done
428 22:50:51.003314 Bytes transferred = 12042752 (b7c200 hex)
429 22:50:51.003783 Sending with 10 millisecond of delay
431 22:50:55.510272 => tftp 0x83000000 1219960/tftp-deploy-y24xrdmw/ramdisk/ramdisk.cpio.gz.uboot
432 22:50:55.520762 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
433 22:50:55.521221 tftp 0x83000000 1219960/tftp-deploy-y24xrdmw/ramdisk/ramdisk.cpio.gz.uboot
434 22:50:55.521454 link up on port 0, speed 100, full duplex
435 22:50:55.521670 Using cpsw device
436 22:50:55.525105 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
437 22:50:55.531508 Filename '1219960/tftp-deploy-y24xrdmw/ramdisk/ramdisk.cpio.gz.uboot'.
438 22:50:55.539084 Load address: 0x83000000
439 22:50:55.730472 Loading: *#################################################################
440 22:50:55.896036 #################################################################
441 22:50:56.131583 #################################################################
442 22:50:56.216354 #################################################################
443 22:50:56.401710 #################################################################
444 22:50:56.576596 #################################################################
445 22:50:56.749503 #################################################################
446 22:50:56.918702 #################################################################
447 22:50:57.101194 #################################################################
448 22:50:57.275956 #################################################################
449 22:50:57.449677 #################################################################
450 22:50:57.623415 #################################################################
451 22:50:57.797676 #################################################################
452 22:50:57.971641 #################################################################
453 22:50:58.146572 #################################################################
454 22:50:58.315925 #################################################################
455 22:50:58.332933 ######
456 22:50:58.333243 5.2 MiB/s
457 22:50:58.333466 done
458 22:50:58.336559 Bytes transferred = 15342845 (ea1cfd hex)
459 22:50:58.337135 Sending with 10 millisecond of delay
461 22:51:00.194197 => setenv initrd_size ${filesize}
462 22:51:00.204691 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
463 22:51:00.205173 setenv initrd_size ${filesize}
464 22:51:00.205618 Sending with 10 millisecond of delay
466 22:51:04.410971 => tftp 0x88000000 1219960/tftp-deploy-y24xrdmw/dtb/am335x-boneblack.dtb
467 22:51:04.421436 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
468 22:51:04.421946 tftp 0x88000000 1219960/tftp-deploy-y24xrdmw/dtb/am335x-boneblack.dtb
469 22:51:04.422223 link up on port 0, speed 100, full duplex
470 22:51:04.422450 Using cpsw device
471 22:51:04.425613 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
472 22:51:04.439081 Filename '1219960/tftp-deploy-y24xrdmw/dtb/am335x-boneblack.dtb'.
473 22:51:04.439354 Load address: 0x88000000
474 22:51:04.454770 Loading: *#####
475 22:51:04.455063 4.5 MiB/s
476 22:51:04.455279 done
477 22:51:04.455485 Bytes transferred = 70568 (113a8 hex)
478 22:51:04.458245 Sending with 10 millisecond of delay
480 22:51:17.757313 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219960/extract-nfsrootfs-7hjuqjro,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 22:51:17.767829 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
482 22:51:17.768293 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219960/extract-nfsrootfs-7hjuqjro,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
483 22:51:17.768759 Sending with 10 millisecond of delay
485 22:51:20.107805 => bootz 0x82000000 0x83000000 0x88000000
486 22:51:20.118283 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
487 22:51:20.118603 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
488 22:51:20.119137 bootz 0x82000000 0x83000000 0x88000000
489 22:51:20.119378 ## Loading init Ramdisk from Legacy Image at 83000000 ...
490 22:51:20.119934 Image Name:
491 22:51:20.120162 Created: 2024-11-08 22:50:32 UTC
492 22:51:20.125438 Image Type: ARM Linux RAMDisk Image (uncompressed)
493 22:51:20.128930 Data Size: 15342781 Bytes = 14.6 MiB
494 22:51:20.134470 Load Address: 00000000
495 22:51:20.134749 Entry Point: 00000000
496 22:51:20.280608 Verifying Checksum ... OK
497 22:51:20.280906 ## Flattened Device Tree blob at 88000000
498 22:51:20.287183 Booting using the fdt blob at 0x88000000
499 22:51:20.292153 Using Device Tree in place at 88000000, end 880143a7
500 22:51:20.299627
501 22:51:20.299907 Starting kernel ...
502 22:51:20.300134
503 22:51:20.300669 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
504 22:51:20.300990 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
505 22:51:20.301241 Setting prompt string to ['Linux version [0-9]']
506 22:51:20.301490 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
507 22:51:20.301737 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
508 22:51:21.198373 [ 0.000000] Booting Linux on physical CPU 0x0
509 22:51:21.204502 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
510 22:51:21.204840 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 22:51:21.205105 Setting prompt string to []
512 22:51:21.205368 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 22:51:21.205621 Using line separator: #'\n'#
514 22:51:21.205842 No login prompt set.
515 22:51:21.206071 Parsing kernel messages
516 22:51:21.206280 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 22:51:21.206673 [login-action] Waiting for messages, (timeout 00:04:11)
518 22:51:21.215401 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j370111-arm-clang-16-multi-v7-defconfig-5q2kc) (Debian clang version 16.0.6 (15~deb12u1), Debian LLD 16.0.6) #1 SMP Fri Nov 8 22:26:11 UTC 2024
519 22:51:21.226909 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
520 22:51:21.232533 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
521 22:51:21.238268 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
522 22:51:21.244021 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
523 22:51:21.249769 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
524 22:51:21.255511 [ 0.000000] Memory policy: Data cache writeback
525 22:51:21.262264 [ 0.000000] efi: UEFI not found.
526 22:51:21.262543 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
527 22:51:21.271032 [ 0.000000] Zone ranges:
528 22:51:21.276787 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
529 22:51:21.282513 [ 0.000000] Normal empty
530 22:51:21.282792 [ 0.000000] HighMem empty
531 22:51:21.288262 [ 0.000000] Movable zone start for each node
532 22:51:21.288539 [ 0.000000] Early memory node ranges
533 22:51:21.299778 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
534 22:51:21.305079 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
535 22:51:21.323303 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 22:51:21.328843 [ 0.000000] AM335X ES2.1 (sgx neon)
537 22:51:21.340658 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
538 22:51:21.358275 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219960/extract-nfsrootfs-7hjuqjro,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 22:51:21.369912 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
540 22:51:21.375655 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
541 22:51:21.381451 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
542 22:51:21.391573 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
543 22:51:21.420965 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
544 22:51:21.426944 <6>[ 0.000000] trace event string verifier disabled
545 22:51:21.427273 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
546 22:51:21.432521 <6>[ 0.000000] rcu: RCU event tracing is enabled.
547 22:51:21.444011 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
548 22:51:21.449762 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
549 22:51:21.457062 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
550 22:51:21.472337 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
551 22:51:21.490014 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
552 22:51:21.496689 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
553 22:51:21.596635 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
554 22:51:21.608129 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
555 22:51:21.614883 <6>[ 0.008340] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
556 22:51:21.628056 <6>[ 0.019188] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
557 22:51:21.635528 <6>[ 0.034231] Console: colour dummy device 80x30
558 22:51:21.641583 Matched prompt #6: WARNING:
559 22:51:21.641896 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
560 22:51:21.647009 <3>[ 0.039130] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
561 22:51:21.652759 <3>[ 0.046207] This ensures that you still see kernel messages. Please
562 22:51:21.656077 <3>[ 0.052936] update your kernel commandline.
563 22:51:21.696508 <6>[ 0.057550] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
564 22:51:21.702255 <6>[ 0.096199] CPU: Testing write buffer coherency: ok
565 22:51:21.705184 <6>[ 0.101567] CPU0: Spectre v2: using BPIALL workaround
566 22:51:21.711131 <6>[ 0.107035] pid_max: default: 32768 minimum: 301
567 22:51:21.717005 <6>[ 0.112233] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 22:51:21.729623 <6>[ 0.120063] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 22:51:21.736770 <6>[ 0.129441] CPU0: thread -1, cpu 0, socket -1, mpidr 0
570 22:51:21.745080 <6>[ 0.136457] Setting up static identity map for 0x80300000 - 0x803000ac
571 22:51:21.750966 <6>[ 0.146161] rcu: Hierarchical SRCU implementation.
572 22:51:21.755543 <6>[ 0.151451] rcu: Max phase no-delay instances is 1000.
573 22:51:21.764433 <6>[ 0.162838] EFI services will not be available.
574 22:51:21.770245 <6>[ 0.168137] smp: Bringing up secondary CPUs ...
575 22:51:21.775939 <6>[ 0.173196] smp: Brought up 1 node, 1 CPU
576 22:51:21.781700 <6>[ 0.177597] SMP: Total of 1 processors activated (996.14 BogoMIPS).
577 22:51:21.787706 <6>[ 0.184369] CPU: All CPU(s) started in SVC mode.
578 22:51:21.807979 <6>[ 0.189577] Memory: 404440K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50608K reserved, 65536K cma-reserved, 0K highmem)
579 22:51:21.808235 <6>[ 0.205877] devtmpfs: initialized
580 22:51:21.831208 <6>[ 0.223785] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
581 22:51:21.842673 <6>[ 0.232402] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
582 22:51:21.848628 <6>[ 0.242867] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
583 22:51:21.859265 <6>[ 0.255165] pinctrl core: initialized pinctrl subsystem
584 22:51:21.868985 <6>[ 0.266024] DMI not present or invalid.
585 22:51:21.877383 <6>[ 0.271931] NET: Registered PF_NETLINK/PF_ROUTE protocol family
586 22:51:21.886791 <6>[ 0.280928] DMA: preallocated 256 KiB pool for atomic coherent allocations
587 22:51:21.902003 <6>[ 0.292634] thermal_sys: Registered thermal governor 'step_wise'
588 22:51:21.902282 <6>[ 0.292808] cpuidle: using governor menu
589 22:51:21.929614 <6>[ 0.328304] No ATAGs?
590 22:51:21.935792 <6>[ 0.331048] hw-breakpoint: debug architecture 0x4 unsupported.
591 22:51:21.946284 <6>[ 0.343226] Serial: AMBA PL011 UART driver
592 22:51:21.976787 <6>[ 0.375357] iommu: Default domain type: Translated
593 22:51:21.985806 <6>[ 0.380706] iommu: DMA domain TLB invalidation policy: strict mode
594 22:51:22.012648 <5>[ 0.410567] SCSI subsystem initialized
595 22:51:22.018505 <6>[ 0.415491] usbcore: registered new interface driver usbfs
596 22:51:22.024236 <6>[ 0.421564] usbcore: registered new interface driver hub
597 22:51:22.031112 <6>[ 0.427363] usbcore: registered new device driver usb
598 22:51:22.036867 <6>[ 0.433943] pps_core: LinuxPPS API ver. 1 registered
599 22:51:22.048355 <6>[ 0.439333] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
600 22:51:22.055536 <6>[ 0.449063] PTP clock support registered
601 22:51:22.055816 <6>[ 0.453530] EDAC MC: Ver: 3.0.0
602 22:51:22.109566 <6>[ 0.505693] scmi_core: SCMI protocol bus registered
603 22:51:22.124392 <6>[ 0.522391] vgaarb: loaded
604 22:51:22.130425 <6>[ 0.526199] clocksource: Switched to clocksource dmtimer
605 22:51:22.165514 <6>[ 0.563848] NET: Registered PF_INET protocol family
606 22:51:22.178227 <6>[ 0.569561] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
607 22:51:22.183996 <6>[ 0.578569] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
608 22:51:22.195513 <6>[ 0.587499] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
609 22:51:22.201225 <6>[ 0.595745] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
610 22:51:22.212851 <6>[ 0.604035] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
611 22:51:22.218729 <6>[ 0.611759] TCP: Hash tables configured (established 4096 bind 4096)
612 22:51:22.224475 <6>[ 0.618680] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
613 22:51:22.230369 <6>[ 0.625697] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
614 22:51:22.237902 <6>[ 0.633300] NET: Registered PF_UNIX/PF_LOCAL protocol family
615 22:51:22.330351 <6>[ 0.723313] RPC: Registered named UNIX socket transport module.
616 22:51:22.330632 <6>[ 0.729763] RPC: Registered udp transport module.
617 22:51:22.336103 <6>[ 0.734872] RPC: Registered tcp transport module.
618 22:51:22.341847 <6>[ 0.739994] RPC: Registered tcp-with-tls transport module.
619 22:51:22.354967 <6>[ 0.745903] RPC: Registered tcp NFSv4.1 backchannel transport module.
620 22:51:22.355248 <6>[ 0.752827] PCI: CLS 0 bytes, default 64
621 22:51:22.362025 <5>[ 0.758710] Initialise system trusted keyrings
622 22:51:22.380447 <6>[ 0.776084] Trying to unpack rootfs image as initramfs...
623 22:51:22.454128 <6>[ 0.846535] workingset: timestamp_bits=30 max_order=17 bucket_order=0
624 22:51:22.458772 <6>[ 0.854039] squashfs: version 4.0 (2009/01/31) Phillip Lougher
625 22:51:22.498251 <5>[ 0.896931] NFS: Registering the id_resolver key type
626 22:51:22.504114 <5>[ 0.902535] Key type id_resolver registered
627 22:51:22.509979 <5>[ 0.907228] Key type id_legacy registered
628 22:51:22.515594 <6>[ 0.911666] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
629 22:51:22.525319 <6>[ 0.918874] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
630 22:51:22.598001 <5>[ 0.996799] Key type asymmetric registered
631 22:51:22.603976 <5>[ 1.001327] Asymmetric key parser 'x509' registered
632 22:51:22.615462 <6>[ 1.006859] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
633 22:51:22.615743 <6>[ 1.014749] io scheduler mq-deadline registered
634 22:51:22.621341 <6>[ 1.019725] io scheduler kyber registered
635 22:51:22.626893 <6>[ 1.024182] io scheduler bfq registered
636 22:51:22.751437 <6>[ 1.146390] ledtrig-cpu: registered to indicate activity on CPUs
637 22:51:23.004136 <6>[ 1.398924] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
638 22:51:23.050721 <6>[ 1.449172] msm_serial: driver initialized
639 22:51:23.056820 <6>[ 1.453967] SuperH (H)SCI(F) driver initialized
640 22:51:23.062684 <6>[ 1.459345] STMicroelectronics ASC driver initialized
641 22:51:23.068032 <6>[ 1.464960] STM32 USART driver initialized
642 22:51:23.167263 <6>[ 1.565411] brd: module loaded
643 22:51:23.230011 <6>[ 1.627907] loop: module loaded
644 22:51:23.268824 <6>[ 1.666828] CAN device driver interface
645 22:51:23.275586 <6>[ 1.671849] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
646 22:51:23.281213 <6>[ 1.678927] e1000e: Intel(R) PRO/1000 Network Driver
647 22:51:23.287052 <6>[ 1.684317] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
648 22:51:23.292946 <6>[ 1.690788] igb: Intel(R) Gigabit Ethernet Network Driver
649 22:51:23.301126 <6>[ 1.696639] igb: Copyright (c) 2007-2014 Intel Corporation.
650 22:51:23.312989 <6>[ 1.705854] pegasus: Pegasus/Pegasus II USB Ethernet driver
651 22:51:23.318693 <6>[ 1.712033] usbcore: registered new interface driver pegasus
652 22:51:23.324440 <6>[ 1.718198] usbcore: registered new interface driver asix
653 22:51:23.330208 <6>[ 1.724054] usbcore: registered new interface driver ax88179_178a
654 22:51:23.336062 <6>[ 1.730648] usbcore: registered new interface driver cdc_ether
655 22:51:23.341810 <6>[ 1.736965] usbcore: registered new interface driver smsc75xx
656 22:51:23.347559 <6>[ 1.743176] usbcore: registered new interface driver smsc95xx
657 22:51:23.353345 <6>[ 1.749417] usbcore: registered new interface driver net1080
658 22:51:23.359186 <6>[ 1.755537] usbcore: registered new interface driver cdc_subset
659 22:51:23.364937 <6>[ 1.761951] usbcore: registered new interface driver zaurus
660 22:51:23.372525 <6>[ 1.768019] usbcore: registered new interface driver cdc_ncm
661 22:51:23.382629 <6>[ 1.777666] usbcore: registered new interface driver usb-storage
662 22:51:23.392203 <6>[ 1.789027] i2c_dev: i2c /dev entries driver
663 22:51:23.418336 <5>[ 1.808942] cpuidle: enable-method property 'ti,am3352' found operations
664 22:51:23.424063 <6>[ 1.818580] sdhci: Secure Digital Host Controller Interface driver
665 22:51:23.431705 <6>[ 1.825236] sdhci: Copyright(c) Pierre Ossman
666 22:51:23.439187 <6>[ 1.831931] Synopsys Designware Multimedia Card Interface Driver
667 22:51:23.444628 <6>[ 1.840060] sdhci-pltfm: SDHCI platform and OF driver helper
668 22:51:23.458987 <6>[ 1.850246] usbcore: registered new interface driver usbhid
669 22:51:23.459267 <6>[ 1.856370] usbhid: USB HID core driver
670 22:51:23.472394 <6>[ 1.868494] NET: Registered PF_INET6 protocol family
671 22:51:23.929225 <6>[ 2.327953] Segment Routing with IPv6
672 22:51:23.935161 <6>[ 2.332099] In-situ OAM (IOAM) with IPv6
673 22:51:23.941906 <6>[ 2.336657] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
674 22:51:23.947654 <6>[ 2.343957] NET: Registered PF_PACKET protocol family
675 22:51:23.953565 <6>[ 2.349537] can: controller area network core
676 22:51:23.959300 <6>[ 2.354366] NET: Registered PF_CAN protocol family
677 22:51:23.959582 <6>[ 2.359595] can: raw protocol
678 22:51:23.965070 <6>[ 2.362924] can: broadcast manager protocol
679 22:51:23.971530 <6>[ 2.367535] can: netlink gateway - max_hops=1
680 22:51:23.977582 <5>[ 2.373049] Key type dns_resolver registered
681 22:51:23.983955 <6>[ 2.378126] ThumbEE CPU extension supported.
682 22:51:23.984102 <5>[ 2.382821] Registering SWP/SWPB emulation handler
683 22:51:23.993627 <3>[ 2.388531] omap_voltage_late_init: Voltage driver support not added
684 22:51:24.206142 <5>[ 2.602420] Loading compiled-in X.509 certificates
685 22:51:24.329545 <6>[ 2.715317] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
686 22:51:24.336723 <6>[ 2.732034] pinctrl-single 44e10800.pinmux: 142 pins, size 568
687 22:51:24.363378 <3>[ 2.756091] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
688 22:51:24.554607 <3>[ 2.947220] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
689 22:51:24.760132 <6>[ 3.157212] OMAP GPIO hardware version 0.1
690 22:51:24.781464 <6>[ 3.176299] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
691 22:51:24.853684 <4>[ 3.248526] at24 2-0054: supply vcc not found, using dummy regulator
692 22:51:24.885218 <4>[ 3.279925] at24 2-0055: supply vcc not found, using dummy regulator
693 22:51:24.924838 <4>[ 3.319571] at24 2-0056: supply vcc not found, using dummy regulator
694 22:51:24.966708 <4>[ 3.361448] at24 2-0057: supply vcc not found, using dummy regulator
695 22:51:25.003251 <6>[ 3.398818] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
696 22:51:25.061204 <3>[ 3.452760] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
697 22:51:25.086071 <6>[ 3.473874] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 22:51:25.108391 <4>[ 3.500566] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
699 22:51:25.116194 <4>[ 3.509674] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
700 22:51:25.203280 <6>[ 3.601884] Freeing initrd memory: 14984K
701 22:51:25.211698 <6>[ 3.606624] omap_rng 48310000.rng: Random Number Generator ver. 20
702 22:51:25.235602 <5>[ 3.633436] random: crng init done
703 22:51:25.282810 <6>[ 3.676206] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
704 22:51:25.336135 <6>[ 3.728661] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
705 22:51:25.341888 <6>[ 3.738987] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
706 22:51:25.353631 <6>[ 3.746319] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
707 22:51:25.359509 <6>[ 3.753785] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
708 22:51:25.371001 <6>[ 3.761917] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
709 22:51:25.378542 <6>[ 3.773559] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
710 22:51:25.391684 <5>[ 3.782671] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
711 22:51:25.420007 <3>[ 3.813030] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
712 22:51:25.425678 <6>[ 3.821632] edma 49000000.dma: TI EDMA DMA engine driver
713 22:51:25.498320 <3>[ 3.890683] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
714 22:51:25.513255 <6>[ 3.905184] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
715 22:51:25.526195 <3>[ 3.922455] l3-aon-clkctrl:0000:0: failed to disable
716 22:51:25.581997 <6>[ 3.975008] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
717 22:51:25.587877 <6>[ 3.984531] printk: legacy console [ttyS0] enabled
718 22:51:25.593384 <6>[ 3.984531] printk: legacy console [ttyS0] enabled
719 22:51:25.599139 <6>[ 3.994878] printk: legacy bootconsole [omap8250] disabled
720 22:51:25.605077 <6>[ 3.994878] printk: legacy bootconsole [omap8250] disabled
721 22:51:25.634935 <4>[ 4.027026] tps65217-pmic: Failed to locate of_node [id: -1]
722 22:51:25.638541 <4>[ 4.034438] tps65217-bl: Failed to locate of_node [id: -1]
723 22:51:25.655468 <6>[ 4.054525] tps65217 0-0024: TPS65217 ID 0xe version 1.2
724 22:51:25.673911 <6>[ 4.061538] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
725 22:51:25.685664 <6>[ 4.075231] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
726 22:51:25.691219 <6>[ 4.087123] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
727 22:51:25.713927 <6>[ 4.107275] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
728 22:51:25.719803 <6>[ 4.116469] sdhci-omap 48060000.mmc: Got CD GPIO
729 22:51:25.727905 <4>[ 4.121618] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
730 22:51:25.742860 <4>[ 4.135424] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
731 22:51:25.749221 <4>[ 4.144188] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
732 22:51:25.759041 <4>[ 4.152823] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
733 22:51:25.858499 <6>[ 4.252954] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
734 22:51:25.898343 <6>[ 4.292003] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
735 22:51:25.943667 <6>[ 4.336391] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
736 22:51:25.950410 <6>[ 4.345224] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
737 22:51:26.017948 <6>[ 4.406670] mmc1: new high speed MMC card at address 0001
738 22:51:26.018241 <6>[ 4.414766] mmcblk1: mmc1:0001 M62704 3.56 GiB
739 22:51:26.029363 <6>[ 4.426910] mmcblk1: p1
740 22:51:26.042473 <6>[ 4.431206] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
741 22:51:26.047571 <6>[ 4.443976] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
742 22:51:26.058305 <6>[ 4.454670] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
743 22:51:26.072901 <6>[ 4.467962] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
744 22:51:29.244198 <6>[ 7.637238] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
745 22:51:29.317376 <5>[ 7.676201] Sending DHCP requests ., OK
746 22:51:29.328873 <6>[ 7.720641] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.3
747 22:51:29.329146 <6>[ 7.728904] IP-Config: Complete:
748 22:51:29.340168 <6>[ 7.732444] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.3, mask=255.255.255.0, gw=192.168.11.1
749 22:51:29.345885 <6>[ 7.743044] host=192.168.11.3, domain=usen.ad.jp, nis-domain=(none)
750 22:51:29.358123 <6>[ 7.750126] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
751 22:51:29.358397 <6>[ 7.750161] nameserver0=192.168.11.1
752 22:51:29.364218 <6>[ 7.762483] clk: Disabling unused clocks
753 22:51:29.370796 <6>[ 7.767253] PM: genpd: Disabling unused power domains
754 22:51:29.388916 <6>[ 7.784342] Freeing unused kernel image (initmem) memory: 2048K
755 22:51:29.396575 <6>[ 7.794300] Run /init as init process
756 22:51:29.422093 Loading, please wait...
757 22:51:29.499673 Starting systemd-udevd version 252.22-1~deb12u1
758 22:51:32.617697 <4>[ 11.009518] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
759 22:51:32.787706 <4>[ 11.179450] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 22:51:32.938105 <6>[ 11.337421] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
761 22:51:32.948776 <6>[ 11.343099] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
762 22:51:33.158897 <6>[ 11.556807] hub 1-0:1.0: USB hub found
763 22:51:33.181017 <6>[ 11.578544] tda998x 0-0070: found TDA19988
764 22:51:33.198765 <6>[ 11.596451] hub 1-0:1.0: 1 port detected
765 22:51:36.055332 Begin: Loading essential drivers ... done.
766 22:51:36.060826 Begin: Running /scripts/init-premount ... done.
767 22:51:36.066434 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
768 22:51:36.080340 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
769 22:51:36.080611 Device /sys/class/net/eth0 found
770 22:51:36.080854 done.
771 22:51:36.158788 Begin: Waiting up to 180 secs for any network device to become available ... done.
772 22:51:36.243082 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
773 22:51:36.243386 IP-Config: eth0 guessed broadcast address 192.168.11.255
774 22:51:36.248579 IP-Config: eth0 complete (dhcp from 192.168.11.1):
775 22:51:36.259848 address: 192.168.11.3 broadcast: 192.168.11.255 netmask: 255.255.255.0
776 22:51:36.265477 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
777 22:51:36.271076 domain : usen.ad.jp
778 22:51:36.275924 rootserver: 192.168.11.1 rootpath:
779 22:51:36.276202 filename :
780 22:51:36.377790 done.
781 22:51:36.386610 Begin: Running /scripts/nfs-bottom ... done.
782 22:51:36.454518 Begin: Running /scripts/init-bottom ... done.
783 22:51:37.879971 <30>[ 16.275045] systemd[1]: System time before build time, advancing clock.
784 22:51:38.024833 <30>[ 16.393848] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 22:51:38.033835 <30>[ 16.430774] systemd[1]: Detected architecture arm.
786 22:51:38.045813
787 22:51:38.046056 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 22:51:38.046281
789 22:51:38.093075 <30>[ 16.488844] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 22:51:40.350598 <30>[ 18.745321] systemd[1]: Queued start job for default target graphical.target.
791 22:51:40.367937 <30>[ 18.760547] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 22:51:40.375506 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 22:51:40.396174 <30>[ 18.789066] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 22:51:40.404515 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 22:51:40.426742 <30>[ 18.819627] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 22:51:40.435192 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 22:51:40.455305 <30>[ 18.848213] systemd[1]: Created slice user.slice - User and Session Slice.
798 22:51:40.461856 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 22:51:40.490338 <30>[ 18.877606] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 22:51:40.496395 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 22:51:40.514340 <30>[ 18.907347] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 22:51:40.525392 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 22:51:40.555307 <30>[ 18.937343] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 22:51:40.561677 <30>[ 18.957899] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 22:51:40.570105 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 22:51:40.593334 <30>[ 18.986706] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 22:51:40.601623 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 22:51:40.623930 <30>[ 19.017012] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 22:51:40.632471 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 22:51:40.653986 <30>[ 19.047227] systemd[1]: Reached target paths.target - Path Units.
811 22:51:40.659036 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 22:51:40.683734 <30>[ 19.076969] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 22:51:40.691035 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 22:51:40.713611 <30>[ 19.106811] systemd[1]: Reached target slices.target - Slice Units.
815 22:51:40.719066 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 22:51:40.743736 <30>[ 19.137021] systemd[1]: Reached target swap.target - Swaps.
817 22:51:40.747819 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 22:51:40.774716 <30>[ 19.168076] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 22:51:40.787035 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 22:51:40.814607 <30>[ 19.207654] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 22:51:40.822954 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 22:51:40.909906 <30>[ 19.298098] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 22:51:40.922724 <30>[ 19.315646] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 22:51:40.931146 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 22:51:40.955816 <30>[ 19.348038] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 22:51:40.963115 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 22:51:40.987100 <30>[ 19.379876] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 22:51:40.995441 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 22:51:41.018725 <30>[ 19.411463] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 22:51:41.024353 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 22:51:41.057735 <30>[ 19.449577] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 22:51:41.065282 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 22:51:41.090721 <30>[ 19.477828] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 22:51:41.107394 <30>[ 19.494350] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 22:51:41.157895 <30>[ 19.551850] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 22:51:41.189379 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 22:51:41.246581 <30>[ 19.640503] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 22:51:41.275364 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 22:51:41.334461 <30>[ 19.727356] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 22:51:41.362384 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 22:51:41.414051 <30>[ 19.807617] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 22:51:41.441805 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 22:51:41.493579 <30>[ 19.887433] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 22:51:41.515237 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 22:51:41.565441 <30>[ 19.959795] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 22:51:41.592013 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 22:51:41.645832 <30>[ 20.038978] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 22:51:41.674251 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 22:51:41.733457 <30>[ 20.127675] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 22:51:41.750475 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 22:51:41.813238 <30>[ 20.207414] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 22:51:41.833517 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 22:51:41.862256 <28>[ 20.248702] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 22:51:41.870701 <28>[ 20.264089] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 22:51:41.924888 <30>[ 20.319654] systemd[1]: Starting systemd-journald.service - Journal Service...
856 22:51:41.942175 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 22:51:42.014702 <30>[ 20.408661] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 22:51:42.043460 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 22:51:42.095244 <30>[ 20.489391] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 22:51:42.152438 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 22:51:42.220555 <30>[ 20.613271] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 22:51:42.272568 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 22:51:42.335908 <30>[ 20.729445] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 22:51:42.396797 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 22:51:42.455415 <30>[ 20.849776] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 22:51:42.519284 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 22:51:42.543908 <30>[ 20.938084] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 22:51:42.563426 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 22:51:42.578245 <30>[ 20.971359] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 22:51:42.607576 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 22:51:42.735401 <30>[ 21.130053] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 22:51:42.783422 <30>[ 21.176757] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 22:51:42.792060 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 22:51:42.813931 <30>[ 21.209031] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
875 22:51:42.843928 <30>[ 21.237967] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
876 22:51:42.863522 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 22:51:42.894344 <30>[ 21.287878] systemd[1]: Started systemd-journald.service - Journal Service.
878 22:51:42.901287 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
879 22:51:42.934274 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
880 22:51:42.967300 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
881 22:51:42.998542 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
882 22:51:43.034462 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
883 22:51:43.063466 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
884 22:51:43.085836 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
885 22:51:43.113656 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
886 22:51:43.137854 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
887 22:51:43.206779 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
888 22:51:43.242837 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
889 22:51:43.305522 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
890 22:51:43.369994 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
891 22:51:43.464691 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
892 22:51:43.622055 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
893 22:51:43.720423 <46>[ 22.113232] systemd-journald[162]: Received client request to flush runtime journal.
894 22:51:43.728764 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
895 22:51:43.839037 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
896 22:51:44.404910 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
897 22:51:44.468130 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
898 22:51:45.476774 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
899 22:51:45.505508 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
900 22:51:45.525423 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
901 22:51:45.543091 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
902 22:51:45.623671 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
903 22:51:45.672377 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
904 22:51:46.674589 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
905 22:51:46.733707 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
906 22:51:46.996132 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
907 22:51:47.093493 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
908 22:51:47.122135 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
909 22:51:48.084253 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
910 22:51:48.877064 <5>[ 27.271488] cfg80211: Loading compiled-in X.509 certificates for regulatory database
911 22:51:49.883536 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
912 22:51:50.449653 <5>[ 28.846371] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
913 22:51:50.485672 <5>[ 28.878934] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
914 22:51:50.491388 <4>[ 28.887704] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
915 22:51:50.499119 <6>[ 28.896798] cfg80211: failed to load regulatory.db
916 22:51:50.515959 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
917 22:51:51.524533 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
918 22:51:51.604643 <46>[ 29.990205] systemd-journald[162]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
919 22:51:51.829031 <46>[ 30.216825] systemd-journald[162]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
920 22:51:52.044318 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
921 22:52:01.153277 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
922 22:52:01.179845 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
923 22:52:01.204964 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
924 22:52:01.225229 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
925 22:52:01.283189 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
926 22:52:01.334119 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
927 22:52:01.375408 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
928 22:52:01.429751 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
929 22:52:01.477635 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
930 22:52:01.520292 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
931 22:52:01.548841 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
932 22:52:01.588566 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
933 22:52:01.616648 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
934 22:52:01.671601 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
935 22:52:01.706032 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
936 22:52:01.740895 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
937 22:52:01.784847 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
938 22:52:01.825864 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
939 22:52:01.854721 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
940 22:52:01.873225 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
941 22:52:01.910688 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
942 22:52:01.933500 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
943 22:52:01.955589 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
944 22:52:02.032683 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
945 22:52:02.073549 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
946 22:52:02.172791 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
947 22:52:02.254516 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
948 22:52:02.344587 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
949 22:52:02.381148 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
950 22:52:02.402386 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
951 22:52:02.646291 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
952 22:52:02.722648 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
953 22:52:02.793957 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
954 22:52:02.817743 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
955 22:52:02.844526 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
956 22:52:03.013763 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
957 22:52:03.392509 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
958 22:52:03.435879 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
959 22:52:03.467312 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
960 22:52:03.557304 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
961 22:52:03.730648 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
962 22:52:03.867249
963 22:52:03.870712 Debian GNU/Linux 12 dworm-armhf login: root (automatic login)
964 22:52:03.870971
965 22:52:04.190397 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Fri Nov 8 22:26:11 UTC 2024 armv7l
966 22:52:04.190678
967 22:52:04.195995 The programs included with the Debian GNU/Linux system are free software;
968 22:52:04.201653 the exact distribution terms for each program are described in the
969 22:52:04.207125 individual files in /usr/share/doc/*/copyright.
970 22:52:04.207372
971 22:52:04.215205 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
972 22:52:04.215469 permitted by applicable law.
973 22:52:08.932865 Unable to match end of the kernel message
975 22:52:08.933969 Setting prompt string to ['/ #']
976 22:52:08.934403 end: 2.4.4.1 login-action (duration 00:00:48) [common]
978 22:52:08.935445 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
979 22:52:08.935883 start: 2.4.5 expect-shell-connection (timeout 00:03:23) [common]
980 22:52:08.936264 Setting prompt string to ['/ #']
981 22:52:08.936598 Forcing a shell prompt, looking for ['/ #']
983 22:52:08.987295 / #
984 22:52:08.987668 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
985 22:52:08.987923 Waiting using forced prompt support (timeout 00:02:30)
986 22:52:08.992214
987 22:52:09.000561 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
988 22:52:09.000927 start: 2.4.6 export-device-env (timeout 00:03:23) [common]
989 22:52:09.001191 Sending with 10 millisecond of delay
991 22:52:14.050225 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1219960/extract-nfsrootfs-7hjuqjro'
992 22:52:14.060835 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1219960/extract-nfsrootfs-7hjuqjro'
993 22:52:14.061818 Sending with 10 millisecond of delay
995 22:52:16.220067 / # export NFS_SERVER_IP='192.168.11.5'
996 22:52:16.230651 export NFS_SERVER_IP='192.168.11.5'
997 22:52:16.232737 end: 2.4.6 export-device-env (duration 00:00:07) [common]
998 22:52:16.233088 end: 2.4 uboot-commands (duration 00:01:44) [common]
999 22:52:16.233407 end: 2 uboot-action (duration 00:01:44) [common]
1000 22:52:16.233718 start: 3 lava-test-retry (timeout 00:07:25) [common]
1001 22:52:16.234032 start: 3.1 lava-test-shell (timeout 00:07:25) [common]
1002 22:52:16.234297 Using namespace: common
1004 22:52:16.334997 / # #
1005 22:52:16.335373 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1006 22:52:16.339830 #
1007 22:52:16.346921 Using /lava-1219960
1009 22:52:16.447647 / # export SHELL=/bin/bash
1010 22:52:16.452452 export SHELL=/bin/bash
1012 22:52:16.559537 / # . /lava-1219960/environment
1013 22:52:16.564374 . /lava-1219960/environment
1015 22:52:16.678392 / # /lava-1219960/bin/lava-test-runner /lava-1219960/0
1016 22:52:16.678783 Test shell timeout: 10s (minimum of the action and connection timeout)
1017 22:52:16.683239 /lava-1219960/bin/lava-test-runner /lava-1219960/0
1018 22:52:17.114105 + export TESTRUN_ID=0_timesync-off
1019 22:52:17.122161 + TESTRUN_ID=0_timesync-off
1020 22:52:17.122446 + cd /lava-1219960/0/tests/0_timesync-off
1021 22:52:17.122677 ++ cat uuid
1022 22:52:17.139326 + UUID=1219960_1.6.2.4.1
1023 22:52:17.139637 + set +x
1024 22:52:17.144930 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1219960_1.6.2.4.1>
1025 22:52:17.145400 Received signal: <STARTRUN> 0_timesync-off 1219960_1.6.2.4.1
1026 22:52:17.145639 Starting test lava.0_timesync-off (1219960_1.6.2.4.1)
1027 22:52:17.145917 Skipping test definition patterns.
1028 22:52:17.148116 + systemctl stop systemd-timesyncd
1029 22:52:17.449220 + set +x
1030 22:52:17.449708 Received signal: <ENDRUN> 0_timesync-off 1219960_1.6.2.4.1
1031 22:52:17.449986 Ending use of test pattern.
1032 22:52:17.450213 Ending test lava.0_timesync-off (1219960_1.6.2.4.1), duration 0.30
1034 22:52:17.452319 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1219960_1.6.2.4.1>
1035 22:52:17.629373 + export TESTRUN_ID=1_kselftest-dt
1036 22:52:17.637396 + TESTRUN_ID=1_kselftest-dt
1037 22:52:17.637679 + cd /lava-1219960/0/tests/1_kselftest-dt
1038 22:52:17.637927 ++ cat uuid
1039 22:52:17.654293 + UUID=1219960_1.6.2.4.5
1040 22:52:17.654604 + set +x
1041 22:52:17.659905 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1219960_1.6.2.4.5>
1042 22:52:17.660202 + cd ./automated/linux/kselftest/
1043 22:52:17.660689 Received signal: <STARTRUN> 1_kselftest-dt 1219960_1.6.2.4.5
1044 22:52:17.660984 Starting test lava.1_kselftest-dt (1219960_1.6.2.4.5)
1045 22:52:17.661312 Skipping test definition patterns.
1046 22:52:17.688485 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1047 22:52:17.808386 INFO: install_deps skipped
1048 22:52:18.372647 --2024-11-08 22:52:18-- http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz
1049 22:52:18.393055 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1050 22:52:18.507107 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1051 22:52:18.620534 HTTP request sent, awaiting response... 200 OK
1052 22:52:18.620903 Length: 2557756 (2.4M) [application/octet-stream]
1053 22:52:18.626171 Saving to: 'kselftest_armhf.tar.gz'
1054 22:52:18.626449
1055 22:52:20.012534 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 1%[ ] 49.92K 225KB/s kselftest_armhf.tar 7%[> ] 194.76K 433KB/s kselftest_armhf.tar 24%[===> ] 606.79K 588KB/s kselftest_armhf.tar 78%[==============> ] 1.92M 1.55MB/s kselftest_armhf.tar 100%[===================>] 2.44M 1.76MB/s in 1.4s
1056 22:52:20.012928
1057 22:52:20.339577 2024-11-08 22:52:19 (1.76 MB/s) - 'kselftest_armhf.tar.gz' saved [2557756/2557756]
1058 22:52:20.339930
1059 22:52:41.055400 skiplist:
1060 22:52:41.055764 ========================================
1061 22:52:41.061156 ========================================
1062 22:52:41.171798 dt:test_unprobed_devices.sh
1063 22:52:41.204779 ============== Tests to run ===============
1064 22:52:41.213846 dt:test_unprobed_devices.sh
1065 22:52:41.217805 ===========End Tests to run ===============
1066 22:52:41.228381 shardfile-dt pass
1067 22:52:41.466543 <12>[ 79.866860] kselftest: Running tests in dt
1068 22:52:41.495950 TAP version 13
1069 22:52:41.520340 1..1
1070 22:52:41.578179 # timeout set to 45
1071 22:52:41.578458 # selftests: dt: test_unprobed_devices.sh
1072 22:52:42.454745 # TAP version 13
1073 22:53:08.255433 # 1..257
1074 22:53:08.429950 # ok 1 / # SKIP
1075 22:53:08.452706 # ok 2 /clk_mcasp0
1076 22:53:08.526626 # ok 3 /clk_mcasp0_fixed # SKIP
1077 22:53:08.602702 # ok 4 /cpus/cpu@0 # SKIP
1078 22:53:08.679515 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1079 22:53:08.701470 # ok 6 /fixedregulator0
1080 22:53:08.717607 # ok 7 /leds
1081 22:53:08.741774 # ok 8 /ocp
1082 22:53:08.765744 # ok 9 /ocp/interconnect@44c00000
1083 22:53:08.789728 # ok 10 /ocp/interconnect@44c00000/segment@0
1084 22:53:08.815018 # ok 11 /ocp/interconnect@44c00000/segment@100000
1085 22:53:08.838662 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1086 22:53:08.912168 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1087 22:53:08.933294 # ok 14 /ocp/interconnect@44c00000/segment@200000
1088 22:53:08.958787 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1089 22:53:09.069514 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1090 22:53:09.148077 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1091 22:53:09.225110 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1092 22:53:09.299123 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1093 22:53:09.376557 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1094 22:53:09.455341 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1095 22:53:09.528914 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1096 22:53:09.601543 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1097 22:53:09.676091 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1098 22:53:09.751631 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1099 22:53:09.825451 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1100 22:53:09.901575 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1101 22:53:09.976218 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1102 22:53:10.051982 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1103 22:53:10.126347 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1104 22:53:10.202066 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1105 22:53:10.276684 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1106 22:53:10.352688 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1107 22:53:10.427191 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1108 22:53:10.503819 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1109 22:53:10.584460 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1110 22:53:10.659083 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1111 22:53:10.735332 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1112 22:53:10.809299 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1113 22:53:10.881916 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1114 22:53:10.956070 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1115 22:53:11.036373 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1116 22:53:11.110335 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1117 22:53:11.187282 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1118 22:53:11.261359 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1119 22:53:11.335313 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1120 22:53:11.412130 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1121 22:53:11.487065 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1122 22:53:11.567174 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1123 22:53:11.640069 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1124 22:53:11.714935 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1125 22:53:11.791045 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1126 22:53:11.866560 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1127 22:53:11.941865 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1128 22:53:12.016692 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1129 22:53:12.093482 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1130 22:53:12.171267 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1131 22:53:12.246176 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1132 22:53:12.321613 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1133 22:53:12.396747 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1134 22:53:12.472985 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1135 22:53:12.548458 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1136 22:53:12.624407 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1137 22:53:12.704253 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1138 22:53:12.778937 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1139 22:53:12.856274 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1140 22:53:12.930234 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1141 22:53:13.002973 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1142 22:53:13.078323 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1143 22:53:13.155748 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1144 22:53:13.231591 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1145 22:53:13.306975 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1146 22:53:13.382569 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1147 22:53:13.457517 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1148 22:53:13.533710 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1149 22:53:13.609861 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1150 22:53:13.684484 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1151 22:53:13.765234 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1152 22:53:13.836745 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1153 22:53:13.912754 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1154 22:53:13.988097 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1155 22:53:14.063973 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1156 22:53:14.139716 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1157 22:53:14.214084 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1158 22:53:14.295086 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1159 22:53:14.368856 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1160 22:53:14.444934 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1161 22:53:14.520116 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1162 22:53:14.600484 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1163 22:53:14.674570 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1164 22:53:14.748115 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1165 22:53:14.826354 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1166 22:53:14.901231 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1167 22:53:14.977571 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1168 22:53:14.999555 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1169 22:53:15.024471 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1170 22:53:15.054061 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1171 22:53:15.077340 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1172 22:53:15.099971 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1173 22:53:15.124593 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1174 22:53:15.149810 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1175 22:53:15.173009 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1176 22:53:15.284295 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1177 22:53:15.314295 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1178 22:53:15.338419 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1179 22:53:15.360334 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1180 22:53:15.471011 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1181 22:53:15.549174 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1182 22:53:15.625175 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1183 22:53:15.703532 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1184 22:53:15.777634 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1185 22:53:15.853973 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1186 22:53:15.929691 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1187 22:53:16.005649 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1188 22:53:16.081688 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1189 22:53:16.158459 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1190 22:53:16.233962 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1191 22:53:16.309508 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1192 22:53:16.384593 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1193 22:53:16.470207 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1194 22:53:16.539651 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1195 22:53:16.615329 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1196 22:53:16.637122 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1197 22:53:16.715200 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1198 22:53:16.786880 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1199 22:53:16.860588 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1200 22:53:16.883237 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1201 22:53:16.963557 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1202 22:53:16.986307 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1203 22:53:17.058225 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1204 22:53:17.086298 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1205 22:53:17.111415 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1206 22:53:17.130173 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1207 22:53:17.155918 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1208 22:53:17.179813 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1209 22:53:17.204551 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1210 22:53:17.236162 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1211 22:53:17.310285 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1212 22:53:17.332415 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1213 22:53:17.356413 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1214 22:53:17.436801 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1215 22:53:17.508788 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1216 22:53:17.529034 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1217 22:53:17.640198 # not ok 144 /ocp/interconnect@47c00000
1218 22:53:17.714513 # not ok 145 /ocp/interconnect@47c00000/segment@0
1219 22:53:17.737377 # ok 146 /ocp/interconnect@48000000
1220 22:53:17.762316 # ok 147 /ocp/interconnect@48000000/segment@0
1221 22:53:17.785988 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1222 22:53:17.807946 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1223 22:53:17.831885 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1224 22:53:17.860169 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1225 22:53:17.884809 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1226 22:53:17.906475 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1227 22:53:17.933895 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1228 22:53:18.006283 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1229 22:53:18.085898 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1230 22:53:18.105945 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1231 22:53:18.129392 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1232 22:53:18.152261 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1233 22:53:18.177606 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1234 22:53:18.205162 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1235 22:53:18.226591 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1236 22:53:18.253817 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1237 22:53:18.276509 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1238 22:53:18.298008 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1239 22:53:18.322328 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1240 22:53:18.347899 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1241 22:53:18.375570 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1242 22:53:18.395877 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1243 22:53:18.419728 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1244 22:53:18.445865 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1245 22:53:18.475793 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1246 22:53:18.495831 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1247 22:53:18.519240 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1248 22:53:18.540186 # ok 175 /ocp/interconnect@48000000/segment@100000
1249 22:53:18.570690 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1250 22:53:18.591608 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1251 22:53:18.671736 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1252 22:53:18.746642 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1253 22:53:18.825113 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1254 22:53:18.900104 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1255 22:53:18.971014 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1256 22:53:19.047900 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1257 22:53:19.121020 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1258 22:53:19.197349 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1259 22:53:19.218390 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1260 22:53:19.242239 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1261 22:53:19.272134 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1262 22:53:19.290093 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1263 22:53:19.314816 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1264 22:53:19.345082 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1265 22:53:19.366313 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1266 22:53:19.389967 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1267 22:53:19.413203 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1268 22:53:19.437003 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1269 22:53:19.462175 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1270 22:53:19.494077 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1271 22:53:19.514631 # ok 198 /ocp/interconnect@48000000/segment@200000
1272 22:53:19.543898 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1273 22:53:19.616119 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1274 22:53:19.640392 # ok 201 /ocp/interconnect@48000000/segment@300000
1275 22:53:19.665872 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1276 22:53:19.685753 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1277 22:53:19.715404 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1278 22:53:19.736105 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1279 22:53:19.763660 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1280 22:53:19.786169 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1281 22:53:19.863595 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1282 22:53:19.883276 # ok 209 /ocp/interconnect@4a000000
1283 22:53:19.904117 # ok 210 /ocp/interconnect@4a000000/segment@0
1284 22:53:19.933773 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1285 22:53:19.956628 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1286 22:53:19.980652 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1287 22:53:20.005895 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1288 22:53:20.077936 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1289 22:53:20.189931 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1290 22:53:20.264650 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1291 22:53:20.373719 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1292 22:53:20.447436 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1293 22:53:20.521501 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1294 22:53:20.625690 # not ok 221 /ocp/interconnect@4b140000
1295 22:53:20.704511 # not ok 222 /ocp/interconnect@4b140000/segment@0
1296 22:53:20.776820 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1297 22:53:20.798309 # ok 224 /ocp/target-module@40300000
1298 22:53:20.823899 # ok 225 /ocp/target-module@40300000/sram@0
1299 22:53:20.904497 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1300 22:53:20.976153 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1301 22:53:21.000645 # ok 228 /ocp/target-module@47400000
1302 22:53:21.025090 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1303 22:53:21.044923 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1304 22:53:21.069083 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1305 22:53:21.093972 # ok 232 /ocp/target-module@47400000/usb@1400
1306 22:53:21.119931 # ok 233 /ocp/target-module@47400000/usb@1800
1307 22:53:21.142210 # ok 234 /ocp/target-module@47810000
1308 22:53:21.160784 # ok 235 /ocp/target-module@49000000
1309 22:53:21.185348 # ok 236 /ocp/target-module@49000000/dma@0
1310 22:53:21.212143 # ok 237 /ocp/target-module@49800000
1311 22:53:21.233888 # ok 238 /ocp/target-module@49800000/dma@0
1312 22:53:21.258956 # ok 239 /ocp/target-module@49900000
1313 22:53:21.278172 # ok 240 /ocp/target-module@49900000/dma@0
1314 22:53:21.303347 # ok 241 /ocp/target-module@49a00000
1315 22:53:21.325183 # ok 242 /ocp/target-module@49a00000/dma@0
1316 22:53:21.352748 # ok 243 /ocp/target-module@4c000000
1317 22:53:21.428934 # not ok 244 /ocp/target-module@4c000000/emif@0
1318 22:53:21.451088 # ok 245 /ocp/target-module@50000000
1319 22:53:21.469641 # ok 246 /ocp/target-module@53100000
1320 22:53:21.545672 # not ok 247 /ocp/target-module@53100000/sham@0
1321 22:53:21.572230 # ok 248 /ocp/target-module@53500000
1322 22:53:21.644187 # not ok 249 /ocp/target-module@53500000/aes@0
1323 22:53:21.670233 # ok 250 /ocp/target-module@56000000
1324 22:53:21.776238 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1325 22:53:21.852265 # ok 252 /opp-table # SKIP
1326 22:53:21.922254 # ok 253 /soc # SKIP
1327 22:53:21.944500 # ok 254 /sound
1328 22:53:21.972972 # ok 255 /target-module@4b000000
1329 22:53:21.995159 # ok 256 /target-module@4b000000/target-module@140000
1330 22:53:22.017095 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1331 22:53:22.025365 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1332 22:53:22.034684 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1333 22:53:24.288670 dt_test_unprobed_devices_sh_ skip
1334 22:53:24.294185 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1335 22:53:24.299652 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1336 22:53:24.299908 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1337 22:53:24.305401 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1338 22:53:24.310922 dt_test_unprobed_devices_sh_fixedregulator0 pass
1339 22:53:24.316537 dt_test_unprobed_devices_sh_leds pass
1340 22:53:24.316796 dt_test_unprobed_devices_sh_ocp pass
1341 22:53:24.322155 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1342 22:53:24.327844 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1343 22:53:24.333429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1344 22:53:24.344613 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1345 22:53:24.350178 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1346 22:53:24.355775 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1347 22:53:24.367026 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1348 22:53:24.372521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1349 22:53:24.383777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1350 22:53:24.395075 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1351 22:53:24.406279 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1352 22:53:24.411903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1353 22:53:24.423088 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1354 22:53:24.434463 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1355 22:53:24.445546 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1356 22:53:24.456642 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1357 22:53:24.462436 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1358 22:53:24.473570 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1359 22:53:24.484650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1360 22:53:24.495895 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1361 22:53:24.507018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1362 22:53:24.512651 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1363 22:53:24.523894 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1364 22:53:24.535059 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1365 22:53:24.546317 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1366 22:53:24.551894 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1367 22:53:24.563017 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1368 22:53:24.574309 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1369 22:53:24.585391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1370 22:53:24.596639 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1371 22:53:24.602317 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1372 22:53:24.613469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1373 22:53:24.624644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1374 22:53:24.635794 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1375 22:53:24.647015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1376 22:53:24.658201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1377 22:53:24.669429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1378 22:53:24.680513 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1379 22:53:24.691763 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1380 22:53:24.703047 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1381 22:53:24.714146 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1382 22:53:24.725406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1383 22:53:24.736547 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1384 22:53:24.747784 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1385 22:53:24.758908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1386 22:53:24.770154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1387 22:53:24.781452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1388 22:53:24.792516 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1389 22:53:24.803654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1390 22:53:24.814946 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1391 22:53:24.826070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1392 22:53:24.837429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1393 22:53:24.848508 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1394 22:53:24.859639 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1395 22:53:24.870878 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1396 22:53:24.882006 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1397 22:53:24.887698 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1398 22:53:24.898767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1399 22:53:24.910008 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1400 22:53:24.921297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1401 22:53:24.932382 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1402 22:53:24.943711 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1403 22:53:24.954833 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1404 22:53:24.966064 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1405 22:53:24.977208 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1406 22:53:24.988437 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1407 22:53:24.999691 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1408 22:53:25.010818 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1409 22:53:25.022064 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1410 22:53:25.033195 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1411 22:53:25.044441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1412 22:53:25.055560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1413 22:53:25.066816 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1414 22:53:25.077877 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1415 22:53:25.083521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1416 22:53:25.094783 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1417 22:53:25.105893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1418 22:53:25.117179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1419 22:53:25.128381 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1420 22:53:25.133878 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1421 22:53:25.150861 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1422 22:53:25.161876 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1423 22:53:25.167502 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1424 22:53:25.184388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1425 22:53:25.195521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1426 22:53:25.206664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1427 22:53:25.212250 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1428 22:53:25.223495 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1429 22:53:25.234724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1430 22:53:25.240264 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1431 22:53:25.251399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1432 22:53:25.262712 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1433 22:53:25.268250 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1434 22:53:25.279370 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1435 22:53:25.285053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1436 22:53:25.296273 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1437 22:53:25.307372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1438 22:53:25.318661 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1439 22:53:25.329740 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1440 22:53:25.341034 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1441 22:53:25.352113 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1442 22:53:25.363362 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1443 22:53:25.374487 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1444 22:53:25.385753 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1445 22:53:25.396887 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1446 22:53:25.408109 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1447 22:53:25.419359 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1448 22:53:25.436140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1449 22:53:25.447421 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1450 22:53:25.458518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1451 22:53:25.469655 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1452 22:53:25.480919 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1453 22:53:25.497623 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1454 22:53:25.508881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1455 22:53:25.519980 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1456 22:53:25.531231 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1457 22:53:25.536884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1458 22:53:25.548087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1459 22:53:25.559265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1460 22:53:25.564768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1461 22:53:25.576005 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1462 22:53:25.581659 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1463 22:53:25.592761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1464 22:53:25.598397 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1465 22:53:25.609634 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1466 22:53:25.615261 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1467 22:53:25.626404 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1468 22:53:25.632009 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1469 22:53:25.643116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1470 22:53:25.654405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1471 22:53:25.665629 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1472 22:53:25.676757 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1473 22:53:25.688015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1474 22:53:25.693519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1475 22:53:25.704758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1476 22:53:25.710382 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1477 22:53:25.715875 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1478 22:53:25.721525 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1479 22:53:25.727127 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1480 22:53:25.732907 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1481 22:53:25.743895 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1482 22:53:25.749528 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1483 22:53:25.755155 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1484 22:53:25.766391 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1485 22:53:25.771900 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1486 22:53:25.783122 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1487 22:53:25.788757 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1488 22:53:25.799869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1489 22:53:25.805515 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1490 22:53:25.816618 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1491 22:53:25.822389 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1492 22:53:25.833507 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1493 22:53:25.838996 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1494 22:53:25.850245 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1495 22:53:25.855874 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1496 22:53:25.866994 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1497 22:53:25.872634 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1498 22:53:25.878254 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1499 22:53:25.889393 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1500 22:53:25.894995 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1501 22:53:25.906260 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1502 22:53:25.911745 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1503 22:53:25.922994 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1504 22:53:25.928623 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1505 22:53:25.939739 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1506 22:53:25.945369 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1507 22:53:25.950996 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1508 22:53:25.962106 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1509 22:53:25.967744 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1510 22:53:25.978990 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1511 22:53:25.990121 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1512 22:53:26.001406 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1513 22:53:26.012488 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1514 22:53:26.023745 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1515 22:53:26.034872 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1516 22:53:26.046123 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1517 22:53:26.057388 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1518 22:53:26.062902 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1519 22:53:26.074125 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1520 22:53:26.079741 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1521 22:53:26.090858 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1522 22:53:26.096495 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1523 22:53:26.107610 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1524 22:53:26.113387 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1525 22:53:26.124493 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1526 22:53:26.130119 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1527 22:53:26.141386 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1528 22:53:26.146882 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1529 22:53:26.157985 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1530 22:53:26.163635 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1531 22:53:26.174863 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1532 22:53:26.180486 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1533 22:53:26.186001 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1534 22:53:26.197259 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1535 22:53:26.202867 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1536 22:53:26.213981 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1537 22:53:26.219618 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1538 22:53:26.230728 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1539 22:53:26.236358 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1540 22:53:26.247610 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1541 22:53:26.253259 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1542 22:53:26.258745 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1543 22:53:26.264358 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1544 22:53:26.275607 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1545 22:53:26.286756 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1546 22:53:26.292379 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1547 22:53:26.297993 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1548 22:53:26.309122 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1549 22:53:26.320379 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1550 22:53:26.331479 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1551 22:53:26.342734 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1552 22:53:26.348354 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1553 22:53:26.353983 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1554 22:53:26.359617 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1555 22:53:26.365256 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1556 22:53:26.370854 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1557 22:53:26.376480 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1558 22:53:26.387597 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1559 22:53:26.393258 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1560 22:53:26.398860 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1561 22:53:26.404483 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1562 22:53:26.409978 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1563 22:53:26.421224 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1564 22:53:26.426860 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1565 22:53:26.432476 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1566 22:53:26.437977 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1567 22:53:26.443601 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1568 22:53:26.449389 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1569 22:53:26.454858 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1570 22:53:26.460477 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1571 22:53:26.466012 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1572 22:53:26.471649 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1573 22:53:26.477400 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1574 22:53:26.482904 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1575 22:53:26.488509 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1576 22:53:26.494140 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1577 22:53:26.499761 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1578 22:53:26.505399 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1579 22:53:26.510888 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1580 22:53:26.516509 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1581 22:53:26.522134 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1582 22:53:26.527772 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1583 22:53:26.533401 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1584 22:53:26.533670 dt_test_unprobed_devices_sh_opp-table skip
1585 22:53:26.538888 dt_test_unprobed_devices_sh_soc skip
1586 22:53:26.544509 dt_test_unprobed_devices_sh_sound pass
1587 22:53:26.550143 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1588 22:53:26.555761 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1589 22:53:26.561381 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1590 22:53:26.567009 dt_test_unprobed_devices_sh fail
1591 22:53:26.567284 + ../../utils/send-to-lava.sh ./output/result.txt
1592 22:53:26.574851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1593 22:53:26.575383 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1595 22:53:26.588701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1596 22:53:26.589197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1598 22:53:26.689105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1599 22:53:26.689591 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1601 22:53:26.786586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1602 22:53:26.787188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1604 22:53:26.883939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1605 22:53:26.884417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1607 22:53:26.984181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1608 22:53:26.984666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1610 22:53:27.079803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1611 22:53:27.080368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1613 22:53:27.177702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1614 22:53:27.178232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1616 22:53:27.278859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1617 22:53:27.279395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1619 22:53:27.380036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1620 22:53:27.380533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1622 22:53:27.480799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1623 22:53:27.481296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1625 22:53:27.579752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1626 22:53:27.580253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1628 22:53:27.682007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1629 22:53:27.682508 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1631 22:53:27.779619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1632 22:53:27.780171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1634 22:53:27.875875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1635 22:53:27.876429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1637 22:53:27.974288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1638 22:53:27.974771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1640 22:53:28.077555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1641 22:53:28.078100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1643 22:53:28.179581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1644 22:53:28.180057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1646 22:53:28.284405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1647 22:53:28.284891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1649 22:53:28.388024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1650 22:53:28.388513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1652 22:53:28.492380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1653 22:53:28.492858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1655 22:53:28.599184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1656 22:53:28.599668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1658 22:53:28.700502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1659 22:53:28.701006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1661 22:53:28.805005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1662 22:53:28.805544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1664 22:53:28.905721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1665 22:53:28.906199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1667 22:53:29.008581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1668 22:53:29.009091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1670 22:53:29.114900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1671 22:53:29.115462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1673 22:53:29.217534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1674 22:53:29.218018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1676 22:53:29.324785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1677 22:53:29.325275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1679 22:53:29.427454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1680 22:53:29.427942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1682 22:53:29.527692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1683 22:53:29.528166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1685 22:53:29.632583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1686 22:53:29.633098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1688 22:53:29.735091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1689 22:53:29.735567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1691 22:53:29.835480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1692 22:53:29.836030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1694 22:53:29.935993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1695 22:53:29.936467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1697 22:53:30.041125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1698 22:53:30.041614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1700 22:53:30.144145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1701 22:53:30.144724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1703 22:53:30.246379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1704 22:53:30.246869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1706 22:53:30.348552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1707 22:53:30.349061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1709 22:53:30.450517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1710 22:53:30.451007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1712 22:53:30.550732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1713 22:53:30.551228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1715 22:53:30.650618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1716 22:53:30.651131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1718 22:53:30.752146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1719 22:53:30.752735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1721 22:53:30.855942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1722 22:53:30.856432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1724 22:53:30.957087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1725 22:53:30.957576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1727 22:53:31.057760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1728 22:53:31.058254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1730 22:53:31.158618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1731 22:53:31.159161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1733 22:53:31.256273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1734 22:53:31.256764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1736 22:53:31.355291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1737 22:53:31.355770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1739 22:53:31.453142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1740 22:53:31.453619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1742 22:53:31.550282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1743 22:53:31.550757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1745 22:53:31.651528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1746 22:53:31.652006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1748 22:53:31.771798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1749 22:53:31.772344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1751 22:53:31.876008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1752 22:53:31.876483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1754 22:53:31.975497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1755 22:53:31.975975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1757 22:53:32.073365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1758 22:53:32.073846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1760 22:53:32.176623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1761 22:53:32.177197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1763 22:53:32.277863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1764 22:53:32.278345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1766 22:53:32.378223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1767 22:53:32.378703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1769 22:53:32.478355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1770 22:53:32.478836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1772 22:53:32.585779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1773 22:53:32.586262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1775 22:53:32.686694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1776 22:53:32.687185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1778 22:53:32.785479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1779 22:53:32.786038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1781 22:53:32.886071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1782 22:53:32.886553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1784 22:53:32.991016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1785 22:53:32.991508 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1787 22:53:33.095751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1788 22:53:33.096304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1790 22:53:33.199608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1791 22:53:33.200130 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1793 22:53:33.303222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1794 22:53:33.303710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1796 22:53:33.405604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1797 22:53:33.406095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1799 22:53:33.506623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1800 22:53:33.507154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1802 22:53:33.609385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1803 22:53:33.609896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1805 22:53:33.714666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1806 22:53:33.715151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1808 22:53:33.815868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1809 22:53:33.816431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1811 22:53:33.917984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1812 22:53:33.918505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1814 22:53:34.019228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1815 22:53:34.019725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1817 22:53:34.122714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1818 22:53:34.123276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1820 22:53:34.226225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1821 22:53:34.226725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1823 22:53:34.328210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1824 22:53:34.328701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1826 22:53:34.431714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1827 22:53:34.432214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1829 22:53:34.535210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1830 22:53:34.535730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1832 22:53:34.635821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1833 22:53:34.636310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1835 22:53:34.738703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1836 22:53:34.739217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1838 22:53:34.843203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1839 22:53:34.843779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1841 22:53:34.945706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1842 22:53:34.946203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1844 22:53:35.044318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1845 22:53:35.044778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1847 22:53:35.146234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1848 22:53:35.146787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1850 22:53:35.250434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1851 22:53:35.250923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1853 22:53:35.350308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1854 22:53:35.350803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1856 22:53:35.448983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1857 22:53:35.449478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1859 22:53:35.551381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1860 22:53:35.551863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1862 22:53:35.652554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1863 22:53:35.653068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1865 22:53:35.755174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1866 22:53:35.755662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1868 22:53:35.856331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1869 22:53:35.856890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1871 22:53:35.952690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1872 22:53:35.953193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1874 22:53:36.058254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1875 22:53:36.058744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1877 22:53:36.156883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1878 22:53:36.157442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1880 22:53:36.260772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1881 22:53:36.261256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1883 22:53:36.368137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1884 22:53:36.368625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1886 22:53:36.470475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1887 22:53:36.470962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1889 22:53:36.570663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1890 22:53:36.571202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1892 22:53:36.673380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1893 22:53:36.673873 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1895 22:53:36.772584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1896 22:53:36.773152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1898 22:53:36.870288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1899 22:53:36.870782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1901 22:53:36.974487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1902 22:53:36.974977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1904 22:53:37.078080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1905 22:53:37.078570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1907 22:53:37.179394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1908 22:53:37.179948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1910 22:53:37.283107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1911 22:53:37.283593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1913 22:53:37.385227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1914 22:53:37.385716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1916 22:53:37.488103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1917 22:53:37.488592 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1919 22:53:37.590972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1920 22:53:37.591462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1922 22:53:37.690594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1923 22:53:37.691092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1925 22:53:37.789846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1926 22:53:37.790407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1928 22:53:37.891087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1929 22:53:37.891576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1931 22:53:37.993583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1932 22:53:37.994075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1934 22:53:38.096507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1935 22:53:38.097115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1937 22:53:38.197697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1938 22:53:38.198190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1940 22:53:38.299669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1941 22:53:38.300159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1943 22:53:38.406161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1944 22:53:38.406646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1946 22:53:38.504625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1947 22:53:38.505133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1949 22:53:38.602121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1950 22:53:38.602622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1952 22:53:38.705887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1954 22:53:38.708903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1955 22:53:38.806403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1957 22:53:38.809390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1958 22:53:38.905775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1960 22:53:38.908759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1961 22:53:39.008756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1962 22:53:39.009272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1964 22:53:39.108571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1965 22:53:39.109149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1967 22:53:39.206544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1968 22:53:39.207036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1970 22:53:39.306530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1971 22:53:39.307018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1973 22:53:39.406647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1974 22:53:39.407143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1976 22:53:39.504985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1977 22:53:39.505495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1979 22:53:39.606301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1980 22:53:39.606795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1982 22:53:39.709148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1983 22:53:39.709632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1985 22:53:39.803659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1986 22:53:39.804196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1988 22:53:39.901349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1989 22:53:39.901840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1991 22:53:39.999339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1992 22:53:39.999832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1994 22:53:40.100759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1995 22:53:40.101332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1997 22:53:40.199573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1998 22:53:40.200070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2000 22:53:40.297121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2001 22:53:40.297610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2003 22:53:40.397582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2004 22:53:40.398070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2006 22:53:40.498915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2007 22:53:40.499394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2009 22:53:40.603308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2010 22:53:40.603786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2012 22:53:40.705328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2013 22:53:40.705816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2015 22:53:40.807431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2016 22:53:40.807979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2018 22:53:40.911291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2019 22:53:40.911766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2021 22:53:41.013014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2022 22:53:41.013488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2024 22:53:41.111955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2025 22:53:41.112500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2027 22:53:41.214342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2028 22:53:41.214828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2030 22:53:41.314469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2031 22:53:41.314957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2033 22:53:41.414458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2034 22:53:41.414954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2036 22:53:41.515919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2037 22:53:41.516407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2039 22:53:41.616928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2040 22:53:41.617417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2042 22:53:41.716017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2043 22:53:41.716498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2045 22:53:41.815975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2046 22:53:41.816556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2048 22:53:41.915739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2049 22:53:41.916216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2051 22:53:42.016029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2052 22:53:42.016538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2054 22:53:42.115291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2055 22:53:42.115834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2057 22:53:42.216508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2058 22:53:42.217008 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2060 22:53:42.315912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2061 22:53:42.316416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2063 22:53:42.415248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2064 22:53:42.415726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2066 22:53:42.514925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2067 22:53:42.515403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2069 22:53:42.615255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2070 22:53:42.615737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2072 22:53:42.717423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2073 22:53:42.717908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2075 22:53:42.815730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2076 22:53:42.816275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2078 22:53:42.916203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2079 22:53:42.916688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2081 22:53:43.016814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2082 22:53:43.017291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2084 22:53:43.114332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2085 22:53:43.114882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2087 22:53:43.209855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2088 22:53:43.210336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2090 22:53:43.308771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2091 22:53:43.309257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2093 22:53:43.407329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2094 22:53:43.407813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2096 22:53:43.503813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2097 22:53:43.504288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2099 22:53:43.598477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2100 22:53:43.598951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2102 22:53:43.702806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2103 22:53:43.703284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2105 22:53:43.802916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2106 22:53:43.803457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2108 22:53:43.902273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2109 22:53:43.902749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2111 22:53:43.999286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2112 22:53:43.999761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2114 22:53:44.100532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2115 22:53:44.101024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2117 22:53:44.200812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2118 22:53:44.201349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2120 22:53:44.302653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2121 22:53:44.303138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2123 22:53:44.404041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2124 22:53:44.404527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2126 22:53:44.505561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2127 22:53:44.506053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2129 22:53:44.608830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2130 22:53:44.609323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2132 22:53:44.709036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2133 22:53:44.709507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2135 22:53:44.809065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2136 22:53:44.809610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2138 22:53:44.908155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2139 22:53:44.908627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2141 22:53:45.005391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2142 22:53:45.005870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2144 22:53:45.104894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2145 22:53:45.105377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2147 22:53:45.206891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2148 22:53:45.207437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2150 22:53:45.304164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2151 22:53:45.304641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2153 22:53:45.403874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2154 22:53:45.404359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2156 22:53:45.505256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2157 22:53:45.505729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2159 22:53:45.605754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2160 22:53:45.606243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2162 22:53:45.707264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2163 22:53:45.707741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2165 22:53:45.808021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2166 22:53:45.808570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2168 22:53:45.905911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2169 22:53:45.906389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2171 22:53:46.006728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2172 22:53:46.007213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2174 22:53:46.107341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2175 22:53:46.107820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2177 22:53:46.206486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2178 22:53:46.207031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2180 22:53:46.306088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2181 22:53:46.306565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2183 22:53:46.405884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2184 22:53:46.406367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2186 22:53:46.503216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2187 22:53:46.503690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2189 22:53:46.605866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2190 22:53:46.606348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2192 22:53:46.706948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2193 22:53:46.707424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2195 22:53:46.804966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2196 22:53:46.805506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2198 22:53:46.907237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2199 22:53:46.907715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2201 22:53:47.011844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2202 22:53:47.012322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2204 22:53:47.114164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2205 22:53:47.114647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2207 22:53:47.212362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2208 22:53:47.212939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2210 22:53:47.313356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2211 22:53:47.313845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2213 22:53:47.415719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2214 22:53:47.416215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2216 22:53:47.516114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2217 22:53:47.516633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2219 22:53:47.612477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2220 22:53:47.613018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2222 22:53:47.713454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2223 22:53:47.713912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2225 22:53:47.817096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2226 22:53:47.817661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2228 22:53:47.916871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2229 22:53:47.917355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2231 22:53:48.017017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2232 22:53:48.017501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2234 22:53:48.114789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2235 22:53:48.115272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2237 22:53:48.215361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2238 22:53:48.215914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2240 22:53:48.316233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2241 22:53:48.316685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2243 22:53:48.418831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2244 22:53:48.419348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2246 22:53:48.517569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2247 22:53:48.518076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2249 22:53:48.617258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2250 22:53:48.617758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2252 22:53:48.716692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2253 22:53:48.717194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2255 22:53:48.812536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2256 22:53:48.813116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2258 22:53:48.916278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2259 22:53:48.916775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2261 22:53:49.019581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2262 22:53:49.020060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2264 22:53:49.121879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2265 22:53:49.122377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2267 22:53:49.222076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2268 22:53:49.222613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2270 22:53:49.319181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2271 22:53:49.319655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2273 22:53:49.413480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2275 22:53:49.416436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2276 22:53:49.511684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2277 22:53:49.512158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2279 22:53:49.610935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2280 22:53:49.611418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2282 22:53:49.707664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2283 22:53:49.708142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2285 22:53:49.804619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2286 22:53:49.805195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2288 22:53:49.901210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2289 22:53:49.901688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2291 22:53:50.003792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2292 22:53:50.004263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2294 22:53:50.102786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2295 22:53:50.103260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2297 22:53:50.202203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2298 22:53:50.202745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2300 22:53:50.303662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2301 22:53:50.304138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2303 22:53:50.404657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2304 22:53:50.405159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2306 22:53:50.508044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2307 22:53:50.508527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2309 22:53:50.609268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2310 22:53:50.609783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2312 22:53:50.711311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2313 22:53:50.711801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2315 22:53:50.810985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2316 22:53:50.811546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2318 22:53:50.910603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2319 22:53:50.911091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2321 22:53:51.011560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2322 22:53:51.012049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2324 22:53:51.110169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2325 22:53:51.110656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2327 22:53:51.209486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2328 22:53:51.210042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2330 22:53:51.310908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2331 22:53:51.311393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2333 22:53:51.411816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2334 22:53:51.412302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2336 22:53:51.509822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2337 22:53:51.510311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2339 22:53:51.611533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2340 22:53:51.612022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2342 22:53:51.712189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2343 22:53:51.712668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2345 22:53:51.812675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2346 22:53:51.813265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2348 22:53:51.911794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2349 22:53:51.912275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2351 22:53:52.010728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2352 22:53:52.011205 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2354 22:53:52.111196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2355 22:53:52.111691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2357 22:53:52.212080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2358 22:53:52.212632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2360 22:53:52.314660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2361 22:53:52.315151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2363 22:53:52.416540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2364 22:53:52.417065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2366 22:53:52.514837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2367 22:53:52.515121 + set +x
2368 22:53:52.515554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2370 22:53:52.519126 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1219960_1.6.2.4.5>
2371 22:53:52.519611 Received signal: <ENDRUN> 1_kselftest-dt 1219960_1.6.2.4.5
2372 22:53:52.519863 Ending use of test pattern.
2373 22:53:52.520085 Ending test lava.1_kselftest-dt (1219960_1.6.2.4.5), duration 94.86
2375 22:53:52.525448 <LAVA_TEST_RUNNER EXIT>
2376 22:53:52.525930 ok: lava_test_shell seems to have completed
2377 22:53:52.531727 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2378 22:53:52.532809 end: 3.1 lava-test-shell (duration 00:01:36) [common]
2379 22:53:52.532970 end: 3 lava-test-retry (duration 00:01:36) [common]
2380 22:53:52.533132 start: 4 finalize (timeout 00:05:48) [common]
2381 22:53:52.533294 start: 4.1 power-off (timeout 00:00:30) [common]
2382 22:53:52.533503 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2383 22:53:52.901672 Returned 0 in 0 seconds
2384 22:53:53.002751 end: 4.1 power-off (duration 00:00:00) [common]
2386 22:53:53.003657 start: 4.2 read-feedback (timeout 00:05:48) [common]
2387 22:53:53.004285 Listened to connection for namespace 'common' for up to 1s
2388 22:53:53.004832 Listened to connection for namespace 'common' for up to 1s
2389 22:53:54.005157 Finalising connection for namespace 'common'
2390 22:53:54.005582 Disconnecting from shell: Finalise
2391 22:53:54.005861 / #
2392 22:53:54.106416 end: 4.2 read-feedback (duration 00:00:01) [common]
2393 22:53:54.106792 end: 4 finalize (duration 00:00:02) [common]
2394 22:53:54.107140 Cleaning after the job
2395 22:53:54.107459 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219960/tftp-deploy-y24xrdmw/ramdisk
2396 22:53:54.111170 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219960/tftp-deploy-y24xrdmw/kernel
2397 22:53:54.114207 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219960/tftp-deploy-y24xrdmw/dtb
2398 22:53:54.114673 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219960/tftp-deploy-y24xrdmw/nfsrootfs
2399 22:53:54.166734 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219960/tftp-deploy-y24xrdmw/modules
2400 22:53:54.170307 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1219960
2401 22:53:54.824487 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1219960
2402 22:53:54.824908 Job finished correctly