Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 22:01:40.024073 lava-dispatcher, installed at version: 2023.08
2 22:01:40.024384 start: 0 validate
3 22:01:40.024565 Start time: 2024-11-08 22:01:40.024554+00:00 (UTC)
4 22:01:40.024806 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 22:01:40.764455 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 22:01:40.878725 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 22:01:41.010778 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 22:01:41.124962 Validating that http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 22:01:41.243926 validate duration: 1.22
11 22:01:41.244785 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 22:01:41.245142 start: 1.1 download-retry (timeout 00:10:00) [common]
13 22:01:41.245455 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 22:01:41.245921 Not decompressing ramdisk as can be used compressed.
15 22:01:41.246221 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 22:01:41.246464 saving as /var/lib/lava/dispatcher/tmp/1219856/tftp-deploy-c_q0q541/ramdisk/initrd.cpio.gz
17 22:01:41.246711 total size: 4775763 (4 MB)
18 22:01:41.473412 progress 0 % (0 MB)
19 22:01:41.811066 progress 5 % (0 MB)
20 22:01:41.922770 progress 10 % (0 MB)
21 22:01:42.171442 progress 15 % (0 MB)
22 22:01:42.177018 progress 20 % (0 MB)
23 22:01:42.181675 progress 25 % (1 MB)
24 22:01:42.185460 progress 30 % (1 MB)
25 22:01:42.282436 progress 35 % (1 MB)
26 22:01:42.492598 progress 40 % (1 MB)
27 22:01:42.498773 progress 45 % (2 MB)
28 22:01:42.508968 progress 50 % (2 MB)
29 22:01:42.608622 progress 55 % (2 MB)
30 22:01:42.709446 progress 60 % (2 MB)
31 22:01:42.736150 progress 65 % (2 MB)
32 22:01:42.841446 progress 70 % (3 MB)
33 22:01:42.937300 progress 75 % (3 MB)
34 22:01:42.965375 progress 80 % (3 MB)
35 22:01:43.063768 progress 85 % (3 MB)
36 22:01:43.161726 progress 90 % (4 MB)
37 22:01:43.189677 progress 95 % (4 MB)
38 22:01:43.282629 progress 100 % (4 MB)
39 22:01:43.283418 4 MB downloaded in 2.04 s (2.24 MB/s)
40 22:01:43.283910 end: 1.1.1 http-download (duration 00:00:02) [common]
42 22:01:43.284776 end: 1.1 download-retry (duration 00:00:02) [common]
43 22:01:43.285030 start: 1.2 download-retry (timeout 00:09:58) [common]
44 22:01:43.285264 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 22:01:43.285595 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 22:01:43.285780 saving as /var/lib/lava/dispatcher/tmp/1219856/tftp-deploy-c_q0q541/kernel/zImage
47 22:01:43.285954 total size: 11444736 (10 MB)
48 22:01:43.286129 No compression specified
49 22:01:43.401730 progress 0 % (0 MB)
50 22:01:43.738289 progress 5 % (0 MB)
51 22:01:43.965700 progress 10 % (1 MB)
52 22:01:44.196585 progress 15 % (1 MB)
53 22:01:44.424231 progress 20 % (2 MB)
54 22:01:44.650177 progress 25 % (2 MB)
55 22:01:44.871482 progress 30 % (3 MB)
56 22:01:45.095979 progress 35 % (3 MB)
57 22:01:45.317420 progress 40 % (4 MB)
58 22:01:45.541586 progress 45 % (4 MB)
59 22:01:45.762128 progress 50 % (5 MB)
60 22:01:45.984649 progress 55 % (6 MB)
61 22:01:46.119164 progress 60 % (6 MB)
62 22:01:46.340237 progress 65 % (7 MB)
63 22:01:46.561557 progress 70 % (7 MB)
64 22:01:46.780171 progress 75 % (8 MB)
65 22:01:47.002262 progress 80 % (8 MB)
66 22:01:47.221709 progress 85 % (9 MB)
67 22:01:47.372939 progress 90 % (9 MB)
68 22:01:47.575978 progress 95 % (10 MB)
69 22:01:47.796477 progress 100 % (10 MB)
70 22:01:47.796917 10 MB downloaded in 4.51 s (2.42 MB/s)
71 22:01:47.797252 end: 1.2.1 http-download (duration 00:00:05) [common]
73 22:01:47.797819 end: 1.2 download-retry (duration 00:00:05) [common]
74 22:01:47.798028 start: 1.3 download-retry (timeout 00:09:53) [common]
75 22:01:47.798231 start: 1.3.1 http-download (timeout 00:09:53) [common]
76 22:01:47.798530 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 22:01:47.798692 saving as /var/lib/lava/dispatcher/tmp/1219856/tftp-deploy-c_q0q541/dtb/am335x-boneblack.dtb
78 22:01:47.798844 total size: 70568 (0 MB)
79 22:01:47.798995 No compression specified
80 22:01:47.914568 progress 46 % (0 MB)
81 22:01:47.917379 progress 92 % (0 MB)
82 22:01:47.918367 progress 100 % (0 MB)
83 22:01:47.918752 0 MB downloaded in 0.12 s (0.56 MB/s)
84 22:01:47.919170 end: 1.3.1 http-download (duration 00:00:00) [common]
86 22:01:47.919972 end: 1.3 download-retry (duration 00:00:00) [common]
87 22:01:47.920259 start: 1.4 download-retry (timeout 00:09:53) [common]
88 22:01:47.920551 start: 1.4.1 http-download (timeout 00:09:53) [common]
89 22:01:47.920922 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 22:01:47.921157 saving as /var/lib/lava/dispatcher/tmp/1219856/tftp-deploy-c_q0q541/nfsrootfs/full.rootfs.tar
91 22:01:47.921374 total size: 117747780 (112 MB)
92 22:01:47.921605 Using unxz to decompress xz
93 22:01:48.043578 progress 0 % (0 MB)
94 22:01:50.604996 progress 5 % (5 MB)
95 22:01:52.750907 progress 10 % (11 MB)
96 22:01:54.882093 progress 15 % (16 MB)
97 22:01:56.914056 progress 20 % (22 MB)
98 22:01:58.816101 progress 25 % (28 MB)
99 22:02:00.376776 progress 30 % (33 MB)
100 22:02:01.618825 progress 35 % (39 MB)
101 22:02:02.636697 progress 40 % (44 MB)
102 22:02:03.514852 progress 45 % (50 MB)
103 22:02:04.230810 progress 50 % (56 MB)
104 22:02:04.887822 progress 55 % (61 MB)
105 22:02:05.464249 progress 60 % (67 MB)
106 22:02:06.073473 progress 65 % (73 MB)
107 22:02:06.728940 progress 70 % (78 MB)
108 22:02:07.361542 progress 75 % (84 MB)
109 22:02:07.963261 progress 80 % (89 MB)
110 22:02:08.537782 progress 85 % (95 MB)
111 22:02:09.097921 progress 90 % (101 MB)
112 22:02:09.634620 progress 95 % (106 MB)
113 22:02:10.165374 progress 100 % (112 MB)
114 22:02:10.168883 112 MB downloaded in 22.25 s (5.05 MB/s)
115 22:02:10.169195 end: 1.4.1 http-download (duration 00:00:22) [common]
117 22:02:10.169751 end: 1.4 download-retry (duration 00:00:22) [common]
118 22:02:10.169948 start: 1.5 download-retry (timeout 00:09:31) [common]
119 22:02:10.170142 start: 1.5.1 http-download (timeout 00:09:31) [common]
120 22:02:10.170433 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 22:02:10.170588 saving as /var/lib/lava/dispatcher/tmp/1219856/tftp-deploy-c_q0q541/modules/modules.tar
122 22:02:10.170735 total size: 6609968 (6 MB)
123 22:02:10.170883 Using unxz to decompress xz
124 22:02:10.286567 progress 0 % (0 MB)
125 22:02:10.518255 progress 5 % (0 MB)
126 22:02:10.735949 progress 10 % (0 MB)
127 22:02:10.761837 progress 15 % (0 MB)
128 22:02:10.786622 progress 20 % (1 MB)
129 22:02:10.811878 progress 25 % (1 MB)
130 22:02:10.867776 progress 30 % (1 MB)
131 22:02:11.074702 progress 35 % (2 MB)
132 22:02:11.101340 progress 40 % (2 MB)
133 22:02:11.125326 progress 45 % (2 MB)
134 22:02:11.202328 progress 50 % (3 MB)
135 22:02:11.305032 progress 55 % (3 MB)
136 22:02:11.407385 progress 60 % (3 MB)
137 22:02:11.445150 progress 65 % (4 MB)
138 22:02:11.543655 progress 70 % (4 MB)
139 22:02:11.642401 progress 75 % (4 MB)
140 22:02:11.741487 progress 80 % (5 MB)
141 22:02:11.774985 progress 85 % (5 MB)
142 22:02:11.872511 progress 90 % (5 MB)
143 22:02:11.970956 progress 95 % (6 MB)
144 22:02:12.005438 progress 100 % (6 MB)
145 22:02:12.009428 6 MB downloaded in 1.84 s (3.43 MB/s)
146 22:02:12.009751 end: 1.5.1 http-download (duration 00:00:02) [common]
148 22:02:12.010313 end: 1.5 download-retry (duration 00:00:02) [common]
149 22:02:12.010515 start: 1.6 prepare-tftp-overlay (timeout 00:09:29) [common]
150 22:02:12.010717 start: 1.6.1 extract-nfsrootfs (timeout 00:09:29) [common]
151 22:02:17.558964 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1219856/extract-nfsrootfs-0s1jed1e
152 22:02:17.559267 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 22:02:17.559418 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
154 22:02:17.559716 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv
155 22:02:17.559907 makedir: /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin
156 22:02:17.560052 makedir: /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/tests
157 22:02:17.560204 makedir: /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/results
158 22:02:17.560367 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-add-keys
159 22:02:17.560594 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-add-sources
160 22:02:17.561051 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-background-process-start
161 22:02:17.561239 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-background-process-stop
162 22:02:17.561445 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-common-functions
163 22:02:17.561630 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-echo-ipv4
164 22:02:17.561806 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-install-packages
165 22:02:17.561988 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-installed-packages
166 22:02:17.562166 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-os-build
167 22:02:17.562339 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-probe-channel
168 22:02:17.562510 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-probe-ip
169 22:02:17.562685 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-target-ip
170 22:02:17.562869 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-target-mac
171 22:02:17.563055 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-target-storage
172 22:02:17.563251 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-test-case
173 22:02:17.563443 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-test-event
174 22:02:17.563615 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-test-feedback
175 22:02:17.563786 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-test-raise
176 22:02:17.563956 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-test-reference
177 22:02:17.564128 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-test-runner
178 22:02:17.564302 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-test-set
179 22:02:17.564473 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-test-shell
180 22:02:17.564647 Updating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-add-keys (debian)
181 22:02:17.564908 Updating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-add-sources (debian)
182 22:02:17.565105 Updating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-install-packages (debian)
183 22:02:17.565300 Updating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-installed-packages (debian)
184 22:02:17.565492 Updating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/bin/lava-os-build (debian)
185 22:02:17.565663 Creating /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/environment
186 22:02:17.565796 LAVA metadata
187 22:02:17.565897 - LAVA_JOB_ID=1219856
188 22:02:17.565994 - LAVA_DISPATCHER_IP=192.168.11.5
189 22:02:17.566140 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
190 22:02:17.566470 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 22:02:17.566595 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
192 22:02:17.566690 skipped lava-vland-overlay
193 22:02:17.566803 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 22:02:17.566923 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
195 22:02:17.567021 skipped lava-multinode-overlay
196 22:02:17.567136 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 22:02:17.567254 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
198 22:02:17.567356 Loading test definitions
199 22:02:17.567481 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
200 22:02:17.567582 Using /lava-1219856 at stage 0
201 22:02:17.567989 uuid=1219856_1.6.2.4.1 testdef=None
202 22:02:17.568116 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 22:02:17.568237 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
204 22:02:17.568863 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 22:02:17.569196 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
207 22:02:17.569998 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 22:02:17.570346 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
210 22:02:17.571096 runner path: /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/0/tests/0_timesync-off test_uuid 1219856_1.6.2.4.1
211 22:02:17.571296 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 22:02:17.571633 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
214 22:02:17.571735 Using /lava-1219856 at stage 0
215 22:02:17.571874 Fetching tests from https://github.com/kernelci/test-definitions.git
216 22:02:17.571979 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/0/tests/1_kselftest-dt'
217 22:02:22.495872 Running '/usr/bin/git checkout kernelci.org
218 22:02:22.716050 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 22:02:22.717059 uuid=1219856_1.6.2.4.5 testdef=None
220 22:02:22.717313 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 22:02:22.717879 start: 1.6.2.4.6 test-overlay (timeout 00:09:19) [common]
223 22:02:22.719772 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 22:02:22.720371 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:19) [common]
226 22:02:22.723022 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 22:02:22.723648 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:19) [common]
229 22:02:22.725628 runner path: /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/0/tests/1_kselftest-dt test_uuid 1219856_1.6.2.4.5
230 22:02:22.725747 BOARD='beaglebone-black'
231 22:02:22.725841 BRANCH='mainline'
232 22:02:22.725932 SKIPFILE='/dev/null'
233 22:02:22.726022 SKIP_INSTALL='True'
234 22:02:22.726110 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 22:02:22.726201 TST_CASENAME=''
236 22:02:22.726289 TST_CMDFILES='dt'
237 22:02:22.726485 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 22:02:22.726798 Creating lava-test-runner.conf files
240 22:02:22.726891 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1219856/lava-overlay-elkvwmmv/lava-1219856/0 for stage 0
241 22:02:22.727018 - 0_timesync-off
242 22:02:22.727114 - 1_kselftest-dt
243 22:02:22.727250 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 22:02:22.727371 start: 1.6.2.5 compress-overlay (timeout 00:09:19) [common]
245 22:02:31.195152 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 22:02:31.195361 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
247 22:02:31.195507 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 22:02:31.195655 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
249 22:02:31.195798 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
250 22:02:31.319903 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 22:02:31.320197 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
252 22:02:31.320361 extracting modules file /var/lib/lava/dispatcher/tmp/1219856/tftp-deploy-c_q0q541/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1219856/extract-nfsrootfs-0s1jed1e
253 22:02:31.626166 extracting modules file /var/lib/lava/dispatcher/tmp/1219856/tftp-deploy-c_q0q541/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1219856/extract-overlay-ramdisk-dtcve2q1/ramdisk
254 22:02:31.933184 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 22:02:31.933402 start: 1.6.5 apply-overlay-tftp (timeout 00:09:09) [common]
256 22:02:31.933536 [common] Applying overlay to NFS
257 22:02:31.933642 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1219856/compress-overlay-4cg4pjj6/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1219856/extract-nfsrootfs-0s1jed1e
258 22:02:33.117123 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 22:02:33.117336 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
260 22:02:33.117463 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
261 22:02:33.117592 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 22:02:33.117711 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 22:02:33.117831 start: 1.6.7 configure-preseed-file (timeout 00:09:08) [common]
264 22:02:33.117945 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 22:02:33.118062 start: 1.6.8 compress-ramdisk (timeout 00:09:08) [common]
266 22:02:33.118162 Building ramdisk /var/lib/lava/dispatcher/tmp/1219856/extract-overlay-ramdisk-dtcve2q1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1219856/extract-overlay-ramdisk-dtcve2q1/ramdisk
267 22:02:33.426054 >> 74902 blocks
268 22:02:35.357819 Adding RAMdisk u-boot header.
269 22:02:35.358051 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1219856/extract-overlay-ramdisk-dtcve2q1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1219856/extract-overlay-ramdisk-dtcve2q1/ramdisk.cpio.gz.uboot
270 22:02:35.497680 output: Image Name:
271 22:02:35.497937 output: Created: Fri Nov 8 22:02:35 2024
272 22:02:35.498081 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 22:02:35.498220 output: Data Size: 14794854 Bytes = 14448.10 KiB = 14.11 MiB
274 22:02:35.498354 output: Load Address: 00000000
275 22:02:35.498485 output: Entry Point: 00000000
276 22:02:35.498614 output:
277 22:02:35.498832 rename /var/lib/lava/dispatcher/tmp/1219856/extract-overlay-ramdisk-dtcve2q1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1219856/tftp-deploy-c_q0q541/ramdisk/ramdisk.cpio.gz.uboot
278 22:02:35.499059 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 22:02:35.499244 end: 1.6 prepare-tftp-overlay (duration 00:00:23) [common]
280 22:02:35.499423 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:06) [common]
281 22:02:35.499563 No LXC device requested
282 22:02:35.499727 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 22:02:35.499898 start: 1.8 deploy-device-env (timeout 00:09:06) [common]
284 22:02:35.500062 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 22:02:35.500196 Checking files for TFTP limit of 4294967296 bytes.
286 22:02:35.501035 end: 1 tftp-deploy (duration 00:00:54) [common]
287 22:02:35.501222 start: 2 uboot-action (timeout 00:05:00) [common]
288 22:02:35.501402 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 22:02:35.501572 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 22:02:35.501746 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 22:02:35.502001 substitutions:
292 22:02:35.502139 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 22:02:35.502274 - {DTB_ADDR}: 0x88000000
294 22:02:35.502406 - {DTB}: 1219856/tftp-deploy-c_q0q541/dtb/am335x-boneblack.dtb
295 22:02:35.502538 - {INITRD}: 1219856/tftp-deploy-c_q0q541/ramdisk/ramdisk.cpio.gz.uboot
296 22:02:35.502668 - {KERNEL_ADDR}: 0x82000000
297 22:02:35.502796 - {KERNEL}: 1219856/tftp-deploy-c_q0q541/kernel/zImage
298 22:02:35.502924 - {LAVA_MAC}: None
299 22:02:35.503059 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1219856/extract-nfsrootfs-0s1jed1e
300 22:02:35.503188 - {NFS_SERVER_IP}: 192.168.11.5
301 22:02:35.503313 - {PRESEED_CONFIG}: None
302 22:02:35.503438 - {PRESEED_LOCAL}: None
303 22:02:35.503563 - {RAMDISK_ADDR}: 0x83000000
304 22:02:35.503687 - {RAMDISK}: 1219856/tftp-deploy-c_q0q541/ramdisk/ramdisk.cpio.gz.uboot
305 22:02:35.503811 - {ROOT_PART}: None
306 22:02:35.503935 - {ROOT}: None
307 22:02:35.504058 - {SERVER_IP}: 192.168.11.5
308 22:02:35.504181 - {TEE_ADDR}: 0x83000000
309 22:02:35.504303 - {TEE}: None
310 22:02:35.504426 Parsed boot commands:
311 22:02:35.504547 - setenv autoload no
312 22:02:35.504670 - setenv initrd_high 0xffffffff
313 22:02:35.504809 - setenv fdt_high 0xffffffff
314 22:02:35.504931 - dhcp
315 22:02:35.505054 - setenv serverip 192.168.11.5
316 22:02:35.505176 - tftp 0x82000000 1219856/tftp-deploy-c_q0q541/kernel/zImage
317 22:02:35.505300 - tftp 0x83000000 1219856/tftp-deploy-c_q0q541/ramdisk/ramdisk.cpio.gz.uboot
318 22:02:35.505424 - setenv initrd_size ${filesize}
319 22:02:35.505547 - tftp 0x88000000 1219856/tftp-deploy-c_q0q541/dtb/am335x-boneblack.dtb
320 22:02:35.505669 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219856/extract-nfsrootfs-0s1jed1e,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 22:02:35.505797 - bootz 0x82000000 0x83000000 0x88000000
322 22:02:35.505957 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 22:02:35.506407 start: 2.3 connect-device (timeout 00:05:00) [common]
325 22:02:35.506538 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 22:02:35.867428 Setting prompt string to ['lava-test: # ']
327 22:02:35.867869 end: 2.3 connect-device (duration 00:00:00) [common]
328 22:02:35.868044 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 22:02:35.868272 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 22:02:35.868528 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 22:02:35.868927 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 22:02:36.231175 Returned 0 in 0 seconds
333 22:02:36.332052 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 22:02:36.332982 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 22:02:36.333304 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 22:02:36.333586 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 22:02:36.333837 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 22:02:36.334599 Trying 127.0.0.1...
340 22:02:36.334837 Connected to 127.0.0.1.
341 22:02:36.335058 Escape character is '^]'.
342 22:02:41.260286
343 22:02:41.263952 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 22:02:41.320605 Trying to boot from MMC2
345 22:02:41.368895 Loading Environment from EXT4... Card did not respond to voltage select!
346 22:02:41.436245
347 22:02:41.436568
348 22:02:41.441713 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 22:02:41.441993
350 22:02:41.446735 CPU : AM335X-GP rev 2.1
351 22:02:41.500704 I2C: ready
352 22:02:41.500999 DRAM: 512 MiB
353 22:02:41.554964 No match for driver 'omap_hsmmc'
354 22:02:41.560567 No match for driver 'omap_hsmmc'
355 22:02:41.560872 Some drivers were not found
356 22:02:41.566812 Reset Source: Power-on reset has occurred.
357 22:02:41.567087 RTC 32KCLK Source: External.
358 22:02:41.574300 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 22:02:41.587631 Loading Environment from EXT4... Card did not respond to voltage select!
360 22:02:41.652084 Board: BeagleBone Black
361 22:02:41.656119 <ethaddr> not set. Validating first E-fuse MAC
362 22:02:41.712596 BeagleBone Black:
363 22:02:41.712939 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 22:02:41.718195 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 22:02:41.724193 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 22:02:41.724457 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 22:02:41.729117 Net: eth0: MII MODE
368 22:02:41.738522 cpsw, usb_ether
369 22:02:41.738796 Press SPACE to abort autoboot in 2 seconds
370 22:02:41.789584 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 22:02:41.789958 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 22:02:41.790270 Setting prompt string to ['=> ']
373 22:02:41.790532 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 22:02:41.793711 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 22:02:41.794023 Sending with 10 millisecond of delay
377 22:02:42.928562 => setenv autoload no
378 22:02:42.939095 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 22:02:42.941485 setenv autoload no
380 22:02:42.941956 Sending with 10 millisecond of delay
382 22:02:44.739010 => setenv initrd_high 0xffffffff
383 22:02:44.749492 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 22:02:44.749962 setenv initrd_high 0xffffffff
385 22:02:44.750412 Sending with 10 millisecond of delay
387 22:02:46.366531 => setenv fdt_high 0xffffffff
388 22:02:46.377034 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 22:02:46.377499 setenv fdt_high 0xffffffff
390 22:02:46.377949 Sending with 10 millisecond of delay
392 22:02:46.669415 => dhcp
393 22:02:46.679831 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 22:02:46.680291 dhcp
395 22:02:46.680539 link up on port 0, speed 100, full duplex
396 22:02:46.680820 BOOTP broadcast 1
397 22:02:46.688201 DHCP client bound to address 192.168.11.3 (3 ms)
398 22:02:46.688639 Sending with 10 millisecond of delay
400 22:02:48.425378 => setenv serverip 192.168.11.5
401 22:02:48.435891 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 22:02:48.436362 setenv serverip 192.168.11.5
403 22:02:48.436833 Sending with 10 millisecond of delay
405 22:02:51.979789 => tftp 0x82000000 1219856/tftp-deploy-c_q0q541/kernel/zImage
406 22:02:51.990279 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 22:02:51.990737 tftp 0x82000000 1219856/tftp-deploy-c_q0q541/kernel/zImage
408 22:02:51.990970 link up on port 0, speed 100, full duplex
409 22:02:51.991185 Using cpsw device
410 22:02:51.994451 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
411 22:02:52.000098 Filename '1219856/tftp-deploy-c_q0q541/kernel/zImage'.
412 22:02:52.099510 Load address: 0x82000000
413 22:02:52.188096 Loading: *#################################################################
414 22:02:52.364455 #################################################################
415 22:02:52.538707 #################################################################
416 22:02:52.735952 #################################################################
417 22:02:52.910409 #################################################################
418 22:02:53.086256 #################################################################
419 22:02:53.261855 #################################################################
420 22:02:53.437738 #################################################################
421 22:02:53.627821 #################################################################
422 22:02:53.803951 #################################################################
423 22:02:53.979571 #################################################################
424 22:02:54.161276 #################################################################
425 22:02:54.161557 5.1 MiB/s
426 22:02:54.161783 done
427 22:02:54.161995 Bytes transferred = 11444736 (aea200 hex)
428 22:02:54.164922 Sending with 10 millisecond of delay
430 22:02:58.671529 => tftp 0x83000000 1219856/tftp-deploy-c_q0q541/ramdisk/ramdisk.cpio.gz.uboot
431 22:02:58.681995 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
432 22:02:58.682457 tftp 0x83000000 1219856/tftp-deploy-c_q0q541/ramdisk/ramdisk.cpio.gz.uboot
433 22:02:58.682690 link up on port 0, speed 100, full duplex
434 22:02:58.682916 Using cpsw device
435 22:02:58.686257 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
436 22:02:58.700081 Filename '1219856/tftp-deploy-c_q0q541/ramdisk/ramdisk.cpio.gz.uboot'.
437 22:02:58.700308 Load address: 0x83000000
438 22:02:58.897788 Loading: *#################################################################
439 22:02:59.075766 #################################################################
440 22:02:59.249922 #################################################################
441 22:02:59.426874 #################################################################
442 22:02:59.601718 #################################################################
443 22:02:59.776748 #################################################################
444 22:02:59.953514 #################################################################
445 22:03:00.138048 #################################################################
446 22:03:00.311976 #################################################################
447 22:03:00.483222 #################################################################
448 22:03:00.659204 #################################################################
449 22:03:00.834453 #################################################################
450 22:03:01.019504 #################################################################
451 22:03:01.194715 #################################################################
452 22:03:01.369226 #################################################################
453 22:03:01.451606 #################################
454 22:03:01.451865 5.1 MiB/s
455 22:03:01.452141 done
456 22:03:01.455327 Bytes transferred = 14794918 (e1c0a6 hex)
457 22:03:01.455876 Sending with 10 millisecond of delay
459 22:03:03.313207 => setenv initrd_size ${filesize}
460 22:03:03.323698 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
461 22:03:03.324204 setenv initrd_size ${filesize}
462 22:03:03.324668 Sending with 10 millisecond of delay
464 22:03:07.530375 => tftp 0x88000000 1219856/tftp-deploy-c_q0q541/dtb/am335x-boneblack.dtb
465 22:03:07.540871 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
466 22:03:07.541328 tftp 0x88000000 1219856/tftp-deploy-c_q0q541/dtb/am335x-boneblack.dtb
467 22:03:07.541558 link up on port 0, speed 100, full duplex
468 22:03:07.541771 Using cpsw device
469 22:03:07.545234 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
470 22:03:07.570194 Filename '1219856/tftp-deploy-c_q0q541/dtb/am335x-boneblack.dtb'.
471 22:03:07.570466 Load address: 0x88000000
472 22:03:07.570685 Loading: *#####
473 22:03:07.570894 4.8 MiB/s
474 22:03:07.576994 done
475 22:03:07.577260 Bytes transferred = 70568 (113a8 hex)
476 22:03:07.577696 Sending with 10 millisecond of delay
478 22:03:20.876615 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219856/extract-nfsrootfs-0s1jed1e,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
479 22:03:20.887126 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
480 22:03:20.887581 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219856/extract-nfsrootfs-0s1jed1e,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 22:03:20.888040 Sending with 10 millisecond of delay
483 22:03:23.226903 => bootz 0x82000000 0x83000000 0x88000000
484 22:03:23.237397 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
485 22:03:23.237721 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
486 22:03:23.238254 bootz 0x82000000 0x83000000 0x88000000
487 22:03:23.238492 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 22:03:23.239085 Image Name:
489 22:03:23.239360 Created: 2024-11-08 22:02:35 UTC
490 22:03:23.244557 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 22:03:23.250193 Data Size: 14794854 Bytes = 14.1 MiB
492 22:03:23.250471 Load Address: 00000000
493 22:03:23.257403 Entry Point: 00000000
494 22:03:23.394749 Verifying Checksum ... OK
495 22:03:23.395029 ## Flattened Device Tree blob at 88000000
496 22:03:23.401193 Booting using the fdt blob at 0x88000000
497 22:03:23.406274 Using Device Tree in place at 88000000, end 880143a7
498 22:03:23.413780
499 22:03:23.414124 Starting kernel ...
500 22:03:23.414352
501 22:03:23.414912 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 22:03:23.415219 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
503 22:03:23.415474 Setting prompt string to ['Linux version [0-9]']
504 22:03:23.415721 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
505 22:03:23.415968 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
506 22:03:24.253947 [ 0.000000] Booting Linux on physical CPU 0x0
507 22:03:24.260010 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
508 22:03:24.260324 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 22:03:24.260580 Setting prompt string to []
510 22:03:24.260863 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 22:03:24.261123 Using line separator: #'\n'#
512 22:03:24.261345 No login prompt set.
513 22:03:24.261572 Parsing kernel messages
514 22:03:24.261781 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 22:03:24.262172 [login-action] Waiting for messages, (timeout 00:04:11)
516 22:03:24.276777 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j369961-arm-gcc-12-multi-v7-defconfig-prhhs) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Fri Nov 8 21:35:42 UTC 2024
517 22:03:24.282530 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
518 22:03:24.288161 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
519 22:03:24.299653 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
520 22:03:24.305393 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
521 22:03:24.311139 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
522 22:03:24.311417 [ 0.000000] Memory policy: Data cache writeback
523 22:03:24.317755 [ 0.000000] efi: UEFI not found.
524 22:03:24.323190 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
525 22:03:24.329017 [ 0.000000] Zone ranges:
526 22:03:24.334653 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
527 22:03:24.340386 [ 0.000000] Normal empty
528 22:03:24.340661 [ 0.000000] HighMem empty
529 22:03:24.343265 [ 0.000000] Movable zone start for each node
530 22:03:24.349021 [ 0.000000] Early memory node ranges
531 22:03:24.354779 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
532 22:03:24.362876 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
533 22:03:24.388289 [ 0.000000] CPU: All CPU(s) started in SVC mode.
534 22:03:24.393958 [ 0.000000] AM335X ES2.1 (sgx neon)
535 22:03:24.405653 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
536 22:03:24.423278 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1219856/extract-nfsrootfs-0s1jed1e,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
537 22:03:24.434783 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
538 22:03:24.440521 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
539 22:03:24.446271 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
540 22:03:24.456455 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
541 22:03:24.485523 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
542 22:03:24.491521 <6>[ 0.000000] trace event string verifier disabled
543 22:03:24.491800 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
544 22:03:24.497271 <6>[ 0.000000] rcu: RCU event tracing is enabled.
545 22:03:24.508643 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
546 22:03:24.514399 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
547 22:03:24.521696 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
548 22:03:24.536659 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
549 22:03:24.553787 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
550 22:03:24.560587 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
551 22:03:24.652895 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
552 22:03:24.664393 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
553 22:03:24.671141 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
554 22:03:24.684205 <6>[ 0.019139] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
555 22:03:24.691524 <6>[ 0.033949] Console: colour dummy device 80x30
556 22:03:24.697595 Matched prompt #6: WARNING:
557 22:03:24.697886 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
558 22:03:24.703144 <3>[ 0.038848] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
559 22:03:24.708777 <3>[ 0.045916] This ensures that you still see kernel messages. Please
560 22:03:24.712068 <3>[ 0.052641] update your kernel commandline.
561 22:03:24.752785 <6>[ 0.057254] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
562 22:03:24.758514 <6>[ 0.096142] CPU: Testing write buffer coherency: ok
563 22:03:24.764400 <6>[ 0.101507] CPU0: Spectre v2: using BPIALL workaround
564 22:03:24.764679 <6>[ 0.106973] pid_max: default: 32768 minimum: 301
565 22:03:24.775879 <6>[ 0.112168] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
566 22:03:24.782765 <6>[ 0.119989] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 22:03:24.789725 <6>[ 0.129343] CPU0: thread -1, cpu 0, socket -1, mpidr 0
568 22:03:24.855394 <6>[ 0.189524] Setting up static identity map for 0x80300000 - 0x803000ac
569 22:03:24.861144 <6>[ 0.199116] rcu: Hierarchical SRCU implementation.
570 22:03:24.864790 <6>[ 0.204398] rcu: Max phase no-delay instances is 1000.
571 22:03:24.873404 <6>[ 0.215426] EFI services will not be available.
572 22:03:24.879134 <6>[ 0.220773] smp: Bringing up secondary CPUs ...
573 22:03:24.885052 <6>[ 0.225743] smp: Brought up 1 node, 1 CPU
574 22:03:24.890673 <6>[ 0.230234] SMP: Total of 1 processors activated (996.14 BogoMIPS).
575 22:03:24.896615 <6>[ 0.236954] CPU: All CPU(s) started in SVC mode.
576 22:03:24.916886 <6>[ 0.242158] Memory: 405992K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49056K reserved, 65536K cma-reserved, 0K highmem)
577 22:03:24.917144 <6>[ 0.258441] devtmpfs: initialized
578 22:03:24.939071 <6>[ 0.275411] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
579 22:03:24.950556 <6>[ 0.284014] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
580 22:03:24.956532 <6>[ 0.294452] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
581 22:03:24.967129 <6>[ 0.306716] pinctrl core: initialized pinctrl subsystem
582 22:03:24.976493 <6>[ 0.317340] DMI not present or invalid.
583 22:03:24.984823 <6>[ 0.323198] NET: Registered PF_NETLINK/PF_ROUTE protocol family
584 22:03:24.994272 <6>[ 0.332186] DMA: preallocated 256 KiB pool for atomic coherent allocations
585 22:03:25.009360 <6>[ 0.343644] thermal_sys: Registered thermal governor 'step_wise'
586 22:03:25.009593 <6>[ 0.343815] cpuidle: using governor menu
587 22:03:25.037101 <6>[ 0.379500] No ATAGs?
588 22:03:25.043119 <6>[ 0.382143] hw-breakpoint: debug architecture 0x4 unsupported.
589 22:03:25.053269 <6>[ 0.393984] Serial: AMBA PL011 UART driver
590 22:03:25.082470 <6>[ 0.424841] iommu: Default domain type: Translated
591 22:03:25.091506 <6>[ 0.430187] iommu: DMA domain TLB invalidation policy: strict mode
592 22:03:25.119000 <5>[ 0.460711] SCSI subsystem initialized
593 22:03:25.124698 <6>[ 0.465592] usbcore: registered new interface driver usbfs
594 22:03:25.130595 <6>[ 0.471614] usbcore: registered new interface driver hub
595 22:03:25.137378 <6>[ 0.477395] usbcore: registered new device driver usb
596 22:03:25.143113 <6>[ 0.483889] pps_core: LinuxPPS API ver. 1 registered
597 22:03:25.154626 <6>[ 0.489276] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
598 22:03:25.161790 <6>[ 0.498999] PTP clock support registered
599 22:03:25.162073 <6>[ 0.503450] EDAC MC: Ver: 3.0.0
600 22:03:25.212567 <6>[ 0.552426] scmi_core: SCMI protocol bus registered
601 22:03:25.228128 <6>[ 0.569814] vgaarb: loaded
602 22:03:25.234192 <6>[ 0.573581] clocksource: Switched to clocksource dmtimer
603 22:03:25.267768 <6>[ 0.609851] NET: Registered PF_INET protocol family
604 22:03:25.280358 <6>[ 0.615561] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
605 22:03:25.286106 <6>[ 0.624404] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
606 22:03:25.297627 <6>[ 0.633294] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
607 22:03:25.303369 <6>[ 0.641574] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
608 22:03:25.314982 <6>[ 0.649862] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
609 22:03:25.320751 <6>[ 0.657580] TCP: Hash tables configured (established 4096 bind 4096)
610 22:03:25.326485 <6>[ 0.664496] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
611 22:03:25.332479 <6>[ 0.671507] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
612 22:03:25.340051 <6>[ 0.679120] NET: Registered PF_UNIX/PF_LOCAL protocol family
613 22:03:25.425997 <6>[ 0.762691] RPC: Registered named UNIX socket transport module.
614 22:03:25.426336 <6>[ 0.769121] RPC: Registered udp transport module.
615 22:03:25.431728 <6>[ 0.774246] RPC: Registered tcp transport module.
616 22:03:25.437492 <6>[ 0.779347] RPC: Registered tcp-with-tls transport module.
617 22:03:25.450550 <6>[ 0.785275] RPC: Registered tcp NFSv4.1 backchannel transport module.
618 22:03:25.450837 <6>[ 0.792183] PCI: CLS 0 bytes, default 64
619 22:03:25.457658 <5>[ 0.797983] Initialise system trusted keyrings
620 22:03:25.478693 <6>[ 0.818010] Trying to unpack rootfs image as initramfs...
621 22:03:25.551623 <6>[ 0.887742] workingset: timestamp_bits=30 max_order=17 bucket_order=0
622 22:03:25.556428 <6>[ 0.895313] squashfs: version 4.0 (2009/01/31) Phillip Lougher
623 22:03:25.601741 <5>[ 0.944120] NFS: Registering the id_resolver key type
624 22:03:25.607612 <5>[ 0.949731] Key type id_resolver registered
625 22:03:25.613358 <5>[ 0.954409] Key type id_legacy registered
626 22:03:25.619102 <6>[ 0.958852] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
627 22:03:25.628686 <6>[ 0.966052] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
628 22:03:25.701863 <5>[ 1.044383] Key type asymmetric registered
629 22:03:25.707851 <5>[ 1.048908] Asymmetric key parser 'x509' registered
630 22:03:25.719352 <6>[ 1.054436] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
631 22:03:25.719637 <6>[ 1.062323] io scheduler mq-deadline registered
632 22:03:25.725230 <6>[ 1.067311] io scheduler kyber registered
633 22:03:25.730775 <6>[ 1.071769] io scheduler bfq registered
634 22:03:25.856944 <6>[ 1.195625] ledtrig-cpu: registered to indicate activity on CPUs
635 22:03:26.129741 <6>[ 1.468295] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
636 22:03:26.166171 <6>[ 1.508381] msm_serial: driver initialized
637 22:03:26.172273 <6>[ 1.513183] SuperH (H)SCI(F) driver initialized
638 22:03:26.178157 <6>[ 1.518512] STMicroelectronics ASC driver initialized
639 22:03:26.183313 <6>[ 1.524193] STM32 USART driver initialized
640 22:03:26.295581 <6>[ 1.637443] brd: module loaded
641 22:03:26.333116 <6>[ 1.674750] loop: module loaded
642 22:03:26.369815 <6>[ 1.711224] CAN device driver interface
643 22:03:26.376411 <6>[ 1.716567] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
644 22:03:26.382137 <6>[ 1.723526] e1000e: Intel(R) PRO/1000 Network Driver
645 22:03:26.388000 <6>[ 1.728996] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
646 22:03:26.393600 <6>[ 1.735431] igb: Intel(R) Gigabit Ethernet Network Driver
647 22:03:26.401939 <6>[ 1.741253] igb: Copyright (c) 2007-2014 Intel Corporation.
648 22:03:26.413893 <6>[ 1.750627] pegasus: Pegasus/Pegasus II USB Ethernet driver
649 22:03:26.419713 <6>[ 1.756786] usbcore: registered new interface driver pegasus
650 22:03:26.422390 <6>[ 1.762914] usbcore: registered new interface driver asix
651 22:03:26.428141 <6>[ 1.768794] usbcore: registered new interface driver ax88179_178a
652 22:03:26.434023 <6>[ 1.775386] usbcore: registered new interface driver cdc_ether
653 22:03:26.439771 <6>[ 1.781685] usbcore: registered new interface driver smsc75xx
654 22:03:26.451269 <6>[ 1.787914] usbcore: registered new interface driver smsc95xx
655 22:03:26.457021 <6>[ 1.794153] usbcore: registered new interface driver net1080
656 22:03:26.462766 <6>[ 1.800273] usbcore: registered new interface driver cdc_subset
657 22:03:26.468517 <6>[ 1.806695] usbcore: registered new interface driver zaurus
658 22:03:26.473423 <6>[ 1.812740] usbcore: registered new interface driver cdc_ncm
659 22:03:26.483676 <6>[ 1.822375] usbcore: registered new interface driver usb-storage
660 22:03:26.493220 <6>[ 1.833804] i2c_dev: i2c /dev entries driver
661 22:03:26.518803 <5>[ 1.853255] cpuidle: enable-method property 'ti,am3352' found operations
662 22:03:26.524666 <6>[ 1.862807] sdhci: Secure Digital Host Controller Interface driver
663 22:03:26.532156 <6>[ 1.869560] sdhci: Copyright(c) Pierre Ossman
664 22:03:26.539431 <6>[ 1.876105] Synopsys Designware Multimedia Card Interface Driver
665 22:03:26.544978 <6>[ 1.884204] sdhci-pltfm: SDHCI platform and OF driver helper
666 22:03:26.559233 <6>[ 1.894352] usbcore: registered new interface driver usbhid
667 22:03:26.559359 <6>[ 1.900379] usbhid: USB HID core driver
668 22:03:26.572387 <6>[ 1.912196] NET: Registered PF_INET6 protocol family
669 22:03:27.023560 <6>[ 2.366032] Segment Routing with IPv6
670 22:03:27.029387 <6>[ 2.370178] In-situ OAM (IOAM) with IPv6
671 22:03:27.036128 <6>[ 2.374685] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
672 22:03:27.041996 <6>[ 2.381936] NET: Registered PF_PACKET protocol family
673 22:03:27.047742 <6>[ 2.387506] can: controller area network core
674 22:03:27.053513 <6>[ 2.392326] NET: Registered PF_CAN protocol family
675 22:03:27.053791 <6>[ 2.397563] can: raw protocol
676 22:03:27.059239 <6>[ 2.400891] can: broadcast manager protocol
677 22:03:27.065742 <6>[ 2.405490] can: netlink gateway - max_hops=1
678 22:03:27.071990 <5>[ 2.410966] Key type dns_resolver registered
679 22:03:27.078117 <6>[ 2.416052] ThumbEE CPU extension supported.
680 22:03:27.078395 <5>[ 2.420740] Registering SWP/SWPB emulation handler
681 22:03:27.087920 <3>[ 2.426439] omap_voltage_late_init: Voltage driver support not added
682 22:03:27.274176 <5>[ 2.614247] Loading compiled-in X.509 certificates
683 22:03:27.402980 <6>[ 2.732575] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
684 22:03:27.410231 <6>[ 2.749242] pinctrl-single 44e10800.pinmux: 142 pins, size 568
685 22:03:27.436469 <3>[ 2.772847] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
686 22:03:27.646169 <3>[ 2.982639] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
687 22:03:27.843220 <6>[ 3.184001] OMAP GPIO hardware version 0.1
688 22:03:27.863802 <6>[ 3.202574] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
689 22:03:27.966690 <4>[ 3.305164] at24 2-0054: supply vcc not found, using dummy regulator
690 22:03:28.005172 <4>[ 3.343733] at24 2-0055: supply vcc not found, using dummy regulator
691 22:03:28.042529 <4>[ 3.380999] at24 2-0056: supply vcc not found, using dummy regulator
692 22:03:28.081953 <4>[ 3.420425] at24 2-0057: supply vcc not found, using dummy regulator
693 22:03:28.119654 <6>[ 3.458939] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
694 22:03:28.194180 <3>[ 3.529396] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
695 22:03:28.218522 <6>[ 3.550147] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
696 22:03:28.240427 <4>[ 3.576216] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
697 22:03:28.248195 <4>[ 3.585425] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
698 22:03:28.385783 <6>[ 3.724501] omap_rng 48310000.rng: Random Number Generator ver. 20
699 22:03:28.409126 <5>[ 3.750566] random: crng init done
700 22:03:28.456907 <6>[ 3.793965] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
701 22:03:28.510602 <6>[ 3.851463] Freeing initrd memory: 14452K
702 22:03:28.559720 <6>[ 3.896037] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
703 22:03:28.565598 <6>[ 3.906389] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
704 22:03:28.577349 <6>[ 3.913737] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
705 22:03:28.583090 <6>[ 3.921169] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
706 22:03:28.594754 <6>[ 3.929312] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
707 22:03:28.601970 <6>[ 3.940946] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
708 22:03:28.615209 <5>[ 3.949968] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
709 22:03:28.642854 <3>[ 3.979581] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
710 22:03:28.648529 <6>[ 3.988181] edma 49000000.dma: TI EDMA DMA engine driver
711 22:03:28.719217 <3>[ 4.055308] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
712 22:03:28.733768 <6>[ 4.069607] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
713 22:03:28.746641 <3>[ 4.086637] l3-aon-clkctrl:0000:0: failed to disable
714 22:03:28.794589 <6>[ 4.131311] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
715 22:03:28.800353 <6>[ 4.140819] printk: legacy console [ttyS0] enabled
716 22:03:28.805975 <6>[ 4.140819] printk: legacy console [ttyS0] enabled
717 22:03:28.811713 <6>[ 4.151175] printk: legacy bootconsole [omap8250] disabled
718 22:03:28.817506 <6>[ 4.151175] printk: legacy bootconsole [omap8250] disabled
719 22:03:28.858587 <4>[ 4.194295] tps65217-pmic: Failed to locate of_node [id: -1]
720 22:03:28.862135 <4>[ 4.201705] tps65217-bl: Failed to locate of_node [id: -1]
721 22:03:28.878604 <6>[ 4.221379] tps65217 0-0024: TPS65217 ID 0xe version 1.2
722 22:03:28.896964 <6>[ 4.228276] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
723 22:03:28.908721 <6>[ 4.241959] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
724 22:03:28.914411 <6>[ 4.253869] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
725 22:03:28.936622 <6>[ 4.273774] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
726 22:03:28.942506 <6>[ 4.282832] sdhci-omap 48060000.mmc: Got CD GPIO
727 22:03:28.950527 <4>[ 4.287991] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
728 22:03:28.964975 <4>[ 4.301325] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
729 22:03:28.971344 <4>[ 4.310012] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
730 22:03:28.981135 <4>[ 4.318709] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
731 22:03:29.079900 <6>[ 4.418027] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
732 22:03:29.127468 <6>[ 4.464247] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
733 22:03:29.133958 <6>[ 4.472753] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 22:03:29.143033 <6>[ 4.481572] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
735 22:03:29.233205 <6>[ 4.565197] mmc1: new high speed MMC card at address 0001
736 22:03:29.233488 <6>[ 4.573765] mmcblk1: mmc1:0001 M62704 3.56 GiB
737 22:03:29.244256 <6>[ 4.585137] mmcblk1: p1
738 22:03:29.250955 <6>[ 4.589861] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
739 22:03:29.261573 <6>[ 4.596103] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
740 22:03:29.276400 <6>[ 4.616634] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
741 22:03:29.286120 <6>[ 4.624964] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
742 22:03:32.457742 <6>[ 7.794621] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
743 22:03:32.531074 <5>[ 7.833664] Sending DHCP requests ., OK
744 22:03:32.542428 <6>[ 7.878092] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.3
745 22:03:32.542704 <6>[ 7.886311] IP-Config: Complete:
746 22:03:32.553800 <6>[ 7.889849] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.3, mask=255.255.255.0, gw=192.168.11.1
747 22:03:32.559427 <6>[ 7.900472] host=192.168.11.3, domain=usen.ad.jp, nis-domain=(none)
748 22:03:32.571803 <6>[ 7.907555] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
749 22:03:32.572077 <6>[ 7.907589] nameserver0=192.168.11.1
750 22:03:32.577952 <6>[ 7.919864] clk: Disabling unused clocks
751 22:03:32.584378 <6>[ 7.924612] PM: genpd: Disabling unused power domains
752 22:03:32.603999 <6>[ 7.943298] Freeing unused kernel image (initmem) memory: 2048K
753 22:03:32.611367 <6>[ 7.952998] Run /init as init process
754 22:03:32.633892 Loading, please wait...
755 22:03:32.708782 Starting systemd-udevd version 252.22-1~deb12u1
756 22:03:35.761264 <4>[ 11.096802] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
757 22:03:35.879168 <4>[ 11.214761] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
758 22:03:36.025390 <6>[ 11.368379] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
759 22:03:36.036151 <6>[ 11.374191] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
760 22:03:36.272926 <6>[ 11.614441] hub 1-0:1.0: USB hub found
761 22:03:36.295871 <6>[ 11.637369] hub 1-0:1.0: 1 port detected
762 22:03:36.396751 <6>[ 11.737975] tda998x 0-0070: found TDA19988
763 22:03:39.516611 Begin: Loading essential drivers ... done.
764 22:03:39.522160 Begin: Running /scripts/init-premount ... done.
765 22:03:39.527776 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
766 22:03:39.537981 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
767 22:03:39.544864 Device /sys/class/net/eth0 found
768 22:03:39.545130 done.
769 22:03:39.603876 Begin: Waiting up to 180 secs for any network device to become available ... done.
770 22:03:39.676629 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
771 22:03:39.676959 IP-Config: eth0 guessed broadcast address 192.168.11.255
772 22:03:39.682236 IP-Config: eth0 complete (dhcp from 192.168.11.1):
773 22:03:39.693513 address: 192.168.11.3 broadcast: 192.168.11.255 netmask: 255.255.255.0
774 22:03:39.698981 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
775 22:03:39.704605 domain : usen.ad.jp
776 22:03:39.709564 rootserver: 192.168.11.1 rootpath:
777 22:03:39.709796 filename :
778 22:03:39.779520 done.
779 22:03:39.791177 Begin: Running /scripts/nfs-bottom ... done.
780 22:03:39.839681 Begin: Running /scripts/init-bottom ... done.
781 22:03:41.337625 <30>[ 16.676500] systemd[1]: System time before build time, advancing clock.
782 22:03:41.517891 <30>[ 16.830697] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
783 22:03:41.527070 <30>[ 16.867777] systemd[1]: Detected architecture arm.
784 22:03:41.540903
785 22:03:41.541187 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
786 22:03:41.541465
787 22:03:41.563830 <30>[ 16.903248] systemd[1]: Hostname set to <debian-bookworm-armhf>.
788 22:03:43.792439 <30>[ 19.130925] systemd[1]: Queued start job for default target graphical.target.
789 22:03:43.809751 <30>[ 19.146043] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
790 22:03:43.817221 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
791 22:03:43.840022 <30>[ 19.176641] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
792 22:03:43.848495 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
793 22:03:43.870426 <30>[ 19.207013] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
794 22:03:43.878695 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
795 22:03:43.898784 <30>[ 19.235575] systemd[1]: Created slice user.slice - User and Session Slice.
796 22:03:43.905445 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
797 22:03:43.933908 <30>[ 19.265006] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
798 22:03:43.939957 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
799 22:03:43.957798 <30>[ 19.294728] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
800 22:03:43.966826 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
801 22:03:43.998778 <30>[ 19.324732] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
802 22:03:44.005526 <30>[ 19.345256] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
803 22:03:44.013889 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
804 22:03:44.037048 <30>[ 19.374110] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
805 22:03:44.045211 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
806 22:03:44.067795 <30>[ 19.404549] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
807 22:03:44.076260 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
808 22:03:44.097647 <30>[ 19.434671] systemd[1]: Reached target paths.target - Path Units.
809 22:03:44.102749 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
810 22:03:44.127153 <30>[ 19.464242] systemd[1]: Reached target remote-fs.target - Remote File Systems.
811 22:03:44.134572 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
812 22:03:44.157025 <30>[ 19.494116] systemd[1]: Reached target slices.target - Slice Units.
813 22:03:44.162446 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
814 22:03:44.187271 <30>[ 19.524336] systemd[1]: Reached target swap.target - Swaps.
815 22:03:44.191316 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
816 22:03:44.217542 <30>[ 19.554334] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
817 22:03:44.226440 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
818 22:03:44.248539 <30>[ 19.585290] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
819 22:03:44.256816 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
820 22:03:44.337208 <30>[ 19.669185] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
821 22:03:44.350021 <30>[ 19.686898] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
822 22:03:44.358437 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
823 22:03:44.379033 <30>[ 19.715432] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
824 22:03:44.386439 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
825 22:03:44.410639 <30>[ 19.747349] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
826 22:03:44.418812 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
827 22:03:44.441653 <30>[ 19.778349] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
828 22:03:44.447392 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
829 22:03:44.479777 <30>[ 19.815360] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
830 22:03:44.487341 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
831 22:03:44.514458 <30>[ 19.845365] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
832 22:03:44.533058 <30>[ 19.863957] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
833 22:03:44.577483 <30>[ 19.915205] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
834 22:03:44.604201 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
835 22:03:44.659451 <30>[ 19.997095] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
836 22:03:44.679993 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
837 22:03:44.740427 <30>[ 20.077005] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
838 22:03:44.765474 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
839 22:03:44.817995 <30>[ 20.155168] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
840 22:03:44.839086 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
841 22:03:44.897839 <30>[ 20.235399] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
842 22:03:44.920790 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
843 22:03:44.979792 <30>[ 20.317864] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
844 22:03:44.999729 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
845 22:03:45.059731 <30>[ 20.396539] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
846 22:03:45.090236 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
847 22:03:45.138981 <30>[ 20.476970] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
848 22:03:45.159482 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
849 22:03:45.219513 <30>[ 20.557315] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
850 22:03:45.246100 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
851 22:03:45.276045 <28>[ 20.606080] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
852 22:03:45.284578 <28>[ 20.621607] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
853 22:03:45.326600 <30>[ 20.665029] systemd[1]: Starting systemd-journald.service - Journal Service...
854 22:03:45.354722 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
855 22:03:45.428771 <30>[ 20.766435] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
856 22:03:45.442131 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
857 22:03:45.509046 <30>[ 20.846867] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
858 22:03:45.558129 Starting [0;1;39msystemd-network-g… units from Kernel command line...
859 22:03:45.611433 <30>[ 20.947850] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
860 22:03:45.667093 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
861 22:03:45.732128 <30>[ 21.069265] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
862 22:03:45.779712 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
863 22:03:45.860489 <30>[ 21.198449] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
864 22:03:45.909531 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
865 22:03:45.916845 <30>[ 21.255720] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
866 22:03:45.952322 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
867 22:03:45.979746 <30>[ 21.316519] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
868 22:03:46.007946 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
869 22:03:46.187572 <30>[ 21.526150] systemd[1]: modprobe@configfs.service: Deactivated successfully.
870 22:03:46.218167 <30>[ 21.555623] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
871 22:03:46.247105 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
872 22:03:46.268006 <30>[ 21.605169] systemd[1]: Started systemd-journald.service - Journal Service.
873 22:03:46.274810 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
874 22:03:46.307188 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
875 22:03:46.331686 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
876 22:03:46.371687 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
877 22:03:46.409058 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
878 22:03:46.432754 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
879 22:03:46.467093 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
880 22:03:46.497189 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
881 22:03:46.520474 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
882 22:03:46.556833 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
883 22:03:46.618932 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
884 22:03:46.691160 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
885 22:03:46.779179 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
886 22:03:46.879589 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
887 22:03:46.971378 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
888 22:03:46.978662 <46>[ 22.316579] systemd-journald[162]: Received client request to flush runtime journal.
889 22:03:47.097468 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
890 22:03:47.180837 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
891 22:03:48.011861 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
892 22:03:48.077275 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
893 22:03:48.133842 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
894 22:03:48.831464 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
895 22:03:48.984866 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
896 22:03:49.017822 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
897 22:03:49.036925 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
898 22:03:49.107881 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
899 22:03:49.149515 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
900 22:03:50.070384 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
901 22:03:50.137825 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
902 22:03:50.441758 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
903 22:03:50.573287 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
904 22:03:50.656425 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
905 22:03:52.577022 [[0m[0;31m* [0m] (1 of 5) Job systemd-timesyncd.service/start running (8s / 1min 36s)
906 22:03:52.630014 M[K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
907 22:03:52.667156 [K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
908 22:03:53.372756 <5>[ 28.711092] cfg80211: Loading compiled-in X.509 certificates for regulatory database
909 22:03:53.605234 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
910 22:03:54.761777 <5>[ 30.102151] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
911 22:03:54.859647 <5>[ 30.198457] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
912 22:03:54.880668 <4>[ 30.218754] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
913 22:03:54.886456 <6>[ 30.227897] cfg80211: failed to load regulatory.db
914 22:03:55.339199 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
915 22:03:55.429262 <46>[ 30.758571] systemd-journald[162]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
916 22:03:55.622496 <46>[ 30.953956] systemd-journald[162]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
917 22:03:55.835033 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
918 22:04:04.453031 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
919 22:04:04.476856 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
920 22:04:04.501008 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
921 22:04:04.534227 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
922 22:04:04.590146 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
923 22:04:04.635522 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
924 22:04:04.690767 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
925 22:04:04.781504 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
926 22:04:04.839081 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
927 22:04:04.862362 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
928 22:04:04.903890 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
929 22:04:04.930859 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
930 22:04:04.970764 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
931 22:04:05.018450 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
932 22:04:05.049817 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
933 22:04:05.077937 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
934 22:04:05.109038 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
935 22:04:05.136518 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
936 22:04:05.161897 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
937 22:04:05.186890 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
938 22:04:05.217185 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
939 22:04:05.237033 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
940 22:04:05.263889 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
941 22:04:05.336891 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
942 22:04:05.385771 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
943 22:04:05.485146 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
944 22:04:05.547893 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
945 22:04:05.617797 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
946 22:04:05.647578 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
947 22:04:05.679163 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
948 22:04:05.882913 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
949 22:04:05.926620 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
950 22:04:05.997693 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
951 22:04:06.015745 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
952 22:04:06.059692 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
953 22:04:06.286592 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
954 22:04:06.651110 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
955 22:04:06.709393 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
956 22:04:06.741660 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
957 22:04:06.836584 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
958 22:04:07.008821 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
959 22:04:07.143700
960 22:04:07.144054 Debian GNU/Linux 12��K��armhf login: root (automatic login)
961 22:04:07.146943
962 22:04:07.484081 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Fri Nov 8 21:35:42 UTC 2024 armv7l
963 22:04:07.484372
964 22:04:07.489709 The programs included with the Debian GNU/Linux system are free software;
965 22:04:07.495222 the exact distribution terms for each program are described in the
966 22:04:07.500857 individual files in /usr/share/doc/*/copyright.
967 22:04:07.500992
968 22:04:07.508652 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
969 22:04:07.508774 permitted by applicable law.
970 22:04:12.116147 Unable to match end of the kernel message
972 22:04:12.116985 Setting prompt string to ['/ #']
973 22:04:12.117286 end: 2.4.4.1 login-action (duration 00:00:48) [common]
975 22:04:12.117967 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
976 22:04:12.118259 start: 2.4.5 expect-shell-connection (timeout 00:03:23) [common]
977 22:04:12.118499 Setting prompt string to ['/ #']
978 22:04:12.118711 Forcing a shell prompt, looking for ['/ #']
980 22:04:12.169237 / #
981 22:04:12.169620 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
982 22:04:12.169906 Waiting using forced prompt support (timeout 00:02:30)
983 22:04:12.176384
984 22:04:12.184841 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
985 22:04:12.185179 start: 2.4.6 export-device-env (timeout 00:03:23) [common]
986 22:04:12.185464 Sending with 10 millisecond of delay
988 22:04:17.234072 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1219856/extract-nfsrootfs-0s1jed1e'
989 22:04:17.244692 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1219856/extract-nfsrootfs-0s1jed1e'
990 22:04:17.245235 Sending with 10 millisecond of delay
992 22:04:19.403411 / # export NFS_SERVER_IP='192.168.11.5'
993 22:04:19.414019 export NFS_SERVER_IP='192.168.11.5'
994 22:04:19.414609 end: 2.4.6 export-device-env (duration 00:00:07) [common]
995 22:04:19.414923 end: 2.4 uboot-commands (duration 00:01:44) [common]
996 22:04:19.415235 end: 2 uboot-action (duration 00:01:44) [common]
997 22:04:19.415544 start: 3 lava-test-retry (timeout 00:07:22) [common]
998 22:04:19.415853 start: 3.1 lava-test-shell (timeout 00:07:22) [common]
999 22:04:19.416101 Using namespace: common
1001 22:04:19.516813 / # #
1002 22:04:19.517186 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1003 22:04:19.521628 #
1004 22:04:19.527657 Using /lava-1219856
1006 22:04:19.628444 / # export SHELL=/bin/bash
1007 22:04:19.633401 export SHELL=/bin/bash
1009 22:04:19.740182 / # . /lava-1219856/environment
1010 22:04:19.744931 . /lava-1219856/environment
1012 22:04:19.857917 / # /lava-1219856/bin/lava-test-runner /lava-1219856/0
1013 22:04:19.858298 Test shell timeout: 10s (minimum of the action and connection timeout)
1014 22:04:19.862645 /lava-1219856/bin/lava-test-runner /lava-1219856/0
1015 22:04:20.289567 + export TESTRUN_ID=0_timesync-off
1016 22:04:20.297568 + TESTRUN_ID=0_timesync-off
1017 22:04:20.297850 + cd /lava-1219856/0/tests/0_timesync-off
1018 22:04:20.298081 ++ cat uuid
1019 22:04:20.313652 + UUID=1219856_1.6.2.4.1
1020 22:04:20.313933 + set +x
1021 22:04:20.319261 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1219856_1.6.2.4.1>
1022 22:04:20.319776 Received signal: <STARTRUN> 0_timesync-off 1219856_1.6.2.4.1
1023 22:04:20.320023 Starting test lava.0_timesync-off (1219856_1.6.2.4.1)
1024 22:04:20.320303 Skipping test definition patterns.
1025 22:04:20.322444 + systemctl stop systemd-timesyncd
1026 22:04:20.650209 + set +x
1027 22:04:20.650788 Received signal: <ENDRUN> 0_timesync-off 1219856_1.6.2.4.1
1028 22:04:20.651064 Ending use of test pattern.
1029 22:04:20.651289 Ending test lava.0_timesync-off (1219856_1.6.2.4.1), duration 0.33
1031 22:04:20.653389 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1219856_1.6.2.4.1>
1032 22:04:20.846383 + export TESTRUN_ID=1_kselftest-dt
1033 22:04:20.854423 + TESTRUN_ID=1_kselftest-dt
1034 22:04:20.854703 + cd /lava-1219856/0/tests/1_kselftest-dt
1035 22:04:20.854932 ++ cat uuid
1036 22:04:20.870631 + UUID=1219856_1.6.2.4.5
1037 22:04:20.870912 + set +x
1038 22:04:20.876240 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1219856_1.6.2.4.5>
1039 22:04:20.876519 + cd ./automated/linux/kselftest/
1040 22:04:20.876969 Received signal: <STARTRUN> 1_kselftest-dt 1219856_1.6.2.4.5
1041 22:04:20.877200 Starting test lava.1_kselftest-dt (1219856_1.6.2.4.5)
1042 22:04:20.877464 Skipping test definition patterns.
1043 22:04:20.904670 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1044 22:04:21.026321 INFO: install_deps skipped
1045 22:04:21.631094 --2024-11-08 22:04:21-- http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1046 22:04:21.650737 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1047 22:04:21.764904 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1048 22:04:21.881354 HTTP request sent, awaiting response... 200 OK
1049 22:04:21.881632 Length: 4106376 (3.9M) [application/octet-stream]
1050 22:04:21.886958 Saving to: 'kselftest_armhf.tar.gz'
1051 22:04:21.887234
1052 22:04:24.046372 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 1%[ ] 49.92K 224KB/s kselftest_armhf.tar 5%[> ] 218.67K 491KB/s kselftest_armhf.tar 10%[=> ] 429.60K 640KB/s kselftest_armhf.tar 27%[====> ] 1.09M 1.22MB/s kselftest_armhf.tar 39%[======> ] 1.54M 1.41MB/s kselftest_armhf.tar 48%[========> ] 1.89M 1.46MB/s kselftest_armhf.tar 59%[==========> ] 2.35M 1.57MB/s kselftest_armhf.tar 72%[=============> ] 2.83M 1.67MB/s kselftest_armhf.tar 84%[===============> ] 3.29M 1.73MB/s kselftest_armhf.tar 97%[==================> ] 3.83M 1.80MB/s kselftest_armhf.tar 100%[===================>] 3.92M 1.81MB/s in 2.2s
1053 22:04:24.046757
1054 22:04:24.774036 2024-11-08 22:04:24 (1.81 MB/s) - 'kselftest_armhf.tar.gz' saved [4106376/4106376]
1055 22:04:24.774386
1056 22:04:47.260629 skiplist:
1057 22:04:47.261062 ========================================
1058 22:04:47.266233 ========================================
1059 22:04:47.400123 dt:test_unprobed_devices.sh
1060 22:04:47.435498 ============== Tests to run ===============
1061 22:04:47.442958 dt:test_unprobed_devices.sh
1062 22:04:47.446875 ===========End Tests to run ===============
1063 22:04:47.456945 shardfile-dt pass
1064 22:04:47.685306 <12>[ 83.029285] kselftest: Running tests in dt
1065 22:04:47.714898 TAP version 13
1066 22:04:47.736999 1..1
1067 22:04:47.790211 # timeout set to 45
1068 22:04:47.790488 # selftests: dt: test_unprobed_devices.sh
1069 22:04:48.602700 # TAP version 13
1070 22:05:13.705966 # 1..257
1071 22:05:13.878439 # ok 1 / # SKIP
1072 22:05:13.900049 # ok 2 /clk_mcasp0
1073 22:05:13.974398 # ok 3 /clk_mcasp0_fixed # SKIP
1074 22:05:14.044705 # ok 4 /cpus/cpu@0 # SKIP
1075 22:05:14.118070 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1076 22:05:14.142649 # ok 6 /fixedregulator0
1077 22:05:14.163115 # ok 7 /leds
1078 22:05:14.179420 # ok 8 /ocp
1079 22:05:14.204220 # ok 9 /ocp/interconnect@44c00000
1080 22:05:14.232142 # ok 10 /ocp/interconnect@44c00000/segment@0
1081 22:05:14.255083 # ok 11 /ocp/interconnect@44c00000/segment@100000
1082 22:05:14.274920 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1083 22:05:14.350219 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1084 22:05:14.368546 # ok 14 /ocp/interconnect@44c00000/segment@200000
1085 22:05:14.395575 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1086 22:05:14.501058 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1087 22:05:14.572739 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1088 22:05:14.650731 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1089 22:05:14.722793 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1090 22:05:14.792280 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1091 22:05:14.865083 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1092 22:05:14.942150 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1093 22:05:15.010401 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1094 22:05:15.083647 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1095 22:05:15.156772 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1096 22:05:15.228689 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1097 22:05:15.302260 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1098 22:05:15.379281 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1099 22:05:15.452042 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1100 22:05:15.521985 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1101 22:05:15.600530 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1102 22:05:15.666282 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1103 22:05:15.739442 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1104 22:05:15.811245 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1105 22:05:15.885133 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1106 22:05:15.956609 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1107 22:05:16.029759 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1108 22:05:16.105554 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1109 22:05:16.175544 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1110 22:05:16.249375 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1111 22:05:16.322372 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1112 22:05:16.402875 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1113 22:05:16.473645 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1114 22:05:16.543357 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1115 22:05:16.616213 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1116 22:05:16.688721 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1117 22:05:16.761615 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1118 22:05:16.837476 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1119 22:05:16.907600 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1120 22:05:16.980228 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1121 22:05:17.052806 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1122 22:05:17.129958 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1123 22:05:17.202945 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1124 22:05:17.272010 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1125 22:05:17.349829 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1126 22:05:17.418178 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1127 22:05:17.490926 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1128 22:05:17.563945 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1129 22:05:17.634822 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1130 22:05:17.708697 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1131 22:05:17.780852 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1132 22:05:17.856644 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1133 22:05:17.929789 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1134 22:05:18.003162 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1135 22:05:18.074946 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1136 22:05:18.148305 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1137 22:05:18.222550 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1138 22:05:18.298233 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1139 22:05:18.370751 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1140 22:05:18.444526 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1141 22:05:18.517626 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1142 22:05:18.590464 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1143 22:05:18.664768 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1144 22:05:18.735672 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1145 22:05:18.809224 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1146 22:05:18.882095 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1147 22:05:18.955828 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1148 22:05:19.028552 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1149 22:05:19.101010 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1150 22:05:19.177733 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1151 22:05:19.247010 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1152 22:05:19.319494 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1153 22:05:19.390878 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1154 22:05:19.468141 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1155 22:05:19.541493 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1156 22:05:19.612485 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1157 22:05:19.684471 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1158 22:05:19.756643 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1159 22:05:19.831073 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1160 22:05:19.904446 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1161 22:05:19.974702 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1162 22:05:20.054101 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1163 22:05:20.122886 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1164 22:05:20.196127 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1165 22:05:20.216821 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1166 22:05:20.240254 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1167 22:05:20.268763 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1168 22:05:20.291021 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1169 22:05:20.311995 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1170 22:05:20.336053 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1171 22:05:20.359377 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1172 22:05:20.386241 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1173 22:05:20.491099 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1174 22:05:20.514008 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1175 22:05:20.538070 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1176 22:05:20.563846 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1177 22:05:20.667190 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1178 22:05:20.742364 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1179 22:05:20.818241 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1180 22:05:20.887835 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1181 22:05:20.960317 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1182 22:05:21.033346 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1183 22:05:21.105781 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1184 22:05:21.182196 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1185 22:05:21.251503 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1186 22:05:21.324677 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1187 22:05:21.402064 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1188 22:05:21.474804 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1189 22:05:21.546602 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1190 22:05:21.618417 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1191 22:05:21.692566 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1192 22:05:21.767208 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1193 22:05:21.787788 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1194 22:05:21.859919 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1195 22:05:21.930475 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1196 22:05:22.008807 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1197 22:05:22.030016 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1198 22:05:22.098898 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1199 22:05:22.129202 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1200 22:05:22.195661 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1201 22:05:22.218102 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1202 22:05:22.242521 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1203 22:05:22.265182 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1204 22:05:22.289409 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1205 22:05:22.312229 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1206 22:05:22.336223 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1207 22:05:22.362155 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1208 22:05:22.436455 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1209 22:05:22.458919 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1210 22:05:22.486751 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1211 22:05:22.560566 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1212 22:05:22.632265 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1213 22:05:22.649340 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1214 22:05:22.751692 # not ok 144 /ocp/interconnect@47c00000
1215 22:05:22.824299 # not ok 145 /ocp/interconnect@47c00000/segment@0
1216 22:05:22.847148 # ok 146 /ocp/interconnect@48000000
1217 22:05:22.874076 # ok 147 /ocp/interconnect@48000000/segment@0
1218 22:05:22.898769 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1219 22:05:22.919719 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1220 22:05:22.945583 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1221 22:05:22.968814 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1222 22:05:22.989623 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1223 22:05:23.012526 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1224 22:05:23.035074 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1225 22:05:23.110113 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1226 22:05:23.186650 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1227 22:05:23.209667 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1228 22:05:23.229417 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1229 22:05:23.252428 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1230 22:05:23.276612 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1231 22:05:23.299114 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1232 22:05:23.327998 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1233 22:05:23.349641 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1234 22:05:23.373632 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1235 22:05:23.393592 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1236 22:05:23.420251 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1237 22:05:23.444676 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1238 22:05:23.470233 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1239 22:05:23.489042 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1240 22:05:23.513460 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1241 22:05:23.535984 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1242 22:05:23.561466 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1243 22:05:23.584243 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1244 22:05:23.609002 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1245 22:05:23.634027 # ok 175 /ocp/interconnect@48000000/segment@100000
1246 22:05:23.658997 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1247 22:05:23.680524 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1248 22:05:23.753268 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1249 22:05:23.832387 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1250 22:05:23.902411 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1251 22:05:23.980039 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1252 22:05:24.046135 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1253 22:05:24.120229 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1254 22:05:24.191391 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1255 22:05:24.270264 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1256 22:05:24.289963 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1257 22:05:24.309955 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1258 22:05:24.332114 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1259 22:05:24.356289 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1260 22:05:24.381958 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1261 22:05:24.403155 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1262 22:05:24.426733 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1263 22:05:24.456554 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1264 22:05:24.473274 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1265 22:05:24.497088 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1266 22:05:24.520860 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1267 22:05:24.545061 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1268 22:05:24.568203 # ok 198 /ocp/interconnect@48000000/segment@200000
1269 22:05:24.594394 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1270 22:05:24.668002 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1271 22:05:24.688228 # ok 201 /ocp/interconnect@48000000/segment@300000
1272 22:05:24.708548 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1273 22:05:24.732464 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1274 22:05:24.756531 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1275 22:05:24.778982 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1276 22:05:24.802775 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1277 22:05:24.826140 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1278 22:05:24.899665 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1279 22:05:24.922698 # ok 209 /ocp/interconnect@4a000000
1280 22:05:24.946446 # ok 210 /ocp/interconnect@4a000000/segment@0
1281 22:05:24.969626 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1282 22:05:24.991645 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1283 22:05:25.021110 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1284 22:05:25.039027 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1285 22:05:25.115623 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1286 22:05:25.217868 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1287 22:05:25.291496 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1288 22:05:25.396843 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1289 22:05:25.467920 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1290 22:05:25.539627 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1291 22:05:25.640696 # not ok 221 /ocp/interconnect@4b140000
1292 22:05:25.713918 # not ok 222 /ocp/interconnect@4b140000/segment@0
1293 22:05:25.786350 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1294 22:05:25.807631 # ok 224 /ocp/target-module@40300000
1295 22:05:25.835063 # ok 225 /ocp/target-module@40300000/sram@0
1296 22:05:25.909489 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1297 22:05:25.978533 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1298 22:05:26.002806 # ok 228 /ocp/target-module@47400000
1299 22:05:26.027298 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1300 22:05:26.048183 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1301 22:05:26.074278 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1302 22:05:26.090312 # ok 232 /ocp/target-module@47400000/usb@1400
1303 22:05:26.113582 # ok 233 /ocp/target-module@47400000/usb@1800
1304 22:05:26.137155 # ok 234 /ocp/target-module@47810000
1305 22:05:26.162188 # ok 235 /ocp/target-module@49000000
1306 22:05:26.182223 # ok 236 /ocp/target-module@49000000/dma@0
1307 22:05:26.206944 # ok 237 /ocp/target-module@49800000
1308 22:05:26.231677 # ok 238 /ocp/target-module@49800000/dma@0
1309 22:05:26.254035 # ok 239 /ocp/target-module@49900000
1310 22:05:26.276936 # ok 240 /ocp/target-module@49900000/dma@0
1311 22:05:26.297072 # ok 241 /ocp/target-module@49a00000
1312 22:05:26.318006 # ok 242 /ocp/target-module@49a00000/dma@0
1313 22:05:26.339862 # ok 243 /ocp/target-module@4c000000
1314 22:05:26.417269 # not ok 244 /ocp/target-module@4c000000/emif@0
1315 22:05:26.436921 # ok 245 /ocp/target-module@50000000
1316 22:05:26.463688 # ok 246 /ocp/target-module@53100000
1317 22:05:26.529100 # not ok 247 /ocp/target-module@53100000/sham@0
1318 22:05:26.551122 # ok 248 /ocp/target-module@53500000
1319 22:05:26.623153 # not ok 249 /ocp/target-module@53500000/aes@0
1320 22:05:26.644401 # ok 250 /ocp/target-module@56000000
1321 22:05:26.754347 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1322 22:05:26.823250 # ok 252 /opp-table # SKIP
1323 22:05:26.893593 # ok 253 /soc # SKIP
1324 22:05:26.909633 # ok 254 /sound
1325 22:05:26.933909 # ok 255 /target-module@4b000000
1326 22:05:26.962553 # ok 256 /target-module@4b000000/target-module@140000
1327 22:05:26.979061 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1328 22:05:26.987340 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1329 22:05:26.995653 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1330 22:05:29.173432 dt_test_unprobed_devices_sh_ skip
1331 22:05:29.179000 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1332 22:05:29.184623 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1333 22:05:29.184917 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1334 22:05:29.190122 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1335 22:05:29.195747 dt_test_unprobed_devices_sh_fixedregulator0 pass
1336 22:05:29.201401 dt_test_unprobed_devices_sh_leds pass
1337 22:05:29.201669 dt_test_unprobed_devices_sh_ocp pass
1338 22:05:29.206997 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1339 22:05:29.212622 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1340 22:05:29.218244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1341 22:05:29.229373 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1342 22:05:29.234996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1343 22:05:29.240758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1344 22:05:29.251904 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1345 22:05:29.257495 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1346 22:05:29.268824 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1347 22:05:29.279897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1348 22:05:29.291142 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1349 22:05:29.296777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1350 22:05:29.308018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1351 22:05:29.319138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1352 22:05:29.330387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1353 22:05:29.341638 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1354 22:05:29.347136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1355 22:05:29.358392 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1356 22:05:29.369519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1357 22:05:29.380772 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1358 22:05:29.391882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1359 22:05:29.397507 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1360 22:05:29.408779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1361 22:05:29.419794 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1362 22:05:29.431040 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1363 22:05:29.436655 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1364 22:05:29.447802 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1365 22:05:29.459116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1366 22:05:29.470294 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1367 22:05:29.481522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1368 22:05:29.487015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1369 22:05:29.498259 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1370 22:05:29.509393 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1371 22:05:29.520642 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1372 22:05:29.531890 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1373 22:05:29.543012 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1374 22:05:29.554267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1375 22:05:29.565393 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1376 22:05:29.576637 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1377 22:05:29.587764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1378 22:05:29.599012 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1379 22:05:29.610111 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1380 22:05:29.621385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1381 22:05:29.632510 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1382 22:05:29.643763 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1383 22:05:29.654887 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1384 22:05:29.666132 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1385 22:05:29.677261 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1386 22:05:29.688505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1387 22:05:29.699756 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1388 22:05:29.710886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1389 22:05:29.722133 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1390 22:05:29.733260 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1391 22:05:29.744504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1392 22:05:29.755756 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1393 22:05:29.766935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1394 22:05:29.772506 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1395 22:05:29.783753 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1396 22:05:29.794879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1397 22:05:29.806129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1398 22:05:29.817255 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1399 22:05:29.828503 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1400 22:05:29.839753 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1401 22:05:29.850873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1402 22:05:29.862127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1403 22:05:29.873253 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1404 22:05:29.884497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1405 22:05:29.895751 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1406 22:05:29.906876 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1407 22:05:29.918004 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1408 22:05:29.929251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1409 22:05:29.940374 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1410 22:05:29.951620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1411 22:05:29.962874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1412 22:05:29.968372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1413 22:05:29.979624 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1414 22:05:29.990751 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1415 22:05:30.001996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1416 22:05:30.013124 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1417 22:05:30.018745 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1418 22:05:30.035494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1419 22:05:30.046701 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1420 22:05:30.052323 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1421 22:05:30.069119 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1422 22:05:30.080369 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1423 22:05:30.091440 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1424 22:05:30.097063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1425 22:05:30.108187 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1426 22:05:30.119387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1427 22:05:30.125018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1428 22:05:30.136134 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1429 22:05:30.147380 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1430 22:05:30.153013 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1431 22:05:30.164129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1432 22:05:30.169762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1433 22:05:30.180886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1434 22:05:30.192127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1435 22:05:30.203252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1436 22:05:30.214502 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1437 22:05:30.225757 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1438 22:05:30.236881 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1439 22:05:30.248129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1440 22:05:30.259249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1441 22:05:30.270628 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1442 22:05:30.281688 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1443 22:05:30.292906 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1444 22:05:30.303988 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1445 22:05:30.320920 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1446 22:05:30.332101 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1447 22:05:30.343293 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1448 22:05:30.354435 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1449 22:05:30.365743 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1450 22:05:30.382473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1451 22:05:30.393673 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1452 22:05:30.404808 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1453 22:05:30.416096 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1454 22:05:30.421690 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1455 22:05:30.432797 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1456 22:05:30.443917 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1457 22:05:30.449705 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1458 22:05:30.460784 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1459 22:05:30.466306 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1460 22:05:30.477699 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1461 22:05:30.483123 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1462 22:05:30.494254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1463 22:05:30.499858 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1464 22:05:30.511097 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1465 22:05:30.516625 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1466 22:05:30.527853 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1467 22:05:30.538994 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1468 22:05:30.550304 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1469 22:05:30.561461 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1470 22:05:30.572644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1471 22:05:30.578270 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1472 22:05:30.589407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1473 22:05:30.595030 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1474 22:05:30.600657 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1475 22:05:30.606297 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1476 22:05:30.611792 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1477 22:05:30.617458 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1478 22:05:30.628639 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1479 22:05:30.634256 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1480 22:05:30.639730 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1481 22:05:30.651010 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1482 22:05:30.656631 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1483 22:05:30.667791 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1484 22:05:30.673470 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1485 22:05:30.684668 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1486 22:05:30.690170 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1487 22:05:30.701463 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1488 22:05:30.706899 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1489 22:05:30.718195 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1490 22:05:30.723791 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1491 22:05:30.734915 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1492 22:05:30.740671 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1493 22:05:30.751821 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1494 22:05:30.757322 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1495 22:05:30.762916 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1496 22:05:30.774173 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1497 22:05:30.779793 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1498 22:05:30.790913 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1499 22:05:30.796542 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1500 22:05:30.807709 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1501 22:05:30.813291 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1502 22:05:30.824536 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1503 22:05:30.830044 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1504 22:05:30.835663 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1505 22:05:30.846913 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1506 22:05:30.852415 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1507 22:05:30.863663 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1508 22:05:30.874913 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1509 22:05:30.886038 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1510 22:05:30.897288 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1511 22:05:30.908406 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1512 22:05:30.919663 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1513 22:05:30.930784 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1514 22:05:30.942038 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1515 22:05:30.947661 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1516 22:05:30.958781 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1517 22:05:30.964384 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1518 22:05:30.975659 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1519 22:05:30.981160 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1520 22:05:30.992405 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1521 22:05:30.997910 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1522 22:05:31.009159 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1523 22:05:31.014784 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1524 22:05:31.026036 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1525 22:05:31.031660 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1526 22:05:31.042782 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1527 22:05:31.048408 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1528 22:05:31.059655 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1529 22:05:31.065312 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1530 22:05:31.070906 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1531 22:05:31.082168 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1532 22:05:31.087783 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1533 22:05:31.098962 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1534 22:05:31.104666 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1535 22:05:31.115764 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1536 22:05:31.121413 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1537 22:05:31.132637 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1538 22:05:31.138142 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1539 22:05:31.143763 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1540 22:05:31.149438 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1541 22:05:31.160638 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1542 22:05:31.171777 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1543 22:05:31.177408 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1544 22:05:31.183040 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1545 22:05:31.194135 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1546 22:05:31.205386 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1547 22:05:31.216649 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1548 22:05:31.227779 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1549 22:05:31.233454 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1550 22:05:31.239042 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1551 22:05:31.244805 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1552 22:05:31.250413 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1553 22:05:31.255914 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1554 22:05:31.261664 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1555 22:05:31.272870 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1556 22:05:31.278389 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1557 22:05:31.284038 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1558 22:05:31.289662 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1559 22:05:31.295200 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1560 22:05:31.306451 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1561 22:05:31.311940 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1562 22:05:31.317698 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1563 22:05:31.323194 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1564 22:05:31.328806 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1565 22:05:31.334450 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1566 22:05:31.340074 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1567 22:05:31.345700 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1568 22:05:31.351200 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1569 22:05:31.356818 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1570 22:05:31.362451 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1571 22:05:31.367948 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1572 22:05:31.373701 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1573 22:05:31.379162 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1574 22:05:31.384768 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1575 22:05:31.390446 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1576 22:05:31.396068 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1577 22:05:31.401695 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1578 22:05:31.407178 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1579 22:05:31.412811 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1580 22:05:31.418445 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1581 22:05:31.418745 dt_test_unprobed_devices_sh_opp-table skip
1582 22:05:31.424066 dt_test_unprobed_devices_sh_soc skip
1583 22:05:31.429694 dt_test_unprobed_devices_sh_sound pass
1584 22:05:31.435321 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1585 22:05:31.440817 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1586 22:05:31.446430 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1587 22:05:31.452044 dt_test_unprobed_devices_sh fail
1588 22:05:31.452318 + ../../utils/send-to-lava.sh ./output/result.txt
1589 22:05:31.458692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1590 22:05:31.459249 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1592 22:05:31.467702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1593 22:05:31.468191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1595 22:05:31.563474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1596 22:05:31.563960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1598 22:05:31.657079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1599 22:05:31.657566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1601 22:05:31.751380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1602 22:05:31.751866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1604 22:05:31.846654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1605 22:05:31.847189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1607 22:05:31.942897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1608 22:05:31.943379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1610 22:05:32.039066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1611 22:05:32.039575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1613 22:05:32.138839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1614 22:05:32.139341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1616 22:05:32.234928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1617 22:05:32.235404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1619 22:05:32.330427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1620 22:05:32.330971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1622 22:05:32.426157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1623 22:05:32.426633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1625 22:05:32.521639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1626 22:05:32.522113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1628 22:05:32.615284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1629 22:05:32.615788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1631 22:05:32.709913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1632 22:05:32.710401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1634 22:05:32.810035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1635 22:05:32.810558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1637 22:05:32.910936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1638 22:05:32.911420 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1640 22:05:33.008902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1641 22:05:33.009387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1643 22:05:33.108566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1644 22:05:33.109068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1646 22:05:33.205972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1647 22:05:33.206447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1649 22:05:33.302746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1650 22:05:33.303290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1652 22:05:33.397698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1653 22:05:33.398179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1655 22:05:33.495567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1656 22:05:33.496044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1658 22:05:33.592195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1659 22:05:33.592676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1661 22:05:33.684106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1662 22:05:33.684597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1664 22:05:33.779212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1665 22:05:33.779762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1667 22:05:33.873687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1668 22:05:33.874172 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1670 22:05:33.972902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1671 22:05:33.973407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1673 22:05:34.069970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1674 22:05:34.070476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1676 22:05:34.165827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1677 22:05:34.166310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1679 22:05:34.261550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1680 22:05:34.262026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1682 22:05:34.356692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1683 22:05:34.357259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1685 22:05:34.454827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1686 22:05:34.455299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1688 22:05:34.558083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1689 22:05:34.558558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1691 22:05:34.654820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1692 22:05:34.655296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1694 22:05:34.751965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1695 22:05:34.752438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1697 22:05:34.848797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1698 22:05:34.849336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1700 22:05:34.948460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1701 22:05:34.948967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1703 22:05:35.045835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1704 22:05:35.046317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1706 22:05:35.141132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1707 22:05:35.141610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1709 22:05:35.235896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1710 22:05:35.236380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1712 22:05:35.331502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1713 22:05:35.332044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1715 22:05:35.430739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1716 22:05:35.431215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1718 22:05:35.529313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1719 22:05:35.529848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1721 22:05:35.627308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1722 22:05:35.627791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1724 22:05:35.726255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1725 22:05:35.726708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1727 22:05:35.826502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1728 22:05:35.827055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1730 22:05:35.923631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1731 22:05:35.924107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1733 22:05:36.021034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1734 22:05:36.021514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1736 22:05:36.117496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1737 22:05:36.117947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1739 22:05:36.214113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1740 22:05:36.214590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1742 22:05:36.310996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1743 22:05:36.311542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1745 22:05:36.409464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1746 22:05:36.409939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1748 22:05:36.507842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1749 22:05:36.508325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1751 22:05:36.607657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1752 22:05:36.608145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1754 22:05:36.707337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1755 22:05:36.707827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1757 22:05:36.806848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1758 22:05:36.807391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1760 22:05:36.906827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1761 22:05:36.907306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1763 22:05:37.009583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1764 22:05:37.010063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1766 22:05:37.109249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1767 22:05:37.109732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1769 22:05:37.207083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1770 22:05:37.207560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1772 22:05:37.303563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1773 22:05:37.304109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1775 22:05:37.401944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1776 22:05:37.402422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1778 22:05:37.501676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1779 22:05:37.502155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1781 22:05:37.600565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1782 22:05:37.601071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1784 22:05:37.698292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1785 22:05:37.698775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1787 22:05:37.798451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1788 22:05:37.799002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1790 22:05:37.899787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1791 22:05:37.900263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1793 22:05:37.998705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1794 22:05:37.999213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1796 22:05:38.094327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1797 22:05:38.094816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1799 22:05:38.195662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1800 22:05:38.196153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1802 22:05:38.294725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1803 22:05:38.295285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1805 22:05:38.393797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1806 22:05:38.394265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1808 22:05:38.489406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1809 22:05:38.490022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1811 22:05:38.586805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1812 22:05:38.587302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1814 22:05:38.683636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1815 22:05:38.684104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1817 22:05:38.779926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1818 22:05:38.780414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1820 22:05:38.879023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1821 22:05:38.879602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1823 22:05:38.978892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1824 22:05:38.979381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1826 22:05:39.078269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1827 22:05:39.078741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1829 22:05:39.174021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1830 22:05:39.174498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1832 22:05:39.270618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1833 22:05:39.271118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1835 22:05:39.368778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1836 22:05:39.369346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1838 22:05:39.465245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1839 22:05:39.465721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1841 22:05:39.563560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1842 22:05:39.564051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1844 22:05:39.664311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1845 22:05:39.664622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1847 22:05:39.757786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1848 22:05:39.758242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1850 22:05:39.855389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1851 22:05:39.855938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1853 22:05:39.953102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1854 22:05:39.953572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1856 22:05:40.052425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1857 22:05:40.052938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1859 22:05:40.150724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1860 22:05:40.151227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1862 22:05:40.246382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1863 22:05:40.246871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1865 22:05:40.346980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1866 22:05:40.347543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1868 22:05:40.446633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1869 22:05:40.447131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1871 22:05:40.544223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1872 22:05:40.544732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1874 22:05:40.638813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1875 22:05:40.639306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1877 22:05:40.734824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1878 22:05:40.735298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1880 22:05:40.834080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1881 22:05:40.834633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1883 22:05:40.931065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1884 22:05:40.931547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1886 22:05:41.025773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1887 22:05:41.026263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1889 22:05:41.126367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1890 22:05:41.126862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1892 22:05:41.225130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1893 22:05:41.225655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1895 22:05:41.323184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1896 22:05:41.323759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1898 22:05:41.420984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1899 22:05:41.421498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1901 22:05:41.519816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1902 22:05:41.520311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1904 22:05:41.618972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1905 22:05:41.619495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1907 22:05:41.717498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1908 22:05:41.718011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1910 22:05:41.817615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1911 22:05:41.818171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1913 22:05:41.919589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1914 22:05:41.920077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1916 22:05:42.019838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1917 22:05:42.020334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1919 22:05:42.120089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1920 22:05:42.120578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1922 22:05:42.220346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1923 22:05:42.220853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1925 22:05:42.319309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1926 22:05:42.319866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1928 22:05:42.417495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1929 22:05:42.417984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1931 22:05:42.515811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1932 22:05:42.516301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1934 22:05:42.615321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1935 22:05:42.615860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1937 22:05:42.714169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1938 22:05:42.714663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1940 22:05:42.812339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1941 22:05:42.812882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1943 22:05:42.909353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1944 22:05:42.909859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1946 22:05:43.006099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1947 22:05:43.006615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1949 22:05:43.102868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1951 22:05:43.105966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1952 22:05:43.199584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1954 22:05:43.202693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1955 22:05:43.298065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1957 22:05:43.301180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1958 22:05:43.398935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1959 22:05:43.399495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1961 22:05:43.495770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1962 22:05:43.496263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1964 22:05:43.592432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1965 22:05:43.592937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1967 22:05:43.693413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1968 22:05:43.693902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1970 22:05:43.791274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1971 22:05:43.791761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1973 22:05:43.888556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1974 22:05:43.889162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1976 22:05:43.986274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1977 22:05:43.986762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1979 22:05:44.086564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1980 22:05:44.087074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1982 22:05:44.185916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1983 22:05:44.186433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1985 22:05:44.284286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1986 22:05:44.284777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1988 22:05:44.382028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1989 22:05:44.382577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1991 22:05:44.481790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1992 22:05:44.482273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1994 22:05:44.579323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1995 22:05:44.579803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1997 22:05:44.677660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1998 22:05:44.678148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2000 22:05:44.779260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2001 22:05:44.779753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2003 22:05:44.879623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2004 22:05:44.880185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2006 22:05:44.974839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2007 22:05:44.975326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2009 22:05:45.072894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2010 22:05:45.073379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2012 22:05:45.171218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2013 22:05:45.171706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2015 22:05:45.267348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2016 22:05:45.267841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2018 22:05:45.366419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2019 22:05:45.366977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2021 22:05:45.457631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2022 22:05:45.458113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2024 22:05:45.550598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2025 22:05:45.551082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2027 22:05:45.644343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2028 22:05:45.644836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2030 22:05:45.737725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2031 22:05:45.738207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2033 22:05:45.836324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2034 22:05:45.836892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2036 22:05:45.928470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2037 22:05:45.928973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2039 22:05:46.025202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2040 22:05:46.025690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2042 22:05:46.119700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2043 22:05:46.120185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2045 22:05:46.218815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2046 22:05:46.219305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2048 22:05:46.316342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2049 22:05:46.316903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2051 22:05:46.411251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2052 22:05:46.411726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2054 22:05:46.506302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2055 22:05:46.506787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2057 22:05:46.602067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2058 22:05:46.602557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2060 22:05:46.693869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2061 22:05:46.694346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2063 22:05:46.790216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2064 22:05:46.790692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2066 22:05:46.883792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2067 22:05:46.884349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2069 22:05:46.979586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2070 22:05:46.980063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2072 22:05:47.072156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2073 22:05:47.072639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2075 22:05:47.167510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2076 22:05:47.167991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2078 22:05:47.263500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2079 22:05:47.263978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2081 22:05:47.359607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2082 22:05:47.360152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2084 22:05:47.456118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2085 22:05:47.456602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2087 22:05:47.558016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2088 22:05:47.558498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2090 22:05:47.656493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2091 22:05:47.657000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2093 22:05:47.755154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2094 22:05:47.755648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2096 22:05:47.851728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2097 22:05:47.852274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2099 22:05:47.949523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2100 22:05:47.950007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2102 22:05:48.044138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2103 22:05:48.044616 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2105 22:05:48.145748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2106 22:05:48.146233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2108 22:05:48.242243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2109 22:05:48.242729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2111 22:05:48.339780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2112 22:05:48.340336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2114 22:05:48.436084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2115 22:05:48.436565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2117 22:05:48.536768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2118 22:05:48.537255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2120 22:05:48.634478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2121 22:05:48.634970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2123 22:05:48.733960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2124 22:05:48.734447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2126 22:05:48.829458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2127 22:05:48.830055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2129 22:05:48.928354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2130 22:05:48.928859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2132 22:05:49.027076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2133 22:05:49.027581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2135 22:05:49.125202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2136 22:05:49.125694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2138 22:05:49.226017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2139 22:05:49.226527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2141 22:05:49.322899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2142 22:05:49.323491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2144 22:05:49.419185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2145 22:05:49.419677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2147 22:05:49.510318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2148 22:05:49.510798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2150 22:05:49.607798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2151 22:05:49.608283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2153 22:05:49.704165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2154 22:05:49.704647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2156 22:05:49.801663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2157 22:05:49.802154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2159 22:05:49.899371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2160 22:05:49.899743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2162 22:05:49.992851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2163 22:05:49.993275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2165 22:05:50.087969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2166 22:05:50.088462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2168 22:05:50.183084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2169 22:05:50.183571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2171 22:05:50.278572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2172 22:05:50.279055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2174 22:05:50.376415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2175 22:05:50.376973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2177 22:05:50.475497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2178 22:05:50.475975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2180 22:05:50.574156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2181 22:05:50.574642 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2183 22:05:50.674016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2184 22:05:50.674505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2186 22:05:50.775139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2187 22:05:50.775618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2189 22:05:50.873906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2190 22:05:50.874453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2192 22:05:50.971009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2193 22:05:50.971467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2195 22:05:51.076006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2196 22:05:51.076481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2198 22:05:51.175937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2199 22:05:51.176423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2201 22:05:51.275702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2202 22:05:51.276182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2204 22:05:51.373662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2205 22:05:51.374207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2207 22:05:51.471960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2208 22:05:51.472434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2210 22:05:51.570978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2211 22:05:51.571452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2213 22:05:51.668171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2214 22:05:51.668654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2216 22:05:51.763602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2217 22:05:51.764088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2219 22:05:51.865242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2220 22:05:51.865785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2222 22:05:51.965988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2223 22:05:51.966469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2225 22:05:52.076965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2226 22:05:52.077451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2228 22:05:52.192858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2229 22:05:52.193338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2231 22:05:52.289710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2232 22:05:52.290190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2234 22:05:52.386664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2235 22:05:52.387209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2237 22:05:52.487627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2238 22:05:52.488125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2240 22:05:52.588247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2241 22:05:52.588773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2243 22:05:52.685375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2244 22:05:52.685866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2246 22:05:52.784161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2247 22:05:52.784647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2249 22:05:52.884019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2250 22:05:52.884601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2252 22:05:52.977610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2253 22:05:52.978128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2255 22:05:53.077487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2256 22:05:53.077973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2258 22:05:53.171983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2259 22:05:53.172471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2261 22:05:53.269642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2262 22:05:53.270129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2264 22:05:53.369353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2265 22:05:53.369909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2267 22:05:53.468779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2268 22:05:53.469263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2270 22:05:53.564626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2272 22:05:53.567608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2273 22:05:53.665470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2274 22:05:53.665963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2276 22:05:53.765335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2277 22:05:53.765848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2279 22:05:53.863586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2280 22:05:53.864144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2282 22:05:53.961327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2283 22:05:53.961820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2285 22:05:54.057950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2286 22:05:54.058435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2288 22:05:54.154694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2289 22:05:54.155180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2291 22:05:54.253942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2292 22:05:54.254430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2294 22:05:54.354198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2295 22:05:54.354752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2297 22:05:54.451193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2298 22:05:54.451691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2300 22:05:54.548953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2301 22:05:54.549432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2303 22:05:54.651145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2304 22:05:54.651635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2306 22:05:54.744786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2307 22:05:54.745264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2309 22:05:54.841648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2310 22:05:54.842192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2312 22:05:54.939272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2313 22:05:54.939749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2315 22:05:55.037607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2316 22:05:55.038081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2318 22:05:55.131303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2319 22:05:55.131784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2321 22:05:55.231382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2322 22:05:55.231862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2324 22:05:55.329581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2325 22:05:55.330090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2327 22:05:55.431856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2328 22:05:55.432399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2330 22:05:55.529981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2331 22:05:55.530467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2333 22:05:55.624020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2334 22:05:55.624507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2336 22:05:55.722864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2337 22:05:55.723340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2339 22:05:55.822203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2340 22:05:55.822679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2342 22:05:55.921254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2343 22:05:55.921802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2345 22:05:56.018439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2346 22:05:56.018914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2348 22:05:56.120347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2349 22:05:56.120822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2351 22:05:56.217815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2352 22:05:56.218288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2354 22:05:56.315986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2355 22:05:56.316473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2357 22:05:56.415191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2358 22:05:56.415729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2360 22:05:56.514808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2361 22:05:56.515286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2363 22:05:56.608272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2364 22:05:56.608572 + set +x
2365 22:05:56.609089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2367 22:05:56.612584 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1219856_1.6.2.4.5>
2368 22:05:56.613045 Received signal: <ENDRUN> 1_kselftest-dt 1219856_1.6.2.4.5
2369 22:05:56.613291 Ending use of test pattern.
2370 22:05:56.613513 Ending test lava.1_kselftest-dt (1219856_1.6.2.4.5), duration 95.74
2372 22:05:56.619437 <LAVA_TEST_RUNNER EXIT>
2373 22:05:56.619916 ok: lava_test_shell seems to have completed
2374 22:05:56.625753 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2375 22:05:56.626821 end: 3.1 lava-test-shell (duration 00:01:37) [common]
2376 22:05:56.627142 end: 3 lava-test-retry (duration 00:01:37) [common]
2377 22:05:56.627441 start: 4 finalize (timeout 00:05:45) [common]
2378 22:05:56.627743 start: 4.1 power-off (timeout 00:00:30) [common]
2379 22:05:56.628126 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2380 22:05:56.993686 Returned 0 in 0 seconds
2381 22:05:57.094758 end: 4.1 power-off (duration 00:00:00) [common]
2383 22:05:57.095676 start: 4.2 read-feedback (timeout 00:05:44) [common]
2384 22:05:57.096300 Listened to connection for namespace 'common' for up to 1s
2385 22:05:57.096855 Listened to connection for namespace 'common' for up to 1s
2386 22:05:58.096877 Finalising connection for namespace 'common'
2387 22:05:58.097296 Disconnecting from shell: Finalise
2388 22:05:58.097565 / #
2389 22:05:58.198116 end: 4.2 read-feedback (duration 00:00:01) [common]
2390 22:05:58.198482 end: 4 finalize (duration 00:00:02) [common]
2391 22:05:58.198842 Cleaning after the job
2392 22:05:58.199167 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219856/tftp-deploy-c_q0q541/ramdisk
2393 22:05:58.202768 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219856/tftp-deploy-c_q0q541/kernel
2394 22:05:58.205688 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219856/tftp-deploy-c_q0q541/dtb
2395 22:05:58.206155 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219856/tftp-deploy-c_q0q541/nfsrootfs
2396 22:05:58.258126 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1219856/tftp-deploy-c_q0q541/modules
2397 22:05:58.261526 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1219856
2398 22:05:58.921343 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1219856
2399 22:05:58.921629 Job finished correctly