Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:14:26.079652 lava-dispatcher, installed at version: 2024.01
2 22:14:26.080477 start: 0 validate
3 22:14:26.080951 Start time: 2024-11-08 22:14:26.080922+00:00 (UTC)
4 22:14:26.081490 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:14:26.082041 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:14:26.123902 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:14:26.124517 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fkernel%2FImage exists
8 22:14:26.153693 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:14:26.154326 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 22:14:26.184858 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:14:26.185369 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:14:26.214074 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 22:14:26.214601 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fmodules.tar.xz exists
14 22:14:26.249163 validate duration: 0.17
16 22:14:26.250252 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:14:26.250606 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:14:26.250947 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:14:26.251558 Not decompressing ramdisk as can be used compressed.
20 22:14:26.252048 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 22:14:26.252356 saving as /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/ramdisk/initrd.cpio.gz
22 22:14:26.252642 total size: 5628182 (5 MB)
23 22:14:26.288035 progress 0 % (0 MB)
24 22:14:26.292614 progress 5 % (0 MB)
25 22:14:26.296734 progress 10 % (0 MB)
26 22:14:26.300306 progress 15 % (0 MB)
27 22:14:26.304306 progress 20 % (1 MB)
28 22:14:26.307916 progress 25 % (1 MB)
29 22:14:26.311843 progress 30 % (1 MB)
30 22:14:26.315870 progress 35 % (1 MB)
31 22:14:26.319480 progress 40 % (2 MB)
32 22:14:26.323407 progress 45 % (2 MB)
33 22:14:26.326950 progress 50 % (2 MB)
34 22:14:26.330912 progress 55 % (2 MB)
35 22:14:26.334857 progress 60 % (3 MB)
36 22:14:26.338402 progress 65 % (3 MB)
37 22:14:26.342303 progress 70 % (3 MB)
38 22:14:26.345980 progress 75 % (4 MB)
39 22:14:26.349729 progress 80 % (4 MB)
40 22:14:26.352991 progress 85 % (4 MB)
41 22:14:26.356649 progress 90 % (4 MB)
42 22:14:26.360252 progress 95 % (5 MB)
43 22:14:26.363484 progress 100 % (5 MB)
44 22:14:26.364125 5 MB downloaded in 0.11 s (48.15 MB/s)
45 22:14:26.364677 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:14:26.365549 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:14:26.365849 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:14:26.366124 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:14:26.366611 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/kernel/Image
51 22:14:26.366873 saving as /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/kernel/Image
52 22:14:26.367085 total size: 39424512 (37 MB)
53 22:14:26.367295 No compression specified
54 22:14:26.400277 progress 0 % (0 MB)
55 22:14:26.424098 progress 5 % (1 MB)
56 22:14:26.447706 progress 10 % (3 MB)
57 22:14:26.471112 progress 15 % (5 MB)
58 22:14:26.494283 progress 20 % (7 MB)
59 22:14:26.518020 progress 25 % (9 MB)
60 22:14:26.541270 progress 30 % (11 MB)
61 22:14:26.564822 progress 35 % (13 MB)
62 22:14:26.588302 progress 40 % (15 MB)
63 22:14:26.611944 progress 45 % (16 MB)
64 22:14:26.635348 progress 50 % (18 MB)
65 22:14:26.658761 progress 55 % (20 MB)
66 22:14:26.682111 progress 60 % (22 MB)
67 22:14:26.705995 progress 65 % (24 MB)
68 22:14:26.729413 progress 70 % (26 MB)
69 22:14:26.752691 progress 75 % (28 MB)
70 22:14:26.775954 progress 80 % (30 MB)
71 22:14:26.800089 progress 85 % (31 MB)
72 22:14:26.823733 progress 90 % (33 MB)
73 22:14:26.847434 progress 95 % (35 MB)
74 22:14:26.870331 progress 100 % (37 MB)
75 22:14:26.870893 37 MB downloaded in 0.50 s (74.63 MB/s)
76 22:14:26.871411 end: 1.2.1 http-download (duration 00:00:01) [common]
78 22:14:26.872338 end: 1.2 download-retry (duration 00:00:01) [common]
79 22:14:26.872648 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:14:26.872944 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:14:26.873467 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 22:14:26.873744 saving as /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/dtb/meson-g12b-a311d-libretech-cc.dtb
83 22:14:26.873968 total size: 54703 (0 MB)
84 22:14:26.874193 No compression specified
85 22:14:26.918955 progress 59 % (0 MB)
86 22:14:26.919959 progress 100 % (0 MB)
87 22:14:26.920663 0 MB downloaded in 0.05 s (1.12 MB/s)
88 22:14:26.921219 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:14:26.923819 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:14:26.926264 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:14:26.927057 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:14:26.928184 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 22:14:26.928512 saving as /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/nfsrootfs/full.rootfs.tar
95 22:14:26.928765 total size: 107552908 (102 MB)
96 22:14:26.929021 Using unxz to decompress xz
97 22:14:26.972913 progress 0 % (0 MB)
98 22:14:27.629141 progress 5 % (5 MB)
99 22:14:28.353795 progress 10 % (10 MB)
100 22:14:29.080527 progress 15 % (15 MB)
101 22:14:29.895171 progress 20 % (20 MB)
102 22:14:30.465834 progress 25 % (25 MB)
103 22:14:31.086608 progress 30 % (30 MB)
104 22:14:31.821903 progress 35 % (35 MB)
105 22:14:32.192689 progress 40 % (41 MB)
106 22:14:32.623068 progress 45 % (46 MB)
107 22:14:33.316311 progress 50 % (51 MB)
108 22:14:33.997618 progress 55 % (56 MB)
109 22:14:34.750297 progress 60 % (61 MB)
110 22:14:35.503210 progress 65 % (66 MB)
111 22:14:36.237861 progress 70 % (71 MB)
112 22:14:37.003262 progress 75 % (76 MB)
113 22:14:37.679439 progress 80 % (82 MB)
114 22:14:38.380340 progress 85 % (87 MB)
115 22:14:39.114693 progress 90 % (92 MB)
116 22:14:39.833105 progress 95 % (97 MB)
117 22:14:40.581733 progress 100 % (102 MB)
118 22:14:40.594928 102 MB downloaded in 13.67 s (7.51 MB/s)
119 22:14:40.595926 end: 1.4.1 http-download (duration 00:00:14) [common]
121 22:14:40.598011 end: 1.4 download-retry (duration 00:00:14) [common]
122 22:14:40.598594 start: 1.5 download-retry (timeout 00:09:46) [common]
123 22:14:40.599174 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 22:14:40.600164 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/modules.tar.xz
125 22:14:40.600696 saving as /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/modules/modules.tar
126 22:14:40.601156 total size: 11765932 (11 MB)
127 22:14:40.601626 Using unxz to decompress xz
128 22:14:40.644427 progress 0 % (0 MB)
129 22:14:40.714947 progress 5 % (0 MB)
130 22:14:40.793622 progress 10 % (1 MB)
131 22:14:40.893347 progress 15 % (1 MB)
132 22:14:40.990295 progress 20 % (2 MB)
133 22:14:41.070583 progress 25 % (2 MB)
134 22:14:41.148163 progress 30 % (3 MB)
135 22:14:41.228787 progress 35 % (3 MB)
136 22:14:41.309260 progress 40 % (4 MB)
137 22:14:41.386113 progress 45 % (5 MB)
138 22:14:41.472109 progress 50 % (5 MB)
139 22:14:41.555342 progress 55 % (6 MB)
140 22:14:41.641227 progress 60 % (6 MB)
141 22:14:41.724246 progress 65 % (7 MB)
142 22:14:41.808081 progress 70 % (7 MB)
143 22:14:41.892709 progress 75 % (8 MB)
144 22:14:41.978842 progress 80 % (9 MB)
145 22:14:42.061257 progress 85 % (9 MB)
146 22:14:42.147013 progress 90 % (10 MB)
147 22:14:42.227651 progress 95 % (10 MB)
148 22:14:42.313487 progress 100 % (11 MB)
149 22:14:42.327308 11 MB downloaded in 1.73 s (6.50 MB/s)
150 22:14:42.328286 end: 1.5.1 http-download (duration 00:00:02) [common]
152 22:14:42.329870 end: 1.5 download-retry (duration 00:00:02) [common]
153 22:14:42.330382 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 22:14:42.330894 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 22:14:52.780908 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/963111/extract-nfsrootfs-zzhmto_d
156 22:14:52.781508 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 22:14:52.781799 start: 1.6.2 lava-overlay (timeout 00:09:33) [common]
158 22:14:52.782523 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c
159 22:14:52.782979 makedir: /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin
160 22:14:52.783305 makedir: /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/tests
161 22:14:52.783620 makedir: /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/results
162 22:14:52.783951 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-add-keys
163 22:14:52.784520 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-add-sources
164 22:14:52.785050 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-background-process-start
165 22:14:52.785568 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-background-process-stop
166 22:14:52.786097 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-common-functions
167 22:14:52.786604 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-echo-ipv4
168 22:14:52.787099 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-install-packages
169 22:14:52.787591 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-installed-packages
170 22:14:52.788100 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-os-build
171 22:14:52.788600 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-probe-channel
172 22:14:52.789117 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-probe-ip
173 22:14:52.789630 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-target-ip
174 22:14:52.790112 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-target-mac
175 22:14:52.790595 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-target-storage
176 22:14:52.791078 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-test-case
177 22:14:52.791563 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-test-event
178 22:14:52.792084 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-test-feedback
179 22:14:52.792582 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-test-raise
180 22:14:52.793121 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-test-reference
181 22:14:52.793632 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-test-runner
182 22:14:52.794124 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-test-set
183 22:14:52.794600 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-test-shell
184 22:14:52.795086 Updating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-install-packages (oe)
185 22:14:52.795621 Updating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/bin/lava-installed-packages (oe)
186 22:14:52.796097 Creating /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/environment
187 22:14:52.796489 LAVA metadata
188 22:14:52.796751 - LAVA_JOB_ID=963111
189 22:14:52.796970 - LAVA_DISPATCHER_IP=192.168.6.2
190 22:14:52.797349 start: 1.6.2.1 ssh-authorize (timeout 00:09:33) [common]
191 22:14:52.798344 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 22:14:52.798675 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:33) [common]
193 22:14:52.798883 skipped lava-vland-overlay
194 22:14:52.799124 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 22:14:52.799382 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:33) [common]
196 22:14:52.799601 skipped lava-multinode-overlay
197 22:14:52.799843 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 22:14:52.800121 start: 1.6.2.4 test-definition (timeout 00:09:33) [common]
199 22:14:52.800379 Loading test definitions
200 22:14:52.800661 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:33) [common]
201 22:14:52.800884 Using /lava-963111 at stage 0
202 22:14:52.802193 uuid=963111_1.6.2.4.1 testdef=None
203 22:14:52.802528 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 22:14:52.802798 start: 1.6.2.4.2 test-overlay (timeout 00:09:33) [common]
205 22:14:52.804703 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 22:14:52.805540 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:33) [common]
208 22:14:52.807923 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 22:14:52.808785 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:33) [common]
211 22:14:52.810978 runner path: /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/0/tests/0_dmesg test_uuid 963111_1.6.2.4.1
212 22:14:52.811569 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 22:14:52.812364 Creating lava-test-runner.conf files
215 22:14:52.812572 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/963111/lava-overlay-kk7xb93c/lava-963111/0 for stage 0
216 22:14:52.812933 - 0_dmesg
217 22:14:52.813288 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 22:14:52.813570 start: 1.6.2.5 compress-overlay (timeout 00:09:33) [common]
219 22:14:52.835704 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 22:14:52.836171 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:33) [common]
221 22:14:52.836441 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 22:14:52.836716 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 22:14:52.836982 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
224 22:14:53.459256 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 22:14:53.459704 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 22:14:53.459959 extracting modules file /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/963111/extract-nfsrootfs-zzhmto_d
227 22:14:54.840718 extracting modules file /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/963111/extract-overlay-ramdisk-f0ufcvf2/ramdisk
228 22:14:56.264282 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 22:14:56.264741 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
230 22:14:56.265020 [common] Applying overlay to NFS
231 22:14:56.265234 [common] Applying overlay /var/lib/lava/dispatcher/tmp/963111/compress-overlay-0rdl552b/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/963111/extract-nfsrootfs-zzhmto_d
232 22:14:56.294778 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 22:14:56.295209 start: 1.6.6 prepare-kernel (timeout 00:09:30) [common]
234 22:14:56.295483 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:30) [common]
235 22:14:56.295715 Converting downloaded kernel to a uImage
236 22:14:56.296055 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/kernel/Image /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/kernel/uImage
237 22:14:56.704196 output: Image Name:
238 22:14:56.704605 output: Created: Fri Nov 8 22:14:56 2024
239 22:14:56.704814 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 22:14:56.705020 output: Data Size: 39424512 Bytes = 38500.50 KiB = 37.60 MiB
241 22:14:56.705224 output: Load Address: 01080000
242 22:14:56.705424 output: Entry Point: 01080000
243 22:14:56.705623 output:
244 22:14:56.705959 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 22:14:56.706223 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 22:14:56.706491 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 22:14:56.706744 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 22:14:56.707000 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 22:14:56.707257 Building ramdisk /var/lib/lava/dispatcher/tmp/963111/extract-overlay-ramdisk-f0ufcvf2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/963111/extract-overlay-ramdisk-f0ufcvf2/ramdisk
250 22:14:58.980376 >> 173486 blocks
251 22:15:06.667533 Adding RAMdisk u-boot header.
252 22:15:06.668331 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/963111/extract-overlay-ramdisk-f0ufcvf2/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/963111/extract-overlay-ramdisk-f0ufcvf2/ramdisk.cpio.gz.uboot
253 22:15:06.928334 output: Image Name:
254 22:15:06.928755 output: Created: Fri Nov 8 22:15:06 2024
255 22:15:06.928970 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 22:15:06.929178 output: Data Size: 24134731 Bytes = 23569.07 KiB = 23.02 MiB
257 22:15:06.929382 output: Load Address: 00000000
258 22:15:06.929582 output: Entry Point: 00000000
259 22:15:06.929779 output:
260 22:15:06.930443 rename /var/lib/lava/dispatcher/tmp/963111/extract-overlay-ramdisk-f0ufcvf2/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/ramdisk/ramdisk.cpio.gz.uboot
261 22:15:06.930874 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 22:15:06.931159 end: 1.6 prepare-tftp-overlay (duration 00:00:25) [common]
263 22:15:06.931459 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
264 22:15:06.931696 No LXC device requested
265 22:15:06.931949 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 22:15:06.932600 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
267 22:15:06.933175 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 22:15:06.933633 Checking files for TFTP limit of 4294967296 bytes.
269 22:15:06.936606 end: 1 tftp-deploy (duration 00:00:41) [common]
270 22:15:06.937263 start: 2 uboot-action (timeout 00:05:00) [common]
271 22:15:06.937845 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 22:15:06.938393 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 22:15:06.938945 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 22:15:06.939523 Using kernel file from prepare-kernel: 963111/tftp-deploy-_52k09kn/kernel/uImage
275 22:15:06.940246 substitutions:
276 22:15:06.940711 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 22:15:06.941163 - {DTB_ADDR}: 0x01070000
278 22:15:06.941605 - {DTB}: 963111/tftp-deploy-_52k09kn/dtb/meson-g12b-a311d-libretech-cc.dtb
279 22:15:06.942047 - {INITRD}: 963111/tftp-deploy-_52k09kn/ramdisk/ramdisk.cpio.gz.uboot
280 22:15:06.942486 - {KERNEL_ADDR}: 0x01080000
281 22:15:06.942921 - {KERNEL}: 963111/tftp-deploy-_52k09kn/kernel/uImage
282 22:15:06.943354 - {LAVA_MAC}: None
283 22:15:06.943836 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/963111/extract-nfsrootfs-zzhmto_d
284 22:15:06.944306 - {NFS_SERVER_IP}: 192.168.6.2
285 22:15:06.944743 - {PRESEED_CONFIG}: None
286 22:15:06.945176 - {PRESEED_LOCAL}: None
287 22:15:06.945604 - {RAMDISK_ADDR}: 0x08000000
288 22:15:06.946031 - {RAMDISK}: 963111/tftp-deploy-_52k09kn/ramdisk/ramdisk.cpio.gz.uboot
289 22:15:06.946462 - {ROOT_PART}: None
290 22:15:06.946891 - {ROOT}: None
291 22:15:06.947322 - {SERVER_IP}: 192.168.6.2
292 22:15:06.947751 - {TEE_ADDR}: 0x83000000
293 22:15:06.948207 - {TEE}: None
294 22:15:06.948641 Parsed boot commands:
295 22:15:06.949062 - setenv autoload no
296 22:15:06.949489 - setenv initrd_high 0xffffffff
297 22:15:06.949914 - setenv fdt_high 0xffffffff
298 22:15:06.950343 - dhcp
299 22:15:06.950769 - setenv serverip 192.168.6.2
300 22:15:06.951192 - tftpboot 0x01080000 963111/tftp-deploy-_52k09kn/kernel/uImage
301 22:15:06.951615 - tftpboot 0x08000000 963111/tftp-deploy-_52k09kn/ramdisk/ramdisk.cpio.gz.uboot
302 22:15:06.952065 - tftpboot 0x01070000 963111/tftp-deploy-_52k09kn/dtb/meson-g12b-a311d-libretech-cc.dtb
303 22:15:06.952495 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/963111/extract-nfsrootfs-zzhmto_d,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 22:15:06.952934 - bootm 0x01080000 0x08000000 0x01070000
305 22:15:06.953487 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 22:15:06.955134 start: 2.3 connect-device (timeout 00:05:00) [common]
308 22:15:06.955592 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 22:15:06.971030 Setting prompt string to ['lava-test: # ']
310 22:15:06.972690 end: 2.3 connect-device (duration 00:00:00) [common]
311 22:15:06.973358 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 22:15:06.973953 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 22:15:06.974519 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 22:15:06.975752 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 22:15:07.013439 >> OK - accepted request
316 22:15:07.015629 Returned 0 in 0 seconds
317 22:15:07.116613 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 22:15:07.118431 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 22:15:07.119052 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 22:15:07.119617 Setting prompt string to ['Hit any key to stop autoboot']
322 22:15:07.120251 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 22:15:07.121982 Trying 192.168.56.21...
324 22:15:07.122520 Connected to conserv1.
325 22:15:07.122985 Escape character is '^]'.
326 22:15:07.123449
327 22:15:07.123913 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 22:15:07.124436
329 22:15:19.092485 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 22:15:19.093178 bl2_stage_init 0x01
331 22:15:19.093662 bl2_stage_init 0x81
332 22:15:19.097960 hw id: 0x0000 - pwm id 0x01
333 22:15:19.098516 bl2_stage_init 0xc1
334 22:15:19.098956 bl2_stage_init 0x02
335 22:15:19.099386
336 22:15:19.103513 L0:00000000
337 22:15:19.104085 L1:20000703
338 22:15:19.104539 L2:00008067
339 22:15:19.104980 L3:14000000
340 22:15:19.106508 B2:00402000
341 22:15:19.106975 B1:e0f83180
342 22:15:19.107417
343 22:15:19.107846 TE: 58124
344 22:15:19.108326
345 22:15:19.117627 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 22:15:19.118119
347 22:15:19.118556 Board ID = 1
348 22:15:19.118984 Set A53 clk to 24M
349 22:15:19.119410 Set A73 clk to 24M
350 22:15:19.123254 Set clk81 to 24M
351 22:15:19.123714 A53 clk: 1200 MHz
352 22:15:19.124188 A73 clk: 1200 MHz
353 22:15:19.126699 CLK81: 166.6M
354 22:15:19.127152 smccc: 00012a92
355 22:15:19.132196 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 22:15:19.137760 board id: 1
357 22:15:19.142971 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 22:15:19.153668 fw parse done
359 22:15:19.159724 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 22:15:19.202183 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 22:15:19.213101 PIEI prepare done
362 22:15:19.213563 fastboot data load
363 22:15:19.213999 fastboot data verify
364 22:15:19.218729 verify result: 266
365 22:15:19.224302 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 22:15:19.224807 LPDDR4 probe
367 22:15:19.225255 ddr clk to 1584MHz
368 22:15:19.232261 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 22:15:19.269560
370 22:15:19.270066 dmc_version 0001
371 22:15:19.276289 Check phy result
372 22:15:19.282040 INFO : End of CA training
373 22:15:19.282513 INFO : End of initialization
374 22:15:19.287648 INFO : Training has run successfully!
375 22:15:19.288152 Check phy result
376 22:15:19.293263 INFO : End of initialization
377 22:15:19.293729 INFO : End of read enable training
378 22:15:19.298895 INFO : End of fine write leveling
379 22:15:19.304464 INFO : End of Write leveling coarse delay
380 22:15:19.304935 INFO : Training has run successfully!
381 22:15:19.305381 Check phy result
382 22:15:19.310076 INFO : End of initialization
383 22:15:19.310548 INFO : End of read dq deskew training
384 22:15:19.315676 INFO : End of MPR read delay center optimization
385 22:15:19.321288 INFO : End of write delay center optimization
386 22:15:19.326845 INFO : End of read delay center optimization
387 22:15:19.327335 INFO : End of max read latency training
388 22:15:19.332437 INFO : Training has run successfully!
389 22:15:19.332905 1D training succeed
390 22:15:19.341668 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 22:15:19.389298 Check phy result
392 22:15:19.389854 INFO : End of initialization
393 22:15:19.411059 INFO : End of 2D read delay Voltage center optimization
394 22:15:19.431265 INFO : End of 2D read delay Voltage center optimization
395 22:15:19.483370 INFO : End of 2D write delay Voltage center optimization
396 22:15:19.532822 INFO : End of 2D write delay Voltage center optimization
397 22:15:19.538314 INFO : Training has run successfully!
398 22:15:19.538810
399 22:15:19.539264 channel==0
400 22:15:19.543930 RxClkDly_Margin_A0==88 ps 9
401 22:15:19.544486 TxDqDly_Margin_A0==98 ps 10
402 22:15:19.549528 RxClkDly_Margin_A1==88 ps 9
403 22:15:19.550021 TxDqDly_Margin_A1==88 ps 9
404 22:15:19.550476 TrainedVREFDQ_A0==74
405 22:15:19.555093 TrainedVREFDQ_A1==74
406 22:15:19.555575 VrefDac_Margin_A0==25
407 22:15:19.556052 DeviceVref_Margin_A0==40
408 22:15:19.560763 VrefDac_Margin_A1==25
409 22:15:19.561248 DeviceVref_Margin_A1==40
410 22:15:19.561695
411 22:15:19.562142
412 22:15:19.562588 channel==1
413 22:15:19.566252 RxClkDly_Margin_A0==98 ps 10
414 22:15:19.566733 TxDqDly_Margin_A0==88 ps 9
415 22:15:19.571926 RxClkDly_Margin_A1==88 ps 9
416 22:15:19.572442 TxDqDly_Margin_A1==108 ps 11
417 22:15:19.577421 TrainedVREFDQ_A0==77
418 22:15:19.577905 TrainedVREFDQ_A1==78
419 22:15:19.578351 VrefDac_Margin_A0==22
420 22:15:19.583003 DeviceVref_Margin_A0==37
421 22:15:19.583469 VrefDac_Margin_A1==24
422 22:15:19.588680 DeviceVref_Margin_A1==36
423 22:15:19.589154
424 22:15:19.589599 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 22:15:19.590041
426 22:15:19.622303 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 22:15:19.622895 2D training succeed
428 22:15:19.627889 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 22:15:19.633369 auto size-- 65535DDR cs0 size: 2048MB
430 22:15:19.633859 DDR cs1 size: 2048MB
431 22:15:19.638969 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 22:15:19.639445 cs0 DataBus test pass
433 22:15:19.644604 cs1 DataBus test pass
434 22:15:19.645087 cs0 AddrBus test pass
435 22:15:19.645533 cs1 AddrBus test pass
436 22:15:19.645972
437 22:15:19.650272 100bdlr_step_size ps== 420
438 22:15:19.650759 result report
439 22:15:19.655768 boot times 0Enable ddr reg access
440 22:15:19.661107 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 22:15:19.674675 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 22:15:20.248390 0.0;M3 CHK:0;cm4_sp_mode 0
443 22:15:20.249085 MVN_1=0x00000000
444 22:15:20.253868 MVN_2=0x00000000
445 22:15:20.259656 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 22:15:20.260243 OPS=0x10
447 22:15:20.260731 ring efuse init
448 22:15:20.261209 chipver efuse init
449 22:15:20.267817 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 22:15:20.268409 [0.018960 Inits done]
451 22:15:20.268871 secure task start!
452 22:15:20.275343 high task start!
453 22:15:20.275899 low task start!
454 22:15:20.276435 run into bl31
455 22:15:20.281947 NOTICE: BL31: v1.3(release):4fc40b1
456 22:15:20.289810 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 22:15:20.290356 NOTICE: BL31: G12A normal boot!
458 22:15:20.315214 NOTICE: BL31: BL33 decompress pass
459 22:15:20.320860 ERROR: Error initializing runtime service opteed_fast
460 22:15:21.553715
461 22:15:21.554152
462 22:15:21.561996 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 22:15:21.562325
464 22:15:21.562543 Model: Libre Computer AML-A311D-CC Alta
465 22:15:21.770571 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 22:15:21.793881 DRAM: 2 GiB (effective 3.8 GiB)
467 22:15:21.936909 Core: 408 devices, 31 uclasses, devicetree: separate
468 22:15:21.942709 WDT: Not starting watchdog@f0d0
469 22:15:21.975001 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 22:15:21.987382 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 22:15:21.992425 ** Bad device specification mmc 0 **
472 22:15:22.002791 Card did not respond to voltage select! : -110
473 22:15:22.010369 ** Bad device specification mmc 0 **
474 22:15:22.010886 Couldn't find partition mmc 0
475 22:15:22.018727 Card did not respond to voltage select! : -110
476 22:15:22.024244 ** Bad device specification mmc 0 **
477 22:15:22.024795 Couldn't find partition mmc 0
478 22:15:22.029300 Error: could not access storage.
479 22:15:23.292541 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 22:15:23.293176 bl2_stage_init 0x01
481 22:15:23.293645 bl2_stage_init 0x81
482 22:15:23.298173 hw id: 0x0000 - pwm id 0x01
483 22:15:23.298685 bl2_stage_init 0xc1
484 22:15:23.299144 bl2_stage_init 0x02
485 22:15:23.299589
486 22:15:23.303761 L0:00000000
487 22:15:23.304300 L1:20000703
488 22:15:23.304754 L2:00008067
489 22:15:23.305195 L3:14000000
490 22:15:23.309368 B2:00402000
491 22:15:23.309865 B1:e0f83180
492 22:15:23.310311
493 22:15:23.310753 TE: 58124
494 22:15:23.311197
495 22:15:23.314974 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 22:15:23.315480
497 22:15:23.315934 Board ID = 1
498 22:15:23.320565 Set A53 clk to 24M
499 22:15:23.321074 Set A73 clk to 24M
500 22:15:23.321531 Set clk81 to 24M
501 22:15:23.326133 A53 clk: 1200 MHz
502 22:15:23.326631 A73 clk: 1200 MHz
503 22:15:23.327081 CLK81: 166.6M
504 22:15:23.327526 smccc: 00012a92
505 22:15:23.331745 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 22:15:23.337310 board id: 1
507 22:15:23.343227 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 22:15:23.353921 fw parse done
509 22:15:23.359865 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 22:15:23.402515 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 22:15:23.413412 PIEI prepare done
512 22:15:23.413949 fastboot data load
513 22:15:23.414413 fastboot data verify
514 22:15:23.419138 verify result: 266
515 22:15:23.424658 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 22:15:23.425162 LPDDR4 probe
517 22:15:23.425615 ddr clk to 1584MHz
518 22:15:23.432635 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 22:15:23.469851
520 22:15:23.470431 dmc_version 0001
521 22:15:23.476572 Check phy result
522 22:15:23.482460 INFO : End of CA training
523 22:15:23.482956 INFO : End of initialization
524 22:15:23.488070 INFO : Training has run successfully!
525 22:15:23.488568 Check phy result
526 22:15:23.493624 INFO : End of initialization
527 22:15:23.494155 INFO : End of read enable training
528 22:15:23.499295 INFO : End of fine write leveling
529 22:15:23.504813 INFO : End of Write leveling coarse delay
530 22:15:23.505335 INFO : Training has run successfully!
531 22:15:23.505797 Check phy result
532 22:15:23.510421 INFO : End of initialization
533 22:15:23.510922 INFO : End of read dq deskew training
534 22:15:23.516053 INFO : End of MPR read delay center optimization
535 22:15:23.521586 INFO : End of write delay center optimization
536 22:15:23.527197 INFO : End of read delay center optimization
537 22:15:23.527701 INFO : End of max read latency training
538 22:15:23.532856 INFO : Training has run successfully!
539 22:15:23.533362 1D training succeed
540 22:15:23.542000 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 22:15:23.589617 Check phy result
542 22:15:23.590206 INFO : End of initialization
543 22:15:23.611278 INFO : End of 2D read delay Voltage center optimization
544 22:15:23.631354 INFO : End of 2D read delay Voltage center optimization
545 22:15:23.683327 INFO : End of 2D write delay Voltage center optimization
546 22:15:23.732432 INFO : End of 2D write delay Voltage center optimization
547 22:15:23.738083 INFO : Training has run successfully!
548 22:15:23.738573
549 22:15:23.739030 channel==0
550 22:15:23.743657 RxClkDly_Margin_A0==88 ps 9
551 22:15:23.744221 TxDqDly_Margin_A0==98 ps 10
552 22:15:23.749205 RxClkDly_Margin_A1==88 ps 9
553 22:15:23.749694 TxDqDly_Margin_A1==88 ps 9
554 22:15:23.750151 TrainedVREFDQ_A0==74
555 22:15:23.754818 TrainedVREFDQ_A1==74
556 22:15:23.755321 VrefDac_Margin_A0==25
557 22:15:23.755774 DeviceVref_Margin_A0==40
558 22:15:23.760410 VrefDac_Margin_A1==25
559 22:15:23.760892 DeviceVref_Margin_A1==40
560 22:15:23.761342
561 22:15:23.761782
562 22:15:23.762217 channel==1
563 22:15:23.766070 RxClkDly_Margin_A0==98 ps 10
564 22:15:23.766545 TxDqDly_Margin_A0==88 ps 9
565 22:15:23.771606 RxClkDly_Margin_A1==88 ps 9
566 22:15:23.772127 TxDqDly_Margin_A1==98 ps 10
567 22:15:23.777229 TrainedVREFDQ_A0==77
568 22:15:23.777718 TrainedVREFDQ_A1==78
569 22:15:23.778172 VrefDac_Margin_A0==22
570 22:15:23.782828 DeviceVref_Margin_A0==37
571 22:15:23.783312 VrefDac_Margin_A1==24
572 22:15:23.788403 DeviceVref_Margin_A1==36
573 22:15:23.788886
574 22:15:23.789339 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 22:15:23.789784
576 22:15:23.822078 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
577 22:15:23.822608 2D training succeed
578 22:15:23.827626 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 22:15:23.833208 auto size-- 65535DDR cs0 size: 2048MB
580 22:15:23.833707 DDR cs1 size: 2048MB
581 22:15:23.838803 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 22:15:23.839320 cs0 DataBus test pass
583 22:15:23.844370 cs1 DataBus test pass
584 22:15:23.844854 cs0 AddrBus test pass
585 22:15:23.845299 cs1 AddrBus test pass
586 22:15:23.845736
587 22:15:23.850074 100bdlr_step_size ps== 420
588 22:15:23.850577 result report
589 22:15:23.855614 boot times 0Enable ddr reg access
590 22:15:23.860884 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 22:15:23.874305 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 22:15:24.446445 0.0;M3 CHK:0;cm4_sp_mode 0
593 22:15:24.447098 MVN_1=0x00000000
594 22:15:24.451882 MVN_2=0x00000000
595 22:15:24.457636 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 22:15:24.458190 OPS=0x10
597 22:15:24.458665 ring efuse init
598 22:15:24.459127 chipver efuse init
599 22:15:24.465790 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 22:15:24.466346 [0.018961 Inits done]
601 22:15:24.473421 secure task start!
602 22:15:24.473925 high task start!
603 22:15:24.474356 low task start!
604 22:15:24.474783 run into bl31
605 22:15:24.480036 NOTICE: BL31: v1.3(release):4fc40b1
606 22:15:24.487851 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 22:15:24.488387 NOTICE: BL31: G12A normal boot!
608 22:15:24.513303 NOTICE: BL31: BL33 decompress pass
609 22:15:24.518891 ERROR: Error initializing runtime service opteed_fast
610 22:15:25.751916
611 22:15:25.752605
612 22:15:25.761964 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 22:15:25.762473
614 22:15:25.762929 Model: Libre Computer AML-A311D-CC Alta
615 22:15:25.968831 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 22:15:25.992182 DRAM: 2 GiB (effective 3.8 GiB)
617 22:15:26.135219 Core: 408 devices, 31 uclasses, devicetree: separate
618 22:15:26.141109 WDT: Not starting watchdog@f0d0
619 22:15:26.173213 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 22:15:26.185628 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 22:15:26.190786 ** Bad device specification mmc 0 **
622 22:15:26.200992 Card did not respond to voltage select! : -110
623 22:15:26.208777 ** Bad device specification mmc 0 **
624 22:15:26.209282 Couldn't find partition mmc 0
625 22:15:26.217002 Card did not respond to voltage select! : -110
626 22:15:26.222485 ** Bad device specification mmc 0 **
627 22:15:26.222984 Couldn't find partition mmc 0
628 22:15:26.227648 Error: could not access storage.
629 22:15:26.570050 Net: eth0: ethernet@ff3f0000
630 22:15:26.570710 starting USB...
631 22:15:26.821842 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 22:15:26.822702 Starting the controller
633 22:15:26.828587 USB XHCI 1.10
634 22:15:28.543085 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 22:15:28.543765 bl2_stage_init 0x01
636 22:15:28.544283 bl2_stage_init 0x81
637 22:15:28.548737 hw id: 0x0000 - pwm id 0x01
638 22:15:28.549285 bl2_stage_init 0xc1
639 22:15:28.549746 bl2_stage_init 0x02
640 22:15:28.550195
641 22:15:28.554622 L0:00000000
642 22:15:28.555142 L1:20000703
643 22:15:28.555596 L2:00008067
644 22:15:28.556077 L3:14000000
645 22:15:28.560029 B2:00402000
646 22:15:28.560543 B1:e0f83180
647 22:15:28.560994
648 22:15:28.561481 TE: 58159
649 22:15:28.561939
650 22:15:28.565412 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 22:15:28.565933
652 22:15:28.566391 Board ID = 1
653 22:15:28.571102 Set A53 clk to 24M
654 22:15:28.571617 Set A73 clk to 24M
655 22:15:28.572104 Set clk81 to 24M
656 22:15:28.576694 A53 clk: 1200 MHz
657 22:15:28.577220 A73 clk: 1200 MHz
658 22:15:28.577673 CLK81: 166.6M
659 22:15:28.578109 smccc: 00012ab5
660 22:15:28.582451 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 22:15:28.587975 board id: 1
662 22:15:28.592721 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 22:15:28.604366 fw parse done
664 22:15:28.609622 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 22:15:28.653026 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 22:15:28.663873 PIEI prepare done
667 22:15:28.664420 fastboot data load
668 22:15:28.664881 fastboot data verify
669 22:15:28.669452 verify result: 266
670 22:15:28.675071 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 22:15:28.675572 LPDDR4 probe
672 22:15:28.676061 ddr clk to 1584MHz
673 22:15:28.682230 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 22:15:28.719927
675 22:15:28.720495 dmc_version 0001
676 22:15:28.726332 Check phy result
677 22:15:28.732905 INFO : End of CA training
678 22:15:28.733434 INFO : End of initialization
679 22:15:28.738458 INFO : Training has run successfully!
680 22:15:28.738962 Check phy result
681 22:15:28.744124 INFO : End of initialization
682 22:15:28.744631 INFO : End of read enable training
683 22:15:28.749560 INFO : End of fine write leveling
684 22:15:28.755218 INFO : End of Write leveling coarse delay
685 22:15:28.755724 INFO : Training has run successfully!
686 22:15:28.756222 Check phy result
687 22:15:28.760837 INFO : End of initialization
688 22:15:28.761342 INFO : End of read dq deskew training
689 22:15:28.766442 INFO : End of MPR read delay center optimization
690 22:15:28.771947 INFO : End of write delay center optimization
691 22:15:28.777602 INFO : End of read delay center optimization
692 22:15:28.778098 INFO : End of max read latency training
693 22:15:28.783246 INFO : Training has run successfully!
694 22:15:28.783746 1D training succeed
695 22:15:28.791852 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 22:15:28.839140 Check phy result
697 22:15:28.839664 INFO : End of initialization
698 22:15:28.860817 INFO : End of 2D read delay Voltage center optimization
699 22:15:28.881194 INFO : End of 2D read delay Voltage center optimization
700 22:15:28.933309 INFO : End of 2D write delay Voltage center optimization
701 22:15:28.983369 INFO : End of 2D write delay Voltage center optimization
702 22:15:28.989019 INFO : Training has run successfully!
703 22:15:28.989520
704 22:15:28.989977 channel==0
705 22:15:28.994577 RxClkDly_Margin_A0==88 ps 9
706 22:15:28.995094 TxDqDly_Margin_A0==98 ps 10
707 22:15:29.000290 RxClkDly_Margin_A1==88 ps 9
708 22:15:29.000801 TxDqDly_Margin_A1==88 ps 9
709 22:15:29.001255 TrainedVREFDQ_A0==74
710 22:15:29.005792 TrainedVREFDQ_A1==74
711 22:15:29.006321 VrefDac_Margin_A0==25
712 22:15:29.006787 DeviceVref_Margin_A0==40
713 22:15:29.011405 VrefDac_Margin_A1==25
714 22:15:29.011915 DeviceVref_Margin_A1==40
715 22:15:29.012419
716 22:15:29.012876
717 22:15:29.013322 channel==1
718 22:15:29.017039 RxClkDly_Margin_A0==98 ps 10
719 22:15:29.017550 TxDqDly_Margin_A0==98 ps 10
720 22:15:29.022478 RxClkDly_Margin_A1==88 ps 9
721 22:15:29.022987 TxDqDly_Margin_A1==88 ps 9
722 22:15:29.028227 TrainedVREFDQ_A0==77
723 22:15:29.028751 TrainedVREFDQ_A1==77
724 22:15:29.029207 VrefDac_Margin_A0==22
725 22:15:29.033782 DeviceVref_Margin_A0==37
726 22:15:29.034305 VrefDac_Margin_A1==24
727 22:15:29.039437 DeviceVref_Margin_A1==37
728 22:15:29.039950
729 22:15:29.040448 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 22:15:29.040896
731 22:15:29.073017 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
732 22:15:29.073621 2D training succeed
733 22:15:29.078572 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 22:15:29.084130 auto size-- 65535DDR cs0 size: 2048MB
735 22:15:29.084649 DDR cs1 size: 2048MB
736 22:15:29.089772 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 22:15:29.090281 cs0 DataBus test pass
738 22:15:29.095373 cs1 DataBus test pass
739 22:15:29.095878 cs0 AddrBus test pass
740 22:15:29.096372 cs1 AddrBus test pass
741 22:15:29.096825
742 22:15:29.101025 100bdlr_step_size ps== 420
743 22:15:29.101538 result report
744 22:15:29.106501 boot times 0Enable ddr reg access
745 22:15:29.111009 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 22:15:29.125291 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 22:15:29.698925 0.0;M3 CHK:0;cm4_sp_mode 0
748 22:15:29.699561 MVN_1=0x00000000
749 22:15:29.704462 MVN_2=0x00000000
750 22:15:29.710245 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 22:15:29.710783 OPS=0x10
752 22:15:29.711222 ring efuse init
753 22:15:29.711651 chipver efuse init
754 22:15:29.715816 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 22:15:29.721347 [0.018960 Inits done]
756 22:15:29.721853 secure task start!
757 22:15:29.722287 high task start!
758 22:15:29.726039 low task start!
759 22:15:29.726523 run into bl31
760 22:15:29.732602 NOTICE: BL31: v1.3(release):4fc40b1
761 22:15:29.740485 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 22:15:29.741001 NOTICE: BL31: G12A normal boot!
763 22:15:29.765735 NOTICE: BL31: BL33 decompress pass
764 22:15:29.771338 ERROR: Error initializing runtime service opteed_fast
765 22:15:31.004290
766 22:15:31.004939
767 22:15:31.012734 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 22:15:31.013255
769 22:15:31.013713 Model: Libre Computer AML-A311D-CC Alta
770 22:15:31.221178 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 22:15:31.244515 DRAM: 2 GiB (effective 3.8 GiB)
772 22:15:31.387481 Core: 408 devices, 31 uclasses, devicetree: separate
773 22:15:31.392500 WDT: Not starting watchdog@f0d0
774 22:15:31.425623 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 22:15:31.438189 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 22:15:31.443203 ** Bad device specification mmc 0 **
777 22:15:31.453503 Card did not respond to voltage select! : -110
778 22:15:31.461108 ** Bad device specification mmc 0 **
779 22:15:31.461629 Couldn't find partition mmc 0
780 22:15:31.469430 Card did not respond to voltage select! : -110
781 22:15:31.474967 ** Bad device specification mmc 0 **
782 22:15:31.475470 Couldn't find partition mmc 0
783 22:15:31.480007 Error: could not access storage.
784 22:15:31.822622 Net: eth0: ethernet@ff3f0000
785 22:15:31.823254 starting USB...
786 22:15:32.075460 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 22:15:32.076157 Starting the controller
788 22:15:32.082439 USB XHCI 1.10
789 22:15:34.244644 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 22:15:34.245288 bl2_stage_init 0x01
791 22:15:34.245787 bl2_stage_init 0x81
792 22:15:34.250344 hw id: 0x0000 - pwm id 0x01
793 22:15:34.250858 bl2_stage_init 0xc1
794 22:15:34.251317 bl2_stage_init 0x02
795 22:15:34.251765
796 22:15:34.255791 L0:00000000
797 22:15:34.256331 L1:20000703
798 22:15:34.256785 L2:00008067
799 22:15:34.257223 L3:14000000
800 22:15:34.261415 B2:00402000
801 22:15:34.261914 B1:e0f83180
802 22:15:34.262365
803 22:15:34.262812 TE: 58124
804 22:15:34.263256
805 22:15:34.266988 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 22:15:34.267494
807 22:15:34.267949 Board ID = 1
808 22:15:34.272660 Set A53 clk to 24M
809 22:15:34.273165 Set A73 clk to 24M
810 22:15:34.273617 Set clk81 to 24M
811 22:15:34.278108 A53 clk: 1200 MHz
812 22:15:34.278614 A73 clk: 1200 MHz
813 22:15:34.279064 CLK81: 166.6M
814 22:15:34.279505 smccc: 00012a92
815 22:15:34.283833 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 22:15:34.289322 board id: 1
817 22:15:34.295067 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 22:15:34.305750 fw parse done
819 22:15:34.311718 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 22:15:34.354346 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 22:15:34.365313 PIEI prepare done
822 22:15:34.365836 fastboot data load
823 22:15:34.366294 fastboot data verify
824 22:15:34.371023 verify result: 266
825 22:15:34.376580 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 22:15:34.377118 LPDDR4 probe
827 22:15:34.377571 ddr clk to 1584MHz
828 22:15:34.384130 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 22:15:34.421797
830 22:15:34.422389 dmc_version 0001
831 22:15:34.427531 Check phy result
832 22:15:34.434289 INFO : End of CA training
833 22:15:34.434835 INFO : End of initialization
834 22:15:34.439963 INFO : Training has run successfully!
835 22:15:34.440504 Check phy result
836 22:15:34.445543 INFO : End of initialization
837 22:15:34.446083 INFO : End of read enable training
838 22:15:34.451171 INFO : End of fine write leveling
839 22:15:34.456751 INFO : End of Write leveling coarse delay
840 22:15:34.457274 INFO : Training has run successfully!
841 22:15:34.457724 Check phy result
842 22:15:34.462394 INFO : End of initialization
843 22:15:34.462908 INFO : End of read dq deskew training
844 22:15:34.467944 INFO : End of MPR read delay center optimization
845 22:15:34.473653 INFO : End of write delay center optimization
846 22:15:34.479101 INFO : End of read delay center optimization
847 22:15:34.479626 INFO : End of max read latency training
848 22:15:34.484741 INFO : Training has run successfully!
849 22:15:34.485264 1D training succeed
850 22:15:34.492985 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 22:15:34.541245 Check phy result
852 22:15:34.541838 INFO : End of initialization
853 22:15:34.563184 INFO : End of 2D read delay Voltage center optimization
854 22:15:34.583237 INFO : End of 2D read delay Voltage center optimization
855 22:15:34.635165 INFO : End of 2D write delay Voltage center optimization
856 22:15:34.684390 INFO : End of 2D write delay Voltage center optimization
857 22:15:34.689986 INFO : Training has run successfully!
858 22:15:34.690515
859 22:15:34.690980 channel==0
860 22:15:34.695542 RxClkDly_Margin_A0==88 ps 9
861 22:15:34.696121 TxDqDly_Margin_A0==98 ps 10
862 22:15:34.701175 RxClkDly_Margin_A1==88 ps 9
863 22:15:34.701688 TxDqDly_Margin_A1==98 ps 10
864 22:15:34.702159 TrainedVREFDQ_A0==74
865 22:15:34.706861 TrainedVREFDQ_A1==74
866 22:15:34.707402 VrefDac_Margin_A0==25
867 22:15:34.707855 DeviceVref_Margin_A0==40
868 22:15:34.712383 VrefDac_Margin_A1==25
869 22:15:34.712916 DeviceVref_Margin_A1==40
870 22:15:34.713342
871 22:15:34.713765
872 22:15:34.717983 channel==1
873 22:15:34.718491 RxClkDly_Margin_A0==98 ps 10
874 22:15:34.718924 TxDqDly_Margin_A0==88 ps 9
875 22:15:34.723553 RxClkDly_Margin_A1==98 ps 10
876 22:15:34.724090 TxDqDly_Margin_A1==88 ps 9
877 22:15:34.729140 TrainedVREFDQ_A0==77
878 22:15:34.729656 TrainedVREFDQ_A1==77
879 22:15:34.730088 VrefDac_Margin_A0==22
880 22:15:34.734787 DeviceVref_Margin_A0==37
881 22:15:34.735286 VrefDac_Margin_A1==24
882 22:15:34.740347 DeviceVref_Margin_A1==37
883 22:15:34.740844
884 22:15:34.741279 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 22:15:34.741705
886 22:15:34.773917 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
887 22:15:34.774540 2D training succeed
888 22:15:34.779553 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 22:15:34.785151 auto size-- 65535DDR cs0 size: 2048MB
890 22:15:34.785654 DDR cs1 size: 2048MB
891 22:15:34.790819 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 22:15:34.791323 cs0 DataBus test pass
893 22:15:34.796345 cs1 DataBus test pass
894 22:15:34.796849 cs0 AddrBus test pass
895 22:15:34.797278 cs1 AddrBus test pass
896 22:15:34.797704
897 22:15:34.801923 100bdlr_step_size ps== 420
898 22:15:34.802436 result report
899 22:15:34.807562 boot times 0Enable ddr reg access
900 22:15:34.812926 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 22:15:34.826293 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 22:15:35.398265 0.0;M3 CHK:0;cm4_sp_mode 0
903 22:15:35.398915 MVN_1=0x00000000
904 22:15:35.403826 MVN_2=0x00000000
905 22:15:35.409566 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 22:15:35.410091 OPS=0x10
907 22:15:35.410545 ring efuse init
908 22:15:35.410990 chipver efuse init
909 22:15:35.415203 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 22:15:35.420824 [0.018961 Inits done]
911 22:15:35.421350 secure task start!
912 22:15:35.421802 high task start!
913 22:15:35.425359 low task start!
914 22:15:35.425870 run into bl31
915 22:15:35.432057 NOTICE: BL31: v1.3(release):4fc40b1
916 22:15:35.439848 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 22:15:35.440388 NOTICE: BL31: G12A normal boot!
918 22:15:35.465255 NOTICE: BL31: BL33 decompress pass
919 22:15:35.470893 ERROR: Error initializing runtime service opteed_fast
920 22:15:36.703771
921 22:15:36.704469
922 22:15:36.712121 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 22:15:36.712637
924 22:15:36.713102 Model: Libre Computer AML-A311D-CC Alta
925 22:15:36.920592 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 22:15:36.944032 DRAM: 2 GiB (effective 3.8 GiB)
927 22:15:37.086926 Core: 408 devices, 31 uclasses, devicetree: separate
928 22:15:37.092827 WDT: Not starting watchdog@f0d0
929 22:15:37.125098 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 22:15:37.137472 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 22:15:37.142554 ** Bad device specification mmc 0 **
932 22:15:37.152934 Card did not respond to voltage select! : -110
933 22:15:37.160547 ** Bad device specification mmc 0 **
934 22:15:37.161124 Couldn't find partition mmc 0
935 22:15:37.168881 Card did not respond to voltage select! : -110
936 22:15:37.174398 ** Bad device specification mmc 0 **
937 22:15:37.174973 Couldn't find partition mmc 0
938 22:15:37.179449 Error: could not access storage.
939 22:15:37.522863 Net: eth0: ethernet@ff3f0000
940 22:15:37.523499 starting USB...
941 22:15:37.774759 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 22:15:37.775347 Starting the controller
943 22:15:37.781674 USB XHCI 1.10
944 22:15:39.336165 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 22:15:39.344251 scanning usb for storage devices... 0 Storage Device(s) found
947 22:15:39.395696 Hit any key to stop autoboot: 1
948 22:15:39.396680 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
949 22:15:39.397388 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
950 22:15:39.397931 Setting prompt string to ['=>']
951 22:15:39.398470 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
952 22:15:39.411889 0
953 22:15:39.412934 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 22:15:39.413512 Sending with 10 millisecond of delay
956 22:15:40.548679 => setenv autoload no
957 22:15:40.559313 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
958 22:15:40.562021 setenv autoload no
959 22:15:40.562544 Sending with 10 millisecond of delay
961 22:15:42.365388 => setenv initrd_high 0xffffffff
962 22:15:42.376154 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
963 22:15:42.376998 setenv initrd_high 0xffffffff
964 22:15:42.377706 Sending with 10 millisecond of delay
966 22:15:43.993755 => setenv fdt_high 0xffffffff
967 22:15:44.004529 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
968 22:15:44.005328 setenv fdt_high 0xffffffff
969 22:15:44.006026 Sending with 10 millisecond of delay
971 22:15:44.298157 => dhcp
972 22:15:44.308733 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
973 22:15:44.309286 dhcp
974 22:15:44.309541 Speed: 1000, full duplex
975 22:15:44.309769 BOOTP broadcast 1
976 22:15:44.330850 DHCP client bound to address 192.168.6.27 (22 ms)
977 22:15:44.331574 Sending with 10 millisecond of delay
979 22:15:46.008398 => setenv serverip 192.168.6.2
980 22:15:46.019266 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
981 22:15:46.020321 setenv serverip 192.168.6.2
982 22:15:46.021075 Sending with 10 millisecond of delay
984 22:15:49.750633 => tftpboot 0x01080000 963111/tftp-deploy-_52k09kn/kernel/uImage
985 22:15:49.761411 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
986 22:15:49.762252 tftpboot 0x01080000 963111/tftp-deploy-_52k09kn/kernel/uImage
987 22:15:49.762715 Speed: 1000, full duplex
988 22:15:49.763134 Using ethernet@ff3f0000 device
989 22:15:49.764214 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
990 22:15:49.769651 Filename '963111/tftp-deploy-_52k09kn/kernel/uImage'.
991 22:15:49.773477 Load address: 0x1080000
992 22:15:52.477505 Loading: *################################################## 37.6 MiB
993 22:15:52.478119 13.9 MiB/s
994 22:15:52.478541 done
995 22:15:52.481907 Bytes transferred = 39424576 (2599240 hex)
996 22:15:52.482704 Sending with 10 millisecond of delay
998 22:15:57.170353 => tftpboot 0x08000000 963111/tftp-deploy-_52k09kn/ramdisk/ramdisk.cpio.gz.uboot
999 22:15:57.181091 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1000 22:15:57.181609 tftpboot 0x08000000 963111/tftp-deploy-_52k09kn/ramdisk/ramdisk.cpio.gz.uboot
1001 22:15:57.181849 Speed: 1000, full duplex
1002 22:15:57.182058 Using ethernet@ff3f0000 device
1003 22:15:57.183629 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1004 22:15:57.192337 Filename '963111/tftp-deploy-_52k09kn/ramdisk/ramdisk.cpio.gz.uboot'.
1005 22:15:57.192761 Load address: 0x8000000
1006 22:16:04.052218 Loading: *#####################T ############################ UDP wrong checksum 00000005 00009f0d
1007 22:16:09.052628 T UDP wrong checksum 00000005 00009f0d
1008 22:16:19.055106 T T UDP wrong checksum 00000005 00009f0d
1009 22:16:39.059015 T T T T UDP wrong checksum 00000005 00009f0d
1010 22:16:54.065344 T T
1011 22:16:54.066015 Retry count exceeded; starting again
1013 22:16:54.067564 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1016 22:16:54.069729 end: 2.4 uboot-commands (duration 00:01:47) [common]
1018 22:16:54.071241 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1020 22:16:54.072296 end: 2 uboot-action (duration 00:01:47) [common]
1022 22:16:54.073208 Cleaning after the job
1023 22:16:54.073815 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/ramdisk
1024 22:16:54.075304 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/kernel
1025 22:16:54.082464 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/dtb
1026 22:16:54.083719 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/nfsrootfs
1027 22:16:54.127004 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963111/tftp-deploy-_52k09kn/modules
1028 22:16:54.134466 start: 4.1 power-off (timeout 00:00:30) [common]
1029 22:16:54.135552 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1030 22:16:54.173718 >> OK - accepted request
1031 22:16:54.176232 Returned 0 in 0 seconds
1032 22:16:54.277439 end: 4.1 power-off (duration 00:00:00) [common]
1034 22:16:54.279168 start: 4.2 read-feedback (timeout 00:10:00) [common]
1035 22:16:54.280338 Listened to connection for namespace 'common' for up to 1s
1036 22:16:55.280152 Finalising connection for namespace 'common'
1037 22:16:55.280931 Disconnecting from shell: Finalise
1038 22:16:55.281470 =>
1039 22:16:55.382540 end: 4.2 read-feedback (duration 00:00:01) [common]
1040 22:16:55.383217 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/963111
1041 22:16:57.062146 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/963111
1042 22:16:57.062762 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.