Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:52:07.504961 lava-dispatcher, installed at version: 2024.01
2 22:52:07.505724 start: 0 validate
3 22:52:07.506199 Start time: 2024-11-08 22:52:07.506169+00:00 (UTC)
4 22:52:07.506747 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:52:07.507286 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:52:07.550779 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:52:07.551465 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 22:52:07.585268 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:52:07.586032 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 22:52:07.619395 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:52:07.620185 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:52:07.653105 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 22:52:07.653586 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 22:52:07.692858 validate duration: 0.19
16 22:52:07.693719 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:52:07.694060 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:52:07.694394 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:52:07.694994 Not decompressing ramdisk as can be used compressed.
20 22:52:07.695464 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 22:52:07.695763 saving as /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/ramdisk/initrd.cpio.gz
22 22:52:07.696081 total size: 5628169 (5 MB)
23 22:52:07.733920 progress 0 % (0 MB)
24 22:52:07.741522 progress 5 % (0 MB)
25 22:52:07.746101 progress 10 % (0 MB)
26 22:52:07.750105 progress 15 % (0 MB)
27 22:52:07.754594 progress 20 % (1 MB)
28 22:52:07.758655 progress 25 % (1 MB)
29 22:52:07.763151 progress 30 % (1 MB)
30 22:52:07.767545 progress 35 % (1 MB)
31 22:52:07.771539 progress 40 % (2 MB)
32 22:52:07.775975 progress 45 % (2 MB)
33 22:52:07.779947 progress 50 % (2 MB)
34 22:52:07.784392 progress 55 % (2 MB)
35 22:52:07.788834 progress 60 % (3 MB)
36 22:52:07.792766 progress 65 % (3 MB)
37 22:52:07.797299 progress 70 % (3 MB)
38 22:52:07.801292 progress 75 % (4 MB)
39 22:52:07.805711 progress 80 % (4 MB)
40 22:52:07.809649 progress 85 % (4 MB)
41 22:52:07.813715 progress 90 % (4 MB)
42 22:52:07.817764 progress 95 % (5 MB)
43 22:52:07.821419 progress 100 % (5 MB)
44 22:52:07.822180 5 MB downloaded in 0.13 s (42.57 MB/s)
45 22:52:07.822845 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:52:07.823924 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:52:07.824349 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:52:07.824721 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:52:07.825322 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm64/defconfig/gcc-12/kernel/Image
51 22:52:07.825618 saving as /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/kernel/Image
52 22:52:07.825905 total size: 45713920 (43 MB)
53 22:52:07.826170 No compression specified
54 22:52:07.866020 progress 0 % (0 MB)
55 22:52:07.896849 progress 5 % (2 MB)
56 22:52:07.927747 progress 10 % (4 MB)
57 22:52:07.958515 progress 15 % (6 MB)
58 22:52:07.989433 progress 20 % (8 MB)
59 22:52:08.019851 progress 25 % (10 MB)
60 22:52:08.050533 progress 30 % (13 MB)
61 22:52:08.081353 progress 35 % (15 MB)
62 22:52:08.112043 progress 40 % (17 MB)
63 22:52:08.142360 progress 45 % (19 MB)
64 22:52:08.173200 progress 50 % (21 MB)
65 22:52:08.204016 progress 55 % (24 MB)
66 22:52:08.234564 progress 60 % (26 MB)
67 22:52:08.265223 progress 65 % (28 MB)
68 22:52:08.296120 progress 70 % (30 MB)
69 22:52:08.327005 progress 75 % (32 MB)
70 22:52:08.357840 progress 80 % (34 MB)
71 22:52:08.388310 progress 85 % (37 MB)
72 22:52:08.419283 progress 90 % (39 MB)
73 22:52:08.450263 progress 95 % (41 MB)
74 22:52:08.480046 progress 100 % (43 MB)
75 22:52:08.480651 43 MB downloaded in 0.65 s (66.59 MB/s)
76 22:52:08.481229 end: 1.2.1 http-download (duration 00:00:01) [common]
78 22:52:08.482208 end: 1.2 download-retry (duration 00:00:01) [common]
79 22:52:08.482581 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:52:08.482927 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:52:08.483467 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 22:52:08.483814 saving as /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/dtb/meson-g12b-a311d-libretech-cc.dtb
83 22:52:08.484115 total size: 54703 (0 MB)
84 22:52:08.484357 No compression specified
85 22:52:08.524241 progress 59 % (0 MB)
86 22:52:08.525195 progress 100 % (0 MB)
87 22:52:08.525878 0 MB downloaded in 0.04 s (1.25 MB/s)
88 22:52:08.526457 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:52:08.527466 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:52:08.527804 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:52:08.528139 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:52:08.528721 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 22:52:08.529002 saving as /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/nfsrootfs/full.rootfs.tar
95 22:52:08.529279 total size: 120894716 (115 MB)
96 22:52:08.529555 Using unxz to decompress xz
97 22:52:08.569420 progress 0 % (0 MB)
98 22:52:09.353548 progress 5 % (5 MB)
99 22:52:10.189359 progress 10 % (11 MB)
100 22:52:10.991610 progress 15 % (17 MB)
101 22:52:11.723688 progress 20 % (23 MB)
102 22:52:12.316833 progress 25 % (28 MB)
103 22:52:13.137209 progress 30 % (34 MB)
104 22:52:13.922694 progress 35 % (40 MB)
105 22:52:14.282044 progress 40 % (46 MB)
106 22:52:14.659581 progress 45 % (51 MB)
107 22:52:15.378092 progress 50 % (57 MB)
108 22:52:16.273036 progress 55 % (63 MB)
109 22:52:17.049954 progress 60 % (69 MB)
110 22:52:17.800573 progress 65 % (74 MB)
111 22:52:18.570950 progress 70 % (80 MB)
112 22:52:19.387382 progress 75 % (86 MB)
113 22:52:20.166599 progress 80 % (92 MB)
114 22:52:20.919686 progress 85 % (98 MB)
115 22:52:21.772949 progress 90 % (103 MB)
116 22:52:22.545465 progress 95 % (109 MB)
117 22:52:23.384249 progress 100 % (115 MB)
118 22:52:23.396759 115 MB downloaded in 14.87 s (7.75 MB/s)
119 22:52:23.397615 end: 1.4.1 http-download (duration 00:00:15) [common]
121 22:52:23.399178 end: 1.4 download-retry (duration 00:00:15) [common]
122 22:52:23.399688 start: 1.5 download-retry (timeout 00:09:44) [common]
123 22:52:23.400256 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 22:52:23.401021 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm64/defconfig/gcc-12/modules.tar.xz
125 22:52:23.401471 saving as /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/modules/modules.tar
126 22:52:23.401872 total size: 11613560 (11 MB)
127 22:52:23.402280 Using unxz to decompress xz
128 22:52:23.447678 progress 0 % (0 MB)
129 22:52:23.525776 progress 5 % (0 MB)
130 22:52:23.614313 progress 10 % (1 MB)
131 22:52:23.727831 progress 15 % (1 MB)
132 22:52:23.836475 progress 20 % (2 MB)
133 22:52:23.929538 progress 25 % (2 MB)
134 22:52:24.018297 progress 30 % (3 MB)
135 22:52:24.110468 progress 35 % (3 MB)
136 22:52:24.193758 progress 40 % (4 MB)
137 22:52:24.268161 progress 45 % (5 MB)
138 22:52:24.351001 progress 50 % (5 MB)
139 22:52:24.427236 progress 55 % (6 MB)
140 22:52:24.511299 progress 60 % (6 MB)
141 22:52:24.591168 progress 65 % (7 MB)
142 22:52:24.670430 progress 70 % (7 MB)
143 22:52:24.747540 progress 75 % (8 MB)
144 22:52:24.829841 progress 80 % (8 MB)
145 22:52:24.908564 progress 85 % (9 MB)
146 22:52:24.986053 progress 90 % (9 MB)
147 22:52:25.062915 progress 95 % (10 MB)
148 22:52:25.138772 progress 100 % (11 MB)
149 22:52:25.150500 11 MB downloaded in 1.75 s (6.33 MB/s)
150 22:52:25.151357 end: 1.5.1 http-download (duration 00:00:02) [common]
152 22:52:25.152988 end: 1.5 download-retry (duration 00:00:02) [common]
153 22:52:25.153505 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 22:52:25.154022 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 22:52:41.476807 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/963283/extract-nfsrootfs-6sbu6v3g
156 22:52:41.477414 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 22:52:41.477701 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 22:52:41.478398 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r
159 22:52:41.478850 makedir: /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin
160 22:52:41.479176 makedir: /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/tests
161 22:52:41.479491 makedir: /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/results
162 22:52:41.479827 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-add-keys
163 22:52:41.480411 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-add-sources
164 22:52:41.480949 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-background-process-start
165 22:52:41.481513 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-background-process-stop
166 22:52:41.482058 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-common-functions
167 22:52:41.482562 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-echo-ipv4
168 22:52:41.483049 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-install-packages
169 22:52:41.483528 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-installed-packages
170 22:52:41.484024 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-os-build
171 22:52:41.484535 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-probe-channel
172 22:52:41.485044 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-probe-ip
173 22:52:41.485573 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-target-ip
174 22:52:41.486056 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-target-mac
175 22:52:41.486532 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-target-storage
176 22:52:41.487014 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-test-case
177 22:52:41.487554 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-test-event
178 22:52:41.488061 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-test-feedback
179 22:52:41.488655 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-test-raise
180 22:52:41.489219 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-test-reference
181 22:52:41.489765 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-test-runner
182 22:52:41.490263 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-test-set
183 22:52:41.490742 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-test-shell
184 22:52:41.491231 Updating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-add-keys (debian)
185 22:52:41.491762 Updating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-add-sources (debian)
186 22:52:41.492325 Updating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-install-packages (debian)
187 22:52:41.492838 Updating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-installed-packages (debian)
188 22:52:41.493336 Updating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/bin/lava-os-build (debian)
189 22:52:41.493772 Creating /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/environment
190 22:52:41.494148 LAVA metadata
191 22:52:41.494409 - LAVA_JOB_ID=963283
192 22:52:41.494624 - LAVA_DISPATCHER_IP=192.168.6.2
193 22:52:41.494996 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 22:52:41.495952 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 22:52:41.496289 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 22:52:41.496498 skipped lava-vland-overlay
197 22:52:41.496738 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 22:52:41.496991 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 22:52:41.497208 skipped lava-multinode-overlay
200 22:52:41.497453 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 22:52:41.497703 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 22:52:41.497949 Loading test definitions
203 22:52:41.498228 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 22:52:41.498448 Using /lava-963283 at stage 0
205 22:52:41.499559 uuid=963283_1.6.2.4.1 testdef=None
206 22:52:41.499874 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 22:52:41.500168 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 22:52:41.501756 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 22:52:41.502547 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 22:52:41.504588 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 22:52:41.505419 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 22:52:41.507261 runner path: /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/0/tests/0_timesync-off test_uuid 963283_1.6.2.4.1
215 22:52:41.507823 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 22:52:41.508665 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 22:52:41.508896 Using /lava-963283 at stage 0
219 22:52:41.509257 Fetching tests from https://github.com/kernelci/test-definitions.git
220 22:52:41.509545 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/0/tests/1_kselftest-alsa'
221 22:52:44.902131 Running '/usr/bin/git checkout kernelci.org
222 22:52:45.350254 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 22:52:45.351719 uuid=963283_1.6.2.4.5 testdef=None
224 22:52:45.352114 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 22:52:45.352875 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 22:52:45.355684 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 22:52:45.356518 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 22:52:45.360219 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 22:52:45.361070 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 22:52:45.364612 runner path: /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/0/tests/1_kselftest-alsa test_uuid 963283_1.6.2.4.5
234 22:52:45.364890 BOARD='meson-g12b-a311d-libretech-cc'
235 22:52:45.365094 BRANCH='mainline'
236 22:52:45.365291 SKIPFILE='/dev/null'
237 22:52:45.365488 SKIP_INSTALL='True'
238 22:52:45.365682 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 22:52:45.365881 TST_CASENAME=''
240 22:52:45.366075 TST_CMDFILES='alsa'
241 22:52:45.366610 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 22:52:45.367390 Creating lava-test-runner.conf files
244 22:52:45.367594 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/963283/lava-overlay-n9vjkq3r/lava-963283/0 for stage 0
245 22:52:45.367932 - 0_timesync-off
246 22:52:45.368190 - 1_kselftest-alsa
247 22:52:45.368519 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 22:52:45.368798 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 22:53:08.753287 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 22:53:08.753738 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 22:53:08.754001 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 22:53:08.754272 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 22:53:08.754537 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 22:53:09.410322 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 22:53:09.410823 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 22:53:09.411078 extracting modules file /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/963283/extract-nfsrootfs-6sbu6v3g
257 22:53:10.761187 extracting modules file /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/963283/extract-overlay-ramdisk-l3fiwmlq/ramdisk
258 22:53:12.151835 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 22:53:12.152329 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
260 22:53:12.152608 [common] Applying overlay to NFS
261 22:53:12.152823 [common] Applying overlay /var/lib/lava/dispatcher/tmp/963283/compress-overlay-7m37lg6r/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/963283/extract-nfsrootfs-6sbu6v3g
262 22:53:14.893149 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 22:53:14.893611 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 22:53:14.893883 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 22:53:14.894113 Converting downloaded kernel to a uImage
266 22:53:14.894426 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/kernel/Image /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/kernel/uImage
267 22:53:15.360491 output: Image Name:
268 22:53:15.360916 output: Created: Fri Nov 8 22:53:14 2024
269 22:53:15.361128 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 22:53:15.361334 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 22:53:15.361534 output: Load Address: 01080000
272 22:53:15.361734 output: Entry Point: 01080000
273 22:53:15.361931 output:
274 22:53:15.362266 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 22:53:15.362536 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 22:53:15.362804 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 22:53:15.363055 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 22:53:15.363312 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 22:53:15.363568 Building ramdisk /var/lib/lava/dispatcher/tmp/963283/extract-overlay-ramdisk-l3fiwmlq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/963283/extract-overlay-ramdisk-l3fiwmlq/ramdisk
280 22:53:17.518465 >> 166827 blocks
281 22:53:25.271779 Adding RAMdisk u-boot header.
282 22:53:25.272589 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/963283/extract-overlay-ramdisk-l3fiwmlq/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/963283/extract-overlay-ramdisk-l3fiwmlq/ramdisk.cpio.gz.uboot
283 22:53:25.520024 output: Image Name:
284 22:53:25.520709 output: Created: Fri Nov 8 22:53:25 2024
285 22:53:25.521163 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 22:53:25.521605 output: Data Size: 23435801 Bytes = 22886.52 KiB = 22.35 MiB
287 22:53:25.522044 output: Load Address: 00000000
288 22:53:25.522475 output: Entry Point: 00000000
289 22:53:25.522909 output:
290 22:53:25.524067 rename /var/lib/lava/dispatcher/tmp/963283/extract-overlay-ramdisk-l3fiwmlq/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/ramdisk/ramdisk.cpio.gz.uboot
291 22:53:25.524853 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 22:53:25.525442 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 22:53:25.526020 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 22:53:25.526531 No LXC device requested
295 22:53:25.527076 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 22:53:25.527634 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 22:53:25.528209 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 22:53:25.528662 Checking files for TFTP limit of 4294967296 bytes.
299 22:53:25.531568 end: 1 tftp-deploy (duration 00:01:18) [common]
300 22:53:25.532235 start: 2 uboot-action (timeout 00:05:00) [common]
301 22:53:25.532815 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 22:53:25.533364 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 22:53:25.533913 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 22:53:25.534488 Using kernel file from prepare-kernel: 963283/tftp-deploy-7il2elk9/kernel/uImage
305 22:53:25.535172 substitutions:
306 22:53:25.535619 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 22:53:25.536094 - {DTB_ADDR}: 0x01070000
308 22:53:25.536538 - {DTB}: 963283/tftp-deploy-7il2elk9/dtb/meson-g12b-a311d-libretech-cc.dtb
309 22:53:25.536981 - {INITRD}: 963283/tftp-deploy-7il2elk9/ramdisk/ramdisk.cpio.gz.uboot
310 22:53:25.537420 - {KERNEL_ADDR}: 0x01080000
311 22:53:25.537853 - {KERNEL}: 963283/tftp-deploy-7il2elk9/kernel/uImage
312 22:53:25.538287 - {LAVA_MAC}: None
313 22:53:25.538757 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/963283/extract-nfsrootfs-6sbu6v3g
314 22:53:25.539194 - {NFS_SERVER_IP}: 192.168.6.2
315 22:53:25.539626 - {PRESEED_CONFIG}: None
316 22:53:25.540075 - {PRESEED_LOCAL}: None
317 22:53:25.540507 - {RAMDISK_ADDR}: 0x08000000
318 22:53:25.540929 - {RAMDISK}: 963283/tftp-deploy-7il2elk9/ramdisk/ramdisk.cpio.gz.uboot
319 22:53:25.541353 - {ROOT_PART}: None
320 22:53:25.541774 - {ROOT}: None
321 22:53:25.542195 - {SERVER_IP}: 192.168.6.2
322 22:53:25.542617 - {TEE_ADDR}: 0x83000000
323 22:53:25.543038 - {TEE}: None
324 22:53:25.543456 Parsed boot commands:
325 22:53:25.543866 - setenv autoload no
326 22:53:25.544317 - setenv initrd_high 0xffffffff
327 22:53:25.544740 - setenv fdt_high 0xffffffff
328 22:53:25.545160 - dhcp
329 22:53:25.545577 - setenv serverip 192.168.6.2
330 22:53:25.545999 - tftpboot 0x01080000 963283/tftp-deploy-7il2elk9/kernel/uImage
331 22:53:25.546425 - tftpboot 0x08000000 963283/tftp-deploy-7il2elk9/ramdisk/ramdisk.cpio.gz.uboot
332 22:53:25.546850 - tftpboot 0x01070000 963283/tftp-deploy-7il2elk9/dtb/meson-g12b-a311d-libretech-cc.dtb
333 22:53:25.547276 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/963283/extract-nfsrootfs-6sbu6v3g,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 22:53:25.547711 - bootm 0x01080000 0x08000000 0x01070000
335 22:53:25.548279 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 22:53:25.549892 start: 2.3 connect-device (timeout 00:05:00) [common]
338 22:53:25.550345 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 22:53:25.566045 Setting prompt string to ['lava-test: # ']
340 22:53:25.567713 end: 2.3 connect-device (duration 00:00:00) [common]
341 22:53:25.568445 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 22:53:25.569059 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 22:53:25.569638 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 22:53:25.570854 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 22:53:25.610064 >> OK - accepted request
346 22:53:25.612484 Returned 0 in 0 seconds
347 22:53:25.713658 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 22:53:25.715409 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 22:53:25.716066 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 22:53:25.716640 Setting prompt string to ['Hit any key to stop autoboot']
352 22:53:25.717147 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 22:53:25.718831 Trying 192.168.56.21...
354 22:53:25.719362 Connected to conserv1.
355 22:53:25.719819 Escape character is '^]'.
356 22:53:25.720320
357 22:53:25.720794 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 22:53:25.721274
359 22:53:37.307167 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 22:53:37.307834 bl2_stage_init 0x01
361 22:53:37.308446 bl2_stage_init 0x81
362 22:53:37.312669 hw id: 0x0000 - pwm id 0x01
363 22:53:37.313260 bl2_stage_init 0xc1
364 22:53:37.313741 bl2_stage_init 0x02
365 22:53:37.314182
366 22:53:37.318319 L0:00000000
367 22:53:37.318858 L1:20000703
368 22:53:37.319315 L2:00008067
369 22:53:37.319767 L3:14000000
370 22:53:37.323682 B2:00402000
371 22:53:37.324222 B1:e0f83180
372 22:53:37.324673
373 22:53:37.325106 TE: 58167
374 22:53:37.325534
375 22:53:37.329332 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 22:53:37.329824
377 22:53:37.330257 Board ID = 1
378 22:53:37.334946 Set A53 clk to 24M
379 22:53:37.335482 Set A73 clk to 24M
380 22:53:37.335909 Set clk81 to 24M
381 22:53:37.340555 A53 clk: 1200 MHz
382 22:53:37.341056 A73 clk: 1200 MHz
383 22:53:37.341483 CLK81: 166.6M
384 22:53:37.341903 smccc: 00012abe
385 22:53:37.346202 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 22:53:37.351635 board id: 1
387 22:53:37.357521 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 22:53:37.368251 fw parse done
389 22:53:37.374264 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 22:53:37.416850 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 22:53:37.427702 PIEI prepare done
392 22:53:37.428292 fastboot data load
393 22:53:37.428740 fastboot data verify
394 22:53:37.433382 verify result: 266
395 22:53:37.438907 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 22:53:37.439397 LPDDR4 probe
397 22:53:37.439831 ddr clk to 1584MHz
398 22:53:37.446914 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 22:53:37.484378
400 22:53:37.484932 dmc_version 0001
401 22:53:37.490928 Check phy result
402 22:53:37.496712 INFO : End of CA training
403 22:53:37.497213 INFO : End of initialization
404 22:53:37.502364 INFO : Training has run successfully!
405 22:53:37.502877 Check phy result
406 22:53:37.508050 INFO : End of initialization
407 22:53:37.508559 INFO : End of read enable training
408 22:53:37.511203 INFO : End of fine write leveling
409 22:53:37.516736 INFO : End of Write leveling coarse delay
410 22:53:37.522385 INFO : Training has run successfully!
411 22:53:37.522895 Check phy result
412 22:53:37.523364 INFO : End of initialization
413 22:53:37.528018 INFO : End of read dq deskew training
414 22:53:37.531351 INFO : End of MPR read delay center optimization
415 22:53:37.536965 INFO : End of write delay center optimization
416 22:53:37.542531 INFO : End of read delay center optimization
417 22:53:37.543063 INFO : End of max read latency training
418 22:53:37.548272 INFO : Training has run successfully!
419 22:53:37.548783 1D training succeed
420 22:53:37.556320 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 22:53:37.603963 Check phy result
422 22:53:37.604585 INFO : End of initialization
423 22:53:37.626417 INFO : End of 2D read delay Voltage center optimization
424 22:53:37.646491 INFO : End of 2D read delay Voltage center optimization
425 22:53:37.698481 INFO : End of 2D write delay Voltage center optimization
426 22:53:37.747747 INFO : End of 2D write delay Voltage center optimization
427 22:53:37.753347 INFO : Training has run successfully!
428 22:53:37.753872
429 22:53:37.754327 channel==0
430 22:53:37.758831 RxClkDly_Margin_A0==88 ps 9
431 22:53:37.759357 TxDqDly_Margin_A0==98 ps 10
432 22:53:37.762124 RxClkDly_Margin_A1==88 ps 9
433 22:53:37.762615 TxDqDly_Margin_A1==98 ps 10
434 22:53:37.767660 TrainedVREFDQ_A0==74
435 22:53:37.768186 TrainedVREFDQ_A1==74
436 22:53:37.773287 VrefDac_Margin_A0==25
437 22:53:37.773775 DeviceVref_Margin_A0==40
438 22:53:37.774225 VrefDac_Margin_A1==24
439 22:53:37.778845 DeviceVref_Margin_A1==40
440 22:53:37.779326
441 22:53:37.779775
442 22:53:37.780267 channel==1
443 22:53:37.780708 RxClkDly_Margin_A0==98 ps 10
444 22:53:37.782294 TxDqDly_Margin_A0==98 ps 10
445 22:53:37.787797 RxClkDly_Margin_A1==98 ps 10
446 22:53:37.788322 TxDqDly_Margin_A1==98 ps 10
447 22:53:37.793394 TrainedVREFDQ_A0==77
448 22:53:37.793888 TrainedVREFDQ_A1==78
449 22:53:37.794338 VrefDac_Margin_A0==22
450 22:53:37.799082 DeviceVref_Margin_A0==37
451 22:53:37.799576 VrefDac_Margin_A1==22
452 22:53:37.800062 DeviceVref_Margin_A1==36
453 22:53:37.800505
454 22:53:37.808092 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 22:53:37.808600
456 22:53:37.835960 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
457 22:53:37.836594 2D training succeed
458 22:53:37.847265 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 22:53:37.847794 auto size-- 65535DDR cs0 size: 2048MB
460 22:53:37.852781 DDR cs1 size: 2048MB
461 22:53:37.853278 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 22:53:37.858394 cs0 DataBus test pass
463 22:53:37.858887 cs1 DataBus test pass
464 22:53:37.859327 cs0 AddrBus test pass
465 22:53:37.864028 cs1 AddrBus test pass
466 22:53:37.864536
467 22:53:37.864986 100bdlr_step_size ps== 420
468 22:53:37.865439 result report
469 22:53:37.869505 boot times 0Enable ddr reg access
470 22:53:37.876292 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 22:53:37.889626 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 22:53:38.461728 0.0;M3 CHK:0;cm4_sp_mode 0
473 22:53:38.462424 MVN_1=0x00000000
474 22:53:38.467246 MVN_2=0x00000000
475 22:53:38.473002 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 22:53:38.473518 OPS=0x10
477 22:53:38.473980 ring efuse init
478 22:53:38.474428 chipver efuse init
479 22:53:38.478494 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 22:53:38.484306 [0.018960 Inits done]
481 22:53:38.484826 secure task start!
482 22:53:38.485279 high task start!
483 22:53:38.488930 low task start!
484 22:53:38.489466 run into bl31
485 22:53:38.495531 NOTICE: BL31: v1.3(release):4fc40b1
486 22:53:38.503401 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 22:53:38.503947 NOTICE: BL31: G12A normal boot!
488 22:53:38.528673 NOTICE: BL31: BL33 decompress pass
489 22:53:38.534450 ERROR: Error initializing runtime service opteed_fast
490 22:53:39.767176
491 22:53:39.767843
492 22:53:39.775696 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 22:53:39.776295
494 22:53:39.776765 Model: Libre Computer AML-A311D-CC Alta
495 22:53:39.984170 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 22:53:40.007527 DRAM: 2 GiB (effective 3.8 GiB)
497 22:53:40.150494 Core: 408 devices, 31 uclasses, devicetree: separate
498 22:53:40.156345 WDT: Not starting watchdog@f0d0
499 22:53:40.188643 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 22:53:40.201026 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 22:53:40.206136 ** Bad device specification mmc 0 **
502 22:53:40.216281 Card did not respond to voltage select! : -110
503 22:53:40.223893 ** Bad device specification mmc 0 **
504 22:53:40.224454 Couldn't find partition mmc 0
505 22:53:40.232320 Card did not respond to voltage select! : -110
506 22:53:40.237832 ** Bad device specification mmc 0 **
507 22:53:40.238424 Couldn't find partition mmc 0
508 22:53:40.242860 Error: could not access storage.
509 22:53:41.507189 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 22:53:41.507618 bl2_stage_init 0x01
511 22:53:41.507843 bl2_stage_init 0x81
512 22:53:41.512759 hw id: 0x0000 - pwm id 0x01
513 22:53:41.513084 bl2_stage_init 0xc1
514 22:53:41.513304 bl2_stage_init 0x02
515 22:53:41.513524
516 22:53:41.518329 L0:00000000
517 22:53:41.518777 L1:20000703
518 22:53:41.519121 L2:00008067
519 22:53:41.519446 L3:14000000
520 22:53:41.523868 B2:00402000
521 22:53:41.524223 B1:e0f83180
522 22:53:41.524444
523 22:53:41.524656 TE: 58124
524 22:53:41.524862
525 22:53:41.529472 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 22:53:41.529787
527 22:53:41.530005 Board ID = 1
528 22:53:41.535090 Set A53 clk to 24M
529 22:53:41.535415 Set A73 clk to 24M
530 22:53:41.535631 Set clk81 to 24M
531 22:53:41.540727 A53 clk: 1200 MHz
532 22:53:41.541056 A73 clk: 1200 MHz
533 22:53:41.541278 CLK81: 166.6M
534 22:53:41.541487 smccc: 00012a92
535 22:53:41.546329 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 22:53:41.551878 board id: 1
537 22:53:41.557766 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 22:53:41.568431 fw parse done
539 22:53:41.574364 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 22:53:41.617002 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 22:53:41.627908 PIEI prepare done
542 22:53:41.628263 fastboot data load
543 22:53:41.628478 fastboot data verify
544 22:53:41.633507 verify result: 266
545 22:53:41.639085 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 22:53:41.639384 LPDDR4 probe
547 22:53:41.639600 ddr clk to 1584MHz
548 22:53:41.647103 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 22:53:41.684377
550 22:53:41.684733 dmc_version 0001
551 22:53:41.691044 Check phy result
552 22:53:41.696857 INFO : End of CA training
553 22:53:41.697357 INFO : End of initialization
554 22:53:41.702480 INFO : Training has run successfully!
555 22:53:41.703185 Check phy result
556 22:53:41.708117 INFO : End of initialization
557 22:53:41.708743 INFO : End of read enable training
558 22:53:41.711395 INFO : End of fine write leveling
559 22:53:41.716990 INFO : End of Write leveling coarse delay
560 22:53:41.722677 INFO : Training has run successfully!
561 22:53:41.723206 Check phy result
562 22:53:41.723668 INFO : End of initialization
563 22:53:41.728165 INFO : End of read dq deskew training
564 22:53:41.733798 INFO : End of MPR read delay center optimization
565 22:53:41.734345 INFO : End of write delay center optimization
566 22:53:41.739398 INFO : End of read delay center optimization
567 22:53:41.745017 INFO : End of max read latency training
568 22:53:41.745533 INFO : Training has run successfully!
569 22:53:41.750667 1D training succeed
570 22:53:41.756486 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 22:53:41.804155 Check phy result
572 22:53:41.804754 INFO : End of initialization
573 22:53:41.826568 INFO : End of 2D read delay Voltage center optimization
574 22:53:41.846647 INFO : End of 2D read delay Voltage center optimization
575 22:53:41.898581 INFO : End of 2D write delay Voltage center optimization
576 22:53:41.947843 INFO : End of 2D write delay Voltage center optimization
577 22:53:41.953348 INFO : Training has run successfully!
578 22:53:41.953709
579 22:53:41.953941 channel==0
580 22:53:41.958947 RxClkDly_Margin_A0==88 ps 9
581 22:53:41.959314 TxDqDly_Margin_A0==98 ps 10
582 22:53:41.964547 RxClkDly_Margin_A1==88 ps 9
583 22:53:41.964915 TxDqDly_Margin_A1==98 ps 10
584 22:53:41.965140 TrainedVREFDQ_A0==74
585 22:53:41.970109 TrainedVREFDQ_A1==75
586 22:53:41.970449 VrefDac_Margin_A0==25
587 22:53:41.970668 DeviceVref_Margin_A0==40
588 22:53:41.975664 VrefDac_Margin_A1==24
589 22:53:41.975971 DeviceVref_Margin_A1==39
590 22:53:41.976219
591 22:53:41.976429
592 22:53:41.981268 channel==1
593 22:53:41.981557 RxClkDly_Margin_A0==98 ps 10
594 22:53:41.981772 TxDqDly_Margin_A0==88 ps 9
595 22:53:41.986879 RxClkDly_Margin_A1==88 ps 9
596 22:53:41.987232 TxDqDly_Margin_A1==108 ps 11
597 22:53:41.992528 TrainedVREFDQ_A0==77
598 22:53:41.992865 TrainedVREFDQ_A1==78
599 22:53:41.993094 VrefDac_Margin_A0==22
600 22:53:41.998122 DeviceVref_Margin_A0==37
601 22:53:41.998457 VrefDac_Margin_A1==24
602 22:53:42.003724 DeviceVref_Margin_A1==36
603 22:53:42.004095
604 22:53:42.004343 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 22:53:42.009336
606 22:53:42.037333 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
607 22:53:42.037742 2D training succeed
608 22:53:42.042925 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 22:53:42.048518 auto size-- 65535DDR cs0 size: 2048MB
610 22:53:42.048861 DDR cs1 size: 2048MB
611 22:53:42.054121 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 22:53:42.054468 cs0 DataBus test pass
613 22:53:42.059729 cs1 DataBus test pass
614 22:53:42.060116 cs0 AddrBus test pass
615 22:53:42.060365 cs1 AddrBus test pass
616 22:53:42.060585
617 22:53:42.065311 100bdlr_step_size ps== 420
618 22:53:42.065654 result report
619 22:53:42.070931 boot times 0Enable ddr reg access
620 22:53:42.076367 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 22:53:42.089851 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 22:53:42.662057 0.0;M3 CHK:0;cm4_sp_mode 0
623 22:53:42.662734 MVN_1=0x00000000
624 22:53:42.667440 MVN_2=0x00000000
625 22:53:42.673221 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 22:53:42.673758 OPS=0x10
627 22:53:42.674206 ring efuse init
628 22:53:42.674696 chipver efuse init
629 22:53:42.678907 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 22:53:42.684431 [0.018961 Inits done]
631 22:53:42.684946 secure task start!
632 22:53:42.685377 high task start!
633 22:53:42.688990 low task start!
634 22:53:42.689505 run into bl31
635 22:53:42.695670 NOTICE: BL31: v1.3(release):4fc40b1
636 22:53:42.703450 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 22:53:42.703972 NOTICE: BL31: G12A normal boot!
638 22:53:42.728930 NOTICE: BL31: BL33 decompress pass
639 22:53:42.734491 ERROR: Error initializing runtime service opteed_fast
640 22:53:43.967739
641 22:53:43.968467
642 22:53:43.976119 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 22:53:43.976648
644 22:53:43.977090 Model: Libre Computer AML-A311D-CC Alta
645 22:53:44.184426 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 22:53:44.207780 DRAM: 2 GiB (effective 3.8 GiB)
647 22:53:44.350834 Core: 408 devices, 31 uclasses, devicetree: separate
648 22:53:44.356606 WDT: Not starting watchdog@f0d0
649 22:53:44.388983 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 22:53:44.401345 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 22:53:44.406446 ** Bad device specification mmc 0 **
652 22:53:44.416694 Card did not respond to voltage select! : -110
653 22:53:44.424416 ** Bad device specification mmc 0 **
654 22:53:44.424936 Couldn't find partition mmc 0
655 22:53:44.432674 Card did not respond to voltage select! : -110
656 22:53:44.438579 ** Bad device specification mmc 0 **
657 22:53:44.439153 Couldn't find partition mmc 0
658 22:53:44.443290 Error: could not access storage.
659 22:53:44.786774 Net: eth0: ethernet@ff3f0000
660 22:53:44.787445 starting USB...
661 22:53:45.038437 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 22:53:45.039105 Starting the controller
663 22:53:45.045499 USB XHCI 1.10
664 22:53:46.757601 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 22:53:46.758284 bl2_stage_init 0x01
666 22:53:46.758755 bl2_stage_init 0x81
667 22:53:46.763070 hw id: 0x0000 - pwm id 0x01
668 22:53:46.763582 bl2_stage_init 0xc1
669 22:53:46.764088 bl2_stage_init 0x02
670 22:53:46.764540
671 22:53:46.768617 L0:00000000
672 22:53:46.769122 L1:20000703
673 22:53:46.769573 L2:00008067
674 22:53:46.770009 L3:14000000
675 22:53:46.774852 B2:00402000
676 22:53:46.775351 B1:e0f83180
677 22:53:46.775796
678 22:53:46.776290 TE: 58167
679 22:53:46.776736
680 22:53:46.779840 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 22:53:46.780392
682 22:53:46.780847 Board ID = 1
683 22:53:46.785635 Set A53 clk to 24M
684 22:53:46.786138 Set A73 clk to 24M
685 22:53:46.786584 Set clk81 to 24M
686 22:53:46.790998 A53 clk: 1200 MHz
687 22:53:46.791495 A73 clk: 1200 MHz
688 22:53:46.791940 CLK81: 166.6M
689 22:53:46.792424 smccc: 00012abd
690 22:53:46.796626 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 22:53:46.802349 board id: 1
692 22:53:46.808241 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 22:53:46.818688 fw parse done
694 22:53:46.824640 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 22:53:46.867238 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 22:53:46.878209 PIEI prepare done
697 22:53:46.878727 fastboot data load
698 22:53:46.879159 fastboot data verify
699 22:53:46.883848 verify result: 266
700 22:53:46.889526 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 22:53:46.890042 LPDDR4 probe
702 22:53:46.890461 ddr clk to 1584MHz
703 22:53:46.897378 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 22:53:46.934756
705 22:53:46.935353 dmc_version 0001
706 22:53:46.941380 Check phy result
707 22:53:46.947256 INFO : End of CA training
708 22:53:46.947769 INFO : End of initialization
709 22:53:46.952836 INFO : Training has run successfully!
710 22:53:46.953345 Check phy result
711 22:53:46.958523 INFO : End of initialization
712 22:53:46.959026 INFO : End of read enable training
713 22:53:46.964039 INFO : End of fine write leveling
714 22:53:46.969617 INFO : End of Write leveling coarse delay
715 22:53:46.970136 INFO : Training has run successfully!
716 22:53:46.970554 Check phy result
717 22:53:46.975215 INFO : End of initialization
718 22:53:46.975746 INFO : End of read dq deskew training
719 22:53:46.980839 INFO : End of MPR read delay center optimization
720 22:53:46.987159 INFO : End of write delay center optimization
721 22:53:46.992025 INFO : End of read delay center optimization
722 22:53:46.992591 INFO : End of max read latency training
723 22:53:46.997540 INFO : Training has run successfully!
724 22:53:46.998079 1D training succeed
725 22:53:47.006847 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 22:53:47.054428 Check phy result
727 22:53:47.054945 INFO : End of initialization
728 22:53:47.076984 INFO : End of 2D read delay Voltage center optimization
729 22:53:47.097192 INFO : End of 2D read delay Voltage center optimization
730 22:53:47.149268 INFO : End of 2D write delay Voltage center optimization
731 22:53:47.198630 INFO : End of 2D write delay Voltage center optimization
732 22:53:47.204328 INFO : Training has run successfully!
733 22:53:47.204787
734 22:53:47.205201 channel==0
735 22:53:47.209799 RxClkDly_Margin_A0==88 ps 9
736 22:53:47.210243 TxDqDly_Margin_A0==98 ps 10
737 22:53:47.213278 RxClkDly_Margin_A1==78 ps 8
738 22:53:47.213720 TxDqDly_Margin_A1==88 ps 9
739 22:53:47.218763 TrainedVREFDQ_A0==74
740 22:53:47.219214 TrainedVREFDQ_A1==74
741 22:53:47.219624 VrefDac_Margin_A0==25
742 22:53:47.224387 DeviceVref_Margin_A0==40
743 22:53:47.224868 VrefDac_Margin_A1==26
744 22:53:47.230043 DeviceVref_Margin_A1==40
745 22:53:47.230552
746 22:53:47.230971
747 22:53:47.231373 channel==1
748 22:53:47.231767 RxClkDly_Margin_A0==98 ps 10
749 22:53:47.233411 TxDqDly_Margin_A0==88 ps 9
750 22:53:47.238995 RxClkDly_Margin_A1==98 ps 10
751 22:53:47.239447 TxDqDly_Margin_A1==88 ps 9
752 22:53:47.239858 TrainedVREFDQ_A0==77
753 22:53:47.244590 TrainedVREFDQ_A1==78
754 22:53:47.245054 VrefDac_Margin_A0==22
755 22:53:47.250165 DeviceVref_Margin_A0==37
756 22:53:47.250612 VrefDac_Margin_A1==22
757 22:53:47.251020 DeviceVref_Margin_A1==36
758 22:53:47.251416
759 22:53:47.259166 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 22:53:47.259624
761 22:53:47.284870 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
762 22:53:47.290568 2D training succeed
763 22:53:47.296082 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 22:53:47.296533 auto size-- 65535DDR cs0 size: 2048MB
765 22:53:47.301685 DDR cs1 size: 2048MB
766 22:53:47.302126 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 22:53:47.307302 cs0 DataBus test pass
768 22:53:47.307746 cs1 DataBus test pass
769 22:53:47.312893 cs0 AddrBus test pass
770 22:53:47.313327 cs1 AddrBus test pass
771 22:53:47.313727
772 22:53:47.314120 100bdlr_step_size ps== 420
773 22:53:47.318526 result report
774 22:53:47.318963 boot times 0Enable ddr reg access
775 22:53:47.327010 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 22:53:47.340584 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 22:53:47.914304 0.0;M3 CHK:0;cm4_sp_mode 0
778 22:53:47.914949 MVN_1=0x00000000
779 22:53:47.919714 MVN_2=0x00000000
780 22:53:47.925619 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 22:53:47.926224 OPS=0x10
782 22:53:47.926629 ring efuse init
783 22:53:47.927019 chipver efuse init
784 22:53:47.931007 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 22:53:47.936589 [0.018961 Inits done]
786 22:53:47.937047 secure task start!
787 22:53:47.937438 high task start!
788 22:53:47.941139 low task start!
789 22:53:47.941581 run into bl31
790 22:53:47.947832 NOTICE: BL31: v1.3(release):4fc40b1
791 22:53:47.955594 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 22:53:47.955843 NOTICE: BL31: G12A normal boot!
793 22:53:47.981195 NOTICE: BL31: BL33 decompress pass
794 22:53:47.986717 ERROR: Error initializing runtime service opteed_fast
795 22:53:49.219745
796 22:53:49.220449
797 22:53:49.228137 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 22:53:49.228691
799 22:53:49.229158 Model: Libre Computer AML-A311D-CC Alta
800 22:53:49.436655 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 22:53:49.459977 DRAM: 2 GiB (effective 3.8 GiB)
802 22:53:49.602980 Core: 408 devices, 31 uclasses, devicetree: separate
803 22:53:49.608970 WDT: Not starting watchdog@f0d0
804 22:53:49.641107 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 22:53:49.653488 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 22:53:49.658934 ** Bad device specification mmc 0 **
807 22:53:49.668906 Card did not respond to voltage select! : -110
808 22:53:49.676513 ** Bad device specification mmc 0 **
809 22:53:49.677036 Couldn't find partition mmc 0
810 22:53:49.684892 Card did not respond to voltage select! : -110
811 22:53:49.690347 ** Bad device specification mmc 0 **
812 22:53:49.690865 Couldn't find partition mmc 0
813 22:53:49.695417 Error: could not access storage.
814 22:53:50.038000 Net: eth0: ethernet@ff3f0000
815 22:53:50.038614 starting USB...
816 22:53:50.289671 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 22:53:50.290321 Starting the controller
818 22:53:50.296723 USB XHCI 1.10
819 22:53:52.459149 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 22:53:52.459576 bl2_stage_init 0x01
821 22:53:52.459794 bl2_stage_init 0x81
822 22:53:52.464540 hw id: 0x0000 - pwm id 0x01
823 22:53:52.464811 bl2_stage_init 0xc1
824 22:53:52.465024 bl2_stage_init 0x02
825 22:53:52.465225
826 22:53:52.470222 L0:00000000
827 22:53:52.470500 L1:20000703
828 22:53:52.470708 L2:00008067
829 22:53:52.470907 L3:14000000
830 22:53:52.473061 B2:00402000
831 22:53:52.473320 B1:e0f83180
832 22:53:52.473524
833 22:53:52.473721 TE: 58124
834 22:53:52.473981
835 22:53:52.484221 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 22:53:52.484612
837 22:53:52.484935 Board ID = 1
838 22:53:52.485260 Set A53 clk to 24M
839 22:53:52.485487 Set A73 clk to 24M
840 22:53:52.489728 Set clk81 to 24M
841 22:53:52.490004 A53 clk: 1200 MHz
842 22:53:52.490208 A73 clk: 1200 MHz
843 22:53:52.493283 CLK81: 166.6M
844 22:53:52.493544 smccc: 00012a92
845 22:53:52.498927 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 22:53:52.504437 board id: 1
847 22:53:52.509626 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 22:53:52.520287 fw parse done
849 22:53:52.526347 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 22:53:52.568834 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 22:53:52.579606 PIEI prepare done
852 22:53:52.579890 fastboot data load
853 22:53:52.580133 fastboot data verify
854 22:53:52.585159 verify result: 266
855 22:53:52.590842 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 22:53:52.591243 LPDDR4 probe
857 22:53:52.591567 ddr clk to 1584MHz
858 22:53:52.598848 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 22:53:52.636164
860 22:53:52.636493 dmc_version 0001
861 22:53:52.642799 Check phy result
862 22:53:52.648648 INFO : End of CA training
863 22:53:52.649035 INFO : End of initialization
864 22:53:52.654257 INFO : Training has run successfully!
865 22:53:52.654515 Check phy result
866 22:53:52.659847 INFO : End of initialization
867 22:53:52.660132 INFO : End of read enable training
868 22:53:52.665453 INFO : End of fine write leveling
869 22:53:52.671199 INFO : End of Write leveling coarse delay
870 22:53:52.671577 INFO : Training has run successfully!
871 22:53:52.671819 Check phy result
872 22:53:52.676694 INFO : End of initialization
873 22:53:52.676952 INFO : End of read dq deskew training
874 22:53:52.682321 INFO : End of MPR read delay center optimization
875 22:53:52.687876 INFO : End of write delay center optimization
876 22:53:52.693474 INFO : End of read delay center optimization
877 22:53:52.693740 INFO : End of max read latency training
878 22:53:52.699216 INFO : Training has run successfully!
879 22:53:52.699598 1D training succeed
880 22:53:52.708301 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 22:53:52.755870 Check phy result
882 22:53:52.756259 INFO : End of initialization
883 22:53:52.778489 INFO : End of 2D read delay Voltage center optimization
884 22:53:52.798690 INFO : End of 2D read delay Voltage center optimization
885 22:53:52.850781 INFO : End of 2D write delay Voltage center optimization
886 22:53:52.900091 INFO : End of 2D write delay Voltage center optimization
887 22:53:52.905661 INFO : Training has run successfully!
888 22:53:52.906131
889 22:53:52.906574 channel==0
890 22:53:52.911329 RxClkDly_Margin_A0==88 ps 9
891 22:53:52.911798 TxDqDly_Margin_A0==98 ps 10
892 22:53:52.916909 RxClkDly_Margin_A1==88 ps 9
893 22:53:52.917377 TxDqDly_Margin_A1==98 ps 10
894 22:53:52.917842 TrainedVREFDQ_A0==74
895 22:53:52.922537 TrainedVREFDQ_A1==74
896 22:53:52.923046 VrefDac_Margin_A0==24
897 22:53:52.923485 DeviceVref_Margin_A0==40
898 22:53:52.928114 VrefDac_Margin_A1==25
899 22:53:52.928610 DeviceVref_Margin_A1==40
900 22:53:52.929035
901 22:53:52.929458
902 22:53:52.933739 channel==1
903 22:53:52.934197 RxClkDly_Margin_A0==98 ps 10
904 22:53:52.934622 TxDqDly_Margin_A0==98 ps 10
905 22:53:52.939306 RxClkDly_Margin_A1==88 ps 9
906 22:53:52.939752 TxDqDly_Margin_A1==88 ps 9
907 22:53:52.944899 TrainedVREFDQ_A0==77
908 22:53:52.945353 TrainedVREFDQ_A1==77
909 22:53:52.945775 VrefDac_Margin_A0==22
910 22:53:52.950446 DeviceVref_Margin_A0==37
911 22:53:52.950904 VrefDac_Margin_A1==24
912 22:53:52.956157 DeviceVref_Margin_A1==37
913 22:53:52.956606
914 22:53:52.957027 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 22:53:52.957445
916 22:53:52.989655 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000016 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 22:53:52.990140 2D training succeed
918 22:53:52.995246 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 22:53:53.000788 auto size-- 65535DDR cs0 size: 2048MB
920 22:53:53.001244 DDR cs1 size: 2048MB
921 22:53:53.006375 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 22:53:53.006825 cs0 DataBus test pass
923 22:53:53.012021 cs1 DataBus test pass
924 22:53:53.012478 cs0 AddrBus test pass
925 22:53:53.012902 cs1 AddrBus test pass
926 22:53:53.013320
927 22:53:53.017609 100bdlr_step_size ps== 420
928 22:53:53.018077 result report
929 22:53:53.023248 boot times 0Enable ddr reg access
930 22:53:53.028567 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 22:53:53.042031 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 22:53:53.615875 0.0;M3 CHK:0;cm4_sp_mode 0
933 22:53:53.616570 MVN_1=0x00000000
934 22:53:53.621346 MVN_2=0x00000000
935 22:53:53.627068 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 22:53:53.627547 OPS=0x10
937 22:53:53.628032 ring efuse init
938 22:53:53.628480 chipver efuse init
939 22:53:53.632621 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 22:53:53.638329 [0.018961 Inits done]
941 22:53:53.638803 secure task start!
942 22:53:53.639245 high task start!
943 22:53:53.642804 low task start!
944 22:53:53.643272 run into bl31
945 22:53:53.649448 NOTICE: BL31: v1.3(release):4fc40b1
946 22:53:53.657424 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 22:53:53.657915 NOTICE: BL31: G12A normal boot!
948 22:53:53.682633 NOTICE: BL31: BL33 decompress pass
949 22:53:53.688398 ERROR: Error initializing runtime service opteed_fast
950 22:53:54.921303
951 22:53:54.921974
952 22:53:54.929610 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 22:53:54.930102
954 22:53:54.930558 Model: Libre Computer AML-A311D-CC Alta
955 22:53:55.138059 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 22:53:55.161386 DRAM: 2 GiB (effective 3.8 GiB)
957 22:53:55.304417 Core: 408 devices, 31 uclasses, devicetree: separate
958 22:53:55.310239 WDT: Not starting watchdog@f0d0
959 22:53:55.342586 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 22:53:55.354933 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 22:53:55.359908 ** Bad device specification mmc 0 **
962 22:53:55.370291 Card did not respond to voltage select! : -110
963 22:53:55.377934 ** Bad device specification mmc 0 **
964 22:53:55.378409 Couldn't find partition mmc 0
965 22:53:55.386376 Card did not respond to voltage select! : -110
966 22:53:55.391725 ** Bad device specification mmc 0 **
967 22:53:55.392230 Couldn't find partition mmc 0
968 22:53:55.396771 Error: could not access storage.
969 22:53:55.739229 Net: eth0: ethernet@ff3f0000
970 22:53:55.739791 starting USB...
971 22:53:55.991054 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 22:53:55.991581 Starting the controller
973 22:53:55.997982 USB XHCI 1.10
974 22:53:57.858723 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 22:53:57.859379 bl2_stage_init 0x01
976 22:53:57.859841 bl2_stage_init 0x81
977 22:53:57.864272 hw id: 0x0000 - pwm id 0x01
978 22:53:57.864751 bl2_stage_init 0xc1
979 22:53:57.865195 bl2_stage_init 0x02
980 22:53:57.865631
981 22:53:57.869874 L0:00000000
982 22:53:57.870342 L1:20000703
983 22:53:57.870784 L2:00008067
984 22:53:57.871217 L3:14000000
985 22:53:57.872897 B2:00402000
986 22:53:57.873365 B1:e0f83180
987 22:53:57.873805
988 22:53:57.874245 TE: 58159
989 22:53:57.874680
990 22:53:57.884067 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 22:53:57.884545
992 22:53:57.884991 Board ID = 1
993 22:53:57.885420 Set A53 clk to 24M
994 22:53:57.885849 Set A73 clk to 24M
995 22:53:57.889664 Set clk81 to 24M
996 22:53:57.890132 A53 clk: 1200 MHz
997 22:53:57.890573 A73 clk: 1200 MHz
998 22:53:57.895246 CLK81: 166.6M
999 22:53:57.895709 smccc: 00012ab5
1000 22:53:57.900875 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 22:53:57.901342 board id: 1
1002 22:53:57.909350 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 22:53:57.920043 fw parse done
1004 22:53:57.926010 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 22:53:57.968595 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 22:53:57.979521 PIEI prepare done
1007 22:53:57.979970 fastboot data load
1008 22:53:57.980448 fastboot data verify
1009 22:53:57.985164 verify result: 266
1010 22:53:57.990752 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 22:53:57.991208 LPDDR4 probe
1012 22:53:57.991633 ddr clk to 1584MHz
1013 22:53:57.998960 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 22:53:58.036257
1015 22:53:58.036732 dmc_version 0001
1016 22:53:58.042884 Check phy result
1017 22:53:58.048772 INFO : End of CA training
1018 22:53:58.049235 INFO : End of initialization
1019 22:53:58.054226 INFO : Training has run successfully!
1020 22:53:58.054686 Check phy result
1021 22:53:58.059886 INFO : End of initialization
1022 22:53:58.060433 INFO : End of read enable training
1023 22:53:58.063198 INFO : End of fine write leveling
1024 22:53:58.068734 INFO : End of Write leveling coarse delay
1025 22:53:58.074329 INFO : Training has run successfully!
1026 22:53:58.074797 Check phy result
1027 22:53:58.075239 INFO : End of initialization
1028 22:53:58.079894 INFO : End of read dq deskew training
1029 22:53:58.085433 INFO : End of MPR read delay center optimization
1030 22:53:58.085905 INFO : End of write delay center optimization
1031 22:53:58.091074 INFO : End of read delay center optimization
1032 22:53:58.096641 INFO : End of max read latency training
1033 22:53:58.097113 INFO : Training has run successfully!
1034 22:53:58.102234 1D training succeed
1035 22:53:58.108241 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 22:53:58.155759 Check phy result
1037 22:53:58.156262 INFO : End of initialization
1038 22:53:58.177487 INFO : End of 2D read delay Voltage center optimization
1039 22:53:58.197956 INFO : End of 2D read delay Voltage center optimization
1040 22:53:58.249811 INFO : End of 2D write delay Voltage center optimization
1041 22:53:58.299239 INFO : End of 2D write delay Voltage center optimization
1042 22:53:58.304923 INFO : Training has run successfully!
1043 22:53:58.305426
1044 22:53:58.305878 channel==0
1045 22:53:58.310337 RxClkDly_Margin_A0==88 ps 9
1046 22:53:58.310808 TxDqDly_Margin_A0==98 ps 10
1047 22:53:58.313789 RxClkDly_Margin_A1==88 ps 9
1048 22:53:58.314252 TxDqDly_Margin_A1==88 ps 9
1049 22:53:58.319343 TrainedVREFDQ_A0==74
1050 22:53:58.319812 TrainedVREFDQ_A1==74
1051 22:53:58.320285 VrefDac_Margin_A0==25
1052 22:53:58.324851 DeviceVref_Margin_A0==40
1053 22:53:58.325333 VrefDac_Margin_A1==25
1054 22:53:58.330559 DeviceVref_Margin_A1==40
1055 22:53:58.331027
1056 22:53:58.331470
1057 22:53:58.331905 channel==1
1058 22:53:58.332378 RxClkDly_Margin_A0==98 ps 10
1059 22:53:58.333999 TxDqDly_Margin_A0==98 ps 10
1060 22:53:58.339495 RxClkDly_Margin_A1==98 ps 10
1061 22:53:58.339961 TxDqDly_Margin_A1==88 ps 9
1062 22:53:58.340440 TrainedVREFDQ_A0==77
1063 22:53:58.345091 TrainedVREFDQ_A1==77
1064 22:53:58.345556 VrefDac_Margin_A0==22
1065 22:53:58.350793 DeviceVref_Margin_A0==37
1066 22:53:58.351254 VrefDac_Margin_A1==24
1067 22:53:58.351691 DeviceVref_Margin_A1==37
1068 22:53:58.352160
1069 22:53:58.356353 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 22:53:58.356820
1071 22:53:58.389982 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
1072 22:53:58.390487 2D training succeed
1073 22:53:58.395464 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 22:53:58.401030 auto size-- 65535DDR cs0 size: 2048MB
1075 22:53:58.401498 DDR cs1 size: 2048MB
1076 22:53:58.406614 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 22:53:58.407078 cs0 DataBus test pass
1078 22:53:58.407515 cs1 DataBus test pass
1079 22:53:58.412221 cs0 AddrBus test pass
1080 22:53:58.412690 cs1 AddrBus test pass
1081 22:53:58.413128
1082 22:53:58.417773 100bdlr_step_size ps== 420
1083 22:53:58.418264 result report
1084 22:53:58.418708 boot times 0Enable ddr reg access
1085 22:53:58.427608 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 22:53:58.441134 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 22:53:59.014854 0.0;M3 CHK:0;cm4_sp_mode 0
1088 22:53:59.015526 MVN_1=0x00000000
1089 22:53:59.020251 MVN_2=0x00000000
1090 22:53:59.026041 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 22:53:59.026540 OPS=0x10
1092 22:53:59.026992 ring efuse init
1093 22:53:59.027435 chipver efuse init
1094 22:53:59.031563 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 22:53:59.037139 [0.018960 Inits done]
1096 22:53:59.037620 secure task start!
1097 22:53:59.038059 high task start!
1098 22:53:59.041737 low task start!
1099 22:53:59.042215 run into bl31
1100 22:53:59.048376 NOTICE: BL31: v1.3(release):4fc40b1
1101 22:53:59.056238 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 22:53:59.056730 NOTICE: BL31: G12A normal boot!
1103 22:53:59.081554 NOTICE: BL31: BL33 decompress pass
1104 22:53:59.087219 ERROR: Error initializing runtime service opteed_fast
1105 22:54:00.320223
1106 22:54:00.320865
1107 22:54:00.328464 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 22:54:00.329039
1109 22:54:00.329540 Model: Libre Computer AML-A311D-CC Alta
1110 22:54:00.537044 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 22:54:00.560437 DRAM: 2 GiB (effective 3.8 GiB)
1112 22:54:00.703556 Core: 408 devices, 31 uclasses, devicetree: separate
1113 22:54:00.709177 WDT: Not starting watchdog@f0d0
1114 22:54:00.741442 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 22:54:00.753914 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 22:54:00.758895 ** Bad device specification mmc 0 **
1117 22:54:00.769343 Card did not respond to voltage select! : -110
1118 22:54:00.776886 ** Bad device specification mmc 0 **
1119 22:54:00.777408 Couldn't find partition mmc 0
1120 22:54:00.785340 Card did not respond to voltage select! : -110
1121 22:54:00.790735 ** Bad device specification mmc 0 **
1122 22:54:00.791259 Couldn't find partition mmc 0
1123 22:54:00.795786 Error: could not access storage.
1124 22:54:01.138294 Net: eth0: ethernet@ff3f0000
1125 22:54:01.138942 starting USB...
1126 22:54:01.390189 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 22:54:01.390788 Starting the controller
1128 22:54:01.397031 USB XHCI 1.10
1129 22:54:02.951176 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 22:54:02.959508 scanning usb for storage devices... 0 Storage Device(s) found
1132 22:54:03.011126 Hit any key to stop autoboot: 1
1133 22:54:03.011950 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 22:54:03.012608 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 22:54:03.013102 Setting prompt string to ['=>']
1136 22:54:03.013611 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 22:54:03.027080 0
1138 22:54:03.028042 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 22:54:03.028560 Sending with 10 millisecond of delay
1141 22:54:04.163298 => setenv autoload no
1142 22:54:04.174115 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1143 22:54:04.179357 setenv autoload no
1144 22:54:04.180142 Sending with 10 millisecond of delay
1146 22:54:05.977092 => setenv initrd_high 0xffffffff
1147 22:54:05.987926 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 22:54:05.988907 setenv initrd_high 0xffffffff
1149 22:54:05.989673 Sending with 10 millisecond of delay
1151 22:54:07.607620 => setenv fdt_high 0xffffffff
1152 22:54:07.618649 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 22:54:07.619722 setenv fdt_high 0xffffffff
1154 22:54:07.620628 Sending with 10 millisecond of delay
1156 22:54:07.912975 => dhcp
1157 22:54:07.924030 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 22:54:07.924759 dhcp
1159 22:54:07.925071 Speed: 1000, full duplex
1160 22:54:07.925356 BOOTP broadcast 1
1161 22:54:07.936377 DHCP client bound to address 192.168.6.27 (13 ms)
1162 22:54:07.937106 Sending with 10 millisecond of delay
1164 22:54:09.615115 => setenv serverip 192.168.6.2
1165 22:54:09.625717 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 22:54:09.626315 setenv serverip 192.168.6.2
1167 22:54:09.626790 Sending with 10 millisecond of delay
1169 22:54:13.351161 => tftpboot 0x01080000 963283/tftp-deploy-7il2elk9/kernel/uImage
1170 22:54:13.362068 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 22:54:13.362608 tftpboot 0x01080000 963283/tftp-deploy-7il2elk9/kernel/uImage
1172 22:54:13.362853 Speed: 1000, full duplex
1173 22:54:13.363066 Using ethernet@ff3f0000 device
1174 22:54:13.364518 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 22:54:13.370369 Filename '963283/tftp-deploy-7il2elk9/kernel/uImage'.
1176 22:54:13.373136 Load address: 0x1080000
1177 22:54:16.304626 Loading: *################################################## 43.6 MiB
1178 22:54:16.305042 14.9 MiB/s
1179 22:54:16.305254 done
1180 22:54:16.309154 Bytes transferred = 45713984 (2b98a40 hex)
1181 22:54:16.309706 Sending with 10 millisecond of delay
1183 22:54:20.995805 => tftpboot 0x08000000 963283/tftp-deploy-7il2elk9/ramdisk/ramdisk.cpio.gz.uboot
1184 22:54:21.006566 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 22:54:21.007066 tftpboot 0x08000000 963283/tftp-deploy-7il2elk9/ramdisk/ramdisk.cpio.gz.uboot
1186 22:54:21.007303 Speed: 1000, full duplex
1187 22:54:21.007510 Using ethernet@ff3f0000 device
1188 22:54:21.009195 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 22:54:21.017798 Filename '963283/tftp-deploy-7il2elk9/ramdisk/ramdisk.cpio.gz.uboot'.
1190 22:54:21.018214 Load address: 0x8000000
1191 22:54:23.956587 Loading: *#################### UDP wrong checksum 000000ff 00003d2d
1192 22:54:24.004170 UDP wrong checksum 000000ff 0000d71f
1193 22:54:28.034310 T ############################# UDP wrong checksum 00000005 0000a769
1194 22:54:32.843273 T UDP wrong checksum 00000005 0000a769
1195 22:54:36.946298 UDP wrong checksum 000000ff 0000253a
1196 22:54:36.989443 UDP wrong checksum 000000ff 0000b12c
1197 22:54:38.361287 T UDP wrong checksum 000000ff 000069ce
1198 22:54:38.374238 UDP wrong checksum 000000ff 0000ffc0
1199 22:54:42.845360 T UDP wrong checksum 00000005 0000a769
1200 22:55:02.848424 T T T T UDP wrong checksum 00000005 0000a769
1201 22:55:03.930338 UDP wrong checksum 000000ff 0000f640
1202 22:55:03.977115 UDP wrong checksum 000000ff 00008133
1203 22:55:17.852382 T T
1204 22:55:17.853039 Retry count exceeded; starting again
1206 22:55:17.854560 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1209 22:55:17.856648 end: 2.4 uboot-commands (duration 00:01:52) [common]
1211 22:55:17.858171 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1213 22:55:17.859261 end: 2 uboot-action (duration 00:01:52) [common]
1215 22:55:17.860913 Cleaning after the job
1216 22:55:17.861467 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/ramdisk
1217 22:55:17.862926 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/kernel
1218 22:55:17.870986 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/dtb
1219 22:55:17.872245 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/nfsrootfs
1220 22:55:17.919596 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963283/tftp-deploy-7il2elk9/modules
1221 22:55:17.925866 start: 4.1 power-off (timeout 00:00:30) [common]
1222 22:55:17.926430 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1223 22:55:17.959175 >> OK - accepted request
1224 22:55:17.961400 Returned 0 in 0 seconds
1225 22:55:18.062340 end: 4.1 power-off (duration 00:00:00) [common]
1227 22:55:18.063388 start: 4.2 read-feedback (timeout 00:10:00) [common]
1228 22:55:18.064325 Listened to connection for namespace 'common' for up to 1s
1229 22:55:19.064793 Finalising connection for namespace 'common'
1230 22:55:19.065582 Disconnecting from shell: Finalise
1231 22:55:19.066194 =>
1232 22:55:19.167315 end: 4.2 read-feedback (duration 00:00:01) [common]
1233 22:55:19.168214 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/963283
1234 22:55:22.305000 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/963283
1235 22:55:22.305637 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.