Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:59:27.788710 lava-dispatcher, installed at version: 2024.01
2 22:59:27.789521 start: 0 validate
3 22:59:27.790001 Start time: 2024-11-08 22:59:27.789970+00:00 (UTC)
4 22:59:27.790575 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:59:27.791118 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:59:27.833393 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:59:27.833977 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 22:59:27.865347 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:59:27.865970 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 22:59:27.894645 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:59:27.895155 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:59:27.925796 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 22:59:27.926320 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 22:59:27.964714 validate duration: 0.17
16 22:59:27.965558 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:59:27.965896 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:59:27.966220 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:59:27.966809 Not decompressing ramdisk as can be used compressed.
20 22:59:27.967264 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 22:59:27.967556 saving as /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/ramdisk/initrd.cpio.gz
22 22:59:27.967835 total size: 5628169 (5 MB)
23 22:59:28.002051 progress 0 % (0 MB)
24 22:59:28.009136 progress 5 % (0 MB)
25 22:59:28.017295 progress 10 % (0 MB)
26 22:59:28.024252 progress 15 % (0 MB)
27 22:59:28.028449 progress 20 % (1 MB)
28 22:59:28.032168 progress 25 % (1 MB)
29 22:59:28.036312 progress 30 % (1 MB)
30 22:59:28.040344 progress 35 % (1 MB)
31 22:59:28.044030 progress 40 % (2 MB)
32 22:59:28.048193 progress 45 % (2 MB)
33 22:59:28.051823 progress 50 % (2 MB)
34 22:59:28.055883 progress 55 % (2 MB)
35 22:59:28.059914 progress 60 % (3 MB)
36 22:59:28.063755 progress 65 % (3 MB)
37 22:59:28.067830 progress 70 % (3 MB)
38 22:59:28.071486 progress 75 % (4 MB)
39 22:59:28.075464 progress 80 % (4 MB)
40 22:59:28.079288 progress 85 % (4 MB)
41 22:59:28.083271 progress 90 % (4 MB)
42 22:59:28.086944 progress 95 % (5 MB)
43 22:59:28.090246 progress 100 % (5 MB)
44 22:59:28.090884 5 MB downloaded in 0.12 s (43.63 MB/s)
45 22:59:28.091425 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:59:28.092360 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:59:28.092658 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:59:28.092931 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:59:28.093395 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm64/defconfig/gcc-12/kernel/Image
51 22:59:28.093644 saving as /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/kernel/Image
52 22:59:28.093854 total size: 45713920 (43 MB)
53 22:59:28.094065 No compression specified
54 22:59:28.134277 progress 0 % (0 MB)
55 22:59:28.163071 progress 5 % (2 MB)
56 22:59:28.192195 progress 10 % (4 MB)
57 22:59:28.220886 progress 15 % (6 MB)
58 22:59:28.250147 progress 20 % (8 MB)
59 22:59:28.278431 progress 25 % (10 MB)
60 22:59:28.306916 progress 30 % (13 MB)
61 22:59:28.335493 progress 35 % (15 MB)
62 22:59:28.365050 progress 40 % (17 MB)
63 22:59:28.393551 progress 45 % (19 MB)
64 22:59:28.423031 progress 50 % (21 MB)
65 22:59:28.452378 progress 55 % (24 MB)
66 22:59:28.481243 progress 60 % (26 MB)
67 22:59:28.509858 progress 65 % (28 MB)
68 22:59:28.538932 progress 70 % (30 MB)
69 22:59:28.568332 progress 75 % (32 MB)
70 22:59:28.597243 progress 80 % (34 MB)
71 22:59:28.625742 progress 85 % (37 MB)
72 22:59:28.654625 progress 90 % (39 MB)
73 22:59:28.683907 progress 95 % (41 MB)
74 22:59:28.712118 progress 100 % (43 MB)
75 22:59:28.712660 43 MB downloaded in 0.62 s (70.45 MB/s)
76 22:59:28.713161 end: 1.2.1 http-download (duration 00:00:01) [common]
78 22:59:28.714010 end: 1.2 download-retry (duration 00:00:01) [common]
79 22:59:28.714306 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:59:28.714599 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:59:28.715086 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 22:59:28.715368 saving as /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/dtb/meson-g12b-a311d-libretech-cc.dtb
83 22:59:28.715588 total size: 54703 (0 MB)
84 22:59:28.715806 No compression specified
85 22:59:28.751643 progress 59 % (0 MB)
86 22:59:28.752527 progress 100 % (0 MB)
87 22:59:28.753100 0 MB downloaded in 0.04 s (1.39 MB/s)
88 22:59:28.753606 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:59:28.754448 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:59:28.754735 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:59:28.755020 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:59:28.755488 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 22:59:28.755740 saving as /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/nfsrootfs/full.rootfs.tar
95 22:59:28.755959 total size: 120894716 (115 MB)
96 22:59:28.756208 Using unxz to decompress xz
97 22:59:28.795098 progress 0 % (0 MB)
98 22:59:29.586462 progress 5 % (5 MB)
99 22:59:30.427356 progress 10 % (11 MB)
100 22:59:31.221803 progress 15 % (17 MB)
101 22:59:31.960322 progress 20 % (23 MB)
102 22:59:32.555696 progress 25 % (28 MB)
103 22:59:33.384525 progress 30 % (34 MB)
104 22:59:34.176459 progress 35 % (40 MB)
105 22:59:34.525238 progress 40 % (46 MB)
106 22:59:34.900862 progress 45 % (51 MB)
107 22:59:35.632262 progress 50 % (57 MB)
108 22:59:36.523519 progress 55 % (63 MB)
109 22:59:37.312897 progress 60 % (69 MB)
110 22:59:38.075650 progress 65 % (74 MB)
111 22:59:38.860103 progress 70 % (80 MB)
112 22:59:39.695068 progress 75 % (86 MB)
113 22:59:40.489993 progress 80 % (92 MB)
114 22:59:41.256313 progress 85 % (98 MB)
115 22:59:42.131418 progress 90 % (103 MB)
116 22:59:42.923797 progress 95 % (109 MB)
117 22:59:43.764095 progress 100 % (115 MB)
118 22:59:43.776600 115 MB downloaded in 15.02 s (7.68 MB/s)
119 22:59:43.777453 end: 1.4.1 http-download (duration 00:00:15) [common]
121 22:59:43.779031 end: 1.4 download-retry (duration 00:00:15) [common]
122 22:59:43.779540 start: 1.5 download-retry (timeout 00:09:44) [common]
123 22:59:43.780086 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 22:59:43.780878 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm64/defconfig/gcc-12/modules.tar.xz
125 22:59:43.781333 saving as /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/modules/modules.tar
126 22:59:43.781737 total size: 11613560 (11 MB)
127 22:59:43.782148 Using unxz to decompress xz
128 22:59:43.826842 progress 0 % (0 MB)
129 22:59:43.893162 progress 5 % (0 MB)
130 22:59:43.967372 progress 10 % (1 MB)
131 22:59:44.065572 progress 15 % (1 MB)
132 22:59:44.157895 progress 20 % (2 MB)
133 22:59:44.238883 progress 25 % (2 MB)
134 22:59:44.314475 progress 30 % (3 MB)
135 22:59:44.393314 progress 35 % (3 MB)
136 22:59:44.466231 progress 40 % (4 MB)
137 22:59:44.542255 progress 45 % (5 MB)
138 22:59:44.626750 progress 50 % (5 MB)
139 22:59:44.706031 progress 55 % (6 MB)
140 22:59:44.791154 progress 60 % (6 MB)
141 22:59:44.873509 progress 65 % (7 MB)
142 22:59:44.956977 progress 70 % (7 MB)
143 22:59:45.036158 progress 75 % (8 MB)
144 22:59:45.119446 progress 80 % (8 MB)
145 22:59:45.199277 progress 85 % (9 MB)
146 22:59:45.277690 progress 90 % (9 MB)
147 22:59:45.356255 progress 95 % (10 MB)
148 22:59:45.433100 progress 100 % (11 MB)
149 22:59:45.445265 11 MB downloaded in 1.66 s (6.66 MB/s)
150 22:59:45.445866 end: 1.5.1 http-download (duration 00:00:02) [common]
152 22:59:45.446694 end: 1.5 download-retry (duration 00:00:02) [common]
153 22:59:45.446963 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 22:59:45.447228 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 23:00:02.335161 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/963296/extract-nfsrootfs-ppjqdbmo
156 23:00:02.335755 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 23:00:02.336078 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 23:00:02.336799 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt
159 23:00:02.337277 makedir: /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin
160 23:00:02.337612 makedir: /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/tests
161 23:00:02.337920 makedir: /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/results
162 23:00:02.338255 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-add-keys
163 23:00:02.338783 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-add-sources
164 23:00:02.339289 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-background-process-start
165 23:00:02.339781 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-background-process-stop
166 23:00:02.340357 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-common-functions
167 23:00:02.340888 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-echo-ipv4
168 23:00:02.341425 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-install-packages
169 23:00:02.341899 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-installed-packages
170 23:00:02.342440 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-os-build
171 23:00:02.342926 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-probe-channel
172 23:00:02.343419 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-probe-ip
173 23:00:02.343892 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-target-ip
174 23:00:02.344408 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-target-mac
175 23:00:02.344910 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-target-storage
176 23:00:02.345438 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-test-case
177 23:00:02.345918 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-test-event
178 23:00:02.346392 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-test-feedback
179 23:00:02.346855 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-test-raise
180 23:00:02.347317 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-test-reference
181 23:00:02.347779 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-test-runner
182 23:00:02.348284 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-test-set
183 23:00:02.348781 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-test-shell
184 23:00:02.349312 Updating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-add-keys (debian)
185 23:00:02.349843 Updating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-add-sources (debian)
186 23:00:02.350342 Updating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-install-packages (debian)
187 23:00:02.350837 Updating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-installed-packages (debian)
188 23:00:02.351321 Updating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/bin/lava-os-build (debian)
189 23:00:02.351743 Creating /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/environment
190 23:00:02.352155 LAVA metadata
191 23:00:02.352424 - LAVA_JOB_ID=963296
192 23:00:02.352639 - LAVA_DISPATCHER_IP=192.168.6.2
193 23:00:02.353007 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 23:00:02.353955 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 23:00:02.354267 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 23:00:02.354477 skipped lava-vland-overlay
197 23:00:02.354717 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 23:00:02.354969 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 23:00:02.355185 skipped lava-multinode-overlay
200 23:00:02.355426 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 23:00:02.355675 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 23:00:02.355919 Loading test definitions
203 23:00:02.356253 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 23:00:02.356484 Using /lava-963296 at stage 0
205 23:00:02.357576 uuid=963296_1.6.2.4.1 testdef=None
206 23:00:02.357879 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 23:00:02.358139 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 23:00:02.359695 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 23:00:02.360520 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 23:00:02.362435 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 23:00:02.363256 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 23:00:02.365093 runner path: /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/0/tests/0_timesync-off test_uuid 963296_1.6.2.4.1
215 23:00:02.365635 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 23:00:02.366442 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 23:00:02.366666 Using /lava-963296 at stage 0
219 23:00:02.367012 Fetching tests from https://github.com/kernelci/test-definitions.git
220 23:00:02.367300 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/0/tests/1_kselftest-dt'
221 23:00:06.342954 Running '/usr/bin/git checkout kernelci.org
222 23:00:06.639064 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 23:00:06.640535 uuid=963296_1.6.2.4.5 testdef=None
224 23:00:06.640895 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 23:00:06.641661 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 23:00:06.644539 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 23:00:06.645377 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 23:00:06.649127 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 23:00:06.650002 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 23:00:06.653628 runner path: /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/0/tests/1_kselftest-dt test_uuid 963296_1.6.2.4.5
234 23:00:06.653918 BOARD='meson-g12b-a311d-libretech-cc'
235 23:00:06.654133 BRANCH='mainline'
236 23:00:06.654336 SKIPFILE='/dev/null'
237 23:00:06.654539 SKIP_INSTALL='True'
238 23:00:06.654738 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 23:00:06.654943 TST_CASENAME=''
240 23:00:06.655143 TST_CMDFILES='dt'
241 23:00:06.655739 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 23:00:06.656569 Creating lava-test-runner.conf files
244 23:00:06.656783 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/963296/lava-overlay-qce27xbt/lava-963296/0 for stage 0
245 23:00:06.657155 - 0_timesync-off
246 23:00:06.657406 - 1_kselftest-dt
247 23:00:06.657758 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 23:00:06.658055 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 23:00:30.119691 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 23:00:30.120156 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 23:00:30.120423 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 23:00:30.120695 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 23:00:30.120959 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 23:00:30.743400 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 23:00:30.743879 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 23:00:30.744177 extracting modules file /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/963296/extract-nfsrootfs-ppjqdbmo
257 23:00:32.257449 extracting modules file /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/963296/extract-overlay-ramdisk-okimap_0/ramdisk
258 23:00:33.681261 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 23:00:33.681737 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 23:00:33.682032 [common] Applying overlay to NFS
261 23:00:33.682257 [common] Applying overlay /var/lib/lava/dispatcher/tmp/963296/compress-overlay-l4c6kpw5/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/963296/extract-nfsrootfs-ppjqdbmo
262 23:00:36.469440 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 23:00:36.469911 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 23:00:36.470221 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 23:00:36.470482 Converting downloaded kernel to a uImage
266 23:00:36.470811 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/kernel/Image /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/kernel/uImage
267 23:00:36.998925 output: Image Name:
268 23:00:36.999343 output: Created: Fri Nov 8 23:00:36 2024
269 23:00:36.999553 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 23:00:36.999758 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 23:00:36.999960 output: Load Address: 01080000
272 23:00:37.000198 output: Entry Point: 01080000
273 23:00:37.000399 output:
274 23:00:37.000738 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 23:00:37.001004 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 23:00:37.001272 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 23:00:37.001528 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 23:00:37.001784 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 23:00:37.002048 Building ramdisk /var/lib/lava/dispatcher/tmp/963296/extract-overlay-ramdisk-okimap_0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/963296/extract-overlay-ramdisk-okimap_0/ramdisk
280 23:00:39.155585 >> 166827 blocks
281 23:00:46.907051 Adding RAMdisk u-boot header.
282 23:00:46.907746 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/963296/extract-overlay-ramdisk-okimap_0/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/963296/extract-overlay-ramdisk-okimap_0/ramdisk.cpio.gz.uboot
283 23:00:47.151012 output: Image Name:
284 23:00:47.151424 output: Created: Fri Nov 8 23:00:46 2024
285 23:00:47.151636 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 23:00:47.151841 output: Data Size: 23434223 Bytes = 22884.98 KiB = 22.35 MiB
287 23:00:47.152156 output: Load Address: 00000000
288 23:00:47.152562 output: Entry Point: 00000000
289 23:00:47.152960 output:
290 23:00:47.154067 rename /var/lib/lava/dispatcher/tmp/963296/extract-overlay-ramdisk-okimap_0/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/ramdisk/ramdisk.cpio.gz.uboot
291 23:00:47.154788 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 23:00:47.155331 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 23:00:47.155851 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 23:00:47.156343 No LXC device requested
295 23:00:47.156847 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 23:00:47.157352 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 23:00:47.157841 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 23:00:47.158251 Checking files for TFTP limit of 4294967296 bytes.
299 23:00:47.161019 end: 1 tftp-deploy (duration 00:01:19) [common]
300 23:00:47.161609 start: 2 uboot-action (timeout 00:05:00) [common]
301 23:00:47.162130 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 23:00:47.162625 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 23:00:47.163117 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 23:00:47.163644 Using kernel file from prepare-kernel: 963296/tftp-deploy-rhr89zsn/kernel/uImage
305 23:00:47.164312 substitutions:
306 23:00:47.164734 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 23:00:47.165136 - {DTB_ADDR}: 0x01070000
308 23:00:47.165534 - {DTB}: 963296/tftp-deploy-rhr89zsn/dtb/meson-g12b-a311d-libretech-cc.dtb
309 23:00:47.165933 - {INITRD}: 963296/tftp-deploy-rhr89zsn/ramdisk/ramdisk.cpio.gz.uboot
310 23:00:47.166327 - {KERNEL_ADDR}: 0x01080000
311 23:00:47.166717 - {KERNEL}: 963296/tftp-deploy-rhr89zsn/kernel/uImage
312 23:00:47.167110 - {LAVA_MAC}: None
313 23:00:47.167538 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/963296/extract-nfsrootfs-ppjqdbmo
314 23:00:47.167935 - {NFS_SERVER_IP}: 192.168.6.2
315 23:00:47.168360 - {PRESEED_CONFIG}: None
316 23:00:47.168753 - {PRESEED_LOCAL}: None
317 23:00:47.169143 - {RAMDISK_ADDR}: 0x08000000
318 23:00:47.169530 - {RAMDISK}: 963296/tftp-deploy-rhr89zsn/ramdisk/ramdisk.cpio.gz.uboot
319 23:00:47.169917 - {ROOT_PART}: None
320 23:00:47.170302 - {ROOT}: None
321 23:00:47.170687 - {SERVER_IP}: 192.168.6.2
322 23:00:47.171068 - {TEE_ADDR}: 0x83000000
323 23:00:47.171451 - {TEE}: None
324 23:00:47.171833 Parsed boot commands:
325 23:00:47.172231 - setenv autoload no
326 23:00:47.172616 - setenv initrd_high 0xffffffff
327 23:00:47.172999 - setenv fdt_high 0xffffffff
328 23:00:47.173380 - dhcp
329 23:00:47.173759 - setenv serverip 192.168.6.2
330 23:00:47.174147 - tftpboot 0x01080000 963296/tftp-deploy-rhr89zsn/kernel/uImage
331 23:00:47.174534 - tftpboot 0x08000000 963296/tftp-deploy-rhr89zsn/ramdisk/ramdisk.cpio.gz.uboot
332 23:00:47.174920 - tftpboot 0x01070000 963296/tftp-deploy-rhr89zsn/dtb/meson-g12b-a311d-libretech-cc.dtb
333 23:00:47.175304 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/963296/extract-nfsrootfs-ppjqdbmo,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 23:00:47.175699 - bootm 0x01080000 0x08000000 0x01070000
335 23:00:47.176226 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 23:00:47.177710 start: 2.3 connect-device (timeout 00:05:00) [common]
338 23:00:47.178124 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 23:00:47.193568 Setting prompt string to ['lava-test: # ']
340 23:00:47.195090 end: 2.3 connect-device (duration 00:00:00) [common]
341 23:00:47.195693 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 23:00:47.196320 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 23:00:47.196852 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 23:00:47.197976 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 23:00:47.241218 >> OK - accepted request
346 23:00:47.243550 Returned 0 in 0 seconds
347 23:00:47.344780 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 23:00:47.346566 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 23:00:47.347171 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 23:00:47.347722 Setting prompt string to ['Hit any key to stop autoboot']
352 23:00:47.348293 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 23:00:47.349906 Trying 192.168.56.21...
354 23:00:47.350381 Connected to conserv1.
355 23:00:47.350789 Escape character is '^]'.
356 23:00:47.351199
357 23:00:47.351610 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 23:00:47.352064
359 23:00:58.660443 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 23:00:58.660894 bl2_stage_init 0x01
361 23:00:58.661131 bl2_stage_init 0x81
362 23:00:58.666056 hw id: 0x0000 - pwm id 0x01
363 23:00:58.666497 bl2_stage_init 0xc1
364 23:00:58.666734 bl2_stage_init 0x02
365 23:00:58.666944
366 23:00:58.672063 L0:00000000
367 23:00:58.672507 L1:20000703
368 23:00:58.672744 L2:00008067
369 23:00:58.672968 L3:14000000
370 23:00:58.677269 B2:00402000
371 23:00:58.677669 B1:e0f83180
372 23:00:58.677883
373 23:00:58.678098 TE: 58167
374 23:00:58.678322
375 23:00:58.682838 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 23:00:58.683457
377 23:00:58.683904 Board ID = 1
378 23:00:58.688331 Set A53 clk to 24M
379 23:00:58.688826 Set A73 clk to 24M
380 23:00:58.689258 Set clk81 to 24M
381 23:00:58.693909 A53 clk: 1200 MHz
382 23:00:58.694387 A73 clk: 1200 MHz
383 23:00:58.694814 CLK81: 166.6M
384 23:00:58.695236 smccc: 00012abd
385 23:00:58.699526 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 23:00:58.705231 board id: 1
387 23:00:58.711050 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 23:00:58.721975 fw parse done
389 23:00:58.727417 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 23:00:58.770363 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 23:00:58.781243 PIEI prepare done
392 23:00:58.781731 fastboot data load
393 23:00:58.782170 fastboot data verify
394 23:00:58.786800 verify result: 266
395 23:00:58.792508 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 23:00:58.793075 LPDDR4 probe
397 23:00:58.793586 ddr clk to 1584MHz
398 23:00:58.799637 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 23:00:58.836813
400 23:00:58.837422 dmc_version 0001
401 23:00:58.843507 Check phy result
402 23:00:58.850251 INFO : End of CA training
403 23:00:58.850799 INFO : End of initialization
404 23:00:58.855933 INFO : Training has run successfully!
405 23:00:58.856499 Check phy result
406 23:00:58.861508 INFO : End of initialization
407 23:00:58.862038 INFO : End of read enable training
408 23:00:58.867075 INFO : End of fine write leveling
409 23:00:58.872723 INFO : End of Write leveling coarse delay
410 23:00:58.873250 INFO : Training has run successfully!
411 23:00:58.873688 Check phy result
412 23:00:58.878280 INFO : End of initialization
413 23:00:58.878755 INFO : End of read dq deskew training
414 23:00:58.883848 INFO : End of MPR read delay center optimization
415 23:00:58.889436 INFO : End of write delay center optimization
416 23:00:58.895082 INFO : End of read delay center optimization
417 23:00:58.895613 INFO : End of max read latency training
418 23:00:58.900644 INFO : Training has run successfully!
419 23:00:58.901108 1D training succeed
420 23:00:58.909012 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 23:00:58.956597 Check phy result
422 23:00:58.957253 INFO : End of initialization
423 23:00:58.979118 INFO : End of 2D read delay Voltage center optimization
424 23:00:58.998398 INFO : End of 2D read delay Voltage center optimization
425 23:00:59.051481 INFO : End of 2D write delay Voltage center optimization
426 23:00:59.100884 INFO : End of 2D write delay Voltage center optimization
427 23:00:59.106258 INFO : Training has run successfully!
428 23:00:59.106755
429 23:00:59.107206 channel==0
430 23:00:59.111948 RxClkDly_Margin_A0==88 ps 9
431 23:00:59.112528 TxDqDly_Margin_A0==98 ps 10
432 23:00:59.117513 RxClkDly_Margin_A1==88 ps 9
433 23:00:59.117993 TxDqDly_Margin_A1==98 ps 10
434 23:00:59.118442 TrainedVREFDQ_A0==74
435 23:00:59.123066 TrainedVREFDQ_A1==74
436 23:00:59.123545 VrefDac_Margin_A0==25
437 23:00:59.124024 DeviceVref_Margin_A0==40
438 23:00:59.128731 VrefDac_Margin_A1==25
439 23:00:59.129208 DeviceVref_Margin_A1==40
440 23:00:59.129656
441 23:00:59.130100
442 23:00:59.134243 channel==1
443 23:00:59.134790 RxClkDly_Margin_A0==98 ps 10
444 23:00:59.135253 TxDqDly_Margin_A0==98 ps 10
445 23:00:59.140139 RxClkDly_Margin_A1==98 ps 10
446 23:00:59.140667 TxDqDly_Margin_A1==88 ps 9
447 23:00:59.145452 TrainedVREFDQ_A0==77
448 23:00:59.145988 TrainedVREFDQ_A1==77
449 23:00:59.146450 VrefDac_Margin_A0==22
450 23:00:59.151051 DeviceVref_Margin_A0==37
451 23:00:59.151590 VrefDac_Margin_A1==22
452 23:00:59.156781 DeviceVref_Margin_A1==37
453 23:00:59.157333
454 23:00:59.157782 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 23:00:59.162277
456 23:00:59.190285 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000019 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 23:00:59.191003 2D training succeed
458 23:00:59.196172 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 23:00:59.201589 auto size-- 65535DDR cs0 size: 2048MB
460 23:00:59.202156 DDR cs1 size: 2048MB
461 23:00:59.207225 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 23:00:59.207803 cs0 DataBus test pass
463 23:00:59.212810 cs1 DataBus test pass
464 23:00:59.213347 cs0 AddrBus test pass
465 23:00:59.213795 cs1 AddrBus test pass
466 23:00:59.214242
467 23:00:59.218430 100bdlr_step_size ps== 420
468 23:00:59.218985 result report
469 23:00:59.224052 boot times 0Enable ddr reg access
470 23:00:59.229450 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 23:00:59.243040 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 23:00:59.816587 0.0;M3 CHK:0;cm4_sp_mode 0
473 23:00:59.817286 MVN_1=0x00000000
474 23:00:59.822134 MVN_2=0x00000000
475 23:00:59.827732 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 23:00:59.828314 OPS=0x10
477 23:00:59.828805 ring efuse init
478 23:00:59.829277 chipver efuse init
479 23:00:59.836081 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 23:00:59.836895 [0.018961 Inits done]
481 23:00:59.842714 secure task start!
482 23:00:59.843315 high task start!
483 23:00:59.843810 low task start!
484 23:00:59.844287 run into bl31
485 23:00:59.850232 NOTICE: BL31: v1.3(release):4fc40b1
486 23:00:59.857066 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 23:00:59.857632 NOTICE: BL31: G12A normal boot!
488 23:00:59.883370 NOTICE: BL31: BL33 decompress pass
489 23:00:59.888375 ERROR: Error initializing runtime service opteed_fast
490 23:01:01.121852
491 23:01:01.122266
492 23:01:01.130263 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 23:01:01.130739
494 23:01:01.131078 Model: Libre Computer AML-A311D-CC Alta
495 23:01:01.340151 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 23:01:01.362238 DRAM: 2 GiB (effective 3.8 GiB)
497 23:01:01.505233 Core: 408 devices, 31 uclasses, devicetree: separate
498 23:01:01.511079 WDT: Not starting watchdog@f0d0
499 23:01:01.543274 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 23:01:01.555867 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 23:01:01.560697 ** Bad device specification mmc 0 **
502 23:01:01.571169 Card did not respond to voltage select! : -110
503 23:01:01.578674 ** Bad device specification mmc 0 **
504 23:01:01.579196 Couldn't find partition mmc 0
505 23:01:01.587037 Card did not respond to voltage select! : -110
506 23:01:01.592538 ** Bad device specification mmc 0 **
507 23:01:01.592940 Couldn't find partition mmc 0
508 23:01:01.597557 Error: could not access storage.
509 23:01:02.861682 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
510 23:01:02.862316 bl2_stage_init 0x81
511 23:01:02.866896 hw id: 0x0000 - pwm id 0x01
512 23:01:02.867231 bl2_stage_init 0xc1
513 23:01:02.867468 bl2_stage_init 0x02
514 23:01:02.867683
515 23:01:02.872435 L0:00000000
516 23:01:02.872906 L1:20000703
517 23:01:02.873184 L2:00008067
518 23:01:02.873447 L3:14000000
519 23:01:02.873703 B2:00402000
520 23:01:02.875376 B1:e0f83180
521 23:01:02.875794
522 23:01:02.876193 TE: 58150
523 23:01:02.876515
524 23:01:02.886501 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 23:01:02.887237
526 23:01:02.887727 Board ID = 1
527 23:01:02.888196 Set A53 clk to 24M
528 23:01:02.888626 Set A73 clk to 24M
529 23:01:02.892265 Set clk81 to 24M
530 23:01:02.892766 A53 clk: 1200 MHz
531 23:01:02.893085 A73 clk: 1200 MHz
532 23:01:02.897661 CLK81: 166.6M
533 23:01:02.898130 smccc: 00012aac
534 23:01:02.903335 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 23:01:02.903971 board id: 1
536 23:01:02.912041 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 23:01:02.922774 fw parse done
538 23:01:02.928584 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 23:01:02.971101 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 23:01:02.981985 PIEI prepare done
541 23:01:02.982509 fastboot data load
542 23:01:02.982814 fastboot data verify
543 23:01:02.987845 verify result: 266
544 23:01:03.263094 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 23:01:03.263637 LPDDR4 probe
546 23:01:03.263944 ddr clk to 1584MHz
547 23:01:03.264291 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 23:01:03.264597
549 23:01:03.264889 dmc_version 0001
550 23:01:03.265170 Check phy result
551 23:01:03.265469 INFO : End of CA training
552 23:01:03.265795 INFO : End of initialization
553 23:01:03.266302 INFO : Training has run successfully!
554 23:01:03.267058 Check phy result
555 23:01:03.267461 INFO : End of initialization
556 23:01:03.267774 INFO : End of read enable training
557 23:01:03.268102 INFO : End of fine write leveling
558 23:01:03.268402 INFO : End of Write leveling coarse delay
559 23:01:03.268732 INFO : Training has run successfully!
560 23:01:03.269030 Check phy result
561 23:01:03.269329 INFO : End of initialization
562 23:01:03.269620 INFO : End of read dq deskew training
563 23:01:03.270123 INFO : End of MPR read delay center optimization
564 23:01:03.270486 INFO : End of write delay center optimization
565 23:01:03.270791 INFO : End of read delay center optimization
566 23:01:03.271065 INFO : End of max read latency training
567 23:01:03.271374 INFO : Training has run successfully!
568 23:01:03.271666 1D training succeed
569 23:01:03.272002 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 23:01:03.272334 Check phy result
571 23:01:03.272655 INFO : End of initialization
572 23:01:03.272963 INFO : End of 2D read delay Voltage center optimization
573 23:01:03.273249 INFO : End of 2D read delay Voltage center optimization
574 23:01:03.273559 INFO : End of 2D write delay Voltage center optimization
575 23:01:03.301828 INFO : End of 2D write delay Voltage center optimization
576 23:01:03.307217 INFO : Training has run successfully!
577 23:01:03.307929
578 23:01:03.308332 channel==0
579 23:01:03.313173 RxClkDly_Margin_A0==88 ps 9
580 23:01:03.313930 TxDqDly_Margin_A0==98 ps 10
581 23:01:03.318779 RxClkDly_Margin_A1==88 ps 9
582 23:01:03.319308 TxDqDly_Margin_A1==88 ps 9
583 23:01:03.319574 TrainedVREFDQ_A0==74
584 23:01:03.324066 TrainedVREFDQ_A1==74
585 23:01:03.324601 VrefDac_Margin_A0==25
586 23:01:03.324899 DeviceVref_Margin_A0==40
587 23:01:03.330685 VrefDac_Margin_A1==25
588 23:01:03.331350 DeviceVref_Margin_A1==40
589 23:01:03.331709
590 23:01:03.332009
591 23:01:03.332339 channel==1
592 23:01:03.335171 RxClkDly_Margin_A0==98 ps 10
593 23:01:03.335874 TxDqDly_Margin_A0==88 ps 9
594 23:01:03.341032 RxClkDly_Margin_A1==98 ps 10
595 23:01:03.341560 TxDqDly_Margin_A1==88 ps 9
596 23:01:03.346322 TrainedVREFDQ_A0==77
597 23:01:03.346818 TrainedVREFDQ_A1==77
598 23:01:03.347138 VrefDac_Margin_A0==22
599 23:01:03.351976 DeviceVref_Margin_A0==37
600 23:01:03.352720 VrefDac_Margin_A1==22
601 23:01:03.357612 DeviceVref_Margin_A1==37
602 23:01:03.358388
603 23:01:03.358795 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 23:01:03.359097
605 23:01:03.391215 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
606 23:01:03.391785 2D training succeed
607 23:01:03.396978 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 23:01:03.402451 auto size-- 65535DDR cs0 size: 2048MB
609 23:01:03.402967 DDR cs1 size: 2048MB
610 23:01:03.408049 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 23:01:03.408761 cs0 DataBus test pass
612 23:01:03.414575 cs1 DataBus test pass
613 23:01:03.415029 cs0 AddrBus test pass
614 23:01:03.415262 cs1 AddrBus test pass
615 23:01:03.415484
616 23:01:03.419155 100bdlr_step_size ps== 420
617 23:01:03.419735 result report
618 23:01:03.424793 boot times 0Enable ddr reg access
619 23:01:03.430061 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 23:01:03.443555 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 23:01:04.017155 0.0;M3 CHK:0;cm4_sp_mode 0
622 23:01:04.017605 MVN_1=0x00000000
623 23:01:04.022721 MVN_2=0x00000000
624 23:01:04.028395 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 23:01:04.028710 OPS=0x10
626 23:01:04.028917 ring efuse init
627 23:01:04.029118 chipver efuse init
628 23:01:04.033959 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 23:01:04.039565 [0.018961 Inits done]
630 23:01:04.040113 secure task start!
631 23:01:04.040551 high task start!
632 23:01:04.044166 low task start!
633 23:01:04.044660 run into bl31
634 23:01:04.050786 NOTICE: BL31: v1.3(release):4fc40b1
635 23:01:04.058630 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 23:01:04.059174 NOTICE: BL31: G12A normal boot!
637 23:01:04.084151 NOTICE: BL31: BL33 decompress pass
638 23:01:04.089693 ERROR: Error initializing runtime service opteed_fast
639 23:01:05.322482
640 23:01:05.322907
641 23:01:05.330985 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 23:01:05.331441
643 23:01:05.331783 Model: Libre Computer AML-A311D-CC Alta
644 23:01:05.539433 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 23:01:05.562997 DRAM: 2 GiB (effective 3.8 GiB)
646 23:01:05.705857 Core: 408 devices, 31 uclasses, devicetree: separate
647 23:01:05.711630 WDT: Not starting watchdog@f0d0
648 23:01:05.743795 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 23:01:05.756244 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 23:01:05.761097 ** Bad device specification mmc 0 **
651 23:01:05.771563 Card did not respond to voltage select! : -110
652 23:01:05.779203 ** Bad device specification mmc 0 **
653 23:01:05.779657 Couldn't find partition mmc 0
654 23:01:05.787555 Card did not respond to voltage select! : -110
655 23:01:05.793185 ** Bad device specification mmc 0 **
656 23:01:05.793638 Couldn't find partition mmc 0
657 23:01:05.798235 Error: could not access storage.
658 23:01:06.140699 Net: eth0: ethernet@ff3f0000
659 23:01:06.141128 starting USB...
660 23:01:06.392754 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 23:01:06.393378 Starting the controller
662 23:01:06.399411 USB XHCI 1.10
663 23:01:08.110290 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
664 23:01:08.110988 bl2_stage_init 0x01
665 23:01:08.111457 bl2_stage_init 0x81
666 23:01:08.115633 hw id: 0x0000 - pwm id 0x01
667 23:01:08.116195 bl2_stage_init 0xc1
668 23:01:08.116659 bl2_stage_init 0x02
669 23:01:08.117106
670 23:01:08.121207 L0:00000000
671 23:01:08.121722 L1:20000703
672 23:01:08.122174 L2:00008067
673 23:01:08.122620 L3:14000000
674 23:01:08.126854 B2:00402000
675 23:01:08.127366 B1:e0f83180
676 23:01:08.127817
677 23:01:08.128306 TE: 58159
678 23:01:08.128752
679 23:01:08.132448 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 23:01:08.132966
681 23:01:08.133424 Board ID = 1
682 23:01:08.138098 Set A53 clk to 24M
683 23:01:08.138629 Set A73 clk to 24M
684 23:01:08.139094 Set clk81 to 24M
685 23:01:08.143634 A53 clk: 1200 MHz
686 23:01:08.144178 A73 clk: 1200 MHz
687 23:01:08.144636 CLK81: 166.6M
688 23:01:08.145078 smccc: 00012ab5
689 23:01:08.149224 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 23:01:08.154846 board id: 1
691 23:01:08.160809 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 23:01:08.171364 fw parse done
693 23:01:08.177386 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 23:01:08.219817 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 23:01:08.230686 PIEI prepare done
696 23:01:08.231206 fastboot data load
697 23:01:08.231666 fastboot data verify
698 23:01:08.236318 verify result: 266
699 23:01:08.241972 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 23:01:08.242506 LPDDR4 probe
701 23:01:08.242973 ddr clk to 1584MHz
702 23:01:08.250143 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 23:01:08.287180
704 23:01:08.287727 dmc_version 0001
705 23:01:08.292850 Check phy result
706 23:01:08.299740 INFO : End of CA training
707 23:01:08.300315 INFO : End of initialization
708 23:01:08.305372 INFO : Training has run successfully!
709 23:01:08.305883 Check phy result
710 23:01:08.310952 INFO : End of initialization
711 23:01:08.311458 INFO : End of read enable training
712 23:01:08.314256 INFO : End of fine write leveling
713 23:01:08.319853 INFO : End of Write leveling coarse delay
714 23:01:08.325501 INFO : Training has run successfully!
715 23:01:08.326011 Check phy result
716 23:01:08.326460 INFO : End of initialization
717 23:01:08.331150 INFO : End of read dq deskew training
718 23:01:08.336681 INFO : End of MPR read delay center optimization
719 23:01:08.337210 INFO : End of write delay center optimization
720 23:01:08.342299 INFO : End of read delay center optimization
721 23:01:08.347865 INFO : End of max read latency training
722 23:01:08.348428 INFO : Training has run successfully!
723 23:01:08.353413 1D training succeed
724 23:01:08.359377 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 23:01:08.407094 Check phy result
726 23:01:08.407714 INFO : End of initialization
727 23:01:08.428855 INFO : End of 2D read delay Voltage center optimization
728 23:01:08.448954 INFO : End of 2D read delay Voltage center optimization
729 23:01:08.500893 INFO : End of 2D write delay Voltage center optimization
730 23:01:08.550443 INFO : End of 2D write delay Voltage center optimization
731 23:01:08.556026 INFO : Training has run successfully!
732 23:01:08.556571
733 23:01:08.557036 channel==0
734 23:01:08.561513 RxClkDly_Margin_A0==88 ps 9
735 23:01:08.562040 TxDqDly_Margin_A0==98 ps 10
736 23:01:08.567144 RxClkDly_Margin_A1==88 ps 9
737 23:01:08.567667 TxDqDly_Margin_A1==98 ps 10
738 23:01:08.568270 TrainedVREFDQ_A0==74
739 23:01:08.572705 TrainedVREFDQ_A1==74
740 23:01:08.573271 VrefDac_Margin_A0==25
741 23:01:08.573729 DeviceVref_Margin_A0==40
742 23:01:08.578244 VrefDac_Margin_A1==25
743 23:01:08.578770 DeviceVref_Margin_A1==40
744 23:01:08.579217
745 23:01:08.579661
746 23:01:08.583805 channel==1
747 23:01:08.584352 RxClkDly_Margin_A0==98 ps 10
748 23:01:08.584800 TxDqDly_Margin_A0==88 ps 9
749 23:01:08.589392 RxClkDly_Margin_A1==98 ps 10
750 23:01:08.589910 TxDqDly_Margin_A1==88 ps 9
751 23:01:08.595073 TrainedVREFDQ_A0==74
752 23:01:08.595608 TrainedVREFDQ_A1==77
753 23:01:08.596091 VrefDac_Margin_A0==22
754 23:01:08.600664 DeviceVref_Margin_A0==40
755 23:01:08.601182 VrefDac_Margin_A1==24
756 23:01:08.606282 DeviceVref_Margin_A1==37
757 23:01:08.606836
758 23:01:08.607291 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 23:01:08.607738
760 23:01:08.639777 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
761 23:01:08.640432 2D training succeed
762 23:01:08.645431 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 23:01:08.651009 auto size-- 65535DDR cs0 size: 2048MB
764 23:01:08.651548 DDR cs1 size: 2048MB
765 23:01:08.656601 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 23:01:08.657129 cs0 DataBus test pass
767 23:01:08.662292 cs1 DataBus test pass
768 23:01:08.662859 cs0 AddrBus test pass
769 23:01:08.663312 cs1 AddrBus test pass
770 23:01:08.663753
771 23:01:08.667831 100bdlr_step_size ps== 420
772 23:01:08.668397 result report
773 23:01:08.673415 boot times 0Enable ddr reg access
774 23:01:08.678765 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 23:01:08.692251 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 23:01:09.265971 0.0;M3 CHK:0;cm4_sp_mode 0
777 23:01:09.266645 MVN_1=0x00000000
778 23:01:09.271440 MVN_2=0x00000000
779 23:01:09.277227 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 23:01:09.277811 OPS=0x10
781 23:01:09.278261 ring efuse init
782 23:01:09.278694 chipver efuse init
783 23:01:09.282765 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 23:01:09.288322 [0.018961 Inits done]
785 23:01:09.288844 secure task start!
786 23:01:09.289276 high task start!
787 23:01:09.292898 low task start!
788 23:01:09.293393 run into bl31
789 23:01:09.299554 NOTICE: BL31: v1.3(release):4fc40b1
790 23:01:09.307427 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 23:01:09.307971 NOTICE: BL31: G12A normal boot!
792 23:01:09.332799 NOTICE: BL31: BL33 decompress pass
793 23:01:09.338472 ERROR: Error initializing runtime service opteed_fast
794 23:01:10.571174
795 23:01:10.571602
796 23:01:10.579220 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 23:01:10.579638
798 23:01:10.579962 Model: Libre Computer AML-A311D-CC Alta
799 23:01:10.788134 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 23:01:10.811405 DRAM: 2 GiB (effective 3.8 GiB)
801 23:01:10.954419 Core: 408 devices, 31 uclasses, devicetree: separate
802 23:01:10.960323 WDT: Not starting watchdog@f0d0
803 23:01:10.992489 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 23:01:11.004976 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 23:01:11.009949 ** Bad device specification mmc 0 **
806 23:01:11.020379 Card did not respond to voltage select! : -110
807 23:01:11.027976 ** Bad device specification mmc 0 **
808 23:01:11.028502 Couldn't find partition mmc 0
809 23:01:11.036304 Card did not respond to voltage select! : -110
810 23:01:11.041778 ** Bad device specification mmc 0 **
811 23:01:11.042256 Couldn't find partition mmc 0
812 23:01:11.046837 Error: could not access storage.
813 23:01:11.389457 Net: eth0: ethernet@ff3f0000
814 23:01:11.390069 starting USB...
815 23:01:11.641226 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 23:01:11.641844 Starting the controller
817 23:01:11.648070 USB XHCI 1.10
818 23:01:13.741662 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 23:01:13.742284 bl2_stage_init 0x01
820 23:01:13.742711 bl2_stage_init 0x81
821 23:01:13.747126 hw id: 0x0000 - pwm id 0x01
822 23:01:13.747578 bl2_stage_init 0xc1
823 23:01:13.748033 bl2_stage_init 0x02
824 23:01:13.748450
825 23:01:13.752803 L0:00000000
826 23:01:13.753249 L1:20000703
827 23:01:13.753651 L2:00008067
828 23:01:13.754045 L3:14000000
829 23:01:13.755585 B2:00402000
830 23:01:13.756055 B1:e0f83180
831 23:01:13.756453
832 23:01:13.756840 TE: 58159
833 23:01:13.757224
834 23:01:13.766733 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 23:01:13.767217
836 23:01:13.767637 Board ID = 1
837 23:01:13.768076 Set A53 clk to 24M
838 23:01:13.768488 Set A73 clk to 24M
839 23:01:13.772203 Set clk81 to 24M
840 23:01:13.772636 A53 clk: 1200 MHz
841 23:01:13.773041 A73 clk: 1200 MHz
842 23:01:13.776324 CLK81: 166.6M
843 23:01:13.776768 smccc: 00012ab5
844 23:01:13.781362 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 23:01:13.787007 board id: 1
846 23:01:13.791194 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 23:01:13.802738 fw parse done
848 23:01:13.808780 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 23:01:13.851377 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 23:01:13.862327 PIEI prepare done
851 23:01:13.862786 fastboot data load
852 23:01:13.863200 fastboot data verify
853 23:01:13.867885 verify result: 266
854 23:01:13.873509 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 23:01:13.873955 LPDDR4 probe
856 23:01:13.874359 ddr clk to 1584MHz
857 23:01:13.879428 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 23:01:13.918735
859 23:01:13.919207 dmc_version 0001
860 23:01:13.925393 Check phy result
861 23:01:13.931263 INFO : End of CA training
862 23:01:13.931729 INFO : End of initialization
863 23:01:13.936886 INFO : Training has run successfully!
864 23:01:13.937326 Check phy result
865 23:01:13.942407 INFO : End of initialization
866 23:01:13.942843 INFO : End of read enable training
867 23:01:13.948085 INFO : End of fine write leveling
868 23:01:13.953719 INFO : End of Write leveling coarse delay
869 23:01:13.954148 INFO : Training has run successfully!
870 23:01:13.954554 Check phy result
871 23:01:13.959236 INFO : End of initialization
872 23:01:13.959669 INFO : End of read dq deskew training
873 23:01:13.964866 INFO : End of MPR read delay center optimization
874 23:01:13.970435 INFO : End of write delay center optimization
875 23:01:13.976075 INFO : End of read delay center optimization
876 23:01:13.976514 INFO : End of max read latency training
877 23:01:13.981740 INFO : Training has run successfully!
878 23:01:13.982171 1D training succeed
879 23:01:13.990818 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 23:01:14.038502 Check phy result
881 23:01:14.039100 INFO : End of initialization
882 23:01:14.060278 INFO : End of 2D read delay Voltage center optimization
883 23:01:14.079624 INFO : End of 2D read delay Voltage center optimization
884 23:01:14.132617 INFO : End of 2D write delay Voltage center optimization
885 23:01:14.182171 INFO : End of 2D write delay Voltage center optimization
886 23:01:14.187607 INFO : Training has run successfully!
887 23:01:14.188104
888 23:01:14.188527 channel==0
889 23:01:14.193223 RxClkDly_Margin_A0==88 ps 9
890 23:01:14.193663 TxDqDly_Margin_A0==98 ps 10
891 23:01:14.198765 RxClkDly_Margin_A1==88 ps 9
892 23:01:14.199197 TxDqDly_Margin_A1==98 ps 10
893 23:01:14.199607 TrainedVREFDQ_A0==74
894 23:01:14.204309 TrainedVREFDQ_A1==74
895 23:01:14.204743 VrefDac_Margin_A0==25
896 23:01:14.205142 DeviceVref_Margin_A0==40
897 23:01:14.209888 VrefDac_Margin_A1==23
898 23:01:14.210321 DeviceVref_Margin_A1==40
899 23:01:14.210724
900 23:01:14.211116
901 23:01:14.215562 channel==1
902 23:01:14.216017 RxClkDly_Margin_A0==98 ps 10
903 23:01:14.216422 TxDqDly_Margin_A0==98 ps 10
904 23:01:14.221132 RxClkDly_Margin_A1==98 ps 10
905 23:01:14.221554 TxDqDly_Margin_A1==88 ps 9
906 23:01:14.226697 TrainedVREFDQ_A0==77
907 23:01:14.227121 TrainedVREFDQ_A1==77
908 23:01:14.227526 VrefDac_Margin_A0==22
909 23:01:14.232269 DeviceVref_Margin_A0==37
910 23:01:14.232693 VrefDac_Margin_A1==22
911 23:01:14.237965 DeviceVref_Margin_A1==37
912 23:01:14.238441
913 23:01:14.238848 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 23:01:14.243593
915 23:01:14.271508 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
916 23:01:14.272009 2D training succeed
917 23:01:14.277163 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 23:01:14.282613 auto size-- 65535DDR cs0 size: 2048MB
919 23:01:14.283084 DDR cs1 size: 2048MB
920 23:01:14.288193 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 23:01:14.288612 cs0 DataBus test pass
922 23:01:14.293813 cs1 DataBus test pass
923 23:01:14.294248 cs0 AddrBus test pass
924 23:01:14.294630 cs1 AddrBus test pass
925 23:01:14.295015
926 23:01:14.299389 100bdlr_step_size ps== 420
927 23:01:14.299817 result report
928 23:01:14.304976 boot times 0Enable ddr reg access
929 23:01:14.310444 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 23:01:14.323954 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 23:01:14.897570 0.0;M3 CHK:0;cm4_sp_mode 0
932 23:01:14.898191 MVN_1=0x00000000
933 23:01:14.903084 MVN_2=0x00000000
934 23:01:14.908787 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 23:01:14.909228 OPS=0x10
936 23:01:14.909636 ring efuse init
937 23:01:14.910029 chipver efuse init
938 23:01:14.914396 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 23:01:14.920068 [0.018961 Inits done]
940 23:01:14.920510 secure task start!
941 23:01:14.920915 high task start!
942 23:01:14.923691 low task start!
943 23:01:14.924152 run into bl31
944 23:01:14.931261 NOTICE: BL31: v1.3(release):4fc40b1
945 23:01:14.939077 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 23:01:14.939831 NOTICE: BL31: G12A normal boot!
947 23:01:14.965024 NOTICE: BL31: BL33 decompress pass
948 23:01:14.970643 ERROR: Error initializing runtime service opteed_fast
949 23:01:16.203580
950 23:01:16.204235
951 23:01:16.211038 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 23:01:16.211492
953 23:01:16.211905 Model: Libre Computer AML-A311D-CC Alta
954 23:01:16.420416 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 23:01:16.443730 DRAM: 2 GiB (effective 3.8 GiB)
956 23:01:16.586869 Core: 408 devices, 31 uclasses, devicetree: separate
957 23:01:16.591730 WDT: Not starting watchdog@f0d0
958 23:01:16.624974 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 23:01:16.637266 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 23:01:16.642267 ** Bad device specification mmc 0 **
961 23:01:16.652728 Card did not respond to voltage select! : -110
962 23:01:16.659317 ** Bad device specification mmc 0 **
963 23:01:16.659764 Couldn't find partition mmc 0
964 23:01:16.668638 Card did not respond to voltage select! : -110
965 23:01:16.674209 ** Bad device specification mmc 0 **
966 23:01:16.674642 Couldn't find partition mmc 0
967 23:01:16.678198 Error: could not access storage.
968 23:01:17.021822 Net: eth0: ethernet@ff3f0000
969 23:01:17.022229 starting USB...
970 23:01:17.274564 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 23:01:17.274940 Starting the controller
972 23:01:17.281466 USB XHCI 1.10
973 23:01:19.141311 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
974 23:01:19.141925 bl2_stage_init 0x81
975 23:01:19.146854 hw id: 0x0000 - pwm id 0x01
976 23:01:19.147148 bl2_stage_init 0xc1
977 23:01:19.147390 bl2_stage_init 0x02
978 23:01:19.147618
979 23:01:19.152431 L0:00000000
980 23:01:19.152969 L1:20000703
981 23:01:19.153336 L2:00008067
982 23:01:19.153699 L3:14000000
983 23:01:19.154061 B2:00402000
984 23:01:19.155250 B1:e0f83180
985 23:01:19.155645
986 23:01:19.156031 TE: 58150
987 23:01:19.156376
988 23:01:19.166417 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
989 23:01:19.166718
990 23:01:19.166952 Board ID = 1
991 23:01:19.167185 Set A53 clk to 24M
992 23:01:19.167409 Set A73 clk to 24M
993 23:01:19.172052 Set clk81 to 24M
994 23:01:19.172436 A53 clk: 1200 MHz
995 23:01:19.172792 A73 clk: 1200 MHz
996 23:01:19.177615 CLK81: 166.6M
997 23:01:19.178132 smccc: 00012aac
998 23:01:19.183232 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
999 23:01:19.183625 board id: 1
1000 23:01:19.191865 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1001 23:01:19.202580 fw parse done
1002 23:01:19.208488 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1003 23:01:19.250405 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1004 23:01:19.262208 PIEI prepare done
1005 23:01:19.262780 fastboot data load
1006 23:01:19.263073 fastboot data verify
1007 23:01:19.267825 verify result: 266
1008 23:01:19.273379 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1009 23:01:19.273752 LPDDR4 probe
1010 23:01:19.273994 ddr clk to 1584MHz
1011 23:01:19.280542 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1012 23:01:19.318809
1013 23:01:19.319518 dmc_version 0001
1014 23:01:19.325393 Check phy result
1015 23:01:19.331339 INFO : End of CA training
1016 23:01:19.331935 INFO : End of initialization
1017 23:01:19.336907 INFO : Training has run successfully!
1018 23:01:19.337500 Check phy result
1019 23:01:19.342390 INFO : End of initialization
1020 23:01:19.342983 INFO : End of read enable training
1021 23:01:19.345804 INFO : End of fine write leveling
1022 23:01:19.351476 INFO : End of Write leveling coarse delay
1023 23:01:19.357006 INFO : Training has run successfully!
1024 23:01:19.357649 Check phy result
1025 23:01:19.358167 INFO : End of initialization
1026 23:01:19.362719 INFO : End of read dq deskew training
1027 23:01:19.368190 INFO : End of MPR read delay center optimization
1028 23:01:19.368778 INFO : End of write delay center optimization
1029 23:01:19.373795 INFO : End of read delay center optimization
1030 23:01:19.379308 INFO : End of max read latency training
1031 23:01:19.379893 INFO : Training has run successfully!
1032 23:01:19.384827 1D training succeed
1033 23:01:19.390720 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1034 23:01:19.440409 Check phy result
1035 23:01:19.441163 INFO : End of initialization
1036 23:01:19.460949 INFO : End of 2D read delay Voltage center optimization
1037 23:01:19.481109 INFO : End of 2D read delay Voltage center optimization
1038 23:01:19.534161 INFO : End of 2D write delay Voltage center optimization
1039 23:01:19.582649 INFO : End of 2D write delay Voltage center optimization
1040 23:01:19.588167 INFO : Training has run successfully!
1041 23:01:19.588674
1042 23:01:19.588963 channel==0
1043 23:01:19.593693 RxClkDly_Margin_A0==78 ps 8
1044 23:01:19.594059 TxDqDly_Margin_A0==98 ps 10
1045 23:01:19.596949 RxClkDly_Margin_A1==88 ps 9
1046 23:01:19.597415 TxDqDly_Margin_A1==98 ps 10
1047 23:01:19.602592 TrainedVREFDQ_A0==74
1048 23:01:19.603079 TrainedVREFDQ_A1==74
1049 23:01:19.608182 VrefDac_Margin_A0==25
1050 23:01:19.608543 DeviceVref_Margin_A0==40
1051 23:01:19.608784 VrefDac_Margin_A1==24
1052 23:01:19.613712 DeviceVref_Margin_A1==40
1053 23:01:19.614214
1054 23:01:19.614600
1055 23:01:19.614966 channel==1
1056 23:01:19.615236 RxClkDly_Margin_A0==88 ps 9
1057 23:01:19.617132 TxDqDly_Margin_A0==88 ps 9
1058 23:01:19.622583 RxClkDly_Margin_A1==98 ps 10
1059 23:01:19.622926 TxDqDly_Margin_A1==88 ps 9
1060 23:01:19.623167 TrainedVREFDQ_A0==76
1061 23:01:19.628190 TrainedVREFDQ_A1==77
1062 23:01:19.628666 VrefDac_Margin_A0==22
1063 23:01:19.633771 DeviceVref_Margin_A0==38
1064 23:01:19.634261 VrefDac_Margin_A1==24
1065 23:01:19.634652 DeviceVref_Margin_A1==37
1066 23:01:19.634928
1067 23:01:19.639375 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1068 23:01:19.639724
1069 23:01:19.672965 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1070 23:01:19.673548 2D training succeed
1071 23:01:19.678627 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1072 23:01:19.684169 auto size-- 65535DDR cs0 size: 2048MB
1073 23:01:19.684528 DDR cs1 size: 2048MB
1074 23:01:19.689903 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1075 23:01:19.690404 cs0 DataBus test pass
1076 23:01:19.690786 cs1 DataBus test pass
1077 23:01:19.695403 cs0 AddrBus test pass
1078 23:01:19.695752 cs1 AddrBus test pass
1079 23:01:19.696030
1080 23:01:19.701028 100bdlr_step_size ps== 420
1081 23:01:19.701578 result report
1082 23:01:19.702046 boot times 0Enable ddr reg access
1083 23:01:19.710932 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1084 23:01:19.724454 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1085 23:01:20.297427 0.0;M3 CHK:0;cm4_sp_mode 0
1086 23:01:20.298075 MVN_1=0x00000000
1087 23:01:20.302923 MVN_2=0x00000000
1088 23:01:20.308723 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1089 23:01:20.309244 OPS=0x10
1090 23:01:20.309709 ring efuse init
1091 23:01:20.310158 chipver efuse init
1092 23:01:20.314268 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1093 23:01:20.319885 [0.018961 Inits done]
1094 23:01:20.320465 secure task start!
1095 23:01:20.320932 high task start!
1096 23:01:20.323520 low task start!
1097 23:01:20.324064 run into bl31
1098 23:01:20.331129 NOTICE: BL31: v1.3(release):4fc40b1
1099 23:01:20.338938 NOTICE: BL31: Built : 15:58:17, May 22 2019
1100 23:01:20.339529 NOTICE: BL31: G12A normal boot!
1101 23:01:20.364472 NOTICE: BL31: BL33 decompress pass
1102 23:01:20.369865 ERROR: Error initializing runtime service opteed_fast
1103 23:01:21.602968
1104 23:01:21.603645
1105 23:01:21.611364 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1106 23:01:21.611936
1107 23:01:21.612447 Model: Libre Computer AML-A311D-CC Alta
1108 23:01:21.819766 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1109 23:01:21.843144 DRAM: 2 GiB (effective 3.8 GiB)
1110 23:01:21.986127 Core: 408 devices, 31 uclasses, devicetree: separate
1111 23:01:21.992048 WDT: Not starting watchdog@f0d0
1112 23:01:22.024243 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1113 23:01:22.036700 Loading Environment from FAT... Card did not respond to voltage select! : -110
1114 23:01:22.041657 ** Bad device specification mmc 0 **
1115 23:01:22.052005 Card did not respond to voltage select! : -110
1116 23:01:22.058741 ** Bad device specification mmc 0 **
1117 23:01:22.059245 Couldn't find partition mmc 0
1118 23:01:22.068038 Card did not respond to voltage select! : -110
1119 23:01:22.073515 ** Bad device specification mmc 0 **
1120 23:01:22.074015 Couldn't find partition mmc 0
1121 23:01:22.078119 Error: could not access storage.
1122 23:01:22.421137 Net: eth0: ethernet@ff3f0000
1123 23:01:22.421760 starting USB...
1124 23:01:22.672959 Bus usb@ff500000: Register 3000140 NbrPorts 3
1125 23:01:22.673634 Starting the controller
1126 23:01:22.679939 USB XHCI 1.10
1127 23:01:24.233805 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1128 23:01:24.242501 scanning usb for storage devices... 0 Storage Device(s) found
1130 23:01:24.294076 Hit any key to stop autoboot: 1
1131 23:01:24.294917 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1132 23:01:24.295349 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1133 23:01:24.295649 Setting prompt string to ['=>']
1134 23:01:24.295949 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1135 23:01:24.310589 0
1136 23:01:24.311483 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1137 23:01:24.311825 Sending with 10 millisecond of delay
1139 23:01:25.447366 => setenv autoload no
1140 23:01:25.457972 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1141 23:01:25.461311 setenv autoload no
1142 23:01:25.461960 Sending with 10 millisecond of delay
1144 23:01:27.259174 => setenv initrd_high 0xffffffff
1145 23:01:27.269968 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1146 23:01:27.270816 setenv initrd_high 0xffffffff
1147 23:01:27.271520 Sending with 10 millisecond of delay
1149 23:01:28.888739 => setenv fdt_high 0xffffffff
1150 23:01:28.899562 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1151 23:01:28.900472 setenv fdt_high 0xffffffff
1152 23:01:28.901210 Sending with 10 millisecond of delay
1154 23:01:29.193048 => dhcp
1155 23:01:29.203844 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1156 23:01:29.204798 dhcp
1157 23:01:29.205245 Speed: 1000, full duplex
1158 23:01:29.205657 BOOTP broadcast 1
1159 23:01:29.216239 DHCP client bound to address 192.168.6.27 (12 ms)
1160 23:01:29.216958 Sending with 10 millisecond of delay
1162 23:01:30.893707 => setenv serverip 192.168.6.2
1163 23:01:30.904513 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1164 23:01:30.905438 setenv serverip 192.168.6.2
1165 23:01:30.906123 Sending with 10 millisecond of delay
1167 23:01:34.631666 => tftpboot 0x01080000 963296/tftp-deploy-rhr89zsn/kernel/uImage
1168 23:01:34.642624 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1169 23:01:34.643693 tftpboot 0x01080000 963296/tftp-deploy-rhr89zsn/kernel/uImage
1170 23:01:34.644289 Speed: 1000, full duplex
1171 23:01:34.644796 Using ethernet@ff3f0000 device
1172 23:01:34.645383 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1173 23:01:34.650707 Filename '963296/tftp-deploy-rhr89zsn/kernel/uImage'.
1174 23:01:34.654459 Load address: 0x1080000
1175 23:01:37.660695 Loading: *################################################## 43.6 MiB
1176 23:01:37.661301 14.5 MiB/s
1177 23:01:37.661705 done
1178 23:01:37.665007 Bytes transferred = 45713984 (2b98a40 hex)
1179 23:01:37.665727 Sending with 10 millisecond of delay
1181 23:01:42.354662 => tftpboot 0x08000000 963296/tftp-deploy-rhr89zsn/ramdisk/ramdisk.cpio.gz.uboot
1182 23:01:42.365501 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1183 23:01:42.366403 tftpboot 0x08000000 963296/tftp-deploy-rhr89zsn/ramdisk/ramdisk.cpio.gz.uboot
1184 23:01:42.366850 Speed: 1000, full duplex
1185 23:01:42.367278 Using ethernet@ff3f0000 device
1186 23:01:42.368450 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1187 23:01:42.376898 Filename '963296/tftp-deploy-rhr89zsn/ramdisk/ramdisk.cpio.gz.uboot'.
1188 23:01:42.377473 Load address: 0x8000000
1189 23:01:48.740489 Loading: *##################T ######################## UDP wrong checksum 000000ff 000089bc
1190 23:01:48.810802 ### UDP wrong checksum 000000ff 000020af
1191 23:01:48.969036 #### UDP wrong checksum 00000005 00008ff9
1192 23:01:53.970677 T UDP wrong checksum 00000005 00008ff9
1193 23:02:03.973147 T T UDP wrong checksum 00000005 00008ff9
1194 23:02:14.207578 T T UDP wrong checksum 000000ff 00009a54
1195 23:02:14.264772 UDP wrong checksum 000000ff 00002647
1196 23:02:20.951975 T UDP wrong checksum 000000ff 0000eaaf
1197 23:02:20.957093 UDP wrong checksum 000000ff 000077a2
1198 23:02:23.976030 T UDP wrong checksum 00000005 00008ff9
1199 23:02:38.981003 T T
1200 23:02:38.981624 Retry count exceeded; starting again
1202 23:02:38.983125 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1205 23:02:38.985127 end: 2.4 uboot-commands (duration 00:01:52) [common]
1207 23:02:38.986599 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1209 23:02:38.987615 end: 2 uboot-action (duration 00:01:52) [common]
1211 23:02:38.989154 Cleaning after the job
1212 23:02:38.989689 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/ramdisk
1213 23:02:38.990997 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/kernel
1214 23:02:39.020134 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/dtb
1215 23:02:39.021381 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/nfsrootfs
1216 23:02:39.056221 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963296/tftp-deploy-rhr89zsn/modules
1217 23:02:39.063073 start: 4.1 power-off (timeout 00:00:30) [common]
1218 23:02:39.063657 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1219 23:02:39.098283 >> OK - accepted request
1220 23:02:39.100667 Returned 0 in 0 seconds
1221 23:02:39.201447 end: 4.1 power-off (duration 00:00:00) [common]
1223 23:02:39.202398 start: 4.2 read-feedback (timeout 00:10:00) [common]
1224 23:02:39.203040 Listened to connection for namespace 'common' for up to 1s
1225 23:02:40.204043 Finalising connection for namespace 'common'
1226 23:02:40.204798 Disconnecting from shell: Finalise
1227 23:02:40.205316 =>
1228 23:02:40.306324 end: 4.2 read-feedback (duration 00:00:01) [common]
1229 23:02:40.306922 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/963296
1230 23:02:43.270494 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/963296
1231 23:02:43.271092 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.