Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:16:28.857973 lava-dispatcher, installed at version: 2024.01
2 23:16:28.858769 start: 0 validate
3 23:16:28.859276 Start time: 2024-11-08 23:16:28.859246+00:00 (UTC)
4 23:16:28.859821 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:16:28.860410 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:16:28.899815 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:16:28.900402 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:16:28.929935 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:16:28.930556 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 23:16:28.964140 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:16:28.964640 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:16:29.000069 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 23:16:29.000698 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-256-gc291c9cfd76a8%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 23:16:29.042207 validate duration: 0.18
16 23:16:29.043057 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:16:29.043366 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:16:29.043669 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:16:29.044277 Not decompressing ramdisk as can be used compressed.
20 23:16:29.044736 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 23:16:29.045010 saving as /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/ramdisk/initrd.cpio.gz
22 23:16:29.045278 total size: 5628140 (5 MB)
23 23:16:29.079823 progress 0 % (0 MB)
24 23:16:29.084345 progress 5 % (0 MB)
25 23:16:29.088547 progress 10 % (0 MB)
26 23:16:29.092428 progress 15 % (0 MB)
27 23:16:29.096510 progress 20 % (1 MB)
28 23:16:29.100172 progress 25 % (1 MB)
29 23:16:29.104311 progress 30 % (1 MB)
30 23:16:29.108443 progress 35 % (1 MB)
31 23:16:29.112129 progress 40 % (2 MB)
32 23:16:29.116473 progress 45 % (2 MB)
33 23:16:29.120324 progress 50 % (2 MB)
34 23:16:29.124415 progress 55 % (2 MB)
35 23:16:29.128651 progress 60 % (3 MB)
36 23:16:29.132506 progress 65 % (3 MB)
37 23:16:29.137470 progress 70 % (3 MB)
38 23:16:29.142507 progress 75 % (4 MB)
39 23:16:29.146351 progress 80 % (4 MB)
40 23:16:29.149732 progress 85 % (4 MB)
41 23:16:29.153409 progress 90 % (4 MB)
42 23:16:29.157059 progress 95 % (5 MB)
43 23:16:29.160428 progress 100 % (5 MB)
44 23:16:29.161114 5 MB downloaded in 0.12 s (46.35 MB/s)
45 23:16:29.161681 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:16:29.162564 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:16:29.162854 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:16:29.163126 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:16:29.163601 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm64/defconfig/gcc-12/kernel/Image
51 23:16:29.163864 saving as /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/kernel/Image
52 23:16:29.164101 total size: 45713920 (43 MB)
53 23:16:29.164315 No compression specified
54 23:16:29.200321 progress 0 % (0 MB)
55 23:16:29.228426 progress 5 % (2 MB)
56 23:16:29.256556 progress 10 % (4 MB)
57 23:16:29.284654 progress 15 % (6 MB)
58 23:16:29.312951 progress 20 % (8 MB)
59 23:16:29.340543 progress 25 % (10 MB)
60 23:16:29.367966 progress 30 % (13 MB)
61 23:16:29.395761 progress 35 % (15 MB)
62 23:16:29.423302 progress 40 % (17 MB)
63 23:16:29.450847 progress 45 % (19 MB)
64 23:16:29.478816 progress 50 % (21 MB)
65 23:16:29.506845 progress 55 % (24 MB)
66 23:16:29.534934 progress 60 % (26 MB)
67 23:16:29.562702 progress 65 % (28 MB)
68 23:16:29.590596 progress 70 % (30 MB)
69 23:16:29.618899 progress 75 % (32 MB)
70 23:16:29.647329 progress 80 % (34 MB)
71 23:16:29.675414 progress 85 % (37 MB)
72 23:16:29.704177 progress 90 % (39 MB)
73 23:16:29.732673 progress 95 % (41 MB)
74 23:16:29.759276 progress 100 % (43 MB)
75 23:16:29.759847 43 MB downloaded in 0.60 s (73.18 MB/s)
76 23:16:29.760372 end: 1.2.1 http-download (duration 00:00:01) [common]
78 23:16:29.761207 end: 1.2 download-retry (duration 00:00:01) [common]
79 23:16:29.761482 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:16:29.761751 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:16:29.762230 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 23:16:29.762531 saving as /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/dtb/meson-g12b-a311d-libretech-cc.dtb
83 23:16:29.762741 total size: 54703 (0 MB)
84 23:16:29.762947 No compression specified
85 23:16:29.800811 progress 59 % (0 MB)
86 23:16:29.801703 progress 100 % (0 MB)
87 23:16:29.802317 0 MB downloaded in 0.04 s (1.32 MB/s)
88 23:16:29.802836 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:16:29.803747 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:16:29.804076 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:16:29.804402 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:16:29.804916 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 23:16:29.805194 saving as /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/nfsrootfs/full.rootfs.tar
95 23:16:29.805426 total size: 474398908 (452 MB)
96 23:16:29.805662 Using unxz to decompress xz
97 23:16:29.839495 progress 0 % (0 MB)
98 23:16:30.962047 progress 5 % (22 MB)
99 23:16:32.523807 progress 10 % (45 MB)
100 23:16:32.968407 progress 15 % (67 MB)
101 23:16:33.812110 progress 20 % (90 MB)
102 23:16:34.371493 progress 25 % (113 MB)
103 23:16:34.778788 progress 30 % (135 MB)
104 23:16:35.400536 progress 35 % (158 MB)
105 23:16:36.322220 progress 40 % (181 MB)
106 23:16:37.105797 progress 45 % (203 MB)
107 23:16:37.732279 progress 50 % (226 MB)
108 23:16:38.353592 progress 55 % (248 MB)
109 23:16:39.553428 progress 60 % (271 MB)
110 23:16:41.041765 progress 65 % (294 MB)
111 23:16:42.671561 progress 70 % (316 MB)
112 23:16:46.015654 progress 75 % (339 MB)
113 23:16:48.500843 progress 80 % (361 MB)
114 23:16:51.444322 progress 85 % (384 MB)
115 23:16:54.638732 progress 90 % (407 MB)
116 23:16:57.875868 progress 95 % (429 MB)
117 23:17:01.247548 progress 100 % (452 MB)
118 23:17:01.262068 452 MB downloaded in 31.46 s (14.38 MB/s)
119 23:17:01.263191 end: 1.4.1 http-download (duration 00:00:31) [common]
121 23:17:01.265185 end: 1.4 download-retry (duration 00:00:31) [common]
122 23:17:01.265783 start: 1.5 download-retry (timeout 00:09:28) [common]
123 23:17:01.266368 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 23:17:01.267253 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-256-gc291c9cfd76a8/arm64/defconfig/gcc-12/modules.tar.xz
125 23:17:01.267794 saving as /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/modules/modules.tar
126 23:17:01.268286 total size: 11613560 (11 MB)
127 23:17:01.268773 Using unxz to decompress xz
128 23:17:01.321195 progress 0 % (0 MB)
129 23:17:01.391332 progress 5 % (0 MB)
130 23:17:01.476675 progress 10 % (1 MB)
131 23:17:01.600109 progress 15 % (1 MB)
132 23:17:01.758144 progress 20 % (2 MB)
133 23:17:01.886181 progress 25 % (2 MB)
134 23:17:01.991970 progress 30 % (3 MB)
135 23:17:02.104373 progress 35 % (3 MB)
136 23:17:02.203506 progress 40 % (4 MB)
137 23:17:02.308837 progress 45 % (5 MB)
138 23:17:02.430241 progress 50 % (5 MB)
139 23:17:02.545347 progress 55 % (6 MB)
140 23:17:02.659206 progress 60 % (6 MB)
141 23:17:02.777579 progress 65 % (7 MB)
142 23:17:02.903637 progress 70 % (7 MB)
143 23:17:03.032863 progress 75 % (8 MB)
144 23:17:03.148720 progress 80 % (8 MB)
145 23:17:03.231834 progress 85 % (9 MB)
146 23:17:03.313033 progress 90 % (9 MB)
147 23:17:03.392827 progress 95 % (10 MB)
148 23:17:03.471105 progress 100 % (11 MB)
149 23:17:03.484386 11 MB downloaded in 2.22 s (5.00 MB/s)
150 23:17:03.485016 end: 1.5.1 http-download (duration 00:00:02) [common]
152 23:17:03.485833 end: 1.5 download-retry (duration 00:00:02) [common]
153 23:17:03.486098 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 23:17:03.486361 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 23:17:20.285146 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/963343/extract-nfsrootfs-l_i61jpa
156 23:17:20.285744 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 23:17:20.286031 start: 1.6.2 lava-overlay (timeout 00:09:09) [common]
158 23:17:20.286605 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9
159 23:17:20.287035 makedir: /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin
160 23:17:20.287361 makedir: /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/tests
161 23:17:20.287674 makedir: /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/results
162 23:17:20.288028 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-add-keys
163 23:17:20.288581 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-add-sources
164 23:17:20.289098 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-background-process-start
165 23:17:20.289598 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-background-process-stop
166 23:17:20.290224 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-common-functions
167 23:17:20.290717 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-echo-ipv4
168 23:17:20.291194 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-install-packages
169 23:17:20.291699 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-installed-packages
170 23:17:20.292218 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-os-build
171 23:17:20.292722 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-probe-channel
172 23:17:20.293210 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-probe-ip
173 23:17:20.293689 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-target-ip
174 23:17:20.294163 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-target-mac
175 23:17:20.294767 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-target-storage
176 23:17:20.295266 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-test-case
177 23:17:20.295744 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-test-event
178 23:17:20.296249 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-test-feedback
179 23:17:20.296729 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-test-raise
180 23:17:20.297224 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-test-reference
181 23:17:20.297713 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-test-runner
182 23:17:20.298197 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-test-set
183 23:17:20.298667 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-test-shell
184 23:17:20.299141 Updating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-install-packages (oe)
185 23:17:20.299691 Updating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/bin/lava-installed-packages (oe)
186 23:17:20.300200 Creating /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/environment
187 23:17:20.300591 LAVA metadata
188 23:17:20.300854 - LAVA_JOB_ID=963343
189 23:17:20.301069 - LAVA_DISPATCHER_IP=192.168.6.2
190 23:17:20.301454 start: 1.6.2.1 ssh-authorize (timeout 00:09:09) [common]
191 23:17:20.303465 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 23:17:20.303790 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:09) [common]
193 23:17:20.304047 skipped lava-vland-overlay
194 23:17:20.304296 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 23:17:20.304553 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:09) [common]
196 23:17:20.304774 skipped lava-multinode-overlay
197 23:17:20.305013 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 23:17:20.305265 start: 1.6.2.4 test-definition (timeout 00:09:09) [common]
199 23:17:20.305517 Loading test definitions
200 23:17:20.305794 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:09) [common]
201 23:17:20.306015 Using /lava-963343 at stage 0
202 23:17:20.307300 uuid=963343_1.6.2.4.1 testdef=None
203 23:17:20.307619 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 23:17:20.307880 start: 1.6.2.4.2 test-overlay (timeout 00:09:09) [common]
205 23:17:20.309707 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 23:17:20.310491 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:09) [common]
208 23:17:20.312669 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 23:17:20.313497 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:09) [common]
211 23:17:20.315592 runner path: /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 963343_1.6.2.4.1
212 23:17:20.316213 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 23:17:20.316971 Creating lava-test-runner.conf files
215 23:17:20.317171 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/963343/lava-overlay-srlaho_9/lava-963343/0 for stage 0
216 23:17:20.317520 - 0_v4l2-decoder-conformance-h265
217 23:17:20.317877 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 23:17:20.318166 start: 1.6.2.5 compress-overlay (timeout 00:09:09) [common]
219 23:17:20.340150 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 23:17:20.340569 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:09) [common]
221 23:17:20.340831 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 23:17:20.341101 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 23:17:20.341363 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:09) [common]
224 23:17:21.031300 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 23:17:21.031835 start: 1.6.4 extract-modules (timeout 00:09:08) [common]
226 23:17:21.032171 extracting modules file /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/963343/extract-nfsrootfs-l_i61jpa
227 23:17:22.864892 extracting modules file /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/963343/extract-overlay-ramdisk-gtfk1v9h/ramdisk
228 23:17:24.454801 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 23:17:24.455285 start: 1.6.5 apply-overlay-tftp (timeout 00:09:05) [common]
230 23:17:24.455564 [common] Applying overlay to NFS
231 23:17:24.455773 [common] Applying overlay /var/lib/lava/dispatcher/tmp/963343/compress-overlay-8amirf8j/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/963343/extract-nfsrootfs-l_i61jpa
232 23:17:24.485138 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 23:17:24.485619 start: 1.6.6 prepare-kernel (timeout 00:09:05) [common]
234 23:17:24.485898 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:05) [common]
235 23:17:24.486140 Converting downloaded kernel to a uImage
236 23:17:24.486467 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/kernel/Image /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/kernel/uImage
237 23:17:24.993063 output: Image Name:
238 23:17:24.993481 output: Created: Fri Nov 8 23:17:24 2024
239 23:17:24.993692 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 23:17:24.993897 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 23:17:24.994097 output: Load Address: 01080000
242 23:17:24.994294 output: Entry Point: 01080000
243 23:17:24.994491 output:
244 23:17:24.994821 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 23:17:24.995087 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 23:17:24.995350 start: 1.6.7 configure-preseed-file (timeout 00:09:04) [common]
247 23:17:24.995600 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 23:17:24.995856 start: 1.6.8 compress-ramdisk (timeout 00:09:04) [common]
249 23:17:24.996153 Building ramdisk /var/lib/lava/dispatcher/tmp/963343/extract-overlay-ramdisk-gtfk1v9h/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/963343/extract-overlay-ramdisk-gtfk1v9h/ramdisk
250 23:17:27.234390 >> 166827 blocks
251 23:17:35.043957 Adding RAMdisk u-boot header.
252 23:17:35.044657 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/963343/extract-overlay-ramdisk-gtfk1v9h/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/963343/extract-overlay-ramdisk-gtfk1v9h/ramdisk.cpio.gz.uboot
253 23:17:35.291406 output: Image Name:
254 23:17:35.291827 output: Created: Fri Nov 8 23:17:35 2024
255 23:17:35.292316 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 23:17:35.292743 output: Data Size: 23434085 Bytes = 22884.85 KiB = 22.35 MiB
257 23:17:35.293150 output: Load Address: 00000000
258 23:17:35.293551 output: Entry Point: 00000000
259 23:17:35.293949 output:
260 23:17:35.294961 rename /var/lib/lava/dispatcher/tmp/963343/extract-overlay-ramdisk-gtfk1v9h/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/ramdisk/ramdisk.cpio.gz.uboot
261 23:17:35.295687 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 23:17:35.296283 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
263 23:17:35.296828 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:54) [common]
264 23:17:35.297289 No LXC device requested
265 23:17:35.297799 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 23:17:35.298321 start: 1.8 deploy-device-env (timeout 00:08:54) [common]
267 23:17:35.298829 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 23:17:35.299246 Checking files for TFTP limit of 4294967296 bytes.
269 23:17:35.302015 end: 1 tftp-deploy (duration 00:01:06) [common]
270 23:17:35.302612 start: 2 uboot-action (timeout 00:05:00) [common]
271 23:17:35.303150 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 23:17:35.303653 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 23:17:35.304191 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 23:17:35.304732 Using kernel file from prepare-kernel: 963343/tftp-deploy-4z4vss2q/kernel/uImage
275 23:17:35.305364 substitutions:
276 23:17:35.305774 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 23:17:35.306175 - {DTB_ADDR}: 0x01070000
278 23:17:35.306575 - {DTB}: 963343/tftp-deploy-4z4vss2q/dtb/meson-g12b-a311d-libretech-cc.dtb
279 23:17:35.306972 - {INITRD}: 963343/tftp-deploy-4z4vss2q/ramdisk/ramdisk.cpio.gz.uboot
280 23:17:35.307368 - {KERNEL_ADDR}: 0x01080000
281 23:17:35.307759 - {KERNEL}: 963343/tftp-deploy-4z4vss2q/kernel/uImage
282 23:17:35.308191 - {LAVA_MAC}: None
283 23:17:35.308652 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/963343/extract-nfsrootfs-l_i61jpa
284 23:17:35.309062 - {NFS_SERVER_IP}: 192.168.6.2
285 23:17:35.309455 - {PRESEED_CONFIG}: None
286 23:17:35.309847 - {PRESEED_LOCAL}: None
287 23:17:35.310237 - {RAMDISK_ADDR}: 0x08000000
288 23:17:35.310622 - {RAMDISK}: 963343/tftp-deploy-4z4vss2q/ramdisk/ramdisk.cpio.gz.uboot
289 23:17:35.311009 - {ROOT_PART}: None
290 23:17:35.311394 - {ROOT}: None
291 23:17:35.311778 - {SERVER_IP}: 192.168.6.2
292 23:17:35.312200 - {TEE_ADDR}: 0x83000000
293 23:17:35.312591 - {TEE}: None
294 23:17:35.312977 Parsed boot commands:
295 23:17:35.313352 - setenv autoload no
296 23:17:35.313737 - setenv initrd_high 0xffffffff
297 23:17:35.314119 - setenv fdt_high 0xffffffff
298 23:17:35.314501 - dhcp
299 23:17:35.314884 - setenv serverip 192.168.6.2
300 23:17:35.315265 - tftpboot 0x01080000 963343/tftp-deploy-4z4vss2q/kernel/uImage
301 23:17:35.315651 - tftpboot 0x08000000 963343/tftp-deploy-4z4vss2q/ramdisk/ramdisk.cpio.gz.uboot
302 23:17:35.316064 - tftpboot 0x01070000 963343/tftp-deploy-4z4vss2q/dtb/meson-g12b-a311d-libretech-cc.dtb
303 23:17:35.316460 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/963343/extract-nfsrootfs-l_i61jpa,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 23:17:35.316862 - bootm 0x01080000 0x08000000 0x01070000
305 23:17:35.317370 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 23:17:35.318864 start: 2.3 connect-device (timeout 00:05:00) [common]
308 23:17:35.319291 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 23:17:35.334543 Setting prompt string to ['lava-test: # ']
310 23:17:35.336102 end: 2.3 connect-device (duration 00:00:00) [common]
311 23:17:35.336741 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 23:17:35.337306 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 23:17:35.338111 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 23:17:35.339580 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 23:17:35.376619 >> OK - accepted request
316 23:17:35.378743 Returned 0 in 0 seconds
317 23:17:35.479667 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 23:17:35.481376 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 23:17:35.481940 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 23:17:35.482448 Setting prompt string to ['Hit any key to stop autoboot']
322 23:17:35.482911 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 23:17:35.484523 Trying 192.168.56.21...
324 23:17:35.485020 Connected to conserv1.
325 23:17:35.485436 Escape character is '^]'.
326 23:17:35.485848
327 23:17:35.486266 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 23:17:35.486692
329 23:17:47.135877 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 23:17:47.136559 bl2_stage_init 0x01
331 23:17:47.136987 bl2_stage_init 0x81
332 23:17:47.141197 hw id: 0x0000 - pwm id 0x01
333 23:17:47.141526 bl2_stage_init 0xc1
334 23:17:47.141738 bl2_stage_init 0x02
335 23:17:47.141953
336 23:17:47.146947 L0:00000000
337 23:17:47.147277 L1:20000703
338 23:17:47.147483 L2:00008067
339 23:17:47.147690 L3:14000000
340 23:17:47.149842 B2:00402000
341 23:17:47.150307 B1:e0f83180
342 23:17:47.150721
343 23:17:47.151094 TE: 58124
344 23:17:47.151313
345 23:17:47.160880 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 23:17:47.161246
347 23:17:47.161463 Board ID = 1
348 23:17:47.161671 Set A53 clk to 24M
349 23:17:47.161876 Set A73 clk to 24M
350 23:17:47.166478 Set clk81 to 24M
351 23:17:47.166764 A53 clk: 1200 MHz
352 23:17:47.166962 A73 clk: 1200 MHz
353 23:17:47.170010 CLK81: 166.6M
354 23:17:47.170277 smccc: 00012a91
355 23:17:47.175421 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 23:17:47.181113 board id: 1
357 23:17:47.186196 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 23:17:47.196828 fw parse done
359 23:17:47.202886 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 23:17:47.245679 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 23:17:47.256468 PIEI prepare done
362 23:17:47.256994 fastboot data load
363 23:17:47.257423 fastboot data verify
364 23:17:47.262087 verify result: 266
365 23:17:47.267656 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 23:17:47.268204 LPDDR4 probe
367 23:17:47.268638 ddr clk to 1584MHz
368 23:17:47.275687 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 23:17:47.313021
370 23:17:47.313654 dmc_version 0001
371 23:17:47.319623 Check phy result
372 23:17:47.325346 INFO : End of CA training
373 23:17:47.325835 INFO : End of initialization
374 23:17:47.331069 INFO : Training has run successfully!
375 23:17:47.331611 Check phy result
376 23:17:47.336626 INFO : End of initialization
377 23:17:47.337114 INFO : End of read enable training
378 23:17:47.339844 INFO : End of fine write leveling
379 23:17:47.345370 INFO : End of Write leveling coarse delay
380 23:17:47.351062 INFO : Training has run successfully!
381 23:17:47.351528 Check phy result
382 23:17:47.351928 INFO : End of initialization
383 23:17:47.356553 INFO : End of read dq deskew training
384 23:17:47.362208 INFO : End of MPR read delay center optimization
385 23:17:47.362681 INFO : End of write delay center optimization
386 23:17:47.367814 INFO : End of read delay center optimization
387 23:17:47.373442 INFO : End of max read latency training
388 23:17:47.373908 INFO : Training has run successfully!
389 23:17:47.379095 1D training succeed
390 23:17:47.384973 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 23:17:47.432652 Check phy result
392 23:17:47.433208 INFO : End of initialization
393 23:17:47.454330 INFO : End of 2D read delay Voltage center optimization
394 23:17:47.474538 INFO : End of 2D read delay Voltage center optimization
395 23:17:47.526717 INFO : End of 2D write delay Voltage center optimization
396 23:17:47.575915 INFO : End of 2D write delay Voltage center optimization
397 23:17:47.581484 INFO : Training has run successfully!
398 23:17:47.581758
399 23:17:47.581968 channel==0
400 23:17:47.587112 RxClkDly_Margin_A0==88 ps 9
401 23:17:47.587380 TxDqDly_Margin_A0==98 ps 10
402 23:17:47.592672 RxClkDly_Margin_A1==88 ps 9
403 23:17:47.592936 TxDqDly_Margin_A1==98 ps 10
404 23:17:47.593140 TrainedVREFDQ_A0==74
405 23:17:47.598190 TrainedVREFDQ_A1==75
406 23:17:47.598449 VrefDac_Margin_A0==25
407 23:17:47.598653 DeviceVref_Margin_A0==40
408 23:17:47.603847 VrefDac_Margin_A1==25
409 23:17:47.604353 DeviceVref_Margin_A1==39
410 23:17:47.604751
411 23:17:47.605144
412 23:17:47.609540 channel==1
413 23:17:47.610003 RxClkDly_Margin_A0==88 ps 9
414 23:17:47.610427 TxDqDly_Margin_A0==88 ps 9
415 23:17:47.615167 RxClkDly_Margin_A1==98 ps 10
416 23:17:47.615630 TxDqDly_Margin_A1==98 ps 10
417 23:17:47.620695 TrainedVREFDQ_A0==77
418 23:17:47.621159 TrainedVREFDQ_A1==77
419 23:17:47.621557 VrefDac_Margin_A0==22
420 23:17:47.626388 DeviceVref_Margin_A0==37
421 23:17:47.626854 VrefDac_Margin_A1==24
422 23:17:47.632054 DeviceVref_Margin_A1==37
423 23:17:47.632552
424 23:17:47.632954 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 23:17:47.633344
426 23:17:47.665487 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 23:17:47.666137 2D training succeed
428 23:17:47.671188 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 23:17:47.676826 auto size-- 65535DDR cs0 size: 2048MB
430 23:17:47.677333 DDR cs1 size: 2048MB
431 23:17:47.682374 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 23:17:47.682854 cs0 DataBus test pass
433 23:17:47.687961 cs1 DataBus test pass
434 23:17:47.688488 cs0 AddrBus test pass
435 23:17:47.688887 cs1 AddrBus test pass
436 23:17:47.689277
437 23:17:47.693571 100bdlr_step_size ps== 420
438 23:17:47.694070 result report
439 23:17:47.699206 boot times 0Enable ddr reg access
440 23:17:47.703687 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 23:17:47.717850 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 23:17:48.291008 0.0;M3 CHK:0;cm4_sp_mode 0
443 23:17:48.291637 MVN_1=0x00000000
444 23:17:48.296494 MVN_2=0x00000000
445 23:17:48.302223 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 23:17:48.302699 OPS=0x10
447 23:17:48.303104 ring efuse init
448 23:17:48.303497 chipver efuse init
449 23:17:48.307882 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 23:17:48.313435 [0.018961 Inits done]
451 23:17:48.313901 secure task start!
452 23:17:48.314298 high task start!
453 23:17:48.318047 low task start!
454 23:17:48.318518 run into bl31
455 23:17:48.324679 NOTICE: BL31: v1.3(release):4fc40b1
456 23:17:48.332481 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 23:17:48.332787 NOTICE: BL31: G12A normal boot!
458 23:17:48.358013 NOTICE: BL31: BL33 decompress pass
459 23:17:48.363609 ERROR: Error initializing runtime service opteed_fast
460 23:17:49.596357
461 23:17:49.596782
462 23:17:49.604807 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 23:17:49.605117
464 23:17:49.605327 Model: Libre Computer AML-A311D-CC Alta
465 23:17:49.812410 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 23:17:49.836605 DRAM: 2 GiB (effective 3.8 GiB)
467 23:17:49.979572 Core: 408 devices, 31 uclasses, devicetree: separate
468 23:17:49.985396 WDT: Not starting watchdog@f0d0
469 23:17:50.017947 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 23:17:50.030197 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 23:17:50.035101 ** Bad device specification mmc 0 **
472 23:17:50.045476 Card did not respond to voltage select! : -110
473 23:17:50.052331 ** Bad device specification mmc 0 **
474 23:17:50.052890 Couldn't find partition mmc 0
475 23:17:50.061538 Card did not respond to voltage select! : -110
476 23:17:50.067070 ** Bad device specification mmc 0 **
477 23:17:50.067610 Couldn't find partition mmc 0
478 23:17:50.072189 Error: could not access storage.
479 23:17:51.335834 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 23:17:51.336449 bl2_stage_init 0x01
481 23:17:51.336851 bl2_stage_init 0x81
482 23:17:51.341376 hw id: 0x0000 - pwm id 0x01
483 23:17:51.341839 bl2_stage_init 0xc1
484 23:17:51.342234 bl2_stage_init 0x02
485 23:17:51.342625
486 23:17:51.346975 L0:00000000
487 23:17:51.347424 L1:20000703
488 23:17:51.347822 L2:00008067
489 23:17:51.348248 L3:14000000
490 23:17:51.352595 B2:00402000
491 23:17:51.353042 B1:e0f83180
492 23:17:51.353432
493 23:17:51.353821 TE: 58124
494 23:17:51.354212
495 23:17:51.358247 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 23:17:51.358703
497 23:17:51.359098 Board ID = 1
498 23:17:51.363775 Set A53 clk to 24M
499 23:17:51.364260 Set A73 clk to 24M
500 23:17:51.364657 Set clk81 to 24M
501 23:17:51.369398 A53 clk: 1200 MHz
502 23:17:51.369845 A73 clk: 1200 MHz
503 23:17:51.370237 CLK81: 166.6M
504 23:17:51.370625 smccc: 00012a92
505 23:17:51.374975 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 23:17:51.380582 board id: 1
507 23:17:51.385558 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 23:17:51.397236 fw parse done
509 23:17:51.403083 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 23:17:51.444801 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 23:17:51.456671 PIEI prepare done
512 23:17:51.457142 fastboot data load
513 23:17:51.457556 fastboot data verify
514 23:17:51.462365 verify result: 266
515 23:17:51.467903 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 23:17:51.468403 LPDDR4 probe
517 23:17:51.468812 ddr clk to 1584MHz
518 23:17:51.475864 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 23:17:51.513132
520 23:17:51.513501 dmc_version 0001
521 23:17:51.519755 Check phy result
522 23:17:51.525616 INFO : End of CA training
523 23:17:51.525910 INFO : End of initialization
524 23:17:51.531285 INFO : Training has run successfully!
525 23:17:51.531585 Check phy result
526 23:17:51.536823 INFO : End of initialization
527 23:17:51.537139 INFO : End of read enable training
528 23:17:51.542437 INFO : End of fine write leveling
529 23:17:51.548065 INFO : End of Write leveling coarse delay
530 23:17:51.548400 INFO : Training has run successfully!
531 23:17:51.548624 Check phy result
532 23:17:51.553636 INFO : End of initialization
533 23:17:51.553970 INFO : End of read dq deskew training
534 23:17:51.559248 INFO : End of MPR read delay center optimization
535 23:17:51.564774 INFO : End of write delay center optimization
536 23:17:51.570428 INFO : End of read delay center optimization
537 23:17:51.570778 INFO : End of max read latency training
538 23:17:51.576083 INFO : Training has run successfully!
539 23:17:51.576419 1D training succeed
540 23:17:51.585244 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 23:17:51.633900 Check phy result
542 23:17:51.634396 INFO : End of initialization
543 23:17:51.655456 INFO : End of 2D read delay Voltage center optimization
544 23:17:51.675648 INFO : End of 2D read delay Voltage center optimization
545 23:17:51.727723 INFO : End of 2D write delay Voltage center optimization
546 23:17:51.777091 INFO : End of 2D write delay Voltage center optimization
547 23:17:51.782658 INFO : Training has run successfully!
548 23:17:51.783128
549 23:17:51.783537 channel==0
550 23:17:51.788434 RxClkDly_Margin_A0==88 ps 9
551 23:17:51.788974 TxDqDly_Margin_A0==98 ps 10
552 23:17:51.793857 RxClkDly_Margin_A1==88 ps 9
553 23:17:51.794341 TxDqDly_Margin_A1==98 ps 10
554 23:17:51.794740 TrainedVREFDQ_A0==74
555 23:17:51.799466 TrainedVREFDQ_A1==74
556 23:17:51.799943 VrefDac_Margin_A0==24
557 23:17:51.800398 DeviceVref_Margin_A0==40
558 23:17:51.805043 VrefDac_Margin_A1==24
559 23:17:51.805506 DeviceVref_Margin_A1==40
560 23:17:51.805898
561 23:17:51.806290
562 23:17:51.810666 channel==1
563 23:17:51.811124 RxClkDly_Margin_A0==98 ps 10
564 23:17:51.811517 TxDqDly_Margin_A0==88 ps 9
565 23:17:51.816395 RxClkDly_Margin_A1==98 ps 10
566 23:17:51.816904 TxDqDly_Margin_A1==88 ps 9
567 23:17:51.821880 TrainedVREFDQ_A0==76
568 23:17:51.822354 TrainedVREFDQ_A1==77
569 23:17:51.822755 VrefDac_Margin_A0==22
570 23:17:51.827445 DeviceVref_Margin_A0==38
571 23:17:51.827921 VrefDac_Margin_A1==24
572 23:17:51.833079 DeviceVref_Margin_A1==37
573 23:17:51.833564
574 23:17:51.833964 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 23:17:51.834362
576 23:17:51.866658 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
577 23:17:51.867238 2D training succeed
578 23:17:51.872399 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 23:17:51.877853 auto size-- 65535DDR cs0 size: 2048MB
580 23:17:51.878322 DDR cs1 size: 2048MB
581 23:17:51.883440 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 23:17:51.883901 cs0 DataBus test pass
583 23:17:51.889022 cs1 DataBus test pass
584 23:17:51.889486 cs0 AddrBus test pass
585 23:17:51.889878 cs1 AddrBus test pass
586 23:17:51.890267
587 23:17:51.894640 100bdlr_step_size ps== 420
588 23:17:51.895112 result report
589 23:17:51.900254 boot times 0Enable ddr reg access
590 23:17:51.905619 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 23:17:51.919061 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 23:17:52.492080 0.0;M3 CHK:0;cm4_sp_mode 0
593 23:17:52.492721 MVN_1=0x00000000
594 23:17:52.497408 MVN_2=0x00000000
595 23:17:52.503349 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 23:17:52.503706 OPS=0x10
597 23:17:52.503942 ring efuse init
598 23:17:52.504186 chipver efuse init
599 23:17:52.511432 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 23:17:52.511766 [0.018961 Inits done]
601 23:17:52.519008 secure task start!
602 23:17:52.519345 high task start!
603 23:17:52.519572 low task start!
604 23:17:52.519787 run into bl31
605 23:17:52.525691 NOTICE: BL31: v1.3(release):4fc40b1
606 23:17:52.532607 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 23:17:52.532926 NOTICE: BL31: G12A normal boot!
608 23:17:52.559420 NOTICE: BL31: BL33 decompress pass
609 23:17:52.565063 ERROR: Error initializing runtime service opteed_fast
610 23:17:53.798202
611 23:17:53.798833
612 23:17:53.806519 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 23:17:53.807009
614 23:17:53.807432 Model: Libre Computer AML-A311D-CC Alta
615 23:17:54.013930 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 23:17:54.038386 DRAM: 2 GiB (effective 3.8 GiB)
617 23:17:54.181480 Core: 408 devices, 31 uclasses, devicetree: separate
618 23:17:54.187226 WDT: Not starting watchdog@f0d0
619 23:17:54.219582 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 23:17:54.232007 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 23:17:54.236910 ** Bad device specification mmc 0 **
622 23:17:54.247208 Card did not respond to voltage select! : -110
623 23:17:54.254955 ** Bad device specification mmc 0 **
624 23:17:54.255448 Couldn't find partition mmc 0
625 23:17:54.263224 Card did not respond to voltage select! : -110
626 23:17:54.268870 ** Bad device specification mmc 0 **
627 23:17:54.269366 Couldn't find partition mmc 0
628 23:17:54.273931 Error: could not access storage.
629 23:17:54.616428 Net: eth0: ethernet@ff3f0000
630 23:17:54.617114 starting USB...
631 23:17:54.868102 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 23:17:54.868781 Starting the controller
633 23:17:54.874967 USB XHCI 1.10
634 23:17:56.587937 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 23:17:56.588645 bl2_stage_init 0x01
636 23:17:56.589083 bl2_stage_init 0x81
637 23:17:56.593346 hw id: 0x0000 - pwm id 0x01
638 23:17:56.593680 bl2_stage_init 0xc1
639 23:17:56.593904 bl2_stage_init 0x02
640 23:17:56.594129
641 23:17:56.599082 L0:00000000
642 23:17:56.600175 L1:20000703
643 23:17:56.600607 L2:00008067
644 23:17:56.601021 L3:14000000
645 23:17:56.604600 B2:00402000
646 23:17:56.605089 B1:e0f83180
647 23:17:56.605512
648 23:17:56.605936 TE: 58159
649 23:17:56.606349
650 23:17:56.610197 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 23:17:56.610699
652 23:17:56.611123 Board ID = 1
653 23:17:56.615803 Set A53 clk to 24M
654 23:17:56.616324 Set A73 clk to 24M
655 23:17:56.616740 Set clk81 to 24M
656 23:17:56.621850 A53 clk: 1200 MHz
657 23:17:56.622351 A73 clk: 1200 MHz
658 23:17:56.622773 CLK81: 166.6M
659 23:17:56.623191 smccc: 00012ab5
660 23:17:56.627022 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 23:17:56.633279 board id: 1
662 23:17:56.639354 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 23:17:56.649154 fw parse done
664 23:17:56.655149 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 23:17:56.697820 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 23:17:56.708568 PIEI prepare done
667 23:17:56.708893 fastboot data load
668 23:17:56.709118 fastboot data verify
669 23:17:56.714283 verify result: 266
670 23:17:56.719879 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 23:17:56.720479 LPDDR4 probe
672 23:17:56.720957 ddr clk to 1584MHz
673 23:17:56.727854 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 23:17:56.765296
675 23:17:56.765931 dmc_version 0001
676 23:17:56.771823 Check phy result
677 23:17:56.778077 INFO : End of CA training
678 23:17:56.778746 INFO : End of initialization
679 23:17:56.783266 INFO : Training has run successfully!
680 23:17:56.783957 Check phy result
681 23:17:56.789511 INFO : End of initialization
682 23:17:56.790116 INFO : End of read enable training
683 23:17:56.794378 INFO : End of fine write leveling
684 23:17:56.801011 INFO : End of Write leveling coarse delay
685 23:17:56.801569 INFO : Training has run successfully!
686 23:17:56.801959 Check phy result
687 23:17:56.806812 INFO : End of initialization
688 23:17:56.807419 INFO : End of read dq deskew training
689 23:17:56.811277 INFO : End of MPR read delay center optimization
690 23:17:56.816796 INFO : End of write delay center optimization
691 23:17:56.822395 INFO : End of read delay center optimization
692 23:17:56.822933 INFO : End of max read latency training
693 23:17:56.828032 INFO : Training has run successfully!
694 23:17:56.828851 1D training succeed
695 23:17:56.841495 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 23:17:56.885459 Check phy result
697 23:17:56.885888 INFO : End of initialization
698 23:17:56.906600 INFO : End of 2D read delay Voltage center optimization
699 23:17:56.926168 INFO : End of 2D read delay Voltage center optimization
700 23:17:56.978122 INFO : End of 2D write delay Voltage center optimization
701 23:17:57.028246 INFO : End of 2D write delay Voltage center optimization
702 23:17:57.033324 INFO : Training has run successfully!
703 23:17:57.034285
704 23:17:57.035617 channel==0
705 23:17:57.038635 RxClkDly_Margin_A0==88 ps 9
706 23:17:57.039171 TxDqDly_Margin_A0==98 ps 10
707 23:17:57.044252 RxClkDly_Margin_A1==88 ps 9
708 23:17:57.045664 TxDqDly_Margin_A1==88 ps 9
709 23:17:57.046625 TrainedVREFDQ_A0==74
710 23:17:57.050194 TrainedVREFDQ_A1==74
711 23:17:57.050538 VrefDac_Margin_A0==25
712 23:17:57.051057 DeviceVref_Margin_A0==40
713 23:17:57.055437 VrefDac_Margin_A1==25
714 23:17:57.055768 DeviceVref_Margin_A1==40
715 23:17:57.056014
716 23:17:57.056277
717 23:17:57.056513 channel==1
718 23:17:57.061317 RxClkDly_Margin_A0==78 ps 8
719 23:17:57.061858 TxDqDly_Margin_A0==98 ps 10
720 23:17:57.066773 RxClkDly_Margin_A1==88 ps 9
721 23:17:57.067333 TxDqDly_Margin_A1==88 ps 9
722 23:17:57.073339 TrainedVREFDQ_A0==77
723 23:17:57.073888 TrainedVREFDQ_A1==77
724 23:17:57.075046 VrefDac_Margin_A0==23
725 23:17:57.077722 DeviceVref_Margin_A0==37
726 23:17:57.080130 VrefDac_Margin_A1==24
727 23:17:57.083751 DeviceVref_Margin_A1==37
728 23:17:57.084934
729 23:17:57.085945 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 23:17:57.086369
731 23:17:57.117352 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
732 23:17:57.117970 2D training succeed
733 23:17:57.122584 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 23:17:57.128141 auto size-- 65535DDR cs0 size: 2048MB
735 23:17:57.129871 DDR cs1 size: 2048MB
736 23:17:57.133709 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 23:17:57.134237 cs0 DataBus test pass
738 23:17:57.139409 cs1 DataBus test pass
739 23:17:57.139914 cs0 AddrBus test pass
740 23:17:57.140362 cs1 AddrBus test pass
741 23:17:57.140758
742 23:17:57.145046 100bdlr_step_size ps== 420
743 23:17:57.145588 result report
744 23:17:57.150449 boot times 0Enable ddr reg access
745 23:17:57.155787 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 23:17:57.169119 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 23:17:57.742840 0.0;M3 CHK:0;cm4_sp_mode 0
748 23:17:57.743470 MVN_1=0x00000000
749 23:17:57.748323 MVN_2=0x00000000
750 23:17:57.754124 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 23:17:57.754642 OPS=0x10
752 23:17:57.755045 ring efuse init
753 23:17:57.755438 chipver efuse init
754 23:17:57.759604 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 23:17:57.765201 [0.018961 Inits done]
756 23:17:57.765680 secure task start!
757 23:17:57.766078 high task start!
758 23:17:57.769780 low task start!
759 23:17:57.770240 run into bl31
760 23:17:57.776400 NOTICE: BL31: v1.3(release):4fc40b1
761 23:17:57.784253 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 23:17:57.784746 NOTICE: BL31: G12A normal boot!
763 23:17:57.809650 NOTICE: BL31: BL33 decompress pass
764 23:17:57.815339 ERROR: Error initializing runtime service opteed_fast
765 23:17:59.048226
766 23:17:59.048857
767 23:17:59.056582 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 23:17:59.057067
769 23:17:59.057504 Model: Libre Computer AML-A311D-CC Alta
770 23:17:59.264962 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 23:17:59.288449 DRAM: 2 GiB (effective 3.8 GiB)
772 23:17:59.431439 Core: 408 devices, 31 uclasses, devicetree: separate
773 23:17:59.437230 WDT: Not starting watchdog@f0d0
774 23:17:59.469618 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 23:17:59.482041 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 23:17:59.487047 ** Bad device specification mmc 0 **
777 23:17:59.497489 Card did not respond to voltage select! : -110
778 23:17:59.504967 ** Bad device specification mmc 0 **
779 23:17:59.505513 Couldn't find partition mmc 0
780 23:17:59.513472 Card did not respond to voltage select! : -110
781 23:17:59.518799 ** Bad device specification mmc 0 **
782 23:17:59.519301 Couldn't find partition mmc 0
783 23:17:59.523937 Error: could not access storage.
784 23:17:59.867374 Net: eth0: ethernet@ff3f0000
785 23:17:59.867975 starting USB...
786 23:18:00.119232 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 23:18:00.119853 Starting the controller
788 23:18:00.126204 USB XHCI 1.10
789 23:18:02.286404 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 23:18:02.287028 bl2_stage_init 0x01
791 23:18:02.287460 bl2_stage_init 0x81
792 23:18:02.292111 hw id: 0x0000 - pwm id 0x01
793 23:18:02.292593 bl2_stage_init 0xc1
794 23:18:02.293007 bl2_stage_init 0x02
795 23:18:02.293409
796 23:18:02.297811 L0:00000000
797 23:18:02.298280 L1:20000703
798 23:18:02.298692 L2:00008067
799 23:18:02.299092 L3:14000000
800 23:18:02.303254 B2:00402000
801 23:18:02.303715 B1:e0f83180
802 23:18:02.304207
803 23:18:02.304619 TE: 58124
804 23:18:02.305020
805 23:18:02.308956 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 23:18:02.309439
807 23:18:02.309851 Board ID = 1
808 23:18:02.314393 Set A53 clk to 24M
809 23:18:02.314862 Set A73 clk to 24M
810 23:18:02.315271 Set clk81 to 24M
811 23:18:02.320121 A53 clk: 1200 MHz
812 23:18:02.320600 A73 clk: 1200 MHz
813 23:18:02.321006 CLK81: 166.6M
814 23:18:02.321401 smccc: 00012a91
815 23:18:02.325697 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 23:18:02.331175 board id: 1
817 23:18:02.337348 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 23:18:02.347739 fw parse done
819 23:18:02.353728 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 23:18:02.396279 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 23:18:02.407217 PIEI prepare done
822 23:18:02.407720 fastboot data load
823 23:18:02.408189 fastboot data verify
824 23:18:02.412957 verify result: 266
825 23:18:02.418430 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 23:18:02.418922 LPDDR4 probe
827 23:18:02.419337 ddr clk to 1584MHz
828 23:18:02.426379 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 23:18:02.463658
830 23:18:02.464232 dmc_version 0001
831 23:18:02.470355 Check phy result
832 23:18:02.476259 INFO : End of CA training
833 23:18:02.476735 INFO : End of initialization
834 23:18:02.481909 INFO : Training has run successfully!
835 23:18:02.482376 Check phy result
836 23:18:02.487457 INFO : End of initialization
837 23:18:02.487933 INFO : End of read enable training
838 23:18:02.490758 INFO : End of fine write leveling
839 23:18:02.496355 INFO : End of Write leveling coarse delay
840 23:18:02.501929 INFO : Training has run successfully!
841 23:18:02.502439 Check phy result
842 23:18:02.502864 INFO : End of initialization
843 23:18:02.507578 INFO : End of read dq deskew training
844 23:18:02.513163 INFO : End of MPR read delay center optimization
845 23:18:02.513658 INFO : End of write delay center optimization
846 23:18:02.518706 INFO : End of read delay center optimization
847 23:18:02.524345 INFO : End of max read latency training
848 23:18:02.524834 INFO : Training has run successfully!
849 23:18:02.529981 1D training succeed
850 23:18:02.535804 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 23:18:02.583373 Check phy result
852 23:18:02.583951 INFO : End of initialization
853 23:18:02.605003 INFO : End of 2D read delay Voltage center optimization
854 23:18:02.625022 INFO : End of 2D read delay Voltage center optimization
855 23:18:02.677144 INFO : End of 2D write delay Voltage center optimization
856 23:18:02.726222 INFO : End of 2D write delay Voltage center optimization
857 23:18:02.731876 INFO : Training has run successfully!
858 23:18:02.732395
859 23:18:02.732832 channel==0
860 23:18:02.737492 RxClkDly_Margin_A0==88 ps 9
861 23:18:02.737973 TxDqDly_Margin_A0==98 ps 10
862 23:18:02.740829 RxClkDly_Margin_A1==88 ps 9
863 23:18:02.741294 TxDqDly_Margin_A1==98 ps 10
864 23:18:02.746385 TrainedVREFDQ_A0==74
865 23:18:02.746861 TrainedVREFDQ_A1==74
866 23:18:02.747292 VrefDac_Margin_A0==25
867 23:18:02.752137 DeviceVref_Margin_A0==40
868 23:18:02.752638 VrefDac_Margin_A1==25
869 23:18:02.757567 DeviceVref_Margin_A1==40
870 23:18:02.758057
871 23:18:02.758452
872 23:18:02.758838 channel==1
873 23:18:02.759218 RxClkDly_Margin_A0==98 ps 10
874 23:18:02.761040 TxDqDly_Margin_A0==88 ps 9
875 23:18:02.766693 RxClkDly_Margin_A1==98 ps 10
876 23:18:02.767147 TxDqDly_Margin_A1==88 ps 9
877 23:18:02.767565 TrainedVREFDQ_A0==77
878 23:18:02.772263 TrainedVREFDQ_A1==77
879 23:18:02.772727 VrefDac_Margin_A0==22
880 23:18:02.777772 DeviceVref_Margin_A0==37
881 23:18:02.778235 VrefDac_Margin_A1==22
882 23:18:02.778627 DeviceVref_Margin_A1==37
883 23:18:02.779012
884 23:18:02.783387 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 23:18:02.783844
886 23:18:02.816967 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
887 23:18:02.817545 2D training succeed
888 23:18:02.822591 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 23:18:02.828222 auto size-- 65535DDR cs0 size: 2048MB
890 23:18:02.828684 DDR cs1 size: 2048MB
891 23:18:02.833769 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 23:18:02.834227 cs0 DataBus test pass
893 23:18:02.834615 cs1 DataBus test pass
894 23:18:02.839398 cs0 AddrBus test pass
895 23:18:02.839851 cs1 AddrBus test pass
896 23:18:02.840285
897 23:18:02.845015 100bdlr_step_size ps== 420
898 23:18:02.845477 result report
899 23:18:02.845865 boot times 0Enable ddr reg access
900 23:18:02.854746 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 23:18:02.868197 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 23:18:03.440074 0.0;M3 CHK:0;cm4_sp_mode 0
903 23:18:03.440538 MVN_1=0x00000000
904 23:18:03.445780 MVN_2=0x00000000
905 23:18:03.451440 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 23:18:03.451928 OPS=0x10
907 23:18:03.452390 ring efuse init
908 23:18:03.452799 chipver efuse init
909 23:18:03.457031 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 23:18:03.462648 [0.018960 Inits done]
911 23:18:03.463130 secure task start!
912 23:18:03.463541 high task start!
913 23:18:03.467151 low task start!
914 23:18:03.467617 run into bl31
915 23:18:03.473836 NOTICE: BL31: v1.3(release):4fc40b1
916 23:18:03.481632 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 23:18:03.482117 NOTICE: BL31: G12A normal boot!
918 23:18:03.507085 NOTICE: BL31: BL33 decompress pass
919 23:18:03.512719 ERROR: Error initializing runtime service opteed_fast
920 23:18:04.745377
921 23:18:04.745774
922 23:18:04.753819 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 23:18:04.754132
924 23:18:04.754351 Model: Libre Computer AML-A311D-CC Alta
925 23:18:04.962231 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 23:18:04.985699 DRAM: 2 GiB (effective 3.8 GiB)
927 23:18:05.128636 Core: 408 devices, 31 uclasses, devicetree: separate
928 23:18:05.134498 WDT: Not starting watchdog@f0d0
929 23:18:05.166859 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 23:18:05.179219 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 23:18:05.184183 ** Bad device specification mmc 0 **
932 23:18:05.194553 Card did not respond to voltage select! : -110
933 23:18:05.202166 ** Bad device specification mmc 0 **
934 23:18:05.202472 Couldn't find partition mmc 0
935 23:18:05.210636 Card did not respond to voltage select! : -110
936 23:18:05.216070 ** Bad device specification mmc 0 **
937 23:18:05.216382 Couldn't find partition mmc 0
938 23:18:05.221111 Error: could not access storage.
939 23:18:05.563647 Net: eth0: ethernet@ff3f0000
940 23:18:05.564352 starting USB...
941 23:18:05.815446 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 23:18:05.816144 Starting the controller
943 23:18:05.822330 USB XHCI 1.10
944 23:18:07.376597 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 23:18:07.384832 scanning usb for storage devices... 0 Storage Device(s) found
947 23:18:07.436354 Hit any key to stop autoboot: 1
948 23:18:07.437305 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
949 23:18:07.437948 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
950 23:18:07.438428 Setting prompt string to ['=>']
951 23:18:07.438915 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
952 23:18:07.452334 0
953 23:18:07.453306 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 23:18:07.453823 Sending with 10 millisecond of delay
956 23:18:08.589238 => setenv autoload no
957 23:18:08.600170 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
958 23:18:08.605099 setenv autoload no
959 23:18:08.605950 Sending with 10 millisecond of delay
961 23:18:10.403232 => setenv initrd_high 0xffffffff
962 23:18:10.414017 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
963 23:18:10.414912 setenv initrd_high 0xffffffff
964 23:18:10.415631 Sending with 10 millisecond of delay
966 23:18:12.032517 => setenv fdt_high 0xffffffff
967 23:18:12.043332 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
968 23:18:12.044252 setenv fdt_high 0xffffffff
969 23:18:12.044960 Sending with 10 millisecond of delay
971 23:18:12.336777 => dhcp
972 23:18:12.347552 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
973 23:18:12.348431 dhcp
974 23:18:12.348859 Speed: 1000, full duplex
975 23:18:12.349256 BOOTP broadcast 1
976 23:18:12.360671 DHCP client bound to address 192.168.6.27 (13 ms)
977 23:18:12.361402 Sending with 10 millisecond of delay
979 23:18:14.039342 => setenv serverip 192.168.6.2
980 23:18:14.050322 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
981 23:18:14.051224 setenv serverip 192.168.6.2
982 23:18:14.051909 Sending with 10 millisecond of delay
984 23:18:17.776157 => tftpboot 0x01080000 963343/tftp-deploy-4z4vss2q/kernel/uImage
985 23:18:17.786919 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
986 23:18:17.787769 tftpboot 0x01080000 963343/tftp-deploy-4z4vss2q/kernel/uImage
987 23:18:17.788297 Speed: 1000, full duplex
988 23:18:17.788720 Using ethernet@ff3f0000 device
989 23:18:17.789872 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
990 23:18:17.795283 Filename '963343/tftp-deploy-4z4vss2q/kernel/uImage'.
991 23:18:17.799248 Load address: 0x1080000
992 23:18:20.705290 Loading: *################################################## 43.6 MiB
993 23:18:20.705915 15 MiB/s
994 23:18:20.706350 done
995 23:18:20.709601 Bytes transferred = 45713984 (2b98a40 hex)
996 23:18:20.710423 Sending with 10 millisecond of delay
998 23:18:25.399564 => tftpboot 0x08000000 963343/tftp-deploy-4z4vss2q/ramdisk/ramdisk.cpio.gz.uboot
999 23:18:25.410433 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1000 23:18:25.411451 tftpboot 0x08000000 963343/tftp-deploy-4z4vss2q/ramdisk/ramdisk.cpio.gz.uboot
1001 23:18:25.411967 Speed: 1000, full duplex
1002 23:18:25.412589 Using ethernet@ff3f0000 device
1003 23:18:25.413525 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1004 23:18:25.424877 Filename '963343/tftp-deploy-4z4vss2q/ramdisk/ramdisk.cpio.gz.uboot'.
1005 23:18:25.425506 Load address: 0x8000000
1006 23:18:32.070694 Loading: *################T ################################# UDP wrong checksum 00000005 00008b81
1007 23:18:34.475754 UDP wrong checksum 000000ff 0000b146
1008 23:18:34.488872 UDP wrong checksum 000000ff 00003a39
1009 23:18:37.072709 T UDP wrong checksum 00000005 00008b81
1010 23:18:47.074646 T T UDP wrong checksum 00000005 00008b81
1011 23:19:07.078970 T T T T UDP wrong checksum 00000005 00008b81
1012 23:19:15.687043 T UDP wrong checksum 000000ff 0000080a
1013 23:19:15.737299 UDP wrong checksum 000000ff 00009afc
1014 23:19:22.083042 T
1015 23:19:22.083473 Retry count exceeded; starting again
1017 23:19:22.084459 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1020 23:19:22.086506 end: 2.4 uboot-commands (duration 00:01:47) [common]
1022 23:19:22.088036 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1024 23:19:22.089182 end: 2 uboot-action (duration 00:01:47) [common]
1026 23:19:22.090873 Cleaning after the job
1027 23:19:22.091491 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/ramdisk
1028 23:19:22.092882 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/kernel
1029 23:19:22.143218 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/dtb
1030 23:19:22.144205 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/nfsrootfs
1031 23:19:22.197619 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/963343/tftp-deploy-4z4vss2q/modules
1032 23:19:22.202988 start: 4.1 power-off (timeout 00:00:30) [common]
1033 23:19:22.203728 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1034 23:19:22.269790 >> OK - accepted request
1035 23:19:22.272894 Returned 0 in 0 seconds
1036 23:19:22.373689 end: 4.1 power-off (duration 00:00:00) [common]
1038 23:19:22.374752 start: 4.2 read-feedback (timeout 00:10:00) [common]
1039 23:19:22.375438 Listened to connection for namespace 'common' for up to 1s
1040 23:19:23.375512 Finalising connection for namespace 'common'
1041 23:19:23.376358 Disconnecting from shell: Finalise
1042 23:19:23.376963 =>
1043 23:19:23.478130 end: 4.2 read-feedback (duration 00:00:01) [common]
1044 23:19:23.478892 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/963343
1045 23:19:26.050066 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/963343
1046 23:19:26.050661 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.