Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 02:34:39.308272 lava-dispatcher, installed at version: 2024.01
2 02:34:39.309093 start: 0 validate
3 02:34:39.309566 Start time: 2024-11-09 02:34:39.309536+00:00 (UTC)
4 02:34:39.310135 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 02:34:39.310676 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 02:34:39.343592 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 02:34:39.344131 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-272-gda4373fbcf006%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fkernel%2FzImage exists
8 02:34:39.369831 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 02:34:39.370452 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-272-gda4373fbcf006%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 02:34:39.393208 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 02:34:39.393716 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 02:34:39.421496 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 02:34:39.422000 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc6-272-gda4373fbcf006%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fmodules.tar.xz exists
14 02:34:39.454421 validate duration: 0.15
16 02:34:39.455318 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:34:39.455638 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:34:39.455922 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:34:39.456508 Not decompressing ramdisk as can be used compressed.
20 02:34:39.456923 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 02:34:39.457193 saving as /var/lib/lava/dispatcher/tmp/964144/tftp-deploy-t63sa4n0/ramdisk/initrd.cpio.gz
22 02:34:39.457457 total size: 4775763 (4 MB)
23 02:34:39.492346 progress 0 % (0 MB)
24 02:34:39.495982 progress 5 % (0 MB)
25 02:34:39.499223 progress 10 % (0 MB)
26 02:34:39.502512 progress 15 % (0 MB)
27 02:34:39.506022 progress 20 % (0 MB)
28 02:34:39.509055 progress 25 % (1 MB)
29 02:34:39.512226 progress 30 % (1 MB)
30 02:34:39.515737 progress 35 % (1 MB)
31 02:34:39.518847 progress 40 % (1 MB)
32 02:34:39.522032 progress 45 % (2 MB)
33 02:34:39.525107 progress 50 % (2 MB)
34 02:34:39.528632 progress 55 % (2 MB)
35 02:34:39.531714 progress 60 % (2 MB)
36 02:34:39.534829 progress 65 % (2 MB)
37 02:34:39.538219 progress 70 % (3 MB)
38 02:34:39.541300 progress 75 % (3 MB)
39 02:34:39.544265 progress 80 % (3 MB)
40 02:34:39.547172 progress 85 % (3 MB)
41 02:34:39.550456 progress 90 % (4 MB)
42 02:34:39.553392 progress 95 % (4 MB)
43 02:34:39.556308 progress 100 % (4 MB)
44 02:34:39.556967 4 MB downloaded in 0.10 s (45.78 MB/s)
45 02:34:39.557522 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:34:39.558423 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:34:39.558730 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:34:39.559014 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:34:39.559512 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-272-gda4373fbcf006/arm/multi_v7_defconfig/clang-15/kernel/zImage
51 02:34:39.559784 saving as /var/lib/lava/dispatcher/tmp/964144/tftp-deploy-t63sa4n0/kernel/zImage
52 02:34:39.560025 total size: 12050944 (11 MB)
53 02:34:39.560253 No compression specified
54 02:34:39.592902 progress 0 % (0 MB)
55 02:34:39.600420 progress 5 % (0 MB)
56 02:34:39.607869 progress 10 % (1 MB)
57 02:34:39.615793 progress 15 % (1 MB)
58 02:34:39.623427 progress 20 % (2 MB)
59 02:34:39.631256 progress 25 % (2 MB)
60 02:34:39.639389 progress 30 % (3 MB)
61 02:34:39.647299 progress 35 % (4 MB)
62 02:34:39.655184 progress 40 % (4 MB)
63 02:34:39.662600 progress 45 % (5 MB)
64 02:34:39.670031 progress 50 % (5 MB)
65 02:34:39.677826 progress 55 % (6 MB)
66 02:34:39.685123 progress 60 % (6 MB)
67 02:34:39.692840 progress 65 % (7 MB)
68 02:34:39.700204 progress 70 % (8 MB)
69 02:34:39.707562 progress 75 % (8 MB)
70 02:34:39.715326 progress 80 % (9 MB)
71 02:34:39.722677 progress 85 % (9 MB)
72 02:34:39.730027 progress 90 % (10 MB)
73 02:34:39.737428 progress 95 % (10 MB)
74 02:34:39.744333 progress 100 % (11 MB)
75 02:34:39.745113 11 MB downloaded in 0.19 s (62.10 MB/s)
76 02:34:39.745608 end: 1.2.1 http-download (duration 00:00:00) [common]
78 02:34:39.746465 end: 1.2 download-retry (duration 00:00:00) [common]
79 02:34:39.746752 start: 1.3 download-retry (timeout 00:10:00) [common]
80 02:34:39.747023 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 02:34:39.747494 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-272-gda4373fbcf006/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
82 02:34:39.747762 saving as /var/lib/lava/dispatcher/tmp/964144/tftp-deploy-t63sa4n0/dtb/am335x-boneblack.dtb
83 02:34:39.747976 total size: 70568 (0 MB)
84 02:34:39.748190 No compression specified
85 02:34:39.781650 progress 46 % (0 MB)
86 02:34:39.782482 progress 92 % (0 MB)
87 02:34:39.783118 progress 100 % (0 MB)
88 02:34:39.783479 0 MB downloaded in 0.04 s (1.90 MB/s)
89 02:34:39.783920 end: 1.3.1 http-download (duration 00:00:00) [common]
91 02:34:39.784716 end: 1.3 download-retry (duration 00:00:00) [common]
92 02:34:39.784977 start: 1.4 download-retry (timeout 00:10:00) [common]
93 02:34:39.785237 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 02:34:39.785679 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 02:34:39.785940 saving as /var/lib/lava/dispatcher/tmp/964144/tftp-deploy-t63sa4n0/nfsrootfs/full.rootfs.tar
96 02:34:39.786161 total size: 117747780 (112 MB)
97 02:34:39.786373 Using unxz to decompress xz
98 02:34:39.818565 progress 0 % (0 MB)
99 02:34:40.548535 progress 5 % (5 MB)
100 02:34:41.287476 progress 10 % (11 MB)
101 02:34:42.050543 progress 15 % (16 MB)
102 02:34:42.760562 progress 20 % (22 MB)
103 02:34:43.338564 progress 25 % (28 MB)
104 02:34:44.143155 progress 30 % (33 MB)
105 02:34:44.954777 progress 35 % (39 MB)
106 02:34:45.284915 progress 40 % (44 MB)
107 02:34:45.643974 progress 45 % (50 MB)
108 02:34:46.309905 progress 50 % (56 MB)
109 02:34:47.120412 progress 55 % (61 MB)
110 02:34:47.841363 progress 60 % (67 MB)
111 02:34:48.552066 progress 65 % (73 MB)
112 02:34:49.303661 progress 70 % (78 MB)
113 02:34:50.067215 progress 75 % (84 MB)
114 02:34:50.791780 progress 80 % (89 MB)
115 02:34:51.494993 progress 85 % (95 MB)
116 02:34:52.273658 progress 90 % (101 MB)
117 02:34:53.027213 progress 95 % (106 MB)
118 02:34:53.837503 progress 100 % (112 MB)
119 02:34:53.849800 112 MB downloaded in 14.06 s (7.98 MB/s)
120 02:34:53.850820 end: 1.4.1 http-download (duration 00:00:14) [common]
122 02:34:53.852611 end: 1.4 download-retry (duration 00:00:14) [common]
123 02:34:53.853193 start: 1.5 download-retry (timeout 00:09:46) [common]
124 02:34:53.853881 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 02:34:53.854866 downloading http://storage.kernelci.org/mainline/master/v6.12-rc6-272-gda4373fbcf006/arm/multi_v7_defconfig/clang-15/modules.tar.xz
126 02:34:53.855389 saving as /var/lib/lava/dispatcher/tmp/964144/tftp-deploy-t63sa4n0/modules/modules.tar
127 02:34:53.855970 total size: 6915224 (6 MB)
128 02:34:53.856512 Using unxz to decompress xz
129 02:34:53.895794 progress 0 % (0 MB)
130 02:34:53.931412 progress 5 % (0 MB)
131 02:34:53.979134 progress 10 % (0 MB)
132 02:34:54.022670 progress 15 % (1 MB)
133 02:34:54.072885 progress 20 % (1 MB)
134 02:34:54.118643 progress 25 % (1 MB)
135 02:34:54.168481 progress 30 % (2 MB)
136 02:34:54.211342 progress 35 % (2 MB)
137 02:34:54.258216 progress 40 % (2 MB)
138 02:34:54.301240 progress 45 % (2 MB)
139 02:34:54.351269 progress 50 % (3 MB)
140 02:34:54.398061 progress 55 % (3 MB)
141 02:34:54.444587 progress 60 % (3 MB)
142 02:34:54.492077 progress 65 % (4 MB)
143 02:34:54.537718 progress 70 % (4 MB)
144 02:34:54.587306 progress 75 % (4 MB)
145 02:34:54.630006 progress 80 % (5 MB)
146 02:34:54.677839 progress 85 % (5 MB)
147 02:34:54.721474 progress 90 % (5 MB)
148 02:34:54.769166 progress 95 % (6 MB)
149 02:34:54.816947 progress 100 % (6 MB)
150 02:34:54.827059 6 MB downloaded in 0.97 s (6.79 MB/s)
151 02:34:54.827976 end: 1.5.1 http-download (duration 00:00:01) [common]
153 02:34:54.829709 end: 1.5 download-retry (duration 00:00:01) [common]
154 02:34:54.830337 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 02:34:54.830908 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 02:35:11.346280 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/964144/extract-nfsrootfs-x0_hsi2i
157 02:35:11.346860 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 02:35:11.347146 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 02:35:11.347748 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am
160 02:35:11.348175 makedir: /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin
161 02:35:11.348501 makedir: /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/tests
162 02:35:11.348819 makedir: /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/results
163 02:35:11.349166 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-add-keys
164 02:35:11.349702 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-add-sources
165 02:35:11.350260 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-background-process-start
166 02:35:11.350778 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-background-process-stop
167 02:35:11.351308 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-common-functions
168 02:35:11.351838 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-echo-ipv4
169 02:35:11.352338 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-install-packages
170 02:35:11.352846 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-installed-packages
171 02:35:11.353336 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-os-build
172 02:35:11.353834 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-probe-channel
173 02:35:11.354374 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-probe-ip
174 02:35:11.354898 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-target-ip
175 02:35:11.355427 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-target-mac
176 02:35:11.355925 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-target-storage
177 02:35:11.356411 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-test-case
178 02:35:11.356945 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-test-event
179 02:35:11.357432 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-test-feedback
180 02:35:11.357934 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-test-raise
181 02:35:11.358437 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-test-reference
182 02:35:11.358922 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-test-runner
183 02:35:11.359419 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-test-set
184 02:35:11.359901 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-test-shell
185 02:35:11.360385 Updating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-add-keys (debian)
186 02:35:11.360935 Updating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-add-sources (debian)
187 02:35:11.361441 Updating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-install-packages (debian)
188 02:35:11.361970 Updating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-installed-packages (debian)
189 02:35:11.362479 Updating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/bin/lava-os-build (debian)
190 02:35:11.362908 Creating /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/environment
191 02:35:11.363287 LAVA metadata
192 02:35:11.363549 - LAVA_JOB_ID=964144
193 02:35:11.363764 - LAVA_DISPATCHER_IP=192.168.6.3
194 02:35:11.364126 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 02:35:11.365082 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 02:35:11.365397 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 02:35:11.365612 skipped lava-vland-overlay
198 02:35:11.365883 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 02:35:11.366147 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 02:35:11.366364 skipped lava-multinode-overlay
201 02:35:11.366603 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 02:35:11.366873 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 02:35:11.367134 Loading test definitions
204 02:35:11.367412 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 02:35:11.367648 Using /lava-964144 at stage 0
206 02:35:11.368750 uuid=964144_1.6.2.4.1 testdef=None
207 02:35:11.369065 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 02:35:11.369334 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 02:35:11.371054 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 02:35:11.371838 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 02:35:11.373854 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 02:35:11.374693 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 02:35:11.376518 runner path: /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/0/tests/0_timesync-off test_uuid 964144_1.6.2.4.1
216 02:35:11.377073 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 02:35:11.377912 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 02:35:11.378163 Using /lava-964144 at stage 0
220 02:35:11.378530 Fetching tests from https://github.com/kernelci/test-definitions.git
221 02:35:11.378817 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/0/tests/1_kselftest-dt'
222 02:35:14.816508 Running '/usr/bin/git checkout kernelci.org
223 02:35:15.263734 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 02:35:15.265139 uuid=964144_1.6.2.4.5 testdef=None
225 02:35:15.265469 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 02:35:15.266269 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 02:35:15.269032 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 02:35:15.269876 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 02:35:15.273669 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 02:35:15.274539 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 02:35:15.278104 runner path: /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/0/tests/1_kselftest-dt test_uuid 964144_1.6.2.4.5
235 02:35:15.278386 BOARD='beaglebone-black'
236 02:35:15.278593 BRANCH='mainline'
237 02:35:15.278790 SKIPFILE='/dev/null'
238 02:35:15.278985 SKIP_INSTALL='True'
239 02:35:15.279179 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc6-272-gda4373fbcf006/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
240 02:35:15.279379 TST_CASENAME=''
241 02:35:15.279575 TST_CMDFILES='dt'
242 02:35:15.280131 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 02:35:15.280909 Creating lava-test-runner.conf files
245 02:35:15.281112 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/964144/lava-overlay-vp_7g6am/lava-964144/0 for stage 0
246 02:35:15.281454 - 0_timesync-off
247 02:35:15.281685 - 1_kselftest-dt
248 02:35:15.282029 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 02:35:15.282309 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 02:35:38.662560 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 02:35:38.663001 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 02:35:38.663265 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 02:35:38.663535 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 02:35:38.663798 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 02:35:39.020165 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 02:35:39.020619 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 02:35:39.020900 extracting modules file /var/lib/lava/dispatcher/tmp/964144/tftp-deploy-t63sa4n0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964144/extract-nfsrootfs-x0_hsi2i
258 02:35:39.940515 extracting modules file /var/lib/lava/dispatcher/tmp/964144/tftp-deploy-t63sa4n0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/964144/extract-overlay-ramdisk-00ug9ux_/ramdisk
259 02:35:40.863042 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 02:35:40.863508 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 02:35:40.863787 [common] Applying overlay to NFS
262 02:35:40.864000 [common] Applying overlay /var/lib/lava/dispatcher/tmp/964144/compress-overlay-sy9ify6i/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/964144/extract-nfsrootfs-x0_hsi2i
263 02:35:43.617576 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 02:35:43.618088 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 02:35:43.618370 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 02:35:43.618646 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 02:35:43.618900 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 02:35:43.619156 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 02:35:43.619405 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 02:35:43.619659 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 02:35:43.619908 Building ramdisk /var/lib/lava/dispatcher/tmp/964144/extract-overlay-ramdisk-00ug9ux_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/964144/extract-overlay-ramdisk-00ug9ux_/ramdisk
272 02:35:44.659916 >> 79013 blocks
273 02:35:49.803912 Adding RAMdisk u-boot header.
274 02:35:49.804670 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/964144/extract-overlay-ramdisk-00ug9ux_/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/964144/extract-overlay-ramdisk-00ug9ux_/ramdisk.cpio.gz.uboot
275 02:35:49.965442 output: Image Name:
276 02:35:49.966163 output: Created: Sat Nov 9 02:35:49 2024
277 02:35:49.966646 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 02:35:49.967109 output: Data Size: 15350250 Bytes = 14990.48 KiB = 14.64 MiB
279 02:35:49.967563 output: Load Address: 00000000
280 02:35:49.968010 output: Entry Point: 00000000
281 02:35:49.968454 output:
282 02:35:49.969564 rename /var/lib/lava/dispatcher/tmp/964144/extract-overlay-ramdisk-00ug9ux_/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/964144/tftp-deploy-t63sa4n0/ramdisk/ramdisk.cpio.gz.uboot
283 02:35:49.970412 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 02:35:49.971036 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 02:35:49.971629 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 02:35:49.972140 No LXC device requested
287 02:35:49.972703 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 02:35:49.973273 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 02:35:49.973847 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 02:35:49.974321 Checking files for TFTP limit of 4294967296 bytes.
291 02:35:49.977252 end: 1 tftp-deploy (duration 00:01:11) [common]
292 02:35:49.977912 start: 2 uboot-action (timeout 00:05:00) [common]
293 02:35:49.978514 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 02:35:49.979073 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 02:35:49.979633 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 02:35:49.980461 substitutions:
297 02:35:49.980936 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 02:35:49.981391 - {DTB_ADDR}: 0x88000000
299 02:35:49.981863 - {DTB}: 964144/tftp-deploy-t63sa4n0/dtb/am335x-boneblack.dtb
300 02:35:49.982316 - {INITRD}: 964144/tftp-deploy-t63sa4n0/ramdisk/ramdisk.cpio.gz.uboot
301 02:35:49.982760 - {KERNEL_ADDR}: 0x82000000
302 02:35:49.983199 - {KERNEL}: 964144/tftp-deploy-t63sa4n0/kernel/zImage
303 02:35:49.983634 - {LAVA_MAC}: None
304 02:35:49.984118 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/964144/extract-nfsrootfs-x0_hsi2i
305 02:35:49.984564 - {NFS_SERVER_IP}: 192.168.6.3
306 02:35:49.985001 - {PRESEED_CONFIG}: None
307 02:35:49.985437 - {PRESEED_LOCAL}: None
308 02:35:49.985893 - {RAMDISK_ADDR}: 0x83000000
309 02:35:49.986334 - {RAMDISK}: 964144/tftp-deploy-t63sa4n0/ramdisk/ramdisk.cpio.gz.uboot
310 02:35:49.986771 - {ROOT_PART}: None
311 02:35:49.987206 - {ROOT}: None
312 02:35:49.987639 - {SERVER_IP}: 192.168.6.3
313 02:35:49.988069 - {TEE_ADDR}: 0x83000000
314 02:35:49.988494 - {TEE}: None
315 02:35:49.988922 Parsed boot commands:
316 02:35:49.989342 - setenv autoload no
317 02:35:49.989768 - setenv initrd_high 0xffffffff
318 02:35:49.990226 - setenv fdt_high 0xffffffff
319 02:35:49.990657 - dhcp
320 02:35:49.991084 - setenv serverip 192.168.6.3
321 02:35:49.991511 - tftp 0x82000000 964144/tftp-deploy-t63sa4n0/kernel/zImage
322 02:35:49.991941 - tftp 0x83000000 964144/tftp-deploy-t63sa4n0/ramdisk/ramdisk.cpio.gz.uboot
323 02:35:49.992369 - setenv initrd_size ${filesize}
324 02:35:49.992797 - tftp 0x88000000 964144/tftp-deploy-t63sa4n0/dtb/am335x-boneblack.dtb
325 02:35:49.993226 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/964144/extract-nfsrootfs-x0_hsi2i,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 02:35:49.993665 - bootz 0x82000000 0x83000000 0x88000000
327 02:35:49.994247 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 02:35:49.995905 start: 2.3 connect-device (timeout 00:05:00) [common]
330 02:35:49.996373 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 02:35:50.011811 Setting prompt string to ['lava-test: # ']
332 02:35:50.013406 end: 2.3 connect-device (duration 00:00:00) [common]
333 02:35:50.014140 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 02:35:50.014795 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 02:35:50.015405 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 02:35:50.016739 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 02:35:50.054877 >> OK - accepted request
338 02:35:50.056794 Returned 0 in 0 seconds
339 02:35:50.158065 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 02:35:50.159986 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 02:35:50.160661 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 02:35:50.161267 Setting prompt string to ['Hit any key to stop autoboot']
344 02:35:50.161801 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 02:35:50.163582 Trying 192.168.56.22...
346 02:35:50.164147 Connected to conserv3.
347 02:35:50.164637 Escape character is '^]'.
348 02:35:50.165109
349 02:35:50.165585 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 02:35:50.166114
351 02:35:58.816886
352 02:35:58.823294 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 02:35:58.823837 Trying to boot from MMC1
354 02:36:02.879756
355 02:36:02.886709 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 02:36:02.887281 Trying to boot from MMC1
357 02:36:05.563124
358 02:36:05.570166 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 02:36:05.570489 Trying to boot from MMC1
360 02:36:06.153639
361 02:36:06.154093
362 02:36:06.159066 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 02:36:06.159560
364 02:36:06.159967 CPU : AM335X-GP rev 2.0
365 02:36:06.164206 Model: TI AM335x BeagleBone Black
366 02:36:06.164549 DRAM: 512 MiB
367 02:36:06.243933 Core: 160 devices, 18 uclasses, devicetree: separate
368 02:36:06.258134 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 02:36:06.658810 NAND: 0 MiB
370 02:36:06.668903 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 02:36:06.791184 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 02:36:06.811918 <ethaddr> not set. Validating first E-fuse MAC
373 02:36:06.842919 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 02:36:06.901567 Hit any key to stop autoboot: 2
376 02:36:06.904457 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
377 02:36:06.905519 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
378 02:36:06.905795 Setting prompt string to ['=>']
379 02:36:06.906121 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
380 02:36:06.911603 0
381 02:36:06.913618 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 02:36:06.914879 Sending with 10 millisecond of delay
384 02:36:08.051808 => setenv autoload no
385 02:36:08.063975 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
386 02:36:08.066704 setenv autoload no
387 02:36:08.067229 Sending with 10 millisecond of delay
389 02:36:09.864719 => setenv initrd_high 0xffffffff
390 02:36:09.875586 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
391 02:36:09.876572 setenv initrd_high 0xffffffff
392 02:36:09.877368 Sending with 10 millisecond of delay
394 02:36:11.495606 => setenv fdt_high 0xffffffff
395 02:36:11.506190 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
396 02:36:11.506775 setenv fdt_high 0xffffffff
397 02:36:11.507244 Sending with 10 millisecond of delay
399 02:36:11.798935 => dhcp
400 02:36:11.809517 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
401 02:36:11.810079 dhcp
402 02:36:11.810316 link up on port 0, speed 100, full duplex
403 02:36:11.810533 BOOTP broadcast 1
404 02:36:12.062687 BOOTP broadcast 2
405 02:36:12.565720 BOOTP broadcast 3
406 02:36:13.566789 BOOTP broadcast 4
407 02:36:15.570040 BOOTP broadcast 5
408 02:36:15.703584 DHCP client bound to address 192.168.6.8 (3889 ms)
409 02:36:15.704454 Sending with 10 millisecond of delay
411 02:36:17.380977 => setenv serverip 192.168.6.3
412 02:36:17.391788 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
413 02:36:17.392611 setenv serverip 192.168.6.3
414 02:36:17.393332 Sending with 10 millisecond of delay
416 02:36:20.877125 => tftp 0x82000000 964144/tftp-deploy-t63sa4n0/kernel/zImage
417 02:36:20.892085 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
418 02:36:20.893001 tftp 0x82000000 964144/tftp-deploy-t63sa4n0/kernel/zImage
419 02:36:20.893438 link up on port 0, speed 100, full duplex
420 02:36:20.896422 Using ethernet@4a100000 device
421 02:36:20.901996 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
422 02:36:20.909233 Filename '964144/tftp-deploy-t63sa4n0/kernel/zImage'.
423 02:36:20.909666 Load address: 0x82000000
424 02:36:22.861038 Loading: *################################################## 11.5 MiB
425 02:36:22.861506 5.9 MiB/s
426 02:36:22.861758 done
427 02:36:22.865120 Bytes transferred = 12050944 (b7e200 hex)
428 02:36:22.865970 Sending with 10 millisecond of delay
430 02:36:27.312143 => tftp 0x83000000 964144/tftp-deploy-t63sa4n0/ramdisk/ramdisk.cpio.gz.uboot
431 02:36:27.322973 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
432 02:36:27.323922 tftp 0x83000000 964144/tftp-deploy-t63sa4n0/ramdisk/ramdisk.cpio.gz.uboot
433 02:36:27.324399 link up on port 0, speed 100, full duplex
434 02:36:27.327987 Using ethernet@4a100000 device
435 02:36:27.333503 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
436 02:36:27.342051 Filename '964144/tftp-deploy-t63sa4n0/ramdisk/ramdisk.cpio.gz.uboot'.
437 02:36:27.342574 Load address: 0x83000000
438 02:36:30.219704 Loading: *################################################## 14.6 MiB
439 02:36:30.220389 5.1 MiB/s
440 02:36:30.220869 done
441 02:36:30.224001 Bytes transferred = 15350314 (ea3a2a hex)
442 02:36:30.224852 Sending with 10 millisecond of delay
444 02:36:32.082582 => setenv initrd_size ${filesize}
445 02:36:32.093395 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
446 02:36:32.094327 setenv initrd_size ${filesize}
447 02:36:32.095087 Sending with 10 millisecond of delay
449 02:36:36.242792 => tftp 0x88000000 964144/tftp-deploy-t63sa4n0/dtb/am335x-boneblack.dtb
450 02:36:36.253346 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
451 02:36:36.253959 tftp 0x88000000 964144/tftp-deploy-t63sa4n0/dtb/am335x-boneblack.dtb
452 02:36:36.254254 link up on port 0, speed 100, full duplex
453 02:36:36.258567 Using ethernet@4a100000 device
454 02:36:36.264132 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
455 02:36:36.268116 Filename '964144/tftp-deploy-t63sa4n0/dtb/am335x-boneblack.dtb'.
456 02:36:36.268589 Load address: 0x88000000
457 02:36:36.288514 Loading: *################################################## 68.9 KiB
458 02:36:36.289018 4.5 MiB/s
459 02:36:36.289422 done
460 02:36:36.294263 Bytes transferred = 70568 (113a8 hex)
461 02:36:36.295026 Sending with 10 millisecond of delay
463 02:36:49.490374 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/964144/extract-nfsrootfs-x0_hsi2i,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
464 02:36:49.502103 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
465 02:36:49.503053 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/964144/extract-nfsrootfs-x0_hsi2i,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
466 02:36:49.503774 Sending with 10 millisecond of delay
468 02:36:51.844073 => bootz 0x82000000 0x83000000 0x88000000
469 02:36:51.855003 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
470 02:36:51.855373 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
471 02:36:51.855947 bootz 0x82000000 0x83000000 0x88000000
472 02:36:51.856186 Kernel image @ 0x82000000 [ 0x000000 - 0xb7e200 ]
473 02:36:51.857049 ## Loading init Ramdisk from Legacy Image at 83000000 ...
474 02:36:51.862703 Image Name:
475 02:36:51.863009 Created: 2024-11-09 2:35:49 UTC
476 02:36:51.868167 Image Type: ARM Linux RAMDisk Image (uncompressed)
477 02:36:51.873680 Data Size: 15350250 Bytes = 14.6 MiB
478 02:36:51.874018 Load Address: 00000000
479 02:36:51.879941 Entry Point: 00000000
480 02:36:52.054419 Verifying Checksum ... OK
481 02:36:52.054842 ## Flattened Device Tree blob at 88000000
482 02:36:52.060983 Booting using the fdt blob at 0x88000000
483 02:36:52.061313 Working FDT set to 88000000
484 02:36:52.066425 Using Device Tree in place at 88000000, end 880143a7
485 02:36:52.070945 Working FDT set to 88000000
486 02:36:52.084385
487 02:36:52.084765 Starting kernel ...
488 02:36:52.084976
489 02:36:52.085587 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
490 02:36:52.085957 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
491 02:36:52.086223 Setting prompt string to ['Linux version [0-9]']
492 02:36:52.086469 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
493 02:36:52.086706 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
494 02:36:52.975142 [ 0.000000] Booting Linux on physical CPU 0x0
495 02:36:52.981085 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
496 02:36:52.981713 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
497 02:36:52.982299 Setting prompt string to []
498 02:36:52.982852 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
499 02:36:52.983364 Using line separator: #'\n'#
500 02:36:52.983825 No login prompt set.
501 02:36:52.984307 Parsing kernel messages
502 02:36:52.984753 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
503 02:36:52.985655 [login-action] Waiting for messages, (timeout 00:03:57)
504 02:36:52.986205 Waiting using forced prompt support (timeout 00:01:58)
505 02:36:52.992002 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j370445-arm-clang-15-multi-v7-defconfig-4gx9h) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Sat Nov 9 01:35:35 UTC 2024
506 02:36:52.997787 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
507 02:36:53.009336 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
508 02:36:53.014891 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
509 02:36:53.020738 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
510 02:36:53.026529 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
511 02:36:53.033308 [ 0.000000] Memory policy: Data cache writeback
512 02:36:53.033990 [ 0.000000] efi: UEFI not found.
513 02:36:53.040921 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
514 02:36:53.046440 [ 0.000000] Zone ranges:
515 02:36:53.052170 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
516 02:36:53.057873 [ 0.000000] Normal empty
517 02:36:53.058506 [ 0.000000] HighMem empty
518 02:36:53.061076 [ 0.000000] Movable zone start for each node
519 02:36:53.067072 [ 0.000000] Early memory node ranges
520 02:36:53.072937 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
521 02:36:53.080600 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
522 02:36:53.098746 [ 0.000000] CPU: All CPU(s) started in SVC mode.
523 02:36:53.104238 [ 0.000000] AM335X ES2.0 (sgx neon)
524 02:36:53.116162 [ 0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
525 02:36:53.133842 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/964144/extract-nfsrootfs-x0_hsi2i,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
526 02:36:53.145242 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
527 02:36:53.150988 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
528 02:36:53.156741 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
529 02:36:53.166777 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
530 02:36:53.195998 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
531 02:36:53.201992 <6>[ 0.000000] trace event string verifier disabled
532 02:36:53.202350 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
533 02:36:53.207879 <6>[ 0.000000] rcu: RCU event tracing is enabled.
534 02:36:53.219157 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
535 02:36:53.224897 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
536 02:36:53.232263 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
537 02:36:53.247238 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
538 02:36:53.265345 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
539 02:36:53.272129 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
540 02:36:53.374821 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
541 02:36:53.383360 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
542 02:36:53.395900 <6>[ 0.008339] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
543 02:36:53.404173 <6>[ 0.019230] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
544 02:36:53.414006 <6>[ 0.034500] Console: colour dummy device 80x30
545 02:36:53.419908 Matched prompt #6: WARNING:
546 02:36:53.420281 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
547 02:36:53.425453 <3>[ 0.039400] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
548 02:36:53.431157 <3>[ 0.046475] This ensures that you still see kernel messages. Please
549 02:36:53.434365 <3>[ 0.053206] update your kernel commandline.
550 02:36:53.474976 <6>[ 0.057819] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
551 02:36:53.480438 <6>[ 0.096238] CPU: Testing write buffer coherency: ok
552 02:36:53.486371 <6>[ 0.101612] CPU0: Spectre v2: using BPIALL workaround
553 02:36:53.486770 <6>[ 0.107079] pid_max: default: 32768 minimum: 301
554 02:36:53.497924 <6>[ 0.112278] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
555 02:36:53.506548 <6>[ 0.120104] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
556 02:36:53.511952 <6>[ 0.129553] CPU0: thread -1, cpu 0, socket -1, mpidr 0
557 02:36:53.520517 <6>[ 0.136510] Setting up static identity map for 0x80300000 - 0x803000ac
558 02:36:53.526314 <6>[ 0.146322] rcu: Hierarchical SRCU implementation.
559 02:36:53.534523 <6>[ 0.151610] rcu: Max phase no-delay instances is 1000.
560 02:36:53.542939 <6>[ 0.163201] EFI services will not be available.
561 02:36:53.548847 <6>[ 0.168493] smp: Bringing up secondary CPUs ...
562 02:36:53.554673 <6>[ 0.173551] smp: Brought up 1 node, 1 CPU
563 02:36:53.560270 <6>[ 0.177951] SMP: Total of 1 processors activated (996.14 BogoMIPS).
564 02:36:53.566164 <6>[ 0.184721] CPU: All CPU(s) started in SVC mode.
565 02:36:53.586928 <6>[ 0.189922] Memory: 404432K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50616K reserved, 65536K cma-reserved, 0K highmem)
566 02:36:53.587472 <6>[ 0.206215] devtmpfs: initialized
567 02:36:53.609919 <6>[ 0.223983] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
568 02:36:53.617990 <6>[ 0.232600] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
569 02:36:53.627043 <6>[ 0.243066] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
570 02:36:53.637805 <6>[ 0.255333] pinctrl core: initialized pinctrl subsystem
571 02:36:53.647498 <6>[ 0.266315] DMI not present or invalid.
572 02:36:53.655998 <6>[ 0.272206] NET: Registered PF_NETLINK/PF_ROUTE protocol family
573 02:36:53.665198 <6>[ 0.281203] DMA: preallocated 256 KiB pool for atomic coherent allocations
574 02:36:53.680619 <6>[ 0.292881] thermal_sys: Registered thermal governor 'step_wise'
575 02:36:53.681048 <6>[ 0.293076] cpuidle: using governor menu
576 02:36:53.707951 <6>[ 0.328425] No ATAGs?
577 02:36:53.714216 <6>[ 0.331166] hw-breakpoint: debug architecture 0x4 unsupported.
578 02:36:53.725384 <6>[ 0.343378] Serial: AMBA PL011 UART driver
579 02:36:53.755408 <6>[ 0.375740] iommu: Default domain type: Translated
580 02:36:53.765932 <6>[ 0.381085] iommu: DMA domain TLB invalidation policy: strict mode
581 02:36:53.790816 <5>[ 0.410506] SCSI subsystem initialized
582 02:36:53.796521 <6>[ 0.415439] usbcore: registered new interface driver usbfs
583 02:36:53.802395 <6>[ 0.421481] usbcore: registered new interface driver hub
584 02:36:53.809077 <6>[ 0.427263] usbcore: registered new device driver usb
585 02:36:53.814825 <6>[ 0.433824] pps_core: LinuxPPS API ver. 1 registered
586 02:36:53.826294 <6>[ 0.439212] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
587 02:36:53.833641 <6>[ 0.448940] PTP clock support registered
588 02:36:53.834050 <6>[ 0.453428] EDAC MC: Ver: 3.0.0
589 02:36:53.891777 <6>[ 0.509334] scmi_core: SCMI protocol bus registered
590 02:36:53.897296 <6>[ 0.517514] vgaarb: loaded
591 02:36:53.909789 <6>[ 0.530275] clocksource: Switched to clocksource dmtimer
592 02:36:53.948830 <6>[ 0.568959] NET: Registered PF_INET protocol family
593 02:36:53.961625 <6>[ 0.574675] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
594 02:36:53.967333 <6>[ 0.583678] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
595 02:36:53.978840 <6>[ 0.592610] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
596 02:36:53.984597 <6>[ 0.600875] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
597 02:36:53.996240 <6>[ 0.609146] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
598 02:36:54.002079 <6>[ 0.616870] TCP: Hash tables configured (established 4096 bind 4096)
599 02:36:54.007752 <6>[ 0.623791] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
600 02:36:54.013734 <6>[ 0.630830] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
601 02:36:54.021197 <6>[ 0.638417] NET: Registered PF_UNIX/PF_LOCAL protocol family
602 02:36:54.103169 <6>[ 0.717742] RPC: Registered named UNIX socket transport module.
603 02:36:54.103614 <6>[ 0.724195] RPC: Registered udp transport module.
604 02:36:54.108747 <6>[ 0.729304] RPC: Registered tcp transport module.
605 02:36:54.114406 <6>[ 0.734429] RPC: Registered tcp-with-tls transport module.
606 02:36:54.127538 <6>[ 0.740355] RPC: Registered tcp NFSv4.1 backchannel transport module.
607 02:36:54.127955 <6>[ 0.747265] PCI: CLS 0 bytes, default 64
608 02:36:54.133781 <5>[ 0.753121] Initialise system trusted keyrings
609 02:36:54.156802 <6>[ 0.774180] Trying to unpack rootfs image as initramfs...
610 02:36:54.227432 <6>[ 0.841638] workingset: timestamp_bits=30 max_order=17 bucket_order=0
611 02:36:54.232073 <6>[ 0.849161] squashfs: version 4.0 (2009/01/31) Phillip Lougher
612 02:36:54.271187 <5>[ 0.891557] NFS: Registering the id_resolver key type
613 02:36:54.277132 <5>[ 0.897148] Key type id_resolver registered
614 02:36:54.282877 <5>[ 0.901842] Key type id_legacy registered
615 02:36:54.290982 <6>[ 0.906283] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
616 02:36:54.298153 <6>[ 0.913498] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
617 02:36:54.380525 <5>[ 1.000962] Key type asymmetric registered
618 02:36:54.386443 <5>[ 1.005492] Asymmetric key parser 'x509' registered
619 02:36:54.398052 <6>[ 1.011047] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
620 02:36:54.398472 <6>[ 1.018935] io scheduler mq-deadline registered
621 02:36:54.403699 <6>[ 1.023915] io scheduler kyber registered
622 02:36:54.408291 <6>[ 1.028372] io scheduler bfq registered
623 02:36:54.504039 <6>[ 1.120957] ledtrig-cpu: registered to indicate activity on CPUs
624 02:36:54.804127 <6>[ 1.420802] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
625 02:36:54.825360 <6>[ 1.445562] msm_serial: driver initialized
626 02:36:54.831269 <6>[ 1.450564] SuperH (H)SCI(F) driver initialized
627 02:36:54.837258 <6>[ 1.455715] STMicroelectronics ASC driver initialized
628 02:36:54.841803 <6>[ 1.461407] STM32 USART driver initialized
629 02:36:54.979661 <6>[ 1.600466] brd: module loaded
630 02:36:55.021934 <6>[ 1.641719] loop: module loaded
631 02:36:55.058485 <6>[ 1.677995] CAN device driver interface
632 02:36:55.064774 <6>[ 1.683220] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
633 02:36:55.070637 <6>[ 1.690143] e1000e: Intel(R) PRO/1000 Network Driver
634 02:36:55.077380 <6>[ 1.695603] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
635 02:36:55.083120 <6>[ 1.702048] igb: Intel(R) Gigabit Ethernet Network Driver
636 02:36:55.090482 <6>[ 1.707871] igb: Copyright (c) 2007-2014 Intel Corporation.
637 02:36:55.102177 <6>[ 1.717039] pegasus: Pegasus/Pegasus II USB Ethernet driver
638 02:36:55.108044 <6>[ 1.723204] usbcore: registered new interface driver pegasus
639 02:36:55.113838 <6>[ 1.729330] usbcore: registered new interface driver asix
640 02:36:55.119555 <6>[ 1.735230] usbcore: registered new interface driver ax88179_178a
641 02:36:55.125304 <6>[ 1.741825] usbcore: registered new interface driver cdc_ether
642 02:36:55.131065 <6>[ 1.748124] usbcore: registered new interface driver smsc75xx
643 02:36:55.136890 <6>[ 1.754363] usbcore: registered new interface driver smsc95xx
644 02:36:55.142629 <6>[ 1.760598] usbcore: registered new interface driver net1080
645 02:36:55.148462 <6>[ 1.766719] usbcore: registered new interface driver cdc_subset
646 02:36:55.154305 <6>[ 1.773131] usbcore: registered new interface driver zaurus
647 02:36:55.162004 <6>[ 1.779174] usbcore: registered new interface driver cdc_ncm
648 02:36:55.171685 <6>[ 1.788565] usbcore: registered new interface driver usb-storage
649 02:36:55.179987 <6>[ 1.799637] i2c_dev: i2c /dev entries driver
650 02:36:55.205720 <5>[ 1.818143] cpuidle: enable-method property 'ti,am3352' found operations
651 02:36:55.211593 <6>[ 1.827829] sdhci: Secure Digital Host Controller Interface driver
652 02:36:55.219356 <6>[ 1.834604] sdhci: Copyright(c) Pierre Ossman
653 02:36:55.226543 <6>[ 1.841209] Synopsys Designware Multimedia Card Interface Driver
654 02:36:55.231763 <6>[ 1.849073] sdhci-pltfm: SDHCI platform and OF driver helper
655 02:36:55.245945 <6>[ 1.859014] usbcore: registered new interface driver usbhid
656 02:36:55.246526 <6>[ 1.865138] usbhid: USB HID core driver
657 02:36:55.259126 <6>[ 1.876813] NET: Registered PF_INET6 protocol family
658 02:36:55.702861 <6>[ 2.323459] Segment Routing with IPv6
659 02:36:55.708745 <6>[ 2.327610] In-situ OAM (IOAM) with IPv6
660 02:36:55.715457 <6>[ 2.332145] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
661 02:36:55.723421 <6>[ 2.339472] NET: Registered PF_PACKET protocol family
662 02:36:55.728740 <6>[ 2.345044] can: controller area network core
663 02:36:55.729088 <6>[ 2.349869] NET: Registered PF_CAN protocol family
664 02:36:55.734461 <6>[ 2.355096] can: raw protocol
665 02:36:55.740274 <6>[ 2.358423] can: broadcast manager protocol
666 02:36:55.747285 <6>[ 2.363034] can: netlink gateway - max_hops=1
667 02:36:55.747636 <5>[ 2.368541] Key type dns_resolver registered
668 02:36:55.752946 <6>[ 2.373616] ThumbEE CPU extension supported.
669 02:36:55.759239 <5>[ 2.378306] Registering SWP/SWPB emulation handler
670 02:36:55.766508 <3>[ 2.384013] omap_voltage_late_init: Voltage driver support not added
671 02:36:55.982859 <5>[ 2.600996] Loading compiled-in X.509 certificates
672 02:36:56.101905 <6>[ 2.709519] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
673 02:36:56.109051 <6>[ 2.726247] pinctrl-single 44e10800.pinmux: 142 pins, size 568
674 02:36:56.136179 <3>[ 2.750661] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
675 02:36:56.336333 <3>[ 2.950912] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
676 02:36:56.542508 <6>[ 3.161342] OMAP GPIO hardware version 0.1
677 02:36:56.562720 <6>[ 3.180619] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
678 02:36:56.655898 <4>[ 3.272490] at24 2-0054: supply vcc not found, using dummy regulator
679 02:36:56.688972 <4>[ 3.306587] at24 2-0055: supply vcc not found, using dummy regulator
680 02:36:56.726826 <4>[ 3.344390] at24 2-0056: supply vcc not found, using dummy regulator
681 02:36:56.776004 <4>[ 3.393622] at24 2-0057: supply vcc not found, using dummy regulator
682 02:36:56.815673 <6>[ 3.434023] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
683 02:36:56.873520 <3>[ 3.487013] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
684 02:36:56.898528 <6>[ 3.508326] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
685 02:36:56.920376 <4>[ 3.535597] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
686 02:36:56.935380 <4>[ 3.551255] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
687 02:36:57.023927 <6>[ 3.640708] omap_rng 48310000.rng: Random Number Generator ver. 20
688 02:36:57.048021 <5>[ 3.667635] random: crng init done
689 02:36:57.076058 <6>[ 3.695139] Freeing initrd memory: 14992K
690 02:36:57.094930 <6>[ 3.710297] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
691 02:36:57.148313 <6>[ 3.762736] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
692 02:36:57.154103 <6>[ 3.773101] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
693 02:36:57.165866 <6>[ 3.780446] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
694 02:36:57.171673 <6>[ 3.787918] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
695 02:36:57.183198 <6>[ 3.796060] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
696 02:36:57.190635 <6>[ 3.807699] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
697 02:36:57.203800 <5>[ 3.816795] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
698 02:36:57.232272 <3>[ 3.847316] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
699 02:36:57.238080 <6>[ 3.855917] edma 49000000.dma: TI EDMA DMA engine driver
700 02:36:57.311527 <3>[ 3.925852] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
701 02:36:57.326603 <6>[ 3.940590] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
702 02:36:57.339705 <3>[ 3.957861] l3-aon-clkctrl:0000:0: failed to disable
703 02:36:57.394311 <6>[ 4.009046] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
704 02:36:57.399856 <6>[ 4.018573] printk: legacy console [ttyS0] enabled
705 02:36:57.405542 <6>[ 4.018573] printk: legacy console [ttyS0] enabled
706 02:36:57.411274 <6>[ 4.028912] printk: legacy bootconsole [omap8250] disabled
707 02:36:57.417090 <6>[ 4.028912] printk: legacy bootconsole [omap8250] disabled
708 02:36:57.447399 <4>[ 4.061105] tps65217-pmic: Failed to locate of_node [id: -1]
709 02:36:57.450932 <4>[ 4.068531] tps65217-bl: Failed to locate of_node [id: -1]
710 02:36:57.467997 <6>[ 4.088817] tps65217 0-0024: TPS65217 ID 0xe version 1.2
711 02:36:57.488304 <6>[ 4.095822] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
712 02:36:57.500062 <6>[ 4.109526] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
713 02:36:57.502855 <6>[ 4.121489] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
714 02:36:57.526566 <6>[ 4.141827] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
715 02:36:57.532495 <6>[ 4.151001] sdhci-omap 48060000.mmc: Got CD GPIO
716 02:36:57.540525 <4>[ 4.156151] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
717 02:36:57.555419 <4>[ 4.169988] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
718 02:36:57.561924 <4>[ 4.178697] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
719 02:36:57.571754 <4>[ 4.187424] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
720 02:36:57.696254 <6>[ 4.312560] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
721 02:36:57.742732 <6>[ 4.356774] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
722 02:36:57.749353 <6>[ 4.366152] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
723 02:36:57.758494 <6>[ 4.375191] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
724 02:36:57.820714 <6>[ 4.438489] mmc1: new high speed MMC card at address 0001
725 02:36:57.828543 <6>[ 4.447280] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
726 02:36:57.848805 <6>[ 4.461979] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
727 02:36:57.855730 <6>[ 4.475020] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
728 02:36:57.870719 <6>[ 4.490330] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
729 02:36:57.878407 <6>[ 4.496766] mmc0: new high speed SDHC card at address aaaa
730 02:36:57.884747 <6>[ 4.504583] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
731 02:36:57.895408 <6>[ 4.512438] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
732 02:36:57.916277 <6>[ 4.535034] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
733 02:36:59.976697 <6>[ 6.591395] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
734 02:37:00.100088 <5>[ 6.620303] Sending DHCP requests ., OK
735 02:37:00.111312 <6>[ 6.724734] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
736 02:37:00.111654 <6>[ 6.732816] IP-Config: Complete:
737 02:37:00.122632 <6>[ 6.736354] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
738 02:37:00.128295 <6>[ 6.746797] host=192.168.6.8, domain=, nis-domain=(none)
739 02:37:00.133927 <6>[ 6.752963] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
740 02:37:00.140564 <6>[ 6.753000] nameserver0=10.255.253.1
741 02:37:00.146794 <6>[ 6.765618] clk: Disabling unused clocks
742 02:37:00.152321 <6>[ 6.770361] PM: genpd: Disabling unused power domains
743 02:37:00.170324 <6>[ 6.787558] Freeing unused kernel image (initmem) memory: 2048K
744 02:37:00.177876 <6>[ 6.797401] Run /init as init process
745 02:37:00.203991 Loading, please wait...
746 02:37:00.282140 Starting systemd-udevd version 252.22-1~deb12u1
747 02:37:03.360126 <4>[ 9.973446] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 02:37:03.458461 <4>[ 10.071846] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 02:37:03.622962 <6>[ 10.243854] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
750 02:37:03.633768 <6>[ 10.249532] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
751 02:37:03.865506 <6>[ 10.484725] hub 1-0:1.0: USB hub found
752 02:37:03.961315 <6>[ 10.580556] hub 1-0:1.0: 1 port detected
753 02:37:04.264656 <6>[ 10.883547] tda998x 0-0070: found TDA19988
754 02:37:07.285298 Begin: Loading essential drivers ... done.
755 02:37:07.290536 Begin: Running /scripts/init-premount ... done.
756 02:37:07.296038 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
757 02:37:07.309969 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
758 02:37:07.310426 Device /sys/class/net/eth0 found
759 02:37:07.310827 done.
760 02:37:07.392524 Begin: Waiting up to 180 secs for any network device to become available ... done.
761 02:37:07.462536 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
762 02:37:07.631624 IP-Config: eth0 guessed broadcast address 192.168.6.255
763 02:37:07.636943 IP-Config: eth0 complete (dhcp from 192.168.6.1):
764 02:37:07.642735 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
765 02:37:07.654094 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
766 02:37:07.654626 rootserver: 192.168.6.1 rootpath:
767 02:37:07.656689 filename :
768 02:37:07.729307 done.
769 02:37:07.738557 Begin: Running /scripts/nfs-bottom ... done.
770 02:37:07.813951 Begin: Running /scripts/init-bottom ... done.
771 02:37:09.351243 <30>[ 15.967876] systemd[1]: System time before build time, advancing clock.
772 02:37:09.563315 <30>[ 16.153820] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
773 02:37:09.572580 <30>[ 16.190999] systemd[1]: Detected architecture arm.
774 02:37:09.587283
775 02:37:09.587691 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
776 02:37:09.587942
777 02:37:09.613783 <30>[ 16.231013] systemd[1]: Hostname set to <debian-bookworm-armhf>.
778 02:37:11.891120 <30>[ 18.508021] systemd[1]: Queued start job for default target graphical.target.
779 02:37:11.909263 <30>[ 18.523262] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
780 02:37:11.916788 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
781 02:37:11.938891 <30>[ 18.553139] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
782 02:37:11.947190 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
783 02:37:11.969446 <30>[ 18.583720] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
784 02:37:11.977750 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
785 02:37:11.997714 <30>[ 18.612291] systemd[1]: Created slice user.slice - User and Session Slice.
786 02:37:12.004428 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
787 02:37:12.032985 <30>[ 18.641709] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
788 02:37:12.039027 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
789 02:37:12.056856 <30>[ 18.671464] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
790 02:37:12.064818 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
791 02:37:12.097713 <30>[ 18.701230] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
792 02:37:12.104100 <30>[ 18.721837] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
793 02:37:12.111712 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
794 02:37:12.136017 <30>[ 18.750831] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
795 02:37:12.144305 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
796 02:37:12.166712 <30>[ 18.781135] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
797 02:37:12.175144 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
798 02:37:12.196569 <30>[ 18.811338] systemd[1]: Reached target paths.target - Path Units.
799 02:37:12.201734 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
800 02:37:12.226301 <30>[ 18.840995] systemd[1]: Reached target remote-fs.target - Remote File Systems.
801 02:37:12.233722 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
802 02:37:12.256067 <30>[ 18.870857] systemd[1]: Reached target slices.target - Slice Units.
803 02:37:12.261623 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
804 02:37:12.286219 <30>[ 18.901036] systemd[1]: Reached target swap.target - Swaps.
805 02:37:12.290312 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
806 02:37:12.316576 <30>[ 18.931016] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
807 02:37:12.324393 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
808 02:37:12.347590 <30>[ 18.961914] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
809 02:37:12.355973 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
810 02:37:12.447299 <30>[ 19.056969] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
811 02:37:12.460321 <30>[ 19.074740] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
812 02:37:12.468733 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
813 02:37:12.498979 <30>[ 19.114832] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
814 02:37:12.511585 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
815 02:37:12.540168 <30>[ 19.153359] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
816 02:37:12.547339 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
817 02:37:12.583319 <30>[ 19.198446] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
818 02:37:12.596872 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
819 02:37:12.618090 <30>[ 19.232288] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
820 02:37:12.625738 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
821 02:37:12.653623 <30>[ 19.262075] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
822 02:37:12.670261 <30>[ 19.278771] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
823 02:37:12.720726 <30>[ 19.336205] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
824 02:37:12.746497 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
825 02:37:12.795871 <30>[ 19.411103] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
826 02:37:12.825200 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
827 02:37:12.907672 <30>[ 19.521591] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
828 02:37:12.942086 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
829 02:37:12.996835 <30>[ 19.611726] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
830 02:37:13.026889 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
831 02:37:13.076197 <30>[ 19.692251] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
832 02:37:13.095300 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
833 02:37:13.118774 <30>[ 19.734501] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
834 02:37:13.142971 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
835 02:37:13.197017 <30>[ 19.811627] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
836 02:37:13.216104 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
837 02:37:13.275848 <30>[ 19.891479] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
838 02:37:13.304819 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
839 02:37:13.358996 <30>[ 19.974696] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
840 02:37:13.375169 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
841 02:37:13.405576 <28>[ 20.012608] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
842 02:37:13.414162 <28>[ 20.028777] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
843 02:37:13.456461 <30>[ 20.071421] systemd[1]: Starting systemd-journald.service - Journal Service...
844 02:37:13.463028 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
845 02:37:13.536402 <30>[ 20.151745] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
846 02:37:13.555398 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
847 02:37:13.581727 <30>[ 20.197395] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
848 02:37:13.623948 Starting [0;1;39msystemd-network-g… units from Kernel command line...
849 02:37:13.669567 <30>[ 20.283614] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
850 02:37:13.719942 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
851 02:37:13.767975 <30>[ 20.382833] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
852 02:37:13.825401 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
853 02:37:13.900192 <30>[ 20.515749] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
854 02:37:13.967121 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
855 02:37:13.993855 <30>[ 20.609302] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
856 02:37:14.055862 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
857 02:37:14.082611 <30>[ 20.697115] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
858 02:37:14.107821 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
859 02:37:14.234750 <30>[ 20.851908] systemd[1]: modprobe@configfs.service: Deactivated successfully.
860 02:37:14.266695 <30>[ 20.881089] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
861 02:37:14.274652 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
862 02:37:14.306814 <30>[ 20.923108] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
863 02:37:14.336743 <30>[ 20.952157] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
864 02:37:14.366176 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
865 02:37:14.386490 <30>[ 21.003184] systemd[1]: modprobe@drm.service: Deactivated successfully.
866 02:37:14.426143 <30>[ 21.040897] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
867 02:37:14.433733 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
868 02:37:14.457178 <30>[ 21.072072] systemd[1]: Started systemd-journald.service - Journal Service.
869 02:37:14.464007 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
870 02:37:14.498642 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
871 02:37:14.526931 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
872 02:37:14.557513 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
873 02:37:14.578967 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
874 02:37:14.608514 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
875 02:37:14.628524 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
876 02:37:14.656148 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
877 02:37:14.715865 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
878 02:37:14.786209 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
879 02:37:14.845989 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
880 02:37:14.935186 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
881 02:37:15.018892 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
882 02:37:15.111269 <46>[ 21.726738] systemd-journald[164]: Received client request to flush runtime journal.
883 02:37:15.185583 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
884 02:37:15.246531 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
885 02:37:16.126676 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
886 02:37:16.437055 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
887 02:37:16.518525 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
888 02:37:16.819192 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
889 02:37:17.048430 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
890 02:37:17.068120 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
891 02:37:17.085756 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
892 02:37:17.164029 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
893 02:37:17.196593 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
894 02:37:18.137032 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
895 02:37:18.206021 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
896 02:37:18.556236 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
897 02:37:18.649035 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
898 02:37:18.694628 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
899 02:37:19.837216 <5>[ 26.452940] cfg80211: Loading compiled-in X.509 certificates for regulatory database
900 02:37:20.070681 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
901 02:37:21.397932 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
902 02:37:21.595361 <5>[ 28.213285] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
903 02:37:21.665263 <5>[ 28.281564] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
904 02:37:21.676669 <4>[ 28.292226] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
905 02:37:21.682564 <6>[ 28.301344] cfg80211: failed to load regulatory.db
906 02:37:22.278816 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
907 02:37:22.799122 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
908 02:37:22.841692 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
909 02:37:22.948468 <46>[ 29.554156] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
910 02:37:23.146155 <46>[ 29.754886] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
911 02:37:32.874935 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
912 02:37:32.900892 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
913 02:37:32.928103 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
914 02:37:32.947270 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
915 02:37:33.021027 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
916 02:37:33.067647 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
917 02:37:33.106209 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
918 02:37:33.151936 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
919 02:37:33.238138 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
920 02:37:33.267186 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
921 02:37:33.307337 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
922 02:37:33.329549 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
923 02:37:33.372980 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
924 02:37:33.403612 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
925 02:37:33.437177 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
926 02:37:33.457899 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
927 02:37:33.486958 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
928 02:37:33.520890 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
929 02:37:33.547120 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
930 02:37:33.566407 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
931 02:37:33.602908 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
932 02:37:33.627847 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
933 02:37:33.658881 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
934 02:37:33.726290 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
935 02:37:33.771118 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
936 02:37:33.900879 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
937 02:37:33.986177 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
938 02:37:34.032134 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
939 02:37:34.083759 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
940 02:37:34.099398 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
941 02:37:34.299389 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
942 02:37:34.366235 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
943 02:37:34.428375 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
944 02:37:34.444378 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
945 02:37:34.466087 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
946 02:37:34.836379 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
947 02:37:35.191104 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
948 02:37:35.248837 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
949 02:37:35.296849 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
950 02:37:35.377441 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
951 02:37:35.568343 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
952 02:37:35.704827
953 02:37:35.707668 Debian GNU/Linux 12 deworm-armhf login: root (automatic login)
954 02:37:35.708191
955 02:37:36.048664 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Sat Nov 9 01:35:35 UTC 2024 armv7l
956 02:37:36.049296
957 02:37:36.054242 The programs included with the Debian GNU/Linux system are free software;
958 02:37:36.057502 the exact distribution terms for each program are described in the
959 02:37:36.063100 individual files in /usr/share/doc/*/copyright.
960 02:37:36.063629
961 02:37:36.068667 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
962 02:37:36.072818 permitted by applicable law.
963 02:37:41.172452 Unable to match end of the kernel message
965 02:37:41.174222 Setting prompt string to ['/ #']
966 02:37:41.174834 end: 2.4.4.1 login-action (duration 00:00:48) [common]
968 02:37:41.176335 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
969 02:37:41.176916 start: 2.4.5 expect-shell-connection (timeout 00:03:09) [common]
970 02:37:41.177393 Setting prompt string to ['/ #']
971 02:37:41.177865 Forcing a shell prompt, looking for ['/ #']
973 02:37:41.228897 / #
974 02:37:41.229935 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
975 02:37:41.230495 Waiting using forced prompt support (timeout 00:02:30)
976 02:37:41.234596
977 02:37:41.241223 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
978 02:37:41.241926 start: 2.4.6 export-device-env (timeout 00:03:09) [common]
979 02:37:41.242483 Sending with 10 millisecond of delay
981 02:37:46.237831 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/964144/extract-nfsrootfs-x0_hsi2i'
982 02:37:46.248719 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/964144/extract-nfsrootfs-x0_hsi2i'
983 02:37:46.250637 Sending with 10 millisecond of delay
985 02:37:48.350261 / # export NFS_SERVER_IP='192.168.6.3'
986 02:37:48.361418 export NFS_SERVER_IP='192.168.6.3'
987 02:37:48.362970 end: 2.4.6 export-device-env (duration 00:00:07) [common]
988 02:37:48.363807 end: 2.4 uboot-commands (duration 00:01:58) [common]
989 02:37:48.364639 end: 2 uboot-action (duration 00:01:58) [common]
990 02:37:48.365441 start: 3 lava-test-retry (timeout 00:06:51) [common]
991 02:37:48.366297 start: 3.1 lava-test-shell (timeout 00:06:51) [common]
992 02:37:48.366955 Using namespace: common
994 02:37:48.468049 / # #
995 02:37:48.468999 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
996 02:37:48.473656 #
997 02:37:48.480448 Using /lava-964144
999 02:37:48.581742 / # export SHELL=/bin/bash
1000 02:37:48.587259 export SHELL=/bin/bash
1002 02:37:48.694353 / # . /lava-964144/environment
1003 02:37:48.699871 . /lava-964144/environment
1005 02:37:48.813383 / # /lava-964144/bin/lava-test-runner /lava-964144/0
1006 02:37:48.814313 Test shell timeout: 10s (minimum of the action and connection timeout)
1007 02:37:48.819101 /lava-964144/bin/lava-test-runner /lava-964144/0
1008 02:37:49.222117 + export TESTRUN_ID=0_timesync-off
1009 02:37:49.229994 + TESTRUN_ID=0_timesync-off
1010 02:37:49.230445 + cd /lava-964144/0/tests/0_timesync-off
1011 02:37:49.230862 ++ cat uuid
1012 02:37:49.246741 + UUID=964144_1.6.2.4.1
1013 02:37:49.247183 + set +x
1014 02:37:49.255386 <LAVA_SIGNAL_STARTRUN 0_timesync-off 964144_1.6.2.4.1>
1015 02:37:49.255833 + systemctl stop systemd-timesyncd
1016 02:37:49.256516 Received signal: <STARTRUN> 0_timesync-off 964144_1.6.2.4.1
1017 02:37:49.256946 Starting test lava.0_timesync-off (964144_1.6.2.4.1)
1018 02:37:49.257472 Skipping test definition patterns.
1019 02:37:49.550184 + set +x
1020 02:37:49.550792 <LAVA_SIGNAL_ENDRUN 0_timesync-off 964144_1.6.2.4.1>
1021 02:37:49.551475 Received signal: <ENDRUN> 0_timesync-off 964144_1.6.2.4.1
1022 02:37:49.551971 Ending use of test pattern.
1023 02:37:49.552378 Ending test lava.0_timesync-off (964144_1.6.2.4.1), duration 0.30
1025 02:37:49.725640 + export TESTRUN_ID=1_kselftest-dt
1026 02:37:49.733494 + TESTRUN_ID=1_kselftest-dt
1027 02:37:49.733958 + cd /lava-964144/0/tests/1_kselftest-dt
1028 02:37:49.734370 ++ cat uuid
1029 02:37:49.750391 + UUID=964144_1.6.2.4.5
1030 02:37:49.750855 + set +x
1031 02:37:49.756105 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 964144_1.6.2.4.5>
1032 02:37:49.756542 + cd ./automated/linux/kselftest/
1033 02:37:49.757193 Received signal: <STARTRUN> 1_kselftest-dt 964144_1.6.2.4.5
1034 02:37:49.757609 Starting test lava.1_kselftest-dt (964144_1.6.2.4.5)
1035 02:37:49.758127 Skipping test definition patterns.
1036 02:37:49.784422 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc6-272-gda4373fbcf006/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1037 02:37:49.887201 INFO: install_deps skipped
1038 02:37:50.509884 --2024-11-09 02:37:50-- http://storage.kernelci.org/mainline/master/v6.12-rc6-272-gda4373fbcf006/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1039 02:37:50.535649 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1040 02:37:50.680736 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1041 02:37:50.824210 HTTP request sent, awaiting response... 200 OK
1042 02:37:50.824750 Length: 2541812 (2.4M) [application/octet-stream]
1043 02:37:50.829787 Saving to: 'kselftest_armhf.tar.gz'
1044 02:37:50.830353
1045 02:37:52.655842
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 2%[ ] 49.92K 175KB/s
kselftest_armhf.tar 7%[> ] 194.76K 338KB/s
kselftest_armhf.tar 26%[====> ] 648.98K 714KB/s
kselftest_armhf.tar 45%[========> ] 1.09M 982KB/s
kselftest_armhf.tar 62%[===========> ] 1.53M 1.14MB/s
kselftest_armhf.tar 78%[==============> ] 1.91M 1.22MB/s
kselftest_armhf.tar 95%[==================> ] 2.31M 1.30MB/s
kselftest_armhf.tar 100%[===================>] 2.42M 1.33MB/s in 1.8s
1046 02:37:52.656321
1047 02:37:53.112154 2024-11-09 02:37:52 (1.33 MB/s) - 'kselftest_armhf.tar.gz' saved [2541812/2541812]
1048 02:37:53.112554
1049 02:38:06.024308 skiplist:
1050 02:38:06.024734 ========================================
1051 02:38:06.029116 ========================================
1052 02:38:06.140309 dt:test_unprobed_devices.sh
1053 02:38:06.181789 ============== Tests to run ===============
1054 02:38:06.189131 dt:test_unprobed_devices.sh
1055 02:38:06.193094 ===========End Tests to run ===============
1056 02:38:06.202113 shardfile-dt pass
1057 02:38:06.443556 <12>[ 73.063999] kselftest: Running tests in dt
1058 02:38:06.474574 TAP version 13
1059 02:38:06.497957 1..1
1060 02:38:06.555174 # timeout set to 45
1061 02:38:06.555834 # selftests: dt: test_unprobed_devices.sh
1062 02:38:07.395178 # TAP version 13
1063 02:38:32.956459 # 1..257
1064 02:38:33.132542 # ok 1 / # SKIP
1065 02:38:33.153621 # ok 2 /clk_mcasp0
1066 02:38:33.232548 # ok 3 /clk_mcasp0_fixed # SKIP
1067 02:38:33.304488 # ok 4 /cpus/cpu@0 # SKIP
1068 02:38:33.374713 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1069 02:38:33.396147 # ok 6 /fixedregulator0
1070 02:38:33.417733 # ok 7 /leds
1071 02:38:33.443460 # ok 8 /ocp
1072 02:38:33.462783 # ok 9 /ocp/interconnect@44c00000
1073 02:38:33.487852 # ok 10 /ocp/interconnect@44c00000/segment@0
1074 02:38:33.514968 # ok 11 /ocp/interconnect@44c00000/segment@100000
1075 02:38:33.540744 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1076 02:38:33.608546 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1077 02:38:33.630250 # ok 14 /ocp/interconnect@44c00000/segment@200000
1078 02:38:33.659369 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1079 02:38:33.767867 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1080 02:38:33.842621 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1081 02:38:33.913847 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1082 02:38:33.986647 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1083 02:38:34.061446 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1084 02:38:34.134213 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1085 02:38:34.213354 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1086 02:38:34.287533 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1087 02:38:34.359015 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1088 02:38:34.433439 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1089 02:38:34.510732 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1090 02:38:34.583446 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1091 02:38:34.654556 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1092 02:38:34.728436 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1093 02:38:34.801249 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1094 02:38:34.876092 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1095 02:38:34.949088 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1096 02:38:35.025179 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1097 02:38:35.095898 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1098 02:38:35.170375 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1099 02:38:35.248490 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1100 02:38:35.323835 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1101 02:38:35.396632 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1102 02:38:35.471866 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1103 02:38:35.547951 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1104 02:38:35.622890 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1105 02:38:35.699370 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1106 02:38:35.783284 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1107 02:38:35.858459 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1108 02:38:35.936978 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1109 02:38:36.026300 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1110 02:38:36.091218 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1111 02:38:36.165525 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1112 02:38:36.240082 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1113 02:38:36.314328 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1114 02:38:36.387712 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1115 02:38:36.462305 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1116 02:38:36.540990 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1117 02:38:36.615173 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1118 02:38:36.689173 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1119 02:38:36.760786 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1120 02:38:36.835790 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1121 02:38:36.908138 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1122 02:38:36.983259 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1123 02:38:37.064128 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1124 02:38:37.138613 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1125 02:38:37.209554 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1126 02:38:37.284293 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1127 02:38:37.356939 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1128 02:38:37.430749 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1129 02:38:37.506048 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1130 02:38:37.580371 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1131 02:38:37.655198 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1132 02:38:37.732594 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1133 02:38:37.804565 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1134 02:38:37.880432 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1135 02:38:37.959710 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1136 02:38:38.030151 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1137 02:38:38.111211 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1138 02:38:38.179874 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1139 02:38:38.255365 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1140 02:38:38.329289 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1141 02:38:38.403164 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1142 02:38:38.478725 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1143 02:38:38.553021 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1144 02:38:38.628452 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1145 02:38:38.702184 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1146 02:38:38.774714 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1147 02:38:38.850251 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1148 02:38:38.927119 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1149 02:38:39.004564 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1150 02:38:39.074877 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1151 02:38:39.153211 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1152 02:38:39.231344 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1153 02:38:39.305408 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1154 02:38:39.375730 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1155 02:38:39.460061 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1156 02:38:39.534532 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1157 02:38:39.614020 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1158 02:38:39.631926 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1159 02:38:39.656550 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1160 02:38:39.680850 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1161 02:38:39.709602 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1162 02:38:39.730951 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1163 02:38:39.755088 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1164 02:38:39.779390 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1165 02:38:39.803130 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1166 02:38:39.911892 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1167 02:38:39.937561 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1168 02:38:39.962925 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1169 02:38:39.987065 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1170 02:38:40.097135 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1171 02:38:40.174331 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1172 02:38:40.248616 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1173 02:38:40.323868 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1174 02:38:40.399064 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1175 02:38:40.473395 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1176 02:38:40.549362 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1177 02:38:40.623374 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1178 02:38:40.699429 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1179 02:38:40.773832 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1180 02:38:40.848580 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1181 02:38:40.922540 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1182 02:38:40.998628 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1183 02:38:41.075505 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1184 02:38:41.151204 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1185 02:38:41.225201 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1186 02:38:41.251911 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1187 02:38:41.320975 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1188 02:38:41.392414 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1189 02:38:41.468124 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1190 02:38:41.496711 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1191 02:38:41.565774 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1192 02:38:41.590843 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1193 02:38:41.664161 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1194 02:38:41.686780 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1195 02:38:41.712175 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1196 02:38:41.734806 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1197 02:38:41.760833 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1198 02:38:41.783332 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1199 02:38:41.808750 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1200 02:38:41.835722 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1201 02:38:41.911619 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1202 02:38:41.933348 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1203 02:38:41.957481 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1204 02:38:42.031803 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1205 02:38:42.109759 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1206 02:38:42.130717 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1207 02:38:42.230310 # not ok 144 /ocp/interconnect@47c00000
1208 02:38:42.302646 # not ok 145 /ocp/interconnect@47c00000/segment@0
1209 02:38:42.324823 # ok 146 /ocp/interconnect@48000000
1210 02:38:42.353910 # ok 147 /ocp/interconnect@48000000/segment@0
1211 02:38:42.379366 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1212 02:38:42.400737 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1213 02:38:42.421652 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1214 02:38:42.450054 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1215 02:38:42.470494 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1216 02:38:42.498512 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1217 02:38:42.520504 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1218 02:38:42.590292 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1219 02:38:42.664286 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1220 02:38:42.687317 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1221 02:38:42.712030 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1222 02:38:42.739207 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1223 02:38:42.761157 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1224 02:38:42.781867 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1225 02:38:42.806923 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1226 02:38:42.829963 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1227 02:38:42.854655 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1228 02:38:42.880551 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1229 02:38:42.901240 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1230 02:38:42.929321 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1231 02:38:42.951189 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1232 02:38:42.977534 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1233 02:38:43.000926 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1234 02:38:43.023852 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1235 02:38:43.046465 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1236 02:38:43.069030 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1237 02:38:43.094722 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1238 02:38:43.119232 # ok 175 /ocp/interconnect@48000000/segment@100000
1239 02:38:43.144690 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1240 02:38:43.166244 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1241 02:38:43.241235 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1242 02:38:43.321253 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1243 02:38:43.393127 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1244 02:38:43.470146 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1245 02:38:43.537571 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1246 02:38:43.612854 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1247 02:38:43.685852 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1248 02:38:43.760370 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1249 02:38:43.781622 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1250 02:38:43.805607 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1251 02:38:43.830710 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1252 02:38:43.857268 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1253 02:38:43.880018 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1254 02:38:43.906396 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1255 02:38:43.930613 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1256 02:38:43.952267 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1257 02:38:43.975839 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1258 02:38:43.999854 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1259 02:38:44.023381 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1260 02:38:44.047566 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1261 02:38:44.068825 # ok 198 /ocp/interconnect@48000000/segment@200000
1262 02:38:44.094069 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1263 02:38:44.170877 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1264 02:38:44.194927 # ok 201 /ocp/interconnect@48000000/segment@300000
1265 02:38:44.219456 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1266 02:38:44.239529 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1267 02:38:44.268752 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1268 02:38:44.290363 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1269 02:38:44.315408 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1270 02:38:44.339914 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1271 02:38:44.413070 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1272 02:38:44.429396 # ok 209 /ocp/interconnect@4a000000
1273 02:38:44.454305 # ok 210 /ocp/interconnect@4a000000/segment@0
1274 02:38:44.484704 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1275 02:38:44.505311 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1276 02:38:44.531342 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1277 02:38:44.554316 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1278 02:38:44.630649 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1279 02:38:44.741620 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1280 02:38:44.813335 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1281 02:38:44.919273 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1282 02:38:44.993411 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1283 02:38:45.067359 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1284 02:38:45.170169 # not ok 221 /ocp/interconnect@4b140000
1285 02:38:45.244161 # not ok 222 /ocp/interconnect@4b140000/segment@0
1286 02:38:45.317571 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1287 02:38:45.343601 # ok 224 /ocp/target-module@40300000
1288 02:38:45.367528 # ok 225 /ocp/target-module@40300000/sram@0
1289 02:38:45.438114 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1290 02:38:45.518532 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1291 02:38:45.537900 # ok 228 /ocp/target-module@47400000
1292 02:38:45.564161 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1293 02:38:45.586823 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1294 02:38:45.608119 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1295 02:38:45.629345 # ok 232 /ocp/target-module@47400000/usb@1400
1296 02:38:45.652174 # ok 233 /ocp/target-module@47400000/usb@1800
1297 02:38:45.673230 # ok 234 /ocp/target-module@47810000
1298 02:38:45.698009 # ok 235 /ocp/target-module@49000000
1299 02:38:45.725626 # ok 236 /ocp/target-module@49000000/dma@0
1300 02:38:45.748068 # ok 237 /ocp/target-module@49800000
1301 02:38:45.774020 # ok 238 /ocp/target-module@49800000/dma@0
1302 02:38:45.791967 # ok 239 /ocp/target-module@49900000
1303 02:38:45.818389 # ok 240 /ocp/target-module@49900000/dma@0
1304 02:38:45.842474 # ok 241 /ocp/target-module@49a00000
1305 02:38:45.866221 # ok 242 /ocp/target-module@49a00000/dma@0
1306 02:38:45.884310 # ok 243 /ocp/target-module@4c000000
1307 02:38:45.963759 # not ok 244 /ocp/target-module@4c000000/emif@0
1308 02:38:45.984980 # ok 245 /ocp/target-module@50000000
1309 02:38:46.007953 # ok 246 /ocp/target-module@53100000
1310 02:38:46.078709 # not ok 247 /ocp/target-module@53100000/sham@0
1311 02:38:46.104632 # ok 248 /ocp/target-module@53500000
1312 02:38:46.178738 # not ok 249 /ocp/target-module@53500000/aes@0
1313 02:38:46.195883 # ok 250 /ocp/target-module@56000000
1314 02:38:46.308939 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1315 02:38:46.376973 # ok 252 /opp-table # SKIP
1316 02:38:46.448024 # ok 253 /soc # SKIP
1317 02:38:46.473524 # ok 254 /sound
1318 02:38:46.492523 # ok 255 /target-module@4b000000
1319 02:38:46.518409 # ok 256 /target-module@4b000000/target-module@140000
1320 02:38:46.540503 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1321 02:38:46.548797 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1322 02:38:46.557157 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1323 02:38:48.773769 dt_test_unprobed_devices_sh_ skip
1324 02:38:48.779244 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1325 02:38:48.784907 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1326 02:38:48.785235 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1327 02:38:48.793760 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1328 02:38:48.794134 dt_test_unprobed_devices_sh_fixedregulator0 pass
1329 02:38:48.799411 dt_test_unprobed_devices_sh_leds pass
1330 02:38:48.804951 dt_test_unprobed_devices_sh_ocp pass
1331 02:38:48.808600 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1332 02:38:48.814139 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1333 02:38:48.819779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1334 02:38:48.830922 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1335 02:38:48.836421 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1336 02:38:48.842049 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1337 02:38:48.853249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1338 02:38:48.859090 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1339 02:38:48.870145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1340 02:38:48.881488 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1341 02:38:48.887013 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1342 02:38:48.898243 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1343 02:38:48.909460 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1344 02:38:48.920667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1345 02:38:48.931868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1346 02:38:48.937512 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1347 02:38:48.948555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1348 02:38:48.959778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1349 02:38:48.970947 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1350 02:38:48.982172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1351 02:38:48.987886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1352 02:38:48.998998 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1353 02:38:49.010237 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1354 02:38:49.021535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1355 02:38:49.027098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1356 02:38:49.038271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1357 02:38:49.049500 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1358 02:38:49.060595 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1359 02:38:49.066205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1360 02:38:49.077313 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1361 02:38:49.088578 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1362 02:38:49.099789 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1363 02:38:49.111018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1364 02:38:49.122180 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1365 02:38:49.133456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1366 02:38:49.144612 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1367 02:38:49.155776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1368 02:38:49.166969 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1369 02:38:49.178160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1370 02:38:49.189487 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1371 02:38:49.200540 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1372 02:38:49.211711 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1373 02:38:49.222921 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1374 02:38:49.234150 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1375 02:38:49.245323 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1376 02:38:49.256505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1377 02:38:49.267757 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1378 02:38:49.278871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1379 02:38:49.290129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1380 02:38:49.301387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1381 02:38:49.312659 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1382 02:38:49.323688 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1383 02:38:49.334900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1384 02:38:49.346126 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1385 02:38:49.351724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1386 02:38:49.363044 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1387 02:38:49.374114 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1388 02:38:49.385438 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1389 02:38:49.396480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1390 02:38:49.407706 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1391 02:38:49.418872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1392 02:38:49.430125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1393 02:38:49.441267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1394 02:38:49.452493 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1395 02:38:49.463687 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1396 02:38:49.474886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1397 02:38:49.486268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1398 02:38:49.497314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1399 02:38:49.508572 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1400 02:38:49.519664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1401 02:38:49.530830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1402 02:38:49.541996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1403 02:38:49.547626 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1404 02:38:49.558888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1405 02:38:49.570119 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1406 02:38:49.581278 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1407 02:38:49.592511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1408 02:38:49.604143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1409 02:38:49.609264 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1410 02:38:49.620478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1411 02:38:49.631669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1412 02:38:49.642782 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1413 02:38:49.654010 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1414 02:38:49.665137 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1415 02:38:49.676428 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1416 02:38:49.693145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1417 02:38:49.698787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1418 02:38:49.709903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1419 02:38:49.721098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1420 02:38:49.726715 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1421 02:38:49.737862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1422 02:38:49.749087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1423 02:38:49.754727 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1424 02:38:49.765871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1425 02:38:49.771442 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1426 02:38:49.782654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1427 02:38:49.793849 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1428 02:38:49.805173 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1429 02:38:49.810602 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1430 02:38:49.821790 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1431 02:38:49.838613 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1432 02:38:49.849892 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1433 02:38:49.861054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1434 02:38:49.872215 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1435 02:38:49.883455 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1436 02:38:49.894643 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1437 02:38:49.905767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1438 02:38:49.917000 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1439 02:38:49.933839 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1440 02:38:49.944989 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1441 02:38:49.956187 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1442 02:38:49.967474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1443 02:38:49.984254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1444 02:38:49.995419 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1445 02:38:50.006641 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1446 02:38:50.017762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1447 02:38:50.023463 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1448 02:38:50.034602 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1449 02:38:50.040220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1450 02:38:50.051429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1451 02:38:50.057036 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1452 02:38:50.068220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1453 02:38:50.073747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1454 02:38:50.085036 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1455 02:38:50.090634 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1456 02:38:50.101732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1457 02:38:50.112952 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1458 02:38:50.118573 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1459 02:38:50.129773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1460 02:38:50.141113 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1461 02:38:50.152268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1462 02:38:50.157871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1463 02:38:50.169005 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1464 02:38:50.180196 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1465 02:38:50.191438 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1466 02:38:50.196999 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1467 02:38:50.202867 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1468 02:38:50.208236 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1469 02:38:50.213869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1470 02:38:50.219520 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1471 02:38:50.224985 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1472 02:38:50.236231 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1473 02:38:50.241939 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1474 02:38:50.252945 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1475 02:38:50.258653 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1476 02:38:50.269773 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1477 02:38:50.275472 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1478 02:38:50.286668 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1479 02:38:50.292214 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1480 02:38:50.297850 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1481 02:38:50.309772 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1482 02:38:50.314670 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1483 02:38:50.325947 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1484 02:38:50.331414 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1485 02:38:50.342672 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1486 02:38:50.348199 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1487 02:38:50.359446 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1488 02:38:50.364886 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1489 02:38:50.376112 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1490 02:38:50.381678 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1491 02:38:50.392833 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1492 02:38:50.398465 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1493 02:38:50.404054 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1494 02:38:50.415335 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1495 02:38:50.421086 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1496 02:38:50.432023 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1497 02:38:50.437688 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1498 02:38:50.448824 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1499 02:38:50.454462 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1500 02:38:50.465692 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1501 02:38:50.476773 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1502 02:38:50.487933 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1503 02:38:50.499171 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1504 02:38:50.510356 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1505 02:38:50.521763 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1506 02:38:50.532855 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1507 02:38:50.544218 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1508 02:38:50.549659 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1509 02:38:50.560739 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1510 02:38:50.566322 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1511 02:38:50.577669 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1512 02:38:50.583168 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1513 02:38:50.594413 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1514 02:38:50.599949 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1515 02:38:50.611173 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1516 02:38:50.616719 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1517 02:38:50.627908 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1518 02:38:50.633654 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1519 02:38:50.644728 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1520 02:38:50.650323 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1521 02:38:50.655888 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1522 02:38:50.667108 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1523 02:38:50.672649 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1524 02:38:50.683888 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1525 02:38:50.689590 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1526 02:38:50.700656 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1527 02:38:50.706299 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1528 02:38:50.717507 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1529 02:38:50.723110 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1530 02:38:50.734259 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1531 02:38:50.739818 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1532 02:38:50.745477 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1533 02:38:50.751017 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1534 02:38:50.762238 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1535 02:38:50.767823 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1536 02:38:50.779114 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1537 02:38:50.784682 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1538 02:38:50.795826 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1539 02:38:50.807004 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1540 02:38:50.818192 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1541 02:38:50.823816 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1542 02:38:50.834975 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1543 02:38:50.840673 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1544 02:38:50.846287 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1545 02:38:50.851801 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1546 02:38:50.857553 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1547 02:38:50.863082 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1548 02:38:50.874234 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1549 02:38:50.879838 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1550 02:38:50.885452 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1551 02:38:50.891055 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1552 02:38:50.896652 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1553 02:38:50.902361 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1554 02:38:50.907961 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1555 02:38:50.919135 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1556 02:38:50.924801 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1557 02:38:50.925138 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1558 02:38:50.935936 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1559 02:38:50.936297 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1560 02:38:50.947164 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1561 02:38:50.947524 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1562 02:38:50.958369 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1563 02:38:50.958733 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1564 02:38:50.969695 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1565 02:38:50.970106 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1566 02:38:50.980779 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1567 02:38:50.981158 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1568 02:38:50.986382 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1569 02:38:50.997655 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1570 02:38:50.998033 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1571 02:38:51.008804 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1572 02:38:51.009167 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1573 02:38:51.019972 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1574 02:38:51.020338 dt_test_unprobed_devices_sh_opp-table skip
1575 02:38:51.025689 dt_test_unprobed_devices_sh_soc skip
1576 02:38:51.026080 dt_test_unprobed_devices_sh_sound pass
1577 02:38:51.031217 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1578 02:38:51.042401 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1579 02:38:51.048140 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1580 02:38:51.048498 dt_test_unprobed_devices_sh fail
1581 02:38:51.053734 + ../../utils/send-to-lava.sh ./output/result.txt
1582 02:38:51.060437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1583 02:38:51.061454 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1585 02:38:51.071164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1586 02:38:51.071999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1588 02:38:51.169052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1589 02:38:51.169969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1591 02:38:51.264626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1592 02:38:51.265987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1594 02:38:51.359353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1595 02:38:51.360407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1597 02:38:51.459590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1598 02:38:51.460567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1600 02:38:51.567752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1601 02:38:51.568708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1603 02:38:51.662553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1604 02:38:51.663467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1606 02:38:51.755106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1607 02:38:51.756016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1609 02:38:51.852491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1610 02:38:51.853432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1612 02:38:51.947879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1613 02:38:51.948803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1615 02:38:52.040346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1616 02:38:52.041280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1618 02:38:52.136935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1619 02:38:52.138031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1621 02:38:52.234734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1622 02:38:52.235668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1624 02:38:52.328873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1625 02:38:52.329758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1627 02:38:52.428434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1628 02:38:52.429084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1630 02:38:52.525589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1631 02:38:52.526555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1633 02:38:52.622456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1634 02:38:52.623393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1636 02:38:52.719268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1637 02:38:52.720218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1639 02:38:52.815999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1640 02:38:52.816911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1642 02:38:52.910956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1643 02:38:52.911877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1645 02:38:53.004173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1646 02:38:53.005077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1648 02:38:53.101270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1649 02:38:53.102247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1651 02:38:53.199354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1652 02:38:53.200335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1654 02:38:53.580267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1655 02:38:53.580707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1656 02:38:53.580927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1657 02:38:53.581374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1659 02:38:53.582311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1661 02:38:53.582970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1663 02:38:53.587898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1664 02:38:53.588598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1666 02:38:53.684299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1667 02:38:53.685114 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1669 02:38:53.783360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1670 02:38:53.785070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1672 02:38:53.875851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1673 02:38:53.876478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1675 02:38:53.973362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1676 02:38:53.974012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1678 02:38:54.069751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1679 02:38:54.070434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1681 02:38:54.163841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1682 02:38:54.164792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1684 02:38:54.260861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1685 02:38:54.261514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1687 02:38:54.357858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1688 02:38:54.358980 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1690 02:38:54.454505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1691 02:38:54.455424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1693 02:38:54.552178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1694 02:38:54.553087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1696 02:38:54.647659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1697 02:38:54.648558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1699 02:38:54.742008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1700 02:38:54.742899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1702 02:38:54.832707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1703 02:38:54.833711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1705 02:38:54.927903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1706 02:38:54.928941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1708 02:38:55.026656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1709 02:38:55.027311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1711 02:38:55.127549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1712 02:38:55.129935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1714 02:38:55.224269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1715 02:38:55.225244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1717 02:38:55.317316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1718 02:38:55.318380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1720 02:38:55.412107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1721 02:38:55.413071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1723 02:38:55.502520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1724 02:38:55.503496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1726 02:38:55.597726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1727 02:38:55.598722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1729 02:38:55.692807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1730 02:38:55.693737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1732 02:38:55.787309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1733 02:38:55.788280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1735 02:38:55.884479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1736 02:38:55.885453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1738 02:38:55.980834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1739 02:38:55.981777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1741 02:38:56.078192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1742 02:38:56.079116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1744 02:38:56.172947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1745 02:38:56.173903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1747 02:38:56.274158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1748 02:38:56.275096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1750 02:38:56.372444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1751 02:38:56.373404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1753 02:38:56.467939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1754 02:38:56.468600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1756 02:38:56.563882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1757 02:38:56.564515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1759 02:38:56.659765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1760 02:38:56.660694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1762 02:38:56.754916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1763 02:38:56.755779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1765 02:38:56.853244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1766 02:38:56.854219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1768 02:38:56.975697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1769 02:38:56.976596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1771 02:38:57.076254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1772 02:38:57.077479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1774 02:38:57.172105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1775 02:38:57.173229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1777 02:38:57.266841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1778 02:38:57.267952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1780 02:38:57.363581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1781 02:38:57.364726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1783 02:38:57.459920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1784 02:38:57.460851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1786 02:38:57.555358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1787 02:38:57.556237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1789 02:38:57.651853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1790 02:38:57.652724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1792 02:38:57.748008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1793 02:38:57.749159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1795 02:38:57.843097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1796 02:38:57.844251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1798 02:38:57.933907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1799 02:38:57.935074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1801 02:38:58.032612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1802 02:38:58.033500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1804 02:38:58.127064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1805 02:38:58.127909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1807 02:38:58.221616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1808 02:38:58.222490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1810 02:38:58.316567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1811 02:38:58.317417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1813 02:38:58.418876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1814 02:38:58.419755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1816 02:38:58.513851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1817 02:38:58.514750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1819 02:38:58.611356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1820 02:38:58.612215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1822 02:38:58.705623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1823 02:38:58.706626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1825 02:38:58.803204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1826 02:38:58.804091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1828 02:38:58.898109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1829 02:38:58.898958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1831 02:38:58.996003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1832 02:38:58.996831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1834 02:38:59.090959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1835 02:38:59.091829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1837 02:38:59.189498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1838 02:38:59.190404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1840 02:38:59.284069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1841 02:38:59.284919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1843 02:38:59.380469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1844 02:38:59.381563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1846 02:38:59.475824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1847 02:38:59.477041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1849 02:38:59.572363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1850 02:38:59.573117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1852 02:38:59.670908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1853 02:38:59.672095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1855 02:38:59.764644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1856 02:38:59.765674 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1858 02:38:59.862593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1859 02:38:59.863494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1861 02:38:59.958367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1862 02:38:59.959241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1864 02:39:00.053877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1865 02:39:00.054760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1867 02:39:00.148959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1868 02:39:00.149834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1870 02:39:00.247769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1871 02:39:00.248644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1873 02:39:00.343481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1874 02:39:00.344353 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1876 02:39:00.438918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1877 02:39:00.439797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1879 02:39:00.534960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1880 02:39:00.536328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1882 02:39:00.630899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1883 02:39:00.631534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1885 02:39:00.726750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1886 02:39:00.727387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1888 02:39:00.820903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1889 02:39:00.821582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1891 02:39:00.916436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1892 02:39:00.917072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1894 02:39:01.011820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1895 02:39:01.012436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1897 02:39:01.109324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1898 02:39:01.110007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1900 02:39:01.205526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1901 02:39:01.206381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1903 02:39:01.300825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1904 02:39:01.301473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1906 02:39:01.398357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1907 02:39:01.399007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1909 02:39:01.494315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1910 02:39:01.495248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1912 02:39:01.591793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1913 02:39:01.593177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1915 02:39:01.691596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1916 02:39:01.693053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1918 02:39:01.791282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1919 02:39:01.792647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1921 02:39:01.886063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1922 02:39:01.886973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1924 02:39:01.981305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1925 02:39:01.982304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1927 02:39:02.077026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1928 02:39:02.077985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1930 02:39:02.176223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1931 02:39:02.177209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1933 02:39:02.274042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1934 02:39:02.275014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1936 02:39:02.370126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1937 02:39:02.371038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1939 02:39:02.464940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1940 02:39:02.465588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1942 02:39:02.559713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1944 02:39:02.562804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1945 02:39:02.657727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1947 02:39:02.660793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1948 02:39:02.756092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1950 02:39:02.758531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1951 02:39:02.854872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1952 02:39:02.855499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1954 02:39:02.952241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1955 02:39:02.952886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1957 02:39:03.044368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1958 02:39:03.045014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1960 02:39:03.141398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1961 02:39:03.142078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1963 02:39:03.238145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1964 02:39:03.238785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1966 02:39:03.333772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1967 02:39:03.334443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1969 02:39:03.428215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1970 02:39:03.428827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1972 02:39:03.524706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1973 02:39:03.525350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1975 02:39:03.620267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1976 02:39:03.620904 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1978 02:39:03.715974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1979 02:39:03.716611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1981 02:39:03.810901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1982 02:39:03.811887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1984 02:39:03.909762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1985 02:39:03.910620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1987 02:39:04.001690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1988 02:39:04.002953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1990 02:39:04.097773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1991 02:39:04.098672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1993 02:39:04.200417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1994 02:39:04.201274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1996 02:39:04.301096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1997 02:39:04.301928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
1999 02:39:04.394070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2000 02:39:04.394908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2002 02:39:04.495449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2003 02:39:04.496311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2005 02:39:04.596320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2006 02:39:04.597151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2008 02:39:04.698128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2009 02:39:04.699005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2011 02:39:04.799023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2012 02:39:04.799880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2014 02:39:04.896523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2015 02:39:04.897375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2017 02:39:04.991927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2018 02:39:04.992791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2020 02:39:05.087955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2021 02:39:05.088823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2023 02:39:05.185304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2024 02:39:05.186237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2026 02:39:05.281857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2027 02:39:05.282737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2029 02:39:05.378226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2030 02:39:05.379095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2032 02:39:05.472874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2033 02:39:05.473544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2035 02:39:05.572947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2036 02:39:05.573646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2038 02:39:05.688367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2039 02:39:05.689079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2041 02:39:05.795951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2042 02:39:05.796609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2044 02:39:05.897461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2045 02:39:05.898175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2047 02:39:05.998447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2048 02:39:05.999067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2050 02:39:06.100060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2051 02:39:06.100693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2053 02:39:06.200665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2054 02:39:06.201297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2056 02:39:06.302077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2057 02:39:06.302709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2059 02:39:06.402963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2060 02:39:06.403596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2062 02:39:06.506148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2063 02:39:06.507538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2065 02:39:06.606760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2066 02:39:06.607862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2068 02:39:06.708237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2069 02:39:06.708883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2071 02:39:06.809040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2072 02:39:06.809866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2074 02:39:06.909998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2075 02:39:06.910933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2077 02:39:07.011295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2078 02:39:07.012090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2080 02:39:07.112290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2081 02:39:07.113108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2083 02:39:07.212435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2084 02:39:07.213185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2086 02:39:07.314566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2087 02:39:07.315339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2089 02:39:07.412148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2090 02:39:07.413001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2092 02:39:07.510248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2093 02:39:07.511779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2095 02:39:07.607238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2096 02:39:07.607993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2098 02:39:07.703820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2099 02:39:07.704695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2101 02:39:07.798083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2102 02:39:07.798990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2104 02:39:07.894003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2105 02:39:07.894929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2107 02:39:07.985361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2108 02:39:07.985959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2110 02:39:08.082297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2111 02:39:08.083225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2113 02:39:08.178343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2114 02:39:08.179240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2116 02:39:08.276430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2117 02:39:08.277387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2119 02:39:08.373308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2120 02:39:08.374342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2122 02:39:08.468631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2123 02:39:08.469594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2125 02:39:08.564384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2126 02:39:08.565311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2128 02:39:08.667765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2129 02:39:08.668804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2131 02:39:08.764768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2132 02:39:08.765703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2134 02:39:08.861254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2135 02:39:08.862194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2137 02:39:08.957279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2138 02:39:08.958242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2140 02:39:09.050118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2141 02:39:09.051060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2143 02:39:09.150532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2144 02:39:09.151203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2146 02:39:09.248895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2147 02:39:09.249633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2149 02:39:09.345310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2150 02:39:09.345995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2152 02:39:09.445666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2153 02:39:09.446370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2155 02:39:09.552459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2156 02:39:09.553130 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2158 02:39:09.649129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2159 02:39:09.650035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2161 02:39:09.746214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2162 02:39:09.747155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2164 02:39:09.840577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2165 02:39:09.841528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2167 02:39:09.937701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2168 02:39:09.938668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2170 02:39:10.034297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2171 02:39:10.035252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2173 02:39:10.130161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2174 02:39:10.131100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2176 02:39:10.224641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2177 02:39:10.225592 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2179 02:39:10.321600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2180 02:39:10.322611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2182 02:39:10.419233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2183 02:39:10.420164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2185 02:39:10.511772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2186 02:39:10.512697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2188 02:39:10.607911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2189 02:39:10.608808 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2191 02:39:10.703818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2192 02:39:10.704683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2194 02:39:10.799965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2195 02:39:10.800821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2197 02:39:10.893147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2198 02:39:10.894020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2200 02:39:10.990698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2201 02:39:10.991588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2203 02:39:11.087902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2204 02:39:11.088918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2206 02:39:11.190288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2207 02:39:11.190918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2209 02:39:11.282260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2210 02:39:11.283758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2212 02:39:11.377613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2213 02:39:11.378336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2215 02:39:11.468931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2216 02:39:11.469552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2218 02:39:11.566335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2219 02:39:11.566968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2221 02:39:11.666182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2222 02:39:11.666811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2224 02:39:11.763749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2225 02:39:11.764375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2227 02:39:11.859528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2228 02:39:11.860145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2230 02:39:11.956148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2231 02:39:11.956783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2233 02:39:12.067147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2234 02:39:12.068188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2236 02:39:12.150914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2237 02:39:12.151848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2239 02:39:12.496316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2240 02:39:12.497004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2241 02:39:12.497860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2243 02:39:12.499446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2245 02:39:12.500981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2246 02:39:12.501771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2248 02:39:12.529693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2249 02:39:12.530612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2251 02:39:12.624786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2252 02:39:12.625731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2254 02:39:12.719960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2255 02:39:12.720905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2257 02:39:12.818498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2258 02:39:12.819420 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2260 02:39:12.914983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2261 02:39:12.915918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2263 02:39:13.007115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2265 02:39:13.010223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2266 02:39:13.104638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2267 02:39:13.105592 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2269 02:39:13.201742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2270 02:39:13.202727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2272 02:39:13.330995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2273 02:39:13.332165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2275 02:39:13.432380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2276 02:39:13.433471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2278 02:39:13.551142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2279 02:39:13.551969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2281 02:39:13.650497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2282 02:39:13.652785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2284 02:39:13.745183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2285 02:39:13.745854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2287 02:39:13.840751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2288 02:39:13.841681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2290 02:39:13.937411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2291 02:39:13.938335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2293 02:39:14.031665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2294 02:39:14.032616 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2296 02:39:14.130094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2297 02:39:14.130987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2299 02:39:14.227458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2300 02:39:14.228390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2302 02:39:14.322391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2303 02:39:14.323263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2305 02:39:14.416437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2306 02:39:14.417380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2308 02:39:14.507473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2309 02:39:14.508151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2311 02:39:14.602123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2312 02:39:14.603068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2314 02:39:14.698045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2315 02:39:14.698929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2317 02:39:14.793332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2318 02:39:14.794288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2320 02:39:14.887427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2321 02:39:14.888518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2323 02:39:14.983206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2324 02:39:14.984287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2326 02:39:15.080439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2327 02:39:15.081078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2329 02:39:15.176919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2330 02:39:15.177883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2332 02:39:15.271588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2333 02:39:15.272521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2335 02:39:15.369708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2336 02:39:15.370739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2338 02:39:15.464175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2339 02:39:15.465109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2341 02:39:15.557081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2342 02:39:15.558077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2344 02:39:15.653040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2345 02:39:15.654017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2347 02:39:15.750657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2348 02:39:15.751542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2350 02:39:15.848177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2351 02:39:15.849096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2353 02:39:15.942418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2354 02:39:15.943343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2356 02:39:16.038935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2357 02:39:16.039658 + set +x
2358 02:39:16.040413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2360 02:39:16.042933 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 964144_1.6.2.4.5>
2361 02:39:16.043740 Received signal: <ENDRUN> 1_kselftest-dt 964144_1.6.2.4.5
2362 02:39:16.044359 Ending use of test pattern.
2363 02:39:16.044884 Ending test lava.1_kselftest-dt (964144_1.6.2.4.5), duration 86.29
2365 02:39:16.050839 <LAVA_TEST_RUNNER EXIT>
2366 02:39:16.051737 ok: lava_test_shell seems to have completed
2367 02:39:16.066304 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2368 02:39:16.068526 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2369 02:39:16.069203 end: 3 lava-test-retry (duration 00:01:28) [common]
2370 02:39:16.069870 start: 4 finalize (timeout 00:05:23) [common]
2371 02:39:16.070525 start: 4.1 power-off (timeout 00:00:30) [common]
2372 02:39:16.071617 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2373 02:39:16.112854 >> OK - accepted request
2374 02:39:16.114874 Returned 0 in 0 seconds
2375 02:39:16.216116 end: 4.1 power-off (duration 00:00:00) [common]
2377 02:39:16.218080 start: 4.2 read-feedback (timeout 00:05:23) [common]
2378 02:39:16.219401 Listened to connection for namespace 'common' for up to 1s
2379 02:39:16.220388 Listened to connection for namespace 'common' for up to 1s
2380 02:39:17.220156 Finalising connection for namespace 'common'
2381 02:39:17.220980 Disconnecting from shell: Finalise
2382 02:39:17.221568 / #
2383 02:39:17.322841 end: 4.2 read-feedback (duration 00:00:01) [common]
2384 02:39:17.323686 end: 4 finalize (duration 00:00:01) [common]
2385 02:39:17.324392 Cleaning after the job
2386 02:39:17.325055 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964144/tftp-deploy-t63sa4n0/ramdisk
2387 02:39:17.329140 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964144/tftp-deploy-t63sa4n0/kernel
2388 02:39:17.335634 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964144/tftp-deploy-t63sa4n0/dtb
2389 02:39:17.337005 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964144/tftp-deploy-t63sa4n0/nfsrootfs
2390 02:39:17.451993 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/964144/tftp-deploy-t63sa4n0/modules
2391 02:39:17.460022 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/964144
2392 02:39:20.283015 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/964144
2393 02:39:20.283569 Job finished correctly